1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation,
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
32 /* From ppc-linux-tdep.c... */
33 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
35 struct regcache *regcache,
37 const gdb_byte *writebuf);
38 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
40 struct regcache *regcache,
42 const gdb_byte *writebuf);
43 CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
44 struct value *function,
45 struct regcache *regcache,
46 CORE_ADDR bp_addr, int nargs,
47 struct value **args, CORE_ADDR sp,
49 CORE_ADDR struct_addr);
50 CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
51 struct value *function,
52 struct regcache *regcache,
53 CORE_ADDR bp_addr, int nargs,
54 struct value **args, CORE_ADDR sp,
56 CORE_ADDR struct_addr);
57 CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
59 int ppc_linux_memory_remove_breakpoint (CORE_ADDR addr,
60 gdb_byte *contents_cache);
61 struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
62 void ppc_linux_supply_gregset (struct regcache *regcache,
63 int regnum, const void *gregs, size_t size,
65 void ppc_linux_supply_fpregset (const struct regset *regset,
66 struct regcache *regcache,
67 int regnum, const void *gregs, size_t size);
69 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
71 struct regcache *regcache,
73 const gdb_byte *writebuf);
75 /* From rs6000-tdep.c... */
76 int altivec_register_p (int regno);
77 int spe_register_p (int regno);
79 /* Return non-zero if the architecture described by GDBARCH has
80 floating-point registers (f0 --- f31 and fpscr). */
81 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
83 /* Register set description. */
85 struct ppc_reg_offsets
87 /* General-purpose registers. */
97 /* Floating-point registers. */
101 /* AltiVec registers. */
107 /* Supply register REGNUM in the general-purpose register set REGSET
108 from the buffer specified by GREGS and LEN to register cache
109 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
111 extern void ppc_supply_gregset (const struct regset *regset,
112 struct regcache *regcache,
113 int regnum, const void *gregs, size_t len);
115 /* Supply register REGNUM in the floating-point register set REGSET
116 from the buffer specified by FPREGS and LEN to register cache
117 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
119 extern void ppc_supply_fpregset (const struct regset *regset,
120 struct regcache *regcache,
121 int regnum, const void *fpregs, size_t len);
123 /* Collect register REGNUM in the general-purpose register set
124 REGSET. from register cache REGCACHE into the buffer specified by
125 GREGS and LEN. If REGNUM is -1, do this for all registers in
128 extern void ppc_collect_gregset (const struct regset *regset,
129 const struct regcache *regcache,
130 int regnum, void *gregs, size_t len);
132 /* Collect register REGNUM in the floating-point register set
133 REGSET. from register cache REGCACHE into the buffer specified by
134 FPREGS and LEN. If REGNUM is -1, do this for all registers in
137 extern void ppc_collect_fpregset (const struct regset *regset,
138 const struct regcache *regcache,
139 int regnum, void *fpregs, size_t len);
141 /* Private data that this module attaches to struct gdbarch. */
145 int wordsize; /* size in bytes of fixed-point word */
146 const struct reg *regs; /* from current variant */
147 int ppc_gp0_regnum; /* GPR register 0 */
148 int ppc_toc_regnum; /* TOC register */
149 int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
150 int ppc_cr_regnum; /* Condition register */
151 int ppc_lr_regnum; /* Link register */
152 int ppc_ctr_regnum; /* Count register */
153 int ppc_xer_regnum; /* Integer exception register */
155 /* Not all PPC and RS6000 variants will have the registers
156 represented below. A -1 is used to indicate that the register
157 is not present in this variant. */
159 /* Floating-point registers. */
160 int ppc_fp0_regnum; /* floating-point register 0 */
161 int ppc_fpscr_regnum; /* fp status and condition register */
163 /* Segment registers. */
164 int ppc_sr0_regnum; /* segment register 0 */
166 /* Multiplier-Quotient Register (older POWER architectures only). */
169 /* Altivec registers. */
170 int ppc_vr0_regnum; /* First AltiVec register */
171 int ppc_vrsave_regnum; /* Last AltiVec register */
174 int ppc_ev0_upper_regnum; /* First GPR upper half register */
175 int ppc_ev0_regnum; /* First ev register */
176 int ppc_ev31_regnum; /* Last ev register */
177 int ppc_acc_regnum; /* SPE 'acc' register */
178 int ppc_spefscr_regnum; /* SPE 'spefscr' register */
180 /* Offset to ABI specific location where link register is saved. */
183 /* An array of integers, such that sim_regno[I] is the simulator
184 register number for GDB register number I, or -1 if the
185 simulator does not implement that register. */
190 /* Constants for register set sizes. */
193 ppc_num_gprs = 32, /* 32 general-purpose registers */
194 ppc_num_fprs = 32, /* 32 floating-point registers */
195 ppc_num_srs = 16, /* 16 segment registers */
196 ppc_num_vrs = 32 /* 32 Altivec vector registers */
200 /* Constants for SPR register numbers. These are *not* GDB register
201 numbers: they are the numbers used in the PowerPC ISA itself to
202 refer to these registers.
204 This table includes all the SPRs from all the variants I could find
207 There may be registers from different PowerPC variants assigned the
208 same number, but that's fine: GDB and the SIM always use the
209 numbers in the context of a particular variant, so it's not
212 We need to deviate from the naming pattern when variants have
213 special-purpose registers of the same name, but with different
214 numbers. Fortunately, this is rare: look below to see how we
215 handle the 'tcr' registers on the 403/403GX and 602. */
242 ppc_spr_counta = 150,
243 ppc_spr_countb = 151,
248 ppc_spr_lctrl1 = 156,
249 ppc_spr_lctrl2 = 157,
252 ppc_spr_vrsave = 256,
262 ppc_spr_spefscr = 512,
263 ppc_spr_ibat0u = 528,
264 ppc_spr_ibat0l = 529,
265 ppc_spr_ibat1u = 530,
266 ppc_spr_ibat1l = 531,
267 ppc_spr_ibat2u = 532,
268 ppc_spr_ibat2l = 533,
269 ppc_spr_ibat3u = 534,
270 ppc_spr_ibat3l = 535,
271 ppc_spr_dbat0u = 536,
272 ppc_spr_dbat0l = 537,
273 ppc_spr_dbat1u = 538,
274 ppc_spr_dbat1l = 539,
275 ppc_spr_dbat2u = 540,
276 ppc_spr_dbat2l = 541,
277 ppc_spr_dbat3u = 542,
278 ppc_spr_dbat3l = 543,
279 ppc_spr_ic_cst = 560,
280 ppc_spr_ic_adr = 561,
281 ppc_spr_ic_dat = 562,
282 ppc_spr_dc_cst = 568,
283 ppc_spr_dc_adr = 569,
284 ppc_spr_dc_dat = 570,
288 ppc_spr_mi_ctr = 784,
290 ppc_spr_mi_epn = 787,
291 ppc_spr_mi_twc = 789,
292 ppc_spr_mi_rpn = 790,
293 ppc_spr_mi_cam = 816,
294 ppc_spr_mi_ram0 = 817,
295 ppc_spr_mi_ram1 = 818,
296 ppc_spr_md_ctr = 792,
297 ppc_spr_m_casid = 793,
299 ppc_spr_md_epn = 795,
301 ppc_spr_md_twc = 797,
302 ppc_spr_md_rpn = 798,
304 ppc_spr_mi_dbcam = 816,
305 ppc_spr_mi_dbram0 = 817,
306 ppc_spr_mi_dbram1 = 818,
307 ppc_spr_md_dbcam = 824,
308 ppc_spr_md_cam = 824,
309 ppc_spr_md_dbram0 = 825,
310 ppc_spr_md_ram0 = 825,
311 ppc_spr_md_dbram1 = 826,
312 ppc_spr_md_ram1 = 826,
313 ppc_spr_ummcr0 = 936,
317 ppc_spr_ummcr1 = 940,
338 ppc_spr_icdbdr = 979,
347 ppc_spr_602_tcr = 984,
348 ppc_spr_403_tcr = 986,
351 ppc_spr_esasrr = 988,
372 ppc_spr_thrm1 = 1020,
374 ppc_spr_thrm2 = 1021,
376 ppc_spr_thrm3 = 1022,
378 ppc_spr_fpecr = 1022,