1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,
4 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb_string.h"
27 #include "gdbthread.h"
30 #include "gdb_assert.h"
32 #include "linux-nat.h"
35 #include <sys/types.h>
36 #include <sys/param.h>
39 #include <sys/ioctl.h>
42 #include <sys/procfs.h>
43 #include <sys/ptrace.h>
45 /* Prototypes for supply_gregset etc. */
48 #include "ppc-linux-tdep.h"
50 /* Required when using the AUXV. */
51 #include "elf/common.h"
54 /* This sometimes isn't defined. */
62 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
63 If they aren't, we can provide them ourselves (their values are fixed
64 because they are part of the kernel ABI). They are used in the AT_HWCAP
66 #ifndef PPC_FEATURE_CELL
67 #define PPC_FEATURE_CELL 0x00010000
69 #ifndef PPC_FEATURE_BOOKE
70 #define PPC_FEATURE_BOOKE 0x00008000
72 #ifndef PPC_FEATURE_HAS_DFP
73 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
76 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
77 configure time check. Some older glibc's (for instance 2.2.1)
78 don't have a specific powerpc version of ptrace.h, and fall back on
79 a generic one. In such cases, sys/ptrace.h defines
80 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
81 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
82 PTRACE_SETVRREGS to be. This also makes a configury check pretty
85 /* These definitions should really come from the glibc header files,
86 but Glibc doesn't know about the vrregs yet. */
87 #ifndef PTRACE_GETVRREGS
88 #define PTRACE_GETVRREGS 18
89 #define PTRACE_SETVRREGS 19
92 /* PTRACE requests for POWER7 VSX registers. */
93 #ifndef PTRACE_GETVSXREGS
94 #define PTRACE_GETVSXREGS 27
95 #define PTRACE_SETVSXREGS 28
98 /* Similarly for the ptrace requests for getting / setting the SPE
99 registers (ev0 -- ev31, acc, and spefscr). See the description of
100 gdb_evrregset_t for details. */
101 #ifndef PTRACE_GETEVRREGS
102 #define PTRACE_GETEVRREGS 20
103 #define PTRACE_SETEVRREGS 21
106 /* Similarly for the hardware watchpoint support. These requests are used
107 when the BookE kernel interface is not available. */
108 #ifndef PTRACE_GET_DEBUGREG
109 #define PTRACE_GET_DEBUGREG 25
111 #ifndef PTRACE_SET_DEBUGREG
112 #define PTRACE_SET_DEBUGREG 26
114 #ifndef PTRACE_GETSIGINFO
115 #define PTRACE_GETSIGINFO 0x4202
118 /* These requests are used when the BookE kernel interface is available.
119 It exposes the additional debug features of BookE processors, such as
120 ranged breakpoints and watchpoints and hardware-accelerated condition
122 #ifndef PPC_PTRACE_GETHWDBGINFO
124 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the new BookE
125 interface is not present in ptrace.h, so we'll have to pretty much include
126 it all here so that the code at least compiles on older systems. */
127 #define PPC_PTRACE_GETHWDBGINFO 0x89
128 #define PPC_PTRACE_SETHWDEBUG 0x88
129 #define PPC_PTRACE_DELHWDEBUG 0x87
131 struct ppc_debug_info
133 uint32_t version; /* Only version 1 exists to date. */
134 uint32_t num_instruction_bps;
135 uint32_t num_data_bps;
136 uint32_t num_condition_regs;
137 uint32_t data_bp_alignment;
138 uint32_t sizeof_condition; /* size of the DVC register. */
142 /* Features will have bits indicating whether there is support for: */
143 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
144 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
145 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
146 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
148 struct ppc_hw_breakpoint
150 uint32_t version; /* currently, version must be 1 */
151 uint32_t trigger_type; /* only some combinations allowed */
152 uint32_t addr_mode; /* address match mode */
153 uint32_t condition_mode; /* break/watchpoint condition flags */
154 uint64_t addr; /* break/watchpoint address */
155 uint64_t addr2; /* range end or mask */
156 uint64_t condition_value; /* contents of the DVC register */
160 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
161 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
162 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
163 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
166 #define PPC_BREAKPOINT_MODE_EXACT 0x0
167 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
168 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
169 #define PPC_BREAKPOINT_MODE_MASK 0x3
171 /* Condition mode. */
172 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
173 #define PPC_BREAKPOINT_CONDITION_AND 0x1
174 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
175 #define PPC_BREAKPOINT_CONDITION_OR 0x2
176 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
177 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
178 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
179 #define PPC_BREAKPOINT_CONDITION_BE(n) \
180 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
181 #endif /* PPC_PTRACE_GETHWDBGINFO */
185 /* Similarly for the general-purpose (gp0 -- gp31)
186 and floating-point registers (fp0 -- fp31). */
187 #ifndef PTRACE_GETREGS
188 #define PTRACE_GETREGS 12
190 #ifndef PTRACE_SETREGS
191 #define PTRACE_SETREGS 13
193 #ifndef PTRACE_GETFPREGS
194 #define PTRACE_GETFPREGS 14
196 #ifndef PTRACE_SETFPREGS
197 #define PTRACE_SETFPREGS 15
200 /* This oddity is because the Linux kernel defines elf_vrregset_t as
201 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
202 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
203 the vrsave as an extra 4 bytes at the end. I opted for creating a
204 flat array of chars, so that it is easier to manipulate for gdb.
206 There are 32 vector registers 16 bytes longs, plus a VSCR register
207 which is only 4 bytes long, but is fetched as a 16 bytes
208 quantity. Up to here we have the elf_vrregset_t structure.
209 Appended to this there is space for the VRSAVE register: 4 bytes.
210 Even though this vrsave register is not included in the regset
211 typedef, it is handled by the ptrace requests.
213 Note that GNU/Linux doesn't support little endian PPC hardware,
214 therefore the offset at which the real value of the VSCR register
215 is located will be always 12 bytes.
217 The layout is like this (where x is the actual value of the vscr reg): */
221 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
222 <-------> <-------><-------><->
227 #define SIZEOF_VRREGS 33*16+4
229 typedef char gdb_vrregset_t[SIZEOF_VRREGS];
231 /* This is the layout of the POWER7 VSX registers and the way they overlap
232 with the existing FPR and VMX registers.
234 VSR doubleword 0 VSR doubleword 1
235 ----------------------------------------------------------------
237 ----------------------------------------------------------------
239 ----------------------------------------------------------------
242 ----------------------------------------------------------------
243 VSR[30] | FPR[30] | |
244 ----------------------------------------------------------------
245 VSR[31] | FPR[31] | |
246 ----------------------------------------------------------------
248 ----------------------------------------------------------------
250 ----------------------------------------------------------------
253 ----------------------------------------------------------------
255 ----------------------------------------------------------------
257 ----------------------------------------------------------------
259 VSX has 64 128bit registers. The first 32 registers overlap with
260 the FP registers (doubleword 0) and hence extend them with additional
261 64 bits (doubleword 1). The other 32 regs overlap with the VMX
263 #define SIZEOF_VSXREGS 32*8
265 typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
267 /* On PPC processors that support the Signal Processing Extension
268 (SPE) APU, the general-purpose registers are 64 bits long.
269 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
270 ptrace calls only access the lower half of each register, to allow
271 them to behave the same way they do on non-SPE systems. There's a
272 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
273 read and write the top halves of all the general-purpose registers
274 at once, along with some SPE-specific registers.
276 GDB itself continues to claim the general-purpose registers are 32
277 bits long. It has unnamed raw registers that hold the upper halves
278 of the gprs, and the full 64-bit SIMD views of the registers,
279 'ev0' -- 'ev31', are pseudo-registers that splice the top and
280 bottom halves together.
282 This is the structure filled in by PTRACE_GETEVRREGS and written to
283 the inferior's registers by PTRACE_SETEVRREGS. */
284 struct gdb_evrregset_t
286 unsigned long evr[32];
287 unsigned long long acc;
288 unsigned long spefscr;
291 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
292 PTRACE_SETVSXREGS requests, for reading and writing the VSX
293 POWER7 registers 0 through 31. Zero if we've tried one of them and
294 gotten an error. Note that VSX registers 32 through 63 overlap
295 with VR registers 0 through 31. */
296 int have_ptrace_getsetvsxregs = 1;
298 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
299 PTRACE_SETVRREGS requests, for reading and writing the Altivec
300 registers. Zero if we've tried one of them and gotten an
302 int have_ptrace_getvrregs = 1;
304 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
305 PTRACE_SETEVRREGS requests, for reading and writing the SPE
306 registers. Zero if we've tried one of them and gotten an
308 int have_ptrace_getsetevrregs = 1;
310 /* Non-zero if our kernel may support the PTRACE_GETREGS and
311 PTRACE_SETREGS requests, for reading and writing the
312 general-purpose registers. Zero if we've tried one of
313 them and gotten an error. */
314 int have_ptrace_getsetregs = 1;
316 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
317 PTRACE_SETFPREGS requests, for reading and writing the
318 floating-pointers registers. Zero if we've tried one of
319 them and gotten an error. */
320 int have_ptrace_getsetfpregs = 1;
323 /* registers layout, as presented by the ptrace interface:
324 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
325 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
326 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
327 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
328 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
329 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
330 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
331 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
332 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
333 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
334 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
335 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
336 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
340 ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
343 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
344 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
345 interface, and not the wordsize of the program's ABI. */
346 int wordsize = sizeof (long);
348 /* General purpose registers occupy 1 slot each in the buffer. */
349 if (regno >= tdep->ppc_gp0_regnum
350 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
351 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
353 /* Floating point regs: eight bytes each in both 32- and 64-bit
354 ptrace interfaces. Thus, two slots each in 32-bit interface, one
355 slot each in 64-bit interface. */
356 if (tdep->ppc_fp0_regnum >= 0
357 && regno >= tdep->ppc_fp0_regnum
358 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
359 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
361 /* UISA special purpose registers: 1 slot each. */
362 if (regno == gdbarch_pc_regnum (gdbarch))
363 u_addr = PT_NIP * wordsize;
364 if (regno == tdep->ppc_lr_regnum)
365 u_addr = PT_LNK * wordsize;
366 if (regno == tdep->ppc_cr_regnum)
367 u_addr = PT_CCR * wordsize;
368 if (regno == tdep->ppc_xer_regnum)
369 u_addr = PT_XER * wordsize;
370 if (regno == tdep->ppc_ctr_regnum)
371 u_addr = PT_CTR * wordsize;
373 if (regno == tdep->ppc_mq_regnum)
374 u_addr = PT_MQ * wordsize;
376 if (regno == tdep->ppc_ps_regnum)
377 u_addr = PT_MSR * wordsize;
378 if (regno == PPC_ORIG_R3_REGNUM)
379 u_addr = PT_ORIG_R3 * wordsize;
380 if (regno == PPC_TRAP_REGNUM)
381 u_addr = PT_TRAP * wordsize;
382 if (tdep->ppc_fpscr_regnum >= 0
383 && regno == tdep->ppc_fpscr_regnum)
385 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
386 kernel headers incorrectly contained the 32-bit definition of
387 PT_FPSCR. For the 32-bit definition, floating-point
388 registers occupy two 32-bit "slots", and the FPSCR lives in
389 the second half of such a slot-pair (hence +1). For 64-bit,
390 the FPSCR instead occupies the full 64-bit 2-word-slot and
391 hence no adjustment is necessary. Hack around this. */
392 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
393 u_addr = (48 + 32) * wordsize;
394 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
395 slot and not just its second word. The PT_FPSCR supplied when
396 GDB is compiled as a 32-bit app doesn't reflect this. */
397 else if (wordsize == 4 && register_size (gdbarch, regno) == 8
398 && PT_FPSCR == (48 + 2*32 + 1))
399 u_addr = (48 + 2*32) * wordsize;
401 u_addr = PT_FPSCR * wordsize;
406 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
407 registers set mechanism, as opposed to the interface for all the
408 other registers, that stores/fetches each register individually. */
410 fetch_vsx_register (struct regcache *regcache, int tid, int regno)
413 gdb_vsxregset_t regs;
414 struct gdbarch *gdbarch = get_regcache_arch (regcache);
415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
418 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
423 have_ptrace_getsetvsxregs = 0;
426 perror_with_name (_("Unable to fetch VSX register"));
429 regcache_raw_supply (regcache, regno,
430 regs + (regno - tdep->ppc_vsr0_upper_regnum)
434 /* The Linux kernel ptrace interface for AltiVec registers uses the
435 registers set mechanism, as opposed to the interface for all the
436 other registers, that stores/fetches each register individually. */
438 fetch_altivec_register (struct regcache *regcache, int tid, int regno)
443 struct gdbarch *gdbarch = get_regcache_arch (regcache);
444 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
445 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
447 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
452 have_ptrace_getvrregs = 0;
455 perror_with_name (_("Unable to fetch AltiVec register"));
458 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
459 long on the hardware. We deal only with the lower 4 bytes of the
460 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
461 there is no need to define an offset for it. */
462 if (regno == (tdep->ppc_vrsave_regnum - 1))
463 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
465 regcache_raw_supply (regcache, regno,
467 - tdep->ppc_vr0_regnum) * vrregsize + offset);
470 /* Fetch the top 32 bits of TID's general-purpose registers and the
471 SPE-specific registers, and place the results in EVRREGSET. If we
472 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
475 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
476 PTRACE_SETEVRREGS requests are supported is isolated here, and in
477 set_spe_registers. */
479 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
481 if (have_ptrace_getsetevrregs)
483 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
487 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
488 we just return zeros. */
490 have_ptrace_getsetevrregs = 0;
492 /* Anything else needs to be reported. */
493 perror_with_name (_("Unable to fetch SPE registers"));
497 memset (evrregset, 0, sizeof (*evrregset));
500 /* Supply values from TID for SPE-specific raw registers: the upper
501 halves of the GPRs, the accumulator, and the spefscr. REGNO must
502 be the number of an upper half register, acc, spefscr, or -1 to
503 supply the values of all registers. */
505 fetch_spe_register (struct regcache *regcache, int tid, int regno)
507 struct gdbarch *gdbarch = get_regcache_arch (regcache);
508 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
509 struct gdb_evrregset_t evrregs;
511 gdb_assert (sizeof (evrregs.evr[0])
512 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
513 gdb_assert (sizeof (evrregs.acc)
514 == register_size (gdbarch, tdep->ppc_acc_regnum));
515 gdb_assert (sizeof (evrregs.spefscr)
516 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
518 get_spe_registers (tid, &evrregs);
524 for (i = 0; i < ppc_num_gprs; i++)
525 regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
528 else if (tdep->ppc_ev0_upper_regnum <= regno
529 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
530 regcache_raw_supply (regcache, regno,
531 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
534 || regno == tdep->ppc_acc_regnum)
535 regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
538 || regno == tdep->ppc_spefscr_regnum)
539 regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
544 fetch_register (struct regcache *regcache, int tid, int regno)
546 struct gdbarch *gdbarch = get_regcache_arch (regcache);
547 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
548 /* This isn't really an address. But ptrace thinks of it as one. */
549 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
550 int bytes_transferred;
551 unsigned int offset; /* Offset of registers within the u area. */
552 char buf[MAX_REGISTER_SIZE];
554 if (altivec_register_p (gdbarch, regno))
556 /* If this is the first time through, or if it is not the first
557 time through, and we have comfirmed that there is kernel
558 support for such a ptrace request, then go and fetch the
560 if (have_ptrace_getvrregs)
562 fetch_altivec_register (regcache, tid, regno);
565 /* If we have discovered that there is no ptrace support for
566 AltiVec registers, fall through and return zeroes, because
567 regaddr will be -1 in this case. */
569 if (vsx_register_p (gdbarch, regno))
571 if (have_ptrace_getsetvsxregs)
573 fetch_vsx_register (regcache, tid, regno);
577 else if (spe_register_p (gdbarch, regno))
579 fetch_spe_register (regcache, tid, regno);
585 memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
586 regcache_raw_supply (regcache, regno, buf);
590 /* Read the raw register using sizeof(long) sized chunks. On a
591 32-bit platform, 64-bit floating-point registers will require two
593 for (bytes_transferred = 0;
594 bytes_transferred < register_size (gdbarch, regno);
595 bytes_transferred += sizeof (long))
598 *(long *) &buf[bytes_transferred]
599 = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
600 regaddr += sizeof (long);
604 sprintf (message, "reading register %s (#%d)",
605 gdbarch_register_name (gdbarch, regno), regno);
606 perror_with_name (message);
610 /* Now supply the register. Keep in mind that the regcache's idea
611 of the register's size may not be a multiple of sizeof
613 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
615 /* Little-endian values are always found at the left end of the
616 bytes transferred. */
617 regcache_raw_supply (regcache, regno, buf);
619 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
621 /* Big-endian values are found at the right end of the bytes
623 size_t padding = (bytes_transferred - register_size (gdbarch, regno));
624 regcache_raw_supply (regcache, regno, buf + padding);
627 internal_error (__FILE__, __LINE__,
628 _("fetch_register: unexpected byte order: %d"),
629 gdbarch_byte_order (gdbarch));
633 supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
636 struct gdbarch *gdbarch = get_regcache_arch (regcache);
637 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
638 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
640 for (i = 0; i < ppc_num_vshrs; i++)
642 regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
643 *vsxregsetp + i * vsxregsize);
648 supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)
651 struct gdbarch *gdbarch = get_regcache_arch (regcache);
652 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
653 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
654 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
655 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
657 for (i = 0; i < num_of_vrregs; i++)
659 /* The last 2 registers of this set are only 32 bit long, not
660 128. However an offset is necessary only for VSCR because it
661 occupies a whole vector, while VRSAVE occupies a full 4 bytes
663 if (i == (num_of_vrregs - 2))
664 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
665 *vrregsetp + i * vrregsize + offset);
667 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
668 *vrregsetp + i * vrregsize);
673 fetch_vsx_registers (struct regcache *regcache, int tid)
676 gdb_vsxregset_t regs;
678 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
683 have_ptrace_getsetvsxregs = 0;
686 perror_with_name (_("Unable to fetch VSX registers"));
688 supply_vsxregset (regcache, ®s);
692 fetch_altivec_registers (struct regcache *regcache, int tid)
697 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
702 have_ptrace_getvrregs = 0;
705 perror_with_name (_("Unable to fetch AltiVec registers"));
707 supply_vrregset (regcache, ®s);
710 /* This function actually issues the request to ptrace, telling
711 it to get all general-purpose registers and put them into the
714 If the ptrace request does not exist, this function returns 0
715 and properly sets the have_ptrace_* flag. If the request fails,
716 this function calls perror_with_name. Otherwise, if the request
717 succeeds, then the regcache gets filled and 1 is returned. */
719 fetch_all_gp_regs (struct regcache *regcache, int tid)
721 struct gdbarch *gdbarch = get_regcache_arch (regcache);
722 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
723 gdb_gregset_t gregset;
725 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
729 have_ptrace_getsetregs = 0;
732 perror_with_name (_("Couldn't get general-purpose registers."));
735 supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
740 /* This is a wrapper for the fetch_all_gp_regs function. It is
741 responsible for verifying if this target has the ptrace request
742 that can be used to fetch all general-purpose registers at one
743 shot. If it doesn't, then we should fetch them using the
744 old-fashioned way, which is to iterate over the registers and
745 request them one by one. */
747 fetch_gp_regs (struct regcache *regcache, int tid)
749 struct gdbarch *gdbarch = get_regcache_arch (regcache);
750 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
753 if (have_ptrace_getsetregs)
754 if (fetch_all_gp_regs (regcache, tid))
757 /* If we've hit this point, it doesn't really matter which
758 architecture we are using. We just need to read the
759 registers in the "old-fashioned way". */
760 for (i = 0; i < ppc_num_gprs; i++)
761 fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
764 /* This function actually issues the request to ptrace, telling
765 it to get all floating-point registers and put them into the
768 If the ptrace request does not exist, this function returns 0
769 and properly sets the have_ptrace_* flag. If the request fails,
770 this function calls perror_with_name. Otherwise, if the request
771 succeeds, then the regcache gets filled and 1 is returned. */
773 fetch_all_fp_regs (struct regcache *regcache, int tid)
775 gdb_fpregset_t fpregs;
777 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
781 have_ptrace_getsetfpregs = 0;
784 perror_with_name (_("Couldn't get floating-point registers."));
787 supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs);
792 /* This is a wrapper for the fetch_all_fp_regs function. It is
793 responsible for verifying if this target has the ptrace request
794 that can be used to fetch all floating-point registers at one
795 shot. If it doesn't, then we should fetch them using the
796 old-fashioned way, which is to iterate over the registers and
797 request them one by one. */
799 fetch_fp_regs (struct regcache *regcache, int tid)
801 struct gdbarch *gdbarch = get_regcache_arch (regcache);
802 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
805 if (have_ptrace_getsetfpregs)
806 if (fetch_all_fp_regs (regcache, tid))
809 /* If we've hit this point, it doesn't really matter which
810 architecture we are using. We just need to read the
811 registers in the "old-fashioned way". */
812 for (i = 0; i < ppc_num_fprs; i++)
813 fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
817 fetch_ppc_registers (struct regcache *regcache, int tid)
820 struct gdbarch *gdbarch = get_regcache_arch (regcache);
821 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
823 fetch_gp_regs (regcache, tid);
824 if (tdep->ppc_fp0_regnum >= 0)
825 fetch_fp_regs (regcache, tid);
826 fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
827 if (tdep->ppc_ps_regnum != -1)
828 fetch_register (regcache, tid, tdep->ppc_ps_regnum);
829 if (tdep->ppc_cr_regnum != -1)
830 fetch_register (regcache, tid, tdep->ppc_cr_regnum);
831 if (tdep->ppc_lr_regnum != -1)
832 fetch_register (regcache, tid, tdep->ppc_lr_regnum);
833 if (tdep->ppc_ctr_regnum != -1)
834 fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
835 if (tdep->ppc_xer_regnum != -1)
836 fetch_register (regcache, tid, tdep->ppc_xer_regnum);
837 if (tdep->ppc_mq_regnum != -1)
838 fetch_register (regcache, tid, tdep->ppc_mq_regnum);
839 if (ppc_linux_trap_reg_p (gdbarch))
841 fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
842 fetch_register (regcache, tid, PPC_TRAP_REGNUM);
844 if (tdep->ppc_fpscr_regnum != -1)
845 fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
846 if (have_ptrace_getvrregs)
847 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
848 fetch_altivec_registers (regcache, tid);
849 if (have_ptrace_getsetvsxregs)
850 if (tdep->ppc_vsr0_upper_regnum != -1)
851 fetch_vsx_registers (regcache, tid);
852 if (tdep->ppc_ev0_upper_regnum >= 0)
853 fetch_spe_register (regcache, tid, -1);
856 /* Fetch registers from the child process. Fetch all registers if
857 regno == -1, otherwise fetch all general registers or all floating
858 point registers depending upon the value of regno. */
860 ppc_linux_fetch_inferior_registers (struct target_ops *ops,
861 struct regcache *regcache, int regno)
863 /* Overload thread id onto process id. */
864 int tid = TIDGET (inferior_ptid);
866 /* No thread id, just use process id. */
868 tid = PIDGET (inferior_ptid);
871 fetch_ppc_registers (regcache, tid);
873 fetch_register (regcache, tid, regno);
876 /* Store one VSX register. */
878 store_vsx_register (const struct regcache *regcache, int tid, int regno)
881 gdb_vsxregset_t regs;
882 struct gdbarch *gdbarch = get_regcache_arch (regcache);
883 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
884 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
886 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
891 have_ptrace_getsetvsxregs = 0;
894 perror_with_name (_("Unable to fetch VSX register"));
897 regcache_raw_collect (regcache, regno, regs +
898 (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
900 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s);
902 perror_with_name (_("Unable to store VSX register"));
905 /* Store one register. */
907 store_altivec_register (const struct regcache *regcache, int tid, int regno)
912 struct gdbarch *gdbarch = get_regcache_arch (regcache);
913 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
914 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
916 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
921 have_ptrace_getvrregs = 0;
924 perror_with_name (_("Unable to fetch AltiVec register"));
927 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
928 long on the hardware. */
929 if (regno == (tdep->ppc_vrsave_regnum - 1))
930 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
932 regcache_raw_collect (regcache, regno,
934 - tdep->ppc_vr0_regnum) * vrregsize + offset);
936 ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s);
938 perror_with_name (_("Unable to store AltiVec register"));
941 /* Assuming TID referrs to an SPE process, set the top halves of TID's
942 general-purpose registers and its SPE-specific registers to the
943 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
946 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
947 PTRACE_SETEVRREGS requests are supported is isolated here, and in
948 get_spe_registers. */
950 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
952 if (have_ptrace_getsetevrregs)
954 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
958 /* EIO means that the PTRACE_SETEVRREGS request isn't
959 supported; we fail silently, and don't try the call
962 have_ptrace_getsetevrregs = 0;
964 /* Anything else needs to be reported. */
965 perror_with_name (_("Unable to set SPE registers"));
970 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
971 If REGNO is -1, write the values of all the SPE-specific
974 store_spe_register (const struct regcache *regcache, int tid, int regno)
976 struct gdbarch *gdbarch = get_regcache_arch (regcache);
977 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
978 struct gdb_evrregset_t evrregs;
980 gdb_assert (sizeof (evrregs.evr[0])
981 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
982 gdb_assert (sizeof (evrregs.acc)
983 == register_size (gdbarch, tdep->ppc_acc_regnum));
984 gdb_assert (sizeof (evrregs.spefscr)
985 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
988 /* Since we're going to write out every register, the code below
989 should store to every field of evrregs; if that doesn't happen,
990 make it obvious by initializing it with suspicious values. */
991 memset (&evrregs, 42, sizeof (evrregs));
993 /* We can only read and write the entire EVR register set at a
994 time, so to write just a single register, we do a
995 read-modify-write maneuver. */
996 get_spe_registers (tid, &evrregs);
1002 for (i = 0; i < ppc_num_gprs; i++)
1003 regcache_raw_collect (regcache,
1004 tdep->ppc_ev0_upper_regnum + i,
1007 else if (tdep->ppc_ev0_upper_regnum <= regno
1008 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
1009 regcache_raw_collect (regcache, regno,
1010 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
1013 || regno == tdep->ppc_acc_regnum)
1014 regcache_raw_collect (regcache,
1015 tdep->ppc_acc_regnum,
1019 || regno == tdep->ppc_spefscr_regnum)
1020 regcache_raw_collect (regcache,
1021 tdep->ppc_spefscr_regnum,
1024 /* Write back the modified register set. */
1025 set_spe_registers (tid, &evrregs);
1029 store_register (const struct regcache *regcache, int tid, int regno)
1031 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1033 /* This isn't really an address. But ptrace thinks of it as one. */
1034 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
1036 size_t bytes_to_transfer;
1037 char buf[MAX_REGISTER_SIZE];
1039 if (altivec_register_p (gdbarch, regno))
1041 store_altivec_register (regcache, tid, regno);
1044 if (vsx_register_p (gdbarch, regno))
1046 store_vsx_register (regcache, tid, regno);
1049 else if (spe_register_p (gdbarch, regno))
1051 store_spe_register (regcache, tid, regno);
1058 /* First collect the register. Keep in mind that the regcache's
1059 idea of the register's size may not be a multiple of sizeof
1061 memset (buf, 0, sizeof buf);
1062 bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
1063 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1065 /* Little-endian values always sit at the left end of the buffer. */
1066 regcache_raw_collect (regcache, regno, buf);
1068 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1070 /* Big-endian values sit at the right end of the buffer. */
1071 size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
1072 regcache_raw_collect (regcache, regno, buf + padding);
1075 for (i = 0; i < bytes_to_transfer; i += sizeof (long))
1078 ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr,
1080 regaddr += sizeof (long);
1083 && (regno == tdep->ppc_fpscr_regnum
1084 || regno == PPC_ORIG_R3_REGNUM
1085 || regno == PPC_TRAP_REGNUM))
1087 /* Some older kernel versions don't allow fpscr, orig_r3
1088 or trap to be written. */
1095 sprintf (message, "writing register %s (#%d)",
1096 gdbarch_register_name (gdbarch, regno), regno);
1097 perror_with_name (message);
1103 fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
1106 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1107 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1108 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
1110 for (i = 0; i < ppc_num_vshrs; i++)
1111 regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
1112 *vsxregsetp + i * vsxregsize);
1116 fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
1119 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1120 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1121 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
1122 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
1123 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
1125 for (i = 0; i < num_of_vrregs; i++)
1127 /* The last 2 registers of this set are only 32 bit long, not
1128 128, but only VSCR is fetched as a 16 bytes quantity. */
1129 if (i == (num_of_vrregs - 2))
1130 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1131 *vrregsetp + i * vrregsize + offset);
1133 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1134 *vrregsetp + i * vrregsize);
1139 store_vsx_registers (const struct regcache *regcache, int tid)
1142 gdb_vsxregset_t regs;
1144 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
1149 have_ptrace_getsetvsxregs = 0;
1152 perror_with_name (_("Couldn't get VSX registers"));
1155 fill_vsxregset (regcache, ®s);
1157 if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0)
1158 perror_with_name (_("Couldn't write VSX registers"));
1162 store_altivec_registers (const struct regcache *regcache, int tid)
1165 gdb_vrregset_t regs;
1167 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
1172 have_ptrace_getvrregs = 0;
1175 perror_with_name (_("Couldn't get AltiVec registers"));
1178 fill_vrregset (regcache, ®s);
1180 if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0)
1181 perror_with_name (_("Couldn't write AltiVec registers"));
1184 /* This function actually issues the request to ptrace, telling
1185 it to store all general-purpose registers present in the specified
1188 If the ptrace request does not exist, this function returns 0
1189 and properly sets the have_ptrace_* flag. If the request fails,
1190 this function calls perror_with_name. Otherwise, if the request
1191 succeeds, then the regcache is stored and 1 is returned. */
1193 store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
1195 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1196 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1197 gdb_gregset_t gregset;
1199 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
1203 have_ptrace_getsetregs = 0;
1206 perror_with_name (_("Couldn't get general-purpose registers."));
1209 fill_gregset (regcache, &gregset, regno);
1211 if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
1215 have_ptrace_getsetregs = 0;
1218 perror_with_name (_("Couldn't set general-purpose registers."));
1224 /* This is a wrapper for the store_all_gp_regs function. It is
1225 responsible for verifying if this target has the ptrace request
1226 that can be used to store all general-purpose registers at one
1227 shot. If it doesn't, then we should store them using the
1228 old-fashioned way, which is to iterate over the registers and
1229 store them one by one. */
1231 store_gp_regs (const struct regcache *regcache, int tid, int regno)
1233 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1234 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1237 if (have_ptrace_getsetregs)
1238 if (store_all_gp_regs (regcache, tid, regno))
1241 /* If we hit this point, it doesn't really matter which
1242 architecture we are using. We just need to store the
1243 registers in the "old-fashioned way". */
1244 for (i = 0; i < ppc_num_gprs; i++)
1245 store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
1248 /* This function actually issues the request to ptrace, telling
1249 it to store all floating-point registers present in the specified
1252 If the ptrace request does not exist, this function returns 0
1253 and properly sets the have_ptrace_* flag. If the request fails,
1254 this function calls perror_with_name. Otherwise, if the request
1255 succeeds, then the regcache is stored and 1 is returned. */
1257 store_all_fp_regs (const struct regcache *regcache, int tid, int regno)
1259 gdb_fpregset_t fpregs;
1261 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
1265 have_ptrace_getsetfpregs = 0;
1268 perror_with_name (_("Couldn't get floating-point registers."));
1271 fill_fpregset (regcache, &fpregs, regno);
1273 if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
1277 have_ptrace_getsetfpregs = 0;
1280 perror_with_name (_("Couldn't set floating-point registers."));
1286 /* This is a wrapper for the store_all_fp_regs function. It is
1287 responsible for verifying if this target has the ptrace request
1288 that can be used to store all floating-point registers at one
1289 shot. If it doesn't, then we should store them using the
1290 old-fashioned way, which is to iterate over the registers and
1291 store them one by one. */
1293 store_fp_regs (const struct regcache *regcache, int tid, int regno)
1295 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1296 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1299 if (have_ptrace_getsetfpregs)
1300 if (store_all_fp_regs (regcache, tid, regno))
1303 /* If we hit this point, it doesn't really matter which
1304 architecture we are using. We just need to store the
1305 registers in the "old-fashioned way". */
1306 for (i = 0; i < ppc_num_fprs; i++)
1307 store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
1311 store_ppc_registers (const struct regcache *regcache, int tid)
1314 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1317 store_gp_regs (regcache, tid, -1);
1318 if (tdep->ppc_fp0_regnum >= 0)
1319 store_fp_regs (regcache, tid, -1);
1320 store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
1321 if (tdep->ppc_ps_regnum != -1)
1322 store_register (regcache, tid, tdep->ppc_ps_regnum);
1323 if (tdep->ppc_cr_regnum != -1)
1324 store_register (regcache, tid, tdep->ppc_cr_regnum);
1325 if (tdep->ppc_lr_regnum != -1)
1326 store_register (regcache, tid, tdep->ppc_lr_regnum);
1327 if (tdep->ppc_ctr_regnum != -1)
1328 store_register (regcache, tid, tdep->ppc_ctr_regnum);
1329 if (tdep->ppc_xer_regnum != -1)
1330 store_register (regcache, tid, tdep->ppc_xer_regnum);
1331 if (tdep->ppc_mq_regnum != -1)
1332 store_register (regcache, tid, tdep->ppc_mq_regnum);
1333 if (tdep->ppc_fpscr_regnum != -1)
1334 store_register (regcache, tid, tdep->ppc_fpscr_regnum);
1335 if (ppc_linux_trap_reg_p (gdbarch))
1337 store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1338 store_register (regcache, tid, PPC_TRAP_REGNUM);
1340 if (have_ptrace_getvrregs)
1341 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1342 store_altivec_registers (regcache, tid);
1343 if (have_ptrace_getsetvsxregs)
1344 if (tdep->ppc_vsr0_upper_regnum != -1)
1345 store_vsx_registers (regcache, tid);
1346 if (tdep->ppc_ev0_upper_regnum >= 0)
1347 store_spe_register (regcache, tid, -1);
1350 /* Fetch the AT_HWCAP entry from the aux vector. */
1351 unsigned long ppc_linux_get_hwcap (void)
1355 if (target_auxv_search (¤t_target, AT_HWCAP, &field))
1356 return (unsigned long) field;
1361 /* The cached DABR value, to install in new threads.
1362 This variable is used when we are dealing with non-BookE
1364 static long saved_dabr_value;
1366 /* Global structure that will store information about the available
1367 features on this BookE processor. */
1368 static struct ppc_debug_info booke_debug_info;
1370 /* Global variable that holds the maximum number of slots that the
1371 kernel will use. This is only used when the processor is BookE. */
1372 static size_t max_slots_number = 0;
1374 struct hw_break_tuple
1377 struct ppc_hw_breakpoint *hw_break;
1380 /* This is an internal VEC created to store information about *points inserted
1381 for each thread. This is used for BookE processors. */
1382 typedef struct thread_points
1384 /* The TID to which this *point relates. */
1386 /* Information about the *point, such as its address, type, etc.
1388 Each element inside this vector corresponds to a hardware
1389 breakpoint or watchpoint in the thread represented by TID. The maximum
1390 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1391 the tuple is NULL, then the position in the vector is free. */
1392 struct hw_break_tuple *hw_breaks;
1394 DEF_VEC_P (thread_points_p);
1396 VEC(thread_points_p) *ppc_threads = NULL;
1398 /* The version of the kernel interface that we will use if the processor is
1400 #define PPC_DEBUG_CURRENT_VERSION 1
1402 /* Returns non-zero if we support the ptrace interface which enables
1403 booke debugging resources. */
1405 have_ptrace_booke_interface (void)
1407 static int have_ptrace_booke_interface = -1;
1409 if (have_ptrace_booke_interface == -1)
1413 tid = TIDGET (inferior_ptid);
1415 tid = PIDGET (inferior_ptid);
1417 /* Check for kernel support for BOOKE debug registers. */
1418 if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &booke_debug_info) >= 0)
1420 have_ptrace_booke_interface = 1;
1421 max_slots_number = booke_debug_info.num_instruction_bps
1422 + booke_debug_info.num_data_bps
1423 + booke_debug_info.num_condition_regs;
1427 /* Old school interface and no BOOKE debug registers support. */
1428 have_ptrace_booke_interface = 0;
1429 memset (&booke_debug_info, 0, sizeof (struct ppc_debug_info));
1433 return have_ptrace_booke_interface;
1437 ppc_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
1439 int total_hw_wp, total_hw_bp;
1441 if (have_ptrace_booke_interface ())
1443 /* For PPC BookE processors, the number of available hardware
1444 watchpoints and breakpoints is stored at the booke_debug_info
1446 total_hw_bp = booke_debug_info.num_instruction_bps;
1447 total_hw_wp = booke_debug_info.num_data_bps;
1451 /* For PPC server processors, we accept 1 hardware watchpoint and 0
1452 hardware breakpoints. */
1457 if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
1458 || type == bp_access_watchpoint || type == bp_watchpoint)
1460 if (cnt > total_hw_wp)
1463 else if (type == bp_hardware_breakpoint)
1465 if (cnt > total_hw_bp)
1469 if (!have_ptrace_booke_interface ())
1472 ptid_t ptid = inferior_ptid;
1474 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1475 and whether the target has DABR. If either answer is no, the
1476 ptrace call will return -1. Fail in that case. */
1477 tid = TIDGET (ptid);
1479 tid = PIDGET (ptid);
1481 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1489 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
1491 /* Handle sub-8-byte quantities. */
1495 /* The new BookE ptrace interface tells if there are alignment restrictions
1496 for watchpoints in the processors. In that case, we use that information
1497 to determine the hardcoded watchable region for watchpoints. */
1498 if (have_ptrace_booke_interface ())
1500 /* DAC-based processors (i.e., embedded processors), like the PowerPC 440
1501 have ranged watchpoints and can watch any access within an arbitrary
1502 memory region. This is useful to watch arrays and structs, for
1503 instance. It takes two hardware watchpoints though. */
1505 && booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)
1507 else if (booke_debug_info.data_bp_alignment
1508 && (addr + len > (addr & ~(booke_debug_info.data_bp_alignment - 1))
1509 + booke_debug_info.data_bp_alignment))
1512 /* addr+len must fall in the 8 byte watchable region for DABR-based
1513 processors (i.e., server processors). Without the new BookE ptrace
1514 interface, DAC-based processors (i.e., embedded processors) will use
1515 addresses aligned to 4-bytes due to the way the read/write flags are
1516 passed in the old ptrace interface. */
1517 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1518 && (addr + len) > (addr & ~3) + 4)
1519 || (addr + len) > (addr & ~7) + 8)
1525 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1527 booke_cmp_hw_point (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
1529 return (a->trigger_type == b->trigger_type
1530 && a->addr_mode == b->addr_mode
1531 && a->condition_mode == b->condition_mode
1532 && a->addr == b->addr
1533 && a->addr2 == b->addr2
1534 && a->condition_value == b->condition_value);
1537 /* This function can be used to retrieve a thread_points by the TID of the
1538 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1539 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1540 provided TID will be created and returned. */
1541 static struct thread_points *
1542 booke_find_thread_points_by_tid (int tid, int alloc_new)
1545 struct thread_points *t;
1547 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
1553 /* Do we need to allocate a new point_item
1554 if the wanted one does not exist? */
1557 t = xmalloc (sizeof (struct thread_points));
1559 = xzalloc (max_slots_number * sizeof (struct hw_break_tuple));
1561 VEC_safe_push (thread_points_p, ppc_threads, t);
1567 /* This function is a generic wrapper that is responsible for inserting a
1568 *point (i.e., calling `ptrace' in order to issue the request to the
1569 kernel) and registering it internally in GDB. */
1571 booke_insert_point (struct ppc_hw_breakpoint *b, int tid)
1575 struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint));
1576 struct hw_break_tuple *hw_breaks;
1577 struct cleanup *c = make_cleanup (xfree, p);
1578 struct thread_points *t;
1579 struct hw_break_tuple *tuple;
1581 memcpy (p, b, sizeof (struct ppc_hw_breakpoint));
1584 slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p);
1586 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1588 /* Everything went fine, so we have to register this *point. */
1589 t = booke_find_thread_points_by_tid (tid, 1);
1590 gdb_assert (t != NULL);
1591 hw_breaks = t->hw_breaks;
1593 /* Find a free element in the hw_breaks vector. */
1594 for (i = 0; i < max_slots_number; i++)
1595 if (hw_breaks[i].hw_break == NULL)
1597 hw_breaks[i].slot = slot;
1598 hw_breaks[i].hw_break = p;
1602 gdb_assert (i != max_slots_number);
1604 discard_cleanups (c);
1607 /* This function is a generic wrapper that is responsible for removing a
1608 *point (i.e., calling `ptrace' in order to issue the request to the
1609 kernel), and unregistering it internally at GDB. */
1611 booke_remove_point (struct ppc_hw_breakpoint *b, int tid)
1614 struct hw_break_tuple *hw_breaks;
1615 struct thread_points *t;
1617 t = booke_find_thread_points_by_tid (tid, 0);
1618 gdb_assert (t != NULL);
1619 hw_breaks = t->hw_breaks;
1621 for (i = 0; i < max_slots_number; i++)
1622 if (hw_breaks[i].hw_break && booke_cmp_hw_point (hw_breaks[i].hw_break, b))
1625 gdb_assert (i != max_slots_number);
1627 /* We have to ignore ENOENT errors because the kernel implements hardware
1628 breakpoints/watchpoints as "one-shot", that is, they are automatically
1629 deleted when hit. */
1631 if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
1632 if (errno != ENOENT)
1633 perror_with_name (_("Unexpected error deleting "
1634 "breakpoint or watchpoint"));
1636 xfree (hw_breaks[i].hw_break);
1637 hw_breaks[i].hw_break = NULL;
1640 /* Return the number of registers needed for a ranged breakpoint. */
1643 ppc_linux_ranged_break_num_registers (struct target_ops *target)
1645 return ((have_ptrace_booke_interface ()
1646 && booke_debug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)?
1650 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1651 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1654 ppc_linux_insert_hw_breakpoint (struct gdbarch *gdbarch,
1655 struct bp_target_info *bp_tgt)
1657 struct lwp_info *lp;
1658 struct ppc_hw_breakpoint p;
1660 if (!have_ptrace_booke_interface ())
1663 p.version = PPC_DEBUG_CURRENT_VERSION;
1664 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1665 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1666 p.addr = (uint64_t) bp_tgt->placed_address;
1667 p.condition_value = 0;
1671 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1673 /* The breakpoint will trigger if the address of the instruction is
1674 within the defined range, as follows: p.addr <= address < p.addr2. */
1675 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1679 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1684 booke_insert_point (&p, TIDGET (lp->ptid));
1690 ppc_linux_remove_hw_breakpoint (struct gdbarch *gdbarch,
1691 struct bp_target_info *bp_tgt)
1693 struct lwp_info *lp;
1694 struct ppc_hw_breakpoint p;
1696 if (!have_ptrace_booke_interface ())
1699 p.version = PPC_DEBUG_CURRENT_VERSION;
1700 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1701 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1702 p.addr = (uint64_t) bp_tgt->placed_address;
1703 p.condition_value = 0;
1707 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1709 /* The breakpoint will trigger if the address of the instruction is within
1710 the defined range, as follows: p.addr <= address < p.addr2. */
1711 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1715 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1720 booke_remove_point (&p, TIDGET (lp->ptid));
1726 get_trigger_type (int rw)
1731 t = PPC_BREAKPOINT_TRIGGER_READ;
1732 else if (rw == hw_write)
1733 t = PPC_BREAKPOINT_TRIGGER_WRITE;
1735 t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
1740 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1741 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1742 or hw_access for an access watchpoint. Returns 0 on success and throws
1743 an error on failure. */
1746 ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1747 CORE_ADDR mask, int rw)
1749 struct lwp_info *lp;
1750 struct ppc_hw_breakpoint p;
1752 gdb_assert (have_ptrace_booke_interface ());
1754 p.version = PPC_DEBUG_CURRENT_VERSION;
1755 p.trigger_type = get_trigger_type (rw);
1756 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1757 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1760 p.condition_value = 0;
1763 booke_insert_point (&p, TIDGET (lp->ptid));
1768 /* Remove a masked watchpoint at ADDR with the mask MASK.
1769 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1770 or hw_access for an access watchpoint. Returns 0 on success and throws
1771 an error on failure. */
1774 ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1775 CORE_ADDR mask, int rw)
1777 struct lwp_info *lp;
1778 struct ppc_hw_breakpoint p;
1780 gdb_assert (have_ptrace_booke_interface ());
1782 p.version = PPC_DEBUG_CURRENT_VERSION;
1783 p.trigger_type = get_trigger_type (rw);
1784 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1785 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1788 p.condition_value = 0;
1791 booke_remove_point (&p, TIDGET (lp->ptid));
1796 /* Check whether we have at least one free DVC register. */
1798 can_use_watchpoint_cond_accel (void)
1800 struct thread_points *p;
1801 int tid = TIDGET (inferior_ptid);
1802 int cnt = booke_debug_info.num_condition_regs, i;
1803 CORE_ADDR tmp_value;
1805 if (!have_ptrace_booke_interface () || cnt == 0)
1808 p = booke_find_thread_points_by_tid (tid, 0);
1812 for (i = 0; i < max_slots_number; i++)
1813 if (p->hw_breaks[i].hw_break != NULL
1814 && (p->hw_breaks[i].hw_break->condition_mode
1815 != PPC_BREAKPOINT_CONDITION_NONE))
1818 /* There are no available slots now. */
1826 /* Calculate the enable bits and the contents of the Data Value Compare
1827 debug register present in BookE processors.
1829 ADDR is the address to be watched, LEN is the length of watched data
1830 and DATA_VALUE is the value which will trigger the watchpoint.
1831 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1832 CONDITION_VALUE will hold the value which should be put in the
1835 calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
1836 uint32_t *condition_mode, uint64_t *condition_value)
1838 int i, num_byte_enable, align_offset, num_bytes_off_dvc,
1839 rightmost_enabled_byte;
1840 CORE_ADDR addr_end_data, addr_end_dvc;
1842 /* The DVC register compares bytes within fixed-length windows which
1843 are word-aligned, with length equal to that of the DVC register.
1844 We need to calculate where our watch region is relative to that
1845 window and enable comparison of the bytes which fall within it. */
1847 align_offset = addr % booke_debug_info.sizeof_condition;
1848 addr_end_data = addr + len;
1849 addr_end_dvc = (addr - align_offset
1850 + booke_debug_info.sizeof_condition);
1851 num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
1852 addr_end_data - addr_end_dvc : 0;
1853 num_byte_enable = len - num_bytes_off_dvc;
1854 /* Here, bytes are numbered from right to left. */
1855 rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
1856 addr_end_dvc - addr_end_data : 0;
1858 *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
1859 for (i = 0; i < num_byte_enable; i++)
1861 |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
1863 /* Now we need to match the position within the DVC of the comparison
1864 value with where the watch region is relative to the window
1865 (i.e., the ALIGN_OFFSET). */
1867 *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
1868 << rightmost_enabled_byte * 8);
1871 /* Return the number of memory locations that need to be accessed to
1872 evaluate the expression which generated the given value chain.
1873 Returns -1 if there's any register access involved, or if there are
1874 other kinds of values which are not acceptable in a condition
1875 expression (e.g., lval_computed or lval_internalvar). */
1877 num_memory_accesses (struct value *v)
1879 int found_memory_cnt = 0;
1880 struct value *head = v;
1882 /* The idea here is that evaluating an expression generates a series
1883 of values, one holding the value of every subexpression. (The
1884 expression a*b+c has five subexpressions: a, b, a*b, c, and
1885 a*b+c.) GDB's values hold almost enough information to establish
1886 the criteria given above --- they identify memory lvalues,
1887 register lvalues, computed values, etcetera. So we can evaluate
1888 the expression, and then scan the chain of values that leaves
1889 behind to determine the memory locations involved in the evaluation
1892 However, I don't think that the values returned by inferior
1893 function calls are special in any way. So this function may not
1894 notice that an expression contains an inferior function call.
1897 for (; v; v = value_next (v))
1899 /* Constants and values from the history are fine. */
1900 if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
1902 else if (VALUE_LVAL (v) == lval_memory)
1904 /* A lazy memory lvalue is one that GDB never needed to fetch;
1905 we either just used its address (e.g., `a' in `a.b') or
1906 we never needed it at all (e.g., `a' in `a,b'). */
1907 if (!value_lazy (v))
1910 /* Other kinds of values are not fine. */
1915 return found_memory_cnt;
1918 /* Verifies whether the expression COND can be implemented using the
1919 DVC (Data Value Compare) register in BookE processors. The expression
1920 must test the watch value for equality with a constant expression.
1921 If the function returns 1, DATA_VALUE will contain the constant against
1922 which the watch value should be compared and LEN will contain the size
1925 check_condition (CORE_ADDR watch_addr, struct expression *cond,
1926 CORE_ADDR *data_value, int *len)
1928 int pc = 1, num_accesses_left, num_accesses_right;
1929 struct value *left_val, *right_val, *left_chain, *right_chain;
1931 if (cond->elts[0].opcode != BINOP_EQUAL)
1934 fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain);
1935 num_accesses_left = num_memory_accesses (left_chain);
1937 if (left_val == NULL || num_accesses_left < 0)
1939 free_value_chain (left_chain);
1944 fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain);
1945 num_accesses_right = num_memory_accesses (right_chain);
1947 if (right_val == NULL || num_accesses_right < 0)
1949 free_value_chain (left_chain);
1950 free_value_chain (right_chain);
1955 if (num_accesses_left == 1 && num_accesses_right == 0
1956 && VALUE_LVAL (left_val) == lval_memory
1957 && value_address (left_val) == watch_addr)
1959 *data_value = value_as_long (right_val);
1961 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1962 the same type as the memory region referenced by LEFT_VAL. */
1963 *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
1965 else if (num_accesses_left == 0 && num_accesses_right == 1
1966 && VALUE_LVAL (right_val) == lval_memory
1967 && value_address (right_val) == watch_addr)
1969 *data_value = value_as_long (left_val);
1971 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1972 the same type as the memory region referenced by RIGHT_VAL. */
1973 *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
1977 free_value_chain (left_chain);
1978 free_value_chain (right_chain);
1983 free_value_chain (left_chain);
1984 free_value_chain (right_chain);
1989 /* Return non-zero if the target is capable of using hardware to evaluate
1990 the condition expression, thus only triggering the watchpoint when it is
1993 ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr, int len, int rw,
1994 struct expression *cond)
1996 CORE_ADDR data_value;
1998 return (have_ptrace_booke_interface ()
1999 && booke_debug_info.num_condition_regs > 0
2000 && check_condition (addr, cond, &data_value, &len));
2003 /* Set up P with the parameters necessary to request a watchpoint covering
2004 LEN bytes starting at ADDR and if possible with condition expression COND
2005 evaluated by hardware. INSERT tells if we are creating a request for
2006 inserting or removing the watchpoint. */
2009 create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
2010 int len, int rw, struct expression *cond,
2014 || !(booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
2017 CORE_ADDR data_value;
2019 use_condition = (insert? can_use_watchpoint_cond_accel ()
2020 : booke_debug_info.num_condition_regs > 0);
2021 if (cond && use_condition && check_condition (addr, cond,
2023 calculate_dvc (addr, len, data_value, &p->condition_mode,
2024 &p->condition_value);
2027 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2028 p->condition_value = 0;
2031 p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
2036 p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
2037 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2038 p->condition_value = 0;
2040 /* The watchpoint will trigger if the address of the memory access is
2041 within the defined range, as follows: p->addr <= address < p->addr2.
2043 Note that the above sentence just documents how ptrace interprets
2044 its arguments; the watchpoint is set to watch the range defined by
2045 the user _inclusively_, as specified by the user interface. */
2046 p->addr2 = (uint64_t) addr + len;
2049 p->version = PPC_DEBUG_CURRENT_VERSION;
2050 p->trigger_type = get_trigger_type (rw);
2051 p->addr = (uint64_t) addr;
2055 ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw,
2056 struct expression *cond)
2058 struct lwp_info *lp;
2061 if (have_ptrace_booke_interface ())
2063 struct ppc_hw_breakpoint p;
2065 create_watchpoint_request (&p, addr, len, rw, cond, 1);
2068 booke_insert_point (&p, TIDGET (lp->ptid));
2075 long read_mode, write_mode;
2077 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2079 /* PowerPC 440 requires only the read/write flags to be passed
2086 /* PowerPC 970 and other DABR-based processors are required to pass
2087 the Breakpoint Translation bit together with the flags. */
2092 dabr_value = addr & ~(read_mode | write_mode);
2096 /* Set read and translate bits. */
2097 dabr_value |= read_mode;
2100 /* Set write and translate bits. */
2101 dabr_value |= write_mode;
2104 /* Set read, write and translate bits. */
2105 dabr_value |= read_mode | write_mode;
2109 saved_dabr_value = dabr_value;
2112 if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (lp->ptid), 0,
2113 saved_dabr_value) < 0)
2123 ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw,
2124 struct expression *cond)
2126 struct lwp_info *lp;
2129 if (have_ptrace_booke_interface ())
2131 struct ppc_hw_breakpoint p;
2133 create_watchpoint_request (&p, addr, len, rw, cond, 0);
2136 booke_remove_point (&p, TIDGET (lp->ptid));
2142 saved_dabr_value = 0;
2144 if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (lp->ptid), 0,
2145 saved_dabr_value) < 0)
2155 ppc_linux_new_thread (struct lwp_info *lp)
2157 int tid = TIDGET (lp->ptid);
2159 if (have_ptrace_booke_interface ())
2162 struct thread_points *p;
2163 struct hw_break_tuple *hw_breaks;
2165 if (VEC_empty (thread_points_p, ppc_threads))
2168 /* Get a list of breakpoints from any thread. */
2169 p = VEC_last (thread_points_p, ppc_threads);
2170 hw_breaks = p->hw_breaks;
2172 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2173 for (i = 0; i < max_slots_number; i++)
2174 if (hw_breaks[i].hw_break)
2175 booke_insert_point (hw_breaks[i].hw_break, tid);
2178 ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
2182 ppc_linux_thread_exit (struct thread_info *tp, int silent)
2185 int tid = TIDGET (tp->ptid);
2186 struct hw_break_tuple *hw_breaks;
2187 struct thread_points *t = NULL, *p;
2189 if (!have_ptrace_booke_interface ())
2192 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
2202 VEC_unordered_remove (thread_points_p, ppc_threads, i);
2204 hw_breaks = t->hw_breaks;
2206 for (i = 0; i < max_slots_number; i++)
2207 if (hw_breaks[i].hw_break)
2208 xfree (hw_breaks[i].hw_break);
2210 xfree (t->hw_breaks);
2215 ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
2217 struct siginfo *siginfo_p;
2219 siginfo_p = linux_nat_get_siginfo (inferior_ptid);
2221 if (siginfo_p->si_signo != SIGTRAP
2222 || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2225 if (have_ptrace_booke_interface ())
2228 struct thread_points *t;
2229 struct hw_break_tuple *hw_breaks;
2230 /* The index (or slot) of the *point is passed in the si_errno field. */
2231 int slot = siginfo_p->si_errno;
2233 t = booke_find_thread_points_by_tid (TIDGET (inferior_ptid), 0);
2235 /* Find out if this *point is a hardware breakpoint.
2236 If so, we should return 0. */
2239 hw_breaks = t->hw_breaks;
2240 for (i = 0; i < max_slots_number; i++)
2241 if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
2242 && hw_breaks[i].hw_break->trigger_type
2243 == PPC_BREAKPOINT_TRIGGER_EXECUTE)
2248 *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr;
2253 ppc_linux_stopped_by_watchpoint (void)
2256 return ppc_linux_stopped_data_address (¤t_target, &addr);
2260 ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
2262 CORE_ADDR start, int length)
2266 if (have_ptrace_booke_interface ()
2267 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2268 return start <= addr && start + length >= addr;
2269 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2276 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2277 return start <= addr + mask && start + length - 1 >= addr;
2280 /* Return the number of registers needed for a masked hardware watchpoint. */
2283 ppc_linux_masked_watch_num_registers (struct target_ops *target,
2284 CORE_ADDR addr, CORE_ADDR mask)
2286 if (!have_ptrace_booke_interface ()
2287 || (booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0)
2289 else if ((mask & 0xC0000000) != 0xC0000000)
2291 warning (_("The given mask covers kernel address space "
2292 "and cannot be used.\n"));
2301 ppc_linux_store_inferior_registers (struct target_ops *ops,
2302 struct regcache *regcache, int regno)
2304 /* Overload thread id onto process id. */
2305 int tid = TIDGET (inferior_ptid);
2307 /* No thread id, just use process id. */
2309 tid = PIDGET (inferior_ptid);
2312 store_register (regcache, tid, regno);
2314 store_ppc_registers (regcache, tid);
2317 /* Functions for transferring registers between a gregset_t or fpregset_t
2318 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2319 by the ptrace interface, not the current program's ABI. Eg. if a
2320 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2321 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2324 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
2326 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2328 ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
2332 fill_gregset (const struct regcache *regcache,
2333 gdb_gregset_t *gregsetp, int regno)
2335 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2338 memset (gregsetp, 0, sizeof (*gregsetp));
2339 ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
2343 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
2345 const struct regset *regset = ppc_linux_fpregset ();
2347 ppc_supply_fpregset (regset, regcache, -1,
2348 fpregsetp, sizeof (*fpregsetp));
2352 fill_fpregset (const struct regcache *regcache,
2353 gdb_fpregset_t *fpregsetp, int regno)
2355 const struct regset *regset = ppc_linux_fpregset ();
2357 ppc_collect_fpregset (regset, regcache, regno,
2358 fpregsetp, sizeof (*fpregsetp));
2362 ppc_linux_target_wordsize (void)
2366 /* Check for 64-bit inferior process. This is the case when the host is
2367 64-bit, and in addition the top bit of the MSR register is set. */
2368 #ifdef __powerpc64__
2371 int tid = TIDGET (inferior_ptid);
2373 tid = PIDGET (inferior_ptid);
2376 msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
2377 if (errno == 0 && msr < 0)
2385 ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
2386 gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
2388 int sizeof_auxv_field = ppc_linux_target_wordsize ();
2389 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch);
2390 gdb_byte *ptr = *readptr;
2395 if (endptr - ptr < sizeof_auxv_field * 2)
2398 *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2399 ptr += sizeof_auxv_field;
2400 *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2401 ptr += sizeof_auxv_field;
2407 static const struct target_desc *
2408 ppc_linux_read_description (struct target_ops *ops)
2415 int tid = TIDGET (inferior_ptid);
2417 tid = PIDGET (inferior_ptid);
2419 if (have_ptrace_getsetevrregs)
2421 struct gdb_evrregset_t evrregset;
2423 if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
2424 return tdesc_powerpc_e500l;
2426 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2427 Anything else needs to be reported. */
2428 else if (errno != EIO)
2429 perror_with_name (_("Unable to fetch SPE registers"));
2432 if (have_ptrace_getsetvsxregs)
2434 gdb_vsxregset_t vsxregset;
2436 if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
2439 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2440 Anything else needs to be reported. */
2441 else if (errno != EIO)
2442 perror_with_name (_("Unable to fetch VSX registers"));
2445 if (have_ptrace_getvrregs)
2447 gdb_vrregset_t vrregset;
2449 if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
2452 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2453 Anything else needs to be reported. */
2454 else if (errno != EIO)
2455 perror_with_name (_("Unable to fetch AltiVec registers"));
2458 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2459 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2460 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2461 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2462 half of the register are for Decimal Floating Point, we check if that
2463 feature is available to decide the size of the FPSCR. */
2464 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP)
2467 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL)
2470 if (ppc_linux_target_wordsize () == 8)
2473 return tdesc_powerpc_cell64l;
2475 return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
2478 ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
2480 return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
2484 return tdesc_powerpc_cell32l;
2486 return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
2488 return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
2490 return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l;
2493 void _initialize_ppc_linux_nat (void);
2496 _initialize_ppc_linux_nat (void)
2498 struct target_ops *t;
2500 /* Fill in the generic GNU/Linux methods. */
2501 t = linux_target ();
2503 /* Add our register access methods. */
2504 t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
2505 t->to_store_registers = ppc_linux_store_inferior_registers;
2507 /* Add our breakpoint/watchpoint methods. */
2508 t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint;
2509 t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint;
2510 t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint;
2511 t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
2512 t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
2513 t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
2514 t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint;
2515 t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint;
2516 t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
2517 t->to_stopped_data_address = ppc_linux_stopped_data_address;
2518 t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
2519 t->to_can_accel_watchpoint_condition
2520 = ppc_linux_can_accel_watchpoint_condition;
2521 t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers;
2522 t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers;
2524 t->to_read_description = ppc_linux_read_description;
2525 t->to_auxv_parse = ppc_linux_auxv_parse;
2527 observer_attach_thread_exit (ppc_linux_thread_exit);
2529 /* Register the target. */
2530 linux_nat_add_target (t);
2531 linux_nat_set_new_thread (t, ppc_linux_new_thread);