1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdbthread.h"
28 #include "linux-nat.h"
31 #include <sys/types.h>
34 #include <sys/ioctl.h>
37 #include <sys/procfs.h>
38 #include <sys/ptrace.h>
40 /* Prototypes for supply_gregset etc. */
43 #include "ppc-linux-tdep.h"
45 /* Required when using the AUXV. */
46 #include "elf/common.h"
49 #include "nat/ppc-linux.h"
51 /* Similarly for the hardware watchpoint support. These requests are used
52 when the PowerPC HWDEBUG ptrace interface is not available. */
53 #ifndef PTRACE_GET_DEBUGREG
54 #define PTRACE_GET_DEBUGREG 25
56 #ifndef PTRACE_SET_DEBUGREG
57 #define PTRACE_SET_DEBUGREG 26
59 #ifndef PTRACE_GETSIGINFO
60 #define PTRACE_GETSIGINFO 0x4202
63 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
64 available. It exposes the debug facilities of PowerPC processors, as well
65 as additional features of BookE processors, such as ranged breakpoints and
66 watchpoints and hardware-accelerated condition evaluation. */
67 #ifndef PPC_PTRACE_GETHWDBGINFO
69 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
70 ptrace interface is not present in ptrace.h, so we'll have to pretty much
71 include it all here so that the code at least compiles on older systems. */
72 #define PPC_PTRACE_GETHWDBGINFO 0x89
73 #define PPC_PTRACE_SETHWDEBUG 0x88
74 #define PPC_PTRACE_DELHWDEBUG 0x87
78 uint32_t version; /* Only version 1 exists to date. */
79 uint32_t num_instruction_bps;
80 uint32_t num_data_bps;
81 uint32_t num_condition_regs;
82 uint32_t data_bp_alignment;
83 uint32_t sizeof_condition; /* size of the DVC register. */
87 /* Features will have bits indicating whether there is support for: */
88 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
89 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
90 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
91 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
93 struct ppc_hw_breakpoint
95 uint32_t version; /* currently, version must be 1 */
96 uint32_t trigger_type; /* only some combinations allowed */
97 uint32_t addr_mode; /* address match mode */
98 uint32_t condition_mode; /* break/watchpoint condition flags */
99 uint64_t addr; /* break/watchpoint address */
100 uint64_t addr2; /* range end or mask */
101 uint64_t condition_value; /* contents of the DVC register */
105 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
106 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
107 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
108 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
111 #define PPC_BREAKPOINT_MODE_EXACT 0x0
112 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
113 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
114 #define PPC_BREAKPOINT_MODE_MASK 0x3
116 /* Condition mode. */
117 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
118 #define PPC_BREAKPOINT_CONDITION_AND 0x1
119 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
120 #define PPC_BREAKPOINT_CONDITION_OR 0x2
121 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
122 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
123 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
124 #define PPC_BREAKPOINT_CONDITION_BE(n) \
125 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
126 #endif /* PPC_PTRACE_GETHWDBGINFO */
128 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
129 watchpoint (up to 512 bytes). */
130 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
131 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
132 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
134 /* Similarly for the general-purpose (gp0 -- gp31)
135 and floating-point registers (fp0 -- fp31). */
136 #ifndef PTRACE_GETREGS
137 #define PTRACE_GETREGS 12
139 #ifndef PTRACE_SETREGS
140 #define PTRACE_SETREGS 13
142 #ifndef PTRACE_GETFPREGS
143 #define PTRACE_GETFPREGS 14
145 #ifndef PTRACE_SETFPREGS
146 #define PTRACE_SETFPREGS 15
149 /* This oddity is because the Linux kernel defines elf_vrregset_t as
150 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
151 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
152 the vrsave as an extra 4 bytes at the end. I opted for creating a
153 flat array of chars, so that it is easier to manipulate for gdb.
155 There are 32 vector registers 16 bytes longs, plus a VSCR register
156 which is only 4 bytes long, but is fetched as a 16 bytes
157 quantity. Up to here we have the elf_vrregset_t structure.
158 Appended to this there is space for the VRSAVE register: 4 bytes.
159 Even though this vrsave register is not included in the regset
160 typedef, it is handled by the ptrace requests.
162 Note that GNU/Linux doesn't support little endian PPC hardware,
163 therefore the offset at which the real value of the VSCR register
164 is located will be always 12 bytes.
166 The layout is like this (where x is the actual value of the vscr reg): */
170 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
171 <-------> <-------><-------><->
176 #define SIZEOF_VRREGS 33*16+4
178 typedef char gdb_vrregset_t[SIZEOF_VRREGS];
180 /* This is the layout of the POWER7 VSX registers and the way they overlap
181 with the existing FPR and VMX registers.
183 VSR doubleword 0 VSR doubleword 1
184 ----------------------------------------------------------------
186 ----------------------------------------------------------------
188 ----------------------------------------------------------------
191 ----------------------------------------------------------------
192 VSR[30] | FPR[30] | |
193 ----------------------------------------------------------------
194 VSR[31] | FPR[31] | |
195 ----------------------------------------------------------------
197 ----------------------------------------------------------------
199 ----------------------------------------------------------------
202 ----------------------------------------------------------------
204 ----------------------------------------------------------------
206 ----------------------------------------------------------------
208 VSX has 64 128bit registers. The first 32 registers overlap with
209 the FP registers (doubleword 0) and hence extend them with additional
210 64 bits (doubleword 1). The other 32 regs overlap with the VMX
212 #define SIZEOF_VSXREGS 32*8
214 typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
216 /* On PPC processors that support the Signal Processing Extension
217 (SPE) APU, the general-purpose registers are 64 bits long.
218 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
219 ptrace calls only access the lower half of each register, to allow
220 them to behave the same way they do on non-SPE systems. There's a
221 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
222 read and write the top halves of all the general-purpose registers
223 at once, along with some SPE-specific registers.
225 GDB itself continues to claim the general-purpose registers are 32
226 bits long. It has unnamed raw registers that hold the upper halves
227 of the gprs, and the full 64-bit SIMD views of the registers,
228 'ev0' -- 'ev31', are pseudo-registers that splice the top and
229 bottom halves together.
231 This is the structure filled in by PTRACE_GETEVRREGS and written to
232 the inferior's registers by PTRACE_SETEVRREGS. */
233 struct gdb_evrregset_t
235 unsigned long evr[32];
236 unsigned long long acc;
237 unsigned long spefscr;
240 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
241 PTRACE_SETVSXREGS requests, for reading and writing the VSX
242 POWER7 registers 0 through 31. Zero if we've tried one of them and
243 gotten an error. Note that VSX registers 32 through 63 overlap
244 with VR registers 0 through 31. */
245 int have_ptrace_getsetvsxregs = 1;
247 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
248 PTRACE_SETVRREGS requests, for reading and writing the Altivec
249 registers. Zero if we've tried one of them and gotten an
251 int have_ptrace_getvrregs = 1;
253 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
254 PTRACE_SETEVRREGS requests, for reading and writing the SPE
255 registers. Zero if we've tried one of them and gotten an
257 int have_ptrace_getsetevrregs = 1;
259 /* Non-zero if our kernel may support the PTRACE_GETREGS and
260 PTRACE_SETREGS requests, for reading and writing the
261 general-purpose registers. Zero if we've tried one of
262 them and gotten an error. */
263 int have_ptrace_getsetregs = 1;
265 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
266 PTRACE_SETFPREGS requests, for reading and writing the
267 floating-pointers registers. Zero if we've tried one of
268 them and gotten an error. */
269 int have_ptrace_getsetfpregs = 1;
272 /* registers layout, as presented by the ptrace interface:
273 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
274 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
275 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
276 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
277 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
278 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
279 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
280 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
281 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
282 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
283 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
284 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
285 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
289 ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
292 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
293 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
294 interface, and not the wordsize of the program's ABI. */
295 int wordsize = sizeof (long);
297 /* General purpose registers occupy 1 slot each in the buffer. */
298 if (regno >= tdep->ppc_gp0_regnum
299 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
300 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
302 /* Floating point regs: eight bytes each in both 32- and 64-bit
303 ptrace interfaces. Thus, two slots each in 32-bit interface, one
304 slot each in 64-bit interface. */
305 if (tdep->ppc_fp0_regnum >= 0
306 && regno >= tdep->ppc_fp0_regnum
307 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
308 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
310 /* UISA special purpose registers: 1 slot each. */
311 if (regno == gdbarch_pc_regnum (gdbarch))
312 u_addr = PT_NIP * wordsize;
313 if (regno == tdep->ppc_lr_regnum)
314 u_addr = PT_LNK * wordsize;
315 if (regno == tdep->ppc_cr_regnum)
316 u_addr = PT_CCR * wordsize;
317 if (regno == tdep->ppc_xer_regnum)
318 u_addr = PT_XER * wordsize;
319 if (regno == tdep->ppc_ctr_regnum)
320 u_addr = PT_CTR * wordsize;
322 if (regno == tdep->ppc_mq_regnum)
323 u_addr = PT_MQ * wordsize;
325 if (regno == tdep->ppc_ps_regnum)
326 u_addr = PT_MSR * wordsize;
327 if (regno == PPC_ORIG_R3_REGNUM)
328 u_addr = PT_ORIG_R3 * wordsize;
329 if (regno == PPC_TRAP_REGNUM)
330 u_addr = PT_TRAP * wordsize;
331 if (tdep->ppc_fpscr_regnum >= 0
332 && regno == tdep->ppc_fpscr_regnum)
334 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
335 kernel headers incorrectly contained the 32-bit definition of
336 PT_FPSCR. For the 32-bit definition, floating-point
337 registers occupy two 32-bit "slots", and the FPSCR lives in
338 the second half of such a slot-pair (hence +1). For 64-bit,
339 the FPSCR instead occupies the full 64-bit 2-word-slot and
340 hence no adjustment is necessary. Hack around this. */
341 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
342 u_addr = (48 + 32) * wordsize;
343 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
344 slot and not just its second word. The PT_FPSCR supplied when
345 GDB is compiled as a 32-bit app doesn't reflect this. */
346 else if (wordsize == 4 && register_size (gdbarch, regno) == 8
347 && PT_FPSCR == (48 + 2*32 + 1))
348 u_addr = (48 + 2*32) * wordsize;
350 u_addr = PT_FPSCR * wordsize;
355 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
356 registers set mechanism, as opposed to the interface for all the
357 other registers, that stores/fetches each register individually. */
359 fetch_vsx_register (struct regcache *regcache, int tid, int regno)
362 gdb_vsxregset_t regs;
363 struct gdbarch *gdbarch = get_regcache_arch (regcache);
364 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
365 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
367 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
372 have_ptrace_getsetvsxregs = 0;
375 perror_with_name (_("Unable to fetch VSX register"));
378 regcache_raw_supply (regcache, regno,
379 regs + (regno - tdep->ppc_vsr0_upper_regnum)
383 /* The Linux kernel ptrace interface for AltiVec registers uses the
384 registers set mechanism, as opposed to the interface for all the
385 other registers, that stores/fetches each register individually. */
387 fetch_altivec_register (struct regcache *regcache, int tid, int regno)
392 struct gdbarch *gdbarch = get_regcache_arch (regcache);
393 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
394 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
396 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
401 have_ptrace_getvrregs = 0;
404 perror_with_name (_("Unable to fetch AltiVec register"));
407 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
408 long on the hardware. We deal only with the lower 4 bytes of the
409 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
410 there is no need to define an offset for it. */
411 if (regno == (tdep->ppc_vrsave_regnum - 1))
412 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
414 regcache_raw_supply (regcache, regno,
416 - tdep->ppc_vr0_regnum) * vrregsize + offset);
419 /* Fetch the top 32 bits of TID's general-purpose registers and the
420 SPE-specific registers, and place the results in EVRREGSET. If we
421 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
424 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
425 PTRACE_SETEVRREGS requests are supported is isolated here, and in
426 set_spe_registers. */
428 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
430 if (have_ptrace_getsetevrregs)
432 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
436 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
437 we just return zeros. */
439 have_ptrace_getsetevrregs = 0;
441 /* Anything else needs to be reported. */
442 perror_with_name (_("Unable to fetch SPE registers"));
446 memset (evrregset, 0, sizeof (*evrregset));
449 /* Supply values from TID for SPE-specific raw registers: the upper
450 halves of the GPRs, the accumulator, and the spefscr. REGNO must
451 be the number of an upper half register, acc, spefscr, or -1 to
452 supply the values of all registers. */
454 fetch_spe_register (struct regcache *regcache, int tid, int regno)
456 struct gdbarch *gdbarch = get_regcache_arch (regcache);
457 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
458 struct gdb_evrregset_t evrregs;
460 gdb_assert (sizeof (evrregs.evr[0])
461 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
462 gdb_assert (sizeof (evrregs.acc)
463 == register_size (gdbarch, tdep->ppc_acc_regnum));
464 gdb_assert (sizeof (evrregs.spefscr)
465 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
467 get_spe_registers (tid, &evrregs);
473 for (i = 0; i < ppc_num_gprs; i++)
474 regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
477 else if (tdep->ppc_ev0_upper_regnum <= regno
478 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
479 regcache_raw_supply (regcache, regno,
480 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
483 || regno == tdep->ppc_acc_regnum)
484 regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
487 || regno == tdep->ppc_spefscr_regnum)
488 regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
493 fetch_register (struct regcache *regcache, int tid, int regno)
495 struct gdbarch *gdbarch = get_regcache_arch (regcache);
496 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
497 /* This isn't really an address. But ptrace thinks of it as one. */
498 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
499 int bytes_transferred;
500 unsigned int offset; /* Offset of registers within the u area. */
501 gdb_byte buf[MAX_REGISTER_SIZE];
503 if (altivec_register_p (gdbarch, regno))
505 /* If this is the first time through, or if it is not the first
506 time through, and we have comfirmed that there is kernel
507 support for such a ptrace request, then go and fetch the
509 if (have_ptrace_getvrregs)
511 fetch_altivec_register (regcache, tid, regno);
514 /* If we have discovered that there is no ptrace support for
515 AltiVec registers, fall through and return zeroes, because
516 regaddr will be -1 in this case. */
518 if (vsx_register_p (gdbarch, regno))
520 if (have_ptrace_getsetvsxregs)
522 fetch_vsx_register (regcache, tid, regno);
526 else if (spe_register_p (gdbarch, regno))
528 fetch_spe_register (regcache, tid, regno);
534 memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
535 regcache_raw_supply (regcache, regno, buf);
539 /* Read the raw register using sizeof(long) sized chunks. On a
540 32-bit platform, 64-bit floating-point registers will require two
542 for (bytes_transferred = 0;
543 bytes_transferred < register_size (gdbarch, regno);
544 bytes_transferred += sizeof (long))
549 l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
550 regaddr += sizeof (long);
554 xsnprintf (message, sizeof (message), "reading register %s (#%d)",
555 gdbarch_register_name (gdbarch, regno), regno);
556 perror_with_name (message);
558 memcpy (&buf[bytes_transferred], &l, sizeof (l));
561 /* Now supply the register. Keep in mind that the regcache's idea
562 of the register's size may not be a multiple of sizeof
564 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
566 /* Little-endian values are always found at the left end of the
567 bytes transferred. */
568 regcache_raw_supply (regcache, regno, buf);
570 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
572 /* Big-endian values are found at the right end of the bytes
574 size_t padding = (bytes_transferred - register_size (gdbarch, regno));
575 regcache_raw_supply (regcache, regno, buf + padding);
578 internal_error (__FILE__, __LINE__,
579 _("fetch_register: unexpected byte order: %d"),
580 gdbarch_byte_order (gdbarch));
584 supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
587 struct gdbarch *gdbarch = get_regcache_arch (regcache);
588 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
589 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
591 for (i = 0; i < ppc_num_vshrs; i++)
593 regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
594 *vsxregsetp + i * vsxregsize);
599 supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)
602 struct gdbarch *gdbarch = get_regcache_arch (regcache);
603 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
604 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
605 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
606 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
608 for (i = 0; i < num_of_vrregs; i++)
610 /* The last 2 registers of this set are only 32 bit long, not
611 128. However an offset is necessary only for VSCR because it
612 occupies a whole vector, while VRSAVE occupies a full 4 bytes
614 if (i == (num_of_vrregs - 2))
615 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
616 *vrregsetp + i * vrregsize + offset);
618 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
619 *vrregsetp + i * vrregsize);
624 fetch_vsx_registers (struct regcache *regcache, int tid)
627 gdb_vsxregset_t regs;
629 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
634 have_ptrace_getsetvsxregs = 0;
637 perror_with_name (_("Unable to fetch VSX registers"));
639 supply_vsxregset (regcache, ®s);
643 fetch_altivec_registers (struct regcache *regcache, int tid)
648 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
653 have_ptrace_getvrregs = 0;
656 perror_with_name (_("Unable to fetch AltiVec registers"));
658 supply_vrregset (regcache, ®s);
661 /* This function actually issues the request to ptrace, telling
662 it to get all general-purpose registers and put them into the
665 If the ptrace request does not exist, this function returns 0
666 and properly sets the have_ptrace_* flag. If the request fails,
667 this function calls perror_with_name. Otherwise, if the request
668 succeeds, then the regcache gets filled and 1 is returned. */
670 fetch_all_gp_regs (struct regcache *regcache, int tid)
672 struct gdbarch *gdbarch = get_regcache_arch (regcache);
673 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
674 gdb_gregset_t gregset;
676 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
680 have_ptrace_getsetregs = 0;
683 perror_with_name (_("Couldn't get general-purpose registers."));
686 supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
691 /* This is a wrapper for the fetch_all_gp_regs function. It is
692 responsible for verifying if this target has the ptrace request
693 that can be used to fetch all general-purpose registers at one
694 shot. If it doesn't, then we should fetch them using the
695 old-fashioned way, which is to iterate over the registers and
696 request them one by one. */
698 fetch_gp_regs (struct regcache *regcache, int tid)
700 struct gdbarch *gdbarch = get_regcache_arch (regcache);
701 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
704 if (have_ptrace_getsetregs)
705 if (fetch_all_gp_regs (regcache, tid))
708 /* If we've hit this point, it doesn't really matter which
709 architecture we are using. We just need to read the
710 registers in the "old-fashioned way". */
711 for (i = 0; i < ppc_num_gprs; i++)
712 fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
715 /* This function actually issues the request to ptrace, telling
716 it to get all floating-point registers and put them into the
719 If the ptrace request does not exist, this function returns 0
720 and properly sets the have_ptrace_* flag. If the request fails,
721 this function calls perror_with_name. Otherwise, if the request
722 succeeds, then the regcache gets filled and 1 is returned. */
724 fetch_all_fp_regs (struct regcache *regcache, int tid)
726 gdb_fpregset_t fpregs;
728 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
732 have_ptrace_getsetfpregs = 0;
735 perror_with_name (_("Couldn't get floating-point registers."));
738 supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs);
743 /* This is a wrapper for the fetch_all_fp_regs function. It is
744 responsible for verifying if this target has the ptrace request
745 that can be used to fetch all floating-point registers at one
746 shot. If it doesn't, then we should fetch them using the
747 old-fashioned way, which is to iterate over the registers and
748 request them one by one. */
750 fetch_fp_regs (struct regcache *regcache, int tid)
752 struct gdbarch *gdbarch = get_regcache_arch (regcache);
753 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
756 if (have_ptrace_getsetfpregs)
757 if (fetch_all_fp_regs (regcache, tid))
760 /* If we've hit this point, it doesn't really matter which
761 architecture we are using. We just need to read the
762 registers in the "old-fashioned way". */
763 for (i = 0; i < ppc_num_fprs; i++)
764 fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
768 fetch_ppc_registers (struct regcache *regcache, int tid)
771 struct gdbarch *gdbarch = get_regcache_arch (regcache);
772 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
774 fetch_gp_regs (regcache, tid);
775 if (tdep->ppc_fp0_regnum >= 0)
776 fetch_fp_regs (regcache, tid);
777 fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
778 if (tdep->ppc_ps_regnum != -1)
779 fetch_register (regcache, tid, tdep->ppc_ps_regnum);
780 if (tdep->ppc_cr_regnum != -1)
781 fetch_register (regcache, tid, tdep->ppc_cr_regnum);
782 if (tdep->ppc_lr_regnum != -1)
783 fetch_register (regcache, tid, tdep->ppc_lr_regnum);
784 if (tdep->ppc_ctr_regnum != -1)
785 fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
786 if (tdep->ppc_xer_regnum != -1)
787 fetch_register (regcache, tid, tdep->ppc_xer_regnum);
788 if (tdep->ppc_mq_regnum != -1)
789 fetch_register (regcache, tid, tdep->ppc_mq_regnum);
790 if (ppc_linux_trap_reg_p (gdbarch))
792 fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
793 fetch_register (regcache, tid, PPC_TRAP_REGNUM);
795 if (tdep->ppc_fpscr_regnum != -1)
796 fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
797 if (have_ptrace_getvrregs)
798 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
799 fetch_altivec_registers (regcache, tid);
800 if (have_ptrace_getsetvsxregs)
801 if (tdep->ppc_vsr0_upper_regnum != -1)
802 fetch_vsx_registers (regcache, tid);
803 if (tdep->ppc_ev0_upper_regnum >= 0)
804 fetch_spe_register (regcache, tid, -1);
807 /* Fetch registers from the child process. Fetch all registers if
808 regno == -1, otherwise fetch all general registers or all floating
809 point registers depending upon the value of regno. */
811 ppc_linux_fetch_inferior_registers (struct target_ops *ops,
812 struct regcache *regcache, int regno)
814 /* Overload thread id onto process id. */
815 int tid = ptid_get_lwp (inferior_ptid);
817 /* No thread id, just use process id. */
819 tid = ptid_get_pid (inferior_ptid);
822 fetch_ppc_registers (regcache, tid);
824 fetch_register (regcache, tid, regno);
827 /* Store one VSX register. */
829 store_vsx_register (const struct regcache *regcache, int tid, int regno)
832 gdb_vsxregset_t regs;
833 struct gdbarch *gdbarch = get_regcache_arch (regcache);
834 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
835 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
837 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
842 have_ptrace_getsetvsxregs = 0;
845 perror_with_name (_("Unable to fetch VSX register"));
848 regcache_raw_collect (regcache, regno, regs +
849 (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
851 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s);
853 perror_with_name (_("Unable to store VSX register"));
856 /* Store one register. */
858 store_altivec_register (const struct regcache *regcache, int tid, int regno)
863 struct gdbarch *gdbarch = get_regcache_arch (regcache);
864 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
865 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
867 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
872 have_ptrace_getvrregs = 0;
875 perror_with_name (_("Unable to fetch AltiVec register"));
878 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
879 long on the hardware. */
880 if (regno == (tdep->ppc_vrsave_regnum - 1))
881 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
883 regcache_raw_collect (regcache, regno,
885 - tdep->ppc_vr0_regnum) * vrregsize + offset);
887 ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s);
889 perror_with_name (_("Unable to store AltiVec register"));
892 /* Assuming TID referrs to an SPE process, set the top halves of TID's
893 general-purpose registers and its SPE-specific registers to the
894 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
897 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
898 PTRACE_SETEVRREGS requests are supported is isolated here, and in
899 get_spe_registers. */
901 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
903 if (have_ptrace_getsetevrregs)
905 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
909 /* EIO means that the PTRACE_SETEVRREGS request isn't
910 supported; we fail silently, and don't try the call
913 have_ptrace_getsetevrregs = 0;
915 /* Anything else needs to be reported. */
916 perror_with_name (_("Unable to set SPE registers"));
921 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
922 If REGNO is -1, write the values of all the SPE-specific
925 store_spe_register (const struct regcache *regcache, int tid, int regno)
927 struct gdbarch *gdbarch = get_regcache_arch (regcache);
928 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
929 struct gdb_evrregset_t evrregs;
931 gdb_assert (sizeof (evrregs.evr[0])
932 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
933 gdb_assert (sizeof (evrregs.acc)
934 == register_size (gdbarch, tdep->ppc_acc_regnum));
935 gdb_assert (sizeof (evrregs.spefscr)
936 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
939 /* Since we're going to write out every register, the code below
940 should store to every field of evrregs; if that doesn't happen,
941 make it obvious by initializing it with suspicious values. */
942 memset (&evrregs, 42, sizeof (evrregs));
944 /* We can only read and write the entire EVR register set at a
945 time, so to write just a single register, we do a
946 read-modify-write maneuver. */
947 get_spe_registers (tid, &evrregs);
953 for (i = 0; i < ppc_num_gprs; i++)
954 regcache_raw_collect (regcache,
955 tdep->ppc_ev0_upper_regnum + i,
958 else if (tdep->ppc_ev0_upper_regnum <= regno
959 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
960 regcache_raw_collect (regcache, regno,
961 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
964 || regno == tdep->ppc_acc_regnum)
965 regcache_raw_collect (regcache,
966 tdep->ppc_acc_regnum,
970 || regno == tdep->ppc_spefscr_regnum)
971 regcache_raw_collect (regcache,
972 tdep->ppc_spefscr_regnum,
975 /* Write back the modified register set. */
976 set_spe_registers (tid, &evrregs);
980 store_register (const struct regcache *regcache, int tid, int regno)
982 struct gdbarch *gdbarch = get_regcache_arch (regcache);
983 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
984 /* This isn't really an address. But ptrace thinks of it as one. */
985 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
987 size_t bytes_to_transfer;
988 gdb_byte buf[MAX_REGISTER_SIZE];
990 if (altivec_register_p (gdbarch, regno))
992 store_altivec_register (regcache, tid, regno);
995 if (vsx_register_p (gdbarch, regno))
997 store_vsx_register (regcache, tid, regno);
1000 else if (spe_register_p (gdbarch, regno))
1002 store_spe_register (regcache, tid, regno);
1009 /* First collect the register. Keep in mind that the regcache's
1010 idea of the register's size may not be a multiple of sizeof
1012 memset (buf, 0, sizeof buf);
1013 bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
1014 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1016 /* Little-endian values always sit at the left end of the buffer. */
1017 regcache_raw_collect (regcache, regno, buf);
1019 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1021 /* Big-endian values sit at the right end of the buffer. */
1022 size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
1023 regcache_raw_collect (regcache, regno, buf + padding);
1026 for (i = 0; i < bytes_to_transfer; i += sizeof (long))
1030 memcpy (&l, &buf[i], sizeof (l));
1032 ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
1033 regaddr += sizeof (long);
1036 && (regno == tdep->ppc_fpscr_regnum
1037 || regno == PPC_ORIG_R3_REGNUM
1038 || regno == PPC_TRAP_REGNUM))
1040 /* Some older kernel versions don't allow fpscr, orig_r3
1041 or trap to be written. */
1048 xsnprintf (message, sizeof (message), "writing register %s (#%d)",
1049 gdbarch_register_name (gdbarch, regno), regno);
1050 perror_with_name (message);
1056 fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
1059 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1060 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1061 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
1063 for (i = 0; i < ppc_num_vshrs; i++)
1064 regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
1065 *vsxregsetp + i * vsxregsize);
1069 fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
1072 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1073 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1074 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
1075 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
1076 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
1078 for (i = 0; i < num_of_vrregs; i++)
1080 /* The last 2 registers of this set are only 32 bit long, not
1081 128, but only VSCR is fetched as a 16 bytes quantity. */
1082 if (i == (num_of_vrregs - 2))
1083 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1084 *vrregsetp + i * vrregsize + offset);
1086 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1087 *vrregsetp + i * vrregsize);
1092 store_vsx_registers (const struct regcache *regcache, int tid)
1095 gdb_vsxregset_t regs;
1097 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
1102 have_ptrace_getsetvsxregs = 0;
1105 perror_with_name (_("Couldn't get VSX registers"));
1108 fill_vsxregset (regcache, ®s);
1110 if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0)
1111 perror_with_name (_("Couldn't write VSX registers"));
1115 store_altivec_registers (const struct regcache *regcache, int tid)
1118 gdb_vrregset_t regs;
1120 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
1125 have_ptrace_getvrregs = 0;
1128 perror_with_name (_("Couldn't get AltiVec registers"));
1131 fill_vrregset (regcache, ®s);
1133 if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0)
1134 perror_with_name (_("Couldn't write AltiVec registers"));
1137 /* This function actually issues the request to ptrace, telling
1138 it to store all general-purpose registers present in the specified
1141 If the ptrace request does not exist, this function returns 0
1142 and properly sets the have_ptrace_* flag. If the request fails,
1143 this function calls perror_with_name. Otherwise, if the request
1144 succeeds, then the regcache is stored and 1 is returned. */
1146 store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
1148 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1149 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1150 gdb_gregset_t gregset;
1152 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
1156 have_ptrace_getsetregs = 0;
1159 perror_with_name (_("Couldn't get general-purpose registers."));
1162 fill_gregset (regcache, &gregset, regno);
1164 if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
1168 have_ptrace_getsetregs = 0;
1171 perror_with_name (_("Couldn't set general-purpose registers."));
1177 /* This is a wrapper for the store_all_gp_regs function. It is
1178 responsible for verifying if this target has the ptrace request
1179 that can be used to store all general-purpose registers at one
1180 shot. If it doesn't, then we should store them using the
1181 old-fashioned way, which is to iterate over the registers and
1182 store them one by one. */
1184 store_gp_regs (const struct regcache *regcache, int tid, int regno)
1186 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1187 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1190 if (have_ptrace_getsetregs)
1191 if (store_all_gp_regs (regcache, tid, regno))
1194 /* If we hit this point, it doesn't really matter which
1195 architecture we are using. We just need to store the
1196 registers in the "old-fashioned way". */
1197 for (i = 0; i < ppc_num_gprs; i++)
1198 store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
1201 /* This function actually issues the request to ptrace, telling
1202 it to store all floating-point registers present in the specified
1205 If the ptrace request does not exist, this function returns 0
1206 and properly sets the have_ptrace_* flag. If the request fails,
1207 this function calls perror_with_name. Otherwise, if the request
1208 succeeds, then the regcache is stored and 1 is returned. */
1210 store_all_fp_regs (const struct regcache *regcache, int tid, int regno)
1212 gdb_fpregset_t fpregs;
1214 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
1218 have_ptrace_getsetfpregs = 0;
1221 perror_with_name (_("Couldn't get floating-point registers."));
1224 fill_fpregset (regcache, &fpregs, regno);
1226 if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
1230 have_ptrace_getsetfpregs = 0;
1233 perror_with_name (_("Couldn't set floating-point registers."));
1239 /* This is a wrapper for the store_all_fp_regs function. It is
1240 responsible for verifying if this target has the ptrace request
1241 that can be used to store all floating-point registers at one
1242 shot. If it doesn't, then we should store them using the
1243 old-fashioned way, which is to iterate over the registers and
1244 store them one by one. */
1246 store_fp_regs (const struct regcache *regcache, int tid, int regno)
1248 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1252 if (have_ptrace_getsetfpregs)
1253 if (store_all_fp_regs (regcache, tid, regno))
1256 /* If we hit this point, it doesn't really matter which
1257 architecture we are using. We just need to store the
1258 registers in the "old-fashioned way". */
1259 for (i = 0; i < ppc_num_fprs; i++)
1260 store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
1264 store_ppc_registers (const struct regcache *regcache, int tid)
1267 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1268 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1270 store_gp_regs (regcache, tid, -1);
1271 if (tdep->ppc_fp0_regnum >= 0)
1272 store_fp_regs (regcache, tid, -1);
1273 store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
1274 if (tdep->ppc_ps_regnum != -1)
1275 store_register (regcache, tid, tdep->ppc_ps_regnum);
1276 if (tdep->ppc_cr_regnum != -1)
1277 store_register (regcache, tid, tdep->ppc_cr_regnum);
1278 if (tdep->ppc_lr_regnum != -1)
1279 store_register (regcache, tid, tdep->ppc_lr_regnum);
1280 if (tdep->ppc_ctr_regnum != -1)
1281 store_register (regcache, tid, tdep->ppc_ctr_regnum);
1282 if (tdep->ppc_xer_regnum != -1)
1283 store_register (regcache, tid, tdep->ppc_xer_regnum);
1284 if (tdep->ppc_mq_regnum != -1)
1285 store_register (regcache, tid, tdep->ppc_mq_regnum);
1286 if (tdep->ppc_fpscr_regnum != -1)
1287 store_register (regcache, tid, tdep->ppc_fpscr_regnum);
1288 if (ppc_linux_trap_reg_p (gdbarch))
1290 store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1291 store_register (regcache, tid, PPC_TRAP_REGNUM);
1293 if (have_ptrace_getvrregs)
1294 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1295 store_altivec_registers (regcache, tid);
1296 if (have_ptrace_getsetvsxregs)
1297 if (tdep->ppc_vsr0_upper_regnum != -1)
1298 store_vsx_registers (regcache, tid);
1299 if (tdep->ppc_ev0_upper_regnum >= 0)
1300 store_spe_register (regcache, tid, -1);
1303 /* Fetch the AT_HWCAP entry from the aux vector. */
1304 static unsigned long
1305 ppc_linux_get_hwcap (void)
1309 if (target_auxv_search (¤t_target, AT_HWCAP, &field))
1310 return (unsigned long) field;
1315 /* The cached DABR value, to install in new threads.
1316 This variable is used when the PowerPC HWDEBUG ptrace
1317 interface is not available. */
1318 static long saved_dabr_value;
1320 /* Global structure that will store information about the available
1321 features provided by the PowerPC HWDEBUG ptrace interface. */
1322 static struct ppc_debug_info hwdebug_info;
1324 /* Global variable that holds the maximum number of slots that the
1325 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1327 static size_t max_slots_number = 0;
1329 struct hw_break_tuple
1332 struct ppc_hw_breakpoint *hw_break;
1335 /* This is an internal VEC created to store information about *points inserted
1336 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1338 typedef struct thread_points
1340 /* The TID to which this *point relates. */
1342 /* Information about the *point, such as its address, type, etc.
1344 Each element inside this vector corresponds to a hardware
1345 breakpoint or watchpoint in the thread represented by TID. The maximum
1346 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1347 the tuple is NULL, then the position in the vector is free. */
1348 struct hw_break_tuple *hw_breaks;
1350 DEF_VEC_P (thread_points_p);
1352 VEC(thread_points_p) *ppc_threads = NULL;
1354 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1356 #define PPC_DEBUG_CURRENT_VERSION 1
1358 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1360 have_ptrace_hwdebug_interface (void)
1362 static int have_ptrace_hwdebug_interface = -1;
1364 if (have_ptrace_hwdebug_interface == -1)
1368 tid = ptid_get_lwp (inferior_ptid);
1370 tid = ptid_get_pid (inferior_ptid);
1372 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1373 if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0)
1375 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1376 provides any supported feature. */
1377 if (hwdebug_info.features != 0)
1379 have_ptrace_hwdebug_interface = 1;
1380 max_slots_number = hwdebug_info.num_instruction_bps
1381 + hwdebug_info.num_data_bps
1382 + hwdebug_info.num_condition_regs;
1383 return have_ptrace_hwdebug_interface;
1386 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1387 have_ptrace_hwdebug_interface = 0;
1388 memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info));
1391 return have_ptrace_hwdebug_interface;
1395 ppc_linux_can_use_hw_breakpoint (struct target_ops *self,
1396 int type, int cnt, int ot)
1398 int total_hw_wp, total_hw_bp;
1400 if (have_ptrace_hwdebug_interface ())
1402 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1403 available hardware watchpoints and breakpoints is stored at the
1404 hwdebug_info struct. */
1405 total_hw_bp = hwdebug_info.num_instruction_bps;
1406 total_hw_wp = hwdebug_info.num_data_bps;
1410 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1411 consider having 1 hardware watchpoint and no hardware breakpoints. */
1416 if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
1417 || type == bp_access_watchpoint || type == bp_watchpoint)
1419 if (cnt + ot > total_hw_wp)
1422 else if (type == bp_hardware_breakpoint)
1424 if (total_hw_bp == 0)
1426 /* No hardware breakpoint support. */
1429 if (cnt > total_hw_bp)
1433 if (!have_ptrace_hwdebug_interface ())
1436 ptid_t ptid = inferior_ptid;
1438 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1439 and whether the target has DABR. If either answer is no, the
1440 ptrace call will return -1. Fail in that case. */
1441 tid = ptid_get_lwp (ptid);
1443 tid = ptid_get_pid (ptid);
1445 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1453 ppc_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
1454 CORE_ADDR addr, int len)
1456 /* Handle sub-8-byte quantities. */
1460 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1461 restrictions for watchpoints in the processors. In that case, we use that
1462 information to determine the hardcoded watchable region for
1464 if (have_ptrace_hwdebug_interface ())
1467 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1468 watchpoints and can watch any access within an arbitrary memory
1469 region. This is useful to watch arrays and structs, for instance. It
1470 takes two hardware watchpoints though. */
1472 && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE
1473 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1475 /* Check if the processor provides DAWR interface. */
1476 if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR)
1477 /* DAWR interface allows to watch up to 512 byte wide ranges which
1478 can't cross a 512 byte boundary. */
1481 region_size = hwdebug_info.data_bp_alignment;
1482 /* Server processors provide one hardware watchpoint and addr+len should
1483 fall in the watchable region provided by the ptrace interface. */
1485 && (addr + len > (addr & ~(region_size - 1)) + region_size))
1488 /* addr+len must fall in the 8 byte watchable region for DABR-based
1489 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1490 ptrace interface, DAC-based processors (i.e., embedded processors) will
1491 use addresses aligned to 4-bytes due to the way the read/write flags are
1492 passed in the old ptrace interface. */
1493 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1494 && (addr + len) > (addr & ~3) + 4)
1495 || (addr + len) > (addr & ~7) + 8)
1501 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1503 hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
1505 return (a->trigger_type == b->trigger_type
1506 && a->addr_mode == b->addr_mode
1507 && a->condition_mode == b->condition_mode
1508 && a->addr == b->addr
1509 && a->addr2 == b->addr2
1510 && a->condition_value == b->condition_value);
1513 /* This function can be used to retrieve a thread_points by the TID of the
1514 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1515 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1516 provided TID will be created and returned. */
1517 static struct thread_points *
1518 hwdebug_find_thread_points_by_tid (int tid, int alloc_new)
1521 struct thread_points *t;
1523 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
1529 /* Do we need to allocate a new point_item
1530 if the wanted one does not exist? */
1533 t = xmalloc (sizeof (struct thread_points));
1535 = xzalloc (max_slots_number * sizeof (struct hw_break_tuple));
1537 VEC_safe_push (thread_points_p, ppc_threads, t);
1543 /* This function is a generic wrapper that is responsible for inserting a
1544 *point (i.e., calling `ptrace' in order to issue the request to the
1545 kernel) and registering it internally in GDB. */
1547 hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid)
1551 struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint));
1552 struct hw_break_tuple *hw_breaks;
1553 struct cleanup *c = make_cleanup (xfree, p);
1554 struct thread_points *t;
1555 struct hw_break_tuple *tuple;
1557 memcpy (p, b, sizeof (struct ppc_hw_breakpoint));
1560 slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p);
1562 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1564 /* Everything went fine, so we have to register this *point. */
1565 t = hwdebug_find_thread_points_by_tid (tid, 1);
1566 gdb_assert (t != NULL);
1567 hw_breaks = t->hw_breaks;
1569 /* Find a free element in the hw_breaks vector. */
1570 for (i = 0; i < max_slots_number; i++)
1571 if (hw_breaks[i].hw_break == NULL)
1573 hw_breaks[i].slot = slot;
1574 hw_breaks[i].hw_break = p;
1578 gdb_assert (i != max_slots_number);
1580 discard_cleanups (c);
1583 /* This function is a generic wrapper that is responsible for removing a
1584 *point (i.e., calling `ptrace' in order to issue the request to the
1585 kernel), and unregistering it internally at GDB. */
1587 hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid)
1590 struct hw_break_tuple *hw_breaks;
1591 struct thread_points *t;
1593 t = hwdebug_find_thread_points_by_tid (tid, 0);
1594 gdb_assert (t != NULL);
1595 hw_breaks = t->hw_breaks;
1597 for (i = 0; i < max_slots_number; i++)
1598 if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b))
1601 gdb_assert (i != max_slots_number);
1603 /* We have to ignore ENOENT errors because the kernel implements hardware
1604 breakpoints/watchpoints as "one-shot", that is, they are automatically
1605 deleted when hit. */
1607 if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
1608 if (errno != ENOENT)
1609 perror_with_name (_("Unexpected error deleting "
1610 "breakpoint or watchpoint"));
1612 xfree (hw_breaks[i].hw_break);
1613 hw_breaks[i].hw_break = NULL;
1616 /* Return the number of registers needed for a ranged breakpoint. */
1619 ppc_linux_ranged_break_num_registers (struct target_ops *target)
1621 return ((have_ptrace_hwdebug_interface ()
1622 && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)?
1626 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1627 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1630 ppc_linux_insert_hw_breakpoint (struct target_ops *self,
1631 struct gdbarch *gdbarch,
1632 struct bp_target_info *bp_tgt)
1634 struct lwp_info *lp;
1635 struct ppc_hw_breakpoint p;
1637 if (!have_ptrace_hwdebug_interface ())
1640 p.version = PPC_DEBUG_CURRENT_VERSION;
1641 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1642 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1643 p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address);
1644 p.condition_value = 0;
1648 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1650 /* The breakpoint will trigger if the address of the instruction is
1651 within the defined range, as follows: p.addr <= address < p.addr2. */
1652 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1656 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1661 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1667 ppc_linux_remove_hw_breakpoint (struct target_ops *self,
1668 struct gdbarch *gdbarch,
1669 struct bp_target_info *bp_tgt)
1671 struct lwp_info *lp;
1672 struct ppc_hw_breakpoint p;
1674 if (!have_ptrace_hwdebug_interface ())
1677 p.version = PPC_DEBUG_CURRENT_VERSION;
1678 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1679 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1680 p.addr = (uint64_t) bp_tgt->placed_address;
1681 p.condition_value = 0;
1685 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1687 /* The breakpoint will trigger if the address of the instruction is within
1688 the defined range, as follows: p.addr <= address < p.addr2. */
1689 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1693 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1698 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
1704 get_trigger_type (int rw)
1709 t = PPC_BREAKPOINT_TRIGGER_READ;
1710 else if (rw == hw_write)
1711 t = PPC_BREAKPOINT_TRIGGER_WRITE;
1713 t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
1718 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1719 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1720 or hw_access for an access watchpoint. Returns 0 on success and throws
1721 an error on failure. */
1724 ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1725 CORE_ADDR mask, int rw)
1727 struct lwp_info *lp;
1728 struct ppc_hw_breakpoint p;
1730 gdb_assert (have_ptrace_hwdebug_interface ());
1732 p.version = PPC_DEBUG_CURRENT_VERSION;
1733 p.trigger_type = get_trigger_type (rw);
1734 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1735 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1738 p.condition_value = 0;
1741 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1746 /* Remove a masked watchpoint at ADDR with the mask MASK.
1747 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1748 or hw_access for an access watchpoint. Returns 0 on success and throws
1749 an error on failure. */
1752 ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1753 CORE_ADDR mask, int rw)
1755 struct lwp_info *lp;
1756 struct ppc_hw_breakpoint p;
1758 gdb_assert (have_ptrace_hwdebug_interface ());
1760 p.version = PPC_DEBUG_CURRENT_VERSION;
1761 p.trigger_type = get_trigger_type (rw);
1762 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1763 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1766 p.condition_value = 0;
1769 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
1774 /* Check whether we have at least one free DVC register. */
1776 can_use_watchpoint_cond_accel (void)
1778 struct thread_points *p;
1779 int tid = ptid_get_lwp (inferior_ptid);
1780 int cnt = hwdebug_info.num_condition_regs, i;
1781 CORE_ADDR tmp_value;
1783 if (!have_ptrace_hwdebug_interface () || cnt == 0)
1786 p = hwdebug_find_thread_points_by_tid (tid, 0);
1790 for (i = 0; i < max_slots_number; i++)
1791 if (p->hw_breaks[i].hw_break != NULL
1792 && (p->hw_breaks[i].hw_break->condition_mode
1793 != PPC_BREAKPOINT_CONDITION_NONE))
1796 /* There are no available slots now. */
1804 /* Calculate the enable bits and the contents of the Data Value Compare
1805 debug register present in BookE processors.
1807 ADDR is the address to be watched, LEN is the length of watched data
1808 and DATA_VALUE is the value which will trigger the watchpoint.
1809 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1810 CONDITION_VALUE will hold the value which should be put in the
1813 calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
1814 uint32_t *condition_mode, uint64_t *condition_value)
1816 int i, num_byte_enable, align_offset, num_bytes_off_dvc,
1817 rightmost_enabled_byte;
1818 CORE_ADDR addr_end_data, addr_end_dvc;
1820 /* The DVC register compares bytes within fixed-length windows which
1821 are word-aligned, with length equal to that of the DVC register.
1822 We need to calculate where our watch region is relative to that
1823 window and enable comparison of the bytes which fall within it. */
1825 align_offset = addr % hwdebug_info.sizeof_condition;
1826 addr_end_data = addr + len;
1827 addr_end_dvc = (addr - align_offset
1828 + hwdebug_info.sizeof_condition);
1829 num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
1830 addr_end_data - addr_end_dvc : 0;
1831 num_byte_enable = len - num_bytes_off_dvc;
1832 /* Here, bytes are numbered from right to left. */
1833 rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
1834 addr_end_dvc - addr_end_data : 0;
1836 *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
1837 for (i = 0; i < num_byte_enable; i++)
1839 |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
1841 /* Now we need to match the position within the DVC of the comparison
1842 value with where the watch region is relative to the window
1843 (i.e., the ALIGN_OFFSET). */
1845 *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
1846 << rightmost_enabled_byte * 8);
1849 /* Return the number of memory locations that need to be accessed to
1850 evaluate the expression which generated the given value chain.
1851 Returns -1 if there's any register access involved, or if there are
1852 other kinds of values which are not acceptable in a condition
1853 expression (e.g., lval_computed or lval_internalvar). */
1855 num_memory_accesses (struct value *v)
1857 int found_memory_cnt = 0;
1858 struct value *head = v;
1860 /* The idea here is that evaluating an expression generates a series
1861 of values, one holding the value of every subexpression. (The
1862 expression a*b+c has five subexpressions: a, b, a*b, c, and
1863 a*b+c.) GDB's values hold almost enough information to establish
1864 the criteria given above --- they identify memory lvalues,
1865 register lvalues, computed values, etcetera. So we can evaluate
1866 the expression, and then scan the chain of values that leaves
1867 behind to determine the memory locations involved in the evaluation
1870 However, I don't think that the values returned by inferior
1871 function calls are special in any way. So this function may not
1872 notice that an expression contains an inferior function call.
1875 for (; v; v = value_next (v))
1877 /* Constants and values from the history are fine. */
1878 if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
1880 else if (VALUE_LVAL (v) == lval_memory)
1882 /* A lazy memory lvalue is one that GDB never needed to fetch;
1883 we either just used its address (e.g., `a' in `a.b') or
1884 we never needed it at all (e.g., `a' in `a,b'). */
1885 if (!value_lazy (v))
1888 /* Other kinds of values are not fine. */
1893 return found_memory_cnt;
1896 /* Verifies whether the expression COND can be implemented using the
1897 DVC (Data Value Compare) register in BookE processors. The expression
1898 must test the watch value for equality with a constant expression.
1899 If the function returns 1, DATA_VALUE will contain the constant against
1900 which the watch value should be compared and LEN will contain the size
1903 check_condition (CORE_ADDR watch_addr, struct expression *cond,
1904 CORE_ADDR *data_value, int *len)
1906 int pc = 1, num_accesses_left, num_accesses_right;
1907 struct value *left_val, *right_val, *left_chain, *right_chain;
1909 if (cond->elts[0].opcode != BINOP_EQUAL)
1912 fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
1913 num_accesses_left = num_memory_accesses (left_chain);
1915 if (left_val == NULL || num_accesses_left < 0)
1917 free_value_chain (left_chain);
1922 fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
1923 num_accesses_right = num_memory_accesses (right_chain);
1925 if (right_val == NULL || num_accesses_right < 0)
1927 free_value_chain (left_chain);
1928 free_value_chain (right_chain);
1933 if (num_accesses_left == 1 && num_accesses_right == 0
1934 && VALUE_LVAL (left_val) == lval_memory
1935 && value_address (left_val) == watch_addr)
1937 *data_value = value_as_long (right_val);
1939 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1940 the same type as the memory region referenced by LEFT_VAL. */
1941 *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
1943 else if (num_accesses_left == 0 && num_accesses_right == 1
1944 && VALUE_LVAL (right_val) == lval_memory
1945 && value_address (right_val) == watch_addr)
1947 *data_value = value_as_long (left_val);
1949 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1950 the same type as the memory region referenced by RIGHT_VAL. */
1951 *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
1955 free_value_chain (left_chain);
1956 free_value_chain (right_chain);
1961 free_value_chain (left_chain);
1962 free_value_chain (right_chain);
1967 /* Return non-zero if the target is capable of using hardware to evaluate
1968 the condition expression, thus only triggering the watchpoint when it is
1971 ppc_linux_can_accel_watchpoint_condition (struct target_ops *self,
1972 CORE_ADDR addr, int len, int rw,
1973 struct expression *cond)
1975 CORE_ADDR data_value;
1977 return (have_ptrace_hwdebug_interface ()
1978 && hwdebug_info.num_condition_regs > 0
1979 && check_condition (addr, cond, &data_value, &len));
1982 /* Set up P with the parameters necessary to request a watchpoint covering
1983 LEN bytes starting at ADDR and if possible with condition expression COND
1984 evaluated by hardware. INSERT tells if we are creating a request for
1985 inserting or removing the watchpoint. */
1988 create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
1989 int len, int rw, struct expression *cond,
1993 || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
1996 CORE_ADDR data_value;
1998 use_condition = (insert? can_use_watchpoint_cond_accel ()
1999 : hwdebug_info.num_condition_regs > 0);
2000 if (cond && use_condition && check_condition (addr, cond,
2002 calculate_dvc (addr, len, data_value, &p->condition_mode,
2003 &p->condition_value);
2006 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2007 p->condition_value = 0;
2010 p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
2015 p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
2016 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2017 p->condition_value = 0;
2019 /* The watchpoint will trigger if the address of the memory access is
2020 within the defined range, as follows: p->addr <= address < p->addr2.
2022 Note that the above sentence just documents how ptrace interprets
2023 its arguments; the watchpoint is set to watch the range defined by
2024 the user _inclusively_, as specified by the user interface. */
2025 p->addr2 = (uint64_t) addr + len;
2028 p->version = PPC_DEBUG_CURRENT_VERSION;
2029 p->trigger_type = get_trigger_type (rw);
2030 p->addr = (uint64_t) addr;
2034 ppc_linux_insert_watchpoint (struct target_ops *self,
2035 CORE_ADDR addr, int len, int rw,
2036 struct expression *cond)
2038 struct lwp_info *lp;
2041 if (have_ptrace_hwdebug_interface ())
2043 struct ppc_hw_breakpoint p;
2045 create_watchpoint_request (&p, addr, len, rw, cond, 1);
2048 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
2055 long read_mode, write_mode;
2057 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2059 /* PowerPC 440 requires only the read/write flags to be passed
2066 /* PowerPC 970 and other DABR-based processors are required to pass
2067 the Breakpoint Translation bit together with the flags. */
2072 dabr_value = addr & ~(read_mode | write_mode);
2076 /* Set read and translate bits. */
2077 dabr_value |= read_mode;
2080 /* Set write and translate bits. */
2081 dabr_value |= write_mode;
2084 /* Set read, write and translate bits. */
2085 dabr_value |= read_mode | write_mode;
2089 saved_dabr_value = dabr_value;
2092 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
2093 saved_dabr_value) < 0)
2103 ppc_linux_remove_watchpoint (struct target_ops *self,
2104 CORE_ADDR addr, int len, int rw,
2105 struct expression *cond)
2107 struct lwp_info *lp;
2110 if (have_ptrace_hwdebug_interface ())
2112 struct ppc_hw_breakpoint p;
2114 create_watchpoint_request (&p, addr, len, rw, cond, 0);
2117 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
2123 saved_dabr_value = 0;
2125 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
2126 saved_dabr_value) < 0)
2136 ppc_linux_new_thread (struct lwp_info *lp)
2138 int tid = ptid_get_lwp (lp->ptid);
2140 if (have_ptrace_hwdebug_interface ())
2143 struct thread_points *p;
2144 struct hw_break_tuple *hw_breaks;
2146 if (VEC_empty (thread_points_p, ppc_threads))
2149 /* Get a list of breakpoints from any thread. */
2150 p = VEC_last (thread_points_p, ppc_threads);
2151 hw_breaks = p->hw_breaks;
2153 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2154 for (i = 0; i < max_slots_number; i++)
2155 if (hw_breaks[i].hw_break)
2157 /* Older kernels did not make new threads inherit their parent
2158 thread's debug state, so we always clear the slot and replicate
2159 the debug state ourselves, ensuring compatibility with all
2162 /* The ppc debug resource accounting is done through "slots".
2163 Ask the kernel the deallocate this specific *point's slot. */
2164 ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
2166 hwdebug_insert_point (hw_breaks[i].hw_break, tid);
2170 ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
2174 ppc_linux_thread_exit (struct thread_info *tp, int silent)
2177 int tid = ptid_get_lwp (tp->ptid);
2178 struct hw_break_tuple *hw_breaks;
2179 struct thread_points *t = NULL, *p;
2181 if (!have_ptrace_hwdebug_interface ())
2184 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
2194 VEC_unordered_remove (thread_points_p, ppc_threads, i);
2196 hw_breaks = t->hw_breaks;
2198 for (i = 0; i < max_slots_number; i++)
2199 if (hw_breaks[i].hw_break)
2200 xfree (hw_breaks[i].hw_break);
2202 xfree (t->hw_breaks);
2207 ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
2211 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
2214 if (siginfo.si_signo != SIGTRAP
2215 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2218 if (have_ptrace_hwdebug_interface ())
2221 struct thread_points *t;
2222 struct hw_break_tuple *hw_breaks;
2223 /* The index (or slot) of the *point is passed in the si_errno field. */
2224 int slot = siginfo.si_errno;
2226 t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0);
2228 /* Find out if this *point is a hardware breakpoint.
2229 If so, we should return 0. */
2232 hw_breaks = t->hw_breaks;
2233 for (i = 0; i < max_slots_number; i++)
2234 if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
2235 && hw_breaks[i].hw_break->trigger_type
2236 == PPC_BREAKPOINT_TRIGGER_EXECUTE)
2241 *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
2246 ppc_linux_stopped_by_watchpoint (struct target_ops *ops)
2249 return ppc_linux_stopped_data_address (ops, &addr);
2253 ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
2255 CORE_ADDR start, int length)
2259 if (have_ptrace_hwdebug_interface ()
2260 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2261 return start <= addr && start + length >= addr;
2262 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2269 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2270 return start <= addr + mask && start + length - 1 >= addr;
2273 /* Return the number of registers needed for a masked hardware watchpoint. */
2276 ppc_linux_masked_watch_num_registers (struct target_ops *target,
2277 CORE_ADDR addr, CORE_ADDR mask)
2279 if (!have_ptrace_hwdebug_interface ()
2280 || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0)
2282 else if ((mask & 0xC0000000) != 0xC0000000)
2284 warning (_("The given mask covers kernel address space "
2285 "and cannot be used.\n"));
2294 ppc_linux_store_inferior_registers (struct target_ops *ops,
2295 struct regcache *regcache, int regno)
2297 /* Overload thread id onto process id. */
2298 int tid = ptid_get_lwp (inferior_ptid);
2300 /* No thread id, just use process id. */
2302 tid = ptid_get_pid (inferior_ptid);
2305 store_register (regcache, tid, regno);
2307 store_ppc_registers (regcache, tid);
2310 /* Functions for transferring registers between a gregset_t or fpregset_t
2311 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2312 by the ptrace interface, not the current program's ABI. Eg. if a
2313 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2314 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2317 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
2319 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2321 ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
2325 fill_gregset (const struct regcache *regcache,
2326 gdb_gregset_t *gregsetp, int regno)
2328 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2331 memset (gregsetp, 0, sizeof (*gregsetp));
2332 ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
2336 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
2338 const struct regset *regset = ppc_linux_fpregset ();
2340 ppc_supply_fpregset (regset, regcache, -1,
2341 fpregsetp, sizeof (*fpregsetp));
2345 fill_fpregset (const struct regcache *regcache,
2346 gdb_fpregset_t *fpregsetp, int regno)
2348 const struct regset *regset = ppc_linux_fpregset ();
2350 ppc_collect_fpregset (regset, regcache, regno,
2351 fpregsetp, sizeof (*fpregsetp));
2355 ppc_linux_target_wordsize (void)
2359 /* Check for 64-bit inferior process. This is the case when the host is
2360 64-bit, and in addition the top bit of the MSR register is set. */
2361 #ifdef __powerpc64__
2364 int tid = ptid_get_lwp (inferior_ptid);
2366 tid = ptid_get_pid (inferior_ptid);
2369 msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
2370 if (errno == 0 && msr < 0)
2378 ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
2379 gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
2381 int sizeof_auxv_field = ppc_linux_target_wordsize ();
2382 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
2383 gdb_byte *ptr = *readptr;
2388 if (endptr - ptr < sizeof_auxv_field * 2)
2391 *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2392 ptr += sizeof_auxv_field;
2393 *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2394 ptr += sizeof_auxv_field;
2400 static const struct target_desc *
2401 ppc_linux_read_description (struct target_ops *ops)
2408 int tid = ptid_get_lwp (inferior_ptid);
2410 tid = ptid_get_pid (inferior_ptid);
2412 if (have_ptrace_getsetevrregs)
2414 struct gdb_evrregset_t evrregset;
2416 if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
2417 return tdesc_powerpc_e500l;
2419 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2420 Anything else needs to be reported. */
2421 else if (errno != EIO)
2422 perror_with_name (_("Unable to fetch SPE registers"));
2425 if (have_ptrace_getsetvsxregs)
2427 gdb_vsxregset_t vsxregset;
2429 if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
2432 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2433 Anything else needs to be reported. */
2434 else if (errno != EIO)
2435 perror_with_name (_("Unable to fetch VSX registers"));
2438 if (have_ptrace_getvrregs)
2440 gdb_vrregset_t vrregset;
2442 if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
2445 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2446 Anything else needs to be reported. */
2447 else if (errno != EIO)
2448 perror_with_name (_("Unable to fetch AltiVec registers"));
2451 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2452 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2453 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2454 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2455 half of the register are for Decimal Floating Point, we check if that
2456 feature is available to decide the size of the FPSCR. */
2457 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP)
2460 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL)
2463 if (ppc_linux_target_wordsize () == 8)
2466 return tdesc_powerpc_cell64l;
2468 return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
2471 ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
2473 return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
2477 return tdesc_powerpc_cell32l;
2479 return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
2481 return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
2483 return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l;
2486 void _initialize_ppc_linux_nat (void);
2489 _initialize_ppc_linux_nat (void)
2491 struct target_ops *t;
2493 /* Fill in the generic GNU/Linux methods. */
2494 t = linux_target ();
2496 /* Add our register access methods. */
2497 t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
2498 t->to_store_registers = ppc_linux_store_inferior_registers;
2500 /* Add our breakpoint/watchpoint methods. */
2501 t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint;
2502 t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint;
2503 t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint;
2504 t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
2505 t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
2506 t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
2507 t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint;
2508 t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint;
2509 t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
2510 t->to_stopped_data_address = ppc_linux_stopped_data_address;
2511 t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
2512 t->to_can_accel_watchpoint_condition
2513 = ppc_linux_can_accel_watchpoint_condition;
2514 t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers;
2515 t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers;
2517 t->to_read_description = ppc_linux_read_description;
2518 t->to_auxv_parse = ppc_linux_auxv_parse;
2520 observer_attach_thread_exit (ppc_linux_thread_exit);
2522 /* Register the target. */
2523 linux_nat_add_target (t);
2524 linux_nat_set_new_thread (t, ppc_linux_new_thread);