1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdbthread.h"
28 #include "linux-nat.h"
31 #include <sys/types.h>
34 #include <sys/ioctl.h>
37 #include <sys/procfs.h>
38 #include <sys/ptrace.h>
40 /* Prototypes for supply_gregset etc. */
43 #include "ppc-linux-tdep.h"
45 /* Required when using the AUXV. */
46 #include "elf/common.h"
49 /* This sometimes isn't defined. */
57 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
58 If they aren't, we can provide them ourselves (their values are fixed
59 because they are part of the kernel ABI). They are used in the AT_HWCAP
61 #ifndef PPC_FEATURE_CELL
62 #define PPC_FEATURE_CELL 0x00010000
64 #ifndef PPC_FEATURE_BOOKE
65 #define PPC_FEATURE_BOOKE 0x00008000
67 #ifndef PPC_FEATURE_HAS_DFP
68 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
71 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
72 configure time check. Some older glibc's (for instance 2.2.1)
73 don't have a specific powerpc version of ptrace.h, and fall back on
74 a generic one. In such cases, sys/ptrace.h defines
75 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
76 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
77 PTRACE_SETVRREGS to be. This also makes a configury check pretty
80 /* These definitions should really come from the glibc header files,
81 but Glibc doesn't know about the vrregs yet. */
82 #ifndef PTRACE_GETVRREGS
83 #define PTRACE_GETVRREGS 18
84 #define PTRACE_SETVRREGS 19
87 /* PTRACE requests for POWER7 VSX registers. */
88 #ifndef PTRACE_GETVSXREGS
89 #define PTRACE_GETVSXREGS 27
90 #define PTRACE_SETVSXREGS 28
93 /* Similarly for the ptrace requests for getting / setting the SPE
94 registers (ev0 -- ev31, acc, and spefscr). See the description of
95 gdb_evrregset_t for details. */
96 #ifndef PTRACE_GETEVRREGS
97 #define PTRACE_GETEVRREGS 20
98 #define PTRACE_SETEVRREGS 21
101 /* Similarly for the hardware watchpoint support. These requests are used
102 when the PowerPC HWDEBUG ptrace interface is not available. */
103 #ifndef PTRACE_GET_DEBUGREG
104 #define PTRACE_GET_DEBUGREG 25
106 #ifndef PTRACE_SET_DEBUGREG
107 #define PTRACE_SET_DEBUGREG 26
109 #ifndef PTRACE_GETSIGINFO
110 #define PTRACE_GETSIGINFO 0x4202
113 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
114 available. It exposes the debug facilities of PowerPC processors, as well
115 as additional features of BookE processors, such as ranged breakpoints and
116 watchpoints and hardware-accelerated condition evaluation. */
117 #ifndef PPC_PTRACE_GETHWDBGINFO
119 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
120 ptrace interface is not present in ptrace.h, so we'll have to pretty much
121 include it all here so that the code at least compiles on older systems. */
122 #define PPC_PTRACE_GETHWDBGINFO 0x89
123 #define PPC_PTRACE_SETHWDEBUG 0x88
124 #define PPC_PTRACE_DELHWDEBUG 0x87
126 struct ppc_debug_info
128 uint32_t version; /* Only version 1 exists to date. */
129 uint32_t num_instruction_bps;
130 uint32_t num_data_bps;
131 uint32_t num_condition_regs;
132 uint32_t data_bp_alignment;
133 uint32_t sizeof_condition; /* size of the DVC register. */
137 /* Features will have bits indicating whether there is support for: */
138 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
139 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
140 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
141 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
143 struct ppc_hw_breakpoint
145 uint32_t version; /* currently, version must be 1 */
146 uint32_t trigger_type; /* only some combinations allowed */
147 uint32_t addr_mode; /* address match mode */
148 uint32_t condition_mode; /* break/watchpoint condition flags */
149 uint64_t addr; /* break/watchpoint address */
150 uint64_t addr2; /* range end or mask */
151 uint64_t condition_value; /* contents of the DVC register */
155 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
156 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
157 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
158 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
161 #define PPC_BREAKPOINT_MODE_EXACT 0x0
162 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
163 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
164 #define PPC_BREAKPOINT_MODE_MASK 0x3
166 /* Condition mode. */
167 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
168 #define PPC_BREAKPOINT_CONDITION_AND 0x1
169 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
170 #define PPC_BREAKPOINT_CONDITION_OR 0x2
171 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
172 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
173 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
174 #define PPC_BREAKPOINT_CONDITION_BE(n) \
175 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
176 #endif /* PPC_PTRACE_GETHWDBGINFO */
178 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
179 watchpoint (up to 512 bytes). */
180 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
181 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
182 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
184 /* Similarly for the general-purpose (gp0 -- gp31)
185 and floating-point registers (fp0 -- fp31). */
186 #ifndef PTRACE_GETREGS
187 #define PTRACE_GETREGS 12
189 #ifndef PTRACE_SETREGS
190 #define PTRACE_SETREGS 13
192 #ifndef PTRACE_GETFPREGS
193 #define PTRACE_GETFPREGS 14
195 #ifndef PTRACE_SETFPREGS
196 #define PTRACE_SETFPREGS 15
199 /* This oddity is because the Linux kernel defines elf_vrregset_t as
200 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
201 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
202 the vrsave as an extra 4 bytes at the end. I opted for creating a
203 flat array of chars, so that it is easier to manipulate for gdb.
205 There are 32 vector registers 16 bytes longs, plus a VSCR register
206 which is only 4 bytes long, but is fetched as a 16 bytes
207 quantity. Up to here we have the elf_vrregset_t structure.
208 Appended to this there is space for the VRSAVE register: 4 bytes.
209 Even though this vrsave register is not included in the regset
210 typedef, it is handled by the ptrace requests.
212 Note that GNU/Linux doesn't support little endian PPC hardware,
213 therefore the offset at which the real value of the VSCR register
214 is located will be always 12 bytes.
216 The layout is like this (where x is the actual value of the vscr reg): */
220 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
221 <-------> <-------><-------><->
226 #define SIZEOF_VRREGS 33*16+4
228 typedef char gdb_vrregset_t[SIZEOF_VRREGS];
230 /* This is the layout of the POWER7 VSX registers and the way they overlap
231 with the existing FPR and VMX registers.
233 VSR doubleword 0 VSR doubleword 1
234 ----------------------------------------------------------------
236 ----------------------------------------------------------------
238 ----------------------------------------------------------------
241 ----------------------------------------------------------------
242 VSR[30] | FPR[30] | |
243 ----------------------------------------------------------------
244 VSR[31] | FPR[31] | |
245 ----------------------------------------------------------------
247 ----------------------------------------------------------------
249 ----------------------------------------------------------------
252 ----------------------------------------------------------------
254 ----------------------------------------------------------------
256 ----------------------------------------------------------------
258 VSX has 64 128bit registers. The first 32 registers overlap with
259 the FP registers (doubleword 0) and hence extend them with additional
260 64 bits (doubleword 1). The other 32 regs overlap with the VMX
262 #define SIZEOF_VSXREGS 32*8
264 typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
266 /* On PPC processors that support the Signal Processing Extension
267 (SPE) APU, the general-purpose registers are 64 bits long.
268 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
269 ptrace calls only access the lower half of each register, to allow
270 them to behave the same way they do on non-SPE systems. There's a
271 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
272 read and write the top halves of all the general-purpose registers
273 at once, along with some SPE-specific registers.
275 GDB itself continues to claim the general-purpose registers are 32
276 bits long. It has unnamed raw registers that hold the upper halves
277 of the gprs, and the full 64-bit SIMD views of the registers,
278 'ev0' -- 'ev31', are pseudo-registers that splice the top and
279 bottom halves together.
281 This is the structure filled in by PTRACE_GETEVRREGS and written to
282 the inferior's registers by PTRACE_SETEVRREGS. */
283 struct gdb_evrregset_t
285 unsigned long evr[32];
286 unsigned long long acc;
287 unsigned long spefscr;
290 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
291 PTRACE_SETVSXREGS requests, for reading and writing the VSX
292 POWER7 registers 0 through 31. Zero if we've tried one of them and
293 gotten an error. Note that VSX registers 32 through 63 overlap
294 with VR registers 0 through 31. */
295 int have_ptrace_getsetvsxregs = 1;
297 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
298 PTRACE_SETVRREGS requests, for reading and writing the Altivec
299 registers. Zero if we've tried one of them and gotten an
301 int have_ptrace_getvrregs = 1;
303 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
304 PTRACE_SETEVRREGS requests, for reading and writing the SPE
305 registers. Zero if we've tried one of them and gotten an
307 int have_ptrace_getsetevrregs = 1;
309 /* Non-zero if our kernel may support the PTRACE_GETREGS and
310 PTRACE_SETREGS requests, for reading and writing the
311 general-purpose registers. Zero if we've tried one of
312 them and gotten an error. */
313 int have_ptrace_getsetregs = 1;
315 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
316 PTRACE_SETFPREGS requests, for reading and writing the
317 floating-pointers registers. Zero if we've tried one of
318 them and gotten an error. */
319 int have_ptrace_getsetfpregs = 1;
322 /* registers layout, as presented by the ptrace interface:
323 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
324 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
325 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
326 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
327 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
328 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
329 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
330 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
331 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
332 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
333 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
334 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
335 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
339 ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
342 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
343 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
344 interface, and not the wordsize of the program's ABI. */
345 int wordsize = sizeof (long);
347 /* General purpose registers occupy 1 slot each in the buffer. */
348 if (regno >= tdep->ppc_gp0_regnum
349 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
350 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
352 /* Floating point regs: eight bytes each in both 32- and 64-bit
353 ptrace interfaces. Thus, two slots each in 32-bit interface, one
354 slot each in 64-bit interface. */
355 if (tdep->ppc_fp0_regnum >= 0
356 && regno >= tdep->ppc_fp0_regnum
357 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
358 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
360 /* UISA special purpose registers: 1 slot each. */
361 if (regno == gdbarch_pc_regnum (gdbarch))
362 u_addr = PT_NIP * wordsize;
363 if (regno == tdep->ppc_lr_regnum)
364 u_addr = PT_LNK * wordsize;
365 if (regno == tdep->ppc_cr_regnum)
366 u_addr = PT_CCR * wordsize;
367 if (regno == tdep->ppc_xer_regnum)
368 u_addr = PT_XER * wordsize;
369 if (regno == tdep->ppc_ctr_regnum)
370 u_addr = PT_CTR * wordsize;
372 if (regno == tdep->ppc_mq_regnum)
373 u_addr = PT_MQ * wordsize;
375 if (regno == tdep->ppc_ps_regnum)
376 u_addr = PT_MSR * wordsize;
377 if (regno == PPC_ORIG_R3_REGNUM)
378 u_addr = PT_ORIG_R3 * wordsize;
379 if (regno == PPC_TRAP_REGNUM)
380 u_addr = PT_TRAP * wordsize;
381 if (tdep->ppc_fpscr_regnum >= 0
382 && regno == tdep->ppc_fpscr_regnum)
384 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
385 kernel headers incorrectly contained the 32-bit definition of
386 PT_FPSCR. For the 32-bit definition, floating-point
387 registers occupy two 32-bit "slots", and the FPSCR lives in
388 the second half of such a slot-pair (hence +1). For 64-bit,
389 the FPSCR instead occupies the full 64-bit 2-word-slot and
390 hence no adjustment is necessary. Hack around this. */
391 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
392 u_addr = (48 + 32) * wordsize;
393 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
394 slot and not just its second word. The PT_FPSCR supplied when
395 GDB is compiled as a 32-bit app doesn't reflect this. */
396 else if (wordsize == 4 && register_size (gdbarch, regno) == 8
397 && PT_FPSCR == (48 + 2*32 + 1))
398 u_addr = (48 + 2*32) * wordsize;
400 u_addr = PT_FPSCR * wordsize;
405 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
406 registers set mechanism, as opposed to the interface for all the
407 other registers, that stores/fetches each register individually. */
409 fetch_vsx_register (struct regcache *regcache, int tid, int regno)
412 gdb_vsxregset_t regs;
413 struct gdbarch *gdbarch = get_regcache_arch (regcache);
414 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
415 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
417 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
422 have_ptrace_getsetvsxregs = 0;
425 perror_with_name (_("Unable to fetch VSX register"));
428 regcache_raw_supply (regcache, regno,
429 regs + (regno - tdep->ppc_vsr0_upper_regnum)
433 /* The Linux kernel ptrace interface for AltiVec registers uses the
434 registers set mechanism, as opposed to the interface for all the
435 other registers, that stores/fetches each register individually. */
437 fetch_altivec_register (struct regcache *regcache, int tid, int regno)
442 struct gdbarch *gdbarch = get_regcache_arch (regcache);
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
444 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
446 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
451 have_ptrace_getvrregs = 0;
454 perror_with_name (_("Unable to fetch AltiVec register"));
457 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
458 long on the hardware. We deal only with the lower 4 bytes of the
459 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
460 there is no need to define an offset for it. */
461 if (regno == (tdep->ppc_vrsave_regnum - 1))
462 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
464 regcache_raw_supply (regcache, regno,
466 - tdep->ppc_vr0_regnum) * vrregsize + offset);
469 /* Fetch the top 32 bits of TID's general-purpose registers and the
470 SPE-specific registers, and place the results in EVRREGSET. If we
471 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
474 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
475 PTRACE_SETEVRREGS requests are supported is isolated here, and in
476 set_spe_registers. */
478 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
480 if (have_ptrace_getsetevrregs)
482 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
486 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
487 we just return zeros. */
489 have_ptrace_getsetevrregs = 0;
491 /* Anything else needs to be reported. */
492 perror_with_name (_("Unable to fetch SPE registers"));
496 memset (evrregset, 0, sizeof (*evrregset));
499 /* Supply values from TID for SPE-specific raw registers: the upper
500 halves of the GPRs, the accumulator, and the spefscr. REGNO must
501 be the number of an upper half register, acc, spefscr, or -1 to
502 supply the values of all registers. */
504 fetch_spe_register (struct regcache *regcache, int tid, int regno)
506 struct gdbarch *gdbarch = get_regcache_arch (regcache);
507 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
508 struct gdb_evrregset_t evrregs;
510 gdb_assert (sizeof (evrregs.evr[0])
511 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
512 gdb_assert (sizeof (evrregs.acc)
513 == register_size (gdbarch, tdep->ppc_acc_regnum));
514 gdb_assert (sizeof (evrregs.spefscr)
515 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
517 get_spe_registers (tid, &evrregs);
523 for (i = 0; i < ppc_num_gprs; i++)
524 regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
527 else if (tdep->ppc_ev0_upper_regnum <= regno
528 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
529 regcache_raw_supply (regcache, regno,
530 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
533 || regno == tdep->ppc_acc_regnum)
534 regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
537 || regno == tdep->ppc_spefscr_regnum)
538 regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
543 fetch_register (struct regcache *regcache, int tid, int regno)
545 struct gdbarch *gdbarch = get_regcache_arch (regcache);
546 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
547 /* This isn't really an address. But ptrace thinks of it as one. */
548 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
549 int bytes_transferred;
550 unsigned int offset; /* Offset of registers within the u area. */
551 gdb_byte buf[MAX_REGISTER_SIZE];
553 if (altivec_register_p (gdbarch, regno))
555 /* If this is the first time through, or if it is not the first
556 time through, and we have comfirmed that there is kernel
557 support for such a ptrace request, then go and fetch the
559 if (have_ptrace_getvrregs)
561 fetch_altivec_register (regcache, tid, regno);
564 /* If we have discovered that there is no ptrace support for
565 AltiVec registers, fall through and return zeroes, because
566 regaddr will be -1 in this case. */
568 if (vsx_register_p (gdbarch, regno))
570 if (have_ptrace_getsetvsxregs)
572 fetch_vsx_register (regcache, tid, regno);
576 else if (spe_register_p (gdbarch, regno))
578 fetch_spe_register (regcache, tid, regno);
584 memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
585 regcache_raw_supply (regcache, regno, buf);
589 /* Read the raw register using sizeof(long) sized chunks. On a
590 32-bit platform, 64-bit floating-point registers will require two
592 for (bytes_transferred = 0;
593 bytes_transferred < register_size (gdbarch, regno);
594 bytes_transferred += sizeof (long))
599 l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
600 regaddr += sizeof (long);
604 xsnprintf (message, sizeof (message), "reading register %s (#%d)",
605 gdbarch_register_name (gdbarch, regno), regno);
606 perror_with_name (message);
608 memcpy (&buf[bytes_transferred], &l, sizeof (l));
611 /* Now supply the register. Keep in mind that the regcache's idea
612 of the register's size may not be a multiple of sizeof
614 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
616 /* Little-endian values are always found at the left end of the
617 bytes transferred. */
618 regcache_raw_supply (regcache, regno, buf);
620 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
622 /* Big-endian values are found at the right end of the bytes
624 size_t padding = (bytes_transferred - register_size (gdbarch, regno));
625 regcache_raw_supply (regcache, regno, buf + padding);
628 internal_error (__FILE__, __LINE__,
629 _("fetch_register: unexpected byte order: %d"),
630 gdbarch_byte_order (gdbarch));
634 supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
637 struct gdbarch *gdbarch = get_regcache_arch (regcache);
638 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
639 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
641 for (i = 0; i < ppc_num_vshrs; i++)
643 regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
644 *vsxregsetp + i * vsxregsize);
649 supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)
652 struct gdbarch *gdbarch = get_regcache_arch (regcache);
653 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
654 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
655 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
656 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
658 for (i = 0; i < num_of_vrregs; i++)
660 /* The last 2 registers of this set are only 32 bit long, not
661 128. However an offset is necessary only for VSCR because it
662 occupies a whole vector, while VRSAVE occupies a full 4 bytes
664 if (i == (num_of_vrregs - 2))
665 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
666 *vrregsetp + i * vrregsize + offset);
668 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
669 *vrregsetp + i * vrregsize);
674 fetch_vsx_registers (struct regcache *regcache, int tid)
677 gdb_vsxregset_t regs;
679 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
684 have_ptrace_getsetvsxregs = 0;
687 perror_with_name (_("Unable to fetch VSX registers"));
689 supply_vsxregset (regcache, ®s);
693 fetch_altivec_registers (struct regcache *regcache, int tid)
698 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
703 have_ptrace_getvrregs = 0;
706 perror_with_name (_("Unable to fetch AltiVec registers"));
708 supply_vrregset (regcache, ®s);
711 /* This function actually issues the request to ptrace, telling
712 it to get all general-purpose registers and put them into the
715 If the ptrace request does not exist, this function returns 0
716 and properly sets the have_ptrace_* flag. If the request fails,
717 this function calls perror_with_name. Otherwise, if the request
718 succeeds, then the regcache gets filled and 1 is returned. */
720 fetch_all_gp_regs (struct regcache *regcache, int tid)
722 struct gdbarch *gdbarch = get_regcache_arch (regcache);
723 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
724 gdb_gregset_t gregset;
726 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
730 have_ptrace_getsetregs = 0;
733 perror_with_name (_("Couldn't get general-purpose registers."));
736 supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
741 /* This is a wrapper for the fetch_all_gp_regs function. It is
742 responsible for verifying if this target has the ptrace request
743 that can be used to fetch all general-purpose registers at one
744 shot. If it doesn't, then we should fetch them using the
745 old-fashioned way, which is to iterate over the registers and
746 request them one by one. */
748 fetch_gp_regs (struct regcache *regcache, int tid)
750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
751 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
754 if (have_ptrace_getsetregs)
755 if (fetch_all_gp_regs (regcache, tid))
758 /* If we've hit this point, it doesn't really matter which
759 architecture we are using. We just need to read the
760 registers in the "old-fashioned way". */
761 for (i = 0; i < ppc_num_gprs; i++)
762 fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
765 /* This function actually issues the request to ptrace, telling
766 it to get all floating-point registers and put them into the
769 If the ptrace request does not exist, this function returns 0
770 and properly sets the have_ptrace_* flag. If the request fails,
771 this function calls perror_with_name. Otherwise, if the request
772 succeeds, then the regcache gets filled and 1 is returned. */
774 fetch_all_fp_regs (struct regcache *regcache, int tid)
776 gdb_fpregset_t fpregs;
778 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
782 have_ptrace_getsetfpregs = 0;
785 perror_with_name (_("Couldn't get floating-point registers."));
788 supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs);
793 /* This is a wrapper for the fetch_all_fp_regs function. It is
794 responsible for verifying if this target has the ptrace request
795 that can be used to fetch all floating-point registers at one
796 shot. If it doesn't, then we should fetch them using the
797 old-fashioned way, which is to iterate over the registers and
798 request them one by one. */
800 fetch_fp_regs (struct regcache *regcache, int tid)
802 struct gdbarch *gdbarch = get_regcache_arch (regcache);
803 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
806 if (have_ptrace_getsetfpregs)
807 if (fetch_all_fp_regs (regcache, tid))
810 /* If we've hit this point, it doesn't really matter which
811 architecture we are using. We just need to read the
812 registers in the "old-fashioned way". */
813 for (i = 0; i < ppc_num_fprs; i++)
814 fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
818 fetch_ppc_registers (struct regcache *regcache, int tid)
821 struct gdbarch *gdbarch = get_regcache_arch (regcache);
822 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
824 fetch_gp_regs (regcache, tid);
825 if (tdep->ppc_fp0_regnum >= 0)
826 fetch_fp_regs (regcache, tid);
827 fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
828 if (tdep->ppc_ps_regnum != -1)
829 fetch_register (regcache, tid, tdep->ppc_ps_regnum);
830 if (tdep->ppc_cr_regnum != -1)
831 fetch_register (regcache, tid, tdep->ppc_cr_regnum);
832 if (tdep->ppc_lr_regnum != -1)
833 fetch_register (regcache, tid, tdep->ppc_lr_regnum);
834 if (tdep->ppc_ctr_regnum != -1)
835 fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
836 if (tdep->ppc_xer_regnum != -1)
837 fetch_register (regcache, tid, tdep->ppc_xer_regnum);
838 if (tdep->ppc_mq_regnum != -1)
839 fetch_register (regcache, tid, tdep->ppc_mq_regnum);
840 if (ppc_linux_trap_reg_p (gdbarch))
842 fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
843 fetch_register (regcache, tid, PPC_TRAP_REGNUM);
845 if (tdep->ppc_fpscr_regnum != -1)
846 fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
847 if (have_ptrace_getvrregs)
848 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
849 fetch_altivec_registers (regcache, tid);
850 if (have_ptrace_getsetvsxregs)
851 if (tdep->ppc_vsr0_upper_regnum != -1)
852 fetch_vsx_registers (regcache, tid);
853 if (tdep->ppc_ev0_upper_regnum >= 0)
854 fetch_spe_register (regcache, tid, -1);
857 /* Fetch registers from the child process. Fetch all registers if
858 regno == -1, otherwise fetch all general registers or all floating
859 point registers depending upon the value of regno. */
861 ppc_linux_fetch_inferior_registers (struct target_ops *ops,
862 struct regcache *regcache, int regno)
864 /* Overload thread id onto process id. */
865 int tid = ptid_get_lwp (inferior_ptid);
867 /* No thread id, just use process id. */
869 tid = ptid_get_pid (inferior_ptid);
872 fetch_ppc_registers (regcache, tid);
874 fetch_register (regcache, tid, regno);
877 /* Store one VSX register. */
879 store_vsx_register (const struct regcache *regcache, int tid, int regno)
882 gdb_vsxregset_t regs;
883 struct gdbarch *gdbarch = get_regcache_arch (regcache);
884 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
885 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
887 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
892 have_ptrace_getsetvsxregs = 0;
895 perror_with_name (_("Unable to fetch VSX register"));
898 regcache_raw_collect (regcache, regno, regs +
899 (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
901 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s);
903 perror_with_name (_("Unable to store VSX register"));
906 /* Store one register. */
908 store_altivec_register (const struct regcache *regcache, int tid, int regno)
913 struct gdbarch *gdbarch = get_regcache_arch (regcache);
914 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
915 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
917 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
922 have_ptrace_getvrregs = 0;
925 perror_with_name (_("Unable to fetch AltiVec register"));
928 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
929 long on the hardware. */
930 if (regno == (tdep->ppc_vrsave_regnum - 1))
931 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
933 regcache_raw_collect (regcache, regno,
935 - tdep->ppc_vr0_regnum) * vrregsize + offset);
937 ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s);
939 perror_with_name (_("Unable to store AltiVec register"));
942 /* Assuming TID referrs to an SPE process, set the top halves of TID's
943 general-purpose registers and its SPE-specific registers to the
944 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
947 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
948 PTRACE_SETEVRREGS requests are supported is isolated here, and in
949 get_spe_registers. */
951 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
953 if (have_ptrace_getsetevrregs)
955 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
959 /* EIO means that the PTRACE_SETEVRREGS request isn't
960 supported; we fail silently, and don't try the call
963 have_ptrace_getsetevrregs = 0;
965 /* Anything else needs to be reported. */
966 perror_with_name (_("Unable to set SPE registers"));
971 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
972 If REGNO is -1, write the values of all the SPE-specific
975 store_spe_register (const struct regcache *regcache, int tid, int regno)
977 struct gdbarch *gdbarch = get_regcache_arch (regcache);
978 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
979 struct gdb_evrregset_t evrregs;
981 gdb_assert (sizeof (evrregs.evr[0])
982 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
983 gdb_assert (sizeof (evrregs.acc)
984 == register_size (gdbarch, tdep->ppc_acc_regnum));
985 gdb_assert (sizeof (evrregs.spefscr)
986 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
989 /* Since we're going to write out every register, the code below
990 should store to every field of evrregs; if that doesn't happen,
991 make it obvious by initializing it with suspicious values. */
992 memset (&evrregs, 42, sizeof (evrregs));
994 /* We can only read and write the entire EVR register set at a
995 time, so to write just a single register, we do a
996 read-modify-write maneuver. */
997 get_spe_registers (tid, &evrregs);
1003 for (i = 0; i < ppc_num_gprs; i++)
1004 regcache_raw_collect (regcache,
1005 tdep->ppc_ev0_upper_regnum + i,
1008 else if (tdep->ppc_ev0_upper_regnum <= regno
1009 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
1010 regcache_raw_collect (regcache, regno,
1011 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
1014 || regno == tdep->ppc_acc_regnum)
1015 regcache_raw_collect (regcache,
1016 tdep->ppc_acc_regnum,
1020 || regno == tdep->ppc_spefscr_regnum)
1021 regcache_raw_collect (regcache,
1022 tdep->ppc_spefscr_regnum,
1025 /* Write back the modified register set. */
1026 set_spe_registers (tid, &evrregs);
1030 store_register (const struct regcache *regcache, int tid, int regno)
1032 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1033 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1034 /* This isn't really an address. But ptrace thinks of it as one. */
1035 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
1037 size_t bytes_to_transfer;
1038 gdb_byte buf[MAX_REGISTER_SIZE];
1040 if (altivec_register_p (gdbarch, regno))
1042 store_altivec_register (regcache, tid, regno);
1045 if (vsx_register_p (gdbarch, regno))
1047 store_vsx_register (regcache, tid, regno);
1050 else if (spe_register_p (gdbarch, regno))
1052 store_spe_register (regcache, tid, regno);
1059 /* First collect the register. Keep in mind that the regcache's
1060 idea of the register's size may not be a multiple of sizeof
1062 memset (buf, 0, sizeof buf);
1063 bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
1064 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1066 /* Little-endian values always sit at the left end of the buffer. */
1067 regcache_raw_collect (regcache, regno, buf);
1069 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1071 /* Big-endian values sit at the right end of the buffer. */
1072 size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
1073 regcache_raw_collect (regcache, regno, buf + padding);
1076 for (i = 0; i < bytes_to_transfer; i += sizeof (long))
1080 memcpy (&l, &buf[i], sizeof (l));
1082 ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
1083 regaddr += sizeof (long);
1086 && (regno == tdep->ppc_fpscr_regnum
1087 || regno == PPC_ORIG_R3_REGNUM
1088 || regno == PPC_TRAP_REGNUM))
1090 /* Some older kernel versions don't allow fpscr, orig_r3
1091 or trap to be written. */
1098 xsnprintf (message, sizeof (message), "writing register %s (#%d)",
1099 gdbarch_register_name (gdbarch, regno), regno);
1100 perror_with_name (message);
1106 fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
1109 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1110 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1111 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
1113 for (i = 0; i < ppc_num_vshrs; i++)
1114 regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
1115 *vsxregsetp + i * vsxregsize);
1119 fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
1122 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1123 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1124 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
1125 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
1126 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
1128 for (i = 0; i < num_of_vrregs; i++)
1130 /* The last 2 registers of this set are only 32 bit long, not
1131 128, but only VSCR is fetched as a 16 bytes quantity. */
1132 if (i == (num_of_vrregs - 2))
1133 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1134 *vrregsetp + i * vrregsize + offset);
1136 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1137 *vrregsetp + i * vrregsize);
1142 store_vsx_registers (const struct regcache *regcache, int tid)
1145 gdb_vsxregset_t regs;
1147 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
1152 have_ptrace_getsetvsxregs = 0;
1155 perror_with_name (_("Couldn't get VSX registers"));
1158 fill_vsxregset (regcache, ®s);
1160 if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0)
1161 perror_with_name (_("Couldn't write VSX registers"));
1165 store_altivec_registers (const struct regcache *regcache, int tid)
1168 gdb_vrregset_t regs;
1170 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
1175 have_ptrace_getvrregs = 0;
1178 perror_with_name (_("Couldn't get AltiVec registers"));
1181 fill_vrregset (regcache, ®s);
1183 if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0)
1184 perror_with_name (_("Couldn't write AltiVec registers"));
1187 /* This function actually issues the request to ptrace, telling
1188 it to store all general-purpose registers present in the specified
1191 If the ptrace request does not exist, this function returns 0
1192 and properly sets the have_ptrace_* flag. If the request fails,
1193 this function calls perror_with_name. Otherwise, if the request
1194 succeeds, then the regcache is stored and 1 is returned. */
1196 store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
1198 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1199 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1200 gdb_gregset_t gregset;
1202 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
1206 have_ptrace_getsetregs = 0;
1209 perror_with_name (_("Couldn't get general-purpose registers."));
1212 fill_gregset (regcache, &gregset, regno);
1214 if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
1218 have_ptrace_getsetregs = 0;
1221 perror_with_name (_("Couldn't set general-purpose registers."));
1227 /* This is a wrapper for the store_all_gp_regs function. It is
1228 responsible for verifying if this target has the ptrace request
1229 that can be used to store all general-purpose registers at one
1230 shot. If it doesn't, then we should store them using the
1231 old-fashioned way, which is to iterate over the registers and
1232 store them one by one. */
1234 store_gp_regs (const struct regcache *regcache, int tid, int regno)
1236 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1237 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1240 if (have_ptrace_getsetregs)
1241 if (store_all_gp_regs (regcache, tid, regno))
1244 /* If we hit this point, it doesn't really matter which
1245 architecture we are using. We just need to store the
1246 registers in the "old-fashioned way". */
1247 for (i = 0; i < ppc_num_gprs; i++)
1248 store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
1251 /* This function actually issues the request to ptrace, telling
1252 it to store all floating-point registers present in the specified
1255 If the ptrace request does not exist, this function returns 0
1256 and properly sets the have_ptrace_* flag. If the request fails,
1257 this function calls perror_with_name. Otherwise, if the request
1258 succeeds, then the regcache is stored and 1 is returned. */
1260 store_all_fp_regs (const struct regcache *regcache, int tid, int regno)
1262 gdb_fpregset_t fpregs;
1264 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
1268 have_ptrace_getsetfpregs = 0;
1271 perror_with_name (_("Couldn't get floating-point registers."));
1274 fill_fpregset (regcache, &fpregs, regno);
1276 if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
1280 have_ptrace_getsetfpregs = 0;
1283 perror_with_name (_("Couldn't set floating-point registers."));
1289 /* This is a wrapper for the store_all_fp_regs function. It is
1290 responsible for verifying if this target has the ptrace request
1291 that can be used to store all floating-point registers at one
1292 shot. If it doesn't, then we should store them using the
1293 old-fashioned way, which is to iterate over the registers and
1294 store them one by one. */
1296 store_fp_regs (const struct regcache *regcache, int tid, int regno)
1298 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1299 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1302 if (have_ptrace_getsetfpregs)
1303 if (store_all_fp_regs (regcache, tid, regno))
1306 /* If we hit this point, it doesn't really matter which
1307 architecture we are using. We just need to store the
1308 registers in the "old-fashioned way". */
1309 for (i = 0; i < ppc_num_fprs; i++)
1310 store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
1314 store_ppc_registers (const struct regcache *regcache, int tid)
1317 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1318 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1320 store_gp_regs (regcache, tid, -1);
1321 if (tdep->ppc_fp0_regnum >= 0)
1322 store_fp_regs (regcache, tid, -1);
1323 store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
1324 if (tdep->ppc_ps_regnum != -1)
1325 store_register (regcache, tid, tdep->ppc_ps_regnum);
1326 if (tdep->ppc_cr_regnum != -1)
1327 store_register (regcache, tid, tdep->ppc_cr_regnum);
1328 if (tdep->ppc_lr_regnum != -1)
1329 store_register (regcache, tid, tdep->ppc_lr_regnum);
1330 if (tdep->ppc_ctr_regnum != -1)
1331 store_register (regcache, tid, tdep->ppc_ctr_regnum);
1332 if (tdep->ppc_xer_regnum != -1)
1333 store_register (regcache, tid, tdep->ppc_xer_regnum);
1334 if (tdep->ppc_mq_regnum != -1)
1335 store_register (regcache, tid, tdep->ppc_mq_regnum);
1336 if (tdep->ppc_fpscr_regnum != -1)
1337 store_register (regcache, tid, tdep->ppc_fpscr_regnum);
1338 if (ppc_linux_trap_reg_p (gdbarch))
1340 store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1341 store_register (regcache, tid, PPC_TRAP_REGNUM);
1343 if (have_ptrace_getvrregs)
1344 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1345 store_altivec_registers (regcache, tid);
1346 if (have_ptrace_getsetvsxregs)
1347 if (tdep->ppc_vsr0_upper_regnum != -1)
1348 store_vsx_registers (regcache, tid);
1349 if (tdep->ppc_ev0_upper_regnum >= 0)
1350 store_spe_register (regcache, tid, -1);
1353 /* Fetch the AT_HWCAP entry from the aux vector. */
1354 static unsigned long
1355 ppc_linux_get_hwcap (void)
1359 if (target_auxv_search (¤t_target, AT_HWCAP, &field))
1360 return (unsigned long) field;
1365 /* The cached DABR value, to install in new threads.
1366 This variable is used when the PowerPC HWDEBUG ptrace
1367 interface is not available. */
1368 static long saved_dabr_value;
1370 /* Global structure that will store information about the available
1371 features provided by the PowerPC HWDEBUG ptrace interface. */
1372 static struct ppc_debug_info hwdebug_info;
1374 /* Global variable that holds the maximum number of slots that the
1375 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1377 static size_t max_slots_number = 0;
1379 struct hw_break_tuple
1382 struct ppc_hw_breakpoint *hw_break;
1385 /* This is an internal VEC created to store information about *points inserted
1386 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1388 typedef struct thread_points
1390 /* The TID to which this *point relates. */
1392 /* Information about the *point, such as its address, type, etc.
1394 Each element inside this vector corresponds to a hardware
1395 breakpoint or watchpoint in the thread represented by TID. The maximum
1396 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1397 the tuple is NULL, then the position in the vector is free. */
1398 struct hw_break_tuple *hw_breaks;
1400 DEF_VEC_P (thread_points_p);
1402 VEC(thread_points_p) *ppc_threads = NULL;
1404 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1406 #define PPC_DEBUG_CURRENT_VERSION 1
1408 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1410 have_ptrace_hwdebug_interface (void)
1412 static int have_ptrace_hwdebug_interface = -1;
1414 if (have_ptrace_hwdebug_interface == -1)
1418 tid = ptid_get_lwp (inferior_ptid);
1420 tid = ptid_get_pid (inferior_ptid);
1422 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1423 if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0)
1425 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1426 provides any supported feature. */
1427 if (hwdebug_info.features != 0)
1429 have_ptrace_hwdebug_interface = 1;
1430 max_slots_number = hwdebug_info.num_instruction_bps
1431 + hwdebug_info.num_data_bps
1432 + hwdebug_info.num_condition_regs;
1433 return have_ptrace_hwdebug_interface;
1436 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1437 have_ptrace_hwdebug_interface = 0;
1438 memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info));
1441 return have_ptrace_hwdebug_interface;
1445 ppc_linux_can_use_hw_breakpoint (struct target_ops *self,
1446 int type, int cnt, int ot)
1448 int total_hw_wp, total_hw_bp;
1450 if (have_ptrace_hwdebug_interface ())
1452 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1453 available hardware watchpoints and breakpoints is stored at the
1454 hwdebug_info struct. */
1455 total_hw_bp = hwdebug_info.num_instruction_bps;
1456 total_hw_wp = hwdebug_info.num_data_bps;
1460 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1461 consider having 1 hardware watchpoint and no hardware breakpoints. */
1466 if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
1467 || type == bp_access_watchpoint || type == bp_watchpoint)
1469 if (cnt + ot > total_hw_wp)
1472 else if (type == bp_hardware_breakpoint)
1474 if (total_hw_bp == 0)
1476 /* No hardware breakpoint support. */
1479 if (cnt > total_hw_bp)
1483 if (!have_ptrace_hwdebug_interface ())
1486 ptid_t ptid = inferior_ptid;
1488 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1489 and whether the target has DABR. If either answer is no, the
1490 ptrace call will return -1. Fail in that case. */
1491 tid = ptid_get_lwp (ptid);
1493 tid = ptid_get_pid (ptid);
1495 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1503 ppc_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
1504 CORE_ADDR addr, int len)
1506 /* Handle sub-8-byte quantities. */
1510 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1511 restrictions for watchpoints in the processors. In that case, we use that
1512 information to determine the hardcoded watchable region for
1514 if (have_ptrace_hwdebug_interface ())
1517 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1518 watchpoints and can watch any access within an arbitrary memory
1519 region. This is useful to watch arrays and structs, for instance. It
1520 takes two hardware watchpoints though. */
1522 && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE
1523 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1525 /* Check if the processor provides DAWR interface. */
1526 if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR)
1527 /* DAWR interface allows to watch up to 512 byte wide ranges which
1528 can't cross a 512 byte boundary. */
1531 region_size = hwdebug_info.data_bp_alignment;
1532 /* Server processors provide one hardware watchpoint and addr+len should
1533 fall in the watchable region provided by the ptrace interface. */
1535 && (addr + len > (addr & ~(region_size - 1)) + region_size))
1538 /* addr+len must fall in the 8 byte watchable region for DABR-based
1539 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1540 ptrace interface, DAC-based processors (i.e., embedded processors) will
1541 use addresses aligned to 4-bytes due to the way the read/write flags are
1542 passed in the old ptrace interface. */
1543 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1544 && (addr + len) > (addr & ~3) + 4)
1545 || (addr + len) > (addr & ~7) + 8)
1551 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1553 hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
1555 return (a->trigger_type == b->trigger_type
1556 && a->addr_mode == b->addr_mode
1557 && a->condition_mode == b->condition_mode
1558 && a->addr == b->addr
1559 && a->addr2 == b->addr2
1560 && a->condition_value == b->condition_value);
1563 /* This function can be used to retrieve a thread_points by the TID of the
1564 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1565 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1566 provided TID will be created and returned. */
1567 static struct thread_points *
1568 hwdebug_find_thread_points_by_tid (int tid, int alloc_new)
1571 struct thread_points *t;
1573 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
1579 /* Do we need to allocate a new point_item
1580 if the wanted one does not exist? */
1583 t = xmalloc (sizeof (struct thread_points));
1585 = xzalloc (max_slots_number * sizeof (struct hw_break_tuple));
1587 VEC_safe_push (thread_points_p, ppc_threads, t);
1593 /* This function is a generic wrapper that is responsible for inserting a
1594 *point (i.e., calling `ptrace' in order to issue the request to the
1595 kernel) and registering it internally in GDB. */
1597 hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid)
1601 struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint));
1602 struct hw_break_tuple *hw_breaks;
1603 struct cleanup *c = make_cleanup (xfree, p);
1604 struct thread_points *t;
1605 struct hw_break_tuple *tuple;
1607 memcpy (p, b, sizeof (struct ppc_hw_breakpoint));
1610 slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p);
1612 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1614 /* Everything went fine, so we have to register this *point. */
1615 t = hwdebug_find_thread_points_by_tid (tid, 1);
1616 gdb_assert (t != NULL);
1617 hw_breaks = t->hw_breaks;
1619 /* Find a free element in the hw_breaks vector. */
1620 for (i = 0; i < max_slots_number; i++)
1621 if (hw_breaks[i].hw_break == NULL)
1623 hw_breaks[i].slot = slot;
1624 hw_breaks[i].hw_break = p;
1628 gdb_assert (i != max_slots_number);
1630 discard_cleanups (c);
1633 /* This function is a generic wrapper that is responsible for removing a
1634 *point (i.e., calling `ptrace' in order to issue the request to the
1635 kernel), and unregistering it internally at GDB. */
1637 hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid)
1640 struct hw_break_tuple *hw_breaks;
1641 struct thread_points *t;
1643 t = hwdebug_find_thread_points_by_tid (tid, 0);
1644 gdb_assert (t != NULL);
1645 hw_breaks = t->hw_breaks;
1647 for (i = 0; i < max_slots_number; i++)
1648 if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b))
1651 gdb_assert (i != max_slots_number);
1653 /* We have to ignore ENOENT errors because the kernel implements hardware
1654 breakpoints/watchpoints as "one-shot", that is, they are automatically
1655 deleted when hit. */
1657 if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
1658 if (errno != ENOENT)
1659 perror_with_name (_("Unexpected error deleting "
1660 "breakpoint or watchpoint"));
1662 xfree (hw_breaks[i].hw_break);
1663 hw_breaks[i].hw_break = NULL;
1666 /* Return the number of registers needed for a ranged breakpoint. */
1669 ppc_linux_ranged_break_num_registers (struct target_ops *target)
1671 return ((have_ptrace_hwdebug_interface ()
1672 && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)?
1676 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1677 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1680 ppc_linux_insert_hw_breakpoint (struct target_ops *self,
1681 struct gdbarch *gdbarch,
1682 struct bp_target_info *bp_tgt)
1684 struct lwp_info *lp;
1685 struct ppc_hw_breakpoint p;
1687 if (!have_ptrace_hwdebug_interface ())
1690 p.version = PPC_DEBUG_CURRENT_VERSION;
1691 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1692 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1693 p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address);
1694 p.condition_value = 0;
1698 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1700 /* The breakpoint will trigger if the address of the instruction is
1701 within the defined range, as follows: p.addr <= address < p.addr2. */
1702 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1706 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1711 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1717 ppc_linux_remove_hw_breakpoint (struct target_ops *self,
1718 struct gdbarch *gdbarch,
1719 struct bp_target_info *bp_tgt)
1721 struct lwp_info *lp;
1722 struct ppc_hw_breakpoint p;
1724 if (!have_ptrace_hwdebug_interface ())
1727 p.version = PPC_DEBUG_CURRENT_VERSION;
1728 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1729 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1730 p.addr = (uint64_t) bp_tgt->placed_address;
1731 p.condition_value = 0;
1735 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1737 /* The breakpoint will trigger if the address of the instruction is within
1738 the defined range, as follows: p.addr <= address < p.addr2. */
1739 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1743 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1748 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
1754 get_trigger_type (int rw)
1759 t = PPC_BREAKPOINT_TRIGGER_READ;
1760 else if (rw == hw_write)
1761 t = PPC_BREAKPOINT_TRIGGER_WRITE;
1763 t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
1768 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1769 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1770 or hw_access for an access watchpoint. Returns 0 on success and throws
1771 an error on failure. */
1774 ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1775 CORE_ADDR mask, int rw)
1777 struct lwp_info *lp;
1778 struct ppc_hw_breakpoint p;
1780 gdb_assert (have_ptrace_hwdebug_interface ());
1782 p.version = PPC_DEBUG_CURRENT_VERSION;
1783 p.trigger_type = get_trigger_type (rw);
1784 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1785 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1788 p.condition_value = 0;
1791 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1796 /* Remove a masked watchpoint at ADDR with the mask MASK.
1797 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1798 or hw_access for an access watchpoint. Returns 0 on success and throws
1799 an error on failure. */
1802 ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1803 CORE_ADDR mask, int rw)
1805 struct lwp_info *lp;
1806 struct ppc_hw_breakpoint p;
1808 gdb_assert (have_ptrace_hwdebug_interface ());
1810 p.version = PPC_DEBUG_CURRENT_VERSION;
1811 p.trigger_type = get_trigger_type (rw);
1812 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1813 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1816 p.condition_value = 0;
1819 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
1824 /* Check whether we have at least one free DVC register. */
1826 can_use_watchpoint_cond_accel (void)
1828 struct thread_points *p;
1829 int tid = ptid_get_lwp (inferior_ptid);
1830 int cnt = hwdebug_info.num_condition_regs, i;
1831 CORE_ADDR tmp_value;
1833 if (!have_ptrace_hwdebug_interface () || cnt == 0)
1836 p = hwdebug_find_thread_points_by_tid (tid, 0);
1840 for (i = 0; i < max_slots_number; i++)
1841 if (p->hw_breaks[i].hw_break != NULL
1842 && (p->hw_breaks[i].hw_break->condition_mode
1843 != PPC_BREAKPOINT_CONDITION_NONE))
1846 /* There are no available slots now. */
1854 /* Calculate the enable bits and the contents of the Data Value Compare
1855 debug register present in BookE processors.
1857 ADDR is the address to be watched, LEN is the length of watched data
1858 and DATA_VALUE is the value which will trigger the watchpoint.
1859 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1860 CONDITION_VALUE will hold the value which should be put in the
1863 calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
1864 uint32_t *condition_mode, uint64_t *condition_value)
1866 int i, num_byte_enable, align_offset, num_bytes_off_dvc,
1867 rightmost_enabled_byte;
1868 CORE_ADDR addr_end_data, addr_end_dvc;
1870 /* The DVC register compares bytes within fixed-length windows which
1871 are word-aligned, with length equal to that of the DVC register.
1872 We need to calculate where our watch region is relative to that
1873 window and enable comparison of the bytes which fall within it. */
1875 align_offset = addr % hwdebug_info.sizeof_condition;
1876 addr_end_data = addr + len;
1877 addr_end_dvc = (addr - align_offset
1878 + hwdebug_info.sizeof_condition);
1879 num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
1880 addr_end_data - addr_end_dvc : 0;
1881 num_byte_enable = len - num_bytes_off_dvc;
1882 /* Here, bytes are numbered from right to left. */
1883 rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
1884 addr_end_dvc - addr_end_data : 0;
1886 *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
1887 for (i = 0; i < num_byte_enable; i++)
1889 |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
1891 /* Now we need to match the position within the DVC of the comparison
1892 value with where the watch region is relative to the window
1893 (i.e., the ALIGN_OFFSET). */
1895 *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
1896 << rightmost_enabled_byte * 8);
1899 /* Return the number of memory locations that need to be accessed to
1900 evaluate the expression which generated the given value chain.
1901 Returns -1 if there's any register access involved, or if there are
1902 other kinds of values which are not acceptable in a condition
1903 expression (e.g., lval_computed or lval_internalvar). */
1905 num_memory_accesses (struct value *v)
1907 int found_memory_cnt = 0;
1908 struct value *head = v;
1910 /* The idea here is that evaluating an expression generates a series
1911 of values, one holding the value of every subexpression. (The
1912 expression a*b+c has five subexpressions: a, b, a*b, c, and
1913 a*b+c.) GDB's values hold almost enough information to establish
1914 the criteria given above --- they identify memory lvalues,
1915 register lvalues, computed values, etcetera. So we can evaluate
1916 the expression, and then scan the chain of values that leaves
1917 behind to determine the memory locations involved in the evaluation
1920 However, I don't think that the values returned by inferior
1921 function calls are special in any way. So this function may not
1922 notice that an expression contains an inferior function call.
1925 for (; v; v = value_next (v))
1927 /* Constants and values from the history are fine. */
1928 if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
1930 else if (VALUE_LVAL (v) == lval_memory)
1932 /* A lazy memory lvalue is one that GDB never needed to fetch;
1933 we either just used its address (e.g., `a' in `a.b') or
1934 we never needed it at all (e.g., `a' in `a,b'). */
1935 if (!value_lazy (v))
1938 /* Other kinds of values are not fine. */
1943 return found_memory_cnt;
1946 /* Verifies whether the expression COND can be implemented using the
1947 DVC (Data Value Compare) register in BookE processors. The expression
1948 must test the watch value for equality with a constant expression.
1949 If the function returns 1, DATA_VALUE will contain the constant against
1950 which the watch value should be compared and LEN will contain the size
1953 check_condition (CORE_ADDR watch_addr, struct expression *cond,
1954 CORE_ADDR *data_value, int *len)
1956 int pc = 1, num_accesses_left, num_accesses_right;
1957 struct value *left_val, *right_val, *left_chain, *right_chain;
1959 if (cond->elts[0].opcode != BINOP_EQUAL)
1962 fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
1963 num_accesses_left = num_memory_accesses (left_chain);
1965 if (left_val == NULL || num_accesses_left < 0)
1967 free_value_chain (left_chain);
1972 fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
1973 num_accesses_right = num_memory_accesses (right_chain);
1975 if (right_val == NULL || num_accesses_right < 0)
1977 free_value_chain (left_chain);
1978 free_value_chain (right_chain);
1983 if (num_accesses_left == 1 && num_accesses_right == 0
1984 && VALUE_LVAL (left_val) == lval_memory
1985 && value_address (left_val) == watch_addr)
1987 *data_value = value_as_long (right_val);
1989 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1990 the same type as the memory region referenced by LEFT_VAL. */
1991 *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
1993 else if (num_accesses_left == 0 && num_accesses_right == 1
1994 && VALUE_LVAL (right_val) == lval_memory
1995 && value_address (right_val) == watch_addr)
1997 *data_value = value_as_long (left_val);
1999 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
2000 the same type as the memory region referenced by RIGHT_VAL. */
2001 *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
2005 free_value_chain (left_chain);
2006 free_value_chain (right_chain);
2011 free_value_chain (left_chain);
2012 free_value_chain (right_chain);
2017 /* Return non-zero if the target is capable of using hardware to evaluate
2018 the condition expression, thus only triggering the watchpoint when it is
2021 ppc_linux_can_accel_watchpoint_condition (struct target_ops *self,
2022 CORE_ADDR addr, int len, int rw,
2023 struct expression *cond)
2025 CORE_ADDR data_value;
2027 return (have_ptrace_hwdebug_interface ()
2028 && hwdebug_info.num_condition_regs > 0
2029 && check_condition (addr, cond, &data_value, &len));
2032 /* Set up P with the parameters necessary to request a watchpoint covering
2033 LEN bytes starting at ADDR and if possible with condition expression COND
2034 evaluated by hardware. INSERT tells if we are creating a request for
2035 inserting or removing the watchpoint. */
2038 create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
2039 int len, int rw, struct expression *cond,
2043 || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
2046 CORE_ADDR data_value;
2048 use_condition = (insert? can_use_watchpoint_cond_accel ()
2049 : hwdebug_info.num_condition_regs > 0);
2050 if (cond && use_condition && check_condition (addr, cond,
2052 calculate_dvc (addr, len, data_value, &p->condition_mode,
2053 &p->condition_value);
2056 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2057 p->condition_value = 0;
2060 p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
2065 p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
2066 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2067 p->condition_value = 0;
2069 /* The watchpoint will trigger if the address of the memory access is
2070 within the defined range, as follows: p->addr <= address < p->addr2.
2072 Note that the above sentence just documents how ptrace interprets
2073 its arguments; the watchpoint is set to watch the range defined by
2074 the user _inclusively_, as specified by the user interface. */
2075 p->addr2 = (uint64_t) addr + len;
2078 p->version = PPC_DEBUG_CURRENT_VERSION;
2079 p->trigger_type = get_trigger_type (rw);
2080 p->addr = (uint64_t) addr;
2084 ppc_linux_insert_watchpoint (struct target_ops *self,
2085 CORE_ADDR addr, int len, int rw,
2086 struct expression *cond)
2088 struct lwp_info *lp;
2091 if (have_ptrace_hwdebug_interface ())
2093 struct ppc_hw_breakpoint p;
2095 create_watchpoint_request (&p, addr, len, rw, cond, 1);
2098 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
2105 long read_mode, write_mode;
2107 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2109 /* PowerPC 440 requires only the read/write flags to be passed
2116 /* PowerPC 970 and other DABR-based processors are required to pass
2117 the Breakpoint Translation bit together with the flags. */
2122 dabr_value = addr & ~(read_mode | write_mode);
2126 /* Set read and translate bits. */
2127 dabr_value |= read_mode;
2130 /* Set write and translate bits. */
2131 dabr_value |= write_mode;
2134 /* Set read, write and translate bits. */
2135 dabr_value |= read_mode | write_mode;
2139 saved_dabr_value = dabr_value;
2142 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
2143 saved_dabr_value) < 0)
2153 ppc_linux_remove_watchpoint (struct target_ops *self,
2154 CORE_ADDR addr, int len, int rw,
2155 struct expression *cond)
2157 struct lwp_info *lp;
2160 if (have_ptrace_hwdebug_interface ())
2162 struct ppc_hw_breakpoint p;
2164 create_watchpoint_request (&p, addr, len, rw, cond, 0);
2167 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
2173 saved_dabr_value = 0;
2175 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
2176 saved_dabr_value) < 0)
2186 ppc_linux_new_thread (struct lwp_info *lp)
2188 int tid = ptid_get_lwp (lp->ptid);
2190 if (have_ptrace_hwdebug_interface ())
2193 struct thread_points *p;
2194 struct hw_break_tuple *hw_breaks;
2196 if (VEC_empty (thread_points_p, ppc_threads))
2199 /* Get a list of breakpoints from any thread. */
2200 p = VEC_last (thread_points_p, ppc_threads);
2201 hw_breaks = p->hw_breaks;
2203 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2204 for (i = 0; i < max_slots_number; i++)
2205 if (hw_breaks[i].hw_break)
2207 /* Older kernels did not make new threads inherit their parent
2208 thread's debug state, so we always clear the slot and replicate
2209 the debug state ourselves, ensuring compatibility with all
2212 /* The ppc debug resource accounting is done through "slots".
2213 Ask the kernel the deallocate this specific *point's slot. */
2214 ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
2216 hwdebug_insert_point (hw_breaks[i].hw_break, tid);
2220 ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
2224 ppc_linux_thread_exit (struct thread_info *tp, int silent)
2227 int tid = ptid_get_lwp (tp->ptid);
2228 struct hw_break_tuple *hw_breaks;
2229 struct thread_points *t = NULL, *p;
2231 if (!have_ptrace_hwdebug_interface ())
2234 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
2244 VEC_unordered_remove (thread_points_p, ppc_threads, i);
2246 hw_breaks = t->hw_breaks;
2248 for (i = 0; i < max_slots_number; i++)
2249 if (hw_breaks[i].hw_break)
2250 xfree (hw_breaks[i].hw_break);
2252 xfree (t->hw_breaks);
2257 ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
2261 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
2264 if (siginfo.si_signo != SIGTRAP
2265 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2268 if (have_ptrace_hwdebug_interface ())
2271 struct thread_points *t;
2272 struct hw_break_tuple *hw_breaks;
2273 /* The index (or slot) of the *point is passed in the si_errno field. */
2274 int slot = siginfo.si_errno;
2276 t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0);
2278 /* Find out if this *point is a hardware breakpoint.
2279 If so, we should return 0. */
2282 hw_breaks = t->hw_breaks;
2283 for (i = 0; i < max_slots_number; i++)
2284 if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
2285 && hw_breaks[i].hw_break->trigger_type
2286 == PPC_BREAKPOINT_TRIGGER_EXECUTE)
2291 *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
2296 ppc_linux_stopped_by_watchpoint (struct target_ops *ops)
2299 return ppc_linux_stopped_data_address (ops, &addr);
2303 ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
2305 CORE_ADDR start, int length)
2309 if (have_ptrace_hwdebug_interface ()
2310 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2311 return start <= addr && start + length >= addr;
2312 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2319 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2320 return start <= addr + mask && start + length - 1 >= addr;
2323 /* Return the number of registers needed for a masked hardware watchpoint. */
2326 ppc_linux_masked_watch_num_registers (struct target_ops *target,
2327 CORE_ADDR addr, CORE_ADDR mask)
2329 if (!have_ptrace_hwdebug_interface ()
2330 || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0)
2332 else if ((mask & 0xC0000000) != 0xC0000000)
2334 warning (_("The given mask covers kernel address space "
2335 "and cannot be used.\n"));
2344 ppc_linux_store_inferior_registers (struct target_ops *ops,
2345 struct regcache *regcache, int regno)
2347 /* Overload thread id onto process id. */
2348 int tid = ptid_get_lwp (inferior_ptid);
2350 /* No thread id, just use process id. */
2352 tid = ptid_get_pid (inferior_ptid);
2355 store_register (regcache, tid, regno);
2357 store_ppc_registers (regcache, tid);
2360 /* Functions for transferring registers between a gregset_t or fpregset_t
2361 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2362 by the ptrace interface, not the current program's ABI. Eg. if a
2363 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2364 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2367 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
2369 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2371 ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
2375 fill_gregset (const struct regcache *regcache,
2376 gdb_gregset_t *gregsetp, int regno)
2378 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2381 memset (gregsetp, 0, sizeof (*gregsetp));
2382 ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
2386 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
2388 const struct regset *regset = ppc_linux_fpregset ();
2390 ppc_supply_fpregset (regset, regcache, -1,
2391 fpregsetp, sizeof (*fpregsetp));
2395 fill_fpregset (const struct regcache *regcache,
2396 gdb_fpregset_t *fpregsetp, int regno)
2398 const struct regset *regset = ppc_linux_fpregset ();
2400 ppc_collect_fpregset (regset, regcache, regno,
2401 fpregsetp, sizeof (*fpregsetp));
2405 ppc_linux_target_wordsize (void)
2409 /* Check for 64-bit inferior process. This is the case when the host is
2410 64-bit, and in addition the top bit of the MSR register is set. */
2411 #ifdef __powerpc64__
2414 int tid = ptid_get_lwp (inferior_ptid);
2416 tid = ptid_get_pid (inferior_ptid);
2419 msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
2420 if (errno == 0 && msr < 0)
2428 ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
2429 gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
2431 int sizeof_auxv_field = ppc_linux_target_wordsize ();
2432 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
2433 gdb_byte *ptr = *readptr;
2438 if (endptr - ptr < sizeof_auxv_field * 2)
2441 *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2442 ptr += sizeof_auxv_field;
2443 *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2444 ptr += sizeof_auxv_field;
2450 static const struct target_desc *
2451 ppc_linux_read_description (struct target_ops *ops)
2458 int tid = ptid_get_lwp (inferior_ptid);
2460 tid = ptid_get_pid (inferior_ptid);
2462 if (have_ptrace_getsetevrregs)
2464 struct gdb_evrregset_t evrregset;
2466 if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
2467 return tdesc_powerpc_e500l;
2469 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2470 Anything else needs to be reported. */
2471 else if (errno != EIO)
2472 perror_with_name (_("Unable to fetch SPE registers"));
2475 if (have_ptrace_getsetvsxregs)
2477 gdb_vsxregset_t vsxregset;
2479 if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
2482 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2483 Anything else needs to be reported. */
2484 else if (errno != EIO)
2485 perror_with_name (_("Unable to fetch VSX registers"));
2488 if (have_ptrace_getvrregs)
2490 gdb_vrregset_t vrregset;
2492 if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
2495 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2496 Anything else needs to be reported. */
2497 else if (errno != EIO)
2498 perror_with_name (_("Unable to fetch AltiVec registers"));
2501 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2502 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2503 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2504 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2505 half of the register are for Decimal Floating Point, we check if that
2506 feature is available to decide the size of the FPSCR. */
2507 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP)
2510 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL)
2513 if (ppc_linux_target_wordsize () == 8)
2516 return tdesc_powerpc_cell64l;
2518 return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
2521 ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
2523 return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
2527 return tdesc_powerpc_cell32l;
2529 return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
2531 return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
2533 return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l;
2536 void _initialize_ppc_linux_nat (void);
2539 _initialize_ppc_linux_nat (void)
2541 struct target_ops *t;
2543 /* Fill in the generic GNU/Linux methods. */
2544 t = linux_target ();
2546 /* Add our register access methods. */
2547 t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
2548 t->to_store_registers = ppc_linux_store_inferior_registers;
2550 /* Add our breakpoint/watchpoint methods. */
2551 t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint;
2552 t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint;
2553 t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint;
2554 t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
2555 t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
2556 t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
2557 t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint;
2558 t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint;
2559 t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
2560 t->to_stopped_data_address = ppc_linux_stopped_data_address;
2561 t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
2562 t->to_can_accel_watchpoint_condition
2563 = ppc_linux_can_accel_watchpoint_condition;
2564 t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers;
2565 t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers;
2567 t->to_read_description = ppc_linux_read_description;
2568 t->to_auxv_parse = ppc_linux_auxv_parse;
2570 observer_attach_thread_exit (ppc_linux_thread_exit);
2572 /* Register the target. */
2573 linux_nat_add_target (t);
2574 linux_nat_set_new_thread (t, ppc_linux_new_thread);