1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "observable.h"
24 #include "gdbthread.h"
29 #include "linux-nat.h"
30 #include <sys/types.h>
33 #include <sys/ioctl.h>
36 #include <sys/procfs.h>
37 #include "nat/gdb_ptrace.h"
38 #include "inf-ptrace.h"
40 /* Prototypes for supply_gregset etc. */
43 #include "ppc-linux-tdep.h"
45 /* Required when using the AUXV. */
46 #include "elf/common.h"
49 #include "arch/ppc-linux-common.h"
50 #include "arch/ppc-linux-tdesc.h"
51 #include "nat/ppc-linux.h"
53 /* Similarly for the hardware watchpoint support. These requests are used
54 when the PowerPC HWDEBUG ptrace interface is not available. */
55 #ifndef PTRACE_GET_DEBUGREG
56 #define PTRACE_GET_DEBUGREG 25
58 #ifndef PTRACE_SET_DEBUGREG
59 #define PTRACE_SET_DEBUGREG 26
61 #ifndef PTRACE_GETSIGINFO
62 #define PTRACE_GETSIGINFO 0x4202
65 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
66 available. It exposes the debug facilities of PowerPC processors, as well
67 as additional features of BookE processors, such as ranged breakpoints and
68 watchpoints and hardware-accelerated condition evaluation. */
69 #ifndef PPC_PTRACE_GETHWDBGINFO
71 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
72 ptrace interface is not present in ptrace.h, so we'll have to pretty much
73 include it all here so that the code at least compiles on older systems. */
74 #define PPC_PTRACE_GETHWDBGINFO 0x89
75 #define PPC_PTRACE_SETHWDEBUG 0x88
76 #define PPC_PTRACE_DELHWDEBUG 0x87
80 uint32_t version; /* Only version 1 exists to date. */
81 uint32_t num_instruction_bps;
82 uint32_t num_data_bps;
83 uint32_t num_condition_regs;
84 uint32_t data_bp_alignment;
85 uint32_t sizeof_condition; /* size of the DVC register. */
89 /* Features will have bits indicating whether there is support for: */
90 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
91 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
92 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
93 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
95 struct ppc_hw_breakpoint
97 uint32_t version; /* currently, version must be 1 */
98 uint32_t trigger_type; /* only some combinations allowed */
99 uint32_t addr_mode; /* address match mode */
100 uint32_t condition_mode; /* break/watchpoint condition flags */
101 uint64_t addr; /* break/watchpoint address */
102 uint64_t addr2; /* range end or mask */
103 uint64_t condition_value; /* contents of the DVC register */
107 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
108 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
109 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
110 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
113 #define PPC_BREAKPOINT_MODE_EXACT 0x0
114 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
115 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
116 #define PPC_BREAKPOINT_MODE_MASK 0x3
118 /* Condition mode. */
119 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
120 #define PPC_BREAKPOINT_CONDITION_AND 0x1
121 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
122 #define PPC_BREAKPOINT_CONDITION_OR 0x2
123 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
124 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
125 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
126 #define PPC_BREAKPOINT_CONDITION_BE(n) \
127 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
128 #endif /* PPC_PTRACE_GETHWDBGINFO */
130 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
131 watchpoint (up to 512 bytes). */
132 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
133 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
134 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
136 /* Similarly for the general-purpose (gp0 -- gp31)
137 and floating-point registers (fp0 -- fp31). */
138 #ifndef PTRACE_GETREGS
139 #define PTRACE_GETREGS 12
141 #ifndef PTRACE_SETREGS
142 #define PTRACE_SETREGS 13
144 #ifndef PTRACE_GETFPREGS
145 #define PTRACE_GETFPREGS 14
147 #ifndef PTRACE_SETFPREGS
148 #define PTRACE_SETFPREGS 15
151 /* This oddity is because the Linux kernel defines elf_vrregset_t as
152 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
153 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
154 the vrsave as an extra 4 bytes at the end. I opted for creating a
155 flat array of chars, so that it is easier to manipulate for gdb.
157 There are 32 vector registers 16 bytes longs, plus a VSCR register
158 which is only 4 bytes long, but is fetched as a 16 bytes
159 quantity. Up to here we have the elf_vrregset_t structure.
160 Appended to this there is space for the VRSAVE register: 4 bytes.
161 Even though this vrsave register is not included in the regset
162 typedef, it is handled by the ptrace requests.
164 The layout is like this (where x is the actual value of the vscr reg): */
169 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
170 <-------> <-------><-------><->
173 |.|.|.|.|.....|.|.|.|.||X|.|.|.||.|
174 <-------> <-------><-------><->
179 typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET];
181 /* This is the layout of the POWER7 VSX registers and the way they overlap
182 with the existing FPR and VMX registers.
184 VSR doubleword 0 VSR doubleword 1
185 ----------------------------------------------------------------
187 ----------------------------------------------------------------
189 ----------------------------------------------------------------
192 ----------------------------------------------------------------
193 VSR[30] | FPR[30] | |
194 ----------------------------------------------------------------
195 VSR[31] | FPR[31] | |
196 ----------------------------------------------------------------
198 ----------------------------------------------------------------
200 ----------------------------------------------------------------
203 ----------------------------------------------------------------
205 ----------------------------------------------------------------
207 ----------------------------------------------------------------
209 VSX has 64 128bit registers. The first 32 registers overlap with
210 the FP registers (doubleword 0) and hence extend them with additional
211 64 bits (doubleword 1). The other 32 regs overlap with the VMX
213 typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET];
215 /* On PPC processors that support the Signal Processing Extension
216 (SPE) APU, the general-purpose registers are 64 bits long.
217 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
218 ptrace calls only access the lower half of each register, to allow
219 them to behave the same way they do on non-SPE systems. There's a
220 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
221 read and write the top halves of all the general-purpose registers
222 at once, along with some SPE-specific registers.
224 GDB itself continues to claim the general-purpose registers are 32
225 bits long. It has unnamed raw registers that hold the upper halves
226 of the gprs, and the full 64-bit SIMD views of the registers,
227 'ev0' -- 'ev31', are pseudo-registers that splice the top and
228 bottom halves together.
230 This is the structure filled in by PTRACE_GETEVRREGS and written to
231 the inferior's registers by PTRACE_SETEVRREGS. */
232 struct gdb_evrregset_t
234 unsigned long evr[32];
235 unsigned long long acc;
236 unsigned long spefscr;
239 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
240 PTRACE_SETVSXREGS requests, for reading and writing the VSX
241 POWER7 registers 0 through 31. Zero if we've tried one of them and
242 gotten an error. Note that VSX registers 32 through 63 overlap
243 with VR registers 0 through 31. */
244 int have_ptrace_getsetvsxregs = 1;
246 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
247 PTRACE_SETVRREGS requests, for reading and writing the Altivec
248 registers. Zero if we've tried one of them and gotten an
250 int have_ptrace_getvrregs = 1;
252 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
253 PTRACE_SETEVRREGS requests, for reading and writing the SPE
254 registers. Zero if we've tried one of them and gotten an
256 int have_ptrace_getsetevrregs = 1;
258 /* Non-zero if our kernel may support the PTRACE_GETREGS and
259 PTRACE_SETREGS requests, for reading and writing the
260 general-purpose registers. Zero if we've tried one of
261 them and gotten an error. */
262 int have_ptrace_getsetregs = 1;
264 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
265 PTRACE_SETFPREGS requests, for reading and writing the
266 floating-pointers registers. Zero if we've tried one of
267 them and gotten an error. */
268 int have_ptrace_getsetfpregs = 1;
270 struct ppc_linux_nat_target final : public linux_nat_target
272 /* Add our register access methods. */
273 void fetch_registers (struct regcache *, int) override;
274 void store_registers (struct regcache *, int) override;
276 /* Add our breakpoint/watchpoint methods. */
277 int can_use_hw_breakpoint (enum bptype, int, int) override;
279 int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *)
282 int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *)
285 int region_ok_for_hw_watchpoint (CORE_ADDR, int) override;
287 int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
288 struct expression *) override;
290 int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
291 struct expression *) override;
293 int insert_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type)
296 int remove_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type)
299 bool stopped_by_watchpoint () override;
301 bool stopped_data_address (CORE_ADDR *) override;
303 bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override;
305 bool can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *)
308 int masked_watch_num_registers (CORE_ADDR, CORE_ADDR) override;
310 int ranged_break_num_registers () override;
312 const struct target_desc *read_description () override;
314 int auxv_parse (gdb_byte **readptr,
315 gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
318 /* Override linux_nat_target low methods. */
319 void low_new_thread (struct lwp_info *lp) override;
322 static ppc_linux_nat_target the_ppc_linux_nat_target;
325 /* registers layout, as presented by the ptrace interface:
326 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
327 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
328 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
329 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
330 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
331 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
332 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
333 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
334 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
335 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
336 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
337 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
338 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
342 ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
345 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
346 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
347 interface, and not the wordsize of the program's ABI. */
348 int wordsize = sizeof (long);
350 /* General purpose registers occupy 1 slot each in the buffer. */
351 if (regno >= tdep->ppc_gp0_regnum
352 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
353 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
355 /* Floating point regs: eight bytes each in both 32- and 64-bit
356 ptrace interfaces. Thus, two slots each in 32-bit interface, one
357 slot each in 64-bit interface. */
358 if (tdep->ppc_fp0_regnum >= 0
359 && regno >= tdep->ppc_fp0_regnum
360 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
361 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
363 /* UISA special purpose registers: 1 slot each. */
364 if (regno == gdbarch_pc_regnum (gdbarch))
365 u_addr = PT_NIP * wordsize;
366 if (regno == tdep->ppc_lr_regnum)
367 u_addr = PT_LNK * wordsize;
368 if (regno == tdep->ppc_cr_regnum)
369 u_addr = PT_CCR * wordsize;
370 if (regno == tdep->ppc_xer_regnum)
371 u_addr = PT_XER * wordsize;
372 if (regno == tdep->ppc_ctr_regnum)
373 u_addr = PT_CTR * wordsize;
375 if (regno == tdep->ppc_mq_regnum)
376 u_addr = PT_MQ * wordsize;
378 if (regno == tdep->ppc_ps_regnum)
379 u_addr = PT_MSR * wordsize;
380 if (regno == PPC_ORIG_R3_REGNUM)
381 u_addr = PT_ORIG_R3 * wordsize;
382 if (regno == PPC_TRAP_REGNUM)
383 u_addr = PT_TRAP * wordsize;
384 if (tdep->ppc_fpscr_regnum >= 0
385 && regno == tdep->ppc_fpscr_regnum)
387 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
388 kernel headers incorrectly contained the 32-bit definition of
389 PT_FPSCR. For the 32-bit definition, floating-point
390 registers occupy two 32-bit "slots", and the FPSCR lives in
391 the second half of such a slot-pair (hence +1). For 64-bit,
392 the FPSCR instead occupies the full 64-bit 2-word-slot and
393 hence no adjustment is necessary. Hack around this. */
394 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
395 u_addr = (48 + 32) * wordsize;
396 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
397 slot and not just its second word. The PT_FPSCR supplied when
398 GDB is compiled as a 32-bit app doesn't reflect this. */
399 else if (wordsize == 4 && register_size (gdbarch, regno) == 8
400 && PT_FPSCR == (48 + 2*32 + 1))
401 u_addr = (48 + 2*32) * wordsize;
403 u_addr = PT_FPSCR * wordsize;
408 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
409 registers set mechanism, as opposed to the interface for all the
410 other registers, that stores/fetches each register individually. */
412 fetch_vsx_register (struct regcache *regcache, int tid, int regno)
415 gdb_vsxregset_t regs;
416 struct gdbarch *gdbarch = regcache->arch ();
417 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
418 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
420 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
425 have_ptrace_getsetvsxregs = 0;
428 perror_with_name (_("Unable to fetch VSX register"));
431 regcache_raw_supply (regcache, regno,
432 regs + (regno - tdep->ppc_vsr0_upper_regnum)
436 /* The Linux kernel ptrace interface for AltiVec registers uses the
437 registers set mechanism, as opposed to the interface for all the
438 other registers, that stores/fetches each register individually. */
440 fetch_altivec_registers (struct regcache *regcache, int tid,
445 struct gdbarch *gdbarch = regcache->arch ();
446 const struct regset *vrregset = ppc_linux_vrregset (gdbarch);
448 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
453 have_ptrace_getvrregs = 0;
456 perror_with_name (_("Unable to fetch AltiVec registers"));
459 vrregset->supply_regset (vrregset, regcache, regno, ®s,
460 PPC_LINUX_SIZEOF_VRREGSET);
463 /* Fetch the top 32 bits of TID's general-purpose registers and the
464 SPE-specific registers, and place the results in EVRREGSET. If we
465 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
468 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
469 PTRACE_SETEVRREGS requests are supported is isolated here, and in
470 set_spe_registers. */
472 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
474 if (have_ptrace_getsetevrregs)
476 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
480 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
481 we just return zeros. */
483 have_ptrace_getsetevrregs = 0;
485 /* Anything else needs to be reported. */
486 perror_with_name (_("Unable to fetch SPE registers"));
490 memset (evrregset, 0, sizeof (*evrregset));
493 /* Supply values from TID for SPE-specific raw registers: the upper
494 halves of the GPRs, the accumulator, and the spefscr. REGNO must
495 be the number of an upper half register, acc, spefscr, or -1 to
496 supply the values of all registers. */
498 fetch_spe_register (struct regcache *regcache, int tid, int regno)
500 struct gdbarch *gdbarch = regcache->arch ();
501 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
502 struct gdb_evrregset_t evrregs;
504 gdb_assert (sizeof (evrregs.evr[0])
505 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
506 gdb_assert (sizeof (evrregs.acc)
507 == register_size (gdbarch, tdep->ppc_acc_regnum));
508 gdb_assert (sizeof (evrregs.spefscr)
509 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
511 get_spe_registers (tid, &evrregs);
517 for (i = 0; i < ppc_num_gprs; i++)
518 regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
521 else if (tdep->ppc_ev0_upper_regnum <= regno
522 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
523 regcache_raw_supply (regcache, regno,
524 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
527 || regno == tdep->ppc_acc_regnum)
528 regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
531 || regno == tdep->ppc_spefscr_regnum)
532 regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
537 fetch_register (struct regcache *regcache, int tid, int regno)
539 struct gdbarch *gdbarch = regcache->arch ();
540 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
541 /* This isn't really an address. But ptrace thinks of it as one. */
542 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
543 int bytes_transferred;
544 unsigned int offset; /* Offset of registers within the u area. */
545 gdb_byte buf[PPC_MAX_REGISTER_SIZE];
547 if (altivec_register_p (gdbarch, regno))
549 /* If this is the first time through, or if it is not the first
550 time through, and we have comfirmed that there is kernel
551 support for such a ptrace request, then go and fetch the
553 if (have_ptrace_getvrregs)
555 fetch_altivec_registers (regcache, tid, regno);
558 /* If we have discovered that there is no ptrace support for
559 AltiVec registers, fall through and return zeroes, because
560 regaddr will be -1 in this case. */
562 if (vsx_register_p (gdbarch, regno))
564 if (have_ptrace_getsetvsxregs)
566 fetch_vsx_register (regcache, tid, regno);
570 else if (spe_register_p (gdbarch, regno))
572 fetch_spe_register (regcache, tid, regno);
578 memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
579 regcache_raw_supply (regcache, regno, buf);
583 /* Read the raw register using sizeof(long) sized chunks. On a
584 32-bit platform, 64-bit floating-point registers will require two
586 for (bytes_transferred = 0;
587 bytes_transferred < register_size (gdbarch, regno);
588 bytes_transferred += sizeof (long))
593 l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
594 regaddr += sizeof (long);
598 xsnprintf (message, sizeof (message), "reading register %s (#%d)",
599 gdbarch_register_name (gdbarch, regno), regno);
600 perror_with_name (message);
602 memcpy (&buf[bytes_transferred], &l, sizeof (l));
605 /* Now supply the register. Keep in mind that the regcache's idea
606 of the register's size may not be a multiple of sizeof
608 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
610 /* Little-endian values are always found at the left end of the
611 bytes transferred. */
612 regcache_raw_supply (regcache, regno, buf);
614 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
616 /* Big-endian values are found at the right end of the bytes
618 size_t padding = (bytes_transferred - register_size (gdbarch, regno));
619 regcache_raw_supply (regcache, regno, buf + padding);
622 internal_error (__FILE__, __LINE__,
623 _("fetch_register: unexpected byte order: %d"),
624 gdbarch_byte_order (gdbarch));
628 supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
631 struct gdbarch *gdbarch = regcache->arch ();
632 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
633 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
635 for (i = 0; i < ppc_num_vshrs; i++)
637 regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
638 *vsxregsetp + i * vsxregsize);
643 fetch_vsx_registers (struct regcache *regcache, int tid)
646 gdb_vsxregset_t regs;
648 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
653 have_ptrace_getsetvsxregs = 0;
656 perror_with_name (_("Unable to fetch VSX registers"));
658 supply_vsxregset (regcache, ®s);
661 /* This function actually issues the request to ptrace, telling
662 it to get all general-purpose registers and put them into the
665 If the ptrace request does not exist, this function returns 0
666 and properly sets the have_ptrace_* flag. If the request fails,
667 this function calls perror_with_name. Otherwise, if the request
668 succeeds, then the regcache gets filled and 1 is returned. */
670 fetch_all_gp_regs (struct regcache *regcache, int tid)
672 struct gdbarch *gdbarch = regcache->arch ();
673 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
674 gdb_gregset_t gregset;
676 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
680 have_ptrace_getsetregs = 0;
683 perror_with_name (_("Couldn't get general-purpose registers."));
686 supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
691 /* This is a wrapper for the fetch_all_gp_regs function. It is
692 responsible for verifying if this target has the ptrace request
693 that can be used to fetch all general-purpose registers at one
694 shot. If it doesn't, then we should fetch them using the
695 old-fashioned way, which is to iterate over the registers and
696 request them one by one. */
698 fetch_gp_regs (struct regcache *regcache, int tid)
700 struct gdbarch *gdbarch = regcache->arch ();
701 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
704 if (have_ptrace_getsetregs)
705 if (fetch_all_gp_regs (regcache, tid))
708 /* If we've hit this point, it doesn't really matter which
709 architecture we are using. We just need to read the
710 registers in the "old-fashioned way". */
711 for (i = 0; i < ppc_num_gprs; i++)
712 fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
715 /* This function actually issues the request to ptrace, telling
716 it to get all floating-point registers and put them into the
719 If the ptrace request does not exist, this function returns 0
720 and properly sets the have_ptrace_* flag. If the request fails,
721 this function calls perror_with_name. Otherwise, if the request
722 succeeds, then the regcache gets filled and 1 is returned. */
724 fetch_all_fp_regs (struct regcache *regcache, int tid)
726 gdb_fpregset_t fpregs;
728 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
732 have_ptrace_getsetfpregs = 0;
735 perror_with_name (_("Couldn't get floating-point registers."));
738 supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs);
743 /* This is a wrapper for the fetch_all_fp_regs function. It is
744 responsible for verifying if this target has the ptrace request
745 that can be used to fetch all floating-point registers at one
746 shot. If it doesn't, then we should fetch them using the
747 old-fashioned way, which is to iterate over the registers and
748 request them one by one. */
750 fetch_fp_regs (struct regcache *regcache, int tid)
752 struct gdbarch *gdbarch = regcache->arch ();
753 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
756 if (have_ptrace_getsetfpregs)
757 if (fetch_all_fp_regs (regcache, tid))
760 /* If we've hit this point, it doesn't really matter which
761 architecture we are using. We just need to read the
762 registers in the "old-fashioned way". */
763 for (i = 0; i < ppc_num_fprs; i++)
764 fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
768 fetch_ppc_registers (struct regcache *regcache, int tid)
771 struct gdbarch *gdbarch = regcache->arch ();
772 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
774 fetch_gp_regs (regcache, tid);
775 if (tdep->ppc_fp0_regnum >= 0)
776 fetch_fp_regs (regcache, tid);
777 fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
778 if (tdep->ppc_ps_regnum != -1)
779 fetch_register (regcache, tid, tdep->ppc_ps_regnum);
780 if (tdep->ppc_cr_regnum != -1)
781 fetch_register (regcache, tid, tdep->ppc_cr_regnum);
782 if (tdep->ppc_lr_regnum != -1)
783 fetch_register (regcache, tid, tdep->ppc_lr_regnum);
784 if (tdep->ppc_ctr_regnum != -1)
785 fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
786 if (tdep->ppc_xer_regnum != -1)
787 fetch_register (regcache, tid, tdep->ppc_xer_regnum);
788 if (tdep->ppc_mq_regnum != -1)
789 fetch_register (regcache, tid, tdep->ppc_mq_regnum);
790 if (ppc_linux_trap_reg_p (gdbarch))
792 fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
793 fetch_register (regcache, tid, PPC_TRAP_REGNUM);
795 if (tdep->ppc_fpscr_regnum != -1)
796 fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
797 if (have_ptrace_getvrregs)
798 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
799 fetch_altivec_registers (regcache, tid, -1);
800 if (have_ptrace_getsetvsxregs)
801 if (tdep->ppc_vsr0_upper_regnum != -1)
802 fetch_vsx_registers (regcache, tid);
803 if (tdep->ppc_ev0_upper_regnum >= 0)
804 fetch_spe_register (regcache, tid, -1);
807 /* Fetch registers from the child process. Fetch all registers if
808 regno == -1, otherwise fetch all general registers or all floating
809 point registers depending upon the value of regno. */
811 ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno)
813 pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache));
816 fetch_ppc_registers (regcache, tid);
818 fetch_register (regcache, tid, regno);
821 /* Store one VSX register. */
823 store_vsx_register (const struct regcache *regcache, int tid, int regno)
826 gdb_vsxregset_t regs;
827 struct gdbarch *gdbarch = regcache->arch ();
828 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
829 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
831 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
836 have_ptrace_getsetvsxregs = 0;
839 perror_with_name (_("Unable to fetch VSX register"));
842 regcache_raw_collect (regcache, regno, regs +
843 (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
845 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s);
847 perror_with_name (_("Unable to store VSX register"));
851 store_altivec_registers (const struct regcache *regcache, int tid,
856 struct gdbarch *gdbarch = regcache->arch ();
857 const struct regset *vrregset = ppc_linux_vrregset (gdbarch);
859 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
864 have_ptrace_getvrregs = 0;
867 perror_with_name (_("Unable to fetch AltiVec registers"));
870 vrregset->collect_regset (vrregset, regcache, regno, ®s,
871 PPC_LINUX_SIZEOF_VRREGSET);
873 ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s);
875 perror_with_name (_("Unable to store AltiVec registers"));
878 /* Assuming TID referrs to an SPE process, set the top halves of TID's
879 general-purpose registers and its SPE-specific registers to the
880 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
883 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
884 PTRACE_SETEVRREGS requests are supported is isolated here, and in
885 get_spe_registers. */
887 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
889 if (have_ptrace_getsetevrregs)
891 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
895 /* EIO means that the PTRACE_SETEVRREGS request isn't
896 supported; we fail silently, and don't try the call
899 have_ptrace_getsetevrregs = 0;
901 /* Anything else needs to be reported. */
902 perror_with_name (_("Unable to set SPE registers"));
907 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
908 If REGNO is -1, write the values of all the SPE-specific
911 store_spe_register (const struct regcache *regcache, int tid, int regno)
913 struct gdbarch *gdbarch = regcache->arch ();
914 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
915 struct gdb_evrregset_t evrregs;
917 gdb_assert (sizeof (evrregs.evr[0])
918 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
919 gdb_assert (sizeof (evrregs.acc)
920 == register_size (gdbarch, tdep->ppc_acc_regnum));
921 gdb_assert (sizeof (evrregs.spefscr)
922 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
925 /* Since we're going to write out every register, the code below
926 should store to every field of evrregs; if that doesn't happen,
927 make it obvious by initializing it with suspicious values. */
928 memset (&evrregs, 42, sizeof (evrregs));
930 /* We can only read and write the entire EVR register set at a
931 time, so to write just a single register, we do a
932 read-modify-write maneuver. */
933 get_spe_registers (tid, &evrregs);
939 for (i = 0; i < ppc_num_gprs; i++)
940 regcache_raw_collect (regcache,
941 tdep->ppc_ev0_upper_regnum + i,
944 else if (tdep->ppc_ev0_upper_regnum <= regno
945 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
946 regcache_raw_collect (regcache, regno,
947 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
950 || regno == tdep->ppc_acc_regnum)
951 regcache_raw_collect (regcache,
952 tdep->ppc_acc_regnum,
956 || regno == tdep->ppc_spefscr_regnum)
957 regcache_raw_collect (regcache,
958 tdep->ppc_spefscr_regnum,
961 /* Write back the modified register set. */
962 set_spe_registers (tid, &evrregs);
966 store_register (const struct regcache *regcache, int tid, int regno)
968 struct gdbarch *gdbarch = regcache->arch ();
969 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
970 /* This isn't really an address. But ptrace thinks of it as one. */
971 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
973 size_t bytes_to_transfer;
974 gdb_byte buf[PPC_MAX_REGISTER_SIZE];
976 if (altivec_register_p (gdbarch, regno))
978 store_altivec_registers (regcache, tid, regno);
981 if (vsx_register_p (gdbarch, regno))
983 store_vsx_register (regcache, tid, regno);
986 else if (spe_register_p (gdbarch, regno))
988 store_spe_register (regcache, tid, regno);
995 /* First collect the register. Keep in mind that the regcache's
996 idea of the register's size may not be a multiple of sizeof
998 memset (buf, 0, sizeof buf);
999 bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
1000 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1002 /* Little-endian values always sit at the left end of the buffer. */
1003 regcache_raw_collect (regcache, regno, buf);
1005 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1007 /* Big-endian values sit at the right end of the buffer. */
1008 size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
1009 regcache_raw_collect (regcache, regno, buf + padding);
1012 for (i = 0; i < bytes_to_transfer; i += sizeof (long))
1016 memcpy (&l, &buf[i], sizeof (l));
1018 ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
1019 regaddr += sizeof (long);
1022 && (regno == tdep->ppc_fpscr_regnum
1023 || regno == PPC_ORIG_R3_REGNUM
1024 || regno == PPC_TRAP_REGNUM))
1026 /* Some older kernel versions don't allow fpscr, orig_r3
1027 or trap to be written. */
1034 xsnprintf (message, sizeof (message), "writing register %s (#%d)",
1035 gdbarch_register_name (gdbarch, regno), regno);
1036 perror_with_name (message);
1042 fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
1045 struct gdbarch *gdbarch = regcache->arch ();
1046 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1047 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
1049 for (i = 0; i < ppc_num_vshrs; i++)
1050 regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
1051 *vsxregsetp + i * vsxregsize);
1055 store_vsx_registers (const struct regcache *regcache, int tid)
1058 gdb_vsxregset_t regs;
1060 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
1065 have_ptrace_getsetvsxregs = 0;
1068 perror_with_name (_("Couldn't get VSX registers"));
1071 fill_vsxregset (regcache, ®s);
1073 if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0)
1074 perror_with_name (_("Couldn't write VSX registers"));
1077 /* This function actually issues the request to ptrace, telling
1078 it to store all general-purpose registers present in the specified
1081 If the ptrace request does not exist, this function returns 0
1082 and properly sets the have_ptrace_* flag. If the request fails,
1083 this function calls perror_with_name. Otherwise, if the request
1084 succeeds, then the regcache is stored and 1 is returned. */
1086 store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
1088 struct gdbarch *gdbarch = regcache->arch ();
1089 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1090 gdb_gregset_t gregset;
1092 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
1096 have_ptrace_getsetregs = 0;
1099 perror_with_name (_("Couldn't get general-purpose registers."));
1102 fill_gregset (regcache, &gregset, regno);
1104 if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
1108 have_ptrace_getsetregs = 0;
1111 perror_with_name (_("Couldn't set general-purpose registers."));
1117 /* This is a wrapper for the store_all_gp_regs function. It is
1118 responsible for verifying if this target has the ptrace request
1119 that can be used to store all general-purpose registers at one
1120 shot. If it doesn't, then we should store them using the
1121 old-fashioned way, which is to iterate over the registers and
1122 store them one by one. */
1124 store_gp_regs (const struct regcache *regcache, int tid, int regno)
1126 struct gdbarch *gdbarch = regcache->arch ();
1127 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1130 if (have_ptrace_getsetregs)
1131 if (store_all_gp_regs (regcache, tid, regno))
1134 /* If we hit this point, it doesn't really matter which
1135 architecture we are using. We just need to store the
1136 registers in the "old-fashioned way". */
1137 for (i = 0; i < ppc_num_gprs; i++)
1138 store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
1141 /* This function actually issues the request to ptrace, telling
1142 it to store all floating-point registers present in the specified
1145 If the ptrace request does not exist, this function returns 0
1146 and properly sets the have_ptrace_* flag. If the request fails,
1147 this function calls perror_with_name. Otherwise, if the request
1148 succeeds, then the regcache is stored and 1 is returned. */
1150 store_all_fp_regs (const struct regcache *regcache, int tid, int regno)
1152 gdb_fpregset_t fpregs;
1154 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
1158 have_ptrace_getsetfpregs = 0;
1161 perror_with_name (_("Couldn't get floating-point registers."));
1164 fill_fpregset (regcache, &fpregs, regno);
1166 if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
1170 have_ptrace_getsetfpregs = 0;
1173 perror_with_name (_("Couldn't set floating-point registers."));
1179 /* This is a wrapper for the store_all_fp_regs function. It is
1180 responsible for verifying if this target has the ptrace request
1181 that can be used to store all floating-point registers at one
1182 shot. If it doesn't, then we should store them using the
1183 old-fashioned way, which is to iterate over the registers and
1184 store them one by one. */
1186 store_fp_regs (const struct regcache *regcache, int tid, int regno)
1188 struct gdbarch *gdbarch = regcache->arch ();
1189 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1192 if (have_ptrace_getsetfpregs)
1193 if (store_all_fp_regs (regcache, tid, regno))
1196 /* If we hit this point, it doesn't really matter which
1197 architecture we are using. We just need to store the
1198 registers in the "old-fashioned way". */
1199 for (i = 0; i < ppc_num_fprs; i++)
1200 store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
1204 store_ppc_registers (const struct regcache *regcache, int tid)
1207 struct gdbarch *gdbarch = regcache->arch ();
1208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1210 store_gp_regs (regcache, tid, -1);
1211 if (tdep->ppc_fp0_regnum >= 0)
1212 store_fp_regs (regcache, tid, -1);
1213 store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
1214 if (tdep->ppc_ps_regnum != -1)
1215 store_register (regcache, tid, tdep->ppc_ps_regnum);
1216 if (tdep->ppc_cr_regnum != -1)
1217 store_register (regcache, tid, tdep->ppc_cr_regnum);
1218 if (tdep->ppc_lr_regnum != -1)
1219 store_register (regcache, tid, tdep->ppc_lr_regnum);
1220 if (tdep->ppc_ctr_regnum != -1)
1221 store_register (regcache, tid, tdep->ppc_ctr_regnum);
1222 if (tdep->ppc_xer_regnum != -1)
1223 store_register (regcache, tid, tdep->ppc_xer_regnum);
1224 if (tdep->ppc_mq_regnum != -1)
1225 store_register (regcache, tid, tdep->ppc_mq_regnum);
1226 if (tdep->ppc_fpscr_regnum != -1)
1227 store_register (regcache, tid, tdep->ppc_fpscr_regnum);
1228 if (ppc_linux_trap_reg_p (gdbarch))
1230 store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1231 store_register (regcache, tid, PPC_TRAP_REGNUM);
1233 if (have_ptrace_getvrregs)
1234 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1235 store_altivec_registers (regcache, tid, -1);
1236 if (have_ptrace_getsetvsxregs)
1237 if (tdep->ppc_vsr0_upper_regnum != -1)
1238 store_vsx_registers (regcache, tid);
1239 if (tdep->ppc_ev0_upper_regnum >= 0)
1240 store_spe_register (regcache, tid, -1);
1243 /* Fetch the AT_HWCAP entry from the aux vector. */
1244 static unsigned long
1245 ppc_linux_get_hwcap (void)
1249 if (target_auxv_search (target_stack, AT_HWCAP, &field))
1250 return (unsigned long) field;
1255 /* The cached DABR value, to install in new threads.
1256 This variable is used when the PowerPC HWDEBUG ptrace
1257 interface is not available. */
1258 static long saved_dabr_value;
1260 /* Global structure that will store information about the available
1261 features provided by the PowerPC HWDEBUG ptrace interface. */
1262 static struct ppc_debug_info hwdebug_info;
1264 /* Global variable that holds the maximum number of slots that the
1265 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1267 static size_t max_slots_number = 0;
1269 struct hw_break_tuple
1272 struct ppc_hw_breakpoint *hw_break;
1275 /* This is an internal VEC created to store information about *points inserted
1276 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1278 typedef struct thread_points
1280 /* The TID to which this *point relates. */
1282 /* Information about the *point, such as its address, type, etc.
1284 Each element inside this vector corresponds to a hardware
1285 breakpoint or watchpoint in the thread represented by TID. The maximum
1286 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1287 the tuple is NULL, then the position in the vector is free. */
1288 struct hw_break_tuple *hw_breaks;
1290 DEF_VEC_P (thread_points_p);
1292 VEC(thread_points_p) *ppc_threads = NULL;
1294 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1296 #define PPC_DEBUG_CURRENT_VERSION 1
1298 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1300 have_ptrace_hwdebug_interface (void)
1302 static int have_ptrace_hwdebug_interface = -1;
1304 if (have_ptrace_hwdebug_interface == -1)
1308 tid = ptid_get_lwp (inferior_ptid);
1310 tid = ptid_get_pid (inferior_ptid);
1312 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1313 if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0)
1315 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1316 provides any supported feature. */
1317 if (hwdebug_info.features != 0)
1319 have_ptrace_hwdebug_interface = 1;
1320 max_slots_number = hwdebug_info.num_instruction_bps
1321 + hwdebug_info.num_data_bps
1322 + hwdebug_info.num_condition_regs;
1323 return have_ptrace_hwdebug_interface;
1326 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1327 have_ptrace_hwdebug_interface = 0;
1328 memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info));
1331 return have_ptrace_hwdebug_interface;
1335 ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, int ot)
1337 int total_hw_wp, total_hw_bp;
1339 if (have_ptrace_hwdebug_interface ())
1341 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1342 available hardware watchpoints and breakpoints is stored at the
1343 hwdebug_info struct. */
1344 total_hw_bp = hwdebug_info.num_instruction_bps;
1345 total_hw_wp = hwdebug_info.num_data_bps;
1349 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1350 consider having 1 hardware watchpoint and no hardware breakpoints. */
1355 if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
1356 || type == bp_access_watchpoint || type == bp_watchpoint)
1358 if (cnt + ot > total_hw_wp)
1361 else if (type == bp_hardware_breakpoint)
1363 if (total_hw_bp == 0)
1365 /* No hardware breakpoint support. */
1368 if (cnt > total_hw_bp)
1372 if (!have_ptrace_hwdebug_interface ())
1375 ptid_t ptid = inferior_ptid;
1377 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1378 and whether the target has DABR. If either answer is no, the
1379 ptrace call will return -1. Fail in that case. */
1380 tid = ptid_get_lwp (ptid);
1382 tid = ptid_get_pid (ptid);
1384 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1392 ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
1394 /* Handle sub-8-byte quantities. */
1398 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1399 restrictions for watchpoints in the processors. In that case, we use that
1400 information to determine the hardcoded watchable region for
1402 if (have_ptrace_hwdebug_interface ())
1405 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1406 watchpoints and can watch any access within an arbitrary memory
1407 region. This is useful to watch arrays and structs, for instance. It
1408 takes two hardware watchpoints though. */
1410 && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE
1411 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1413 /* Check if the processor provides DAWR interface. */
1414 if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR)
1415 /* DAWR interface allows to watch up to 512 byte wide ranges which
1416 can't cross a 512 byte boundary. */
1419 region_size = hwdebug_info.data_bp_alignment;
1420 /* Server processors provide one hardware watchpoint and addr+len should
1421 fall in the watchable region provided by the ptrace interface. */
1423 && (addr + len > (addr & ~(region_size - 1)) + region_size))
1426 /* addr+len must fall in the 8 byte watchable region for DABR-based
1427 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1428 ptrace interface, DAC-based processors (i.e., embedded processors) will
1429 use addresses aligned to 4-bytes due to the way the read/write flags are
1430 passed in the old ptrace interface. */
1431 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1432 && (addr + len) > (addr & ~3) + 4)
1433 || (addr + len) > (addr & ~7) + 8)
1439 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1441 hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
1443 return (a->trigger_type == b->trigger_type
1444 && a->addr_mode == b->addr_mode
1445 && a->condition_mode == b->condition_mode
1446 && a->addr == b->addr
1447 && a->addr2 == b->addr2
1448 && a->condition_value == b->condition_value);
1451 /* This function can be used to retrieve a thread_points by the TID of the
1452 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1453 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1454 provided TID will be created and returned. */
1455 static struct thread_points *
1456 hwdebug_find_thread_points_by_tid (int tid, int alloc_new)
1459 struct thread_points *t;
1461 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
1467 /* Do we need to allocate a new point_item
1468 if the wanted one does not exist? */
1471 t = XNEW (struct thread_points);
1472 t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number);
1474 VEC_safe_push (thread_points_p, ppc_threads, t);
1480 /* This function is a generic wrapper that is responsible for inserting a
1481 *point (i.e., calling `ptrace' in order to issue the request to the
1482 kernel) and registering it internally in GDB. */
1484 hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid)
1488 gdb::unique_xmalloc_ptr<ppc_hw_breakpoint> p (XDUP (ppc_hw_breakpoint, b));
1489 struct hw_break_tuple *hw_breaks;
1490 struct thread_points *t;
1491 struct hw_break_tuple *tuple;
1494 slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ());
1496 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1498 /* Everything went fine, so we have to register this *point. */
1499 t = hwdebug_find_thread_points_by_tid (tid, 1);
1500 gdb_assert (t != NULL);
1501 hw_breaks = t->hw_breaks;
1503 /* Find a free element in the hw_breaks vector. */
1504 for (i = 0; i < max_slots_number; i++)
1505 if (hw_breaks[i].hw_break == NULL)
1507 hw_breaks[i].slot = slot;
1508 hw_breaks[i].hw_break = p.release ();
1512 gdb_assert (i != max_slots_number);
1515 /* This function is a generic wrapper that is responsible for removing a
1516 *point (i.e., calling `ptrace' in order to issue the request to the
1517 kernel), and unregistering it internally at GDB. */
1519 hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid)
1522 struct hw_break_tuple *hw_breaks;
1523 struct thread_points *t;
1525 t = hwdebug_find_thread_points_by_tid (tid, 0);
1526 gdb_assert (t != NULL);
1527 hw_breaks = t->hw_breaks;
1529 for (i = 0; i < max_slots_number; i++)
1530 if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b))
1533 gdb_assert (i != max_slots_number);
1535 /* We have to ignore ENOENT errors because the kernel implements hardware
1536 breakpoints/watchpoints as "one-shot", that is, they are automatically
1537 deleted when hit. */
1539 if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
1540 if (errno != ENOENT)
1541 perror_with_name (_("Unexpected error deleting "
1542 "breakpoint or watchpoint"));
1544 xfree (hw_breaks[i].hw_break);
1545 hw_breaks[i].hw_break = NULL;
1548 /* Return the number of registers needed for a ranged breakpoint. */
1551 ppc_linux_nat_target::ranged_break_num_registers ()
1553 return ((have_ptrace_hwdebug_interface ()
1554 && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)?
1558 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1559 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1562 ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch,
1563 struct bp_target_info *bp_tgt)
1565 struct lwp_info *lp;
1566 struct ppc_hw_breakpoint p;
1568 if (!have_ptrace_hwdebug_interface ())
1571 p.version = PPC_DEBUG_CURRENT_VERSION;
1572 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1573 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1574 p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address);
1575 p.condition_value = 0;
1579 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1581 /* The breakpoint will trigger if the address of the instruction is
1582 within the defined range, as follows: p.addr <= address < p.addr2. */
1583 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1587 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1592 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1598 ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch,
1599 struct bp_target_info *bp_tgt)
1601 struct lwp_info *lp;
1602 struct ppc_hw_breakpoint p;
1604 if (!have_ptrace_hwdebug_interface ())
1607 p.version = PPC_DEBUG_CURRENT_VERSION;
1608 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1609 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1610 p.addr = (uint64_t) bp_tgt->placed_address;
1611 p.condition_value = 0;
1615 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1617 /* The breakpoint will trigger if the address of the instruction is within
1618 the defined range, as follows: p.addr <= address < p.addr2. */
1619 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1623 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1628 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
1634 get_trigger_type (enum target_hw_bp_type type)
1638 if (type == hw_read)
1639 t = PPC_BREAKPOINT_TRIGGER_READ;
1640 else if (type == hw_write)
1641 t = PPC_BREAKPOINT_TRIGGER_WRITE;
1643 t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
1648 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1649 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1650 or hw_access for an access watchpoint. Returns 0 on success and throws
1651 an error on failure. */
1654 ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask,
1655 target_hw_bp_type rw)
1657 struct lwp_info *lp;
1658 struct ppc_hw_breakpoint p;
1660 gdb_assert (have_ptrace_hwdebug_interface ());
1662 p.version = PPC_DEBUG_CURRENT_VERSION;
1663 p.trigger_type = get_trigger_type (rw);
1664 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1665 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1668 p.condition_value = 0;
1671 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1676 /* Remove a masked watchpoint at ADDR with the mask MASK.
1677 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1678 or hw_access for an access watchpoint. Returns 0 on success and throws
1679 an error on failure. */
1682 ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask,
1683 target_hw_bp_type rw)
1685 struct lwp_info *lp;
1686 struct ppc_hw_breakpoint p;
1688 gdb_assert (have_ptrace_hwdebug_interface ());
1690 p.version = PPC_DEBUG_CURRENT_VERSION;
1691 p.trigger_type = get_trigger_type (rw);
1692 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1693 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1696 p.condition_value = 0;
1699 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
1704 /* Check whether we have at least one free DVC register. */
1706 can_use_watchpoint_cond_accel (void)
1708 struct thread_points *p;
1709 int tid = ptid_get_lwp (inferior_ptid);
1710 int cnt = hwdebug_info.num_condition_regs, i;
1711 CORE_ADDR tmp_value;
1713 if (!have_ptrace_hwdebug_interface () || cnt == 0)
1716 p = hwdebug_find_thread_points_by_tid (tid, 0);
1720 for (i = 0; i < max_slots_number; i++)
1721 if (p->hw_breaks[i].hw_break != NULL
1722 && (p->hw_breaks[i].hw_break->condition_mode
1723 != PPC_BREAKPOINT_CONDITION_NONE))
1726 /* There are no available slots now. */
1734 /* Calculate the enable bits and the contents of the Data Value Compare
1735 debug register present in BookE processors.
1737 ADDR is the address to be watched, LEN is the length of watched data
1738 and DATA_VALUE is the value which will trigger the watchpoint.
1739 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1740 CONDITION_VALUE will hold the value which should be put in the
1743 calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
1744 uint32_t *condition_mode, uint64_t *condition_value)
1746 int i, num_byte_enable, align_offset, num_bytes_off_dvc,
1747 rightmost_enabled_byte;
1748 CORE_ADDR addr_end_data, addr_end_dvc;
1750 /* The DVC register compares bytes within fixed-length windows which
1751 are word-aligned, with length equal to that of the DVC register.
1752 We need to calculate where our watch region is relative to that
1753 window and enable comparison of the bytes which fall within it. */
1755 align_offset = addr % hwdebug_info.sizeof_condition;
1756 addr_end_data = addr + len;
1757 addr_end_dvc = (addr - align_offset
1758 + hwdebug_info.sizeof_condition);
1759 num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
1760 addr_end_data - addr_end_dvc : 0;
1761 num_byte_enable = len - num_bytes_off_dvc;
1762 /* Here, bytes are numbered from right to left. */
1763 rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
1764 addr_end_dvc - addr_end_data : 0;
1766 *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
1767 for (i = 0; i < num_byte_enable; i++)
1769 |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
1771 /* Now we need to match the position within the DVC of the comparison
1772 value with where the watch region is relative to the window
1773 (i.e., the ALIGN_OFFSET). */
1775 *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
1776 << rightmost_enabled_byte * 8);
1779 /* Return the number of memory locations that need to be accessed to
1780 evaluate the expression which generated the given value chain.
1781 Returns -1 if there's any register access involved, or if there are
1782 other kinds of values which are not acceptable in a condition
1783 expression (e.g., lval_computed or lval_internalvar). */
1785 num_memory_accesses (const std::vector<value_ref_ptr> &chain)
1787 int found_memory_cnt = 0;
1789 /* The idea here is that evaluating an expression generates a series
1790 of values, one holding the value of every subexpression. (The
1791 expression a*b+c has five subexpressions: a, b, a*b, c, and
1792 a*b+c.) GDB's values hold almost enough information to establish
1793 the criteria given above --- they identify memory lvalues,
1794 register lvalues, computed values, etcetera. So we can evaluate
1795 the expression, and then scan the chain of values that leaves
1796 behind to determine the memory locations involved in the evaluation
1799 However, I don't think that the values returned by inferior
1800 function calls are special in any way. So this function may not
1801 notice that an expression contains an inferior function call.
1804 for (const value_ref_ptr &iter : chain)
1806 struct value *v = iter.get ();
1808 /* Constants and values from the history are fine. */
1809 if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
1811 else if (VALUE_LVAL (v) == lval_memory)
1813 /* A lazy memory lvalue is one that GDB never needed to fetch;
1814 we either just used its address (e.g., `a' in `a.b') or
1815 we never needed it at all (e.g., `a' in `a,b'). */
1816 if (!value_lazy (v))
1819 /* Other kinds of values are not fine. */
1824 return found_memory_cnt;
1827 /* Verifies whether the expression COND can be implemented using the
1828 DVC (Data Value Compare) register in BookE processors. The expression
1829 must test the watch value for equality with a constant expression.
1830 If the function returns 1, DATA_VALUE will contain the constant against
1831 which the watch value should be compared and LEN will contain the size
1834 check_condition (CORE_ADDR watch_addr, struct expression *cond,
1835 CORE_ADDR *data_value, int *len)
1837 int pc = 1, num_accesses_left, num_accesses_right;
1838 struct value *left_val, *right_val;
1839 std::vector<value_ref_ptr> left_chain, right_chain;
1841 if (cond->elts[0].opcode != BINOP_EQUAL)
1844 fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
1845 num_accesses_left = num_memory_accesses (left_chain);
1847 if (left_val == NULL || num_accesses_left < 0)
1850 fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
1851 num_accesses_right = num_memory_accesses (right_chain);
1853 if (right_val == NULL || num_accesses_right < 0)
1856 if (num_accesses_left == 1 && num_accesses_right == 0
1857 && VALUE_LVAL (left_val) == lval_memory
1858 && value_address (left_val) == watch_addr)
1860 *data_value = value_as_long (right_val);
1862 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1863 the same type as the memory region referenced by LEFT_VAL. */
1864 *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
1866 else if (num_accesses_left == 0 && num_accesses_right == 1
1867 && VALUE_LVAL (right_val) == lval_memory
1868 && value_address (right_val) == watch_addr)
1870 *data_value = value_as_long (left_val);
1872 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1873 the same type as the memory region referenced by RIGHT_VAL. */
1874 *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
1882 /* Return non-zero if the target is capable of using hardware to evaluate
1883 the condition expression, thus only triggering the watchpoint when it is
1886 ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len,
1888 struct expression *cond)
1890 CORE_ADDR data_value;
1892 return (have_ptrace_hwdebug_interface ()
1893 && hwdebug_info.num_condition_regs > 0
1894 && check_condition (addr, cond, &data_value, &len));
1897 /* Set up P with the parameters necessary to request a watchpoint covering
1898 LEN bytes starting at ADDR and if possible with condition expression COND
1899 evaluated by hardware. INSERT tells if we are creating a request for
1900 inserting or removing the watchpoint. */
1903 create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
1904 int len, enum target_hw_bp_type type,
1905 struct expression *cond, int insert)
1908 || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
1911 CORE_ADDR data_value;
1913 use_condition = (insert? can_use_watchpoint_cond_accel ()
1914 : hwdebug_info.num_condition_regs > 0);
1915 if (cond && use_condition && check_condition (addr, cond,
1917 calculate_dvc (addr, len, data_value, &p->condition_mode,
1918 &p->condition_value);
1921 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1922 p->condition_value = 0;
1925 p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1930 p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1931 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1932 p->condition_value = 0;
1934 /* The watchpoint will trigger if the address of the memory access is
1935 within the defined range, as follows: p->addr <= address < p->addr2.
1937 Note that the above sentence just documents how ptrace interprets
1938 its arguments; the watchpoint is set to watch the range defined by
1939 the user _inclusively_, as specified by the user interface. */
1940 p->addr2 = (uint64_t) addr + len;
1943 p->version = PPC_DEBUG_CURRENT_VERSION;
1944 p->trigger_type = get_trigger_type (type);
1945 p->addr = (uint64_t) addr;
1949 ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
1950 enum target_hw_bp_type type,
1951 struct expression *cond)
1953 struct lwp_info *lp;
1956 if (have_ptrace_hwdebug_interface ())
1958 struct ppc_hw_breakpoint p;
1960 create_watchpoint_request (&p, addr, len, type, cond, 1);
1963 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1970 long read_mode, write_mode;
1972 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1974 /* PowerPC 440 requires only the read/write flags to be passed
1981 /* PowerPC 970 and other DABR-based processors are required to pass
1982 the Breakpoint Translation bit together with the flags. */
1987 dabr_value = addr & ~(read_mode | write_mode);
1991 /* Set read and translate bits. */
1992 dabr_value |= read_mode;
1995 /* Set write and translate bits. */
1996 dabr_value |= write_mode;
1999 /* Set read, write and translate bits. */
2000 dabr_value |= read_mode | write_mode;
2004 saved_dabr_value = dabr_value;
2007 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
2008 saved_dabr_value) < 0)
2018 ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
2019 enum target_hw_bp_type type,
2020 struct expression *cond)
2022 struct lwp_info *lp;
2025 if (have_ptrace_hwdebug_interface ())
2027 struct ppc_hw_breakpoint p;
2029 create_watchpoint_request (&p, addr, len, type, cond, 0);
2032 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
2038 saved_dabr_value = 0;
2040 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
2041 saved_dabr_value) < 0)
2051 ppc_linux_nat_target::low_new_thread (struct lwp_info *lp)
2053 int tid = ptid_get_lwp (lp->ptid);
2055 if (have_ptrace_hwdebug_interface ())
2058 struct thread_points *p;
2059 struct hw_break_tuple *hw_breaks;
2061 if (VEC_empty (thread_points_p, ppc_threads))
2064 /* Get a list of breakpoints from any thread. */
2065 p = VEC_last (thread_points_p, ppc_threads);
2066 hw_breaks = p->hw_breaks;
2068 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2069 for (i = 0; i < max_slots_number; i++)
2070 if (hw_breaks[i].hw_break)
2072 /* Older kernels did not make new threads inherit their parent
2073 thread's debug state, so we always clear the slot and replicate
2074 the debug state ourselves, ensuring compatibility with all
2077 /* The ppc debug resource accounting is done through "slots".
2078 Ask the kernel the deallocate this specific *point's slot. */
2079 ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
2081 hwdebug_insert_point (hw_breaks[i].hw_break, tid);
2085 ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
2089 ppc_linux_thread_exit (struct thread_info *tp, int silent)
2092 int tid = ptid_get_lwp (tp->ptid);
2093 struct hw_break_tuple *hw_breaks;
2094 struct thread_points *t = NULL, *p;
2096 if (!have_ptrace_hwdebug_interface ())
2099 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
2109 VEC_unordered_remove (thread_points_p, ppc_threads, i);
2111 hw_breaks = t->hw_breaks;
2113 for (i = 0; i < max_slots_number; i++)
2114 if (hw_breaks[i].hw_break)
2115 xfree (hw_breaks[i].hw_break);
2117 xfree (t->hw_breaks);
2122 ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
2126 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
2129 if (siginfo.si_signo != SIGTRAP
2130 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2133 if (have_ptrace_hwdebug_interface ())
2136 struct thread_points *t;
2137 struct hw_break_tuple *hw_breaks;
2138 /* The index (or slot) of the *point is passed in the si_errno field. */
2139 int slot = siginfo.si_errno;
2141 t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0);
2143 /* Find out if this *point is a hardware breakpoint.
2144 If so, we should return 0. */
2147 hw_breaks = t->hw_breaks;
2148 for (i = 0; i < max_slots_number; i++)
2149 if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
2150 && hw_breaks[i].hw_break->trigger_type
2151 == PPC_BREAKPOINT_TRIGGER_EXECUTE)
2156 *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
2161 ppc_linux_nat_target::stopped_by_watchpoint ()
2164 return stopped_data_address (&addr);
2168 ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr,
2174 if (have_ptrace_hwdebug_interface ()
2175 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2176 return start <= addr && start + length >= addr;
2177 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2184 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2185 return start <= addr + mask && start + length - 1 >= addr;
2188 /* Return the number of registers needed for a masked hardware watchpoint. */
2191 ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask)
2193 if (!have_ptrace_hwdebug_interface ()
2194 || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0)
2196 else if ((mask & 0xC0000000) != 0xC0000000)
2198 warning (_("The given mask covers kernel address space "
2199 "and cannot be used.\n"));
2208 ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno)
2210 pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache));
2213 store_register (regcache, tid, regno);
2215 store_ppc_registers (regcache, tid);
2218 /* Functions for transferring registers between a gregset_t or fpregset_t
2219 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2220 by the ptrace interface, not the current program's ABI. Eg. if a
2221 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2222 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2225 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
2227 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2229 ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
2233 fill_gregset (const struct regcache *regcache,
2234 gdb_gregset_t *gregsetp, int regno)
2236 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2239 memset (gregsetp, 0, sizeof (*gregsetp));
2240 ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
2244 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
2246 const struct regset *regset = ppc_linux_fpregset ();
2248 ppc_supply_fpregset (regset, regcache, -1,
2249 fpregsetp, sizeof (*fpregsetp));
2253 fill_fpregset (const struct regcache *regcache,
2254 gdb_fpregset_t *fpregsetp, int regno)
2256 const struct regset *regset = ppc_linux_fpregset ();
2258 ppc_collect_fpregset (regset, regcache, regno,
2259 fpregsetp, sizeof (*fpregsetp));
2263 ppc_linux_nat_target::auxv_parse (gdb_byte **readptr,
2264 gdb_byte *endptr, CORE_ADDR *typep,
2267 int tid = ptid_get_lwp (inferior_ptid);
2269 tid = ptid_get_pid (inferior_ptid);
2271 int sizeof_auxv_field = ppc_linux_target_wordsize (tid);
2273 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
2274 gdb_byte *ptr = *readptr;
2279 if (endptr - ptr < sizeof_auxv_field * 2)
2282 *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2283 ptr += sizeof_auxv_field;
2284 *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2285 ptr += sizeof_auxv_field;
2291 const struct target_desc *
2292 ppc_linux_nat_target::read_description ()
2294 int tid = ptid_get_lwp (inferior_ptid);
2296 tid = ptid_get_pid (inferior_ptid);
2298 if (have_ptrace_getsetevrregs)
2300 struct gdb_evrregset_t evrregset;
2302 if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
2303 return tdesc_powerpc_e500l;
2305 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2306 Anything else needs to be reported. */
2307 else if (errno != EIO)
2308 perror_with_name (_("Unable to fetch SPE registers"));
2311 struct ppc_linux_features features = ppc_linux_no_features;
2313 features.wordsize = ppc_linux_target_wordsize (tid);
2315 unsigned long hwcap = ppc_linux_get_hwcap ();
2317 if (have_ptrace_getsetvsxregs
2318 && (hwcap & PPC_FEATURE_HAS_VSX))
2320 gdb_vsxregset_t vsxregset;
2322 if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
2323 features.vsx = true;
2325 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2326 Anything else needs to be reported. */
2327 else if (errno != EIO)
2328 perror_with_name (_("Unable to fetch VSX registers"));
2331 if (have_ptrace_getvrregs
2332 && (hwcap & PPC_FEATURE_HAS_ALTIVEC))
2334 gdb_vrregset_t vrregset;
2336 if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
2337 features.altivec = true;
2339 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2340 Anything else needs to be reported. */
2341 else if (errno != EIO)
2342 perror_with_name (_("Unable to fetch AltiVec registers"));
2345 if (hwcap & PPC_FEATURE_CELL)
2346 features.cell = true;
2348 features.isa205 = ppc_linux_has_isa205 (hwcap);
2350 return ppc_linux_match_description (features);
2354 _initialize_ppc_linux_nat (void)
2356 linux_target = &the_ppc_linux_nat_target;
2358 gdb::observers::thread_exit.attach (ppc_linux_thread_exit);
2360 /* Register the target. */
2361 add_inf_child_target (linux_target);