1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,
4 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "gdb_string.h"
27 #include "gdb_assert.h"
29 #include "linux-nat.h"
32 #include <sys/types.h>
33 #include <sys/param.h>
36 #include <sys/ioctl.h>
39 #include <sys/procfs.h>
40 #include <sys/ptrace.h>
42 /* Prototypes for supply_gregset etc. */
45 #include "ppc-linux-tdep.h"
47 /* Required when using the AUXV. */
48 #include "elf/common.h"
51 /* This sometimes isn't defined. */
59 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
60 If they aren't, we can provide them ourselves (their values are fixed
61 because they are part of the kernel ABI). They are used in the AT_HWCAP
63 #ifndef PPC_FEATURE_BOOKE
64 #define PPC_FEATURE_BOOKE 0x00008000
66 #ifndef PPC_FEATURE_HAS_DFP
67 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
70 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
71 configure time check. Some older glibc's (for instance 2.2.1)
72 don't have a specific powerpc version of ptrace.h, and fall back on
73 a generic one. In such cases, sys/ptrace.h defines
74 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
75 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
76 PTRACE_SETVRREGS to be. This also makes a configury check pretty
79 /* These definitions should really come from the glibc header files,
80 but Glibc doesn't know about the vrregs yet. */
81 #ifndef PTRACE_GETVRREGS
82 #define PTRACE_GETVRREGS 18
83 #define PTRACE_SETVRREGS 19
86 /* PTRACE requests for POWER7 VSX registers. */
87 #ifndef PTRACE_GETVSXREGS
88 #define PTRACE_GETVSXREGS 27
89 #define PTRACE_SETVSXREGS 28
92 /* Similarly for the ptrace requests for getting / setting the SPE
93 registers (ev0 -- ev31, acc, and spefscr). See the description of
94 gdb_evrregset_t for details. */
95 #ifndef PTRACE_GETEVRREGS
96 #define PTRACE_GETEVRREGS 20
97 #define PTRACE_SETEVRREGS 21
100 /* Similarly for the hardware watchpoint support. */
101 #ifndef PTRACE_GET_DEBUGREG
102 #define PTRACE_GET_DEBUGREG 25
104 #ifndef PTRACE_SET_DEBUGREG
105 #define PTRACE_SET_DEBUGREG 26
107 #ifndef PTRACE_GETSIGINFO
108 #define PTRACE_GETSIGINFO 0x4202
111 /* This oddity is because the Linux kernel defines elf_vrregset_t as
112 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
113 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
114 the vrsave as an extra 4 bytes at the end. I opted for creating a
115 flat array of chars, so that it is easier to manipulate for gdb.
117 There are 32 vector registers 16 bytes longs, plus a VSCR register
118 which is only 4 bytes long, but is fetched as a 16 bytes
119 quantity. Up to here we have the elf_vrregset_t structure.
120 Appended to this there is space for the VRSAVE register: 4 bytes.
121 Even though this vrsave register is not included in the regset
122 typedef, it is handled by the ptrace requests.
124 Note that GNU/Linux doesn't support little endian PPC hardware,
125 therefore the offset at which the real value of the VSCR register
126 is located will be always 12 bytes.
128 The layout is like this (where x is the actual value of the vscr reg): */
132 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
133 <-------> <-------><-------><->
138 #define SIZEOF_VRREGS 33*16+4
140 typedef char gdb_vrregset_t[SIZEOF_VRREGS];
142 /* This is the layout of the POWER7 VSX registers and the way they overlap
143 with the existing FPR and VMX registers.
145 VSR doubleword 0 VSR doubleword 1
146 ----------------------------------------------------------------
148 ----------------------------------------------------------------
150 ----------------------------------------------------------------
153 ----------------------------------------------------------------
154 VSR[30] | FPR[30] | |
155 ----------------------------------------------------------------
156 VSR[31] | FPR[31] | |
157 ----------------------------------------------------------------
159 ----------------------------------------------------------------
161 ----------------------------------------------------------------
164 ----------------------------------------------------------------
166 ----------------------------------------------------------------
168 ----------------------------------------------------------------
170 VSX has 64 128bit registers. The first 32 registers overlap with
171 the FP registers (doubleword 0) and hence extend them with additional
172 64 bits (doubleword 1). The other 32 regs overlap with the VMX
174 #define SIZEOF_VSXREGS 32*8
176 typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
178 /* On PPC processors that support the the Signal Processing Extension
179 (SPE) APU, the general-purpose registers are 64 bits long.
180 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
181 ptrace calls only access the lower half of each register, to allow
182 them to behave the same way they do on non-SPE systems. There's a
183 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
184 read and write the top halves of all the general-purpose registers
185 at once, along with some SPE-specific registers.
187 GDB itself continues to claim the general-purpose registers are 32
188 bits long. It has unnamed raw registers that hold the upper halves
189 of the gprs, and the the full 64-bit SIMD views of the registers,
190 'ev0' -- 'ev31', are pseudo-registers that splice the top and
191 bottom halves together.
193 This is the structure filled in by PTRACE_GETEVRREGS and written to
194 the inferior's registers by PTRACE_SETEVRREGS. */
195 struct gdb_evrregset_t
197 unsigned long evr[32];
198 unsigned long long acc;
199 unsigned long spefscr;
202 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
203 PTRACE_SETVSXREGS requests, for reading and writing the VSX
204 POWER7 registers 0 through 31. Zero if we've tried one of them and
205 gotten an error. Note that VSX registers 32 through 63 overlap
206 with VR registers 0 through 31. */
207 int have_ptrace_getsetvsxregs = 1;
209 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
210 PTRACE_SETVRREGS requests, for reading and writing the Altivec
211 registers. Zero if we've tried one of them and gotten an
213 int have_ptrace_getvrregs = 1;
215 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
216 PTRACE_SETEVRREGS requests, for reading and writing the SPE
217 registers. Zero if we've tried one of them and gotten an
219 int have_ptrace_getsetevrregs = 1;
222 /* registers layout, as presented by the ptrace interface:
223 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
224 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
225 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
226 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
227 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
228 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
229 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
230 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
231 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
235 ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
238 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
239 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
240 interface, and not the wordsize of the program's ABI. */
241 int wordsize = sizeof (long);
243 /* General purpose registers occupy 1 slot each in the buffer */
244 if (regno >= tdep->ppc_gp0_regnum
245 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
246 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
248 /* Floating point regs: eight bytes each in both 32- and 64-bit
249 ptrace interfaces. Thus, two slots each in 32-bit interface, one
250 slot each in 64-bit interface. */
251 if (tdep->ppc_fp0_regnum >= 0
252 && regno >= tdep->ppc_fp0_regnum
253 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
254 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
256 /* UISA special purpose registers: 1 slot each */
257 if (regno == gdbarch_pc_regnum (gdbarch))
258 u_addr = PT_NIP * wordsize;
259 if (regno == tdep->ppc_lr_regnum)
260 u_addr = PT_LNK * wordsize;
261 if (regno == tdep->ppc_cr_regnum)
262 u_addr = PT_CCR * wordsize;
263 if (regno == tdep->ppc_xer_regnum)
264 u_addr = PT_XER * wordsize;
265 if (regno == tdep->ppc_ctr_regnum)
266 u_addr = PT_CTR * wordsize;
268 if (regno == tdep->ppc_mq_regnum)
269 u_addr = PT_MQ * wordsize;
271 if (regno == tdep->ppc_ps_regnum)
272 u_addr = PT_MSR * wordsize;
273 if (regno == PPC_ORIG_R3_REGNUM)
274 u_addr = PT_ORIG_R3 * wordsize;
275 if (regno == PPC_TRAP_REGNUM)
276 u_addr = PT_TRAP * wordsize;
277 if (tdep->ppc_fpscr_regnum >= 0
278 && regno == tdep->ppc_fpscr_regnum)
280 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
281 kernel headers incorrectly contained the 32-bit definition of
282 PT_FPSCR. For the 32-bit definition, floating-point
283 registers occupy two 32-bit "slots", and the FPSCR lives in
284 the second half of such a slot-pair (hence +1). For 64-bit,
285 the FPSCR instead occupies the full 64-bit 2-word-slot and
286 hence no adjustment is necessary. Hack around this. */
287 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
288 u_addr = (48 + 32) * wordsize;
289 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
290 slot and not just its second word. The PT_FPSCR supplied when
291 GDB is compiled as a 32-bit app doesn't reflect this. */
292 else if (wordsize == 4 && register_size (gdbarch, regno) == 8
293 && PT_FPSCR == (48 + 2*32 + 1))
294 u_addr = (48 + 2*32) * wordsize;
296 u_addr = PT_FPSCR * wordsize;
301 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
302 registers set mechanism, as opposed to the interface for all the
303 other registers, that stores/fetches each register individually. */
305 fetch_vsx_register (struct regcache *regcache, int tid, int regno)
308 gdb_vsxregset_t regs;
309 struct gdbarch *gdbarch = get_regcache_arch (regcache);
310 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
311 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
313 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
318 have_ptrace_getsetvsxregs = 0;
321 perror_with_name (_("Unable to fetch VSX register"));
324 regcache_raw_supply (regcache, regno,
325 regs + (regno - tdep->ppc_vsr0_upper_regnum)
329 /* The Linux kernel ptrace interface for AltiVec registers uses the
330 registers set mechanism, as opposed to the interface for all the
331 other registers, that stores/fetches each register individually. */
333 fetch_altivec_register (struct regcache *regcache, int tid, int regno)
338 struct gdbarch *gdbarch = get_regcache_arch (regcache);
339 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
340 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
342 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
347 have_ptrace_getvrregs = 0;
350 perror_with_name (_("Unable to fetch AltiVec register"));
353 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
354 long on the hardware. We deal only with the lower 4 bytes of the
355 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
356 there is no need to define an offset for it. */
357 if (regno == (tdep->ppc_vrsave_regnum - 1))
358 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
360 regcache_raw_supply (regcache, regno,
361 regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
364 /* Fetch the top 32 bits of TID's general-purpose registers and the
365 SPE-specific registers, and place the results in EVRREGSET. If we
366 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
369 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
370 PTRACE_SETEVRREGS requests are supported is isolated here, and in
371 set_spe_registers. */
373 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
375 if (have_ptrace_getsetevrregs)
377 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
381 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
382 we just return zeros. */
384 have_ptrace_getsetevrregs = 0;
386 /* Anything else needs to be reported. */
387 perror_with_name (_("Unable to fetch SPE registers"));
391 memset (evrregset, 0, sizeof (*evrregset));
394 /* Supply values from TID for SPE-specific raw registers: the upper
395 halves of the GPRs, the accumulator, and the spefscr. REGNO must
396 be the number of an upper half register, acc, spefscr, or -1 to
397 supply the values of all registers. */
399 fetch_spe_register (struct regcache *regcache, int tid, int regno)
401 struct gdbarch *gdbarch = get_regcache_arch (regcache);
402 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
403 struct gdb_evrregset_t evrregs;
405 gdb_assert (sizeof (evrregs.evr[0])
406 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
407 gdb_assert (sizeof (evrregs.acc)
408 == register_size (gdbarch, tdep->ppc_acc_regnum));
409 gdb_assert (sizeof (evrregs.spefscr)
410 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
412 get_spe_registers (tid, &evrregs);
418 for (i = 0; i < ppc_num_gprs; i++)
419 regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
422 else if (tdep->ppc_ev0_upper_regnum <= regno
423 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
424 regcache_raw_supply (regcache, regno,
425 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
428 || regno == tdep->ppc_acc_regnum)
429 regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
432 || regno == tdep->ppc_spefscr_regnum)
433 regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
438 fetch_register (struct regcache *regcache, int tid, int regno)
440 struct gdbarch *gdbarch = get_regcache_arch (regcache);
441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
442 /* This isn't really an address. But ptrace thinks of it as one. */
443 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
444 int bytes_transferred;
445 unsigned int offset; /* Offset of registers within the u area. */
446 char buf[MAX_REGISTER_SIZE];
448 if (altivec_register_p (gdbarch, regno))
450 /* If this is the first time through, or if it is not the first
451 time through, and we have comfirmed that there is kernel
452 support for such a ptrace request, then go and fetch the
454 if (have_ptrace_getvrregs)
456 fetch_altivec_register (regcache, tid, regno);
459 /* If we have discovered that there is no ptrace support for
460 AltiVec registers, fall through and return zeroes, because
461 regaddr will be -1 in this case. */
463 if (vsx_register_p (gdbarch, regno))
465 if (have_ptrace_getsetvsxregs)
467 fetch_vsx_register (regcache, tid, regno);
471 else if (spe_register_p (gdbarch, regno))
473 fetch_spe_register (regcache, tid, regno);
479 memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
480 regcache_raw_supply (regcache, regno, buf);
484 /* Read the raw register using sizeof(long) sized chunks. On a
485 32-bit platform, 64-bit floating-point registers will require two
487 for (bytes_transferred = 0;
488 bytes_transferred < register_size (gdbarch, regno);
489 bytes_transferred += sizeof (long))
492 *(long *) &buf[bytes_transferred]
493 = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
494 regaddr += sizeof (long);
498 sprintf (message, "reading register %s (#%d)",
499 gdbarch_register_name (gdbarch, regno), regno);
500 perror_with_name (message);
504 /* Now supply the register. Keep in mind that the regcache's idea
505 of the register's size may not be a multiple of sizeof
507 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
509 /* Little-endian values are always found at the left end of the
510 bytes transferred. */
511 regcache_raw_supply (regcache, regno, buf);
513 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
515 /* Big-endian values are found at the right end of the bytes
517 size_t padding = (bytes_transferred - register_size (gdbarch, regno));
518 regcache_raw_supply (regcache, regno, buf + padding);
521 internal_error (__FILE__, __LINE__,
522 _("fetch_register: unexpected byte order: %d"),
523 gdbarch_byte_order (gdbarch));
527 supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
530 struct gdbarch *gdbarch = get_regcache_arch (regcache);
531 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
532 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
534 for (i = 0; i < ppc_num_vshrs; i++)
536 regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
537 *vsxregsetp + i * vsxregsize);
542 supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)
545 struct gdbarch *gdbarch = get_regcache_arch (regcache);
546 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
547 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
548 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
549 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
551 for (i = 0; i < num_of_vrregs; i++)
553 /* The last 2 registers of this set are only 32 bit long, not
554 128. However an offset is necessary only for VSCR because it
555 occupies a whole vector, while VRSAVE occupies a full 4 bytes
557 if (i == (num_of_vrregs - 2))
558 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
559 *vrregsetp + i * vrregsize + offset);
561 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
562 *vrregsetp + i * vrregsize);
567 fetch_vsx_registers (struct regcache *regcache, int tid)
570 gdb_vsxregset_t regs;
572 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
577 have_ptrace_getsetvsxregs = 0;
580 perror_with_name (_("Unable to fetch VSX registers"));
582 supply_vsxregset (regcache, ®s);
586 fetch_altivec_registers (struct regcache *regcache, int tid)
591 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
596 have_ptrace_getvrregs = 0;
599 perror_with_name (_("Unable to fetch AltiVec registers"));
601 supply_vrregset (regcache, ®s);
605 fetch_ppc_registers (struct regcache *regcache, int tid)
608 struct gdbarch *gdbarch = get_regcache_arch (regcache);
609 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
611 for (i = 0; i < ppc_num_gprs; i++)
612 fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
613 if (tdep->ppc_fp0_regnum >= 0)
614 for (i = 0; i < ppc_num_fprs; i++)
615 fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
616 fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
617 if (tdep->ppc_ps_regnum != -1)
618 fetch_register (regcache, tid, tdep->ppc_ps_regnum);
619 if (tdep->ppc_cr_regnum != -1)
620 fetch_register (regcache, tid, tdep->ppc_cr_regnum);
621 if (tdep->ppc_lr_regnum != -1)
622 fetch_register (regcache, tid, tdep->ppc_lr_regnum);
623 if (tdep->ppc_ctr_regnum != -1)
624 fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
625 if (tdep->ppc_xer_regnum != -1)
626 fetch_register (regcache, tid, tdep->ppc_xer_regnum);
627 if (tdep->ppc_mq_regnum != -1)
628 fetch_register (regcache, tid, tdep->ppc_mq_regnum);
629 if (ppc_linux_trap_reg_p (gdbarch))
631 fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
632 fetch_register (regcache, tid, PPC_TRAP_REGNUM);
634 if (tdep->ppc_fpscr_regnum != -1)
635 fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
636 if (have_ptrace_getvrregs)
637 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
638 fetch_altivec_registers (regcache, tid);
639 if (have_ptrace_getsetvsxregs)
640 if (tdep->ppc_vsr0_upper_regnum != -1)
641 fetch_vsx_registers (regcache, tid);
642 if (tdep->ppc_ev0_upper_regnum >= 0)
643 fetch_spe_register (regcache, tid, -1);
646 /* Fetch registers from the child process. Fetch all registers if
647 regno == -1, otherwise fetch all general registers or all floating
648 point registers depending upon the value of regno. */
650 ppc_linux_fetch_inferior_registers (struct target_ops *ops,
651 struct regcache *regcache, int regno)
653 /* Overload thread id onto process id */
654 int tid = TIDGET (inferior_ptid);
656 /* No thread id, just use process id */
658 tid = PIDGET (inferior_ptid);
661 fetch_ppc_registers (regcache, tid);
663 fetch_register (regcache, tid, regno);
666 /* Store one VSX register. */
668 store_vsx_register (const struct regcache *regcache, int tid, int regno)
671 gdb_vsxregset_t regs;
672 struct gdbarch *gdbarch = get_regcache_arch (regcache);
673 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
674 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
676 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s);
681 have_ptrace_getsetvsxregs = 0;
684 perror_with_name (_("Unable to fetch VSX register"));
687 regcache_raw_collect (regcache, regno, regs +
688 (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
690 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s);
692 perror_with_name (_("Unable to store VSX register"));
695 /* Store one register. */
697 store_altivec_register (const struct regcache *regcache, int tid, int regno)
702 struct gdbarch *gdbarch = get_regcache_arch (regcache);
703 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
704 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
706 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
711 have_ptrace_getvrregs = 0;
714 perror_with_name (_("Unable to fetch AltiVec register"));
717 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
718 long on the hardware. */
719 if (regno == (tdep->ppc_vrsave_regnum - 1))
720 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
722 regcache_raw_collect (regcache, regno,
723 regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
725 ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s);
727 perror_with_name (_("Unable to store AltiVec register"));
730 /* Assuming TID referrs to an SPE process, set the top halves of TID's
731 general-purpose registers and its SPE-specific registers to the
732 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
735 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
736 PTRACE_SETEVRREGS requests are supported is isolated here, and in
737 get_spe_registers. */
739 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
741 if (have_ptrace_getsetevrregs)
743 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
747 /* EIO means that the PTRACE_SETEVRREGS request isn't
748 supported; we fail silently, and don't try the call
751 have_ptrace_getsetevrregs = 0;
753 /* Anything else needs to be reported. */
754 perror_with_name (_("Unable to set SPE registers"));
759 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
760 If REGNO is -1, write the values of all the SPE-specific
763 store_spe_register (const struct regcache *regcache, int tid, int regno)
765 struct gdbarch *gdbarch = get_regcache_arch (regcache);
766 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
767 struct gdb_evrregset_t evrregs;
769 gdb_assert (sizeof (evrregs.evr[0])
770 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
771 gdb_assert (sizeof (evrregs.acc)
772 == register_size (gdbarch, tdep->ppc_acc_regnum));
773 gdb_assert (sizeof (evrregs.spefscr)
774 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
777 /* Since we're going to write out every register, the code below
778 should store to every field of evrregs; if that doesn't happen,
779 make it obvious by initializing it with suspicious values. */
780 memset (&evrregs, 42, sizeof (evrregs));
782 /* We can only read and write the entire EVR register set at a
783 time, so to write just a single register, we do a
784 read-modify-write maneuver. */
785 get_spe_registers (tid, &evrregs);
791 for (i = 0; i < ppc_num_gprs; i++)
792 regcache_raw_collect (regcache,
793 tdep->ppc_ev0_upper_regnum + i,
796 else if (tdep->ppc_ev0_upper_regnum <= regno
797 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
798 regcache_raw_collect (regcache, regno,
799 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
802 || regno == tdep->ppc_acc_regnum)
803 regcache_raw_collect (regcache,
804 tdep->ppc_acc_regnum,
808 || regno == tdep->ppc_spefscr_regnum)
809 regcache_raw_collect (regcache,
810 tdep->ppc_spefscr_regnum,
813 /* Write back the modified register set. */
814 set_spe_registers (tid, &evrregs);
818 store_register (const struct regcache *regcache, int tid, int regno)
820 struct gdbarch *gdbarch = get_regcache_arch (regcache);
821 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
822 /* This isn't really an address. But ptrace thinks of it as one. */
823 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
825 size_t bytes_to_transfer;
826 char buf[MAX_REGISTER_SIZE];
828 if (altivec_register_p (gdbarch, regno))
830 store_altivec_register (regcache, tid, regno);
833 if (vsx_register_p (gdbarch, regno))
835 store_vsx_register (regcache, tid, regno);
838 else if (spe_register_p (gdbarch, regno))
840 store_spe_register (regcache, tid, regno);
847 /* First collect the register. Keep in mind that the regcache's
848 idea of the register's size may not be a multiple of sizeof
850 memset (buf, 0, sizeof buf);
851 bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
852 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
854 /* Little-endian values always sit at the left end of the buffer. */
855 regcache_raw_collect (regcache, regno, buf);
857 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
859 /* Big-endian values sit at the right end of the buffer. */
860 size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
861 regcache_raw_collect (regcache, regno, buf + padding);
864 for (i = 0; i < bytes_to_transfer; i += sizeof (long))
867 ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr,
869 regaddr += sizeof (long);
872 && (regno == tdep->ppc_fpscr_regnum
873 || regno == PPC_ORIG_R3_REGNUM
874 || regno == PPC_TRAP_REGNUM))
876 /* Some older kernel versions don't allow fpscr, orig_r3
877 or trap to be written. */
884 sprintf (message, "writing register %s (#%d)",
885 gdbarch_register_name (gdbarch, regno), regno);
886 perror_with_name (message);
892 fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
895 struct gdbarch *gdbarch = get_regcache_arch (regcache);
896 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
897 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
899 for (i = 0; i < ppc_num_vshrs; i++)
900 regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
901 *vsxregsetp + i * vsxregsize);
905 fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
908 struct gdbarch *gdbarch = get_regcache_arch (regcache);
909 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
910 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
911 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
912 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
914 for (i = 0; i < num_of_vrregs; i++)
916 /* The last 2 registers of this set are only 32 bit long, not
917 128, but only VSCR is fetched as a 16 bytes quantity. */
918 if (i == (num_of_vrregs - 2))
919 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
920 *vrregsetp + i * vrregsize + offset);
922 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
923 *vrregsetp + i * vrregsize);
928 store_vsx_registers (const struct regcache *regcache, int tid)
931 gdb_vsxregset_t regs;
933 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s);
938 have_ptrace_getsetvsxregs = 0;
941 perror_with_name (_("Couldn't get VSX registers"));
944 fill_vsxregset (regcache, ®s);
946 if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0)
947 perror_with_name (_("Couldn't write VSX registers"));
951 store_altivec_registers (const struct regcache *regcache, int tid)
956 ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
961 have_ptrace_getvrregs = 0;
964 perror_with_name (_("Couldn't get AltiVec registers"));
967 fill_vrregset (regcache, ®s);
969 if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0)
970 perror_with_name (_("Couldn't write AltiVec registers"));
974 store_ppc_registers (const struct regcache *regcache, int tid)
977 struct gdbarch *gdbarch = get_regcache_arch (regcache);
978 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
980 for (i = 0; i < ppc_num_gprs; i++)
981 store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
982 if (tdep->ppc_fp0_regnum >= 0)
983 for (i = 0; i < ppc_num_fprs; i++)
984 store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
985 store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
986 if (tdep->ppc_ps_regnum != -1)
987 store_register (regcache, tid, tdep->ppc_ps_regnum);
988 if (tdep->ppc_cr_regnum != -1)
989 store_register (regcache, tid, tdep->ppc_cr_regnum);
990 if (tdep->ppc_lr_regnum != -1)
991 store_register (regcache, tid, tdep->ppc_lr_regnum);
992 if (tdep->ppc_ctr_regnum != -1)
993 store_register (regcache, tid, tdep->ppc_ctr_regnum);
994 if (tdep->ppc_xer_regnum != -1)
995 store_register (regcache, tid, tdep->ppc_xer_regnum);
996 if (tdep->ppc_mq_regnum != -1)
997 store_register (regcache, tid, tdep->ppc_mq_regnum);
998 if (tdep->ppc_fpscr_regnum != -1)
999 store_register (regcache, tid, tdep->ppc_fpscr_regnum);
1000 if (ppc_linux_trap_reg_p (gdbarch))
1002 store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1003 store_register (regcache, tid, PPC_TRAP_REGNUM);
1005 if (have_ptrace_getvrregs)
1006 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1007 store_altivec_registers (regcache, tid);
1008 if (have_ptrace_getsetvsxregs)
1009 if (tdep->ppc_vsr0_upper_regnum != -1)
1010 store_vsx_registers (regcache, tid);
1011 if (tdep->ppc_ev0_upper_regnum >= 0)
1012 store_spe_register (regcache, tid, -1);
1016 ppc_linux_check_watch_resources (int type, int cnt, int ot)
1019 ptid_t ptid = inferior_ptid;
1021 /* DABR (data address breakpoint register) is optional for PPC variants.
1022 Some variants have one DABR, others have none. So CNT can't be larger
1027 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether
1028 the target has DABR. If either answer is no, the ptrace call will
1029 return -1. Fail in that case. */
1030 tid = TIDGET (ptid);
1032 tid = PIDGET (ptid);
1034 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1039 /* Fetch the AT_HWCAP entry from the aux vector. */
1040 unsigned long ppc_linux_get_hwcap (void)
1044 if (target_auxv_search (¤t_target, AT_HWCAP, &field))
1045 return (unsigned long) field;
1051 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
1053 /* Handle sub-8-byte quantities. */
1057 /* addr+len must fall in the 8 byte watchable region for DABR-based
1058 processors. DAC-based processors, like the PowerPC 440, will use
1059 addresses aligned to 4-bytes due to the way the read/write flags are
1060 passed at the moment. */
1061 if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1062 && (addr + len) > (addr & ~3) + 4)
1063 || (addr + len) > (addr & ~7) + 8)
1069 /* The cached DABR value, to install in new threads. */
1070 static long saved_dabr_value;
1072 /* Set a watchpoint of type TYPE at address ADDR. */
1074 ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw)
1076 struct lwp_info *lp;
1079 long read_mode, write_mode;
1081 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1083 /* PowerPC 440 requires only the read/write flags to be passed
1090 /* PowerPC 970 and other DABR-based processors are required to pass
1091 the Breakpoint Translation bit together with the flags. */
1096 dabr_value = addr & ~(read_mode | write_mode);
1100 /* Set read and translate bits. */
1101 dabr_value |= read_mode;
1104 /* Set write and translate bits. */
1105 dabr_value |= write_mode;
1108 /* Set read, write and translate bits. */
1109 dabr_value |= read_mode | write_mode;
1113 saved_dabr_value = dabr_value;
1116 if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0)
1123 ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw)
1125 struct lwp_info *lp;
1127 long dabr_value = 0;
1129 saved_dabr_value = 0;
1131 if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0)
1137 ppc_linux_new_thread (ptid_t ptid)
1139 ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value);
1143 ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
1145 struct siginfo *siginfo_p;
1147 siginfo_p = linux_nat_get_siginfo (inferior_ptid);
1149 if (siginfo_p->si_signo != SIGTRAP
1150 || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1153 *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr;
1158 ppc_linux_stopped_by_watchpoint (void)
1161 return ppc_linux_stopped_data_address (¤t_target, &addr);
1165 ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
1167 CORE_ADDR start, int length)
1171 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1178 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
1179 return start <= addr + mask && start + length - 1 >= addr;
1183 ppc_linux_store_inferior_registers (struct target_ops *ops,
1184 struct regcache *regcache, int regno)
1186 /* Overload thread id onto process id */
1187 int tid = TIDGET (inferior_ptid);
1189 /* No thread id, just use process id */
1191 tid = PIDGET (inferior_ptid);
1194 store_register (regcache, tid, regno);
1196 store_ppc_registers (regcache, tid);
1199 /* Functions for transferring registers between a gregset_t or fpregset_t
1200 (see sys/ucontext.h) and gdb's regcache. The word size is that used
1201 by the ptrace interface, not the current program's ABI. eg. If a
1202 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
1203 read or write 64-bit gregsets. This is to suit the host libthread_db. */
1206 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
1208 const struct regset *regset = ppc_linux_gregset (sizeof (long));
1210 ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
1214 fill_gregset (const struct regcache *regcache,
1215 gdb_gregset_t *gregsetp, int regno)
1217 const struct regset *regset = ppc_linux_gregset (sizeof (long));
1220 memset (gregsetp, 0, sizeof (*gregsetp));
1221 ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
1225 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
1227 const struct regset *regset = ppc_linux_fpregset ();
1229 ppc_supply_fpregset (regset, regcache, -1,
1230 fpregsetp, sizeof (*fpregsetp));
1234 fill_fpregset (const struct regcache *regcache,
1235 gdb_fpregset_t *fpregsetp, int regno)
1237 const struct regset *regset = ppc_linux_fpregset ();
1239 ppc_collect_fpregset (regset, regcache, regno,
1240 fpregsetp, sizeof (*fpregsetp));
1244 ppc_linux_target_wordsize (void)
1248 /* Check for 64-bit inferior process. This is the case when the host is
1249 64-bit, and in addition the top bit of the MSR register is set. */
1250 #ifdef __powerpc64__
1253 int tid = TIDGET (inferior_ptid);
1255 tid = PIDGET (inferior_ptid);
1258 msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
1259 if (errno == 0 && msr < 0)
1267 ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
1268 gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
1270 int sizeof_auxv_field = ppc_linux_target_wordsize ();
1271 gdb_byte *ptr = *readptr;
1276 if (endptr - ptr < sizeof_auxv_field * 2)
1279 *typep = extract_unsigned_integer (ptr, sizeof_auxv_field);
1280 ptr += sizeof_auxv_field;
1281 *valp = extract_unsigned_integer (ptr, sizeof_auxv_field);
1282 ptr += sizeof_auxv_field;
1288 static const struct target_desc *
1289 ppc_linux_read_description (struct target_ops *ops)
1295 int tid = TIDGET (inferior_ptid);
1297 tid = PIDGET (inferior_ptid);
1299 if (have_ptrace_getsetevrregs)
1301 struct gdb_evrregset_t evrregset;
1303 if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
1304 return tdesc_powerpc_e500l;
1306 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
1307 Anything else needs to be reported. */
1308 else if (errno != EIO)
1309 perror_with_name (_("Unable to fetch SPE registers"));
1312 if (have_ptrace_getsetvsxregs)
1314 gdb_vsxregset_t vsxregset;
1316 if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
1319 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
1320 Anything else needs to be reported. */
1321 else if (errno != EIO)
1322 perror_with_name (_("Unable to fetch VSX registers"));
1325 if (have_ptrace_getvrregs)
1327 gdb_vrregset_t vrregset;
1329 if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
1332 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
1333 Anything else needs to be reported. */
1334 else if (errno != EIO)
1335 perror_with_name (_("Unable to fetch AltiVec registers"));
1338 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
1339 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
1340 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
1341 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
1342 half of the register are for Decimal Floating Point, we check if that
1343 feature is available to decide the size of the FPSCR. */
1344 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP)
1347 if (ppc_linux_target_wordsize () == 8)
1350 return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
1352 return isa205? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
1354 return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
1358 return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
1360 return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
1362 return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l;
1365 void _initialize_ppc_linux_nat (void);
1368 _initialize_ppc_linux_nat (void)
1370 struct target_ops *t;
1372 /* Fill in the generic GNU/Linux methods. */
1373 t = linux_target ();
1375 /* Add our register access methods. */
1376 t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
1377 t->to_store_registers = ppc_linux_store_inferior_registers;
1379 /* Add our watchpoint methods. */
1380 t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources;
1381 t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
1382 t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
1383 t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
1384 t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
1385 t->to_stopped_data_address = ppc_linux_stopped_data_address;
1386 t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
1388 t->to_read_description = ppc_linux_read_description;
1389 t->to_auxv_parse = ppc_linux_auxv_parse;
1391 /* Register the target. */
1392 linux_nat_add_target (t);
1393 linux_nat_set_new_thread (t, ppc_linux_new_thread);