1 /* Target-machine dependent code for Nios II, for GDB.
2 Copyright (C) 2012-2019 Free Software Foundation, Inc.
3 Contributed by Peter Brookes (pbrookes@altera.com)
4 and Andrew Draper (adraper@altera.com).
5 Contributed by Mentor Graphics, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2-frame.h"
39 #include "arch-utils.h"
42 #include "target-descriptions.h"
44 /* To get entry_point_address. */
48 /* Nios II specific header. */
49 #include "nios2-tdep.h"
51 #include "features/nios2.c"
53 /* Control debugging information emitted in this file. */
55 static int nios2_debug = 0;
57 /* The following structures are used in the cache for prologue
58 analysis; see the reg_value and reg_saved tables in
59 struct nios2_unwind_cache, respectively. */
61 /* struct reg_value is used to record that a register has the same value
62 as reg at the given offset from the start of a function. */
70 /* struct reg_saved is used to record that a register value has been saved at
71 basereg + addr, for basereg >= 0. If basereg < 0, that indicates
72 that the register is not known to have been saved. Note that when
73 basereg == NIOS2_Z_REGNUM (that is, r0, which holds value 0),
74 addr is an absolute address. */
82 struct nios2_unwind_cache
84 /* The frame's base, optionally used by the high-level debug info. */
87 /* The previous frame's inner most stack address. Used as this
88 frame ID's stack_addr. */
91 /* The address of the first instruction in this function. */
94 /* Which register holds the return address for the frame. */
97 /* Table indicating what changes have been made to each register. */
98 struct reg_value reg_value[NIOS2_NUM_REGS];
100 /* Table indicating where each register has been saved. */
101 struct reg_saved reg_saved[NIOS2_NUM_REGS];
105 /* This array is a mapping from Dwarf-2 register numbering to GDB's. */
107 static int nios2_dwarf2gdb_regno_map[] =
116 NIOS2_GP_REGNUM, /* 26 */
117 NIOS2_SP_REGNUM, /* 27 */
118 NIOS2_FP_REGNUM, /* 28 */
119 NIOS2_EA_REGNUM, /* 29 */
120 NIOS2_BA_REGNUM, /* 30 */
121 NIOS2_RA_REGNUM, /* 31 */
122 NIOS2_PC_REGNUM, /* 32 */
123 NIOS2_STATUS_REGNUM, /* 33 */
124 NIOS2_ESTATUS_REGNUM, /* 34 */
125 NIOS2_BSTATUS_REGNUM, /* 35 */
126 NIOS2_IENABLE_REGNUM, /* 36 */
127 NIOS2_IPENDING_REGNUM, /* 37 */
128 NIOS2_CPUID_REGNUM, /* 38 */
129 39, /* CTL6 */ /* 39 */
130 NIOS2_EXCEPTION_REGNUM, /* 40 */
131 NIOS2_PTEADDR_REGNUM, /* 41 */
132 NIOS2_TLBACC_REGNUM, /* 42 */
133 NIOS2_TLBMISC_REGNUM, /* 43 */
134 NIOS2_ECCINJ_REGNUM, /* 44 */
135 NIOS2_BADADDR_REGNUM, /* 45 */
136 NIOS2_CONFIG_REGNUM, /* 46 */
137 NIOS2_MPUBASE_REGNUM, /* 47 */
138 NIOS2_MPUACC_REGNUM /* 48 */
141 gdb_static_assert (ARRAY_SIZE (nios2_dwarf2gdb_regno_map) == NIOS2_NUM_REGS);
143 /* Implement the dwarf2_reg_to_regnum gdbarch method. */
146 nios2_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg)
148 if (dw_reg < 0 || dw_reg >= NIOS2_NUM_REGS)
151 return nios2_dwarf2gdb_regno_map[dw_reg];
154 /* Canonical names for the 49 registers. */
156 static const char *const nios2_reg_names[NIOS2_NUM_REGS] =
158 "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7",
159 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
160 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
161 "et", "bt", "gp", "sp", "fp", "ea", "sstatus", "ra",
163 "status", "estatus", "bstatus", "ienable",
164 "ipending", "cpuid", "ctl6", "exception",
165 "pteaddr", "tlbacc", "tlbmisc", "eccinj",
166 "badaddr", "config", "mpubase", "mpuacc"
169 /* Implement the register_name gdbarch method. */
172 nios2_register_name (struct gdbarch *gdbarch, int regno)
174 /* Use mnemonic aliases for GPRs. */
175 if (regno >= 0 && regno < NIOS2_NUM_REGS)
176 return nios2_reg_names[regno];
178 return tdesc_register_name (gdbarch, regno);
181 /* Implement the register_type gdbarch method. */
184 nios2_register_type (struct gdbarch *gdbarch, int regno)
186 /* If the XML description has register information, use that to
187 determine the register type. */
188 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
189 return tdesc_register_type (gdbarch, regno);
191 if (regno == NIOS2_PC_REGNUM)
192 return builtin_type (gdbarch)->builtin_func_ptr;
193 else if (regno == NIOS2_SP_REGNUM)
194 return builtin_type (gdbarch)->builtin_data_ptr;
196 return builtin_type (gdbarch)->builtin_uint32;
199 /* Given a return value in REGCACHE with a type VALTYPE,
200 extract and copy its value into VALBUF. */
203 nios2_extract_return_value (struct gdbarch *gdbarch, struct type *valtype,
204 struct regcache *regcache, gdb_byte *valbuf)
206 int len = TYPE_LENGTH (valtype);
208 /* Return values of up to 8 bytes are returned in $r2 $r3. */
209 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM))
210 regcache->cooked_read (NIOS2_R2_REGNUM, valbuf);
213 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM)
214 + register_size (gdbarch, NIOS2_R3_REGNUM)));
215 regcache->cooked_read (NIOS2_R2_REGNUM, valbuf);
216 regcache->cooked_read (NIOS2_R3_REGNUM, valbuf + 4);
220 /* Write into appropriate registers a function return value
221 of type TYPE, given in virtual format. */
224 nios2_store_return_value (struct gdbarch *gdbarch, struct type *valtype,
225 struct regcache *regcache, const gdb_byte *valbuf)
227 int len = TYPE_LENGTH (valtype);
229 /* Return values of up to 8 bytes are returned in $r2 $r3. */
230 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM))
231 regcache->cooked_write (NIOS2_R2_REGNUM, valbuf);
234 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM)
235 + register_size (gdbarch, NIOS2_R3_REGNUM)));
236 regcache->cooked_write (NIOS2_R2_REGNUM, valbuf);
237 regcache->cooked_write (NIOS2_R3_REGNUM, valbuf + 4);
242 /* Set up the default values of the registers. */
245 nios2_setup_default (struct nios2_unwind_cache *cache)
249 for (i = 0; i < NIOS2_NUM_REGS; i++)
251 /* All registers start off holding their previous values. */
252 cache->reg_value[i].reg = i;
253 cache->reg_value[i].offset = 0;
255 /* All registers start off not saved. */
256 cache->reg_saved[i].basereg = -1;
257 cache->reg_saved[i].addr = 0;
261 /* Initialize the unwind cache. */
264 nios2_init_cache (struct nios2_unwind_cache *cache, CORE_ADDR pc)
269 cache->return_regnum = NIOS2_RA_REGNUM;
270 nios2_setup_default (cache);
273 /* Read and identify an instruction at PC. If INSNP is non-null,
274 store the instruction word into that location. Return the opcode
275 pointer or NULL if the memory couldn't be read or disassembled. */
277 static const struct nios2_opcode *
278 nios2_fetch_insn (struct gdbarch *gdbarch, CORE_ADDR pc,
282 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
285 if (mach == bfd_mach_nios2r2)
287 if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE,
288 BFD_ENDIAN_LITTLE, &memword)
289 && !safe_read_memory_integer (pc, NIOS2_CDX_OPCODE_SIZE,
290 BFD_ENDIAN_LITTLE, &memword))
293 else if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE,
294 gdbarch_byte_order (gdbarch), &memword))
297 insn = (unsigned int) memword;
300 return nios2_find_opcode_hash (insn, mach);
304 /* Match and disassemble an ADD-type instruction, with 3 register operands.
305 Returns true on success, and fills in the operand pointers. */
308 nios2_match_add (uint32_t insn, const struct nios2_opcode *op,
309 unsigned long mach, int *ra, int *rb, int *rc)
311 int is_r2 = (mach == bfd_mach_nios2r2);
313 if (!is_r2 && (op->match == MATCH_R1_ADD || op->match == MATCH_R1_MOV))
315 *ra = GET_IW_R_A (insn);
316 *rb = GET_IW_R_B (insn);
317 *rc = GET_IW_R_C (insn);
322 else if (op->match == MATCH_R2_ADD || op->match == MATCH_R2_MOV)
324 *ra = GET_IW_F3X6L5_A (insn);
325 *rb = GET_IW_F3X6L5_B (insn);
326 *rc = GET_IW_F3X6L5_C (insn);
329 else if (op->match == MATCH_R2_ADD_N)
331 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)];
332 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)];
333 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)];
336 else if (op->match == MATCH_R2_MOV_N)
338 *ra = GET_IW_F2_A (insn);
340 *rc = GET_IW_F2_B (insn);
346 /* Match and disassemble a SUB-type instruction, with 3 register operands.
347 Returns true on success, and fills in the operand pointers. */
350 nios2_match_sub (uint32_t insn, const struct nios2_opcode *op,
351 unsigned long mach, int *ra, int *rb, int *rc)
353 int is_r2 = (mach == bfd_mach_nios2r2);
355 if (!is_r2 && op->match == MATCH_R1_SUB)
357 *ra = GET_IW_R_A (insn);
358 *rb = GET_IW_R_B (insn);
359 *rc = GET_IW_R_C (insn);
364 else if (op->match == MATCH_R2_SUB)
366 *ra = GET_IW_F3X6L5_A (insn);
367 *rb = GET_IW_F3X6L5_B (insn);
368 *rc = GET_IW_F3X6L5_C (insn);
371 else if (op->match == MATCH_R2_SUB_N)
373 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)];
374 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)];
375 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)];
381 /* Match and disassemble an ADDI-type instruction, with 2 register operands
382 and one immediate operand.
383 Returns true on success, and fills in the operand pointers. */
386 nios2_match_addi (uint32_t insn, const struct nios2_opcode *op,
387 unsigned long mach, int *ra, int *rb, int *imm)
389 int is_r2 = (mach == bfd_mach_nios2r2);
391 if (!is_r2 && op->match == MATCH_R1_ADDI)
393 *ra = GET_IW_I_A (insn);
394 *rb = GET_IW_I_B (insn);
395 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16;
400 else if (op->match == MATCH_R2_ADDI)
402 *ra = GET_IW_F2I16_A (insn);
403 *rb = GET_IW_F2I16_B (insn);
404 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16;
407 else if (op->match == MATCH_R2_ADDI_N || op->match == MATCH_R2_SUBI_N)
409 *ra = nios2_r2_reg3_mappings[GET_IW_T2X1I3_A3 (insn)];
410 *rb = nios2_r2_reg3_mappings[GET_IW_T2X1I3_B3 (insn)];
411 *imm = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (insn)];
412 if (op->match == MATCH_R2_SUBI_N)
416 else if (op->match == MATCH_R2_SPADDI_N)
418 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)];
419 *rb = NIOS2_SP_REGNUM;
420 *imm = GET_IW_T1I7_IMM7 (insn) << 2;
423 else if (op->match == MATCH_R2_SPINCI_N || op->match == MATCH_R2_SPDECI_N)
425 *ra = NIOS2_SP_REGNUM;
426 *rb = NIOS2_SP_REGNUM;
427 *imm = GET_IW_X1I7_IMM7 (insn) << 2;
428 if (op->match == MATCH_R2_SPDECI_N)
435 /* Match and disassemble an ORHI-type instruction, with 2 register operands
436 and one unsigned immediate operand.
437 Returns true on success, and fills in the operand pointers. */
440 nios2_match_orhi (uint32_t insn, const struct nios2_opcode *op,
441 unsigned long mach, int *ra, int *rb, unsigned int *uimm)
443 int is_r2 = (mach == bfd_mach_nios2r2);
445 if (!is_r2 && op->match == MATCH_R1_ORHI)
447 *ra = GET_IW_I_A (insn);
448 *rb = GET_IW_I_B (insn);
449 *uimm = GET_IW_I_IMM16 (insn);
454 else if (op->match == MATCH_R2_ORHI)
456 *ra = GET_IW_F2I16_A (insn);
457 *rb = GET_IW_F2I16_B (insn);
458 *uimm = GET_IW_F2I16_IMM16 (insn);
464 /* Match and disassemble a STW-type instruction, with 2 register operands
465 and one immediate operand.
466 Returns true on success, and fills in the operand pointers. */
469 nios2_match_stw (uint32_t insn, const struct nios2_opcode *op,
470 unsigned long mach, int *ra, int *rb, int *imm)
472 int is_r2 = (mach == bfd_mach_nios2r2);
474 if (!is_r2 && (op->match == MATCH_R1_STW || op->match == MATCH_R1_STWIO))
476 *ra = GET_IW_I_A (insn);
477 *rb = GET_IW_I_B (insn);
478 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16;
483 else if (op->match == MATCH_R2_STW)
485 *ra = GET_IW_F2I16_A (insn);
486 *rb = GET_IW_F2I16_B (insn);
487 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16;
490 else if (op->match == MATCH_R2_STWIO)
492 *ra = GET_IW_F2X4I12_A (insn);
493 *rb = GET_IW_F2X4I12_B (insn);
494 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20;
497 else if (op->match == MATCH_R2_STW_N)
499 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)];
500 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)];
501 *imm = GET_IW_T2I4_IMM4 (insn) << 2;
504 else if (op->match == MATCH_R2_STWSP_N)
506 *ra = NIOS2_SP_REGNUM;
507 *rb = GET_IW_F1I5_B (insn);
508 *imm = GET_IW_F1I5_IMM5 (insn) << 2;
511 else if (op->match == MATCH_R2_STWZ_N)
513 *ra = nios2_r2_reg3_mappings[GET_IW_T1X1I6_A3 (insn)];
515 *imm = GET_IW_T1X1I6_IMM6 (insn) << 2;
521 /* Match and disassemble a LDW-type instruction, with 2 register operands
522 and one immediate operand.
523 Returns true on success, and fills in the operand pointers. */
526 nios2_match_ldw (uint32_t insn, const struct nios2_opcode *op,
527 unsigned long mach, int *ra, int *rb, int *imm)
529 int is_r2 = (mach == bfd_mach_nios2r2);
531 if (!is_r2 && (op->match == MATCH_R1_LDW || op->match == MATCH_R1_LDWIO))
533 *ra = GET_IW_I_A (insn);
534 *rb = GET_IW_I_B (insn);
535 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16;
540 else if (op->match == MATCH_R2_LDW)
542 *ra = GET_IW_F2I16_A (insn);
543 *rb = GET_IW_F2I16_B (insn);
544 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16;
547 else if (op->match == MATCH_R2_LDWIO)
549 *ra = GET_IW_F2X4I12_A (insn);
550 *rb = GET_IW_F2X4I12_B (insn);
551 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20;
554 else if (op->match == MATCH_R2_LDW_N)
556 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)];
557 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)];
558 *imm = GET_IW_T2I4_IMM4 (insn) << 2;
561 else if (op->match == MATCH_R2_LDWSP_N)
563 *ra = NIOS2_SP_REGNUM;
564 *rb = GET_IW_F1I5_B (insn);
565 *imm = GET_IW_F1I5_IMM5 (insn) << 2;
571 /* Match and disassemble a RDCTL instruction, with 2 register operands.
572 Returns true on success, and fills in the operand pointers. */
575 nios2_match_rdctl (uint32_t insn, const struct nios2_opcode *op,
576 unsigned long mach, int *ra, int *rc)
578 int is_r2 = (mach == bfd_mach_nios2r2);
580 if (!is_r2 && (op->match == MATCH_R1_RDCTL))
582 *ra = GET_IW_R_IMM5 (insn);
583 *rc = GET_IW_R_C (insn);
588 else if (op->match == MATCH_R2_RDCTL)
590 *ra = GET_IW_F3X6L5_IMM5 (insn);
591 *rc = GET_IW_F3X6L5_C (insn);
597 /* Match and disassemble a PUSH.N or STWM instruction.
598 Returns true on success, and fills in the operand pointers. */
601 nios2_match_stwm (uint32_t insn, const struct nios2_opcode *op,
602 unsigned long mach, unsigned int *reglist,
603 int *ra, int *imm, int *wb, int *id)
605 int is_r2 = (mach == bfd_mach_nios2r2);
609 else if (op->match == MATCH_R2_PUSH_N)
612 if (GET_IW_L5I4X1_FP (insn))
613 *reglist |= (1 << 28);
614 if (GET_IW_L5I4X1_CS (insn))
616 int val = GET_IW_L5I4X1_REGRANGE (insn);
617 *reglist |= nios2_r2_reg_range_mappings[val];
619 *ra = NIOS2_SP_REGNUM;
620 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2;
625 else if (op->match == MATCH_R2_STWM)
627 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn);
628 if (GET_IW_F1X4L17_RS (insn))
630 *reglist = ((rawmask << 14) & 0x00ffc000);
631 if (rawmask & (1 << 10))
632 *reglist |= (1 << 28);
633 if (rawmask & (1 << 11))
634 *reglist |= (1 << 31);
637 *reglist = rawmask << 2;
638 *ra = GET_IW_F1X4L17_A (insn);
640 *wb = GET_IW_F1X4L17_WB (insn);
641 *id = GET_IW_F1X4L17_ID (insn);
647 /* Match and disassemble a POP.N or LDWM instruction.
648 Returns true on success, and fills in the operand pointers. */
651 nios2_match_ldwm (uint32_t insn, const struct nios2_opcode *op,
652 unsigned long mach, unsigned int *reglist,
653 int *ra, int *imm, int *wb, int *id, int *ret)
655 int is_r2 = (mach == bfd_mach_nios2r2);
659 else if (op->match == MATCH_R2_POP_N)
662 if (GET_IW_L5I4X1_FP (insn))
663 *reglist |= (1 << 28);
664 if (GET_IW_L5I4X1_CS (insn))
666 int val = GET_IW_L5I4X1_REGRANGE (insn);
667 *reglist |= nios2_r2_reg_range_mappings[val];
669 *ra = NIOS2_SP_REGNUM;
670 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2;
676 else if (op->match == MATCH_R2_LDWM)
678 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn);
679 if (GET_IW_F1X4L17_RS (insn))
681 *reglist = ((rawmask << 14) & 0x00ffc000);
682 if (rawmask & (1 << 10))
683 *reglist |= (1 << 28);
684 if (rawmask & (1 << 11))
685 *reglist |= (1 << 31);
688 *reglist = rawmask << 2;
689 *ra = GET_IW_F1X4L17_A (insn);
691 *wb = GET_IW_F1X4L17_WB (insn);
692 *id = GET_IW_F1X4L17_ID (insn);
693 *ret = GET_IW_F1X4L17_PC (insn);
699 /* Match and disassemble a branch instruction, with (potentially)
700 2 register operands and one immediate operand.
701 Returns true on success, and fills in the operand pointers. */
703 enum branch_condition {
714 nios2_match_branch (uint32_t insn, const struct nios2_opcode *op,
715 unsigned long mach, int *ra, int *rb, int *imm,
716 enum branch_condition *cond)
718 int is_r2 = (mach == bfd_mach_nios2r2);
748 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16;
749 *ra = GET_IW_I_A (insn);
750 *rb = GET_IW_I_B (insn);
759 *ra = NIOS2_Z_REGNUM;
760 *rb = NIOS2_Z_REGNUM;
761 *imm = (signed) ((GET_IW_I10_IMM10 (insn) << 1) << 21) >> 21;
763 case MATCH_R2_BEQZ_N:
765 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)];
766 *rb = NIOS2_Z_REGNUM;
767 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24;
769 case MATCH_R2_BNEZ_N:
771 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)];
772 *rb = NIOS2_Z_REGNUM;
773 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24;
799 *ra = GET_IW_F2I16_A (insn);
800 *rb = GET_IW_F2I16_B (insn);
801 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16;
807 /* Match and disassemble a direct jump instruction, with an
808 unsigned operand. Returns true on success, and fills in the operand
812 nios2_match_jmpi (uint32_t insn, const struct nios2_opcode *op,
813 unsigned long mach, unsigned int *uimm)
815 int is_r2 = (mach == bfd_mach_nios2r2);
817 if (!is_r2 && op->match == MATCH_R1_JMPI)
819 *uimm = GET_IW_J_IMM26 (insn) << 2;
824 else if (op->match == MATCH_R2_JMPI)
826 *uimm = GET_IW_L26_IMM26 (insn) << 2;
832 /* Match and disassemble a direct call instruction, with an
833 unsigned operand. Returns true on success, and fills in the operand
837 nios2_match_calli (uint32_t insn, const struct nios2_opcode *op,
838 unsigned long mach, unsigned int *uimm)
840 int is_r2 = (mach == bfd_mach_nios2r2);
842 if (!is_r2 && op->match == MATCH_R1_CALL)
844 *uimm = GET_IW_J_IMM26 (insn) << 2;
849 else if (op->match == MATCH_R2_CALL)
851 *uimm = GET_IW_L26_IMM26 (insn) << 2;
857 /* Match and disassemble an indirect jump instruction, with a
858 (possibly implicit) register operand. Returns true on success, and fills
859 in the operand pointer. */
862 nios2_match_jmpr (uint32_t insn, const struct nios2_opcode *op,
863 unsigned long mach, int *ra)
865 int is_r2 = (mach == bfd_mach_nios2r2);
871 *ra = GET_IW_I_A (insn);
874 *ra = NIOS2_RA_REGNUM;
877 *ra = NIOS2_EA_REGNUM;
880 *ra = NIOS2_BA_REGNUM;
889 *ra = GET_IW_F2I16_A (insn);
891 case MATCH_R2_JMPR_N:
892 *ra = GET_IW_F1X1_A (insn);
896 *ra = NIOS2_RA_REGNUM;
899 *ra = NIOS2_EA_REGNUM;
902 *ra = NIOS2_BA_REGNUM;
910 /* Match and disassemble an indirect call instruction, with a register
911 operand. Returns true on success, and fills in the operand pointer. */
914 nios2_match_callr (uint32_t insn, const struct nios2_opcode *op,
915 unsigned long mach, int *ra)
917 int is_r2 = (mach == bfd_mach_nios2r2);
919 if (!is_r2 && op->match == MATCH_R1_CALLR)
921 *ra = GET_IW_I_A (insn);
926 else if (op->match == MATCH_R2_CALLR)
928 *ra = GET_IW_F2I16_A (insn);
931 else if (op->match == MATCH_R2_CALLR_N)
933 *ra = GET_IW_F1X1_A (insn);
939 /* Match and disassemble a break instruction, with an unsigned operand.
940 Returns true on success, and fills in the operand pointer. */
943 nios2_match_break (uint32_t insn, const struct nios2_opcode *op,
944 unsigned long mach, unsigned int *uimm)
946 int is_r2 = (mach == bfd_mach_nios2r2);
948 if (!is_r2 && op->match == MATCH_R1_BREAK)
950 *uimm = GET_IW_R_IMM5 (insn);
955 else if (op->match == MATCH_R2_BREAK)
957 *uimm = GET_IW_F3X6L5_IMM5 (insn);
960 else if (op->match == MATCH_R2_BREAK_N)
962 *uimm = GET_IW_X2L5_IMM5 (insn);
968 /* Match and disassemble a trap instruction, with an unsigned operand.
969 Returns true on success, and fills in the operand pointer. */
972 nios2_match_trap (uint32_t insn, const struct nios2_opcode *op,
973 unsigned long mach, unsigned int *uimm)
975 int is_r2 = (mach == bfd_mach_nios2r2);
977 if (!is_r2 && op->match == MATCH_R1_TRAP)
979 *uimm = GET_IW_R_IMM5 (insn);
984 else if (op->match == MATCH_R2_TRAP)
986 *uimm = GET_IW_F3X6L5_IMM5 (insn);
989 else if (op->match == MATCH_R2_TRAP_N)
991 *uimm = GET_IW_X2L5_IMM5 (insn);
997 /* Helper function to identify when we're in a function epilogue;
998 that is, the part of the function from the point at which the
999 stack adjustments are made, to the return or sibcall.
1000 Note that we may have several stack adjustment instructions, and
1001 this function needs to test whether the stack teardown has already
1002 started before current_pc, not whether it has completed. */
1005 nios2_in_epilogue_p (struct gdbarch *gdbarch,
1006 CORE_ADDR current_pc,
1009 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1010 int is_r2 = (mach == bfd_mach_nios2r2);
1011 /* Maximum number of possibly-epilogue instructions to check.
1012 Note that this number should not be too large, else we can
1013 potentially end up iterating through unmapped memory. */
1014 int ninsns, max_insns = 5;
1016 const struct nios2_opcode *op = NULL;
1021 enum branch_condition cond;
1024 /* There has to be a previous instruction in the function. */
1025 if (current_pc <= start_pc)
1028 /* Find the previous instruction before current_pc. For R2, it might
1029 be either a 16-bit or 32-bit instruction; the only way to know for
1030 sure is to scan through from the beginning of the function,
1031 disassembling as we go. */
1033 for (pc = start_pc; ; )
1035 op = nios2_fetch_insn (gdbarch, pc, &insn);
1038 if (pc + op->size < current_pc)
1042 /* We can skip over insns to a forward branch target. Since
1043 the branch offset is relative to the next instruction,
1044 it's correct to do this after incrementing the pc above. */
1045 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)
1047 && pc + imm < current_pc)
1050 /* Otherwise just go back to the previous 32-bit insn. */
1052 pc = current_pc - NIOS2_OPCODE_SIZE;
1054 /* Beginning with the previous instruction we just located, check whether
1055 we are in a sequence of at least one stack adjustment instruction.
1056 Possible instructions here include:
1062 LDWM {reglist}, (sp)++, wb */
1063 for (ninsns = 0; ninsns < max_insns; ninsns++)
1067 /* Fetch the insn at pc. */
1068 op = nios2_fetch_insn (gdbarch, pc, &insn);
1073 /* Was it a stack adjustment? */
1074 if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm))
1075 ok = (rb == NIOS2_SP_REGNUM);
1076 else if (nios2_match_add (insn, op, mach, &ra, &rb, &rc))
1077 ok = (rc == NIOS2_SP_REGNUM);
1078 else if (nios2_match_ldw (insn, op, mach, &ra, &rb, &imm))
1079 ok = (rb == NIOS2_SP_REGNUM);
1080 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra,
1081 &imm, &wb, &ret, &id))
1082 ok = (ra == NIOS2_SP_REGNUM && wb && id);
1087 /* No stack adjustments found. */
1091 /* We found more stack adjustments than we expect GCC to be generating.
1092 Since it looks like a stack unwind might be in progress tell GDB to
1093 treat it as such. */
1094 if (ninsns == max_insns)
1097 /* The next instruction following the stack adjustments must be a
1098 return, jump, or unconditional branch, or a CDX pop.n or ldwm
1099 that does an implicit return. */
1100 if (nios2_match_jmpr (insn, op, mach, &ra)
1101 || nios2_match_jmpi (insn, op, mach, &uimm)
1102 || (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret)
1104 || (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)
1105 && cond == branch_none))
1111 /* Implement the stack_frame_destroyed_p gdbarch method. */
1114 nios2_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1116 CORE_ADDR func_addr;
1118 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1119 return nios2_in_epilogue_p (gdbarch, pc, func_addr);
1124 /* Do prologue analysis, returning the PC of the first instruction
1125 after the function prologue. Assumes CACHE has already been
1126 initialized. THIS_FRAME can be null, in which case we are only
1127 interested in skipping the prologue. Otherwise CACHE is filled in
1128 from the frame information.
1130 The prologue may consist of the following parts:
1131 1) Profiling instrumentation. For non-PIC code it looks like:
1136 2) A stack adjustment and save of R4-R7 for varargs functions.
1137 For R2 CDX this is typically handled with a STWM, otherwise
1138 this is typically merged with item 3.
1140 3) A stack adjustment and save of the callee-saved registers.
1141 For R2 CDX these are typically handled with a PUSH.N or STWM,
1142 otherwise as an explicit SP decrement and individual register
1145 There may also be a stack switch here in an exception handler
1146 in place of a stack adjustment. It looks like:
1147 movhi rx, %hiadj(newstack)
1148 addhi rx, rx, %lo(newstack)
1149 stw sp, constant(rx)
1152 4) A frame pointer save, which can be either a MOV or ADDI.
1154 5) A further stack pointer adjustment. This is normally included
1155 adjustment in step 3 unless the total adjustment is too large
1156 to be done in one step.
1158 7) A stack overflow check, which can take either of these forms:
1162 bltu sp, rx, .Lstack_overflow
1167 Older versions of GCC emitted "break 3" instead of "trap 3" here,
1168 so we check for both cases.
1170 Older GCC versions emitted stack overflow checks after the SP
1171 adjustments in both steps 3 and 4. Starting with GCC 6, there is
1172 at most one overflow check, which is placed before the first
1173 stack adjustment for R2 CDX and after the first stack adjustment
1176 The prologue instructions may be combined or interleaved with other
1179 To cope with all this variability we decode all the instructions
1180 from the start of the prologue until we hit an instruction that
1181 cannot possibly be a prologue instruction, such as a branch, call,
1182 return, or epilogue instruction. The prologue is considered to end
1183 at the last instruction that can definitely be considered a
1184 prologue instruction. */
1187 nios2_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
1188 const CORE_ADDR current_pc,
1189 struct nios2_unwind_cache *cache,
1190 struct frame_info *this_frame)
1192 /* Maximum number of possibly-prologue instructions to check.
1193 Note that this number should not be too large, else we can
1194 potentially end up iterating through unmapped memory. */
1195 int ninsns, max_insns = 50;
1196 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1197 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1199 /* Does the frame set up the FP register? */
1202 struct reg_value *value = cache->reg_value;
1203 struct reg_value temp_value[NIOS2_NUM_REGS];
1205 /* Save the starting PC so we can correct the pc after running
1206 through the prolog, using symbol info. */
1207 CORE_ADDR pc = start_pc;
1209 /* Is this an exception handler? */
1210 int exception_handler = 0;
1212 /* What was the original value of SP (or fake original value for
1213 functions which switch stacks? */
1214 CORE_ADDR frame_high;
1216 /* The last definitely-prologue instruction seen. */
1217 CORE_ADDR prologue_end;
1219 /* Is this the innermost function? */
1220 int innermost = (this_frame ? (frame_relative_level (this_frame) == 0) : 1);
1223 fprintf_unfiltered (gdb_stdlog,
1224 "{ nios2_analyze_prologue start=%s, current=%s ",
1225 paddress (gdbarch, start_pc),
1226 paddress (gdbarch, current_pc));
1228 /* Set up the default values of the registers. */
1229 nios2_setup_default (cache);
1231 /* Find the prologue instructions. */
1232 prologue_end = start_pc;
1233 for (ninsns = 0; ninsns < max_insns; ninsns++)
1235 /* Present instruction. */
1237 const struct nios2_opcode *op;
1238 int ra, rb, rc, imm;
1240 unsigned int reglist;
1242 enum branch_condition cond;
1244 if (pc == current_pc)
1246 /* When we reach the current PC we must save the current
1247 register state (for the backtrace) but keep analysing
1248 because there might be more to find out (eg. is this an
1249 exception handler). */
1250 memcpy (temp_value, value, sizeof (temp_value));
1253 fprintf_unfiltered (gdb_stdlog, "*");
1256 op = nios2_fetch_insn (gdbarch, pc, &insn);
1258 /* Unknown opcode? Stop scanning. */
1266 fprintf_unfiltered (gdb_stdlog, "[%04X]", insn & 0xffff);
1268 fprintf_unfiltered (gdb_stdlog, "[%08X]", insn);
1271 /* The following instructions can appear in the prologue. */
1273 if (nios2_match_add (insn, op, mach, &ra, &rb, &rc))
1275 /* ADD rc, ra, rb (also used for MOV) */
1276 if (rc == NIOS2_SP_REGNUM
1278 && value[ra].reg == cache->reg_saved[NIOS2_SP_REGNUM].basereg)
1280 /* If the previous value of SP is available somewhere
1281 near the new stack pointer value then this is a
1284 /* If any registers were saved on the stack before then
1285 we can't backtrace into them now. */
1286 for (int i = 0 ; i < NIOS2_NUM_REGS ; i++)
1288 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM)
1289 cache->reg_saved[i].basereg = -1;
1290 if (value[i].reg == NIOS2_SP_REGNUM)
1294 /* Create a fake "high water mark" 4 bytes above where SP
1295 was stored and fake up the registers to be consistent
1297 value[NIOS2_SP_REGNUM].reg = NIOS2_SP_REGNUM;
1298 value[NIOS2_SP_REGNUM].offset
1300 - cache->reg_saved[NIOS2_SP_REGNUM].addr
1302 cache->reg_saved[NIOS2_SP_REGNUM].basereg = NIOS2_SP_REGNUM;
1303 cache->reg_saved[NIOS2_SP_REGNUM].addr = -4;
1306 else if (rc == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM)
1307 /* This is setting SP from FP. This only happens in the
1308 function epilogue. */
1313 if (value[rb].reg == 0)
1314 value[rc].reg = value[ra].reg;
1315 else if (value[ra].reg == 0)
1316 value[rc].reg = value[rb].reg;
1319 value[rc].offset = value[ra].offset + value[rb].offset;
1322 /* The add/move is only considered a prologue instruction
1323 if the destination is SP or FP. */
1324 if (rc == NIOS2_SP_REGNUM || rc == NIOS2_FP_REGNUM)
1328 else if (nios2_match_sub (insn, op, mach, &ra, &rb, &rc))
1330 /* SUB rc, ra, rb */
1331 if (rc == NIOS2_SP_REGNUM && rb == NIOS2_SP_REGNUM
1332 && value[rc].reg != 0)
1333 /* If we are decrementing the SP by a non-constant amount,
1334 this is alloca, not part of the prologue. */
1338 if (value[rb].reg == 0)
1339 value[rc].reg = value[ra].reg;
1342 value[rc].offset = value[ra].offset - value[rb].offset;
1346 else if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm))
1348 /* ADDI rb, ra, imm */
1350 /* A positive stack adjustment has to be part of the epilogue. */
1351 if (rb == NIOS2_SP_REGNUM
1352 && (imm > 0 || value[ra].reg != NIOS2_SP_REGNUM))
1355 /* Likewise restoring SP from FP. */
1356 else if (rb == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM)
1361 value[rb].reg = value[ra].reg;
1362 value[rb].offset = value[ra].offset + imm;
1365 /* The add is only considered a prologue instruction
1366 if the destination is SP or FP. */
1367 if (rb == NIOS2_SP_REGNUM || rb == NIOS2_FP_REGNUM)
1371 else if (nios2_match_orhi (insn, op, mach, &ra, &rb, &uimm))
1373 /* ORHI rb, ra, uimm (also used for MOVHI) */
1376 value[rb].reg = (value[ra].reg == 0) ? 0 : -1;
1377 value[rb].offset = value[ra].offset | (uimm << 16);
1381 else if (nios2_match_stw (insn, op, mach, &ra, &rb, &imm))
1383 /* STW rb, imm(ra) */
1385 /* Are we storing the original value of a register to the stack?
1386 For exception handlers the value of EA-4 (return
1387 address from interrupts etc) is sometimes stored. */
1388 int orig = value[rb].reg;
1390 && (value[rb].offset == 0
1391 || (orig == NIOS2_EA_REGNUM && value[rb].offset == -4))
1392 && value[ra].reg == NIOS2_SP_REGNUM)
1394 if (pc < current_pc)
1396 /* Save off callee saved registers. */
1397 cache->reg_saved[orig].basereg = value[ra].reg;
1398 cache->reg_saved[orig].addr = value[ra].offset + imm;
1403 if (orig == NIOS2_EA_REGNUM || orig == NIOS2_ESTATUS_REGNUM)
1404 exception_handler = 1;
1407 /* Non-stack memory writes cannot appear in the prologue. */
1411 else if (nios2_match_stwm (insn, op, mach,
1412 ®list, &ra, &imm, &wb, &id))
1414 /* PUSH.N {reglist}, adjust
1416 STWM {reglist}, --(SP)[, writeback] */
1419 if (ra != NIOS2_SP_REGNUM || id != 0)
1420 /* This is a non-stack-push memory write and cannot be
1421 part of the prologue. */
1424 for (int i = 31; i >= 0; i--)
1425 if (reglist & (1 << i))
1427 int orig = value[i].reg;
1430 if (orig > 0 && value[i].offset == 0 && pc < current_pc)
1432 cache->reg_saved[orig].basereg
1433 = value[NIOS2_SP_REGNUM].reg;
1434 cache->reg_saved[orig].addr
1435 = value[NIOS2_SP_REGNUM].offset - off;
1440 value[NIOS2_SP_REGNUM].offset -= off;
1441 value[NIOS2_SP_REGNUM].offset -= imm;
1446 else if (nios2_match_rdctl (insn, op, mach, &ra, &rc))
1449 This can appear in exception handlers in combination with
1450 a subsequent save to the stack frame. */
1453 value[rc].reg = NIOS2_STATUS_REGNUM + ra;
1454 value[rc].offset = 0;
1458 else if (nios2_match_calli (insn, op, mach, &uimm))
1460 if (value[8].reg == NIOS2_RA_REGNUM
1461 && value[8].offset == 0
1462 && value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM
1463 && value[NIOS2_SP_REGNUM].offset == 0)
1465 /* A CALL instruction. This is treated as a call to mcount
1466 if ra has been stored into r8 beforehand and if it's
1467 before the stack adjust.
1468 Note mcount corrupts r2-r3, r9-r15 & ra. */
1469 for (int i = 2 ; i <= 3 ; i++)
1471 for (int i = 9 ; i <= 15 ; i++)
1473 value[NIOS2_RA_REGNUM].reg = -1;
1478 /* Other calls are not part of the prologue. */
1483 else if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond))
1485 /* Branches not involving a stack overflow check aren't part of
1487 if (ra != NIOS2_SP_REGNUM)
1489 else if (cond == branch_geu)
1493 This instruction sequence is used in stack checking;
1494 we can ignore it. */
1495 unsigned int next_insn;
1496 const struct nios2_opcode *next_op
1497 = nios2_fetch_insn (gdbarch, pc, &next_insn);
1499 && (nios2_match_trap (next_insn, op, mach, &uimm)
1500 || nios2_match_break (next_insn, op, mach, &uimm)))
1501 pc += next_op->size;
1505 else if (cond == branch_ltu)
1507 /* BLTU sp, rx, .Lstackoverflow
1508 If the location branched to holds a TRAP or BREAK
1509 instruction then this is also stack overflow detection. */
1510 unsigned int next_insn;
1511 const struct nios2_opcode *next_op
1512 = nios2_fetch_insn (gdbarch, pc + imm, &next_insn);
1514 && (nios2_match_trap (next_insn, op, mach, &uimm)
1515 || nios2_match_break (next_insn, op, mach, &uimm)))
1524 /* All other calls, jumps, returns, TRAPs, or BREAKs terminate
1526 else if (nios2_match_callr (insn, op, mach, &ra)
1527 || nios2_match_jmpr (insn, op, mach, &ra)
1528 || nios2_match_jmpi (insn, op, mach, &uimm)
1529 || (nios2_match_ldwm (insn, op, mach, ®list, &ra,
1530 &imm, &wb, &id, &ret)
1532 || nios2_match_trap (insn, op, mach, &uimm)
1533 || nios2_match_break (insn, op, mach, &uimm))
1537 /* If THIS_FRAME is NULL, we are being called from skip_prologue
1538 and are only interested in the PROLOGUE_END value, so just
1539 return that now and skip over the cache updates, which depend
1540 on having frame information. */
1541 if (this_frame == NULL)
1542 return prologue_end;
1544 /* If we are in the function epilogue and have already popped
1545 registers off the stack in preparation for returning, then we
1546 want to go back to the original register values. */
1547 if (innermost && nios2_in_epilogue_p (gdbarch, current_pc, start_pc))
1548 nios2_setup_default (cache);
1550 /* Exception handlers use a different return address register. */
1551 if (exception_handler)
1552 cache->return_regnum = NIOS2_EA_REGNUM;
1555 fprintf_unfiltered (gdb_stdlog, "\n-> retreg=%d, ", cache->return_regnum);
1557 if (cache->reg_value[NIOS2_FP_REGNUM].reg == NIOS2_SP_REGNUM)
1558 /* If the FP now holds an offset from the CFA then this is a
1559 normal frame which uses the frame pointer. */
1560 base_reg = NIOS2_FP_REGNUM;
1561 else if (cache->reg_value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM)
1562 /* FP doesn't hold an offset from the CFA. If SP still holds an
1563 offset from the CFA then we might be in a function which omits
1564 the frame pointer, or we might be partway through the prologue.
1565 In both cases we can find the CFA using SP. */
1566 base_reg = NIOS2_SP_REGNUM;
1569 /* Somehow the stack pointer has been corrupted.
1572 fprintf_unfiltered (gdb_stdlog, "<can't reach cfa> }\n");
1576 if (cache->reg_value[base_reg].offset == 0
1577 || cache->reg_saved[NIOS2_RA_REGNUM].basereg != NIOS2_SP_REGNUM
1578 || cache->reg_saved[cache->return_regnum].basereg != NIOS2_SP_REGNUM)
1580 /* If the frame didn't adjust the stack, didn't save RA or
1581 didn't save EA in an exception handler then it must either
1582 be a leaf function (doesn't call any other functions) or it
1583 can't return. If it has called another function then it
1584 can't be a leaf, so set base == 0 to indicate that we can't
1585 backtrace past it. */
1589 /* If it isn't the innermost function then it can't be a
1590 leaf, unless it was interrupted. Check whether RA for
1591 this frame is the same as PC. If so then it probably
1592 wasn't interrupted. */
1594 = get_frame_register_unsigned (this_frame, NIOS2_RA_REGNUM);
1596 if (ra == current_pc)
1601 "<noreturn ADJUST %s, r31@r%d+?>, r%d@r%d+?> }\n",
1602 paddress (gdbarch, cache->reg_value[base_reg].offset),
1603 cache->reg_saved[NIOS2_RA_REGNUM].basereg,
1604 cache->return_regnum,
1605 cache->reg_saved[cache->return_regnum].basereg);
1611 /* Get the value of whichever register we are using for the
1613 cache->base = get_frame_register_unsigned (this_frame, base_reg);
1615 /* What was the value of SP at the start of this function (or just
1616 after the stack switch). */
1617 frame_high = cache->base - cache->reg_value[base_reg].offset;
1619 /* Adjust all the saved registers such that they contain addresses
1620 instead of offsets. */
1621 for (int i = 0; i < NIOS2_NUM_REGS; i++)
1622 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM)
1624 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM;
1625 cache->reg_saved[i].addr += frame_high;
1628 for (int i = 0; i < NIOS2_NUM_REGS; i++)
1629 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM)
1631 CORE_ADDR gp = get_frame_register_unsigned (this_frame,
1634 for ( ; i < NIOS2_NUM_REGS; i++)
1635 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM)
1637 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM;
1638 cache->reg_saved[i].addr += gp;
1642 /* Work out what the value of SP was on the first instruction of
1643 this function. If we didn't switch stacks then this can be
1644 trivially computed from the base address. */
1645 if (cache->reg_saved[NIOS2_SP_REGNUM].basereg == NIOS2_Z_REGNUM)
1647 = read_memory_unsigned_integer (cache->reg_saved[NIOS2_SP_REGNUM].addr,
1650 cache->cfa = frame_high;
1652 /* Exception handlers restore ESTATUS into STATUS. */
1653 if (exception_handler)
1655 cache->reg_saved[NIOS2_STATUS_REGNUM]
1656 = cache->reg_saved[NIOS2_ESTATUS_REGNUM];
1657 cache->reg_saved[NIOS2_ESTATUS_REGNUM].basereg = -1;
1661 fprintf_unfiltered (gdb_stdlog, "cfa=%s }\n",
1662 paddress (gdbarch, cache->cfa));
1664 return prologue_end;
1667 /* Implement the skip_prologue gdbarch hook. */
1670 nios2_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1672 CORE_ADDR func_addr;
1674 struct nios2_unwind_cache cache;
1676 /* See if we can determine the end of the prologue via the symbol
1677 table. If so, then return either PC, or the PC after the
1678 prologue, whichever is greater. */
1679 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1681 CORE_ADDR post_prologue_pc
1682 = skip_prologue_using_sal (gdbarch, func_addr);
1684 if (post_prologue_pc != 0)
1685 return std::max (start_pc, post_prologue_pc);
1688 /* Prologue analysis does the rest.... */
1689 nios2_init_cache (&cache, start_pc);
1690 return nios2_analyze_prologue (gdbarch, start_pc, start_pc, &cache, NULL);
1693 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1696 nios2_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1698 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1700 if (mach == bfd_mach_nios2r2)
1703 const struct nios2_opcode *op
1704 = nios2_fetch_insn (gdbarch, *pcptr, &insn);
1706 if (op && op->size == NIOS2_CDX_OPCODE_SIZE)
1707 return NIOS2_CDX_OPCODE_SIZE;
1709 return NIOS2_OPCODE_SIZE;
1712 return NIOS2_OPCODE_SIZE;
1715 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1717 static const gdb_byte *
1718 nios2_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1720 /* The Nios II ABI for Linux says: "Userspace programs should not use
1721 the break instruction and userspace debuggers should not insert
1722 one." and "Userspace breakpoints are accomplished using the trap
1723 instruction with immediate operand 31 (all ones)."
1725 So, we use "trap 31" consistently as the breakpoint on bare-metal
1726 as well as Linux targets. */
1728 /* R2 trap encoding:
1729 ((0x2d << 26) | (0x1f << 21) | (0x1d << 16) | (0x20 << 0))
1731 CDX trap.n encoding:
1732 ((0xd << 12) | (0x1f << 6) | (0x9 << 0))
1734 Note that code is always little-endian on R2. */
1737 if (kind == NIOS2_CDX_OPCODE_SIZE)
1739 static const gdb_byte cdx_breakpoint_le[] = {0xc9, 0xd7};
1741 return cdx_breakpoint_le;
1745 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1747 if (mach == bfd_mach_nios2r2)
1749 static const gdb_byte r2_breakpoint_le[] = {0x20, 0x00, 0xfd, 0xb7};
1751 return r2_breakpoint_le;
1755 enum bfd_endian byte_order_for_code
1756 = gdbarch_byte_order_for_code (gdbarch);
1757 /* R1 trap encoding:
1758 ((0x1d << 17) | (0x2d << 11) | (0x1f << 6) | (0x3a << 0))
1760 static const gdb_byte r1_breakpoint_le[] = {0xfa, 0x6f, 0x3b, 0x0};
1761 static const gdb_byte r1_breakpoint_be[] = {0x0, 0x3b, 0x6f, 0xfa};
1763 if (byte_order_for_code == BFD_ENDIAN_BIG)
1764 return r1_breakpoint_be;
1766 return r1_breakpoint_le;
1771 /* Implement the frame_align gdbarch method. */
1774 nios2_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1776 return align_down (addr, 4);
1780 /* Implement the return_value gdbarch method. */
1782 static enum return_value_convention
1783 nios2_return_value (struct gdbarch *gdbarch, struct value *function,
1784 struct type *type, struct regcache *regcache,
1785 gdb_byte *readbuf, const gdb_byte *writebuf)
1787 if (TYPE_LENGTH (type) > 8)
1788 return RETURN_VALUE_STRUCT_CONVENTION;
1791 nios2_extract_return_value (gdbarch, type, regcache, readbuf);
1793 nios2_store_return_value (gdbarch, type, regcache, writebuf);
1795 return RETURN_VALUE_REGISTER_CONVENTION;
1798 /* Implement the dummy_id gdbarch method. */
1800 static struct frame_id
1801 nios2_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1803 return frame_id_build
1804 (get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM),
1805 get_frame_pc (this_frame));
1808 /* Implement the push_dummy_call gdbarch method. */
1811 nios2_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1812 struct regcache *regcache, CORE_ADDR bp_addr,
1813 int nargs, struct value **args, CORE_ADDR sp,
1814 function_call_return_method return_method,
1815 CORE_ADDR struct_addr)
1820 int stack_offset = 0;
1821 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1823 /* Set the return address register to point to the entry point of
1824 the program, where a breakpoint lies in wait. */
1825 regcache_cooked_write_signed (regcache, NIOS2_RA_REGNUM, bp_addr);
1827 /* Now make space on the stack for the args. */
1828 for (argnum = 0; argnum < nargs; argnum++)
1829 arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
1832 /* Initialize the register pointer. */
1833 argreg = NIOS2_FIRST_ARGREG;
1835 /* The struct_return pointer occupies the first parameter-passing
1837 if (return_method == return_method_struct)
1838 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
1840 /* Now load as many as possible of the first arguments into
1841 registers, and push the rest onto the stack. Loop through args
1842 from first to last. */
1843 for (argnum = 0; argnum < nargs; argnum++)
1845 const gdb_byte *val;
1846 struct value *arg = args[argnum];
1847 struct type *arg_type = check_typedef (value_type (arg));
1848 int len = TYPE_LENGTH (arg_type);
1850 val = value_contents (arg);
1852 /* Copy the argument to general registers or the stack in
1853 register-sized pieces. Large arguments are split between
1854 registers and stack. */
1857 int partial_len = (len < 4 ? len : 4);
1859 if (argreg <= NIOS2_LAST_ARGREG)
1861 /* The argument is being passed in a register. */
1862 CORE_ADDR regval = extract_unsigned_integer (val, partial_len,
1865 regcache_cooked_write_unsigned (regcache, argreg, regval);
1870 /* The argument is being passed on the stack. */
1871 CORE_ADDR addr = sp + stack_offset;
1873 write_memory (addr, val, partial_len);
1874 stack_offset += align_up (partial_len, 4);
1882 regcache_cooked_write_signed (regcache, NIOS2_SP_REGNUM, sp);
1884 /* Return adjusted stack pointer. */
1888 /* Implement the unwind_pc gdbarch method. */
1891 nios2_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1895 frame_unwind_register (next_frame, NIOS2_PC_REGNUM, buf);
1896 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1899 /* Implement the unwind_sp gdbarch method. */
1902 nios2_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1904 return frame_unwind_register_unsigned (this_frame, NIOS2_SP_REGNUM);
1907 /* Use prologue analysis to fill in the register cache
1908 *THIS_PROLOGUE_CACHE for THIS_FRAME. This function initializes
1909 *THIS_PROLOGUE_CACHE first. */
1911 static struct nios2_unwind_cache *
1912 nios2_frame_unwind_cache (struct frame_info *this_frame,
1913 void **this_prologue_cache)
1915 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1916 CORE_ADDR current_pc;
1917 struct nios2_unwind_cache *cache;
1919 if (*this_prologue_cache)
1920 return (struct nios2_unwind_cache *) *this_prologue_cache;
1922 cache = FRAME_OBSTACK_ZALLOC (struct nios2_unwind_cache);
1923 *this_prologue_cache = cache;
1925 /* Zero all fields. */
1926 nios2_init_cache (cache, get_frame_func (this_frame));
1928 /* Prologue analysis does the rest... */
1929 current_pc = get_frame_pc (this_frame);
1931 nios2_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);
1936 /* Implement the this_id function for the normal unwinder. */
1939 nios2_frame_this_id (struct frame_info *this_frame, void **this_cache,
1940 struct frame_id *this_id)
1942 struct nios2_unwind_cache *cache =
1943 nios2_frame_unwind_cache (this_frame, this_cache);
1945 /* This marks the outermost frame. */
1946 if (cache->base == 0)
1949 *this_id = frame_id_build (cache->cfa, cache->pc);
1952 /* Implement the prev_register function for the normal unwinder. */
1954 static struct value *
1955 nios2_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1958 struct nios2_unwind_cache *cache =
1959 nios2_frame_unwind_cache (this_frame, this_cache);
1961 gdb_assert (regnum >= 0 && regnum < NIOS2_NUM_REGS);
1963 /* The PC of the previous frame is stored in the RA register of
1964 the current frame. Frob regnum so that we pull the value from
1965 the correct place. */
1966 if (regnum == NIOS2_PC_REGNUM)
1967 regnum = cache->return_regnum;
1969 if (regnum == NIOS2_SP_REGNUM && cache->cfa)
1970 return frame_unwind_got_constant (this_frame, regnum, cache->cfa);
1972 /* If we've worked out where a register is stored then load it from
1974 if (cache->reg_saved[regnum].basereg == NIOS2_Z_REGNUM)
1975 return frame_unwind_got_memory (this_frame, regnum,
1976 cache->reg_saved[regnum].addr);
1978 return frame_unwind_got_register (this_frame, regnum, regnum);
1981 /* Implement the this_base, this_locals, and this_args hooks
1982 for the normal unwinder. */
1985 nios2_frame_base_address (struct frame_info *this_frame, void **this_cache)
1987 struct nios2_unwind_cache *info
1988 = nios2_frame_unwind_cache (this_frame, this_cache);
1993 /* Data structures for the normal prologue-analysis-based
1996 static const struct frame_unwind nios2_frame_unwind =
1999 default_frame_unwind_stop_reason,
2000 nios2_frame_this_id,
2001 nios2_frame_prev_register,
2003 default_frame_sniffer
2006 static const struct frame_base nios2_frame_base =
2008 &nios2_frame_unwind,
2009 nios2_frame_base_address,
2010 nios2_frame_base_address,
2011 nios2_frame_base_address
2014 /* Fill in the register cache *THIS_CACHE for THIS_FRAME for use
2015 in the stub unwinder. */
2017 static struct trad_frame_cache *
2018 nios2_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
2021 CORE_ADDR start_addr;
2022 CORE_ADDR stack_addr;
2023 struct trad_frame_cache *this_trad_cache;
2024 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2026 if (*this_cache != NULL)
2027 return (struct trad_frame_cache *) *this_cache;
2028 this_trad_cache = trad_frame_cache_zalloc (this_frame);
2029 *this_cache = this_trad_cache;
2031 /* The return address is in the link register. */
2032 trad_frame_set_reg_realreg (this_trad_cache,
2033 gdbarch_pc_regnum (gdbarch),
2036 /* Frame ID, since it's a frameless / stackless function, no stack
2037 space is allocated and SP on entry is the current SP. */
2038 pc = get_frame_pc (this_frame);
2039 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2040 stack_addr = get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM);
2041 trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr));
2042 /* Assume that the frame's base is the same as the stack pointer. */
2043 trad_frame_set_this_base (this_trad_cache, stack_addr);
2045 return this_trad_cache;
2048 /* Implement the this_id function for the stub unwinder. */
2051 nios2_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
2052 struct frame_id *this_id)
2054 struct trad_frame_cache *this_trad_cache
2055 = nios2_stub_frame_cache (this_frame, this_cache);
2057 trad_frame_get_id (this_trad_cache, this_id);
2060 /* Implement the prev_register function for the stub unwinder. */
2062 static struct value *
2063 nios2_stub_frame_prev_register (struct frame_info *this_frame,
2064 void **this_cache, int regnum)
2066 struct trad_frame_cache *this_trad_cache
2067 = nios2_stub_frame_cache (this_frame, this_cache);
2069 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
2072 /* Implement the sniffer function for the stub unwinder.
2073 This unwinder is used for cases where the normal
2074 prologue-analysis-based unwinder can't work,
2075 such as PLT stubs. */
2078 nios2_stub_frame_sniffer (const struct frame_unwind *self,
2079 struct frame_info *this_frame, void **cache)
2082 CORE_ADDR pc = get_frame_address_in_block (this_frame);
2084 /* Use the stub unwinder for unreadable code. */
2085 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2088 if (in_plt_section (pc))
2094 /* Define the data structures for the stub unwinder. */
2096 static const struct frame_unwind nios2_stub_frame_unwind =
2099 default_frame_unwind_stop_reason,
2100 nios2_stub_frame_this_id,
2101 nios2_stub_frame_prev_register,
2103 nios2_stub_frame_sniffer
2108 /* Determine where to set a single step breakpoint while considering
2109 branch prediction. */
2112 nios2_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
2114 struct gdbarch *gdbarch = regcache->arch ();
2115 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2116 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
2118 const struct nios2_opcode *op = nios2_fetch_insn (gdbarch, pc, &insn);
2124 enum branch_condition cond;
2126 /* Do something stupid if we can't disassemble the insn at pc. */
2128 return pc + NIOS2_OPCODE_SIZE;
2130 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond))
2132 int ras = regcache_raw_get_signed (regcache, ra);
2133 int rbs = regcache_raw_get_signed (regcache, rb);
2134 unsigned int rau = regcache_raw_get_unsigned (regcache, ra);
2135 unsigned int rbu = regcache_raw_get_unsigned (regcache, rb);
2172 else if (nios2_match_jmpi (insn, op, mach, &uimm))
2173 pc = (pc & 0xf0000000) | uimm;
2174 else if (nios2_match_calli (insn, op, mach, &uimm))
2176 CORE_ADDR callto = (pc & 0xf0000000) | uimm;
2177 if (tdep->is_kernel_helper != NULL
2178 && tdep->is_kernel_helper (callto))
2179 /* Step over call to kernel helper, which we cannot debug
2186 else if (nios2_match_jmpr (insn, op, mach, &ra))
2187 pc = regcache_raw_get_unsigned (regcache, ra);
2188 else if (nios2_match_callr (insn, op, mach, &ra))
2190 CORE_ADDR callto = regcache_raw_get_unsigned (regcache, ra);
2191 if (tdep->is_kernel_helper != NULL
2192 && tdep->is_kernel_helper (callto))
2193 /* Step over call to kernel helper. */
2199 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret)
2202 /* If ra is in the reglist, we have to use the value saved in the
2203 stack frame rather than the current value. */
2204 if (uimm & (1 << NIOS2_RA_REGNUM))
2205 pc = nios2_unwind_pc (gdbarch, get_current_frame ());
2207 pc = regcache_raw_get_unsigned (regcache, NIOS2_RA_REGNUM);
2210 else if (nios2_match_trap (insn, op, mach, &uimm) && uimm == 0)
2212 if (tdep->syscall_next_pc != NULL)
2213 return tdep->syscall_next_pc (get_current_frame (), op);
2222 /* Implement the software_single_step gdbarch method. */
2224 static std::vector<CORE_ADDR>
2225 nios2_software_single_step (struct regcache *regcache)
2227 CORE_ADDR next_pc = nios2_get_next_pc (regcache, regcache_read_pc (regcache));
2232 /* Implement the get_longjump_target gdbarch method. */
2235 nios2_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2237 struct gdbarch *gdbarch = get_frame_arch (frame);
2238 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2239 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2240 CORE_ADDR jb_addr = get_frame_register_unsigned (frame, NIOS2_R4_REGNUM);
2243 if (target_read_memory (jb_addr + (tdep->jb_pc * 4), buf, 4))
2246 *pc = extract_unsigned_integer (buf, 4, byte_order);
2250 /* Implement the type_align gdbarch function. */
2253 nios2_type_align (struct gdbarch *gdbarch, struct type *type)
2255 switch (TYPE_CODE (type))
2258 case TYPE_CODE_FUNC:
2259 case TYPE_CODE_FLAGS:
2261 case TYPE_CODE_RANGE:
2263 case TYPE_CODE_ENUM:
2265 case TYPE_CODE_RVALUE_REF:
2266 case TYPE_CODE_CHAR:
2267 case TYPE_CODE_BOOL:
2268 case TYPE_CODE_DECFLOAT:
2269 case TYPE_CODE_METHODPTR:
2270 case TYPE_CODE_MEMBERPTR:
2271 type = check_typedef (type);
2272 return std::min<ULONGEST> (4, TYPE_LENGTH (type));
2278 /* Implement the gcc_target_options gdbarch method. */
2280 nios2_gcc_target_options (struct gdbarch *gdbarch)
2282 /* GCC doesn't know "-m32". */
2286 /* Initialize the Nios II gdbarch. */
2288 static struct gdbarch *
2289 nios2_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2291 struct gdbarch *gdbarch;
2292 struct gdbarch_tdep *tdep;
2294 struct tdesc_arch_data *tdesc_data = NULL;
2295 const struct target_desc *tdesc = info.target_desc;
2297 if (!tdesc_has_registers (tdesc))
2298 /* Pick a default target description. */
2299 tdesc = tdesc_nios2;
2301 /* Check any target description for validity. */
2302 if (tdesc_has_registers (tdesc))
2304 const struct tdesc_feature *feature;
2307 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nios2.cpu");
2308 if (feature == NULL)
2311 tdesc_data = tdesc_data_alloc ();
2315 for (i = 0; i < NIOS2_NUM_REGS; i++)
2316 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2317 nios2_reg_names[i]);
2321 tdesc_data_cleanup (tdesc_data);
2326 /* Find a candidate among the list of pre-declared architectures. */
2327 arches = gdbarch_list_lookup_by_info (arches, &info);
2329 return arches->gdbarch;
2331 /* None found, create a new architecture from the information
2333 tdep = XCNEW (struct gdbarch_tdep);
2334 gdbarch = gdbarch_alloc (&info, tdep);
2336 /* longjmp support not enabled by default. */
2339 /* Data type sizes. */
2340 set_gdbarch_ptr_bit (gdbarch, 32);
2341 set_gdbarch_addr_bit (gdbarch, 32);
2342 set_gdbarch_short_bit (gdbarch, 16);
2343 set_gdbarch_int_bit (gdbarch, 32);
2344 set_gdbarch_long_bit (gdbarch, 32);
2345 set_gdbarch_long_long_bit (gdbarch, 64);
2346 set_gdbarch_float_bit (gdbarch, 32);
2347 set_gdbarch_double_bit (gdbarch, 64);
2349 set_gdbarch_type_align (gdbarch, nios2_type_align);
2351 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2352 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2354 /* The register set. */
2355 set_gdbarch_num_regs (gdbarch, NIOS2_NUM_REGS);
2356 set_gdbarch_sp_regnum (gdbarch, NIOS2_SP_REGNUM);
2357 set_gdbarch_pc_regnum (gdbarch, NIOS2_PC_REGNUM); /* Pseudo register PC */
2359 set_gdbarch_register_name (gdbarch, nios2_register_name);
2360 set_gdbarch_register_type (gdbarch, nios2_register_type);
2362 /* Provide register mappings for stabs and dwarf2. */
2363 set_gdbarch_stab_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum);
2364 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum);
2366 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2368 /* Call dummy code. */
2369 set_gdbarch_frame_align (gdbarch, nios2_frame_align);
2371 set_gdbarch_return_value (gdbarch, nios2_return_value);
2373 set_gdbarch_skip_prologue (gdbarch, nios2_skip_prologue);
2374 set_gdbarch_stack_frame_destroyed_p (gdbarch, nios2_stack_frame_destroyed_p);
2375 set_gdbarch_breakpoint_kind_from_pc (gdbarch, nios2_breakpoint_kind_from_pc);
2376 set_gdbarch_sw_breakpoint_from_kind (gdbarch, nios2_sw_breakpoint_from_kind);
2378 set_gdbarch_dummy_id (gdbarch, nios2_dummy_id);
2379 set_gdbarch_unwind_pc (gdbarch, nios2_unwind_pc);
2380 set_gdbarch_unwind_sp (gdbarch, nios2_unwind_sp);
2382 /* The dwarf2 unwinder will normally produce the best results if
2383 the debug information is available, so register it first. */
2384 dwarf2_append_unwinders (gdbarch);
2385 frame_unwind_append_unwinder (gdbarch, &nios2_stub_frame_unwind);
2386 frame_unwind_append_unwinder (gdbarch, &nios2_frame_unwind);
2388 /* Single stepping. */
2389 set_gdbarch_software_single_step (gdbarch, nios2_software_single_step);
2391 /* Target options for compile. */
2392 set_gdbarch_gcc_target_options (gdbarch, nios2_gcc_target_options);
2394 /* Hook in ABI-specific overrides, if they have been registered. */
2395 gdbarch_init_osabi (info, gdbarch);
2397 if (tdep->jb_pc >= 0)
2398 set_gdbarch_get_longjmp_target (gdbarch, nios2_get_longjmp_target);
2400 frame_base_set_default (gdbarch, &nios2_frame_base);
2402 /* Enable inferior call support. */
2403 set_gdbarch_push_dummy_call (gdbarch, nios2_push_dummy_call);
2406 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2412 _initialize_nios2_tdep (void)
2414 gdbarch_register (bfd_arch_nios2, nios2_gdbarch_init, NULL);
2415 initialize_tdesc_nios2 ();
2417 /* Allow debugging this file's internals. */
2418 add_setshow_boolean_cmd ("nios2", class_maintenance, &nios2_debug,
2419 _("Set Nios II debugging."),
2420 _("Show Nios II debugging."),
2421 _("When on, Nios II specific debugging is enabled."),
2424 &setdebuglist, &showdebuglist);