1 /* Target-dependent code for the NDS32 architecture, for GDB.
3 Copyright (C) 2013-2016 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
29 #include "reggroups.h"
32 #include "arch-utils.h"
35 #include "user-regs.h"
37 #include "dwarf2-frame.h"
39 #include "target-descriptions.h"
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
44 #include "features/nds32.c"
46 /* Simple macros for instruction analysis. */
47 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
48 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
50 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
52 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
54 N32_TYPE2 (LDC, 0, REG_SP, 0)
56 extern void _initialize_nds32_tdep (void);
58 /* Use an invalid address value as 'not available' marker. */
59 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
61 /* Use an impossible value as invalid offset. */
62 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
64 /* Instruction groups for NDS32 epilogue analysis. */
67 /* Instructions used everywhere, not only in epilogue. */
69 /* Instructions used to reset sp for local vars, arguments, etc. */
71 /* Instructions used to recover saved regs and to recover padding. */
73 /* Instructions used to return to the caller. */
75 /* Instructions used to recover saved regs and to return to the caller. */
79 static const char *const nds32_register_names[] =
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
85 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
90 static const char *const nds32_fdr_register_names[] =
92 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
93 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
94 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
95 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
98 static const char *const nds32_fsr_register_names[] =
100 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
101 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
102 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
103 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
106 /* The number of registers for four FPU configuration options. */
107 const int num_fdr_map[] = { 4, 8, 16, 32 };
108 const int num_fsr_map[] = { 8, 16, 32, 32 };
110 /* Aliases for registers. */
115 } nds32_register_aliases[] =
131 {"cr6", "fucop_exist"},
148 {"ir14", "int_mask"},
149 {"ir15", "int_pend"},
153 {"ir19", "int_ctrl"},
155 {"ir21", "sp_priv1"},
157 {"ir23", "sp_priv2"},
159 {"ir25", "sp_priv3"},
160 {"ir26", "int_mask2"},
161 {"ir27", "int_pend2"},
162 {"ir28", "int_pri2"},
163 {"ir29", "int_trigger"},
173 {"mr8", "cache_ctl"},
174 {"mr9", "hsmp_saddr"},
175 {"mr10", "hsmp_eaddr"},
176 {"mr11", "bg_region"},
227 {"hspr0", "hsp_ctl"},
228 {"hspr1", "sp_bound"},
229 {"hspr2", "sp_bound_priv"},
237 {"dmar0", "dma_cfg"},
238 {"dmar1", "dma_gcsw"},
239 {"dmar2", "dma_chnsel"},
240 {"dmar3", "dma_act"},
241 {"dmar4", "dma_setup"},
242 {"dmar5", "dma_isaddr"},
243 {"dmar6", "dma_esaddr"},
244 {"dmar7", "dma_tcnt"},
245 {"dmar8", "dma_status"},
246 {"dmar9", "dma_2dset"},
247 {"dmar10", "dma_2dsctl"},
248 {"dmar11", "dma_rcnt"},
249 {"dmar12", "dma_hstatus"},
251 {"racr0", "prusr_acc_ctl"},
252 {"fucpr", "fucop_ctl"},
255 {"idr1", "misc_ctl"},
256 {"idr2", "ecc_misc"},
261 {"secur3", "p_isign"},
264 /* Value of a register alias. BATON is the regnum of the corresponding
267 static struct value *
268 value_of_nds32_reg (struct frame_info *frame, const void *baton)
270 return value_of_register ((int) (intptr_t) baton, frame);
273 /* Implement the "frame_align" gdbarch method. */
276 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
278 /* 8-byte aligned. */
279 return align_down (sp, 8);
282 /* Implement the "breakpoint_from_pc" gdbarch method.
284 Use the program counter to determine the contents and size of a
285 breakpoint instruction. Return a pointer to a string of bytes that
286 encode a breakpoint instruction, store the length of the string in
287 *LENPTR and optionally adjust *PCPTR to point to the correct memory
288 location for inserting the breakpoint. */
290 static const gdb_byte *
291 nds32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
294 /* The same insn machine code is used for little-endian and big-endian. */
295 static const gdb_byte break_insn[] = { 0xEA, 0x00 };
297 *lenptr = sizeof (break_insn);
301 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
304 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
306 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
308 const int FDR = FSR + 32;
310 if (num >= 0 && num < 32)
312 /* General-purpose registers (R0 - R31). */
315 else if (num >= FSR && num < FSR + 32)
317 /* Single precision floating-point registers (FS0 - FS31). */
318 return num - FSR + tdep->fs0_regnum;
320 else if (num >= FDR && num < FDR + 32)
322 /* Double precision floating-point registers (FD0 - FD31). */
323 return num - FDR + NDS32_FD0_REGNUM;
326 /* No match, return a inaccessible register number. */
330 /* NDS32 register groups. */
331 static struct reggroup *nds32_cr_reggroup;
332 static struct reggroup *nds32_ir_reggroup;
333 static struct reggroup *nds32_mr_reggroup;
334 static struct reggroup *nds32_dr_reggroup;
335 static struct reggroup *nds32_pfr_reggroup;
336 static struct reggroup *nds32_hspr_reggroup;
337 static struct reggroup *nds32_dmar_reggroup;
338 static struct reggroup *nds32_racr_reggroup;
339 static struct reggroup *nds32_idr_reggroup;
340 static struct reggroup *nds32_secur_reggroup;
343 nds32_init_reggroups (void)
345 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
346 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
347 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
348 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
349 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
350 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
351 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
352 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
353 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
354 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
358 nds32_add_reggroups (struct gdbarch *gdbarch)
360 /* Add pre-defined register groups. */
361 reggroup_add (gdbarch, general_reggroup);
362 reggroup_add (gdbarch, float_reggroup);
363 reggroup_add (gdbarch, system_reggroup);
364 reggroup_add (gdbarch, all_reggroup);
365 reggroup_add (gdbarch, save_reggroup);
366 reggroup_add (gdbarch, restore_reggroup);
368 /* Add NDS32 register groups. */
369 reggroup_add (gdbarch, nds32_cr_reggroup);
370 reggroup_add (gdbarch, nds32_ir_reggroup);
371 reggroup_add (gdbarch, nds32_mr_reggroup);
372 reggroup_add (gdbarch, nds32_dr_reggroup);
373 reggroup_add (gdbarch, nds32_pfr_reggroup);
374 reggroup_add (gdbarch, nds32_hspr_reggroup);
375 reggroup_add (gdbarch, nds32_dmar_reggroup);
376 reggroup_add (gdbarch, nds32_racr_reggroup);
377 reggroup_add (gdbarch, nds32_idr_reggroup);
378 reggroup_add (gdbarch, nds32_secur_reggroup);
381 /* Implement the "register_reggroup_p" gdbarch method. */
384 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
385 struct reggroup *reggroup)
387 const char *reg_name;
388 const char *group_name;
391 if (reggroup == all_reggroup)
394 /* General reggroup contains only GPRs and PC. */
395 if (reggroup == general_reggroup)
396 return regnum <= NDS32_PC_REGNUM;
398 if (reggroup == float_reggroup || reggroup == save_reggroup
399 || reggroup == restore_reggroup)
401 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
405 return default_register_reggroup_p (gdbarch, regnum, reggroup);
408 if (reggroup == system_reggroup)
409 return (regnum > NDS32_PC_REGNUM)
410 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
412 /* The NDS32 reggroup contains registers whose name is prefixed
414 reg_name = gdbarch_register_name (gdbarch, regnum);
415 group_name = reggroup_name (reggroup);
416 return !strncmp (reg_name, group_name, strlen (group_name));
419 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
422 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
424 regnum -= gdbarch_num_regs (gdbarch);
426 /* Currently, only FSRs could be defined as pseudo registers. */
427 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
428 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
429 floatformats_ieee_single);
431 warning (_("Unknown nds32 pseudo register %d."), regnum);
435 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
438 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
440 regnum -= gdbarch_num_regs (gdbarch);
442 /* Currently, only FSRs could be defined as pseudo registers. */
443 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
444 return nds32_fsr_register_names[regnum];
446 warning (_("Unknown nds32 pseudo register %d."), regnum);
450 /* Implement the "pseudo_register_read" gdbarch method. */
452 static enum register_status
453 nds32_pseudo_register_read (struct gdbarch *gdbarch,
454 struct regcache *regcache, int regnum,
457 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
459 int offset, fdr_regnum;
460 enum register_status status = REG_UNKNOWN;
463 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
466 regnum -= gdbarch_num_regs (gdbarch);
468 /* Currently, only FSRs could be defined as pseudo registers. */
469 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
471 /* fs0 is always the most significant half of fd0. */
472 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
473 offset = (regnum & 1) ? 4 : 0;
475 offset = (regnum & 1) ? 0 : 4;
477 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
478 status = regcache_raw_read (regcache, fdr_regnum, reg_buf);
479 if (status == REG_VALID)
480 memcpy (buf, reg_buf + offset, 4);
486 /* Implement the "pseudo_register_write" gdbarch method. */
489 nds32_pseudo_register_write (struct gdbarch *gdbarch,
490 struct regcache *regcache, int regnum,
493 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
495 int offset, fdr_regnum;
498 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
501 regnum -= gdbarch_num_regs (gdbarch);
503 /* Currently, only FSRs could be defined as pseudo registers. */
504 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
506 /* fs0 is always the most significant half of fd0. */
507 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
508 offset = (regnum & 1) ? 4 : 0;
510 offset = (regnum & 1) ? 0 : 4;
512 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
513 regcache_raw_read (regcache, fdr_regnum, reg_buf);
514 memcpy (reg_buf + offset, buf, 4);
515 regcache_raw_write (regcache, fdr_regnum, reg_buf);
519 /* Helper function for NDS32 ABI. Return true if FPRs can be used
520 to pass function arguments and return value. */
523 nds32_abi_use_fpr (int elf_abi)
525 return elf_abi == E_NDS_ABI_V2FP_PLUS;
528 /* Helper function for NDS32 ABI. Return true if GPRs and stack
529 can be used together to pass an argument. */
532 nds32_abi_split (int elf_abi)
534 return elf_abi == E_NDS_ABI_AABI;
537 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
539 struct nds32_frame_cache
541 /* The previous frame's inner most stack address. Used as this
542 frame ID's stack_addr. */
545 /* The frame's base, optionally used by the high-level debug info. */
548 /* During prologue analysis, keep how far the SP and FP have been offset
549 from the start of the stack frame (as defined by the previous frame's
551 During epilogue analysis, keep how far the SP has been offset from the
552 current stack pointer. */
556 /* The address of the first instruction in this function. */
559 /* Saved registers. */
560 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
563 /* Allocate and initialize a frame cache. */
565 static struct nds32_frame_cache *
566 nds32_alloc_frame_cache (void)
568 struct nds32_frame_cache *cache;
571 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
573 /* Initialize fp_offset to check if FP is set in prologue. */
574 cache->fp_offset = INVALID_OFFSET;
576 /* Saved registers. We initialize these to -1 since zero is a valid
578 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
579 cache->saved_regs[i] = REG_UNAVAIL;
584 /* Helper function for instructions used to push multiple words. */
587 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
590 CORE_ADDR sp_offset = cache->sp_offset;
593 /* Check LP, GP, FP in enable4. */
594 for (i = 1; i <= 3; i++)
596 if ((enable4 >> i) & 0x1)
599 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
603 /* Skip case where re == rb == sp. */
604 if ((rb < REG_FP) && (re < REG_FP))
606 for (i = re; i >= rb; i--)
609 cache->saved_regs[i] = sp_offset;
613 /* For sp, update the offset. */
614 cache->sp_offset = sp_offset;
617 /* Analyze the instructions within the given address range. If CACHE
618 is non-NULL, fill it in. Return the first address beyond the given
619 address range. If CACHE is NULL, return the first address not
620 recognized as a prologue instruction. */
623 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
624 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
626 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
627 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
628 /* Current scanning status. */
629 int in_prologue_bb = 0;
631 uint32_t insn, insn_len;
633 for (; pc < limit_pc; pc += insn_len)
635 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
637 if ((insn & 0x80000000) == 0)
639 /* 32-bit instruction */
642 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
644 /* addi $sp, $sp, imm15s */
645 int imm15s = N32_IMM15S (insn);
650 cache->sp_offset += -imm15s;
656 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
658 /* addi $fp, $sp, imm15s */
659 int imm15s = N32_IMM15S (insn);
664 cache->fp_offset = cache->sp_offset - imm15s;
670 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
671 && N32_RA5 (insn) == REG_SP)
673 /* smw.adm Rb, [$sp], Re, enable4 */
675 nds32_push_multiple_words (cache, N32_RT5 (insn),
677 N32_LSMW_ENABLE4 (insn));
681 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
682 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
684 /* add $sp, $sp, $ta */
685 /* add $sp, $ta, $sp */
689 cache->sp_offset += -val_ta;
695 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
697 /* movi $ta, imm20s */
699 val_ta = N32_IMM20S (insn);
703 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
705 /* sethi $ta, imm20u */
707 val_ta = N32_IMM20U (insn) << 12;
711 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
713 /* ori $ta, $ta, imm15u */
715 val_ta |= N32_IMM15U (insn);
719 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
721 /* addi $ta, $ta, imm15s */
723 val_ta += N32_IMM15S (insn);
727 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
728 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
730 /* add $gp, $ta, $gp */
731 /* add $gp, $gp, $ta */
735 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
737 /* movi $gp, imm20s */
741 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
743 /* sethi $gp, imm20u */
747 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
749 /* ori $gp, $gp, imm15u */
755 /* Jump/Branch insns never appear in prologue basic block.
756 The loop can be escaped early when these insns are met. */
757 if (in_prologue_bb == 1)
759 int op = N32_OP6 (insn);
762 || op == N32_OP6_JREG
765 || op == N32_OP6_BR3)
770 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
771 && __GF (insn, 12, 3) == 0)
773 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
774 normal form (bit [12] == 0) is used. */
776 /* fsdi FDt, [$sp + (imm12s << 2)] */
777 if (N32_RA5 (insn) == REG_SP)
781 /* The optimizer might shove anything into the prologue, if
782 we build up cache (cache != NULL) from analyzing prologue,
783 we just skip what we don't recognize and analyze further to
784 make cache as complete as possible. However, if we skip
785 prologue, we'll stop immediately on unrecognized
792 /* 16-bit instruction */
797 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
800 int imm10s = N16_IMM10S (insn);
805 cache->sp_offset += -imm10s;
811 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
816 int imm8u = (insn & 0x1f) << 3;
817 int re = (insn >> 5) & 0x3;
818 const int reg_map[] = { 6, 8, 10, 14 };
820 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
821 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
823 /* Operation 2 -- sp = sp - (imm5u << 3) */
824 cache->sp_offset += imm8u;
830 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
836 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
838 /* movi55 $gp, imm5s */
844 /* Jump/Branch insns never appear in prologue basic block.
845 The loop can be escaped early when these insns are met. */
846 if (in_prologue_bb == 1)
848 uint32_t insn5 = CHOP_BITS (insn, 5);
849 uint32_t insn8 = CHOP_BITS (insn, 8);
850 uint32_t insn38 = CHOP_BITS (insn, 11);
852 if (insn5 == N16_TYPE5 (JR5, 0)
853 || insn5 == N16_TYPE5 (JRAL5, 0)
854 || insn5 == N16_TYPE5 (RET5, 0)
855 || insn8 == N16_TYPE8 (J8, 0)
856 || insn8 == N16_TYPE8 (BEQZS8, 0)
857 || insn8 == N16_TYPE8 (BNEZS8, 0)
858 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
859 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
860 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
861 || insn38 == N16_TYPE38 (BNES38, 0, 0))
866 /* The optimizer might shove anything into the prologue, if
867 we build up cache (cache != NULL) from analyzing prologue,
868 we just skip what we don't recognize and analyze further to
869 make cache as complete as possible. However, if we skip
870 prologue, we'll stop immediately on unrecognized
880 /* Implement the "skip_prologue" gdbarch method.
882 Find the end of function prologue. */
885 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
887 CORE_ADDR func_addr, limit_pc;
889 /* See if we can determine the end of the prologue via the symbol table.
890 If so, then return either PC, or the PC after the prologue, whichever
892 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
894 CORE_ADDR post_prologue_pc
895 = skip_prologue_using_sal (gdbarch, func_addr);
896 if (post_prologue_pc != 0)
897 return max (pc, post_prologue_pc);
900 /* Can't determine prologue from the symbol table, need to examine
903 /* Find an upper limit on the function prologue using the debug
904 information. If the debug information could not be used to provide
905 that bound, then use an arbitrary large number as the upper bound. */
906 limit_pc = skip_prologue_using_sal (gdbarch, pc);
908 limit_pc = pc + 128; /* Magic. */
910 /* Find the end of prologue. */
911 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
914 /* Allocate and fill in *THIS_CACHE with information about the prologue of
915 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
916 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
918 static struct nds32_frame_cache *
919 nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
921 struct gdbarch *gdbarch = get_frame_arch (this_frame);
922 struct nds32_frame_cache *cache;
923 CORE_ADDR current_pc;
929 return (struct nds32_frame_cache *) *this_cache;
931 cache = nds32_alloc_frame_cache ();
934 cache->pc = get_frame_func (this_frame);
935 current_pc = get_frame_pc (this_frame);
936 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
938 /* Compute the previous frame's stack pointer (which is also the
939 frame's ID's stack address), and this frame's base pointer. */
940 if (cache->fp_offset != INVALID_OFFSET)
942 /* FP is set in prologue, so it can be used to calculate other info. */
943 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
944 prev_sp = this_base + cache->fp_offset;
948 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
949 prev_sp = this_base + cache->sp_offset;
952 cache->prev_sp = prev_sp;
953 cache->base = this_base;
955 /* Adjust all the saved registers such that they contain addresses
956 instead of offsets. */
957 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
958 if (cache->saved_regs[i] != REG_UNAVAIL)
959 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
964 /* Implement the "this_id" frame_unwind method.
966 Our frame ID for a normal frame is the current function's starting
967 PC and the caller's SP when we were called. */
970 nds32_frame_this_id (struct frame_info *this_frame,
971 void **this_cache, struct frame_id *this_id)
973 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
975 /* This marks the outermost frame. */
976 if (cache->prev_sp == 0)
979 *this_id = frame_id_build (cache->prev_sp, cache->pc);
982 /* Implement the "prev_register" frame_unwind method. */
984 static struct value *
985 nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
988 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
990 if (regnum == NDS32_SP_REGNUM)
991 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
993 /* The PC of the previous frame is stored in the LP register of
994 the current frame. */
995 if (regnum == NDS32_PC_REGNUM)
996 regnum = NDS32_LP_REGNUM;
998 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
999 return frame_unwind_got_memory (this_frame, regnum,
1000 cache->saved_regs[regnum]);
1002 return frame_unwind_got_register (this_frame, regnum, regnum);
1005 static const struct frame_unwind nds32_frame_unwind =
1008 default_frame_unwind_stop_reason,
1009 nds32_frame_this_id,
1010 nds32_frame_prev_register,
1012 default_frame_sniffer,
1015 /* Return the frame base address of *THIS_FRAME. */
1018 nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1020 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1025 static const struct frame_base nds32_frame_base =
1027 &nds32_frame_unwind,
1028 nds32_frame_base_address,
1029 nds32_frame_base_address,
1030 nds32_frame_base_address
1033 /* Helper function for instructions used to pop multiple words. */
1036 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1039 CORE_ADDR sp_offset = cache->sp_offset;
1042 /* Skip case where re == rb == sp. */
1043 if ((rb < REG_FP) && (re < REG_FP))
1045 for (i = rb; i <= re; i++)
1047 cache->saved_regs[i] = sp_offset;
1052 /* Check FP, GP, LP in enable4. */
1053 for (i = 3; i >= 1; i--)
1055 if ((enable4 >> i) & 0x1)
1057 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1062 /* For sp, update the offset. */
1063 cache->sp_offset = sp_offset;
1066 /* The instruction sequences in NDS32 epilogue are
1068 INSN_RESET_SP (optional)
1069 (If exists, this must be the first instruction in epilogue
1070 and the stack has not been destroyed.).
1071 INSN_RECOVER (optional).
1072 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1074 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1075 the necessary information will be recorded. */
1078 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1079 struct nds32_frame_cache *cache)
1081 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1082 && N32_IMM15S (insn) > 0)
1083 /* addi $sp, $sp, imm15s */
1084 return INSN_RESET_SP;
1085 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1086 && N32_IMM15S (insn) < 0)
1087 /* addi $sp, $fp, imm15s */
1088 return INSN_RESET_SP;
1089 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1090 && N32_RA5 (insn) == REG_SP)
1092 /* lmw.bim Rb, [$sp], Re, enable4 */
1094 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1095 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1097 return INSN_RECOVER;
1099 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1102 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1103 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1104 /* add $sp, $sp, $ta */
1105 /* add $sp, $ta, $sp */
1106 return INSN_RESET_SP;
1107 else if (abi_use_fpr
1108 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1110 if (__GF (insn, 12, 1) == 0)
1111 /* fldi FDt, [$sp + (imm12s << 2)] */
1112 return INSN_RECOVER;
1115 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1116 int offset = N32_IMM12S (insn) << 2;
1118 if (offset == 8 || offset == 12)
1121 cache->sp_offset += offset;
1123 return INSN_RECOVER;
1131 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1132 the necessary information will be recorded. */
1135 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1137 if (insn == N16_TYPE5 (RET5, REG_LP))
1140 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1143 int imm10s = N16_IMM10S (insn);
1148 cache->sp_offset += imm10s;
1150 return INSN_RECOVER;
1153 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1158 int imm8u = (insn & 0x1f) << 3;
1159 int re = (insn >> 5) & 0x3;
1160 const int reg_map[] = { 6, 8, 10, 14 };
1162 /* Operation 1 -- sp = sp + (imm5u << 3) */
1163 cache->sp_offset += imm8u;
1165 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1166 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1169 /* Operation 3 -- ret $lp */
1170 return INSN_RECOVER_RETURN;
1176 /* Analyze a reasonable amount of instructions from the given PC to find
1177 the instruction used to return to the caller. Return 1 if the 'return'
1178 instruction could be found, 0 otherwise.
1180 If CACHE is non-NULL, fill it in. */
1183 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1184 struct nds32_frame_cache *cache)
1186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1187 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1189 uint32_t insn, insn_len;
1190 int insn_type = INSN_NORMAL;
1197 for (; pc < limit_pc; pc += insn_len)
1199 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1201 if ((insn & 0x80000000) == 0)
1203 /* 32-bit instruction */
1206 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1207 if (insn_type == INSN_RETURN)
1209 else if (insn_type == INSN_RECOVER)
1214 /* 16-bit instruction */
1218 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1219 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1221 else if (insn_type == INSN_RECOVER)
1225 /* Stop the scan if this is an unexpected instruction. */
1232 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1235 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1237 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1238 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1239 int insn_type = INSN_NORMAL;
1243 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1245 if ((insn & 0x80000000) == 0)
1247 /* 32-bit instruction */
1249 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1253 /* 16-bit instruction */
1256 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1259 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1262 /* Search the required 'return' instruction within the following reasonable
1264 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1268 /* Scan backwards to make sure that the last instruction has adjusted
1269 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1270 just a heuristic, so the false positives will be acceptable. */
1271 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1273 /* Only 16-bit instructions are possible at addr - 2. */
1274 if ((insn & 0x80000000) != 0)
1276 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1278 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1279 if (insn_type == INSN_RECOVER)
1283 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1285 /* If this is a 16-bit instruction at addr - 4, then there must be another
1286 16-bit instruction at addr - 2, so only 32-bit instructions need to
1287 be analyzed here. */
1288 if ((insn & 0x80000000) == 0)
1290 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1292 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1293 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1300 /* Implement the "sniffer" frame_unwind method. */
1303 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1304 struct frame_info *this_frame, void **this_cache)
1306 if (frame_relative_level (this_frame) == 0)
1307 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1308 get_frame_pc (this_frame));
1313 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1314 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1315 allocated. Return a pointer to the current nds32_frame_cache in
1318 static struct nds32_frame_cache *
1319 nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1321 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1322 struct nds32_frame_cache *cache;
1323 CORE_ADDR current_pc, current_sp;
1327 return (struct nds32_frame_cache *) *this_cache;
1329 cache = nds32_alloc_frame_cache ();
1330 *this_cache = cache;
1332 cache->pc = get_frame_func (this_frame);
1333 current_pc = get_frame_pc (this_frame);
1334 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1336 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1337 cache->prev_sp = current_sp + cache->sp_offset;
1339 /* Adjust all the saved registers such that they contain addresses
1340 instead of offsets. */
1341 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1342 if (cache->saved_regs[i] != REG_UNAVAIL)
1343 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1348 /* Implement the "this_id" frame_unwind method. */
1351 nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1352 void **this_cache, struct frame_id *this_id)
1354 struct nds32_frame_cache *cache
1355 = nds32_epilogue_frame_cache (this_frame, this_cache);
1357 /* This marks the outermost frame. */
1358 if (cache->prev_sp == 0)
1361 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1364 /* Implement the "prev_register" frame_unwind method. */
1366 static struct value *
1367 nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1368 void **this_cache, int regnum)
1370 struct nds32_frame_cache *cache
1371 = nds32_epilogue_frame_cache (this_frame, this_cache);
1373 if (regnum == NDS32_SP_REGNUM)
1374 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1376 /* The PC of the previous frame is stored in the LP register of
1377 the current frame. */
1378 if (regnum == NDS32_PC_REGNUM)
1379 regnum = NDS32_LP_REGNUM;
1381 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1382 return frame_unwind_got_memory (this_frame, regnum,
1383 cache->saved_regs[regnum]);
1385 return frame_unwind_got_register (this_frame, regnum, regnum);
1388 static const struct frame_unwind nds32_epilogue_frame_unwind =
1391 default_frame_unwind_stop_reason,
1392 nds32_epilogue_frame_this_id,
1393 nds32_epilogue_frame_prev_register,
1395 nds32_epilogue_frame_sniffer
1398 /* Implement the "dummy_id" gdbarch method. */
1400 static struct frame_id
1401 nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1403 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1405 return frame_id_build (sp, get_frame_pc (this_frame));
1408 /* Implement the "unwind_pc" gdbarch method. */
1411 nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1413 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1416 /* Implement the "unwind_sp" gdbarch method. */
1419 nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1421 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1424 /* Floating type and struct type that has only one floating type member
1425 can pass value using FPU registers (when FPU ABI is used). */
1428 nds32_check_calling_use_fpr (struct type *type)
1431 enum type_code typecode;
1436 t = check_typedef (t);
1437 typecode = TYPE_CODE (t);
1438 if (typecode != TYPE_CODE_STRUCT)
1440 else if (TYPE_NFIELDS (t) != 1)
1443 t = TYPE_FIELD_TYPE (t, 0);
1446 return typecode == TYPE_CODE_FLT;
1449 /* Return the alignment (in bytes) of the given type. */
1452 nds32_type_align (struct type *type)
1458 type = check_typedef (type);
1459 switch (TYPE_CODE (type))
1462 /* Should never happen. */
1463 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1467 case TYPE_CODE_ENUM:
1471 case TYPE_CODE_RANGE:
1473 case TYPE_CODE_CHAR:
1474 case TYPE_CODE_BOOL:
1475 return TYPE_LENGTH (type);
1477 case TYPE_CODE_ARRAY:
1478 case TYPE_CODE_COMPLEX:
1479 return nds32_type_align (TYPE_TARGET_TYPE (type));
1481 case TYPE_CODE_STRUCT:
1482 case TYPE_CODE_UNION:
1484 for (n = 0; n < TYPE_NFIELDS (type); n++)
1486 falign = nds32_type_align (TYPE_FIELD_TYPE (type, n));
1494 /* Implement the "push_dummy_call" gdbarch method. */
1497 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1498 struct regcache *regcache, CORE_ADDR bp_addr,
1499 int nargs, struct value **args, CORE_ADDR sp,
1500 int struct_return, CORE_ADDR struct_addr)
1502 const int REND = 6; /* End for register offset. */
1503 int goff = 0; /* Current gpr offset for argument. */
1504 int foff = 0; /* Current fpr offset for argument. */
1505 int soff = 0; /* Current stack offset for argument. */
1508 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1509 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1510 struct type *func_type = value_type (function);
1511 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1512 int abi_split = nds32_abi_split (tdep->elf_abi);
1514 /* Set the return address. For the NDS32, the return breakpoint is
1515 always at BP_ADDR. */
1516 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1518 /* If STRUCT_RETURN is true, then the struct return address (in
1519 STRUCT_ADDR) will consume the first argument-passing register.
1520 Both adjust the register count and store that value. */
1523 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1527 /* Now make sure there's space on the stack */
1528 for (i = 0; i < nargs; i++)
1530 struct type *type = value_type (args[i]);
1531 int align = nds32_type_align (type);
1533 /* If align is zero, it may be an empty struct.
1534 Just ignore the argument of empty struct. */
1538 sp -= TYPE_LENGTH (type);
1539 sp = align_down (sp, align);
1542 /* Stack must be 8-byte aligned. */
1543 sp = align_down (sp, 8);
1546 for (i = 0; i < nargs; i++)
1548 const gdb_byte *val;
1551 int calling_use_fpr;
1554 type = value_type (args[i]);
1555 calling_use_fpr = nds32_check_calling_use_fpr (type);
1556 len = TYPE_LENGTH (type);
1557 align = nds32_type_align (type);
1558 val = value_contents (args[i]);
1560 /* The size of a composite type larger than 4 bytes will be rounded
1561 up to the nearest multiple of 4. */
1563 len = align_up (len, 4);
1565 /* Variadic functions are handled differently between AABI and ABI2FP+.
1567 For AABI, the caller pushes arguments in registers, callee stores
1568 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1569 Therefore, we don't have to handle variadic functions specially.
1571 For ABI2FP+, the caller pushes only named arguments in registers
1572 and pushes all unnamed arguments in stack. */
1574 if (abi_use_fpr && TYPE_VARARGS (func_type)
1575 && i >= TYPE_NFIELDS (func_type))
1578 /* Try to use FPRs to pass arguments only when
1579 1. The program is built using toolchain with FPU support.
1580 2. The type of this argument can use FPR to pass value. */
1581 use_fpr = abi_use_fpr && calling_use_fpr;
1585 if (tdep->fpu_freg == -1)
1588 /* Adjust alignment. */
1589 if ((align >> 2) > 0)
1590 foff = align_up (foff, align >> 2);
1597 regcache_cooked_write (regcache,
1598 tdep->fs0_regnum + foff, val);
1602 regcache_cooked_write (regcache,
1603 NDS32_FD0_REGNUM + (foff >> 1), val);
1608 internal_error (__FILE__, __LINE__,
1609 "Do not know how to handle %d-byte double.\n",
1619 When passing arguments using GPRs,
1621 * A composite type not larger than 4 bytes is passed in $rN.
1622 The format is as if the value is loaded with load instruction
1623 of corresponding size (e.g., LB, LH, LW).
1632 * Otherwise, a composite type is passed in consecutive registers.
1633 The size is rounded up to the nearest multiple of 4.
1634 The successive registers hold the parts of the argument as if
1635 were loaded using lmw instructions.
1641 LITTLE: [d c b a] [x x x e]
1642 BIG: [a b c d] [e x x x]
1645 /* Adjust alignment. */
1646 if ((align >> 2) > 0)
1647 goff = align_up (goff, align >> 2);
1649 if (len <= (REND - goff) * 4)
1651 /* This argument can be passed wholly via GPRs. */
1654 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1656 regcache_cooked_write_unsigned (regcache,
1657 NDS32_R0_REGNUM + goff,
1667 /* Some parts of this argument can be passed via GPRs. */
1670 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1672 regcache_cooked_write_unsigned (regcache,
1673 NDS32_R0_REGNUM + goff,
1684 When pushing (split parts of) an argument into stack,
1686 * A composite type not larger than 4 bytes is copied to different
1688 In little-endian, the first byte of this argument is aligned
1689 at the low address of the next free word.
1690 In big-endian, the last byte of this argument is aligned
1691 at the high address of the next free word.
1702 /* Adjust alignment. */
1703 soff = align_up (soff, align);
1707 int rlen = (len > 4) ? 4 : len;
1709 if (byte_order == BFD_ENDIAN_BIG)
1710 write_memory (sp + soff + 4 - rlen, val, rlen);
1712 write_memory (sp + soff, val, rlen);
1720 /* Finally, update the SP register. */
1721 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1726 /* If use_fpr, but no floating-point register exists,
1727 then it is an error. */
1728 error (_("Fail to call. FPU registers are required."));
1731 /* Read, for architecture GDBARCH, a function return value of TYPE
1732 from REGCACHE, and copy that into VALBUF. */
1735 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1736 struct regcache *regcache, gdb_byte *valbuf)
1738 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1739 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1740 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1741 int calling_use_fpr;
1744 calling_use_fpr = nds32_check_calling_use_fpr (type);
1745 len = TYPE_LENGTH (type);
1747 if (abi_use_fpr && calling_use_fpr)
1750 regcache_cooked_read (regcache, tdep->fs0_regnum, valbuf);
1752 regcache_cooked_read (regcache, NDS32_FD0_REGNUM, valbuf);
1754 internal_error (__FILE__, __LINE__,
1755 _("Cannot extract return value of %d bytes "
1756 "long floating-point."), len);
1761 When returning result,
1763 * A composite type not larger than 4 bytes is returned in $r0.
1764 The format is as if the result is loaded with load instruction
1765 of corresponding size (e.g., LB, LH, LW).
1774 * Otherwise, a composite type not larger than 8 bytes is returned
1776 In little-endian, the first word is loaded in $r0.
1777 In big-endian, the last word is loaded in $r1.
1783 LITTLE: [d c b a] [x x x e]
1784 BIG: [x x x a] [b c d e]
1791 /* By using store_unsigned_integer we avoid having to do
1792 anything special for small big-endian values. */
1793 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1794 store_unsigned_integer (valbuf, len, byte_order, tmp);
1798 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1804 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1807 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1808 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1810 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1811 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1815 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1816 regcache_cooked_read (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1821 /* Write, for architecture GDBARCH, a function return value of TYPE
1822 from VALBUF into REGCACHE. */
1825 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1826 struct regcache *regcache, const gdb_byte *valbuf)
1828 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1829 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1830 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1831 int calling_use_fpr;
1834 calling_use_fpr = nds32_check_calling_use_fpr (type);
1835 len = TYPE_LENGTH (type);
1837 if (abi_use_fpr && calling_use_fpr)
1840 regcache_cooked_write (regcache, tdep->fs0_regnum, valbuf);
1842 regcache_cooked_write (regcache, NDS32_FD0_REGNUM, valbuf);
1844 internal_error (__FILE__, __LINE__,
1845 _("Cannot store return value of %d bytes "
1846 "long floating-point."), len);
1854 regval = extract_unsigned_integer (valbuf, len, byte_order);
1855 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1859 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1865 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1868 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1869 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1871 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1872 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1877 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1878 regcache_cooked_write (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1883 /* Implement the "return_value" gdbarch method.
1885 Determine, for architecture GDBARCH, how a return value of TYPE
1886 should be returned. If it is supposed to be returned in registers,
1887 and READBUF is non-zero, read the appropriate value from REGCACHE,
1888 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1889 from WRITEBUF into REGCACHE. */
1891 static enum return_value_convention
1892 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1893 struct type *type, struct regcache *regcache,
1894 gdb_byte *readbuf, const gdb_byte *writebuf)
1896 if (TYPE_LENGTH (type) > 8)
1898 return RETURN_VALUE_STRUCT_CONVENTION;
1902 if (readbuf != NULL)
1903 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1904 if (writebuf != NULL)
1905 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1907 return RETURN_VALUE_REGISTER_CONVENTION;
1911 /* Implement the "get_longjmp_target" gdbarch method. */
1914 nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1918 struct gdbarch *gdbarch = get_frame_arch (frame);
1919 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1921 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1923 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1926 *pc = extract_unsigned_integer (buf, 4, byte_order);
1930 /* Validate the given TDESC, and fixed-number some registers in it.
1931 Return 0 if the given TDESC does not contain the required feature
1932 or not contain required registers. */
1935 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1936 struct tdesc_arch_data *tdesc_data,
1937 int *fpu_freg, int *use_pseudo_fsrs)
1939 const struct tdesc_feature *feature;
1942 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1943 if (feature == NULL)
1947 /* Validate and fixed-number R0-R10. */
1948 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1949 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1950 nds32_register_names[i]);
1953 valid_p &= tdesc_unnumbered_register (feature,
1954 nds32_register_names[NDS32_TA_REGNUM]);
1956 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1957 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1958 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1959 nds32_register_names[i]);
1964 /* Fixed-number R11-R27. */
1965 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1966 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1968 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1969 if (feature != NULL)
1971 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1974 /* Guess FPU configuration via listed registers. */
1975 if (tdesc_unnumbered_register (feature, "fd31"))
1977 else if (tdesc_unnumbered_register (feature, "fd15"))
1979 else if (tdesc_unnumbered_register (feature, "fd7"))
1981 else if (tdesc_unnumbered_register (feature, "fd3"))
1985 /* Required FDR is not found. */
1990 /* Validate and fixed-number required FDRs. */
1991 num_fdr_regs = num_fdr_map[freg];
1992 for (i = 0; i < num_fdr_regs; i++)
1993 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1994 NDS32_FD0_REGNUM + i,
1995 nds32_fdr_register_names[i]);
1999 /* Count the number of listed FSRs, and fixed-number them if present. */
2000 num_fsr_regs = num_fsr_map[freg];
2001 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
2003 for (i = 0; i < num_fsr_regs; i++)
2004 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
2006 nds32_fsr_register_names[i]);
2008 if (num_listed_fsr == 0)
2009 /* No required FSRs are listed explicitly, make them pseudo registers
2011 *use_pseudo_fsrs = 1;
2012 else if (num_listed_fsr == num_fsr_regs)
2013 /* All required FSRs are listed explicitly. */
2014 *use_pseudo_fsrs = 0;
2016 /* Some required FSRs are missing. */
2023 /* Initialize the current architecture based on INFO. If possible,
2024 re-use an architecture from ARCHES, which is a list of
2025 architectures already created during this debugging session.
2027 Called e.g. at program startup, when reading a core file, and when
2028 reading a binary file. */
2030 static struct gdbarch *
2031 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2033 struct gdbarch *gdbarch;
2034 struct gdbarch_tdep *tdep;
2035 struct gdbarch_list *best_arch;
2036 struct tdesc_arch_data *tdesc_data = NULL;
2037 const struct target_desc *tdesc = info.target_desc;
2038 int elf_abi = E_NDS_ABI_AABI;
2040 int use_pseudo_fsrs = 0;
2041 int i, num_regs, maxregs;
2043 /* Extract the elf_flags if available. */
2044 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2045 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
2047 /* If there is already a candidate, use it. */
2048 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2050 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2052 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2054 if (idep->elf_abi != elf_abi)
2057 /* Found a match. */
2061 if (best_arch != NULL)
2062 return best_arch->gdbarch;
2064 if (!tdesc_has_registers (tdesc))
2065 tdesc = tdesc_nds32;
2067 tdesc_data = tdesc_data_alloc ();
2069 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2071 tdesc_data_cleanup (tdesc_data);
2075 /* Allocate space for the new architecture. */
2076 tdep = XCNEW (struct gdbarch_tdep);
2077 tdep->fpu_freg = fpu_freg;
2078 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2079 tdep->fs0_regnum = -1;
2080 tdep->elf_abi = elf_abi;
2082 gdbarch = gdbarch_alloc (&info, tdep);
2085 num_regs = NDS32_NUM_REGS;
2086 else if (use_pseudo_fsrs == 1)
2088 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2089 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2090 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2091 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2092 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2094 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2097 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2099 set_gdbarch_num_regs (gdbarch, num_regs);
2100 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2102 /* Cache the register number of fs0. */
2104 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2106 /* Add NDS32 register aliases. To avoid search in user register name space,
2107 user_reg_map_name_to_regnum is not used. */
2108 maxregs = (gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch));
2109 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2114 /* Search register name space. */
2115 for (j = 0; j < maxregs; j++)
2117 const char *regname = gdbarch_register_name (gdbarch, j);
2120 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2127 /* Try next alias entry if the given name can not be found in register
2132 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2133 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2136 nds32_add_reggroups (gdbarch);
2138 /* Hook in ABI-specific overrides, if they have been registered. */
2139 info.tdep_info = (void *) tdesc_data;
2140 gdbarch_init_osabi (info, gdbarch);
2142 /* Override tdesc_register callbacks for system registers. */
2143 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2145 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2146 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2147 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2148 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2149 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2150 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2152 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2153 set_gdbarch_return_value (gdbarch, nds32_return_value);
2154 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2156 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2157 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2158 set_gdbarch_breakpoint_from_pc (gdbarch, nds32_breakpoint_from_pc);
2160 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2161 frame_base_set_default (gdbarch, &nds32_frame_base);
2163 set_gdbarch_print_insn (gdbarch, print_insn_nds32);
2165 /* Handle longjmp. */
2166 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2168 /* The order of appending is the order it check frame. */
2169 dwarf2_append_unwinders (gdbarch);
2170 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2171 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2177 _initialize_nds32_tdep (void)
2179 /* Initialize gdbarch. */
2180 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2182 initialize_tdesc_nds32 ();
2183 nds32_init_reggroups ();