1 /* Target-dependent code for the NDS32 architecture, for GDB.
3 Copyright (C) 2013-2017 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
29 #include "reggroups.h"
32 #include "arch-utils.h"
35 #include "user-regs.h"
37 #include "dwarf2-frame.h"
39 #include "target-descriptions.h"
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
46 #include "features/nds32.c"
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
58 extern void _initialize_nds32_tdep (void);
60 /* Use an invalid address value as 'not available' marker. */
61 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
63 /* Use an impossible value as invalid offset. */
64 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
66 /* Instruction groups for NDS32 epilogue analysis. */
69 /* Instructions used everywhere, not only in epilogue. */
71 /* Instructions used to reset sp for local vars, arguments, etc. */
73 /* Instructions used to recover saved regs and to recover padding. */
75 /* Instructions used to return to the caller. */
77 /* Instructions used to recover saved regs and to return to the caller. */
81 static const char *const nds32_register_names[] =
84 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
85 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
86 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
87 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
92 static const char *const nds32_fdr_register_names[] =
94 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
95 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
96 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
97 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
100 static const char *const nds32_fsr_register_names[] =
102 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
103 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
104 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
105 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
108 /* The number of registers for four FPU configuration options. */
109 const int num_fdr_map[] = { 4, 8, 16, 32 };
110 const int num_fsr_map[] = { 8, 16, 32, 32 };
112 /* Aliases for registers. */
117 } nds32_register_aliases[] =
133 {"cr6", "fucop_exist"},
150 {"ir14", "int_mask"},
151 {"ir15", "int_pend"},
155 {"ir19", "int_ctrl"},
157 {"ir21", "sp_priv1"},
159 {"ir23", "sp_priv2"},
161 {"ir25", "sp_priv3"},
162 {"ir26", "int_mask2"},
163 {"ir27", "int_pend2"},
164 {"ir28", "int_pri2"},
165 {"ir29", "int_trigger"},
175 {"mr8", "cache_ctl"},
176 {"mr9", "hsmp_saddr"},
177 {"mr10", "hsmp_eaddr"},
178 {"mr11", "bg_region"},
229 {"hspr0", "hsp_ctl"},
230 {"hspr1", "sp_bound"},
231 {"hspr2", "sp_bound_priv"},
239 {"dmar0", "dma_cfg"},
240 {"dmar1", "dma_gcsw"},
241 {"dmar2", "dma_chnsel"},
242 {"dmar3", "dma_act"},
243 {"dmar4", "dma_setup"},
244 {"dmar5", "dma_isaddr"},
245 {"dmar6", "dma_esaddr"},
246 {"dmar7", "dma_tcnt"},
247 {"dmar8", "dma_status"},
248 {"dmar9", "dma_2dset"},
249 {"dmar10", "dma_2dsctl"},
250 {"dmar11", "dma_rcnt"},
251 {"dmar12", "dma_hstatus"},
253 {"racr0", "prusr_acc_ctl"},
254 {"fucpr", "fucop_ctl"},
257 {"idr1", "misc_ctl"},
258 {"idr2", "ecc_misc"},
263 {"secur3", "p_isign"},
266 /* Value of a register alias. BATON is the regnum of the corresponding
269 static struct value *
270 value_of_nds32_reg (struct frame_info *frame, const void *baton)
272 return value_of_register ((int) (intptr_t) baton, frame);
275 /* Implement the "frame_align" gdbarch method. */
278 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
280 /* 8-byte aligned. */
281 return align_down (sp, 8);
284 /* The same insn machine code is used for little-endian and big-endian. */
285 constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
287 typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
289 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
292 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
294 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
296 const int FDR = FSR + 32;
298 if (num >= 0 && num < 32)
300 /* General-purpose registers (R0 - R31). */
303 else if (num >= FSR && num < FSR + 32)
305 /* Single precision floating-point registers (FS0 - FS31). */
306 return num - FSR + tdep->fs0_regnum;
308 else if (num >= FDR && num < FDR + 32)
310 /* Double precision floating-point registers (FD0 - FD31). */
311 return num - FDR + NDS32_FD0_REGNUM;
314 /* No match, return a inaccessible register number. */
318 /* NDS32 register groups. */
319 static struct reggroup *nds32_cr_reggroup;
320 static struct reggroup *nds32_ir_reggroup;
321 static struct reggroup *nds32_mr_reggroup;
322 static struct reggroup *nds32_dr_reggroup;
323 static struct reggroup *nds32_pfr_reggroup;
324 static struct reggroup *nds32_hspr_reggroup;
325 static struct reggroup *nds32_dmar_reggroup;
326 static struct reggroup *nds32_racr_reggroup;
327 static struct reggroup *nds32_idr_reggroup;
328 static struct reggroup *nds32_secur_reggroup;
331 nds32_init_reggroups (void)
333 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
334 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
335 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
336 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
337 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
338 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
339 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
340 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
341 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
342 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
346 nds32_add_reggroups (struct gdbarch *gdbarch)
348 /* Add pre-defined register groups. */
349 reggroup_add (gdbarch, general_reggroup);
350 reggroup_add (gdbarch, float_reggroup);
351 reggroup_add (gdbarch, system_reggroup);
352 reggroup_add (gdbarch, all_reggroup);
353 reggroup_add (gdbarch, save_reggroup);
354 reggroup_add (gdbarch, restore_reggroup);
356 /* Add NDS32 register groups. */
357 reggroup_add (gdbarch, nds32_cr_reggroup);
358 reggroup_add (gdbarch, nds32_ir_reggroup);
359 reggroup_add (gdbarch, nds32_mr_reggroup);
360 reggroup_add (gdbarch, nds32_dr_reggroup);
361 reggroup_add (gdbarch, nds32_pfr_reggroup);
362 reggroup_add (gdbarch, nds32_hspr_reggroup);
363 reggroup_add (gdbarch, nds32_dmar_reggroup);
364 reggroup_add (gdbarch, nds32_racr_reggroup);
365 reggroup_add (gdbarch, nds32_idr_reggroup);
366 reggroup_add (gdbarch, nds32_secur_reggroup);
369 /* Implement the "register_reggroup_p" gdbarch method. */
372 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
373 struct reggroup *reggroup)
375 const char *reg_name;
376 const char *group_name;
379 if (reggroup == all_reggroup)
382 /* General reggroup contains only GPRs and PC. */
383 if (reggroup == general_reggroup)
384 return regnum <= NDS32_PC_REGNUM;
386 if (reggroup == float_reggroup || reggroup == save_reggroup
387 || reggroup == restore_reggroup)
389 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
393 return default_register_reggroup_p (gdbarch, regnum, reggroup);
396 if (reggroup == system_reggroup)
397 return (regnum > NDS32_PC_REGNUM)
398 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
400 /* The NDS32 reggroup contains registers whose name is prefixed
402 reg_name = gdbarch_register_name (gdbarch, regnum);
403 group_name = reggroup_name (reggroup);
404 return !strncmp (reg_name, group_name, strlen (group_name));
407 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
410 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
412 regnum -= gdbarch_num_regs (gdbarch);
414 /* Currently, only FSRs could be defined as pseudo registers. */
415 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
416 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
417 floatformats_ieee_single);
419 warning (_("Unknown nds32 pseudo register %d."), regnum);
423 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
426 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
428 regnum -= gdbarch_num_regs (gdbarch);
430 /* Currently, only FSRs could be defined as pseudo registers. */
431 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
432 return nds32_fsr_register_names[regnum];
434 warning (_("Unknown nds32 pseudo register %d."), regnum);
438 /* Implement the "pseudo_register_read" gdbarch method. */
440 static enum register_status
441 nds32_pseudo_register_read (struct gdbarch *gdbarch,
442 struct regcache *regcache, int regnum,
445 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
447 int offset, fdr_regnum;
448 enum register_status status;
450 /* This function is registered in nds32_gdbarch_init only after these are
452 gdb_assert (tdep->fpu_freg != -1);
453 gdb_assert (tdep->use_pseudo_fsrs != 0);
455 regnum -= gdbarch_num_regs (gdbarch);
457 /* Currently, only FSRs could be defined as pseudo registers. */
458 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
460 /* fs0 is always the most significant half of fd0. */
461 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
462 offset = (regnum & 1) ? 4 : 0;
464 offset = (regnum & 1) ? 0 : 4;
466 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
467 status = regcache_raw_read (regcache, fdr_regnum, reg_buf);
468 if (status == REG_VALID)
469 memcpy (buf, reg_buf + offset, 4);
474 gdb_assert_not_reached ("invalid pseudo register number");
477 /* Implement the "pseudo_register_write" gdbarch method. */
480 nds32_pseudo_register_write (struct gdbarch *gdbarch,
481 struct regcache *regcache, int regnum,
484 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
486 int offset, fdr_regnum;
488 /* This function is registered in nds32_gdbarch_init only after these are
490 gdb_assert (tdep->fpu_freg != -1);
491 gdb_assert (tdep->use_pseudo_fsrs != 0);
493 regnum -= gdbarch_num_regs (gdbarch);
495 /* Currently, only FSRs could be defined as pseudo registers. */
496 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
498 /* fs0 is always the most significant half of fd0. */
499 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
500 offset = (regnum & 1) ? 4 : 0;
502 offset = (regnum & 1) ? 0 : 4;
504 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
505 regcache_raw_read (regcache, fdr_regnum, reg_buf);
506 memcpy (reg_buf + offset, buf, 4);
507 regcache_raw_write (regcache, fdr_regnum, reg_buf);
511 gdb_assert_not_reached ("invalid pseudo register number");
514 /* Helper function for NDS32 ABI. Return true if FPRs can be used
515 to pass function arguments and return value. */
518 nds32_abi_use_fpr (int elf_abi)
520 return elf_abi == E_NDS_ABI_V2FP_PLUS;
523 /* Helper function for NDS32 ABI. Return true if GPRs and stack
524 can be used together to pass an argument. */
527 nds32_abi_split (int elf_abi)
529 return elf_abi == E_NDS_ABI_AABI;
532 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
534 struct nds32_frame_cache
536 /* The previous frame's inner most stack address. Used as this
537 frame ID's stack_addr. */
540 /* The frame's base, optionally used by the high-level debug info. */
543 /* During prologue analysis, keep how far the SP and FP have been offset
544 from the start of the stack frame (as defined by the previous frame's
546 During epilogue analysis, keep how far the SP has been offset from the
547 current stack pointer. */
551 /* The address of the first instruction in this function. */
554 /* Saved registers. */
555 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
558 /* Allocate and initialize a frame cache. */
560 static struct nds32_frame_cache *
561 nds32_alloc_frame_cache (void)
563 struct nds32_frame_cache *cache;
566 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
568 /* Initialize fp_offset to check if FP is set in prologue. */
569 cache->fp_offset = INVALID_OFFSET;
571 /* Saved registers. We initialize these to -1 since zero is a valid
573 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
574 cache->saved_regs[i] = REG_UNAVAIL;
579 /* Helper function for instructions used to push multiple words. */
582 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
585 CORE_ADDR sp_offset = cache->sp_offset;
588 /* Check LP, GP, FP in enable4. */
589 for (i = 1; i <= 3; i++)
591 if ((enable4 >> i) & 0x1)
594 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
598 /* Skip case where re == rb == sp. */
599 if ((rb < REG_FP) && (re < REG_FP))
601 for (i = re; i >= rb; i--)
604 cache->saved_regs[i] = sp_offset;
608 /* For sp, update the offset. */
609 cache->sp_offset = sp_offset;
612 /* Analyze the instructions within the given address range. If CACHE
613 is non-NULL, fill it in. Return the first address beyond the given
614 address range. If CACHE is NULL, return the first address not
615 recognized as a prologue instruction. */
618 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
619 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
621 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
622 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
623 /* Current scanning status. */
624 int in_prologue_bb = 0;
626 uint32_t insn, insn_len;
628 for (; pc < limit_pc; pc += insn_len)
630 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
632 if ((insn & 0x80000000) == 0)
634 /* 32-bit instruction */
637 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
639 /* addi $sp, $sp, imm15s */
640 int imm15s = N32_IMM15S (insn);
645 cache->sp_offset += -imm15s;
651 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
653 /* addi $fp, $sp, imm15s */
654 int imm15s = N32_IMM15S (insn);
659 cache->fp_offset = cache->sp_offset - imm15s;
665 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
666 && N32_RA5 (insn) == REG_SP)
668 /* smw.adm Rb, [$sp], Re, enable4 */
670 nds32_push_multiple_words (cache, N32_RT5 (insn),
672 N32_LSMW_ENABLE4 (insn));
676 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
677 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
679 /* add $sp, $sp, $ta */
680 /* add $sp, $ta, $sp */
684 cache->sp_offset += -val_ta;
690 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
692 /* movi $ta, imm20s */
694 val_ta = N32_IMM20S (insn);
698 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
700 /* sethi $ta, imm20u */
702 val_ta = N32_IMM20U (insn) << 12;
706 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
708 /* ori $ta, $ta, imm15u */
710 val_ta |= N32_IMM15U (insn);
714 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
716 /* addi $ta, $ta, imm15s */
718 val_ta += N32_IMM15S (insn);
722 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
723 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
725 /* add $gp, $ta, $gp */
726 /* add $gp, $gp, $ta */
730 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
732 /* movi $gp, imm20s */
736 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
738 /* sethi $gp, imm20u */
742 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
744 /* ori $gp, $gp, imm15u */
750 /* Jump/Branch insns never appear in prologue basic block.
751 The loop can be escaped early when these insns are met. */
752 if (in_prologue_bb == 1)
754 int op = N32_OP6 (insn);
757 || op == N32_OP6_JREG
760 || op == N32_OP6_BR3)
765 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
766 && __GF (insn, 12, 3) == 0)
768 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
769 normal form (bit [12] == 0) is used. */
771 /* fsdi FDt, [$sp + (imm12s << 2)] */
772 if (N32_RA5 (insn) == REG_SP)
776 /* The optimizer might shove anything into the prologue, if
777 we build up cache (cache != NULL) from analyzing prologue,
778 we just skip what we don't recognize and analyze further to
779 make cache as complete as possible. However, if we skip
780 prologue, we'll stop immediately on unrecognized
787 /* 16-bit instruction */
792 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
795 int imm10s = N16_IMM10S (insn);
800 cache->sp_offset += -imm10s;
806 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
811 int imm8u = (insn & 0x1f) << 3;
812 int re = (insn >> 5) & 0x3;
813 const int reg_map[] = { 6, 8, 10, 14 };
815 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
816 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
818 /* Operation 2 -- sp = sp - (imm5u << 3) */
819 cache->sp_offset += imm8u;
825 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
831 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
833 /* movi55 $gp, imm5s */
839 /* Jump/Branch insns never appear in prologue basic block.
840 The loop can be escaped early when these insns are met. */
841 if (in_prologue_bb == 1)
843 uint32_t insn5 = CHOP_BITS (insn, 5);
844 uint32_t insn8 = CHOP_BITS (insn, 8);
845 uint32_t insn38 = CHOP_BITS (insn, 11);
847 if (insn5 == N16_TYPE5 (JR5, 0)
848 || insn5 == N16_TYPE5 (JRAL5, 0)
849 || insn5 == N16_TYPE5 (RET5, 0)
850 || insn8 == N16_TYPE8 (J8, 0)
851 || insn8 == N16_TYPE8 (BEQZS8, 0)
852 || insn8 == N16_TYPE8 (BNEZS8, 0)
853 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
854 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
855 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
856 || insn38 == N16_TYPE38 (BNES38, 0, 0))
861 /* The optimizer might shove anything into the prologue, if
862 we build up cache (cache != NULL) from analyzing prologue,
863 we just skip what we don't recognize and analyze further to
864 make cache as complete as possible. However, if we skip
865 prologue, we'll stop immediately on unrecognized
875 /* Implement the "skip_prologue" gdbarch method.
877 Find the end of function prologue. */
880 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
882 CORE_ADDR func_addr, limit_pc;
884 /* See if we can determine the end of the prologue via the symbol table.
885 If so, then return either PC, or the PC after the prologue, whichever
887 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
889 CORE_ADDR post_prologue_pc
890 = skip_prologue_using_sal (gdbarch, func_addr);
891 if (post_prologue_pc != 0)
892 return std::max (pc, post_prologue_pc);
895 /* Can't determine prologue from the symbol table, need to examine
898 /* Find an upper limit on the function prologue using the debug
899 information. If the debug information could not be used to provide
900 that bound, then use an arbitrary large number as the upper bound. */
901 limit_pc = skip_prologue_using_sal (gdbarch, pc);
903 limit_pc = pc + 128; /* Magic. */
905 /* Find the end of prologue. */
906 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
909 /* Allocate and fill in *THIS_CACHE with information about the prologue of
910 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
911 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
913 static struct nds32_frame_cache *
914 nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
916 struct gdbarch *gdbarch = get_frame_arch (this_frame);
917 struct nds32_frame_cache *cache;
918 CORE_ADDR current_pc;
924 return (struct nds32_frame_cache *) *this_cache;
926 cache = nds32_alloc_frame_cache ();
929 cache->pc = get_frame_func (this_frame);
930 current_pc = get_frame_pc (this_frame);
931 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
933 /* Compute the previous frame's stack pointer (which is also the
934 frame's ID's stack address), and this frame's base pointer. */
935 if (cache->fp_offset != INVALID_OFFSET)
937 /* FP is set in prologue, so it can be used to calculate other info. */
938 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
939 prev_sp = this_base + cache->fp_offset;
943 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
944 prev_sp = this_base + cache->sp_offset;
947 cache->prev_sp = prev_sp;
948 cache->base = this_base;
950 /* Adjust all the saved registers such that they contain addresses
951 instead of offsets. */
952 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
953 if (cache->saved_regs[i] != REG_UNAVAIL)
954 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
959 /* Implement the "this_id" frame_unwind method.
961 Our frame ID for a normal frame is the current function's starting
962 PC and the caller's SP when we were called. */
965 nds32_frame_this_id (struct frame_info *this_frame,
966 void **this_cache, struct frame_id *this_id)
968 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
970 /* This marks the outermost frame. */
971 if (cache->prev_sp == 0)
974 *this_id = frame_id_build (cache->prev_sp, cache->pc);
977 /* Implement the "prev_register" frame_unwind method. */
979 static struct value *
980 nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
983 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
985 if (regnum == NDS32_SP_REGNUM)
986 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
988 /* The PC of the previous frame is stored in the LP register of
989 the current frame. */
990 if (regnum == NDS32_PC_REGNUM)
991 regnum = NDS32_LP_REGNUM;
993 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
994 return frame_unwind_got_memory (this_frame, regnum,
995 cache->saved_regs[regnum]);
997 return frame_unwind_got_register (this_frame, regnum, regnum);
1000 static const struct frame_unwind nds32_frame_unwind =
1003 default_frame_unwind_stop_reason,
1004 nds32_frame_this_id,
1005 nds32_frame_prev_register,
1007 default_frame_sniffer,
1010 /* Return the frame base address of *THIS_FRAME. */
1013 nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1015 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1020 static const struct frame_base nds32_frame_base =
1022 &nds32_frame_unwind,
1023 nds32_frame_base_address,
1024 nds32_frame_base_address,
1025 nds32_frame_base_address
1028 /* Helper function for instructions used to pop multiple words. */
1031 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1034 CORE_ADDR sp_offset = cache->sp_offset;
1037 /* Skip case where re == rb == sp. */
1038 if ((rb < REG_FP) && (re < REG_FP))
1040 for (i = rb; i <= re; i++)
1042 cache->saved_regs[i] = sp_offset;
1047 /* Check FP, GP, LP in enable4. */
1048 for (i = 3; i >= 1; i--)
1050 if ((enable4 >> i) & 0x1)
1052 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1057 /* For sp, update the offset. */
1058 cache->sp_offset = sp_offset;
1061 /* The instruction sequences in NDS32 epilogue are
1063 INSN_RESET_SP (optional)
1064 (If exists, this must be the first instruction in epilogue
1065 and the stack has not been destroyed.).
1066 INSN_RECOVER (optional).
1067 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1069 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1070 the necessary information will be recorded. */
1073 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1074 struct nds32_frame_cache *cache)
1076 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1077 && N32_IMM15S (insn) > 0)
1078 /* addi $sp, $sp, imm15s */
1079 return INSN_RESET_SP;
1080 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1081 && N32_IMM15S (insn) < 0)
1082 /* addi $sp, $fp, imm15s */
1083 return INSN_RESET_SP;
1084 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1085 && N32_RA5 (insn) == REG_SP)
1087 /* lmw.bim Rb, [$sp], Re, enable4 */
1089 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1090 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1092 return INSN_RECOVER;
1094 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1097 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1098 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1099 /* add $sp, $sp, $ta */
1100 /* add $sp, $ta, $sp */
1101 return INSN_RESET_SP;
1102 else if (abi_use_fpr
1103 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1105 if (__GF (insn, 12, 1) == 0)
1106 /* fldi FDt, [$sp + (imm12s << 2)] */
1107 return INSN_RECOVER;
1110 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1111 int offset = N32_IMM12S (insn) << 2;
1113 if (offset == 8 || offset == 12)
1116 cache->sp_offset += offset;
1118 return INSN_RECOVER;
1126 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1127 the necessary information will be recorded. */
1130 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1132 if (insn == N16_TYPE5 (RET5, REG_LP))
1135 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1138 int imm10s = N16_IMM10S (insn);
1143 cache->sp_offset += imm10s;
1145 return INSN_RECOVER;
1148 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1153 int imm8u = (insn & 0x1f) << 3;
1154 int re = (insn >> 5) & 0x3;
1155 const int reg_map[] = { 6, 8, 10, 14 };
1157 /* Operation 1 -- sp = sp + (imm5u << 3) */
1158 cache->sp_offset += imm8u;
1160 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1161 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1164 /* Operation 3 -- ret $lp */
1165 return INSN_RECOVER_RETURN;
1171 /* Analyze a reasonable amount of instructions from the given PC to find
1172 the instruction used to return to the caller. Return 1 if the 'return'
1173 instruction could be found, 0 otherwise.
1175 If CACHE is non-NULL, fill it in. */
1178 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1179 struct nds32_frame_cache *cache)
1181 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1182 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1184 uint32_t insn, insn_len;
1185 int insn_type = INSN_NORMAL;
1192 for (; pc < limit_pc; pc += insn_len)
1194 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1196 if ((insn & 0x80000000) == 0)
1198 /* 32-bit instruction */
1201 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1202 if (insn_type == INSN_RETURN)
1204 else if (insn_type == INSN_RECOVER)
1209 /* 16-bit instruction */
1213 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1214 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1216 else if (insn_type == INSN_RECOVER)
1220 /* Stop the scan if this is an unexpected instruction. */
1227 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1230 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1233 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1234 int insn_type = INSN_NORMAL;
1238 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1240 if ((insn & 0x80000000) == 0)
1242 /* 32-bit instruction */
1244 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1248 /* 16-bit instruction */
1251 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1254 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1257 /* Search the required 'return' instruction within the following reasonable
1259 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1263 /* Scan backwards to make sure that the last instruction has adjusted
1264 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1265 just a heuristic, so the false positives will be acceptable. */
1266 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1268 /* Only 16-bit instructions are possible at addr - 2. */
1269 if ((insn & 0x80000000) != 0)
1271 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1273 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1274 if (insn_type == INSN_RECOVER)
1278 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1280 /* If this is a 16-bit instruction at addr - 4, then there must be another
1281 16-bit instruction at addr - 2, so only 32-bit instructions need to
1282 be analyzed here. */
1283 if ((insn & 0x80000000) == 0)
1285 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1287 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1288 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1295 /* Implement the "sniffer" frame_unwind method. */
1298 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1299 struct frame_info *this_frame, void **this_cache)
1301 if (frame_relative_level (this_frame) == 0)
1302 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1303 get_frame_pc (this_frame));
1308 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1309 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1310 allocated. Return a pointer to the current nds32_frame_cache in
1313 static struct nds32_frame_cache *
1314 nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1316 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1317 struct nds32_frame_cache *cache;
1318 CORE_ADDR current_pc, current_sp;
1322 return (struct nds32_frame_cache *) *this_cache;
1324 cache = nds32_alloc_frame_cache ();
1325 *this_cache = cache;
1327 cache->pc = get_frame_func (this_frame);
1328 current_pc = get_frame_pc (this_frame);
1329 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1331 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1332 cache->prev_sp = current_sp + cache->sp_offset;
1334 /* Adjust all the saved registers such that they contain addresses
1335 instead of offsets. */
1336 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1337 if (cache->saved_regs[i] != REG_UNAVAIL)
1338 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1343 /* Implement the "this_id" frame_unwind method. */
1346 nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1347 void **this_cache, struct frame_id *this_id)
1349 struct nds32_frame_cache *cache
1350 = nds32_epilogue_frame_cache (this_frame, this_cache);
1352 /* This marks the outermost frame. */
1353 if (cache->prev_sp == 0)
1356 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1359 /* Implement the "prev_register" frame_unwind method. */
1361 static struct value *
1362 nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1363 void **this_cache, int regnum)
1365 struct nds32_frame_cache *cache
1366 = nds32_epilogue_frame_cache (this_frame, this_cache);
1368 if (regnum == NDS32_SP_REGNUM)
1369 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1371 /* The PC of the previous frame is stored in the LP register of
1372 the current frame. */
1373 if (regnum == NDS32_PC_REGNUM)
1374 regnum = NDS32_LP_REGNUM;
1376 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1377 return frame_unwind_got_memory (this_frame, regnum,
1378 cache->saved_regs[regnum]);
1380 return frame_unwind_got_register (this_frame, regnum, regnum);
1383 static const struct frame_unwind nds32_epilogue_frame_unwind =
1386 default_frame_unwind_stop_reason,
1387 nds32_epilogue_frame_this_id,
1388 nds32_epilogue_frame_prev_register,
1390 nds32_epilogue_frame_sniffer
1393 /* Implement the "dummy_id" gdbarch method. */
1395 static struct frame_id
1396 nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1398 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1400 return frame_id_build (sp, get_frame_pc (this_frame));
1403 /* Implement the "unwind_pc" gdbarch method. */
1406 nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1408 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1411 /* Implement the "unwind_sp" gdbarch method. */
1414 nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1416 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1419 /* Floating type and struct type that has only one floating type member
1420 can pass value using FPU registers (when FPU ABI is used). */
1423 nds32_check_calling_use_fpr (struct type *type)
1426 enum type_code typecode;
1431 t = check_typedef (t);
1432 typecode = TYPE_CODE (t);
1433 if (typecode != TYPE_CODE_STRUCT)
1435 else if (TYPE_NFIELDS (t) != 1)
1438 t = TYPE_FIELD_TYPE (t, 0);
1441 return typecode == TYPE_CODE_FLT;
1444 /* Return the alignment (in bytes) of the given type. */
1447 nds32_type_align (struct type *type)
1453 type = check_typedef (type);
1454 switch (TYPE_CODE (type))
1457 /* Should never happen. */
1458 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1462 case TYPE_CODE_ENUM:
1466 case TYPE_CODE_RANGE:
1468 case TYPE_CODE_CHAR:
1469 case TYPE_CODE_BOOL:
1470 return TYPE_LENGTH (type);
1472 case TYPE_CODE_ARRAY:
1473 case TYPE_CODE_COMPLEX:
1474 return nds32_type_align (TYPE_TARGET_TYPE (type));
1476 case TYPE_CODE_STRUCT:
1477 case TYPE_CODE_UNION:
1479 for (n = 0; n < TYPE_NFIELDS (type); n++)
1481 falign = nds32_type_align (TYPE_FIELD_TYPE (type, n));
1489 /* Implement the "push_dummy_call" gdbarch method. */
1492 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1493 struct regcache *regcache, CORE_ADDR bp_addr,
1494 int nargs, struct value **args, CORE_ADDR sp,
1495 int struct_return, CORE_ADDR struct_addr)
1497 const int REND = 6; /* End for register offset. */
1498 int goff = 0; /* Current gpr offset for argument. */
1499 int foff = 0; /* Current fpr offset for argument. */
1500 int soff = 0; /* Current stack offset for argument. */
1503 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1504 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1505 struct type *func_type = value_type (function);
1506 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1507 int abi_split = nds32_abi_split (tdep->elf_abi);
1509 /* Set the return address. For the NDS32, the return breakpoint is
1510 always at BP_ADDR. */
1511 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1513 /* If STRUCT_RETURN is true, then the struct return address (in
1514 STRUCT_ADDR) will consume the first argument-passing register.
1515 Both adjust the register count and store that value. */
1518 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1522 /* Now make sure there's space on the stack */
1523 for (i = 0; i < nargs; i++)
1525 struct type *type = value_type (args[i]);
1526 int align = nds32_type_align (type);
1528 /* If align is zero, it may be an empty struct.
1529 Just ignore the argument of empty struct. */
1533 sp -= TYPE_LENGTH (type);
1534 sp = align_down (sp, align);
1537 /* Stack must be 8-byte aligned. */
1538 sp = align_down (sp, 8);
1541 for (i = 0; i < nargs; i++)
1543 const gdb_byte *val;
1546 int calling_use_fpr;
1549 type = value_type (args[i]);
1550 calling_use_fpr = nds32_check_calling_use_fpr (type);
1551 len = TYPE_LENGTH (type);
1552 align = nds32_type_align (type);
1553 val = value_contents (args[i]);
1555 /* The size of a composite type larger than 4 bytes will be rounded
1556 up to the nearest multiple of 4. */
1558 len = align_up (len, 4);
1560 /* Variadic functions are handled differently between AABI and ABI2FP+.
1562 For AABI, the caller pushes arguments in registers, callee stores
1563 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1564 Therefore, we don't have to handle variadic functions specially.
1566 For ABI2FP+, the caller pushes only named arguments in registers
1567 and pushes all unnamed arguments in stack. */
1569 if (abi_use_fpr && TYPE_VARARGS (func_type)
1570 && i >= TYPE_NFIELDS (func_type))
1573 /* Try to use FPRs to pass arguments only when
1574 1. The program is built using toolchain with FPU support.
1575 2. The type of this argument can use FPR to pass value. */
1576 use_fpr = abi_use_fpr && calling_use_fpr;
1580 if (tdep->fpu_freg == -1)
1583 /* Adjust alignment. */
1584 if ((align >> 2) > 0)
1585 foff = align_up (foff, align >> 2);
1592 regcache_cooked_write (regcache,
1593 tdep->fs0_regnum + foff, val);
1597 regcache_cooked_write (regcache,
1598 NDS32_FD0_REGNUM + (foff >> 1), val);
1603 internal_error (__FILE__, __LINE__,
1604 "Do not know how to handle %d-byte double.\n",
1614 When passing arguments using GPRs,
1616 * A composite type not larger than 4 bytes is passed in $rN.
1617 The format is as if the value is loaded with load instruction
1618 of corresponding size (e.g., LB, LH, LW).
1627 * Otherwise, a composite type is passed in consecutive registers.
1628 The size is rounded up to the nearest multiple of 4.
1629 The successive registers hold the parts of the argument as if
1630 were loaded using lmw instructions.
1636 LITTLE: [d c b a] [x x x e]
1637 BIG: [a b c d] [e x x x]
1640 /* Adjust alignment. */
1641 if ((align >> 2) > 0)
1642 goff = align_up (goff, align >> 2);
1644 if (len <= (REND - goff) * 4)
1646 /* This argument can be passed wholly via GPRs. */
1649 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1651 regcache_cooked_write_unsigned (regcache,
1652 NDS32_R0_REGNUM + goff,
1662 /* Some parts of this argument can be passed via GPRs. */
1665 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1667 regcache_cooked_write_unsigned (regcache,
1668 NDS32_R0_REGNUM + goff,
1679 When pushing (split parts of) an argument into stack,
1681 * A composite type not larger than 4 bytes is copied to different
1683 In little-endian, the first byte of this argument is aligned
1684 at the low address of the next free word.
1685 In big-endian, the last byte of this argument is aligned
1686 at the high address of the next free word.
1697 /* Adjust alignment. */
1698 soff = align_up (soff, align);
1702 int rlen = (len > 4) ? 4 : len;
1704 if (byte_order == BFD_ENDIAN_BIG)
1705 write_memory (sp + soff + 4 - rlen, val, rlen);
1707 write_memory (sp + soff, val, rlen);
1715 /* Finally, update the SP register. */
1716 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1721 /* If use_fpr, but no floating-point register exists,
1722 then it is an error. */
1723 error (_("Fail to call. FPU registers are required."));
1726 /* Read, for architecture GDBARCH, a function return value of TYPE
1727 from REGCACHE, and copy that into VALBUF. */
1730 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1731 struct regcache *regcache, gdb_byte *valbuf)
1733 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1734 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1735 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1736 int calling_use_fpr;
1739 calling_use_fpr = nds32_check_calling_use_fpr (type);
1740 len = TYPE_LENGTH (type);
1742 if (abi_use_fpr && calling_use_fpr)
1745 regcache_cooked_read (regcache, tdep->fs0_regnum, valbuf);
1747 regcache_cooked_read (regcache, NDS32_FD0_REGNUM, valbuf);
1749 internal_error (__FILE__, __LINE__,
1750 _("Cannot extract return value of %d bytes "
1751 "long floating-point."), len);
1756 When returning result,
1758 * A composite type not larger than 4 bytes is returned in $r0.
1759 The format is as if the result is loaded with load instruction
1760 of corresponding size (e.g., LB, LH, LW).
1769 * Otherwise, a composite type not larger than 8 bytes is returned
1771 In little-endian, the first word is loaded in $r0.
1772 In big-endian, the last word is loaded in $r1.
1778 LITTLE: [d c b a] [x x x e]
1779 BIG: [x x x a] [b c d e]
1786 /* By using store_unsigned_integer we avoid having to do
1787 anything special for small big-endian values. */
1788 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1789 store_unsigned_integer (valbuf, len, byte_order, tmp);
1793 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1799 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1802 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1803 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1805 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1806 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1810 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1811 regcache_cooked_read (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1816 /* Write, for architecture GDBARCH, a function return value of TYPE
1817 from VALBUF into REGCACHE. */
1820 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1821 struct regcache *regcache, const gdb_byte *valbuf)
1823 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1824 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1825 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1826 int calling_use_fpr;
1829 calling_use_fpr = nds32_check_calling_use_fpr (type);
1830 len = TYPE_LENGTH (type);
1832 if (abi_use_fpr && calling_use_fpr)
1835 regcache_cooked_write (regcache, tdep->fs0_regnum, valbuf);
1837 regcache_cooked_write (regcache, NDS32_FD0_REGNUM, valbuf);
1839 internal_error (__FILE__, __LINE__,
1840 _("Cannot store return value of %d bytes "
1841 "long floating-point."), len);
1849 regval = extract_unsigned_integer (valbuf, len, byte_order);
1850 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1854 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1860 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1863 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1864 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1866 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1867 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1872 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1873 regcache_cooked_write (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1878 /* Implement the "return_value" gdbarch method.
1880 Determine, for architecture GDBARCH, how a return value of TYPE
1881 should be returned. If it is supposed to be returned in registers,
1882 and READBUF is non-zero, read the appropriate value from REGCACHE,
1883 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1884 from WRITEBUF into REGCACHE. */
1886 static enum return_value_convention
1887 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1888 struct type *type, struct regcache *regcache,
1889 gdb_byte *readbuf, const gdb_byte *writebuf)
1891 if (TYPE_LENGTH (type) > 8)
1893 return RETURN_VALUE_STRUCT_CONVENTION;
1897 if (readbuf != NULL)
1898 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1899 if (writebuf != NULL)
1900 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1902 return RETURN_VALUE_REGISTER_CONVENTION;
1906 /* Implement the "get_longjmp_target" gdbarch method. */
1909 nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1913 struct gdbarch *gdbarch = get_frame_arch (frame);
1914 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1916 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1918 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1921 *pc = extract_unsigned_integer (buf, 4, byte_order);
1925 /* Validate the given TDESC, and fixed-number some registers in it.
1926 Return 0 if the given TDESC does not contain the required feature
1927 or not contain required registers. */
1930 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1931 struct tdesc_arch_data *tdesc_data,
1932 int *fpu_freg, int *use_pseudo_fsrs)
1934 const struct tdesc_feature *feature;
1937 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1938 if (feature == NULL)
1942 /* Validate and fixed-number R0-R10. */
1943 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1944 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1945 nds32_register_names[i]);
1948 valid_p &= tdesc_unnumbered_register (feature,
1949 nds32_register_names[NDS32_TA_REGNUM]);
1951 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1952 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1953 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1954 nds32_register_names[i]);
1959 /* Fixed-number R11-R27. */
1960 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1961 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1963 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1964 if (feature != NULL)
1966 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1969 /* Guess FPU configuration via listed registers. */
1970 if (tdesc_unnumbered_register (feature, "fd31"))
1972 else if (tdesc_unnumbered_register (feature, "fd15"))
1974 else if (tdesc_unnumbered_register (feature, "fd7"))
1976 else if (tdesc_unnumbered_register (feature, "fd3"))
1980 /* Required FDR is not found. */
1985 /* Validate and fixed-number required FDRs. */
1986 num_fdr_regs = num_fdr_map[freg];
1987 for (i = 0; i < num_fdr_regs; i++)
1988 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1989 NDS32_FD0_REGNUM + i,
1990 nds32_fdr_register_names[i]);
1994 /* Count the number of listed FSRs, and fixed-number them if present. */
1995 num_fsr_regs = num_fsr_map[freg];
1996 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1998 for (i = 0; i < num_fsr_regs; i++)
1999 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
2001 nds32_fsr_register_names[i]);
2003 if (num_listed_fsr == 0)
2004 /* No required FSRs are listed explicitly, make them pseudo registers
2006 *use_pseudo_fsrs = 1;
2007 else if (num_listed_fsr == num_fsr_regs)
2008 /* All required FSRs are listed explicitly. */
2009 *use_pseudo_fsrs = 0;
2011 /* Some required FSRs are missing. */
2018 /* Initialize the current architecture based on INFO. If possible,
2019 re-use an architecture from ARCHES, which is a list of
2020 architectures already created during this debugging session.
2022 Called e.g. at program startup, when reading a core file, and when
2023 reading a binary file. */
2025 static struct gdbarch *
2026 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2028 struct gdbarch *gdbarch;
2029 struct gdbarch_tdep *tdep;
2030 struct gdbarch_list *best_arch;
2031 struct tdesc_arch_data *tdesc_data = NULL;
2032 const struct target_desc *tdesc = info.target_desc;
2033 int elf_abi = E_NDS_ABI_AABI;
2035 int use_pseudo_fsrs = 0;
2036 int i, num_regs, maxregs;
2038 /* Extract the elf_flags if available. */
2039 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2040 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
2042 /* If there is already a candidate, use it. */
2043 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2045 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2047 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2049 if (idep->elf_abi != elf_abi)
2052 /* Found a match. */
2056 if (best_arch != NULL)
2057 return best_arch->gdbarch;
2059 if (!tdesc_has_registers (tdesc))
2060 tdesc = tdesc_nds32;
2062 tdesc_data = tdesc_data_alloc ();
2064 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2066 tdesc_data_cleanup (tdesc_data);
2070 /* Allocate space for the new architecture. */
2071 tdep = XCNEW (struct gdbarch_tdep);
2072 tdep->fpu_freg = fpu_freg;
2073 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2074 tdep->fs0_regnum = -1;
2075 tdep->elf_abi = elf_abi;
2077 gdbarch = gdbarch_alloc (&info, tdep);
2079 set_gdbarch_wchar_bit (gdbarch, 16);
2080 set_gdbarch_wchar_signed (gdbarch, 0);
2083 num_regs = NDS32_NUM_REGS;
2084 else if (use_pseudo_fsrs == 1)
2086 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2087 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2088 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2089 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2090 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2092 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2095 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2097 set_gdbarch_num_regs (gdbarch, num_regs);
2098 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2100 /* Cache the register number of fs0. */
2102 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2104 /* Add NDS32 register aliases. To avoid search in user register name space,
2105 user_reg_map_name_to_regnum is not used. */
2106 maxregs = (gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch));
2107 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2112 /* Search register name space. */
2113 for (j = 0; j < maxregs; j++)
2115 const char *regname = gdbarch_register_name (gdbarch, j);
2118 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2125 /* Try next alias entry if the given name can not be found in register
2130 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2131 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2134 nds32_add_reggroups (gdbarch);
2136 /* Hook in ABI-specific overrides, if they have been registered. */
2137 info.tdep_info = (void *) tdesc_data;
2138 gdbarch_init_osabi (info, gdbarch);
2140 /* Override tdesc_register callbacks for system registers. */
2141 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2143 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2144 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2145 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2146 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2147 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2148 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2150 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2151 set_gdbarch_return_value (gdbarch, nds32_return_value);
2152 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2154 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2155 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2156 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2157 nds32_breakpoint::kind_from_pc);
2158 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2159 nds32_breakpoint::bp_from_kind);
2161 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2162 frame_base_set_default (gdbarch, &nds32_frame_base);
2164 /* Handle longjmp. */
2165 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2167 /* The order of appending is the order it check frame. */
2168 dwarf2_append_unwinders (gdbarch);
2169 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2170 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2176 _initialize_nds32_tdep (void)
2178 /* Initialize gdbarch. */
2179 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2181 initialize_tdesc_nds32 ();
2182 nds32_init_reggroups ();