1 /* Target-dependent code for the NDS32 architecture, for GDB.
3 Copyright (C) 2013-2016 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
29 #include "reggroups.h"
32 #include "arch-utils.h"
35 #include "user-regs.h"
37 #include "dwarf2-frame.h"
39 #include "target-descriptions.h"
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
46 #include "features/nds32.c"
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
58 extern void _initialize_nds32_tdep (void);
60 /* Use an invalid address value as 'not available' marker. */
61 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
63 /* Use an impossible value as invalid offset. */
64 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
66 /* Instruction groups for NDS32 epilogue analysis. */
69 /* Instructions used everywhere, not only in epilogue. */
71 /* Instructions used to reset sp for local vars, arguments, etc. */
73 /* Instructions used to recover saved regs and to recover padding. */
75 /* Instructions used to return to the caller. */
77 /* Instructions used to recover saved regs and to return to the caller. */
81 static const char *const nds32_register_names[] =
84 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
85 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
86 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
87 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
92 static const char *const nds32_fdr_register_names[] =
94 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
95 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
96 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
97 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
100 static const char *const nds32_fsr_register_names[] =
102 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
103 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
104 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
105 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
108 /* The number of registers for four FPU configuration options. */
109 const int num_fdr_map[] = { 4, 8, 16, 32 };
110 const int num_fsr_map[] = { 8, 16, 32, 32 };
112 /* Aliases for registers. */
117 } nds32_register_aliases[] =
133 {"cr6", "fucop_exist"},
150 {"ir14", "int_mask"},
151 {"ir15", "int_pend"},
155 {"ir19", "int_ctrl"},
157 {"ir21", "sp_priv1"},
159 {"ir23", "sp_priv2"},
161 {"ir25", "sp_priv3"},
162 {"ir26", "int_mask2"},
163 {"ir27", "int_pend2"},
164 {"ir28", "int_pri2"},
165 {"ir29", "int_trigger"},
175 {"mr8", "cache_ctl"},
176 {"mr9", "hsmp_saddr"},
177 {"mr10", "hsmp_eaddr"},
178 {"mr11", "bg_region"},
229 {"hspr0", "hsp_ctl"},
230 {"hspr1", "sp_bound"},
231 {"hspr2", "sp_bound_priv"},
239 {"dmar0", "dma_cfg"},
240 {"dmar1", "dma_gcsw"},
241 {"dmar2", "dma_chnsel"},
242 {"dmar3", "dma_act"},
243 {"dmar4", "dma_setup"},
244 {"dmar5", "dma_isaddr"},
245 {"dmar6", "dma_esaddr"},
246 {"dmar7", "dma_tcnt"},
247 {"dmar8", "dma_status"},
248 {"dmar9", "dma_2dset"},
249 {"dmar10", "dma_2dsctl"},
250 {"dmar11", "dma_rcnt"},
251 {"dmar12", "dma_hstatus"},
253 {"racr0", "prusr_acc_ctl"},
254 {"fucpr", "fucop_ctl"},
257 {"idr1", "misc_ctl"},
258 {"idr2", "ecc_misc"},
263 {"secur3", "p_isign"},
266 /* Value of a register alias. BATON is the regnum of the corresponding
269 static struct value *
270 value_of_nds32_reg (struct frame_info *frame, const void *baton)
272 return value_of_register ((int) (intptr_t) baton, frame);
275 /* Implement the "frame_align" gdbarch method. */
278 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
280 /* 8-byte aligned. */
281 return align_down (sp, 8);
284 /* The same insn machine code is used for little-endian and big-endian. */
285 constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
287 typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
289 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
292 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
294 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
296 const int FDR = FSR + 32;
298 if (num >= 0 && num < 32)
300 /* General-purpose registers (R0 - R31). */
303 else if (num >= FSR && num < FSR + 32)
305 /* Single precision floating-point registers (FS0 - FS31). */
306 return num - FSR + tdep->fs0_regnum;
308 else if (num >= FDR && num < FDR + 32)
310 /* Double precision floating-point registers (FD0 - FD31). */
311 return num - FDR + NDS32_FD0_REGNUM;
314 /* No match, return a inaccessible register number. */
318 /* NDS32 register groups. */
319 static struct reggroup *nds32_cr_reggroup;
320 static struct reggroup *nds32_ir_reggroup;
321 static struct reggroup *nds32_mr_reggroup;
322 static struct reggroup *nds32_dr_reggroup;
323 static struct reggroup *nds32_pfr_reggroup;
324 static struct reggroup *nds32_hspr_reggroup;
325 static struct reggroup *nds32_dmar_reggroup;
326 static struct reggroup *nds32_racr_reggroup;
327 static struct reggroup *nds32_idr_reggroup;
328 static struct reggroup *nds32_secur_reggroup;
331 nds32_init_reggroups (void)
333 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
334 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
335 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
336 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
337 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
338 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
339 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
340 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
341 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
342 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
346 nds32_add_reggroups (struct gdbarch *gdbarch)
348 /* Add pre-defined register groups. */
349 reggroup_add (gdbarch, general_reggroup);
350 reggroup_add (gdbarch, float_reggroup);
351 reggroup_add (gdbarch, system_reggroup);
352 reggroup_add (gdbarch, all_reggroup);
353 reggroup_add (gdbarch, save_reggroup);
354 reggroup_add (gdbarch, restore_reggroup);
356 /* Add NDS32 register groups. */
357 reggroup_add (gdbarch, nds32_cr_reggroup);
358 reggroup_add (gdbarch, nds32_ir_reggroup);
359 reggroup_add (gdbarch, nds32_mr_reggroup);
360 reggroup_add (gdbarch, nds32_dr_reggroup);
361 reggroup_add (gdbarch, nds32_pfr_reggroup);
362 reggroup_add (gdbarch, nds32_hspr_reggroup);
363 reggroup_add (gdbarch, nds32_dmar_reggroup);
364 reggroup_add (gdbarch, nds32_racr_reggroup);
365 reggroup_add (gdbarch, nds32_idr_reggroup);
366 reggroup_add (gdbarch, nds32_secur_reggroup);
369 /* Implement the "register_reggroup_p" gdbarch method. */
372 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
373 struct reggroup *reggroup)
375 const char *reg_name;
376 const char *group_name;
379 if (reggroup == all_reggroup)
382 /* General reggroup contains only GPRs and PC. */
383 if (reggroup == general_reggroup)
384 return regnum <= NDS32_PC_REGNUM;
386 if (reggroup == float_reggroup || reggroup == save_reggroup
387 || reggroup == restore_reggroup)
389 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
393 return default_register_reggroup_p (gdbarch, regnum, reggroup);
396 if (reggroup == system_reggroup)
397 return (regnum > NDS32_PC_REGNUM)
398 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
400 /* The NDS32 reggroup contains registers whose name is prefixed
402 reg_name = gdbarch_register_name (gdbarch, regnum);
403 group_name = reggroup_name (reggroup);
404 return !strncmp (reg_name, group_name, strlen (group_name));
407 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
410 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
412 regnum -= gdbarch_num_regs (gdbarch);
414 /* Currently, only FSRs could be defined as pseudo registers. */
415 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
416 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
417 floatformats_ieee_single);
419 warning (_("Unknown nds32 pseudo register %d."), regnum);
423 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
426 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
428 regnum -= gdbarch_num_regs (gdbarch);
430 /* Currently, only FSRs could be defined as pseudo registers. */
431 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
432 return nds32_fsr_register_names[regnum];
434 warning (_("Unknown nds32 pseudo register %d."), regnum);
438 /* Implement the "pseudo_register_read" gdbarch method. */
440 static enum register_status
441 nds32_pseudo_register_read (struct gdbarch *gdbarch,
442 struct regcache *regcache, int regnum,
445 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
447 int offset, fdr_regnum;
448 enum register_status status = REG_UNKNOWN;
451 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
454 regnum -= gdbarch_num_regs (gdbarch);
456 /* Currently, only FSRs could be defined as pseudo registers. */
457 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
459 /* fs0 is always the most significant half of fd0. */
460 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
461 offset = (regnum & 1) ? 4 : 0;
463 offset = (regnum & 1) ? 0 : 4;
465 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
466 status = regcache_raw_read (regcache, fdr_regnum, reg_buf);
467 if (status == REG_VALID)
468 memcpy (buf, reg_buf + offset, 4);
474 /* Implement the "pseudo_register_write" gdbarch method. */
477 nds32_pseudo_register_write (struct gdbarch *gdbarch,
478 struct regcache *regcache, int regnum,
481 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
483 int offset, fdr_regnum;
486 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
489 regnum -= gdbarch_num_regs (gdbarch);
491 /* Currently, only FSRs could be defined as pseudo registers. */
492 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
494 /* fs0 is always the most significant half of fd0. */
495 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
496 offset = (regnum & 1) ? 4 : 0;
498 offset = (regnum & 1) ? 0 : 4;
500 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
501 regcache_raw_read (regcache, fdr_regnum, reg_buf);
502 memcpy (reg_buf + offset, buf, 4);
503 regcache_raw_write (regcache, fdr_regnum, reg_buf);
507 /* Helper function for NDS32 ABI. Return true if FPRs can be used
508 to pass function arguments and return value. */
511 nds32_abi_use_fpr (int elf_abi)
513 return elf_abi == E_NDS_ABI_V2FP_PLUS;
516 /* Helper function for NDS32 ABI. Return true if GPRs and stack
517 can be used together to pass an argument. */
520 nds32_abi_split (int elf_abi)
522 return elf_abi == E_NDS_ABI_AABI;
525 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
527 struct nds32_frame_cache
529 /* The previous frame's inner most stack address. Used as this
530 frame ID's stack_addr. */
533 /* The frame's base, optionally used by the high-level debug info. */
536 /* During prologue analysis, keep how far the SP and FP have been offset
537 from the start of the stack frame (as defined by the previous frame's
539 During epilogue analysis, keep how far the SP has been offset from the
540 current stack pointer. */
544 /* The address of the first instruction in this function. */
547 /* Saved registers. */
548 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
551 /* Allocate and initialize a frame cache. */
553 static struct nds32_frame_cache *
554 nds32_alloc_frame_cache (void)
556 struct nds32_frame_cache *cache;
559 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
561 /* Initialize fp_offset to check if FP is set in prologue. */
562 cache->fp_offset = INVALID_OFFSET;
564 /* Saved registers. We initialize these to -1 since zero is a valid
566 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
567 cache->saved_regs[i] = REG_UNAVAIL;
572 /* Helper function for instructions used to push multiple words. */
575 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
578 CORE_ADDR sp_offset = cache->sp_offset;
581 /* Check LP, GP, FP in enable4. */
582 for (i = 1; i <= 3; i++)
584 if ((enable4 >> i) & 0x1)
587 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
591 /* Skip case where re == rb == sp. */
592 if ((rb < REG_FP) && (re < REG_FP))
594 for (i = re; i >= rb; i--)
597 cache->saved_regs[i] = sp_offset;
601 /* For sp, update the offset. */
602 cache->sp_offset = sp_offset;
605 /* Analyze the instructions within the given address range. If CACHE
606 is non-NULL, fill it in. Return the first address beyond the given
607 address range. If CACHE is NULL, return the first address not
608 recognized as a prologue instruction. */
611 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
612 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
614 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
615 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
616 /* Current scanning status. */
617 int in_prologue_bb = 0;
619 uint32_t insn, insn_len;
621 for (; pc < limit_pc; pc += insn_len)
623 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
625 if ((insn & 0x80000000) == 0)
627 /* 32-bit instruction */
630 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
632 /* addi $sp, $sp, imm15s */
633 int imm15s = N32_IMM15S (insn);
638 cache->sp_offset += -imm15s;
644 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
646 /* addi $fp, $sp, imm15s */
647 int imm15s = N32_IMM15S (insn);
652 cache->fp_offset = cache->sp_offset - imm15s;
658 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
659 && N32_RA5 (insn) == REG_SP)
661 /* smw.adm Rb, [$sp], Re, enable4 */
663 nds32_push_multiple_words (cache, N32_RT5 (insn),
665 N32_LSMW_ENABLE4 (insn));
669 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
670 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
672 /* add $sp, $sp, $ta */
673 /* add $sp, $ta, $sp */
677 cache->sp_offset += -val_ta;
683 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
685 /* movi $ta, imm20s */
687 val_ta = N32_IMM20S (insn);
691 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
693 /* sethi $ta, imm20u */
695 val_ta = N32_IMM20U (insn) << 12;
699 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
701 /* ori $ta, $ta, imm15u */
703 val_ta |= N32_IMM15U (insn);
707 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
709 /* addi $ta, $ta, imm15s */
711 val_ta += N32_IMM15S (insn);
715 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
716 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
718 /* add $gp, $ta, $gp */
719 /* add $gp, $gp, $ta */
723 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
725 /* movi $gp, imm20s */
729 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
731 /* sethi $gp, imm20u */
735 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
737 /* ori $gp, $gp, imm15u */
743 /* Jump/Branch insns never appear in prologue basic block.
744 The loop can be escaped early when these insns are met. */
745 if (in_prologue_bb == 1)
747 int op = N32_OP6 (insn);
750 || op == N32_OP6_JREG
753 || op == N32_OP6_BR3)
758 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
759 && __GF (insn, 12, 3) == 0)
761 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
762 normal form (bit [12] == 0) is used. */
764 /* fsdi FDt, [$sp + (imm12s << 2)] */
765 if (N32_RA5 (insn) == REG_SP)
769 /* The optimizer might shove anything into the prologue, if
770 we build up cache (cache != NULL) from analyzing prologue,
771 we just skip what we don't recognize and analyze further to
772 make cache as complete as possible. However, if we skip
773 prologue, we'll stop immediately on unrecognized
780 /* 16-bit instruction */
785 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
788 int imm10s = N16_IMM10S (insn);
793 cache->sp_offset += -imm10s;
799 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
804 int imm8u = (insn & 0x1f) << 3;
805 int re = (insn >> 5) & 0x3;
806 const int reg_map[] = { 6, 8, 10, 14 };
808 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
809 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
811 /* Operation 2 -- sp = sp - (imm5u << 3) */
812 cache->sp_offset += imm8u;
818 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
824 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
826 /* movi55 $gp, imm5s */
832 /* Jump/Branch insns never appear in prologue basic block.
833 The loop can be escaped early when these insns are met. */
834 if (in_prologue_bb == 1)
836 uint32_t insn5 = CHOP_BITS (insn, 5);
837 uint32_t insn8 = CHOP_BITS (insn, 8);
838 uint32_t insn38 = CHOP_BITS (insn, 11);
840 if (insn5 == N16_TYPE5 (JR5, 0)
841 || insn5 == N16_TYPE5 (JRAL5, 0)
842 || insn5 == N16_TYPE5 (RET5, 0)
843 || insn8 == N16_TYPE8 (J8, 0)
844 || insn8 == N16_TYPE8 (BEQZS8, 0)
845 || insn8 == N16_TYPE8 (BNEZS8, 0)
846 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
847 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
848 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
849 || insn38 == N16_TYPE38 (BNES38, 0, 0))
854 /* The optimizer might shove anything into the prologue, if
855 we build up cache (cache != NULL) from analyzing prologue,
856 we just skip what we don't recognize and analyze further to
857 make cache as complete as possible. However, if we skip
858 prologue, we'll stop immediately on unrecognized
868 /* Implement the "skip_prologue" gdbarch method.
870 Find the end of function prologue. */
873 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
875 CORE_ADDR func_addr, limit_pc;
877 /* See if we can determine the end of the prologue via the symbol table.
878 If so, then return either PC, or the PC after the prologue, whichever
880 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
882 CORE_ADDR post_prologue_pc
883 = skip_prologue_using_sal (gdbarch, func_addr);
884 if (post_prologue_pc != 0)
885 return std::max (pc, post_prologue_pc);
888 /* Can't determine prologue from the symbol table, need to examine
891 /* Find an upper limit on the function prologue using the debug
892 information. If the debug information could not be used to provide
893 that bound, then use an arbitrary large number as the upper bound. */
894 limit_pc = skip_prologue_using_sal (gdbarch, pc);
896 limit_pc = pc + 128; /* Magic. */
898 /* Find the end of prologue. */
899 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
902 /* Allocate and fill in *THIS_CACHE with information about the prologue of
903 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
904 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
906 static struct nds32_frame_cache *
907 nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
909 struct gdbarch *gdbarch = get_frame_arch (this_frame);
910 struct nds32_frame_cache *cache;
911 CORE_ADDR current_pc;
917 return (struct nds32_frame_cache *) *this_cache;
919 cache = nds32_alloc_frame_cache ();
922 cache->pc = get_frame_func (this_frame);
923 current_pc = get_frame_pc (this_frame);
924 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
926 /* Compute the previous frame's stack pointer (which is also the
927 frame's ID's stack address), and this frame's base pointer. */
928 if (cache->fp_offset != INVALID_OFFSET)
930 /* FP is set in prologue, so it can be used to calculate other info. */
931 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
932 prev_sp = this_base + cache->fp_offset;
936 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
937 prev_sp = this_base + cache->sp_offset;
940 cache->prev_sp = prev_sp;
941 cache->base = this_base;
943 /* Adjust all the saved registers such that they contain addresses
944 instead of offsets. */
945 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
946 if (cache->saved_regs[i] != REG_UNAVAIL)
947 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
952 /* Implement the "this_id" frame_unwind method.
954 Our frame ID for a normal frame is the current function's starting
955 PC and the caller's SP when we were called. */
958 nds32_frame_this_id (struct frame_info *this_frame,
959 void **this_cache, struct frame_id *this_id)
961 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
963 /* This marks the outermost frame. */
964 if (cache->prev_sp == 0)
967 *this_id = frame_id_build (cache->prev_sp, cache->pc);
970 /* Implement the "prev_register" frame_unwind method. */
972 static struct value *
973 nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
976 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
978 if (regnum == NDS32_SP_REGNUM)
979 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
981 /* The PC of the previous frame is stored in the LP register of
982 the current frame. */
983 if (regnum == NDS32_PC_REGNUM)
984 regnum = NDS32_LP_REGNUM;
986 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
987 return frame_unwind_got_memory (this_frame, regnum,
988 cache->saved_regs[regnum]);
990 return frame_unwind_got_register (this_frame, regnum, regnum);
993 static const struct frame_unwind nds32_frame_unwind =
996 default_frame_unwind_stop_reason,
998 nds32_frame_prev_register,
1000 default_frame_sniffer,
1003 /* Return the frame base address of *THIS_FRAME. */
1006 nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1008 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1013 static const struct frame_base nds32_frame_base =
1015 &nds32_frame_unwind,
1016 nds32_frame_base_address,
1017 nds32_frame_base_address,
1018 nds32_frame_base_address
1021 /* Helper function for instructions used to pop multiple words. */
1024 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1027 CORE_ADDR sp_offset = cache->sp_offset;
1030 /* Skip case where re == rb == sp. */
1031 if ((rb < REG_FP) && (re < REG_FP))
1033 for (i = rb; i <= re; i++)
1035 cache->saved_regs[i] = sp_offset;
1040 /* Check FP, GP, LP in enable4. */
1041 for (i = 3; i >= 1; i--)
1043 if ((enable4 >> i) & 0x1)
1045 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1050 /* For sp, update the offset. */
1051 cache->sp_offset = sp_offset;
1054 /* The instruction sequences in NDS32 epilogue are
1056 INSN_RESET_SP (optional)
1057 (If exists, this must be the first instruction in epilogue
1058 and the stack has not been destroyed.).
1059 INSN_RECOVER (optional).
1060 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1062 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1063 the necessary information will be recorded. */
1066 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1067 struct nds32_frame_cache *cache)
1069 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1070 && N32_IMM15S (insn) > 0)
1071 /* addi $sp, $sp, imm15s */
1072 return INSN_RESET_SP;
1073 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1074 && N32_IMM15S (insn) < 0)
1075 /* addi $sp, $fp, imm15s */
1076 return INSN_RESET_SP;
1077 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1078 && N32_RA5 (insn) == REG_SP)
1080 /* lmw.bim Rb, [$sp], Re, enable4 */
1082 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1083 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1085 return INSN_RECOVER;
1087 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1090 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1091 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1092 /* add $sp, $sp, $ta */
1093 /* add $sp, $ta, $sp */
1094 return INSN_RESET_SP;
1095 else if (abi_use_fpr
1096 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1098 if (__GF (insn, 12, 1) == 0)
1099 /* fldi FDt, [$sp + (imm12s << 2)] */
1100 return INSN_RECOVER;
1103 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1104 int offset = N32_IMM12S (insn) << 2;
1106 if (offset == 8 || offset == 12)
1109 cache->sp_offset += offset;
1111 return INSN_RECOVER;
1119 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1120 the necessary information will be recorded. */
1123 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1125 if (insn == N16_TYPE5 (RET5, REG_LP))
1128 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1131 int imm10s = N16_IMM10S (insn);
1136 cache->sp_offset += imm10s;
1138 return INSN_RECOVER;
1141 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1146 int imm8u = (insn & 0x1f) << 3;
1147 int re = (insn >> 5) & 0x3;
1148 const int reg_map[] = { 6, 8, 10, 14 };
1150 /* Operation 1 -- sp = sp + (imm5u << 3) */
1151 cache->sp_offset += imm8u;
1153 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1154 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1157 /* Operation 3 -- ret $lp */
1158 return INSN_RECOVER_RETURN;
1164 /* Analyze a reasonable amount of instructions from the given PC to find
1165 the instruction used to return to the caller. Return 1 if the 'return'
1166 instruction could be found, 0 otherwise.
1168 If CACHE is non-NULL, fill it in. */
1171 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1172 struct nds32_frame_cache *cache)
1174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1175 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1177 uint32_t insn, insn_len;
1178 int insn_type = INSN_NORMAL;
1185 for (; pc < limit_pc; pc += insn_len)
1187 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1189 if ((insn & 0x80000000) == 0)
1191 /* 32-bit instruction */
1194 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1195 if (insn_type == INSN_RETURN)
1197 else if (insn_type == INSN_RECOVER)
1202 /* 16-bit instruction */
1206 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1207 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1209 else if (insn_type == INSN_RECOVER)
1213 /* Stop the scan if this is an unexpected instruction. */
1220 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1223 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1225 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1226 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1227 int insn_type = INSN_NORMAL;
1231 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1233 if ((insn & 0x80000000) == 0)
1235 /* 32-bit instruction */
1237 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1241 /* 16-bit instruction */
1244 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1247 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1250 /* Search the required 'return' instruction within the following reasonable
1252 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1256 /* Scan backwards to make sure that the last instruction has adjusted
1257 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1258 just a heuristic, so the false positives will be acceptable. */
1259 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1261 /* Only 16-bit instructions are possible at addr - 2. */
1262 if ((insn & 0x80000000) != 0)
1264 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1266 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1267 if (insn_type == INSN_RECOVER)
1271 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1273 /* If this is a 16-bit instruction at addr - 4, then there must be another
1274 16-bit instruction at addr - 2, so only 32-bit instructions need to
1275 be analyzed here. */
1276 if ((insn & 0x80000000) == 0)
1278 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1280 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1281 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1288 /* Implement the "sniffer" frame_unwind method. */
1291 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1292 struct frame_info *this_frame, void **this_cache)
1294 if (frame_relative_level (this_frame) == 0)
1295 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1296 get_frame_pc (this_frame));
1301 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1302 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1303 allocated. Return a pointer to the current nds32_frame_cache in
1306 static struct nds32_frame_cache *
1307 nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1309 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1310 struct nds32_frame_cache *cache;
1311 CORE_ADDR current_pc, current_sp;
1315 return (struct nds32_frame_cache *) *this_cache;
1317 cache = nds32_alloc_frame_cache ();
1318 *this_cache = cache;
1320 cache->pc = get_frame_func (this_frame);
1321 current_pc = get_frame_pc (this_frame);
1322 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1324 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1325 cache->prev_sp = current_sp + cache->sp_offset;
1327 /* Adjust all the saved registers such that they contain addresses
1328 instead of offsets. */
1329 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1330 if (cache->saved_regs[i] != REG_UNAVAIL)
1331 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1336 /* Implement the "this_id" frame_unwind method. */
1339 nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1340 void **this_cache, struct frame_id *this_id)
1342 struct nds32_frame_cache *cache
1343 = nds32_epilogue_frame_cache (this_frame, this_cache);
1345 /* This marks the outermost frame. */
1346 if (cache->prev_sp == 0)
1349 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1352 /* Implement the "prev_register" frame_unwind method. */
1354 static struct value *
1355 nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1356 void **this_cache, int regnum)
1358 struct nds32_frame_cache *cache
1359 = nds32_epilogue_frame_cache (this_frame, this_cache);
1361 if (regnum == NDS32_SP_REGNUM)
1362 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1364 /* The PC of the previous frame is stored in the LP register of
1365 the current frame. */
1366 if (regnum == NDS32_PC_REGNUM)
1367 regnum = NDS32_LP_REGNUM;
1369 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1370 return frame_unwind_got_memory (this_frame, regnum,
1371 cache->saved_regs[regnum]);
1373 return frame_unwind_got_register (this_frame, regnum, regnum);
1376 static const struct frame_unwind nds32_epilogue_frame_unwind =
1379 default_frame_unwind_stop_reason,
1380 nds32_epilogue_frame_this_id,
1381 nds32_epilogue_frame_prev_register,
1383 nds32_epilogue_frame_sniffer
1386 /* Implement the "dummy_id" gdbarch method. */
1388 static struct frame_id
1389 nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1391 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1393 return frame_id_build (sp, get_frame_pc (this_frame));
1396 /* Implement the "unwind_pc" gdbarch method. */
1399 nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1401 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1404 /* Implement the "unwind_sp" gdbarch method. */
1407 nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1409 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1412 /* Floating type and struct type that has only one floating type member
1413 can pass value using FPU registers (when FPU ABI is used). */
1416 nds32_check_calling_use_fpr (struct type *type)
1419 enum type_code typecode;
1424 t = check_typedef (t);
1425 typecode = TYPE_CODE (t);
1426 if (typecode != TYPE_CODE_STRUCT)
1428 else if (TYPE_NFIELDS (t) != 1)
1431 t = TYPE_FIELD_TYPE (t, 0);
1434 return typecode == TYPE_CODE_FLT;
1437 /* Return the alignment (in bytes) of the given type. */
1440 nds32_type_align (struct type *type)
1446 type = check_typedef (type);
1447 switch (TYPE_CODE (type))
1450 /* Should never happen. */
1451 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1455 case TYPE_CODE_ENUM:
1459 case TYPE_CODE_RANGE:
1461 case TYPE_CODE_CHAR:
1462 case TYPE_CODE_BOOL:
1463 return TYPE_LENGTH (type);
1465 case TYPE_CODE_ARRAY:
1466 case TYPE_CODE_COMPLEX:
1467 return nds32_type_align (TYPE_TARGET_TYPE (type));
1469 case TYPE_CODE_STRUCT:
1470 case TYPE_CODE_UNION:
1472 for (n = 0; n < TYPE_NFIELDS (type); n++)
1474 falign = nds32_type_align (TYPE_FIELD_TYPE (type, n));
1482 /* Implement the "push_dummy_call" gdbarch method. */
1485 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1486 struct regcache *regcache, CORE_ADDR bp_addr,
1487 int nargs, struct value **args, CORE_ADDR sp,
1488 int struct_return, CORE_ADDR struct_addr)
1490 const int REND = 6; /* End for register offset. */
1491 int goff = 0; /* Current gpr offset for argument. */
1492 int foff = 0; /* Current fpr offset for argument. */
1493 int soff = 0; /* Current stack offset for argument. */
1496 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1497 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1498 struct type *func_type = value_type (function);
1499 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1500 int abi_split = nds32_abi_split (tdep->elf_abi);
1502 /* Set the return address. For the NDS32, the return breakpoint is
1503 always at BP_ADDR. */
1504 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1506 /* If STRUCT_RETURN is true, then the struct return address (in
1507 STRUCT_ADDR) will consume the first argument-passing register.
1508 Both adjust the register count and store that value. */
1511 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1515 /* Now make sure there's space on the stack */
1516 for (i = 0; i < nargs; i++)
1518 struct type *type = value_type (args[i]);
1519 int align = nds32_type_align (type);
1521 /* If align is zero, it may be an empty struct.
1522 Just ignore the argument of empty struct. */
1526 sp -= TYPE_LENGTH (type);
1527 sp = align_down (sp, align);
1530 /* Stack must be 8-byte aligned. */
1531 sp = align_down (sp, 8);
1534 for (i = 0; i < nargs; i++)
1536 const gdb_byte *val;
1539 int calling_use_fpr;
1542 type = value_type (args[i]);
1543 calling_use_fpr = nds32_check_calling_use_fpr (type);
1544 len = TYPE_LENGTH (type);
1545 align = nds32_type_align (type);
1546 val = value_contents (args[i]);
1548 /* The size of a composite type larger than 4 bytes will be rounded
1549 up to the nearest multiple of 4. */
1551 len = align_up (len, 4);
1553 /* Variadic functions are handled differently between AABI and ABI2FP+.
1555 For AABI, the caller pushes arguments in registers, callee stores
1556 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1557 Therefore, we don't have to handle variadic functions specially.
1559 For ABI2FP+, the caller pushes only named arguments in registers
1560 and pushes all unnamed arguments in stack. */
1562 if (abi_use_fpr && TYPE_VARARGS (func_type)
1563 && i >= TYPE_NFIELDS (func_type))
1566 /* Try to use FPRs to pass arguments only when
1567 1. The program is built using toolchain with FPU support.
1568 2. The type of this argument can use FPR to pass value. */
1569 use_fpr = abi_use_fpr && calling_use_fpr;
1573 if (tdep->fpu_freg == -1)
1576 /* Adjust alignment. */
1577 if ((align >> 2) > 0)
1578 foff = align_up (foff, align >> 2);
1585 regcache_cooked_write (regcache,
1586 tdep->fs0_regnum + foff, val);
1590 regcache_cooked_write (regcache,
1591 NDS32_FD0_REGNUM + (foff >> 1), val);
1596 internal_error (__FILE__, __LINE__,
1597 "Do not know how to handle %d-byte double.\n",
1607 When passing arguments using GPRs,
1609 * A composite type not larger than 4 bytes is passed in $rN.
1610 The format is as if the value is loaded with load instruction
1611 of corresponding size (e.g., LB, LH, LW).
1620 * Otherwise, a composite type is passed in consecutive registers.
1621 The size is rounded up to the nearest multiple of 4.
1622 The successive registers hold the parts of the argument as if
1623 were loaded using lmw instructions.
1629 LITTLE: [d c b a] [x x x e]
1630 BIG: [a b c d] [e x x x]
1633 /* Adjust alignment. */
1634 if ((align >> 2) > 0)
1635 goff = align_up (goff, align >> 2);
1637 if (len <= (REND - goff) * 4)
1639 /* This argument can be passed wholly via GPRs. */
1642 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1644 regcache_cooked_write_unsigned (regcache,
1645 NDS32_R0_REGNUM + goff,
1655 /* Some parts of this argument can be passed via GPRs. */
1658 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1660 regcache_cooked_write_unsigned (regcache,
1661 NDS32_R0_REGNUM + goff,
1672 When pushing (split parts of) an argument into stack,
1674 * A composite type not larger than 4 bytes is copied to different
1676 In little-endian, the first byte of this argument is aligned
1677 at the low address of the next free word.
1678 In big-endian, the last byte of this argument is aligned
1679 at the high address of the next free word.
1690 /* Adjust alignment. */
1691 soff = align_up (soff, align);
1695 int rlen = (len > 4) ? 4 : len;
1697 if (byte_order == BFD_ENDIAN_BIG)
1698 write_memory (sp + soff + 4 - rlen, val, rlen);
1700 write_memory (sp + soff, val, rlen);
1708 /* Finally, update the SP register. */
1709 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1714 /* If use_fpr, but no floating-point register exists,
1715 then it is an error. */
1716 error (_("Fail to call. FPU registers are required."));
1719 /* Read, for architecture GDBARCH, a function return value of TYPE
1720 from REGCACHE, and copy that into VALBUF. */
1723 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1724 struct regcache *regcache, gdb_byte *valbuf)
1726 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1727 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1728 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1729 int calling_use_fpr;
1732 calling_use_fpr = nds32_check_calling_use_fpr (type);
1733 len = TYPE_LENGTH (type);
1735 if (abi_use_fpr && calling_use_fpr)
1738 regcache_cooked_read (regcache, tdep->fs0_regnum, valbuf);
1740 regcache_cooked_read (regcache, NDS32_FD0_REGNUM, valbuf);
1742 internal_error (__FILE__, __LINE__,
1743 _("Cannot extract return value of %d bytes "
1744 "long floating-point."), len);
1749 When returning result,
1751 * A composite type not larger than 4 bytes is returned in $r0.
1752 The format is as if the result is loaded with load instruction
1753 of corresponding size (e.g., LB, LH, LW).
1762 * Otherwise, a composite type not larger than 8 bytes is returned
1764 In little-endian, the first word is loaded in $r0.
1765 In big-endian, the last word is loaded in $r1.
1771 LITTLE: [d c b a] [x x x e]
1772 BIG: [x x x a] [b c d e]
1779 /* By using store_unsigned_integer we avoid having to do
1780 anything special for small big-endian values. */
1781 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1782 store_unsigned_integer (valbuf, len, byte_order, tmp);
1786 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1792 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1795 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1796 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1798 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1799 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1803 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1804 regcache_cooked_read (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1809 /* Write, for architecture GDBARCH, a function return value of TYPE
1810 from VALBUF into REGCACHE. */
1813 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1814 struct regcache *regcache, const gdb_byte *valbuf)
1816 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1817 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1818 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1819 int calling_use_fpr;
1822 calling_use_fpr = nds32_check_calling_use_fpr (type);
1823 len = TYPE_LENGTH (type);
1825 if (abi_use_fpr && calling_use_fpr)
1828 regcache_cooked_write (regcache, tdep->fs0_regnum, valbuf);
1830 regcache_cooked_write (regcache, NDS32_FD0_REGNUM, valbuf);
1832 internal_error (__FILE__, __LINE__,
1833 _("Cannot store return value of %d bytes "
1834 "long floating-point."), len);
1842 regval = extract_unsigned_integer (valbuf, len, byte_order);
1843 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1847 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1853 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1856 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1857 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1859 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1860 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1865 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1866 regcache_cooked_write (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1871 /* Implement the "return_value" gdbarch method.
1873 Determine, for architecture GDBARCH, how a return value of TYPE
1874 should be returned. If it is supposed to be returned in registers,
1875 and READBUF is non-zero, read the appropriate value from REGCACHE,
1876 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1877 from WRITEBUF into REGCACHE. */
1879 static enum return_value_convention
1880 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1881 struct type *type, struct regcache *regcache,
1882 gdb_byte *readbuf, const gdb_byte *writebuf)
1884 if (TYPE_LENGTH (type) > 8)
1886 return RETURN_VALUE_STRUCT_CONVENTION;
1890 if (readbuf != NULL)
1891 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1892 if (writebuf != NULL)
1893 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1895 return RETURN_VALUE_REGISTER_CONVENTION;
1899 /* Implement the "get_longjmp_target" gdbarch method. */
1902 nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1906 struct gdbarch *gdbarch = get_frame_arch (frame);
1907 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1909 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1911 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1914 *pc = extract_unsigned_integer (buf, 4, byte_order);
1918 /* Validate the given TDESC, and fixed-number some registers in it.
1919 Return 0 if the given TDESC does not contain the required feature
1920 or not contain required registers. */
1923 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1924 struct tdesc_arch_data *tdesc_data,
1925 int *fpu_freg, int *use_pseudo_fsrs)
1927 const struct tdesc_feature *feature;
1930 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1931 if (feature == NULL)
1935 /* Validate and fixed-number R0-R10. */
1936 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1937 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1938 nds32_register_names[i]);
1941 valid_p &= tdesc_unnumbered_register (feature,
1942 nds32_register_names[NDS32_TA_REGNUM]);
1944 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1945 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1946 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1947 nds32_register_names[i]);
1952 /* Fixed-number R11-R27. */
1953 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1954 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1956 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1957 if (feature != NULL)
1959 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1962 /* Guess FPU configuration via listed registers. */
1963 if (tdesc_unnumbered_register (feature, "fd31"))
1965 else if (tdesc_unnumbered_register (feature, "fd15"))
1967 else if (tdesc_unnumbered_register (feature, "fd7"))
1969 else if (tdesc_unnumbered_register (feature, "fd3"))
1973 /* Required FDR is not found. */
1978 /* Validate and fixed-number required FDRs. */
1979 num_fdr_regs = num_fdr_map[freg];
1980 for (i = 0; i < num_fdr_regs; i++)
1981 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1982 NDS32_FD0_REGNUM + i,
1983 nds32_fdr_register_names[i]);
1987 /* Count the number of listed FSRs, and fixed-number them if present. */
1988 num_fsr_regs = num_fsr_map[freg];
1989 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1991 for (i = 0; i < num_fsr_regs; i++)
1992 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
1994 nds32_fsr_register_names[i]);
1996 if (num_listed_fsr == 0)
1997 /* No required FSRs are listed explicitly, make them pseudo registers
1999 *use_pseudo_fsrs = 1;
2000 else if (num_listed_fsr == num_fsr_regs)
2001 /* All required FSRs are listed explicitly. */
2002 *use_pseudo_fsrs = 0;
2004 /* Some required FSRs are missing. */
2011 /* Initialize the current architecture based on INFO. If possible,
2012 re-use an architecture from ARCHES, which is a list of
2013 architectures already created during this debugging session.
2015 Called e.g. at program startup, when reading a core file, and when
2016 reading a binary file. */
2018 static struct gdbarch *
2019 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2021 struct gdbarch *gdbarch;
2022 struct gdbarch_tdep *tdep;
2023 struct gdbarch_list *best_arch;
2024 struct tdesc_arch_data *tdesc_data = NULL;
2025 const struct target_desc *tdesc = info.target_desc;
2026 int elf_abi = E_NDS_ABI_AABI;
2028 int use_pseudo_fsrs = 0;
2029 int i, num_regs, maxregs;
2031 /* Extract the elf_flags if available. */
2032 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2033 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
2035 /* If there is already a candidate, use it. */
2036 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2038 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2040 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2042 if (idep->elf_abi != elf_abi)
2045 /* Found a match. */
2049 if (best_arch != NULL)
2050 return best_arch->gdbarch;
2052 if (!tdesc_has_registers (tdesc))
2053 tdesc = tdesc_nds32;
2055 tdesc_data = tdesc_data_alloc ();
2057 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2059 tdesc_data_cleanup (tdesc_data);
2063 /* Allocate space for the new architecture. */
2064 tdep = XCNEW (struct gdbarch_tdep);
2065 tdep->fpu_freg = fpu_freg;
2066 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2067 tdep->fs0_regnum = -1;
2068 tdep->elf_abi = elf_abi;
2070 gdbarch = gdbarch_alloc (&info, tdep);
2073 num_regs = NDS32_NUM_REGS;
2074 else if (use_pseudo_fsrs == 1)
2076 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2077 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2078 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2079 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2080 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2082 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2085 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2087 set_gdbarch_num_regs (gdbarch, num_regs);
2088 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2090 /* Cache the register number of fs0. */
2092 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2094 /* Add NDS32 register aliases. To avoid search in user register name space,
2095 user_reg_map_name_to_regnum is not used. */
2096 maxregs = (gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch));
2097 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2102 /* Search register name space. */
2103 for (j = 0; j < maxregs; j++)
2105 const char *regname = gdbarch_register_name (gdbarch, j);
2108 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2115 /* Try next alias entry if the given name can not be found in register
2120 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2121 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2124 nds32_add_reggroups (gdbarch);
2126 /* Hook in ABI-specific overrides, if they have been registered. */
2127 info.tdep_info = (void *) tdesc_data;
2128 gdbarch_init_osabi (info, gdbarch);
2130 /* Override tdesc_register callbacks for system registers. */
2131 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2133 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2134 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2135 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2136 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2137 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2138 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2140 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2141 set_gdbarch_return_value (gdbarch, nds32_return_value);
2142 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2144 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2145 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2146 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2147 nds32_breakpoint::kind_from_pc);
2148 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2149 nds32_breakpoint::bp_from_kind);
2151 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2152 frame_base_set_default (gdbarch, &nds32_frame_base);
2154 set_gdbarch_print_insn (gdbarch, print_insn_nds32);
2156 /* Handle longjmp. */
2157 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2159 /* The order of appending is the order it check frame. */
2160 dwarf2_append_unwinders (gdbarch);
2161 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2162 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2168 _initialize_nds32_tdep (void)
2170 /* Initialize gdbarch. */
2171 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2173 initialize_tdesc_nds32 ();
2174 nds32_init_reggroups ();