1 /* Target-dependent code for the NDS32 architecture, for GDB.
3 Copyright (C) 2013-2018 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
29 #include "reggroups.h"
32 #include "arch-utils.h"
35 #include "user-regs.h"
37 #include "dwarf2-frame.h"
39 #include "target-descriptions.h"
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
46 #include "features/nds32.c"
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
58 /* Use an invalid address value as 'not available' marker. */
59 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
61 /* Use an impossible value as invalid offset. */
62 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
64 /* Instruction groups for NDS32 epilogue analysis. */
67 /* Instructions used everywhere, not only in epilogue. */
69 /* Instructions used to reset sp for local vars, arguments, etc. */
71 /* Instructions used to recover saved regs and to recover padding. */
73 /* Instructions used to return to the caller. */
75 /* Instructions used to recover saved regs and to return to the caller. */
79 static const char *const nds32_register_names[] =
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
85 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
90 static const char *const nds32_fdr_register_names[] =
92 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
93 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
94 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
95 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
98 static const char *const nds32_fsr_register_names[] =
100 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
101 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
102 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
103 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
106 /* The number of registers for four FPU configuration options. */
107 const int num_fdr_map[] = { 4, 8, 16, 32 };
108 const int num_fsr_map[] = { 8, 16, 32, 32 };
110 /* Aliases for registers. */
115 } nds32_register_aliases[] =
131 {"cr6", "fucop_exist"},
148 {"ir14", "int_mask"},
149 {"ir15", "int_pend"},
153 {"ir19", "int_ctrl"},
155 {"ir21", "sp_priv1"},
157 {"ir23", "sp_priv2"},
159 {"ir25", "sp_priv3"},
160 {"ir26", "int_mask2"},
161 {"ir27", "int_pend2"},
162 {"ir28", "int_pri2"},
163 {"ir29", "int_trigger"},
173 {"mr8", "cache_ctl"},
174 {"mr9", "hsmp_saddr"},
175 {"mr10", "hsmp_eaddr"},
176 {"mr11", "bg_region"},
227 {"hspr0", "hsp_ctl"},
228 {"hspr1", "sp_bound"},
229 {"hspr2", "sp_bound_priv"},
237 {"dmar0", "dma_cfg"},
238 {"dmar1", "dma_gcsw"},
239 {"dmar2", "dma_chnsel"},
240 {"dmar3", "dma_act"},
241 {"dmar4", "dma_setup"},
242 {"dmar5", "dma_isaddr"},
243 {"dmar6", "dma_esaddr"},
244 {"dmar7", "dma_tcnt"},
245 {"dmar8", "dma_status"},
246 {"dmar9", "dma_2dset"},
247 {"dmar10", "dma_2dsctl"},
248 {"dmar11", "dma_rcnt"},
249 {"dmar12", "dma_hstatus"},
251 {"racr0", "prusr_acc_ctl"},
252 {"fucpr", "fucop_ctl"},
255 {"idr1", "misc_ctl"},
256 {"idr2", "ecc_misc"},
261 {"secur3", "p_isign"},
264 /* Value of a register alias. BATON is the regnum of the corresponding
267 static struct value *
268 value_of_nds32_reg (struct frame_info *frame, const void *baton)
270 return value_of_register ((int) (intptr_t) baton, frame);
273 /* Implement the "frame_align" gdbarch method. */
276 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
278 /* 8-byte aligned. */
279 return align_down (sp, 8);
282 /* The same insn machine code is used for little-endian and big-endian. */
283 constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
285 typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
287 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
290 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
292 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
294 const int FDR = FSR + 32;
296 if (num >= 0 && num < 32)
298 /* General-purpose registers (R0 - R31). */
301 else if (num >= FSR && num < FSR + 32)
303 /* Single precision floating-point registers (FS0 - FS31). */
304 return num - FSR + tdep->fs0_regnum;
306 else if (num >= FDR && num < FDR + 32)
308 /* Double precision floating-point registers (FD0 - FD31). */
309 return num - FDR + NDS32_FD0_REGNUM;
312 /* No match, return a inaccessible register number. */
316 /* NDS32 register groups. */
317 static struct reggroup *nds32_cr_reggroup;
318 static struct reggroup *nds32_ir_reggroup;
319 static struct reggroup *nds32_mr_reggroup;
320 static struct reggroup *nds32_dr_reggroup;
321 static struct reggroup *nds32_pfr_reggroup;
322 static struct reggroup *nds32_hspr_reggroup;
323 static struct reggroup *nds32_dmar_reggroup;
324 static struct reggroup *nds32_racr_reggroup;
325 static struct reggroup *nds32_idr_reggroup;
326 static struct reggroup *nds32_secur_reggroup;
329 nds32_init_reggroups (void)
331 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
332 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
333 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
334 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
335 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
336 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
337 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
338 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
339 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
340 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
344 nds32_add_reggroups (struct gdbarch *gdbarch)
346 /* Add pre-defined register groups. */
347 reggroup_add (gdbarch, general_reggroup);
348 reggroup_add (gdbarch, float_reggroup);
349 reggroup_add (gdbarch, system_reggroup);
350 reggroup_add (gdbarch, all_reggroup);
351 reggroup_add (gdbarch, save_reggroup);
352 reggroup_add (gdbarch, restore_reggroup);
354 /* Add NDS32 register groups. */
355 reggroup_add (gdbarch, nds32_cr_reggroup);
356 reggroup_add (gdbarch, nds32_ir_reggroup);
357 reggroup_add (gdbarch, nds32_mr_reggroup);
358 reggroup_add (gdbarch, nds32_dr_reggroup);
359 reggroup_add (gdbarch, nds32_pfr_reggroup);
360 reggroup_add (gdbarch, nds32_hspr_reggroup);
361 reggroup_add (gdbarch, nds32_dmar_reggroup);
362 reggroup_add (gdbarch, nds32_racr_reggroup);
363 reggroup_add (gdbarch, nds32_idr_reggroup);
364 reggroup_add (gdbarch, nds32_secur_reggroup);
367 /* Implement the "register_reggroup_p" gdbarch method. */
370 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
371 struct reggroup *reggroup)
373 const char *reg_name;
374 const char *group_name;
377 if (reggroup == all_reggroup)
380 /* General reggroup contains only GPRs and PC. */
381 if (reggroup == general_reggroup)
382 return regnum <= NDS32_PC_REGNUM;
384 if (reggroup == float_reggroup || reggroup == save_reggroup
385 || reggroup == restore_reggroup)
387 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
391 return default_register_reggroup_p (gdbarch, regnum, reggroup);
394 if (reggroup == system_reggroup)
395 return (regnum > NDS32_PC_REGNUM)
396 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
398 /* The NDS32 reggroup contains registers whose name is prefixed
400 reg_name = gdbarch_register_name (gdbarch, regnum);
401 group_name = reggroup_name (reggroup);
402 return !strncmp (reg_name, group_name, strlen (group_name));
405 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
408 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
410 regnum -= gdbarch_num_regs (gdbarch);
412 /* Currently, only FSRs could be defined as pseudo registers. */
413 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
414 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
415 floatformats_ieee_single);
417 warning (_("Unknown nds32 pseudo register %d."), regnum);
421 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
424 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
426 regnum -= gdbarch_num_regs (gdbarch);
428 /* Currently, only FSRs could be defined as pseudo registers. */
429 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
430 return nds32_fsr_register_names[regnum];
432 warning (_("Unknown nds32 pseudo register %d."), regnum);
436 /* Implement the "pseudo_register_read" gdbarch method. */
438 static enum register_status
439 nds32_pseudo_register_read (struct gdbarch *gdbarch,
440 readable_regcache *regcache, int regnum,
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
445 int offset, fdr_regnum;
446 enum register_status status;
448 /* This function is registered in nds32_gdbarch_init only after these are
450 gdb_assert (tdep->fpu_freg != -1);
451 gdb_assert (tdep->use_pseudo_fsrs != 0);
453 regnum -= gdbarch_num_regs (gdbarch);
455 /* Currently, only FSRs could be defined as pseudo registers. */
456 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
458 /* fs0 is always the most significant half of fd0. */
459 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
460 offset = (regnum & 1) ? 4 : 0;
462 offset = (regnum & 1) ? 0 : 4;
464 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
465 status = regcache->raw_read (fdr_regnum, reg_buf);
466 if (status == REG_VALID)
467 memcpy (buf, reg_buf + offset, 4);
472 gdb_assert_not_reached ("invalid pseudo register number");
475 /* Implement the "pseudo_register_write" gdbarch method. */
478 nds32_pseudo_register_write (struct gdbarch *gdbarch,
479 struct regcache *regcache, int regnum,
482 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
484 int offset, fdr_regnum;
486 /* This function is registered in nds32_gdbarch_init only after these are
488 gdb_assert (tdep->fpu_freg != -1);
489 gdb_assert (tdep->use_pseudo_fsrs != 0);
491 regnum -= gdbarch_num_regs (gdbarch);
493 /* Currently, only FSRs could be defined as pseudo registers. */
494 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
496 /* fs0 is always the most significant half of fd0. */
497 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
498 offset = (regnum & 1) ? 4 : 0;
500 offset = (regnum & 1) ? 0 : 4;
502 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
503 regcache->raw_read (fdr_regnum, reg_buf);
504 memcpy (reg_buf + offset, buf, 4);
505 regcache->raw_write (fdr_regnum, reg_buf);
509 gdb_assert_not_reached ("invalid pseudo register number");
512 /* Helper function for NDS32 ABI. Return true if FPRs can be used
513 to pass function arguments and return value. */
516 nds32_abi_use_fpr (int elf_abi)
518 return elf_abi == E_NDS_ABI_V2FP_PLUS;
521 /* Helper function for NDS32 ABI. Return true if GPRs and stack
522 can be used together to pass an argument. */
525 nds32_abi_split (int elf_abi)
527 return elf_abi == E_NDS_ABI_AABI;
530 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
532 struct nds32_frame_cache
534 /* The previous frame's inner most stack address. Used as this
535 frame ID's stack_addr. */
538 /* The frame's base, optionally used by the high-level debug info. */
541 /* During prologue analysis, keep how far the SP and FP have been offset
542 from the start of the stack frame (as defined by the previous frame's
544 During epilogue analysis, keep how far the SP has been offset from the
545 current stack pointer. */
549 /* The address of the first instruction in this function. */
552 /* Saved registers. */
553 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
556 /* Allocate and initialize a frame cache. */
558 static struct nds32_frame_cache *
559 nds32_alloc_frame_cache (void)
561 struct nds32_frame_cache *cache;
564 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
566 /* Initialize fp_offset to check if FP is set in prologue. */
567 cache->fp_offset = INVALID_OFFSET;
569 /* Saved registers. We initialize these to -1 since zero is a valid
571 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
572 cache->saved_regs[i] = REG_UNAVAIL;
577 /* Helper function for instructions used to push multiple words. */
580 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
583 CORE_ADDR sp_offset = cache->sp_offset;
586 /* Check LP, GP, FP in enable4. */
587 for (i = 1; i <= 3; i++)
589 if ((enable4 >> i) & 0x1)
592 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
596 /* Skip case where re == rb == sp. */
597 if ((rb < REG_FP) && (re < REG_FP))
599 for (i = re; i >= rb; i--)
602 cache->saved_regs[i] = sp_offset;
606 /* For sp, update the offset. */
607 cache->sp_offset = sp_offset;
610 /* Analyze the instructions within the given address range. If CACHE
611 is non-NULL, fill it in. Return the first address beyond the given
612 address range. If CACHE is NULL, return the first address not
613 recognized as a prologue instruction. */
616 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
617 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
619 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
620 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
621 /* Current scanning status. */
622 int in_prologue_bb = 0;
624 uint32_t insn, insn_len;
626 for (; pc < limit_pc; pc += insn_len)
628 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
630 if ((insn & 0x80000000) == 0)
632 /* 32-bit instruction */
635 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
637 /* addi $sp, $sp, imm15s */
638 int imm15s = N32_IMM15S (insn);
643 cache->sp_offset += -imm15s;
649 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
651 /* addi $fp, $sp, imm15s */
652 int imm15s = N32_IMM15S (insn);
657 cache->fp_offset = cache->sp_offset - imm15s;
663 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
664 && N32_RA5 (insn) == REG_SP)
666 /* smw.adm Rb, [$sp], Re, enable4 */
668 nds32_push_multiple_words (cache, N32_RT5 (insn),
670 N32_LSMW_ENABLE4 (insn));
674 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
675 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
677 /* add $sp, $sp, $ta */
678 /* add $sp, $ta, $sp */
682 cache->sp_offset += -val_ta;
688 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
690 /* movi $ta, imm20s */
692 val_ta = N32_IMM20S (insn);
696 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
698 /* sethi $ta, imm20u */
700 val_ta = N32_IMM20U (insn) << 12;
704 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
706 /* ori $ta, $ta, imm15u */
708 val_ta |= N32_IMM15U (insn);
712 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
714 /* addi $ta, $ta, imm15s */
716 val_ta += N32_IMM15S (insn);
720 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
721 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
723 /* add $gp, $ta, $gp */
724 /* add $gp, $gp, $ta */
728 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
730 /* movi $gp, imm20s */
734 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
736 /* sethi $gp, imm20u */
740 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
742 /* ori $gp, $gp, imm15u */
748 /* Jump/Branch insns never appear in prologue basic block.
749 The loop can be escaped early when these insns are met. */
750 if (in_prologue_bb == 1)
752 int op = N32_OP6 (insn);
755 || op == N32_OP6_JREG
758 || op == N32_OP6_BR3)
763 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
764 && __GF (insn, 12, 3) == 0)
766 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
767 normal form (bit [12] == 0) is used. */
769 /* fsdi FDt, [$sp + (imm12s << 2)] */
770 if (N32_RA5 (insn) == REG_SP)
774 /* The optimizer might shove anything into the prologue, if
775 we build up cache (cache != NULL) from analyzing prologue,
776 we just skip what we don't recognize and analyze further to
777 make cache as complete as possible. However, if we skip
778 prologue, we'll stop immediately on unrecognized
785 /* 16-bit instruction */
790 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
793 int imm10s = N16_IMM10S (insn);
798 cache->sp_offset += -imm10s;
804 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
809 int imm8u = (insn & 0x1f) << 3;
810 int re = (insn >> 5) & 0x3;
811 const int reg_map[] = { 6, 8, 10, 14 };
813 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
814 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
816 /* Operation 2 -- sp = sp - (imm5u << 3) */
817 cache->sp_offset += imm8u;
823 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
829 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
831 /* movi55 $gp, imm5s */
837 /* Jump/Branch insns never appear in prologue basic block.
838 The loop can be escaped early when these insns are met. */
839 if (in_prologue_bb == 1)
841 uint32_t insn5 = CHOP_BITS (insn, 5);
842 uint32_t insn8 = CHOP_BITS (insn, 8);
843 uint32_t insn38 = CHOP_BITS (insn, 11);
845 if (insn5 == N16_TYPE5 (JR5, 0)
846 || insn5 == N16_TYPE5 (JRAL5, 0)
847 || insn5 == N16_TYPE5 (RET5, 0)
848 || insn8 == N16_TYPE8 (J8, 0)
849 || insn8 == N16_TYPE8 (BEQZS8, 0)
850 || insn8 == N16_TYPE8 (BNEZS8, 0)
851 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
852 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
853 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
854 || insn38 == N16_TYPE38 (BNES38, 0, 0))
859 /* The optimizer might shove anything into the prologue, if
860 we build up cache (cache != NULL) from analyzing prologue,
861 we just skip what we don't recognize and analyze further to
862 make cache as complete as possible. However, if we skip
863 prologue, we'll stop immediately on unrecognized
873 /* Implement the "skip_prologue" gdbarch method.
875 Find the end of function prologue. */
878 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
880 CORE_ADDR func_addr, limit_pc;
882 /* See if we can determine the end of the prologue via the symbol table.
883 If so, then return either PC, or the PC after the prologue, whichever
885 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
887 CORE_ADDR post_prologue_pc
888 = skip_prologue_using_sal (gdbarch, func_addr);
889 if (post_prologue_pc != 0)
890 return std::max (pc, post_prologue_pc);
893 /* Can't determine prologue from the symbol table, need to examine
896 /* Find an upper limit on the function prologue using the debug
897 information. If the debug information could not be used to provide
898 that bound, then use an arbitrary large number as the upper bound. */
899 limit_pc = skip_prologue_using_sal (gdbarch, pc);
901 limit_pc = pc + 128; /* Magic. */
903 /* Find the end of prologue. */
904 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
907 /* Allocate and fill in *THIS_CACHE with information about the prologue of
908 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
909 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
911 static struct nds32_frame_cache *
912 nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
914 struct gdbarch *gdbarch = get_frame_arch (this_frame);
915 struct nds32_frame_cache *cache;
916 CORE_ADDR current_pc;
922 return (struct nds32_frame_cache *) *this_cache;
924 cache = nds32_alloc_frame_cache ();
927 cache->pc = get_frame_func (this_frame);
928 current_pc = get_frame_pc (this_frame);
929 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
931 /* Compute the previous frame's stack pointer (which is also the
932 frame's ID's stack address), and this frame's base pointer. */
933 if (cache->fp_offset != INVALID_OFFSET)
935 /* FP is set in prologue, so it can be used to calculate other info. */
936 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
937 prev_sp = this_base + cache->fp_offset;
941 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
942 prev_sp = this_base + cache->sp_offset;
945 cache->prev_sp = prev_sp;
946 cache->base = this_base;
948 /* Adjust all the saved registers such that they contain addresses
949 instead of offsets. */
950 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
951 if (cache->saved_regs[i] != REG_UNAVAIL)
952 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
957 /* Implement the "this_id" frame_unwind method.
959 Our frame ID for a normal frame is the current function's starting
960 PC and the caller's SP when we were called. */
963 nds32_frame_this_id (struct frame_info *this_frame,
964 void **this_cache, struct frame_id *this_id)
966 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
968 /* This marks the outermost frame. */
969 if (cache->prev_sp == 0)
972 *this_id = frame_id_build (cache->prev_sp, cache->pc);
975 /* Implement the "prev_register" frame_unwind method. */
977 static struct value *
978 nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
981 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
983 if (regnum == NDS32_SP_REGNUM)
984 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
986 /* The PC of the previous frame is stored in the LP register of
987 the current frame. */
988 if (regnum == NDS32_PC_REGNUM)
989 regnum = NDS32_LP_REGNUM;
991 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
992 return frame_unwind_got_memory (this_frame, regnum,
993 cache->saved_regs[regnum]);
995 return frame_unwind_got_register (this_frame, regnum, regnum);
998 static const struct frame_unwind nds32_frame_unwind =
1001 default_frame_unwind_stop_reason,
1002 nds32_frame_this_id,
1003 nds32_frame_prev_register,
1005 default_frame_sniffer,
1008 /* Return the frame base address of *THIS_FRAME. */
1011 nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1013 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1018 static const struct frame_base nds32_frame_base =
1020 &nds32_frame_unwind,
1021 nds32_frame_base_address,
1022 nds32_frame_base_address,
1023 nds32_frame_base_address
1026 /* Helper function for instructions used to pop multiple words. */
1029 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1032 CORE_ADDR sp_offset = cache->sp_offset;
1035 /* Skip case where re == rb == sp. */
1036 if ((rb < REG_FP) && (re < REG_FP))
1038 for (i = rb; i <= re; i++)
1040 cache->saved_regs[i] = sp_offset;
1045 /* Check FP, GP, LP in enable4. */
1046 for (i = 3; i >= 1; i--)
1048 if ((enable4 >> i) & 0x1)
1050 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1055 /* For sp, update the offset. */
1056 cache->sp_offset = sp_offset;
1059 /* The instruction sequences in NDS32 epilogue are
1061 INSN_RESET_SP (optional)
1062 (If exists, this must be the first instruction in epilogue
1063 and the stack has not been destroyed.).
1064 INSN_RECOVER (optional).
1065 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1067 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1068 the necessary information will be recorded. */
1071 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1072 struct nds32_frame_cache *cache)
1074 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1075 && N32_IMM15S (insn) > 0)
1076 /* addi $sp, $sp, imm15s */
1077 return INSN_RESET_SP;
1078 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1079 && N32_IMM15S (insn) < 0)
1080 /* addi $sp, $fp, imm15s */
1081 return INSN_RESET_SP;
1082 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1083 && N32_RA5 (insn) == REG_SP)
1085 /* lmw.bim Rb, [$sp], Re, enable4 */
1087 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1088 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1090 return INSN_RECOVER;
1092 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1095 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1096 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1097 /* add $sp, $sp, $ta */
1098 /* add $sp, $ta, $sp */
1099 return INSN_RESET_SP;
1100 else if (abi_use_fpr
1101 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1103 if (__GF (insn, 12, 1) == 0)
1104 /* fldi FDt, [$sp + (imm12s << 2)] */
1105 return INSN_RECOVER;
1108 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1109 int offset = N32_IMM12S (insn) << 2;
1111 if (offset == 8 || offset == 12)
1114 cache->sp_offset += offset;
1116 return INSN_RECOVER;
1124 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1125 the necessary information will be recorded. */
1128 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1130 if (insn == N16_TYPE5 (RET5, REG_LP))
1133 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1136 int imm10s = N16_IMM10S (insn);
1141 cache->sp_offset += imm10s;
1143 return INSN_RECOVER;
1146 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1151 int imm8u = (insn & 0x1f) << 3;
1152 int re = (insn >> 5) & 0x3;
1153 const int reg_map[] = { 6, 8, 10, 14 };
1155 /* Operation 1 -- sp = sp + (imm5u << 3) */
1156 cache->sp_offset += imm8u;
1158 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1159 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1162 /* Operation 3 -- ret $lp */
1163 return INSN_RECOVER_RETURN;
1169 /* Analyze a reasonable amount of instructions from the given PC to find
1170 the instruction used to return to the caller. Return 1 if the 'return'
1171 instruction could be found, 0 otherwise.
1173 If CACHE is non-NULL, fill it in. */
1176 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1177 struct nds32_frame_cache *cache)
1179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1180 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1182 uint32_t insn, insn_len;
1183 int insn_type = INSN_NORMAL;
1190 for (; pc < limit_pc; pc += insn_len)
1192 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1194 if ((insn & 0x80000000) == 0)
1196 /* 32-bit instruction */
1199 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1200 if (insn_type == INSN_RETURN)
1202 else if (insn_type == INSN_RECOVER)
1207 /* 16-bit instruction */
1211 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1212 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1214 else if (insn_type == INSN_RECOVER)
1218 /* Stop the scan if this is an unexpected instruction. */
1225 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1228 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1230 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1231 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1232 int insn_type = INSN_NORMAL;
1236 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1238 if ((insn & 0x80000000) == 0)
1240 /* 32-bit instruction */
1242 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1246 /* 16-bit instruction */
1249 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1252 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1255 /* Search the required 'return' instruction within the following reasonable
1257 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1261 /* Scan backwards to make sure that the last instruction has adjusted
1262 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1263 just a heuristic, so the false positives will be acceptable. */
1264 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1266 /* Only 16-bit instructions are possible at addr - 2. */
1267 if ((insn & 0x80000000) != 0)
1269 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1271 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1272 if (insn_type == INSN_RECOVER)
1276 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1278 /* If this is a 16-bit instruction at addr - 4, then there must be another
1279 16-bit instruction at addr - 2, so only 32-bit instructions need to
1280 be analyzed here. */
1281 if ((insn & 0x80000000) == 0)
1283 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1285 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1286 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1293 /* Implement the "sniffer" frame_unwind method. */
1296 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1297 struct frame_info *this_frame, void **this_cache)
1299 if (frame_relative_level (this_frame) == 0)
1300 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1301 get_frame_pc (this_frame));
1306 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1307 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1308 allocated. Return a pointer to the current nds32_frame_cache in
1311 static struct nds32_frame_cache *
1312 nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1314 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1315 struct nds32_frame_cache *cache;
1316 CORE_ADDR current_pc, current_sp;
1320 return (struct nds32_frame_cache *) *this_cache;
1322 cache = nds32_alloc_frame_cache ();
1323 *this_cache = cache;
1325 cache->pc = get_frame_func (this_frame);
1326 current_pc = get_frame_pc (this_frame);
1327 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1329 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1330 cache->prev_sp = current_sp + cache->sp_offset;
1332 /* Adjust all the saved registers such that they contain addresses
1333 instead of offsets. */
1334 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1335 if (cache->saved_regs[i] != REG_UNAVAIL)
1336 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1341 /* Implement the "this_id" frame_unwind method. */
1344 nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1345 void **this_cache, struct frame_id *this_id)
1347 struct nds32_frame_cache *cache
1348 = nds32_epilogue_frame_cache (this_frame, this_cache);
1350 /* This marks the outermost frame. */
1351 if (cache->prev_sp == 0)
1354 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1357 /* Implement the "prev_register" frame_unwind method. */
1359 static struct value *
1360 nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1361 void **this_cache, int regnum)
1363 struct nds32_frame_cache *cache
1364 = nds32_epilogue_frame_cache (this_frame, this_cache);
1366 if (regnum == NDS32_SP_REGNUM)
1367 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1369 /* The PC of the previous frame is stored in the LP register of
1370 the current frame. */
1371 if (regnum == NDS32_PC_REGNUM)
1372 regnum = NDS32_LP_REGNUM;
1374 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1375 return frame_unwind_got_memory (this_frame, regnum,
1376 cache->saved_regs[regnum]);
1378 return frame_unwind_got_register (this_frame, regnum, regnum);
1381 static const struct frame_unwind nds32_epilogue_frame_unwind =
1384 default_frame_unwind_stop_reason,
1385 nds32_epilogue_frame_this_id,
1386 nds32_epilogue_frame_prev_register,
1388 nds32_epilogue_frame_sniffer
1391 /* Implement the "dummy_id" gdbarch method. */
1393 static struct frame_id
1394 nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1396 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1398 return frame_id_build (sp, get_frame_pc (this_frame));
1401 /* Implement the "unwind_pc" gdbarch method. */
1404 nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1406 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1409 /* Implement the "unwind_sp" gdbarch method. */
1412 nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1414 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1417 /* Floating type and struct type that has only one floating type member
1418 can pass value using FPU registers (when FPU ABI is used). */
1421 nds32_check_calling_use_fpr (struct type *type)
1424 enum type_code typecode;
1429 t = check_typedef (t);
1430 typecode = TYPE_CODE (t);
1431 if (typecode != TYPE_CODE_STRUCT)
1433 else if (TYPE_NFIELDS (t) != 1)
1436 t = TYPE_FIELD_TYPE (t, 0);
1439 return typecode == TYPE_CODE_FLT;
1442 /* Return the alignment (in bytes) of the given type. */
1445 nds32_type_align (struct type *type)
1451 type = check_typedef (type);
1452 switch (TYPE_CODE (type))
1455 /* Should never happen. */
1456 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1460 case TYPE_CODE_ENUM:
1464 case TYPE_CODE_RANGE:
1466 case TYPE_CODE_CHAR:
1467 case TYPE_CODE_BOOL:
1468 return TYPE_LENGTH (type);
1470 case TYPE_CODE_ARRAY:
1471 case TYPE_CODE_COMPLEX:
1472 return nds32_type_align (TYPE_TARGET_TYPE (type));
1474 case TYPE_CODE_STRUCT:
1475 case TYPE_CODE_UNION:
1477 for (n = 0; n < TYPE_NFIELDS (type); n++)
1479 falign = nds32_type_align (TYPE_FIELD_TYPE (type, n));
1487 /* Implement the "push_dummy_call" gdbarch method. */
1490 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1491 struct regcache *regcache, CORE_ADDR bp_addr,
1492 int nargs, struct value **args, CORE_ADDR sp,
1493 int struct_return, CORE_ADDR struct_addr)
1495 const int REND = 6; /* End for register offset. */
1496 int goff = 0; /* Current gpr offset for argument. */
1497 int foff = 0; /* Current fpr offset for argument. */
1498 int soff = 0; /* Current stack offset for argument. */
1501 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1502 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1503 struct type *func_type = value_type (function);
1504 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1505 int abi_split = nds32_abi_split (tdep->elf_abi);
1507 /* Set the return address. For the NDS32, the return breakpoint is
1508 always at BP_ADDR. */
1509 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1511 /* If STRUCT_RETURN is true, then the struct return address (in
1512 STRUCT_ADDR) will consume the first argument-passing register.
1513 Both adjust the register count and store that value. */
1516 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1520 /* Now make sure there's space on the stack */
1521 for (i = 0; i < nargs; i++)
1523 struct type *type = value_type (args[i]);
1524 int align = nds32_type_align (type);
1526 /* If align is zero, it may be an empty struct.
1527 Just ignore the argument of empty struct. */
1531 sp -= TYPE_LENGTH (type);
1532 sp = align_down (sp, align);
1535 /* Stack must be 8-byte aligned. */
1536 sp = align_down (sp, 8);
1539 for (i = 0; i < nargs; i++)
1541 const gdb_byte *val;
1544 int calling_use_fpr;
1547 type = value_type (args[i]);
1548 calling_use_fpr = nds32_check_calling_use_fpr (type);
1549 len = TYPE_LENGTH (type);
1550 align = nds32_type_align (type);
1551 val = value_contents (args[i]);
1553 /* The size of a composite type larger than 4 bytes will be rounded
1554 up to the nearest multiple of 4. */
1556 len = align_up (len, 4);
1558 /* Variadic functions are handled differently between AABI and ABI2FP+.
1560 For AABI, the caller pushes arguments in registers, callee stores
1561 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1562 Therefore, we don't have to handle variadic functions specially.
1564 For ABI2FP+, the caller pushes only named arguments in registers
1565 and pushes all unnamed arguments in stack. */
1567 if (abi_use_fpr && TYPE_VARARGS (func_type)
1568 && i >= TYPE_NFIELDS (func_type))
1571 /* Try to use FPRs to pass arguments only when
1572 1. The program is built using toolchain with FPU support.
1573 2. The type of this argument can use FPR to pass value. */
1574 use_fpr = abi_use_fpr && calling_use_fpr;
1578 if (tdep->fpu_freg == -1)
1581 /* Adjust alignment. */
1582 if ((align >> 2) > 0)
1583 foff = align_up (foff, align >> 2);
1590 regcache->cooked_write (tdep->fs0_regnum + foff, val);
1594 regcache->cooked_write (NDS32_FD0_REGNUM + (foff >> 1), val);
1599 internal_error (__FILE__, __LINE__,
1600 "Do not know how to handle %d-byte double.\n",
1610 When passing arguments using GPRs,
1612 * A composite type not larger than 4 bytes is passed in $rN.
1613 The format is as if the value is loaded with load instruction
1614 of corresponding size (e.g., LB, LH, LW).
1623 * Otherwise, a composite type is passed in consecutive registers.
1624 The size is rounded up to the nearest multiple of 4.
1625 The successive registers hold the parts of the argument as if
1626 were loaded using lmw instructions.
1632 LITTLE: [d c b a] [x x x e]
1633 BIG: [a b c d] [e x x x]
1636 /* Adjust alignment. */
1637 if ((align >> 2) > 0)
1638 goff = align_up (goff, align >> 2);
1640 if (len <= (REND - goff) * 4)
1642 /* This argument can be passed wholly via GPRs. */
1645 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1647 regcache_cooked_write_unsigned (regcache,
1648 NDS32_R0_REGNUM + goff,
1658 /* Some parts of this argument can be passed via GPRs. */
1661 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1663 regcache_cooked_write_unsigned (regcache,
1664 NDS32_R0_REGNUM + goff,
1675 When pushing (split parts of) an argument into stack,
1677 * A composite type not larger than 4 bytes is copied to different
1679 In little-endian, the first byte of this argument is aligned
1680 at the low address of the next free word.
1681 In big-endian, the last byte of this argument is aligned
1682 at the high address of the next free word.
1693 /* Adjust alignment. */
1694 soff = align_up (soff, align);
1698 int rlen = (len > 4) ? 4 : len;
1700 if (byte_order == BFD_ENDIAN_BIG)
1701 write_memory (sp + soff + 4 - rlen, val, rlen);
1703 write_memory (sp + soff, val, rlen);
1711 /* Finally, update the SP register. */
1712 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1717 /* If use_fpr, but no floating-point register exists,
1718 then it is an error. */
1719 error (_("Fail to call. FPU registers are required."));
1722 /* Read, for architecture GDBARCH, a function return value of TYPE
1723 from REGCACHE, and copy that into VALBUF. */
1726 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1727 struct regcache *regcache, gdb_byte *valbuf)
1729 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1730 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1731 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1732 int calling_use_fpr;
1735 calling_use_fpr = nds32_check_calling_use_fpr (type);
1736 len = TYPE_LENGTH (type);
1738 if (abi_use_fpr && calling_use_fpr)
1741 regcache->cooked_read (tdep->fs0_regnum, valbuf);
1743 regcache->cooked_read (NDS32_FD0_REGNUM, valbuf);
1745 internal_error (__FILE__, __LINE__,
1746 _("Cannot extract return value of %d bytes "
1747 "long floating-point."), len);
1752 When returning result,
1754 * A composite type not larger than 4 bytes is returned in $r0.
1755 The format is as if the result is loaded with load instruction
1756 of corresponding size (e.g., LB, LH, LW).
1765 * Otherwise, a composite type not larger than 8 bytes is returned
1767 In little-endian, the first word is loaded in $r0.
1768 In big-endian, the last word is loaded in $r1.
1774 LITTLE: [d c b a] [x x x e]
1775 BIG: [x x x a] [b c d e]
1782 /* By using store_unsigned_integer we avoid having to do
1783 anything special for small big-endian values. */
1784 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1785 store_unsigned_integer (valbuf, len, byte_order, tmp);
1789 regcache->cooked_read (NDS32_R0_REGNUM, valbuf);
1795 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1798 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1799 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1801 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1802 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1806 regcache->cooked_read (NDS32_R0_REGNUM, valbuf);
1807 regcache->cooked_read (NDS32_R0_REGNUM + 1, valbuf + 4);
1812 /* Write, for architecture GDBARCH, a function return value of TYPE
1813 from VALBUF into REGCACHE. */
1816 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1817 struct regcache *regcache, const gdb_byte *valbuf)
1819 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1820 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1821 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1822 int calling_use_fpr;
1825 calling_use_fpr = nds32_check_calling_use_fpr (type);
1826 len = TYPE_LENGTH (type);
1828 if (abi_use_fpr && calling_use_fpr)
1831 regcache->cooked_write (tdep->fs0_regnum, valbuf);
1833 regcache->cooked_write (NDS32_FD0_REGNUM, valbuf);
1835 internal_error (__FILE__, __LINE__,
1836 _("Cannot store return value of %d bytes "
1837 "long floating-point."), len);
1845 regval = extract_unsigned_integer (valbuf, len, byte_order);
1846 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1850 regcache->cooked_write (NDS32_R0_REGNUM, valbuf);
1856 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1859 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1860 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1862 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1863 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1868 regcache->cooked_write (NDS32_R0_REGNUM, valbuf);
1869 regcache->cooked_write (NDS32_R0_REGNUM + 1, valbuf + 4);
1874 /* Implement the "return_value" gdbarch method.
1876 Determine, for architecture GDBARCH, how a return value of TYPE
1877 should be returned. If it is supposed to be returned in registers,
1878 and READBUF is non-zero, read the appropriate value from REGCACHE,
1879 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1880 from WRITEBUF into REGCACHE. */
1882 static enum return_value_convention
1883 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1884 struct type *type, struct regcache *regcache,
1885 gdb_byte *readbuf, const gdb_byte *writebuf)
1887 if (TYPE_LENGTH (type) > 8)
1889 return RETURN_VALUE_STRUCT_CONVENTION;
1893 if (readbuf != NULL)
1894 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1895 if (writebuf != NULL)
1896 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1898 return RETURN_VALUE_REGISTER_CONVENTION;
1902 /* Implement the "get_longjmp_target" gdbarch method. */
1905 nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1909 struct gdbarch *gdbarch = get_frame_arch (frame);
1910 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1912 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1914 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1917 *pc = extract_unsigned_integer (buf, 4, byte_order);
1921 /* Validate the given TDESC, and fixed-number some registers in it.
1922 Return 0 if the given TDESC does not contain the required feature
1923 or not contain required registers. */
1926 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1927 struct tdesc_arch_data *tdesc_data,
1928 int *fpu_freg, int *use_pseudo_fsrs)
1930 const struct tdesc_feature *feature;
1933 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1934 if (feature == NULL)
1938 /* Validate and fixed-number R0-R10. */
1939 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1940 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1941 nds32_register_names[i]);
1944 valid_p &= tdesc_unnumbered_register (feature,
1945 nds32_register_names[NDS32_TA_REGNUM]);
1947 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1948 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1949 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1950 nds32_register_names[i]);
1955 /* Fixed-number R11-R27. */
1956 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1957 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1959 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1960 if (feature != NULL)
1962 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1965 /* Guess FPU configuration via listed registers. */
1966 if (tdesc_unnumbered_register (feature, "fd31"))
1968 else if (tdesc_unnumbered_register (feature, "fd15"))
1970 else if (tdesc_unnumbered_register (feature, "fd7"))
1972 else if (tdesc_unnumbered_register (feature, "fd3"))
1976 /* Required FDR is not found. */
1981 /* Validate and fixed-number required FDRs. */
1982 num_fdr_regs = num_fdr_map[freg];
1983 for (i = 0; i < num_fdr_regs; i++)
1984 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1985 NDS32_FD0_REGNUM + i,
1986 nds32_fdr_register_names[i]);
1990 /* Count the number of listed FSRs, and fixed-number them if present. */
1991 num_fsr_regs = num_fsr_map[freg];
1992 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1994 for (i = 0; i < num_fsr_regs; i++)
1995 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
1997 nds32_fsr_register_names[i]);
1999 if (num_listed_fsr == 0)
2000 /* No required FSRs are listed explicitly, make them pseudo registers
2002 *use_pseudo_fsrs = 1;
2003 else if (num_listed_fsr == num_fsr_regs)
2004 /* All required FSRs are listed explicitly. */
2005 *use_pseudo_fsrs = 0;
2007 /* Some required FSRs are missing. */
2014 /* Initialize the current architecture based on INFO. If possible,
2015 re-use an architecture from ARCHES, which is a list of
2016 architectures already created during this debugging session.
2018 Called e.g. at program startup, when reading a core file, and when
2019 reading a binary file. */
2021 static struct gdbarch *
2022 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2024 struct gdbarch *gdbarch;
2025 struct gdbarch_tdep *tdep;
2026 struct gdbarch_list *best_arch;
2027 struct tdesc_arch_data *tdesc_data = NULL;
2028 const struct target_desc *tdesc = info.target_desc;
2029 int elf_abi = E_NDS_ABI_AABI;
2031 int use_pseudo_fsrs = 0;
2032 int i, num_regs, maxregs;
2034 /* Extract the elf_flags if available. */
2035 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2036 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
2038 /* If there is already a candidate, use it. */
2039 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2041 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2043 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2045 if (idep->elf_abi != elf_abi)
2048 /* Found a match. */
2052 if (best_arch != NULL)
2053 return best_arch->gdbarch;
2055 if (!tdesc_has_registers (tdesc))
2056 tdesc = tdesc_nds32;
2058 tdesc_data = tdesc_data_alloc ();
2060 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2062 tdesc_data_cleanup (tdesc_data);
2066 /* Allocate space for the new architecture. */
2067 tdep = XCNEW (struct gdbarch_tdep);
2068 tdep->fpu_freg = fpu_freg;
2069 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2070 tdep->fs0_regnum = -1;
2071 tdep->elf_abi = elf_abi;
2073 gdbarch = gdbarch_alloc (&info, tdep);
2075 set_gdbarch_wchar_bit (gdbarch, 16);
2076 set_gdbarch_wchar_signed (gdbarch, 0);
2079 num_regs = NDS32_NUM_REGS;
2080 else if (use_pseudo_fsrs == 1)
2082 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2083 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2084 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2085 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2086 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2088 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2091 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2093 set_gdbarch_num_regs (gdbarch, num_regs);
2094 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2096 /* Cache the register number of fs0. */
2098 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2100 /* Add NDS32 register aliases. To avoid search in user register name space,
2101 user_reg_map_name_to_regnum is not used. */
2102 maxregs = gdbarch_num_cooked_regs (gdbarch);
2103 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2108 /* Search register name space. */
2109 for (j = 0; j < maxregs; j++)
2111 const char *regname = gdbarch_register_name (gdbarch, j);
2114 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2121 /* Try next alias entry if the given name can not be found in register
2126 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2127 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2130 nds32_add_reggroups (gdbarch);
2132 /* Hook in ABI-specific overrides, if they have been registered. */
2133 info.tdesc_data = tdesc_data;
2134 gdbarch_init_osabi (info, gdbarch);
2136 /* Override tdesc_register callbacks for system registers. */
2137 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2139 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2140 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2141 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2142 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2143 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2144 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2146 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2147 set_gdbarch_return_value (gdbarch, nds32_return_value);
2148 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2150 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2151 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2152 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2153 nds32_breakpoint::kind_from_pc);
2154 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2155 nds32_breakpoint::bp_from_kind);
2157 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2158 frame_base_set_default (gdbarch, &nds32_frame_base);
2160 /* Handle longjmp. */
2161 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2163 /* The order of appending is the order it check frame. */
2164 dwarf2_append_unwinders (gdbarch);
2165 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2166 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2172 _initialize_nds32_tdep (void)
2174 /* Initialize gdbarch. */
2175 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2177 initialize_tdesc_nds32 ();
2178 nds32_init_reggroups ();