1 /* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 2002-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
27 /* All the possible MIPS ABIs. */
40 /* Return the MIPS ABI associated with GDBARCH. */
41 enum mips_abi mips_abi (struct gdbarch *gdbarch);
43 /* Base and compressed MIPS ISA variations. */
46 ISA_MIPS = -1, /* mips_compression_string depends on it. */
51 /* Return the MIPS ISA's register size. Just a short cut to the BFD
52 architecture's word size. */
53 extern int mips_isa_regsize (struct gdbarch *gdbarch);
55 /* Return the current index for various MIPS registers. */
60 int fp_implementation_revision;
61 int fp_control_status;
62 int badvaddr; /* Bad vaddr for addressing exception. */
63 int cause; /* Describes last exception. */
64 int hi; /* Multiply/divide temp. */
66 int dspacc; /* SmartMIPS/DSP accumulators. */
67 int dspctl; /* DSP control. */
69 extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);
71 /* Some MIPS boards don't support floating point while others only
72 support single-precision floating-point operations. */
76 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
77 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
78 MIPS_FPU_NONE /* No floating point. */
81 /* MIPS specific per-architecture information. */
84 /* from the elf header */
88 enum mips_abi mips_abi;
89 enum mips_abi found_abi;
90 enum mips_isa mips_isa;
91 enum mips_fpu_type mips_fpu_type;
92 int mips_last_arg_regnum;
93 int mips_last_fp_arg_regnum;
94 int default_mask_address_p;
95 /* Is the target using 64-bit raw integer registers but only
96 storing a left-aligned 32-bit value in each? */
97 int mips64_transfers_32bit_regs_p;
98 /* Indexes for various registers. IRIX and embedded have
99 different values. This contains the "public" fields. Don't
100 add any that do not need to be public. */
101 const struct mips_regnum *regnum;
102 /* Register names table for the current register set. */
103 const char **mips_processor_reg_names;
105 /* The size of register data available from the target, if known.
106 This doesn't quite obsolete the manual
107 mips64_transfers_32bit_regs_p, since that is documented to force
108 left alignment even for big endian (very strange). */
109 int register_size_valid_p;
112 /* Return the expected next PC if FRAME is stopped at a syscall
114 CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
117 /* Register numbers of various important registers. */
121 MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */
123 MIPS_V0_REGNUM = 2, /* Function integer return value. */
124 MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call. */
125 MIPS_S2_REGNUM = 18, /* Contains return address in MIPS16 thunks. */
126 MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */
130 MIPS_PS_REGNUM = 32, /* Contains processor status. */
131 MIPS_EMBED_LO_REGNUM = 33,
132 MIPS_EMBED_HI_REGNUM = 34,
133 MIPS_EMBED_BADVADDR_REGNUM = 35,
134 MIPS_EMBED_CAUSE_REGNUM = 36,
135 MIPS_EMBED_PC_REGNUM = 37,
136 MIPS_EMBED_FP0_REGNUM = 38,
137 MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME. */
138 MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */
139 MIPS_PRID_REGNUM = 89, /* Processor ID. */
140 MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */
143 /* Defined in mips-tdep.c and used in remote-mips.c. */
144 extern void deprecated_mips_set_processor_regs_hack (void);
146 /* Instruction sizes and other useful constants. */
149 MIPS_INSN16_SIZE = 2,
150 MIPS_INSN32_SIZE = 4,
151 /* The number of floating-point or integer registers. */
155 /* Single step based on where the current instruction will take us. */
156 extern int mips_software_single_step (struct frame_info *frame);
158 /* Strip the ISA (compression) bit off from ADDR. */
159 extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr);
161 /* Tell if the program counter value in MEMADDR is in a standard
163 extern int mips_pc_is_mips (bfd_vma memaddr);
165 /* Tell if the program counter value in MEMADDR is in a MIPS16
167 extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, bfd_vma memaddr);
169 /* Tell if the program counter value in MEMADDR is in a microMIPS
171 extern int mips_pc_is_micromips (struct gdbarch *gdbarch, bfd_vma memaddr);
173 /* Return the currently configured (or set) saved register size. */
174 extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
176 /* Make PC the address of the next instruction to execute. */
177 extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc);
179 /* Target descriptions which only indicate the size of general
181 extern struct target_desc *mips_tdesc_gp32;
182 extern struct target_desc *mips_tdesc_gp64;
184 /* Return non-zero if PC is in a MIPS SVR4 lazy binding stub section. */
187 in_mips_stubs_section (CORE_ADDR pc)
189 return pc_in_section (pc, ".MIPS.stubs");
192 #endif /* MIPS_TDEP_H */