1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data *mips_pdr_data;
63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
65 static int mips32_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR);
66 static int micromips_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR,
68 static int mips16_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR,
71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
73 #define ST0_FR (1 << 26)
75 /* The sizes of floating point registers. */
79 MIPS_FPU_SINGLE_REGSIZE = 4,
80 MIPS_FPU_DOUBLE_REGSIZE = 8
89 static const char *mips_abi_string;
91 static const char *const mips_abi_strings[] = {
102 /* For backwards compatibility we default to MIPS16. This flag is
103 overridden as soon as unambiguous ELF file flags tell us the
104 compressed ISA encoding used. */
105 static const char mips_compression_mips16[] = "mips16";
106 static const char mips_compression_micromips[] = "micromips";
107 static const char *const mips_compression_strings[] =
109 mips_compression_mips16,
110 mips_compression_micromips,
114 static const char *mips_compression_string = mips_compression_mips16;
116 /* The standard register names, and all the valid aliases for them. */
117 struct register_alias
123 /* Aliases for o32 and most other ABIs. */
124 const struct register_alias mips_o32_aliases[] = {
131 /* Aliases for n32 and n64. */
132 const struct register_alias mips_n32_n64_aliases[] = {
139 /* Aliases for ABI-independent registers. */
140 const struct register_alias mips_register_aliases[] = {
141 /* The architecture manuals specify these ABI-independent names for
143 #define R(n) { "r" #n, n }
144 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
145 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
146 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
147 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
150 /* k0 and k1 are sometimes called these instead (for "kernel
155 /* This is the traditional GDB name for the CP0 status register. */
156 { "sr", MIPS_PS_REGNUM },
158 /* This is the traditional GDB name for the CP0 BadVAddr register. */
159 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
161 /* This is the traditional GDB name for the FCSR. */
162 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
165 const struct register_alias mips_numeric_register_aliases[] = {
166 #define R(n) { #n, n }
167 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
168 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
169 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
170 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
174 #ifndef MIPS_DEFAULT_FPU_TYPE
175 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
177 static int mips_fpu_type_auto = 1;
178 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
180 static unsigned int mips_debug = 0;
182 /* Properties (for struct target_desc) describing the g/G packet
184 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
185 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
187 struct target_desc *mips_tdesc_gp32;
188 struct target_desc *mips_tdesc_gp64;
190 const struct mips_regnum *
191 mips_regnum (struct gdbarch *gdbarch)
193 return gdbarch_tdep (gdbarch)->regnum;
197 mips_fpa0_regnum (struct gdbarch *gdbarch)
199 return mips_regnum (gdbarch)->fp0 + 12;
202 /* Return 1 if REGNUM refers to a floating-point general register, raw
203 or cooked. Otherwise return 0. */
206 mips_float_register_p (struct gdbarch *gdbarch, int regnum)
208 int rawnum = regnum % gdbarch_num_regs (gdbarch);
210 return (rawnum >= mips_regnum (gdbarch)->fp0
211 && rawnum < mips_regnum (gdbarch)->fp0 + 32);
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch *gdbarch)
230 return gdbarch_tdep (gdbarch)->mips_abi;
234 mips_isa_regsize (struct gdbarch *gdbarch)
236 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
238 /* If we know how big the registers are, use that size. */
239 if (tdep->register_size_valid_p)
240 return tdep->register_size;
242 /* Fall back to the previous behavior. */
243 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
244 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
247 /* Return the currently configured (or set) saved register size. */
250 mips_abi_regsize (struct gdbarch *gdbarch)
252 switch (mips_abi (gdbarch))
254 case MIPS_ABI_EABI32:
260 case MIPS_ABI_EABI64:
262 case MIPS_ABI_UNKNOWN:
265 internal_error (__FILE__, __LINE__, _("bad switch"));
269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
270 are some functions to handle addresses associated with compressed
271 code including but not limited to testing, setting, or clearing
272 bit 0 of such addresses. */
274 /* Return one iff compressed code is the MIPS16 instruction set. */
277 is_mips16_isa (struct gdbarch *gdbarch)
279 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16;
282 /* Return one iff compressed code is the microMIPS instruction set. */
285 is_micromips_isa (struct gdbarch *gdbarch)
287 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS;
290 /* Return one iff ADDR denotes compressed code. */
293 is_compact_addr (CORE_ADDR addr)
298 /* Return one iff ADDR denotes standard ISA code. */
301 is_mips_addr (CORE_ADDR addr)
303 return !is_compact_addr (addr);
306 /* Return one iff ADDR denotes MIPS16 code. */
309 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
311 return is_compact_addr (addr) && is_mips16_isa (gdbarch);
314 /* Return one iff ADDR denotes microMIPS code. */
317 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
319 return is_compact_addr (addr) && is_micromips_isa (gdbarch);
322 /* Strip the ISA (compression) bit off from ADDR. */
325 unmake_compact_addr (CORE_ADDR addr)
327 return ((addr) & ~(CORE_ADDR) 1);
330 /* Add the ISA (compression) bit to ADDR. */
333 make_compact_addr (CORE_ADDR addr)
335 return ((addr) | (CORE_ADDR) 1);
338 /* Functions for setting and testing a bit in a minimal symbol that
339 marks it as MIPS16 or microMIPS function. The MSB of the minimal
340 symbol's "info" field is used for this purpose.
342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
344 one of the "special" bits in a minimal symbol to mark it accordingly.
345 The test checks an ELF-private flag that is valid for true function
346 symbols only; in particular synthetic symbols such as for PLT stubs
347 have no ELF-private part at all.
349 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
350 in a minimal symbol. */
353 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
355 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
357 if ((sym->flags & BSF_SYNTHETIC) != 0)
360 if (ELF_ST_IS_MICROMIPS (elfsym->internal_elf_sym.st_other))
361 MSYMBOL_TARGET_FLAG_2 (msym) = 1;
362 else if (ELF_ST_IS_MIPS16 (elfsym->internal_elf_sym.st_other))
363 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
366 /* Return one iff MSYM refers to standard ISA code. */
369 msymbol_is_mips (struct minimal_symbol *msym)
371 return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym));
374 /* Return one iff MSYM refers to MIPS16 code. */
377 msymbol_is_mips16 (struct minimal_symbol *msym)
379 return MSYMBOL_TARGET_FLAG_1 (msym);
382 /* Return one iff MSYM refers to microMIPS code. */
385 msymbol_is_micromips (struct minimal_symbol *msym)
387 return MSYMBOL_TARGET_FLAG_2 (msym);
390 /* XFER a value from the big/little/left end of the register.
391 Depending on the size of the value it might occupy the entire
392 register or just part of it. Make an allowance for this, aligning
393 things accordingly. */
396 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
397 int reg_num, int length,
398 enum bfd_endian endian, gdb_byte *in,
399 const gdb_byte *out, int buf_offset)
403 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
404 /* Need to transfer the left or right part of the register, based on
405 the targets byte order. */
409 reg_offset = register_size (gdbarch, reg_num) - length;
411 case BFD_ENDIAN_LITTLE:
414 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
418 internal_error (__FILE__, __LINE__, _("bad switch"));
421 fprintf_unfiltered (gdb_stderr,
422 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
423 reg_num, reg_offset, buf_offset, length);
424 if (mips_debug && out != NULL)
427 fprintf_unfiltered (gdb_stdlog, "out ");
428 for (i = 0; i < length; i++)
429 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
432 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
435 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
437 if (mips_debug && in != NULL)
440 fprintf_unfiltered (gdb_stdlog, "in ");
441 for (i = 0; i < length; i++)
442 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
445 fprintf_unfiltered (gdb_stdlog, "\n");
448 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
449 compatiblity mode. A return value of 1 means that we have
450 physical 64-bit registers, but should treat them as 32-bit registers. */
453 mips2_fp_compat (struct frame_info *frame)
455 struct gdbarch *gdbarch = get_frame_arch (frame);
456 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
458 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
462 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
463 in all the places we deal with FP registers. PR gdb/413. */
464 /* Otherwise check the FR bit in the status register - it controls
465 the FP compatiblity mode. If it is clear we are in compatibility
467 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
474 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
476 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
478 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
480 /* The list of available "set mips " and "show mips " commands. */
482 static struct cmd_list_element *setmipscmdlist = NULL;
483 static struct cmd_list_element *showmipscmdlist = NULL;
485 /* Integer registers 0 thru 31 are handled explicitly by
486 mips_register_name(). Processor specific registers 32 and above
487 are listed in the following tables. */
490 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
494 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
495 "sr", "lo", "hi", "bad", "cause", "pc",
496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
503 /* Names of IDT R3041 registers. */
505 static const char *mips_r3041_reg_names[] = {
506 "sr", "lo", "hi", "bad", "cause", "pc",
507 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
511 "fsr", "fir", "", /*"fp" */ "",
512 "", "", "bus", "ccfg", "", "", "", "",
513 "", "", "port", "cmp", "", "", "epc", "prid",
516 /* Names of tx39 registers. */
518 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
519 "sr", "lo", "hi", "bad", "cause", "pc",
520 "", "", "", "", "", "", "", "",
521 "", "", "", "", "", "", "", "",
522 "", "", "", "", "", "", "", "",
523 "", "", "", "", "", "", "", "",
525 "", "", "", "", "", "", "", "",
526 "", "", "config", "cache", "debug", "depc", "epc",
529 /* Names of IRIX registers. */
530 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
531 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
532 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
533 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
534 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
535 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
538 /* Names of registers with Linux kernels. */
539 static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
540 "sr", "lo", "hi", "bad", "cause", "pc",
541 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
542 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
543 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
544 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
549 /* Return the name of the register corresponding to REGNO. */
551 mips_register_name (struct gdbarch *gdbarch, int regno)
553 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
554 /* GPR names for all ABIs other than n32/n64. */
555 static char *mips_gpr_names[] = {
556 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
557 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
559 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
562 /* GPR names for n32 and n64 ABIs. */
563 static char *mips_n32_n64_gpr_names[] = {
564 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
565 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
566 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
567 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
570 enum mips_abi abi = mips_abi (gdbarch);
572 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
573 but then don't make the raw register names visible. This (upper)
574 range of user visible register numbers are the pseudo-registers.
576 This approach was adopted accommodate the following scenario:
577 It is possible to debug a 64-bit device using a 32-bit
578 programming model. In such instances, the raw registers are
579 configured to be 64-bits wide, while the pseudo registers are
580 configured to be 32-bits wide. The registers that the user
581 sees - the pseudo registers - match the users expectations
582 given the programming model being used. */
583 int rawnum = regno % gdbarch_num_regs (gdbarch);
584 if (regno < gdbarch_num_regs (gdbarch))
587 /* The MIPS integer registers are always mapped from 0 to 31. The
588 names of the registers (which reflects the conventions regarding
589 register use) vary depending on the ABI. */
590 if (0 <= rawnum && rawnum < 32)
592 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
593 return mips_n32_n64_gpr_names[rawnum];
595 return mips_gpr_names[rawnum];
597 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
598 return tdesc_register_name (gdbarch, rawnum);
599 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
601 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
602 if (tdep->mips_processor_reg_names[rawnum - 32])
603 return tdep->mips_processor_reg_names[rawnum - 32];
607 internal_error (__FILE__, __LINE__,
608 _("mips_register_name: bad register number %d"), rawnum);
611 /* Return the groups that a MIPS register can be categorised into. */
614 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
615 struct reggroup *reggroup)
620 int rawnum = regnum % gdbarch_num_regs (gdbarch);
621 int pseudo = regnum / gdbarch_num_regs (gdbarch);
622 if (reggroup == all_reggroup)
624 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
625 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
626 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
627 (gdbarch), as not all architectures are multi-arch. */
628 raw_p = rawnum < gdbarch_num_regs (gdbarch);
629 if (gdbarch_register_name (gdbarch, regnum) == NULL
630 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
632 if (reggroup == float_reggroup)
633 return float_p && pseudo;
634 if (reggroup == vector_reggroup)
635 return vector_p && pseudo;
636 if (reggroup == general_reggroup)
637 return (!vector_p && !float_p) && pseudo;
638 /* Save the pseudo registers. Need to make certain that any code
639 extracting register values from a saved register cache also uses
641 if (reggroup == save_reggroup)
642 return raw_p && pseudo;
643 /* Restore the same pseudo register. */
644 if (reggroup == restore_reggroup)
645 return raw_p && pseudo;
649 /* Return the groups that a MIPS register can be categorised into.
650 This version is only used if we have a target description which
651 describes real registers (and their groups). */
654 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
655 struct reggroup *reggroup)
657 int rawnum = regnum % gdbarch_num_regs (gdbarch);
658 int pseudo = regnum / gdbarch_num_regs (gdbarch);
661 /* Only save, restore, and display the pseudo registers. Need to
662 make certain that any code extracting register values from a
663 saved register cache also uses pseudo registers.
665 Note: saving and restoring the pseudo registers is slightly
666 strange; if we have 64 bits, we should save and restore all
667 64 bits. But this is hard and has little benefit. */
671 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
675 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
678 /* Map the symbol table registers which live in the range [1 *
679 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
680 registers. Take care of alignment and size problems. */
682 static enum register_status
683 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
684 int cookednum, gdb_byte *buf)
686 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
687 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
688 && cookednum < 2 * gdbarch_num_regs (gdbarch));
689 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
690 return regcache_raw_read (regcache, rawnum, buf);
691 else if (register_size (gdbarch, rawnum) >
692 register_size (gdbarch, cookednum))
694 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
695 return regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
698 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
700 enum register_status status;
702 status = regcache_raw_read_signed (regcache, rawnum, ®val);
703 if (status == REG_VALID)
704 store_signed_integer (buf, 4, byte_order, regval);
709 internal_error (__FILE__, __LINE__, _("bad register size"));
713 mips_pseudo_register_write (struct gdbarch *gdbarch,
714 struct regcache *regcache, int cookednum,
717 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
718 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
719 && cookednum < 2 * gdbarch_num_regs (gdbarch));
720 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
721 regcache_raw_write (regcache, rawnum, buf);
722 else if (register_size (gdbarch, rawnum) >
723 register_size (gdbarch, cookednum))
725 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
726 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
729 /* Sign extend the shortened version of the register prior
730 to placing it in the raw register. This is required for
731 some mips64 parts in order to avoid unpredictable behavior. */
732 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
733 LONGEST regval = extract_signed_integer (buf, 4, byte_order);
734 regcache_raw_write_signed (regcache, rawnum, regval);
738 internal_error (__FILE__, __LINE__, _("bad register size"));
742 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch,
743 struct agent_expr *ax, int reg)
745 int rawnum = reg % gdbarch_num_regs (gdbarch);
746 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
747 && reg < 2 * gdbarch_num_regs (gdbarch));
749 ax_reg_mask (ax, rawnum);
755 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
756 struct agent_expr *ax, int reg)
758 int rawnum = reg % gdbarch_num_regs (gdbarch);
759 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
760 && reg < 2 * gdbarch_num_regs (gdbarch));
761 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg))
765 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg))
767 if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
768 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG)
771 ax_simple (ax, aop_lsh);
774 ax_simple (ax, aop_rsh_signed);
778 internal_error (__FILE__, __LINE__, _("bad register size"));
783 /* Table to translate 3-bit register field to actual register number. */
784 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
786 /* Heuristic_proc_start may hunt through the text section for a long
787 time across a 2400 baud serial line. Allows the user to limit this
790 static unsigned int heuristic_fence_post = 0;
792 /* Number of bytes of storage in the actual machine representation for
793 register N. NOTE: This defines the pseudo register type so need to
794 rebuild the architecture vector. */
796 static int mips64_transfers_32bit_regs_p = 0;
799 set_mips64_transfers_32bit_regs (char *args, int from_tty,
800 struct cmd_list_element *c)
802 struct gdbarch_info info;
803 gdbarch_info_init (&info);
804 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
805 instead of relying on globals. Doing that would let generic code
806 handle the search for this specific architecture. */
807 if (!gdbarch_update_p (info))
809 mips64_transfers_32bit_regs_p = 0;
810 error (_("32-bit compatibility mode not supported"));
814 /* Convert to/from a register and the corresponding memory value. */
816 /* This predicate tests for the case of an 8 byte floating point
817 value that is being transferred to or from a pair of floating point
818 registers each of which are (or are considered to be) only 4 bytes
821 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum,
824 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
825 && register_size (gdbarch, regnum) == 4
826 && mips_float_register_p (gdbarch, regnum)
827 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
830 /* This predicate tests for the case of a value of less than 8
831 bytes in width that is being transfered to or from an 8 byte
832 general purpose register. */
834 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum,
837 int num_regs = gdbarch_num_regs (gdbarch);
839 return (register_size (gdbarch, regnum) == 8
840 && regnum % num_regs > 0 && regnum % num_regs < 32
841 && TYPE_LENGTH (type) < 8);
845 mips_convert_register_p (struct gdbarch *gdbarch,
846 int regnum, struct type *type)
848 return (mips_convert_register_float_case_p (gdbarch, regnum, type)
849 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type));
853 mips_register_to_value (struct frame_info *frame, int regnum,
854 struct type *type, gdb_byte *to,
855 int *optimizedp, int *unavailablep)
857 struct gdbarch *gdbarch = get_frame_arch (frame);
859 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
861 get_frame_register (frame, regnum + 0, to + 4);
862 get_frame_register (frame, regnum + 1, to + 0);
864 if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4,
865 optimizedp, unavailablep))
868 if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0,
869 optimizedp, unavailablep))
871 *optimizedp = *unavailablep = 0;
874 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
876 int len = TYPE_LENGTH (type);
879 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0;
880 if (!get_frame_register_bytes (frame, regnum, offset, len, to,
881 optimizedp, unavailablep))
884 *optimizedp = *unavailablep = 0;
889 internal_error (__FILE__, __LINE__,
890 _("mips_register_to_value: unrecognized case"));
895 mips_value_to_register (struct frame_info *frame, int regnum,
896 struct type *type, const gdb_byte *from)
898 struct gdbarch *gdbarch = get_frame_arch (frame);
900 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
902 put_frame_register (frame, regnum + 0, from + 4);
903 put_frame_register (frame, regnum + 1, from + 0);
905 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
908 int len = TYPE_LENGTH (type);
910 /* Sign extend values, irrespective of type, that are stored to
911 a 64-bit general purpose register. (32-bit unsigned values
912 are stored as signed quantities within a 64-bit register.
913 When performing an operation, in compiled code, that combines
914 a 32-bit unsigned value with a signed 64-bit value, a type
915 conversion is first performed that zeroes out the high 32 bits.) */
916 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
919 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1);
921 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0);
922 put_frame_register_bytes (frame, regnum, 0, 8 - len, fill);
923 put_frame_register_bytes (frame, regnum, 8 - len, len, from);
927 if (from[len-1] & 0x80)
928 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1);
930 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0);
931 put_frame_register_bytes (frame, regnum, 0, len, from);
932 put_frame_register_bytes (frame, regnum, len, 8 - len, fill);
937 internal_error (__FILE__, __LINE__,
938 _("mips_value_to_register: unrecognized case"));
942 /* Return the GDB type object for the "standard" data type of data in
946 mips_register_type (struct gdbarch *gdbarch, int regnum)
948 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
949 if (mips_float_register_p (gdbarch, regnum))
951 /* The floating-point registers raw, or cooked, always match
952 mips_isa_regsize(), and also map 1:1, byte for byte. */
953 if (mips_isa_regsize (gdbarch) == 4)
954 return builtin_type (gdbarch)->builtin_float;
956 return builtin_type (gdbarch)->builtin_double;
958 else if (regnum < gdbarch_num_regs (gdbarch))
960 /* The raw or ISA registers. These are all sized according to
962 if (mips_isa_regsize (gdbarch) == 4)
963 return builtin_type (gdbarch)->builtin_int32;
965 return builtin_type (gdbarch)->builtin_int64;
969 int rawnum = regnum - gdbarch_num_regs (gdbarch);
971 /* The cooked or ABI registers. These are sized according to
972 the ABI (with a few complications). */
973 if (rawnum == mips_regnum (gdbarch)->fp_control_status
974 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision)
975 return builtin_type (gdbarch)->builtin_int32;
976 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX
977 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
978 && rawnum >= MIPS_FIRST_EMBED_REGNUM
979 && rawnum <= MIPS_LAST_EMBED_REGNUM)
980 /* The pseudo/cooked view of the embedded registers is always
981 32-bit. The raw view is handled below. */
982 return builtin_type (gdbarch)->builtin_int32;
983 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
984 /* The target, while possibly using a 64-bit register buffer,
985 is only transfering 32-bits of each integer register.
986 Reflect this in the cooked/pseudo (ABI) register value. */
987 return builtin_type (gdbarch)->builtin_int32;
988 else if (mips_abi_regsize (gdbarch) == 4)
989 /* The ABI is restricted to 32-bit registers (the ISA could be
991 return builtin_type (gdbarch)->builtin_int32;
994 return builtin_type (gdbarch)->builtin_int64;
998 /* Return the GDB type for the pseudo register REGNUM, which is the
999 ABI-level view. This function is only called if there is a target
1000 description which includes registers, so we know precisely the
1001 types of hardware registers. */
1003 static struct type *
1004 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
1006 const int num_regs = gdbarch_num_regs (gdbarch);
1007 int rawnum = regnum % num_regs;
1008 struct type *rawtype;
1010 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
1012 /* Absent registers are still absent. */
1013 rawtype = gdbarch_register_type (gdbarch, rawnum);
1014 if (TYPE_LENGTH (rawtype) == 0)
1017 if (mips_float_register_p (gdbarch, rawnum))
1018 /* Present the floating point registers however the hardware did;
1019 do not try to convert between FPU layouts. */
1022 /* Use pointer types for registers if we can. For n32 we can not,
1023 since we do not have a 64-bit pointer type. */
1024 if (mips_abi_regsize (gdbarch)
1025 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
1027 if (rawnum == MIPS_SP_REGNUM
1028 || rawnum == mips_regnum (gdbarch)->badvaddr)
1029 return builtin_type (gdbarch)->builtin_data_ptr;
1030 else if (rawnum == mips_regnum (gdbarch)->pc)
1031 return builtin_type (gdbarch)->builtin_func_ptr;
1034 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
1035 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM)
1036 || rawnum == mips_regnum (gdbarch)->lo
1037 || rawnum == mips_regnum (gdbarch)->hi
1038 || rawnum == mips_regnum (gdbarch)->badvaddr
1039 || rawnum == mips_regnum (gdbarch)->cause
1040 || rawnum == mips_regnum (gdbarch)->pc
1041 || (mips_regnum (gdbarch)->dspacc != -1
1042 && rawnum >= mips_regnum (gdbarch)->dspacc
1043 && rawnum < mips_regnum (gdbarch)->dspacc + 6)))
1044 return builtin_type (gdbarch)->builtin_int32;
1046 if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX
1047 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
1048 && rawnum >= MIPS_EMBED_FP0_REGNUM + 32
1049 && rawnum <= MIPS_LAST_EMBED_REGNUM)
1051 /* The pseudo/cooked view of embedded registers is always
1052 32-bit, even if the target transfers 64-bit values for them.
1053 New targets relying on XML descriptions should only transfer
1054 the necessary 32 bits, but older versions of GDB expected 64,
1055 so allow the target to provide 64 bits without interfering
1056 with the displayed type. */
1057 return builtin_type (gdbarch)->builtin_int32;
1060 /* For all other registers, pass through the hardware type. */
1064 /* Should the upper word of 64-bit addresses be zeroed? */
1065 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
1068 mips_mask_address_p (struct gdbarch_tdep *tdep)
1070 switch (mask_address_var)
1072 case AUTO_BOOLEAN_TRUE:
1074 case AUTO_BOOLEAN_FALSE:
1077 case AUTO_BOOLEAN_AUTO:
1078 return tdep->default_mask_address_p;
1080 internal_error (__FILE__, __LINE__,
1081 _("mips_mask_address_p: bad switch"));
1087 show_mask_address (struct ui_file *file, int from_tty,
1088 struct cmd_list_element *c, const char *value)
1090 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
1092 deprecated_show_value_hack (file, from_tty, c, value);
1093 switch (mask_address_var)
1095 case AUTO_BOOLEAN_TRUE:
1096 printf_filtered ("The 32 bit mips address mask is enabled\n");
1098 case AUTO_BOOLEAN_FALSE:
1099 printf_filtered ("The 32 bit mips address mask is disabled\n");
1101 case AUTO_BOOLEAN_AUTO:
1103 ("The 32 bit address mask is set automatically. Currently %s\n",
1104 mips_mask_address_p (tdep) ? "enabled" : "disabled");
1107 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
1112 /* Tell if the program counter value in MEMADDR is in a standard ISA
1116 mips_pc_is_mips (CORE_ADDR memaddr)
1118 struct minimal_symbol *sym;
1120 /* Flags indicating that this is a MIPS16 or microMIPS function is
1121 stored by elfread.c in the high bit of the info field. Use this
1122 to decide if the function is standard MIPS. Otherwise if bit 0
1123 of the address is clear, then this is a standard MIPS function. */
1124 sym = lookup_minimal_symbol_by_pc (memaddr);
1126 return msymbol_is_mips (sym);
1128 return is_mips_addr (memaddr);
1131 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1134 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1136 struct minimal_symbol *sym;
1138 /* A flag indicating that this is a MIPS16 function is stored by
1139 elfread.c in the high bit of the info field. Use this to decide
1140 if the function is MIPS16. Otherwise if bit 0 of the address is
1141 set, then ELF file flags will tell if this is a MIPS16 function. */
1142 sym = lookup_minimal_symbol_by_pc (memaddr);
1144 return msymbol_is_mips16 (sym);
1146 return is_mips16_addr (gdbarch, memaddr);
1149 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1152 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1154 struct minimal_symbol *sym;
1156 /* A flag indicating that this is a microMIPS function is stored by
1157 elfread.c in the high bit of the info field. Use this to decide
1158 if the function is microMIPS. Otherwise if bit 0 of the address
1159 is set, then ELF file flags will tell if this is a microMIPS
1161 sym = lookup_minimal_symbol_by_pc (memaddr);
1163 return msymbol_is_micromips (sym);
1165 return is_micromips_addr (gdbarch, memaddr);
1168 /* Tell the ISA type of the function the program counter value in MEMADDR
1171 static enum mips_isa
1172 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1174 struct minimal_symbol *sym;
1176 /* A flag indicating that this is a MIPS16 or a microMIPS function
1177 is stored by elfread.c in the high bit of the info field. Use
1178 this to decide if the function is MIPS16 or microMIPS or normal
1179 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1180 flags will tell if this is a MIPS16 or a microMIPS function. */
1181 sym = lookup_minimal_symbol_by_pc (memaddr);
1184 if (msymbol_is_micromips (sym))
1185 return ISA_MICROMIPS;
1186 else if (msymbol_is_mips16 (sym))
1193 if (is_mips_addr (memaddr))
1195 else if (is_micromips_addr (gdbarch, memaddr))
1196 return ISA_MICROMIPS;
1202 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1204 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_";
1205 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_";
1206 static const char mips_str_call_fp_stub[] = "__call_stub_fp_";
1207 static const char mips_str_call_stub[] = "__call_stub_";
1208 static const char mips_str_fn_stub[] = "__fn_stub_";
1210 /* This is used as a PIC thunk prefix. */
1212 static const char mips_str_pic[] = ".pic.";
1214 /* Return non-zero if the PC is inside a call thunk (aka stub or
1215 trampoline) that should be treated as a temporary frame. */
1218 mips_in_frame_stub (CORE_ADDR pc)
1220 CORE_ADDR start_addr;
1223 /* Find the starting address of the function containing the PC. */
1224 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
1227 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1228 if (strncmp (name, mips_str_mips16_call_stub,
1229 strlen (mips_str_mips16_call_stub)) == 0)
1231 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1232 if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0)
1234 /* If the PC is in __fn_stub_*, this is a call stub. */
1235 if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0)
1238 return 0; /* Not a stub. */
1241 /* MIPS believes that the PC has a sign extended value. Perhaps the
1242 all registers should be sign extended for simplicity? */
1245 mips_read_pc (struct regcache *regcache)
1247 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache));
1250 regcache_cooked_read_signed (regcache, regnum, &pc);
1251 if (is_compact_addr (pc))
1252 pc = unmake_compact_addr (pc);
1257 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1261 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch));
1262 if (is_compact_addr (pc))
1263 pc = unmake_compact_addr (pc);
1264 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1265 intermediate frames. In this case we can get the caller's address
1266 from $ra, or if $ra contains an address within a thunk as well, then
1267 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1268 and thus the caller's address is in $s2. */
1269 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc))
1271 pc = frame_unwind_register_signed
1272 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
1273 if (is_compact_addr (pc))
1274 pc = unmake_compact_addr (pc);
1275 if (mips_in_frame_stub (pc))
1277 pc = frame_unwind_register_signed
1278 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
1279 if (is_compact_addr (pc))
1280 pc = unmake_compact_addr (pc);
1287 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1289 return frame_unwind_register_signed
1290 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
1293 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1294 dummy frame. The frame ID's base needs to match the TOS value
1295 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1298 static struct frame_id
1299 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1301 return frame_id_build
1302 (get_frame_register_signed (this_frame,
1303 gdbarch_num_regs (gdbarch)
1305 get_frame_pc (this_frame));
1308 /* Implement the "write_pc" gdbarch method. */
1311 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
1313 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache));
1315 if (mips_pc_is_mips (pc))
1316 regcache_cooked_write_unsigned (regcache, regnum, pc);
1318 regcache_cooked_write_unsigned (regcache, regnum, make_compact_addr (pc));
1321 /* Fetch and return instruction from the specified location. Handle
1322 MIPS16/microMIPS as appropriate. */
1325 mips_fetch_instruction (struct gdbarch *gdbarch,
1326 enum mips_isa isa, CORE_ADDR addr, int *statusp)
1328 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1329 gdb_byte buf[MIPS_INSN32_SIZE];
1337 instlen = MIPS_INSN16_SIZE;
1338 addr = unmake_compact_addr (addr);
1341 instlen = MIPS_INSN32_SIZE;
1344 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1347 status = target_read_memory (addr, buf, instlen);
1348 if (statusp != NULL)
1352 if (statusp == NULL)
1353 memory_error (status, addr);
1356 return extract_unsigned_integer (buf, instlen, byte_order);
1359 /* These are the fields of 32 bit mips instructions. */
1360 #define mips32_op(x) (x >> 26)
1361 #define itype_op(x) (x >> 26)
1362 #define itype_rs(x) ((x >> 21) & 0x1f)
1363 #define itype_rt(x) ((x >> 16) & 0x1f)
1364 #define itype_immediate(x) (x & 0xffff)
1366 #define jtype_op(x) (x >> 26)
1367 #define jtype_target(x) (x & 0x03ffffff)
1369 #define rtype_op(x) (x >> 26)
1370 #define rtype_rs(x) ((x >> 21) & 0x1f)
1371 #define rtype_rt(x) ((x >> 16) & 0x1f)
1372 #define rtype_rd(x) ((x >> 11) & 0x1f)
1373 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1374 #define rtype_funct(x) (x & 0x3f)
1376 /* MicroMIPS instruction fields. */
1377 #define micromips_op(x) ((x) >> 10)
1379 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1380 bit and the size respectively of the field extracted. */
1381 #define b0s4_imm(x) ((x) & 0xf)
1382 #define b0s5_imm(x) ((x) & 0x1f)
1383 #define b0s5_reg(x) ((x) & 0x1f)
1384 #define b0s7_imm(x) ((x) & 0x7f)
1385 #define b0s10_imm(x) ((x) & 0x3ff)
1386 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1387 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1388 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1389 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1390 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1391 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1392 #define b6s4_op(x) (((x) >> 6) & 0xf)
1393 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1395 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1396 respectively of the field extracted. */
1397 #define b0s6_op(x) ((x) & 0x3f)
1398 #define b0s11_op(x) ((x) & 0x7ff)
1399 #define b0s12_imm(x) ((x) & 0xfff)
1400 #define b0s16_imm(x) ((x) & 0xffff)
1401 #define b0s26_imm(x) ((x) & 0x3ffffff)
1402 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1403 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1404 #define b12s4_op(x) (((x) >> 12) & 0xf)
1406 /* Return the size in bytes of the instruction INSN encoded in the ISA
1410 mips_insn_size (enum mips_isa isa, ULONGEST insn)
1415 if (micromips_op (insn) == 0x1f)
1416 return 3 * MIPS_INSN16_SIZE;
1417 else if (((micromips_op (insn) & 0x4) == 0x4)
1418 || ((micromips_op (insn) & 0x7) == 0x0))
1419 return 2 * MIPS_INSN16_SIZE;
1421 return MIPS_INSN16_SIZE;
1423 if ((insn & 0xf800) == 0xf000)
1424 return 2 * MIPS_INSN16_SIZE;
1426 return MIPS_INSN16_SIZE;
1428 return MIPS_INSN32_SIZE;
1430 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1434 mips32_relative_offset (ULONGEST inst)
1436 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
1439 /* Determine the address of the next instruction executed after the INST
1440 floating condition branch instruction at PC. COUNT specifies the
1441 number of the floating condition bits tested by the branch. */
1444 mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
1445 ULONGEST inst, CORE_ADDR pc, int count)
1447 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1448 int cnum = (itype_rt (inst) >> 2) & (count - 1);
1449 int tf = itype_rt (inst) & 1;
1450 int mask = (1 << count) - 1;
1455 /* No way to handle; it'll most likely trap anyway. */
1458 fcs = get_frame_register_unsigned (frame, fcsr);
1459 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1461 if (((cond >> cnum) & mask) != mask * !tf)
1462 pc += mips32_relative_offset (inst);
1469 /* Return nonzero if the gdbarch is an Octeon series. */
1472 is_octeon (struct gdbarch *gdbarch)
1474 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
1476 return (info->mach == bfd_mach_mips_octeon
1477 || info->mach == bfd_mach_mips_octeonp
1478 || info->mach == bfd_mach_mips_octeon2);
1481 /* Return true if the OP represents the Octeon's BBIT instruction. */
1484 is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
1486 if (!is_octeon (gdbarch))
1488 /* BBIT0 is encoded as LWC2: 110 010. */
1489 /* BBIT032 is encoded as LDC2: 110 110. */
1490 /* BBIT1 is encoded as SWC2: 111 010. */
1491 /* BBIT132 is encoded as SDC2: 111 110. */
1492 if (op == 50 || op == 54 || op == 58 || op == 62)
1498 /* Determine where to set a single step breakpoint while considering
1499 branch prediction. */
1502 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
1504 struct gdbarch *gdbarch = get_frame_arch (frame);
1507 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
1508 op = itype_op (inst);
1509 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch
1513 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1524 goto greater_branch;
1529 else if (op == 17 && itype_rs (inst) == 8)
1530 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1531 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1);
1532 else if (op == 17 && itype_rs (inst) == 9
1533 && (itype_rt (inst) & 2) == 0)
1534 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1535 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2);
1536 else if (op == 17 && itype_rs (inst) == 10
1537 && (itype_rt (inst) & 2) == 0)
1538 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1539 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4);
1542 /* The new PC will be alternate mode. */
1546 reg = jtype_target (inst) << 2;
1547 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1548 pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1;
1550 else if (is_octeon_bbit_op (op, gdbarch))
1554 branch_if = op == 58 || op == 62;
1555 bit = itype_rt (inst);
1557 /* Take into account the *32 instructions. */
1558 if (op == 54 || op == 62)
1561 if (((get_frame_register_signed (frame,
1562 itype_rs (inst)) >> bit) & 1)
1564 pc += mips32_relative_offset (inst) + 4;
1566 pc += 8; /* After the delay slot. */
1570 pc += 4; /* Not a branch, next instruction is easy. */
1573 { /* This gets way messy. */
1575 /* Further subdivide into SPECIAL, REGIMM and other. */
1576 switch (op & 0x07) /* Extract bits 28,27,26. */
1578 case 0: /* SPECIAL */
1579 op = rtype_funct (inst);
1584 /* Set PC to that address. */
1585 pc = get_frame_register_signed (frame, rtype_rs (inst));
1587 case 12: /* SYSCALL */
1589 struct gdbarch_tdep *tdep;
1591 tdep = gdbarch_tdep (get_frame_arch (frame));
1592 if (tdep->syscall_next_pc != NULL)
1593 pc = tdep->syscall_next_pc (frame);
1602 break; /* end SPECIAL */
1603 case 1: /* REGIMM */
1605 op = itype_rt (inst); /* branch condition */
1610 case 16: /* BLTZAL */
1611 case 18: /* BLTZALL */
1613 if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1614 pc += mips32_relative_offset (inst) + 4;
1616 pc += 8; /* after the delay slot */
1620 case 17: /* BGEZAL */
1621 case 19: /* BGEZALL */
1622 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1623 pc += mips32_relative_offset (inst) + 4;
1625 pc += 8; /* after the delay slot */
1627 case 0x1c: /* BPOSGE32 */
1628 case 0x1e: /* BPOSGE64 */
1630 if (itype_rs (inst) == 0)
1632 unsigned int pos = (op & 2) ? 64 : 32;
1633 int dspctl = mips_regnum (gdbarch)->dspctl;
1636 /* No way to handle; it'll most likely trap anyway. */
1639 if ((get_frame_register_unsigned (frame,
1640 dspctl) & 0x7f) >= pos)
1641 pc += mips32_relative_offset (inst);
1646 /* All of the other instructions in the REGIMM category */
1651 break; /* end REGIMM */
1656 reg = jtype_target (inst) << 2;
1657 /* Upper four bits get never changed... */
1658 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1661 case 4: /* BEQ, BEQL */
1663 if (get_frame_register_signed (frame, itype_rs (inst)) ==
1664 get_frame_register_signed (frame, itype_rt (inst)))
1665 pc += mips32_relative_offset (inst) + 4;
1669 case 5: /* BNE, BNEL */
1671 if (get_frame_register_signed (frame, itype_rs (inst)) !=
1672 get_frame_register_signed (frame, itype_rt (inst)))
1673 pc += mips32_relative_offset (inst) + 4;
1677 case 6: /* BLEZ, BLEZL */
1678 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1679 pc += mips32_relative_offset (inst) + 4;
1685 greater_branch: /* BGTZ, BGTZL */
1686 if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1687 pc += mips32_relative_offset (inst) + 4;
1694 } /* mips32_next_pc */
1696 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1700 micromips_relative_offset7 (ULONGEST insn)
1702 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1;
1705 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1709 micromips_relative_offset10 (ULONGEST insn)
1711 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1;
1714 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1718 micromips_relative_offset16 (ULONGEST insn)
1720 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1;
1723 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1726 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc)
1730 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1731 return mips_insn_size (ISA_MICROMIPS, insn);
1734 /* Calculate the address of the next microMIPS instruction to execute
1735 after the INSN coprocessor 1 conditional branch instruction at the
1736 address PC. COUNT denotes the number of coprocessor condition bits
1737 examined by the branch. */
1740 micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
1741 ULONGEST insn, CORE_ADDR pc, int count)
1743 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1744 int cnum = b2s3_cc (insn >> 16) & (count - 1);
1745 int tf = b5s5_op (insn >> 16) & 1;
1746 int mask = (1 << count) - 1;
1751 /* No way to handle; it'll most likely trap anyway. */
1754 fcs = get_frame_register_unsigned (frame, fcsr);
1755 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1757 if (((cond >> cnum) & mask) != mask * !tf)
1758 pc += micromips_relative_offset16 (insn);
1760 pc += micromips_pc_insn_size (gdbarch, pc);
1765 /* Calculate the address of the next microMIPS instruction to execute
1766 after the instruction at the address PC. */
1769 micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1771 struct gdbarch *gdbarch = get_frame_arch (frame);
1774 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1775 pc += MIPS_INSN16_SIZE;
1776 switch (mips_insn_size (ISA_MICROMIPS, insn))
1778 /* 48-bit instructions. */
1779 case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
1780 /* No branch or jump instructions in this category. */
1781 pc += 2 * MIPS_INSN16_SIZE;
1784 /* 32-bit instructions. */
1785 case 2 * MIPS_INSN16_SIZE:
1787 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1788 pc += MIPS_INSN16_SIZE;
1789 switch (micromips_op (insn >> 16))
1791 case 0x00: /* POOL32A: bits 000000 */
1792 if (b0s6_op (insn) == 0x3c
1793 /* POOL32Axf: bits 000000 ... 111100 */
1794 && (b6s10_ext (insn) & 0x2bf) == 0x3c)
1795 /* JALR, JALR.HB: 000000 000x111100 111100 */
1796 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1797 pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16));
1800 case 0x10: /* POOL32I: bits 010000 */
1801 switch (b5s5_op (insn >> 16))
1803 case 0x00: /* BLTZ: bits 010000 00000 */
1804 case 0x01: /* BLTZAL: bits 010000 00001 */
1805 case 0x11: /* BLTZALS: bits 010000 10001 */
1806 if (get_frame_register_signed (frame,
1807 b0s5_reg (insn >> 16)) < 0)
1808 pc += micromips_relative_offset16 (insn);
1810 pc += micromips_pc_insn_size (gdbarch, pc);
1813 case 0x02: /* BGEZ: bits 010000 00010 */
1814 case 0x03: /* BGEZAL: bits 010000 00011 */
1815 case 0x13: /* BGEZALS: bits 010000 10011 */
1816 if (get_frame_register_signed (frame,
1817 b0s5_reg (insn >> 16)) >= 0)
1818 pc += micromips_relative_offset16 (insn);
1820 pc += micromips_pc_insn_size (gdbarch, pc);
1823 case 0x04: /* BLEZ: bits 010000 00100 */
1824 if (get_frame_register_signed (frame,
1825 b0s5_reg (insn >> 16)) <= 0)
1826 pc += micromips_relative_offset16 (insn);
1828 pc += micromips_pc_insn_size (gdbarch, pc);
1831 case 0x05: /* BNEZC: bits 010000 00101 */
1832 if (get_frame_register_signed (frame,
1833 b0s5_reg (insn >> 16)) != 0)
1834 pc += micromips_relative_offset16 (insn);
1837 case 0x06: /* BGTZ: bits 010000 00110 */
1838 if (get_frame_register_signed (frame,
1839 b0s5_reg (insn >> 16)) > 0)
1840 pc += micromips_relative_offset16 (insn);
1842 pc += micromips_pc_insn_size (gdbarch, pc);
1845 case 0x07: /* BEQZC: bits 010000 00111 */
1846 if (get_frame_register_signed (frame,
1847 b0s5_reg (insn >> 16)) == 0)
1848 pc += micromips_relative_offset16 (insn);
1851 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1852 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1853 if (((insn >> 16) & 0x3) == 0x0)
1854 /* BC2F, BC2T: don't know how to handle these. */
1858 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1859 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1861 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64;
1862 int dspctl = mips_regnum (gdbarch)->dspctl;
1865 /* No way to handle; it'll most likely trap anyway. */
1868 if ((get_frame_register_unsigned (frame,
1869 dspctl) & 0x7f) >= pos)
1870 pc += micromips_relative_offset16 (insn);
1872 pc += micromips_pc_insn_size (gdbarch, pc);
1876 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1877 /* BC1ANY2F: bits 010000 11100 xxx01 */
1878 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1879 /* BC1ANY2T: bits 010000 11101 xxx01 */
1880 if (((insn >> 16) & 0x2) == 0x0)
1881 pc = micromips_bc1_pc (gdbarch, frame, insn, pc,
1882 ((insn >> 16) & 0x1) + 1);
1885 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1886 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1887 if (((insn >> 16) & 0x3) == 0x1)
1888 pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4);
1893 case 0x1d: /* JALS: bits 011101 */
1894 case 0x35: /* J: bits 110101 */
1895 case 0x3d: /* JAL: bits 111101 */
1896 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1);
1899 case 0x25: /* BEQ: bits 100101 */
1900 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16))
1901 == get_frame_register_signed (frame, b5s5_reg (insn >> 16)))
1902 pc += micromips_relative_offset16 (insn);
1904 pc += micromips_pc_insn_size (gdbarch, pc);
1907 case 0x2d: /* BNE: bits 101101 */
1908 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16))
1909 != get_frame_register_signed (frame, b5s5_reg (insn >> 16)))
1910 pc += micromips_relative_offset16 (insn);
1912 pc += micromips_pc_insn_size (gdbarch, pc);
1915 case 0x3c: /* JALX: bits 111100 */
1916 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2);
1921 /* 16-bit instructions. */
1922 case MIPS_INSN16_SIZE:
1923 switch (micromips_op (insn))
1925 case 0x11: /* POOL16C: bits 010001 */
1926 if ((b5s5_op (insn) & 0x1c) == 0xc)
1927 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1928 pc = get_frame_register_signed (frame, b0s5_reg (insn));
1929 else if (b5s5_op (insn) == 0x18)
1930 /* JRADDIUSP: bits 010001 11000 */
1931 pc = get_frame_register_signed (frame, MIPS_RA_REGNUM);
1934 case 0x23: /* BEQZ16: bits 100011 */
1936 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
1938 if (get_frame_register_signed (frame, rs) == 0)
1939 pc += micromips_relative_offset7 (insn);
1941 pc += micromips_pc_insn_size (gdbarch, pc);
1945 case 0x2b: /* BNEZ16: bits 101011 */
1947 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
1949 if (get_frame_register_signed (frame, rs) != 0)
1950 pc += micromips_relative_offset7 (insn);
1952 pc += micromips_pc_insn_size (gdbarch, pc);
1956 case 0x33: /* B16: bits 110011 */
1957 pc += micromips_relative_offset10 (insn);
1966 /* Decoding the next place to set a breakpoint is irregular for the
1967 mips 16 variant, but fortunately, there fewer instructions. We have
1968 to cope ith extensions for 16 bit instructions and a pair of actual
1969 32 bit instructions. We dont want to set a single step instruction
1970 on the extend instruction either. */
1972 /* Lots of mips16 instruction formats */
1973 /* Predicting jumps requires itype,ritype,i8type
1974 and their extensions extItype,extritype,extI8type. */
1975 enum mips16_inst_fmts
1977 itype, /* 0 immediate 5,10 */
1978 ritype, /* 1 5,3,8 */
1979 rrtype, /* 2 5,3,3,5 */
1980 rritype, /* 3 5,3,3,5 */
1981 rrrtype, /* 4 5,3,3,3,2 */
1982 rriatype, /* 5 5,3,3,1,4 */
1983 shifttype, /* 6 5,3,3,3,2 */
1984 i8type, /* 7 5,3,8 */
1985 i8movtype, /* 8 5,3,3,5 */
1986 i8mov32rtype, /* 9 5,3,5,3 */
1987 i64type, /* 10 5,3,8 */
1988 ri64type, /* 11 5,3,3,5 */
1989 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1990 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1991 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1992 extRRItype, /* 15 5,5,5,5,3,3,5 */
1993 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1994 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1995 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1996 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1997 extRi64type, /* 20 5,6,5,5,3,3,5 */
1998 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2000 /* I am heaping all the fields of the formats into one structure and
2001 then, only the fields which are involved in instruction extension. */
2005 unsigned int regx; /* Function in i8 type. */
2010 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2011 for the bits which make up the immediate extension. */
2014 extended_offset (unsigned int extension)
2018 value = (extension >> 16) & 0x1f; /* Extract 15:11. */
2020 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */
2022 value |= extension & 0x1f; /* Extract 4:0. */
2027 /* Only call this function if you know that this is an extendable
2028 instruction. It won't malfunction, but why make excess remote memory
2029 references? If the immediate operands get sign extended or something,
2030 do it after the extension is performed. */
2031 /* FIXME: Every one of these cases needs to worry about sign extension
2032 when the offset is to be used in relative addressing. */
2035 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc)
2037 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2039 pc &= 0xfffffffe; /* Clear the low order bit. */
2040 target_read_memory (pc, buf, 2);
2041 return extract_unsigned_integer (buf, 2, byte_order);
2045 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc,
2046 unsigned int extension,
2048 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
2053 switch (insn_format)
2060 value = extended_offset ((extension << 16) | inst);
2061 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2065 value = inst & 0x7ff;
2066 value = (value ^ 0x400) - 0x400; /* Sign-extend. */
2075 { /* A register identifier and an offset. */
2076 /* Most of the fields are the same as I type but the
2077 immediate value is of a different length. */
2081 value = extended_offset ((extension << 16) | inst);
2082 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2086 value = inst & 0xff; /* 8 bits */
2087 value = (value ^ 0x80) - 0x80; /* Sign-extend. */
2090 regx = (inst >> 8) & 0x07; /* i8 funct */
2096 unsigned long value;
2097 unsigned int nexthalf;
2098 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
2099 value = value << 16;
2100 nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL);
2101 /* Low bit still set. */
2109 internal_error (__FILE__, __LINE__, _("bad switch"));
2111 upk->offset = offset;
2118 add_offset_16 (CORE_ADDR pc, int offset)
2120 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
2124 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
2125 unsigned int extension, unsigned int insn)
2127 struct gdbarch *gdbarch = get_frame_arch (frame);
2128 int op = (insn >> 11);
2131 case 2: /* Branch */
2133 struct upk_mips16 upk;
2134 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk);
2135 pc += (upk.offset << 1) + 2;
2138 case 3: /* JAL , JALX - Watch out, these are 32 bit
2141 struct upk_mips16 upk;
2142 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk);
2143 pc = add_offset_16 (pc, upk.offset);
2144 if ((insn >> 10) & 0x01) /* Exchange mode */
2145 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */
2152 struct upk_mips16 upk;
2154 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2155 reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]);
2157 pc += (upk.offset << 1) + 2;
2164 struct upk_mips16 upk;
2166 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2167 reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]);
2169 pc += (upk.offset << 1) + 2;
2174 case 12: /* I8 Formats btez btnez */
2176 struct upk_mips16 upk;
2178 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
2179 /* upk.regx contains the opcode */
2180 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
2181 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
2182 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
2183 /* pc = add_offset_16(pc,upk.offset) ; */
2184 pc += (upk.offset << 1) + 2;
2189 case 29: /* RR Formats JR, JALR, JALR-RA */
2191 struct upk_mips16 upk;
2192 /* upk.fmt = rrtype; */
2197 upk.regx = (insn >> 8) & 0x07;
2198 upk.regy = (insn >> 5) & 0x07;
2199 if ((upk.regy & 1) == 0)
2200 reg = mips_reg3_to_reg[upk.regx];
2202 reg = 31; /* Function return instruction. */
2203 pc = get_frame_register_signed (frame, reg);
2210 /* This is an instruction extension. Fetch the real instruction
2211 (which follows the extension) and decode things based on
2215 pc = extended_mips16_next_pc (frame, pc, insn,
2216 fetch_mips_16 (gdbarch, pc));
2229 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
2231 struct gdbarch *gdbarch = get_frame_arch (frame);
2232 unsigned int insn = fetch_mips_16 (gdbarch, pc);
2233 return extended_mips16_next_pc (frame, pc, 0, insn);
2236 /* The mips_next_pc function supports single_step when the remote
2237 target monitor or stub is not developed enough to do a single_step.
2238 It works by decoding the current instruction and predicting where a
2239 branch will go. This isnt hard because all the data is available.
2240 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2242 mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
2244 struct gdbarch *gdbarch = get_frame_arch (frame);
2246 if (mips_pc_is_mips16 (gdbarch, pc))
2247 return mips16_next_pc (frame, pc);
2248 else if (mips_pc_is_micromips (gdbarch, pc))
2249 return micromips_next_pc (frame, pc);
2251 return mips32_next_pc (frame, pc);
2254 struct mips_frame_cache
2257 struct trad_frame_saved_reg *saved_regs;
2260 /* Set a register's saved stack address in temp_saved_regs. If an
2261 address has already been set for this register, do nothing; this
2262 way we will only recognize the first save of a given register in a
2265 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2266 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2267 Strictly speaking, only the second range is used as it is only second
2268 range (the ABI instead of ISA registers) that comes into play when finding
2269 saved registers in a frame. */
2272 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
2273 int regnum, CORE_ADDR offset)
2275 if (this_cache != NULL
2276 && this_cache->saved_regs[regnum].addr == -1)
2278 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
2280 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
2286 /* Fetch the immediate value from a MIPS16 instruction.
2287 If the previous instruction was an EXTEND, use it to extend
2288 the upper bits of the immediate value. This is a helper function
2289 for mips16_scan_prologue. */
2292 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
2293 unsigned short inst, /* current instruction */
2294 int nbits, /* number of bits in imm field */
2295 int scale, /* scale factor to be applied to imm */
2296 int is_signed) /* is the imm field signed? */
2300 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2302 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
2303 if (offset & 0x8000) /* check for negative extend */
2304 offset = 0 - (0x10000 - (offset & 0xffff));
2305 return offset | (inst & 0x1f);
2309 int max_imm = 1 << nbits;
2310 int mask = max_imm - 1;
2311 int sign_bit = max_imm >> 1;
2313 offset = inst & mask;
2314 if (is_signed && (offset & sign_bit))
2315 offset = 0 - (max_imm - offset);
2316 return offset * scale;
2321 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2322 the associated FRAME_CACHE if not null.
2323 Return the address of the first instruction past the prologue. */
2326 mips16_scan_prologue (struct gdbarch *gdbarch,
2327 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2328 struct frame_info *this_frame,
2329 struct mips_frame_cache *this_cache)
2332 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */
2334 long frame_offset = 0; /* Size of stack frame. */
2335 long frame_adjust = 0; /* Offset of FP from SP. */
2336 int frame_reg = MIPS_SP_REGNUM;
2337 unsigned short prev_inst = 0; /* saved copy of previous instruction. */
2338 unsigned inst = 0; /* current instruction */
2339 unsigned entry_inst = 0; /* the entry instruction */
2340 unsigned save_inst = 0; /* the save instruction */
2343 int extend_bytes = 0;
2344 int prev_extend_bytes;
2345 CORE_ADDR end_prologue_addr = 0;
2347 /* Can be called when there's no process, and hence when there's no
2349 if (this_frame != NULL)
2350 sp = get_frame_register_signed (this_frame,
2351 gdbarch_num_regs (gdbarch)
2356 if (limit_pc > start_pc + 200)
2357 limit_pc = start_pc + 200;
2359 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
2361 /* Save the previous instruction. If it's an EXTEND, we'll extract
2362 the immediate offset extension from it in mips16_get_imm. */
2365 /* Fetch and decode the instruction. */
2366 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16,
2369 /* Normally we ignore extend instructions. However, if it is
2370 not followed by a valid prologue instruction, then this
2371 instruction is not part of the prologue either. We must
2372 remember in this case to adjust the end_prologue_addr back
2374 if ((inst & 0xf800) == 0xf000) /* extend */
2376 extend_bytes = MIPS_INSN16_SIZE;
2380 prev_extend_bytes = extend_bytes;
2383 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2384 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2386 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2387 if (offset < 0) /* Negative stack adjustment? */
2388 frame_offset -= offset;
2390 /* Exit loop if a positive stack adjustment is found, which
2391 usually means that the stack cleanup code in the function
2392 epilogue is reached. */
2395 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2397 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2398 reg = mips_reg3_to_reg[(inst & 0x700) >> 8];
2399 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2401 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2403 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2404 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2405 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2407 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2409 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2410 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2412 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2414 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2415 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2417 else if (inst == 0x673d) /* move $s1, $sp */
2422 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2424 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2425 frame_addr = sp + offset;
2427 frame_adjust = offset;
2429 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2431 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2432 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2433 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2435 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2437 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2438 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2439 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2441 else if ((inst & 0xf81f) == 0xe809
2442 && (inst & 0x700) != 0x700) /* entry */
2443 entry_inst = inst; /* Save for later processing. */
2444 else if ((inst & 0xff80) == 0x6480) /* save */
2446 save_inst = inst; /* Save for later processing. */
2447 if (prev_extend_bytes) /* extend */
2448 save_inst |= prev_inst << 16;
2450 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
2451 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
2452 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2454 /* This instruction is part of the prologue, but we don't
2455 need to do anything special to handle it. */
2459 /* This instruction is not an instruction typically found
2460 in a prologue, so we must have reached the end of the
2462 if (end_prologue_addr == 0)
2463 end_prologue_addr = cur_pc - prev_extend_bytes;
2467 /* The entry instruction is typically the first instruction in a function,
2468 and it stores registers at offsets relative to the value of the old SP
2469 (before the prologue). But the value of the sp parameter to this
2470 function is the new SP (after the prologue has been executed). So we
2471 can't calculate those offsets until we've seen the entire prologue,
2472 and can calculate what the old SP must have been. */
2473 if (entry_inst != 0)
2475 int areg_count = (entry_inst >> 8) & 7;
2476 int sreg_count = (entry_inst >> 6) & 3;
2478 /* The entry instruction always subtracts 32 from the SP. */
2481 /* Now we can calculate what the SP must have been at the
2482 start of the function prologue. */
2485 /* Check if a0-a3 were saved in the caller's argument save area. */
2486 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2488 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2489 offset += mips_abi_regsize (gdbarch);
2492 /* Check if the ra register was pushed on the stack. */
2494 if (entry_inst & 0x20)
2496 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2497 offset -= mips_abi_regsize (gdbarch);
2500 /* Check if the s0 and s1 registers were pushed on the stack. */
2501 for (reg = 16; reg < sreg_count + 16; reg++)
2503 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2504 offset -= mips_abi_regsize (gdbarch);
2508 /* The SAVE instruction is similar to ENTRY, except that defined by the
2509 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2510 size of the frame is specified as an immediate field of instruction
2511 and an extended variation exists which lets additional registers and
2512 frame space to be specified. The instruction always treats registers
2513 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2514 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
2516 static int args_table[16] = {
2517 0, 0, 0, 0, 1, 1, 1, 1,
2518 2, 2, 2, 0, 3, 3, 4, -1,
2520 static int astatic_table[16] = {
2521 0, 1, 2, 3, 0, 1, 2, 3,
2522 0, 1, 2, 4, 0, 1, 0, -1,
2524 int aregs = (save_inst >> 16) & 0xf;
2525 int xsregs = (save_inst >> 24) & 0x7;
2526 int args = args_table[aregs];
2527 int astatic = astatic_table[aregs];
2532 warning (_("Invalid number of argument registers encoded in SAVE."));
2537 warning (_("Invalid number of static registers encoded in SAVE."));
2541 /* For standard SAVE the frame size of 0 means 128. */
2542 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
2543 if (frame_size == 0 && (save_inst >> 16) == 0)
2546 frame_offset += frame_size;
2548 /* Now we can calculate what the SP must have been at the
2549 start of the function prologue. */
2552 /* Check if A0-A3 were saved in the caller's argument save area. */
2553 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
2555 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2556 offset += mips_abi_regsize (gdbarch);
2561 /* Check if the RA register was pushed on the stack. */
2562 if (save_inst & 0x40)
2564 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2565 offset -= mips_abi_regsize (gdbarch);
2568 /* Check if the S8 register was pushed on the stack. */
2571 set_reg_offset (gdbarch, this_cache, 30, sp + offset);
2572 offset -= mips_abi_regsize (gdbarch);
2575 /* Check if S2-S7 were pushed on the stack. */
2576 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
2578 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2579 offset -= mips_abi_regsize (gdbarch);
2582 /* Check if the S1 register was pushed on the stack. */
2583 if (save_inst & 0x10)
2585 set_reg_offset (gdbarch, this_cache, 17, sp + offset);
2586 offset -= mips_abi_regsize (gdbarch);
2588 /* Check if the S0 register was pushed on the stack. */
2589 if (save_inst & 0x20)
2591 set_reg_offset (gdbarch, this_cache, 16, sp + offset);
2592 offset -= mips_abi_regsize (gdbarch);
2595 /* Check if A0-A3 were pushed on the stack. */
2596 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
2598 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2599 offset -= mips_abi_regsize (gdbarch);
2603 if (this_cache != NULL)
2606 (get_frame_register_signed (this_frame,
2607 gdbarch_num_regs (gdbarch) + frame_reg)
2608 + frame_offset - frame_adjust);
2609 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2610 be able to get rid of the assignment below, evetually. But it's
2611 still needed for now. */
2612 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2613 + mips_regnum (gdbarch)->pc]
2614 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
2617 /* If we didn't reach the end of the prologue when scanning the function
2618 instructions, then set end_prologue_addr to the address of the
2619 instruction immediately after the last one we scanned. */
2620 if (end_prologue_addr == 0)
2621 end_prologue_addr = cur_pc;
2623 return end_prologue_addr;
2626 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2627 Procedures that use the 32-bit instruction set are handled by the
2628 mips_insn32 unwinder. */
2630 static struct mips_frame_cache *
2631 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
2633 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2634 struct mips_frame_cache *cache;
2636 if ((*this_cache) != NULL)
2637 return (*this_cache);
2638 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2639 (*this_cache) = cache;
2640 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2642 /* Analyze the function prologue. */
2644 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2645 CORE_ADDR start_addr;
2647 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2648 if (start_addr == 0)
2649 start_addr = heuristic_proc_start (gdbarch, pc);
2650 /* We can't analyze the prologue if we couldn't find the begining
2652 if (start_addr == 0)
2655 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
2658 /* gdbarch_sp_regnum contains the value and not the address. */
2659 trad_frame_set_value (cache->saved_regs,
2660 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
2663 return (*this_cache);
2667 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
2668 struct frame_id *this_id)
2670 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2672 /* This marks the outermost frame. */
2673 if (info->base == 0)
2675 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2678 static struct value *
2679 mips_insn16_frame_prev_register (struct frame_info *this_frame,
2680 void **this_cache, int regnum)
2682 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2684 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2688 mips_insn16_frame_sniffer (const struct frame_unwind *self,
2689 struct frame_info *this_frame, void **this_cache)
2691 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2692 CORE_ADDR pc = get_frame_pc (this_frame);
2693 if (mips_pc_is_mips16 (gdbarch, pc))
2698 static const struct frame_unwind mips_insn16_frame_unwind =
2701 default_frame_unwind_stop_reason,
2702 mips_insn16_frame_this_id,
2703 mips_insn16_frame_prev_register,
2705 mips_insn16_frame_sniffer
2709 mips_insn16_frame_base_address (struct frame_info *this_frame,
2712 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2717 static const struct frame_base mips_insn16_frame_base =
2719 &mips_insn16_frame_unwind,
2720 mips_insn16_frame_base_address,
2721 mips_insn16_frame_base_address,
2722 mips_insn16_frame_base_address
2725 static const struct frame_base *
2726 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
2728 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2729 CORE_ADDR pc = get_frame_pc (this_frame);
2730 if (mips_pc_is_mips16 (gdbarch, pc))
2731 return &mips_insn16_frame_base;
2736 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2737 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2738 interpreted directly, and then multiplied by 4. */
2741 micromips_decode_imm9 (int imm)
2743 imm = (imm ^ 0x100) - 0x100;
2744 if (imm > -3 && imm < 2)
2749 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2750 the address of the first instruction past the prologue. */
2753 micromips_scan_prologue (struct gdbarch *gdbarch,
2754 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2755 struct frame_info *this_frame,
2756 struct mips_frame_cache *this_cache)
2758 CORE_ADDR end_prologue_addr = 0;
2759 int prev_non_prologue_insn = 0;
2760 int frame_reg = MIPS_SP_REGNUM;
2761 int this_non_prologue_insn;
2762 int non_prologue_insns = 0;
2763 long frame_offset = 0; /* Size of stack frame. */
2764 long frame_adjust = 0; /* Offset of FP from SP. */
2765 CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */
2768 ULONGEST insn; /* current instruction */
2772 long v1_off = 0; /* The assumption is LUI will replace it. */
2783 /* Can be called when there's no process, and hence when there's no
2785 if (this_frame != NULL)
2786 sp = get_frame_register_signed (this_frame,
2787 gdbarch_num_regs (gdbarch)
2792 if (limit_pc > start_pc + 200)
2793 limit_pc = start_pc + 200;
2796 /* Permit at most one non-prologue non-control-transfer instruction
2797 in the middle which may have been reordered by the compiler for
2799 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc)
2801 this_non_prologue_insn = 0;
2804 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL);
2805 loc += MIPS_INSN16_SIZE;
2806 switch (mips_insn_size (ISA_MICROMIPS, insn))
2808 /* 48-bit instructions. */
2809 case 3 * MIPS_INSN16_SIZE:
2810 /* No prologue instructions in this category. */
2811 this_non_prologue_insn = 1;
2812 loc += 2 * MIPS_INSN16_SIZE;
2815 /* 32-bit instructions. */
2816 case 2 * MIPS_INSN16_SIZE:
2818 insn |= mips_fetch_instruction (gdbarch,
2819 ISA_MICROMIPS, cur_pc + loc, NULL);
2820 loc += MIPS_INSN16_SIZE;
2821 switch (micromips_op (insn >> 16))
2823 /* Record $sp/$fp adjustment. */
2824 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2825 case 0x0: /* POOL32A: bits 000000 */
2826 case 0x16: /* POOL32S: bits 010110 */
2827 op = b0s11_op (insn);
2828 sreg = b0s5_reg (insn >> 16);
2829 treg = b5s5_reg (insn >> 16);
2830 dreg = b11s5_reg (insn);
2832 /* SUBU: bits 000000 00111010000 */
2833 /* DSUBU: bits 010110 00111010000 */
2834 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM
2836 /* (D)SUBU $sp, $v1 */
2838 else if (op != 0x150
2839 /* ADDU: bits 000000 00101010000 */
2840 /* DADDU: bits 010110 00101010000 */
2841 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM)
2842 this_non_prologue_insn = 1;
2845 case 0x8: /* POOL32B: bits 001000 */
2846 op = b12s4_op (insn);
2847 breg = b0s5_reg (insn >> 16);
2848 reglist = sreg = b5s5_reg (insn >> 16);
2849 offset = (b0s12_imm (insn) ^ 0x800) - 0x800;
2850 if ((op == 0x9 || op == 0xc)
2851 /* SWP: bits 001000 1001 */
2852 /* SDP: bits 001000 1100 */
2853 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM)
2854 /* S[DW]P reg,offset($sp) */
2856 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4);
2857 set_reg_offset (gdbarch, this_cache,
2859 set_reg_offset (gdbarch, this_cache,
2860 sreg + 1, sp + offset + s);
2862 else if ((op == 0xd || op == 0xf)
2863 /* SWM: bits 001000 1101 */
2864 /* SDM: bits 001000 1111 */
2865 && breg == MIPS_SP_REGNUM
2866 /* SWM reglist,offset($sp) */
2867 && ((reglist >= 1 && reglist <= 9)
2868 || (reglist >= 16 && reglist <= 25)))
2870 int sreglist = min(reglist & 0xf, 8);
2872 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2);
2873 for (i = 0; i < sreglist; i++)
2874 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i);
2875 if ((reglist & 0xf) > 8)
2876 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++);
2877 if ((reglist & 0x10) == 0x10)
2878 set_reg_offset (gdbarch, this_cache,
2879 MIPS_RA_REGNUM, sp + s * i++);
2882 this_non_prologue_insn = 1;
2885 /* Record $sp/$fp adjustment. */
2886 /* Discard (D)ADDIU $gp used for PIC code. */
2887 case 0xc: /* ADDIU: bits 001100 */
2888 case 0x17: /* DADDIU: bits 010111 */
2889 sreg = b0s5_reg (insn >> 16);
2890 dreg = b5s5_reg (insn >> 16);
2891 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
2892 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM)
2893 /* (D)ADDIU $sp, imm */
2895 else if (sreg == MIPS_SP_REGNUM && dreg == 30)
2896 /* (D)ADDIU $fp, $sp, imm */
2898 frame_addr = sp + offset;
2899 frame_adjust = offset;
2902 else if (sreg != 28 || dreg != 28)
2903 /* (D)ADDIU $gp, imm */
2904 this_non_prologue_insn = 1;
2907 /* LUI $v1 is used for larger $sp adjustments. */
2908 /* Discard LUI $gp is used for PIC code. */
2909 case 0x10: /* POOL32I: bits 010000 */
2910 if (b5s5_op (insn >> 16) == 0xd
2911 /* LUI: bits 010000 001101 */
2912 && b0s5_reg (insn >> 16) == 3)
2914 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000;
2915 else if (b5s5_op (insn >> 16) != 0xd
2916 /* LUI: bits 010000 001101 */
2917 || b0s5_reg (insn >> 16) != 28)
2919 this_non_prologue_insn = 1;
2922 /* ORI $v1 is used for larger $sp adjustments. */
2923 case 0x14: /* ORI: bits 010100 */
2924 sreg = b0s5_reg (insn >> 16);
2925 dreg = b5s5_reg (insn >> 16);
2926 if (sreg == 3 && dreg == 3)
2928 v1_off |= b0s16_imm (insn);
2930 this_non_prologue_insn = 1;
2933 case 0x26: /* SWC1: bits 100110 */
2934 case 0x2e: /* SDC1: bits 101110 */
2935 breg = b0s5_reg (insn >> 16);
2936 if (breg != MIPS_SP_REGNUM)
2937 /* S[DW]C1 reg,offset($sp) */
2938 this_non_prologue_insn = 1;
2941 case 0x36: /* SD: bits 110110 */
2942 case 0x3e: /* SW: bits 111110 */
2943 breg = b0s5_reg (insn >> 16);
2944 sreg = b5s5_reg (insn >> 16);
2945 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
2946 if (breg == MIPS_SP_REGNUM)
2947 /* S[DW] reg,offset($sp) */
2948 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
2950 this_non_prologue_insn = 1;
2954 this_non_prologue_insn = 1;
2959 /* 16-bit instructions. */
2960 case MIPS_INSN16_SIZE:
2961 switch (micromips_op (insn))
2963 case 0x3: /* MOVE: bits 000011 */
2964 sreg = b0s5_reg (insn);
2965 dreg = b5s5_reg (insn);
2966 if (sreg == MIPS_SP_REGNUM && dreg == 30)
2972 else if ((sreg & 0x1c) != 0x4)
2973 /* MOVE reg, $a0-$a3 */
2974 this_non_prologue_insn = 1;
2977 case 0x11: /* POOL16C: bits 010001 */
2978 if (b6s4_op (insn) == 0x5)
2979 /* SWM: bits 010001 0101 */
2981 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20;
2982 reglist = b4s2_regl (insn);
2983 for (i = 0; i <= reglist; i++)
2984 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i);
2985 set_reg_offset (gdbarch, this_cache,
2986 MIPS_RA_REGNUM, sp + 4 * i++);
2989 this_non_prologue_insn = 1;
2992 case 0x13: /* POOL16D: bits 010011 */
2993 if ((insn & 0x1) == 0x1)
2994 /* ADDIUSP: bits 010011 1 */
2995 sp_adj = micromips_decode_imm9 (b1s9_imm (insn));
2996 else if (b5s5_reg (insn) == MIPS_SP_REGNUM)
2997 /* ADDIUS5: bits 010011 0 */
2998 /* ADDIUS5 $sp, imm */
2999 sp_adj = (b1s4_imm (insn) ^ 8) - 8;
3001 this_non_prologue_insn = 1;
3004 case 0x32: /* SWSP: bits 110010 */
3005 offset = b0s5_imm (insn) << 2;
3006 sreg = b5s5_reg (insn);
3007 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
3011 this_non_prologue_insn = 1;
3017 frame_offset -= sp_adj;
3019 non_prologue_insns += this_non_prologue_insn;
3020 /* Enough non-prologue insns seen or positive stack adjustment? */
3021 if (end_prologue_addr == 0 && (non_prologue_insns > 1 || sp_adj > 0))
3023 end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc;
3026 prev_non_prologue_insn = this_non_prologue_insn;
3030 if (this_cache != NULL)
3033 (get_frame_register_signed (this_frame,
3034 gdbarch_num_regs (gdbarch) + frame_reg)
3035 + frame_offset - frame_adjust);
3036 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3037 be able to get rid of the assignment below, evetually. But it's
3038 still needed for now. */
3039 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3040 + mips_regnum (gdbarch)->pc]
3041 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
3044 /* If we didn't reach the end of the prologue when scanning the function
3045 instructions, then set end_prologue_addr to the address of the
3046 instruction immediately after the last one we scanned. Unless the
3047 last one looked like a non-prologue instruction (and we looked ahead),
3048 in which case use its address instead. */
3049 if (end_prologue_addr == 0)
3050 end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc;
3052 return end_prologue_addr;
3055 /* Heuristic unwinder for procedures using microMIPS instructions.
3056 Procedures that use the 32-bit instruction set are handled by the
3057 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3059 static struct mips_frame_cache *
3060 mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache)
3062 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3063 struct mips_frame_cache *cache;
3065 if ((*this_cache) != NULL)
3066 return (*this_cache);
3068 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3069 (*this_cache) = cache;
3070 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3072 /* Analyze the function prologue. */
3074 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3075 CORE_ADDR start_addr;
3077 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3078 if (start_addr == 0)
3079 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc);
3080 /* We can't analyze the prologue if we couldn't find the begining
3082 if (start_addr == 0)
3085 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
3088 /* gdbarch_sp_regnum contains the value and not the address. */
3089 trad_frame_set_value (cache->saved_regs,
3090 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3093 return (*this_cache);
3097 mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache,
3098 struct frame_id *this_id)
3100 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3102 /* This marks the outermost frame. */
3103 if (info->base == 0)
3105 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3108 static struct value *
3109 mips_micro_frame_prev_register (struct frame_info *this_frame,
3110 void **this_cache, int regnum)
3112 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3114 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3118 mips_micro_frame_sniffer (const struct frame_unwind *self,
3119 struct frame_info *this_frame, void **this_cache)
3121 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3122 CORE_ADDR pc = get_frame_pc (this_frame);
3124 if (mips_pc_is_micromips (gdbarch, pc))
3129 static const struct frame_unwind mips_micro_frame_unwind =
3132 default_frame_unwind_stop_reason,
3133 mips_micro_frame_this_id,
3134 mips_micro_frame_prev_register,
3136 mips_micro_frame_sniffer
3140 mips_micro_frame_base_address (struct frame_info *this_frame,
3143 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3148 static const struct frame_base mips_micro_frame_base =
3150 &mips_micro_frame_unwind,
3151 mips_micro_frame_base_address,
3152 mips_micro_frame_base_address,
3153 mips_micro_frame_base_address
3156 static const struct frame_base *
3157 mips_micro_frame_base_sniffer (struct frame_info *this_frame)
3159 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3160 CORE_ADDR pc = get_frame_pc (this_frame);
3162 if (mips_pc_is_micromips (gdbarch, pc))
3163 return &mips_micro_frame_base;
3168 /* Mark all the registers as unset in the saved_regs array
3169 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3172 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
3174 if (this_cache == NULL || this_cache->saved_regs == NULL)
3178 const int num_regs = gdbarch_num_regs (gdbarch);
3181 for (i = 0; i < num_regs; i++)
3183 this_cache->saved_regs[i].addr = -1;
3188 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3189 the associated FRAME_CACHE if not null.
3190 Return the address of the first instruction past the prologue. */
3193 mips32_scan_prologue (struct gdbarch *gdbarch,
3194 CORE_ADDR start_pc, CORE_ADDR limit_pc,
3195 struct frame_info *this_frame,
3196 struct mips_frame_cache *this_cache)
3199 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for
3203 int frame_reg = MIPS_SP_REGNUM;
3205 CORE_ADDR end_prologue_addr = 0;
3206 int seen_sp_adjust = 0;
3207 int load_immediate_bytes = 0;
3208 int in_delay_slot = 0;
3209 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
3211 /* Can be called when there's no process, and hence when there's no
3213 if (this_frame != NULL)
3214 sp = get_frame_register_signed (this_frame,
3215 gdbarch_num_regs (gdbarch)
3220 if (limit_pc > start_pc + 200)
3221 limit_pc = start_pc + 200;
3226 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
3228 unsigned long inst, high_word, low_word;
3231 /* Fetch the instruction. */
3232 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS,
3235 /* Save some code by pre-extracting some useful fields. */
3236 high_word = (inst >> 16) & 0xffff;
3237 low_word = inst & 0xffff;
3238 reg = high_word & 0x1f;
3240 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
3241 || high_word == 0x23bd /* addi $sp,$sp,-i */
3242 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
3244 if (low_word & 0x8000) /* Negative stack adjustment? */
3245 frame_offset += 0x10000 - low_word;
3247 /* Exit loop if a positive stack adjustment is found, which
3248 usually means that the stack cleanup code in the function
3249 epilogue is reached. */
3253 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3254 && !regsize_is_64_bits)
3256 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
3258 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3259 && regsize_is_64_bits)
3261 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3262 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
3264 else if (high_word == 0x27be) /* addiu $30,$sp,size */
3266 /* Old gcc frame, r30 is virtual frame pointer. */
3267 if ((long) low_word != frame_offset)
3268 frame_addr = sp + low_word;
3269 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
3271 unsigned alloca_adjust;
3274 frame_addr = get_frame_register_signed
3275 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3277 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
3278 if (alloca_adjust > 0)
3280 /* FP > SP + frame_size. This may be because of
3281 an alloca or somethings similar. Fix sp to
3282 "pre-alloca" value, and try again. */
3283 sp += alloca_adjust;
3284 /* Need to reset the status of all registers. Otherwise,
3285 we will hit a guard that prevents the new address
3286 for each register to be recomputed during the second
3288 reset_saved_regs (gdbarch, this_cache);
3293 /* move $30,$sp. With different versions of gas this will be either
3294 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3295 Accept any one of these. */
3296 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3298 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3299 if (this_frame && frame_reg == MIPS_SP_REGNUM)
3301 unsigned alloca_adjust;
3304 frame_addr = get_frame_register_signed
3305 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3307 alloca_adjust = (unsigned) (frame_addr - sp);
3308 if (alloca_adjust > 0)
3310 /* FP > SP + frame_size. This may be because of
3311 an alloca or somethings similar. Fix sp to
3312 "pre-alloca" value, and try again. */
3314 /* Need to reset the status of all registers. Otherwise,
3315 we will hit a guard that prevents the new address
3316 for each register to be recomputed during the second
3318 reset_saved_regs (gdbarch, this_cache);
3323 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3324 && !regsize_is_64_bits)
3326 set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word);
3328 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3329 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3330 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3331 || high_word == 0x3c1c /* lui $gp,n */
3332 || high_word == 0x279c /* addiu $gp,$gp,n */
3333 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3334 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
3337 /* These instructions are part of the prologue, but we don't
3338 need to do anything special to handle them. */
3340 /* The instructions below load $at or $t0 with an immediate
3341 value in preparation for a stack adjustment via
3342 subu $sp,$sp,[$at,$t0]. These instructions could also
3343 initialize a local variable, so we accept them only before
3344 a stack adjustment instruction was seen. */
3345 else if (!seen_sp_adjust
3346 && (high_word == 0x3c01 /* lui $at,n */
3347 || high_word == 0x3c08 /* lui $t0,n */
3348 || high_word == 0x3421 /* ori $at,$at,n */
3349 || high_word == 0x3508 /* ori $t0,$t0,n */
3350 || high_word == 0x3401 /* ori $at,$zero,n */
3351 || high_word == 0x3408 /* ori $t0,$zero,n */
3354 if (end_prologue_addr == 0)
3355 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
3359 /* This instruction is not an instruction typically found
3360 in a prologue, so we must have reached the end of the
3362 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3363 loop now? Why would we need to continue scanning the function
3365 if (end_prologue_addr == 0)
3366 end_prologue_addr = cur_pc;
3368 /* Check for branches and jumps. For now, only jump to
3369 register are caught (i.e. returns). */
3370 if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8)
3374 /* If the previous instruction was a jump, we must have reached
3375 the end of the prologue by now. Stop scanning so that we do
3376 not go past the function return. */
3381 if (this_cache != NULL)
3384 (get_frame_register_signed (this_frame,
3385 gdbarch_num_regs (gdbarch) + frame_reg)
3387 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3388 this assignment below, eventually. But it's still needed
3390 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3391 + mips_regnum (gdbarch)->pc]
3392 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3396 /* If we didn't reach the end of the prologue when scanning the function
3397 instructions, then set end_prologue_addr to the address of the
3398 instruction immediately after the last one we scanned. */
3399 /* brobecker/2004-10-10: I don't think this would ever happen, but
3400 we may as well be careful and do our best if we have a null
3401 end_prologue_addr. */
3402 if (end_prologue_addr == 0)
3403 end_prologue_addr = cur_pc;
3405 /* In a frameless function, we might have incorrectly
3406 skipped some load immediate instructions. Undo the skipping
3407 if the load immediate was not followed by a stack adjustment. */
3408 if (load_immediate_bytes && !seen_sp_adjust)
3409 end_prologue_addr -= load_immediate_bytes;
3411 return end_prologue_addr;
3414 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3415 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3416 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3417 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3419 static struct mips_frame_cache *
3420 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
3422 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3423 struct mips_frame_cache *cache;
3425 if ((*this_cache) != NULL)
3426 return (*this_cache);
3428 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3429 (*this_cache) = cache;
3430 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3432 /* Analyze the function prologue. */
3434 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3435 CORE_ADDR start_addr;
3437 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3438 if (start_addr == 0)
3439 start_addr = heuristic_proc_start (gdbarch, pc);
3440 /* We can't analyze the prologue if we couldn't find the begining
3442 if (start_addr == 0)
3445 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
3448 /* gdbarch_sp_regnum contains the value and not the address. */
3449 trad_frame_set_value (cache->saved_regs,
3450 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3453 return (*this_cache);
3457 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
3458 struct frame_id *this_id)
3460 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3462 /* This marks the outermost frame. */
3463 if (info->base == 0)
3465 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3468 static struct value *
3469 mips_insn32_frame_prev_register (struct frame_info *this_frame,
3470 void **this_cache, int regnum)
3472 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3474 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3478 mips_insn32_frame_sniffer (const struct frame_unwind *self,
3479 struct frame_info *this_frame, void **this_cache)
3481 CORE_ADDR pc = get_frame_pc (this_frame);
3482 if (mips_pc_is_mips (pc))
3487 static const struct frame_unwind mips_insn32_frame_unwind =
3490 default_frame_unwind_stop_reason,
3491 mips_insn32_frame_this_id,
3492 mips_insn32_frame_prev_register,
3494 mips_insn32_frame_sniffer
3498 mips_insn32_frame_base_address (struct frame_info *this_frame,
3501 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3506 static const struct frame_base mips_insn32_frame_base =
3508 &mips_insn32_frame_unwind,
3509 mips_insn32_frame_base_address,
3510 mips_insn32_frame_base_address,
3511 mips_insn32_frame_base_address
3514 static const struct frame_base *
3515 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
3517 CORE_ADDR pc = get_frame_pc (this_frame);
3518 if (mips_pc_is_mips (pc))
3519 return &mips_insn32_frame_base;
3524 static struct trad_frame_cache *
3525 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
3528 CORE_ADDR start_addr;
3529 CORE_ADDR stack_addr;
3530 struct trad_frame_cache *this_trad_cache;
3531 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3532 int num_regs = gdbarch_num_regs (gdbarch);
3534 if ((*this_cache) != NULL)
3535 return (*this_cache);
3536 this_trad_cache = trad_frame_cache_zalloc (this_frame);
3537 (*this_cache) = this_trad_cache;
3539 /* The return address is in the link register. */
3540 trad_frame_set_reg_realreg (this_trad_cache,
3541 gdbarch_pc_regnum (gdbarch),
3542 num_regs + MIPS_RA_REGNUM);
3544 /* Frame ID, since it's a frameless / stackless function, no stack
3545 space is allocated and SP on entry is the current SP. */
3546 pc = get_frame_pc (this_frame);
3547 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3548 stack_addr = get_frame_register_signed (this_frame,
3549 num_regs + MIPS_SP_REGNUM);
3550 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
3552 /* Assume that the frame's base is the same as the
3554 trad_frame_set_this_base (this_trad_cache, stack_addr);
3556 return this_trad_cache;
3560 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
3561 struct frame_id *this_id)
3563 struct trad_frame_cache *this_trad_cache
3564 = mips_stub_frame_cache (this_frame, this_cache);
3565 trad_frame_get_id (this_trad_cache, this_id);
3568 static struct value *
3569 mips_stub_frame_prev_register (struct frame_info *this_frame,
3570 void **this_cache, int regnum)
3572 struct trad_frame_cache *this_trad_cache
3573 = mips_stub_frame_cache (this_frame, this_cache);
3574 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
3578 mips_stub_frame_sniffer (const struct frame_unwind *self,
3579 struct frame_info *this_frame, void **this_cache)
3582 struct obj_section *s;
3583 CORE_ADDR pc = get_frame_address_in_block (this_frame);
3584 struct minimal_symbol *msym;
3586 /* Use the stub unwinder for unreadable code. */
3587 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
3590 if (in_plt_section (pc, NULL))
3593 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
3594 s = find_pc_section (pc);
3597 && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
3598 ".MIPS.stubs") == 0)
3601 /* Calling a PIC function from a non-PIC function passes through a
3602 stub. The stub for foo is named ".pic.foo". */
3603 msym = lookup_minimal_symbol_by_pc (pc);
3605 && SYMBOL_LINKAGE_NAME (msym) != NULL
3606 && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0)
3612 static const struct frame_unwind mips_stub_frame_unwind =
3615 default_frame_unwind_stop_reason,
3616 mips_stub_frame_this_id,
3617 mips_stub_frame_prev_register,
3619 mips_stub_frame_sniffer
3623 mips_stub_frame_base_address (struct frame_info *this_frame,
3626 struct trad_frame_cache *this_trad_cache
3627 = mips_stub_frame_cache (this_frame, this_cache);
3628 return trad_frame_get_this_base (this_trad_cache);
3631 static const struct frame_base mips_stub_frame_base =
3633 &mips_stub_frame_unwind,
3634 mips_stub_frame_base_address,
3635 mips_stub_frame_base_address,
3636 mips_stub_frame_base_address
3639 static const struct frame_base *
3640 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
3642 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
3643 return &mips_stub_frame_base;
3648 /* mips_addr_bits_remove - remove useless address bits */
3651 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
3653 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3655 if (is_compact_addr (addr))
3656 addr = unmake_compact_addr (addr);
3658 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
3659 /* This hack is a work-around for existing boards using PMON, the
3660 simulator, and any other 64-bit targets that doesn't have true
3661 64-bit addressing. On these targets, the upper 32 bits of
3662 addresses are ignored by the hardware. Thus, the PC or SP are
3663 likely to have been sign extended to all 1s by instruction
3664 sequences that load 32-bit addresses. For example, a typical
3665 piece of code that loads an address is this:
3667 lui $r2, <upper 16 bits>
3668 ori $r2, <lower 16 bits>
3670 But the lui sign-extends the value such that the upper 32 bits
3671 may be all 1s. The workaround is simply to mask off these
3672 bits. In the future, gcc may be changed to support true 64-bit
3673 addressing, and this masking will have to be disabled. */
3674 return addr &= 0xffffffffUL;
3680 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3681 instruction and ending with a SC/SCD instruction. If such a sequence
3682 is found, attempt to step through it. A breakpoint is placed at the end of
3685 /* Instructions used during single-stepping of atomic sequences, standard
3687 #define LL_OPCODE 0x30
3688 #define LLD_OPCODE 0x34
3689 #define SC_OPCODE 0x38
3690 #define SCD_OPCODE 0x3c
3693 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
3694 struct address_space *aspace, CORE_ADDR pc)
3696 CORE_ADDR breaks[2] = {-1, -1};
3698 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
3702 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
3703 const int atomic_sequence_length = 16; /* Instruction sequence length. */
3705 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3706 /* Assume all atomic sequences start with a ll/lld instruction. */
3707 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
3710 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3712 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
3715 loc += MIPS_INSN32_SIZE;
3716 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3718 /* Assume that there is at most one branch in the atomic
3719 sequence. If a branch is found, put a breakpoint in its
3720 destination address. */
3721 switch (itype_op (insn))
3723 case 0: /* SPECIAL */
3724 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
3725 return 0; /* fallback to the standard single-step code. */
3727 case 1: /* REGIMM */
3728 is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */
3729 || ((itype_rt (insn) & 0x1e) == 0
3730 && itype_rs (insn) == 0)); /* BPOSGE* */
3734 return 0; /* fallback to the standard single-step code. */
3741 case 22: /* BLEZL */
3742 case 23: /* BGTTL */
3746 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10)
3747 && (itype_rt (insn) & 0x2) == 0);
3748 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3753 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3758 branch_bp = loc + mips32_relative_offset (insn) + 4;
3759 if (last_breakpoint >= 1)
3760 return 0; /* More than one branch found, fallback to the
3761 standard single-step code. */
3762 breaks[1] = branch_bp;
3766 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
3770 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3771 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
3774 loc += MIPS_INSN32_SIZE;
3776 /* Insert a breakpoint right after the end of the atomic sequence. */
3779 /* Check for duplicated breakpoints. Check also for a breakpoint
3780 placed (branch instruction's destination) in the atomic sequence. */
3781 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
3782 last_breakpoint = 0;
3784 /* Effectively inserts the breakpoints. */
3785 for (index = 0; index <= last_breakpoint; index++)
3786 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
3792 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
3793 struct address_space *aspace,
3796 const int atomic_sequence_length = 16; /* Instruction sequence length. */
3797 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
3798 CORE_ADDR breaks[2] = {-1, -1};
3799 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
3806 /* Assume all atomic sequences start with a ll/lld instruction. */
3807 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
3808 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */
3810 loc += MIPS_INSN16_SIZE;
3812 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
3813 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3815 loc += MIPS_INSN16_SIZE;
3817 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3818 that no atomic sequence is longer than "atomic_sequence_length"
3820 for (insn_count = 0;
3821 !sc_found && insn_count < atomic_sequence_length;
3826 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
3827 loc += MIPS_INSN16_SIZE;
3829 /* Assume that there is at most one conditional branch in the
3830 atomic sequence. If a branch is found, put a breakpoint in
3831 its destination address. */
3832 switch (mips_insn_size (ISA_MICROMIPS, insn))
3834 /* 48-bit instructions. */
3835 case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
3836 loc += 2 * MIPS_INSN16_SIZE;
3839 /* 32-bit instructions. */
3840 case 2 * MIPS_INSN16_SIZE:
3841 switch (micromips_op (insn))
3843 case 0x10: /* POOL32I: bits 010000 */
3844 if ((b5s5_op (insn) & 0x18) != 0x0
3845 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3846 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3847 && (b5s5_op (insn) & 0x1d) != 0x11
3848 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3849 && ((b5s5_op (insn) & 0x1e) != 0x14
3850 || (insn & 0x3) != 0x0)
3851 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3852 && (b5s5_op (insn) & 0x1e) != 0x1a
3853 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3854 && ((b5s5_op (insn) & 0x1e) != 0x1c
3855 || (insn & 0x3) != 0x0)
3856 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3857 && ((b5s5_op (insn) & 0x1c) != 0x1c
3858 || (insn & 0x3) != 0x1))
3859 /* BC1ANY*: bits 010000 111xx xxx01 */
3863 case 0x25: /* BEQ: bits 100101 */
3864 case 0x2d: /* BNE: bits 101101 */
3866 insn |= mips_fetch_instruction (gdbarch,
3867 ISA_MICROMIPS, loc, NULL);
3868 branch_bp = (loc + MIPS_INSN16_SIZE
3869 + micromips_relative_offset16 (insn));
3873 case 0x00: /* POOL32A: bits 000000 */
3875 insn |= mips_fetch_instruction (gdbarch,
3876 ISA_MICROMIPS, loc, NULL);
3877 if (b0s6_op (insn) != 0x3c
3878 /* POOL32Axf: bits 000000 ... 111100 */
3879 || (b6s10_ext (insn) & 0x2bf) != 0x3c)
3880 /* JALR, JALR.HB: 000000 000x111100 111100 */
3881 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3885 case 0x1d: /* JALS: bits 011101 */
3886 case 0x35: /* J: bits 110101 */
3887 case 0x3d: /* JAL: bits 111101 */
3888 case 0x3c: /* JALX: bits 111100 */
3889 return 0; /* Fall back to the standard single-step code. */
3891 case 0x18: /* POOL32C: bits 011000 */
3892 if ((b12s4_op (insn) & 0xb) == 0xb)
3893 /* SC, SCD: bits 011000 1x11 */
3897 loc += MIPS_INSN16_SIZE;
3900 /* 16-bit instructions. */
3901 case MIPS_INSN16_SIZE:
3902 switch (micromips_op (insn))
3904 case 0x23: /* BEQZ16: bits 100011 */
3905 case 0x2b: /* BNEZ16: bits 101011 */
3906 branch_bp = loc + micromips_relative_offset7 (insn);
3910 case 0x11: /* POOL16C: bits 010001 */
3911 if ((b5s5_op (insn) & 0x1c) != 0xc
3912 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3913 && b5s5_op (insn) != 0x18)
3914 /* JRADDIUSP: bits 010001 11000 */
3916 return 0; /* Fall back to the standard single-step code. */
3918 case 0x33: /* B16: bits 110011 */
3919 return 0; /* Fall back to the standard single-step code. */
3925 if (last_breakpoint >= 1)
3926 return 0; /* More than one branch found, fallback to the
3927 standard single-step code. */
3928 breaks[1] = branch_bp;
3935 /* Insert a breakpoint right after the end of the atomic sequence. */
3938 /* Check for duplicated breakpoints. Check also for a breakpoint
3939 placed (branch instruction's destination) in the atomic sequence */
3940 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
3941 last_breakpoint = 0;
3943 /* Effectively inserts the breakpoints. */
3944 for (index = 0; index <= last_breakpoint; index++)
3945 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
3951 deal_with_atomic_sequence (struct gdbarch *gdbarch,
3952 struct address_space *aspace, CORE_ADDR pc)
3954 if (mips_pc_is_mips (pc))
3955 return mips_deal_with_atomic_sequence (gdbarch, aspace, pc);
3956 else if (mips_pc_is_micromips (gdbarch, pc))
3957 return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc);
3962 /* mips_software_single_step() is called just before we want to resume
3963 the inferior, if we want to single-step it but there is no hardware
3964 or kernel single-step support (MIPS on GNU/Linux for example). We find
3965 the target of the coming instruction and breakpoint it. */
3968 mips_software_single_step (struct frame_info *frame)
3970 struct gdbarch *gdbarch = get_frame_arch (frame);
3971 struct address_space *aspace = get_frame_address_space (frame);
3972 CORE_ADDR pc, next_pc;
3974 pc = get_frame_pc (frame);
3975 if (deal_with_atomic_sequence (gdbarch, aspace, pc))
3978 next_pc = mips_next_pc (frame, pc);
3980 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
3984 /* Test whether the PC points to the return instruction at the
3985 end of a function. */
3988 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
3993 /* This used to check for MIPS16, but this piece of code is never
3994 called for MIPS16 functions. And likewise microMIPS ones. */
3995 gdb_assert (mips_pc_is_mips (pc));
3997 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
3999 return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */
4003 /* This fencepost looks highly suspicious to me. Removing it also
4004 seems suspicious as it could affect remote debugging across serial
4008 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
4014 struct inferior *inf;
4016 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4018 fence = start_pc - heuristic_fence_post;
4022 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
4023 fence = VM_MIN_ADDRESS;
4025 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE;
4027 inf = current_inferior ();
4029 /* Search back for previous return. */
4030 for (start_pc -= instlen;; start_pc -= instlen)
4031 if (start_pc < fence)
4033 /* It's not clear to me why we reach this point when
4034 stop_soon, but with this test, at least we
4035 don't print out warnings for every child forked (eg, on
4036 decstation). 22apr93 rich@cygnus.com. */
4037 if (inf->control.stop_soon == NO_STOP_QUIETLY)
4039 static int blurb_printed = 0;
4041 warning (_("GDB can't find the start of the function at %s."),
4042 paddress (gdbarch, pc));
4046 /* This actually happens frequently in embedded
4047 development, when you first connect to a board
4048 and your stack pointer and pc are nowhere in
4049 particular. This message needs to give people
4050 in that situation enough information to
4051 determine that it's no big deal. */
4052 printf_filtered ("\n\
4053 GDB is unable to find the start of the function at %s\n\
4054 and thus can't determine the size of that function's stack frame.\n\
4055 This means that GDB may be unable to access that stack frame, or\n\
4056 the frames below it.\n\
4057 This problem is most likely caused by an invalid program counter or\n\
4059 However, if you think GDB should simply search farther back\n\
4060 from %s for code which looks like the beginning of a\n\
4061 function, you can increase the range of the search using the `set\n\
4062 heuristic-fence-post' command.\n",
4063 paddress (gdbarch, pc), paddress (gdbarch, pc));
4070 else if (mips_pc_is_mips16 (gdbarch, start_pc))
4072 unsigned short inst;
4074 /* On MIPS16, any one of the following is likely to be the
4075 start of a function:
4081 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4082 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL);
4083 if ((inst & 0xff80) == 0x6480) /* save */
4085 if (start_pc - instlen >= fence)
4087 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16,
4088 start_pc - instlen, NULL);
4089 if ((inst & 0xf800) == 0xf000) /* extend */
4090 start_pc -= instlen;
4094 else if (((inst & 0xf81f) == 0xe809
4095 && (inst & 0x700) != 0x700) /* entry */
4096 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
4097 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
4098 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
4100 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
4101 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
4106 else if (mips_pc_is_micromips (gdbarch, start_pc))
4114 /* On microMIPS, any one of the following is likely to be the
4115 start of a function:
4119 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
4120 switch (micromips_op (insn))
4122 case 0xc: /* ADDIU: bits 001100 */
4123 case 0x17: /* DADDIU: bits 010111 */
4124 sreg = b0s5_reg (insn);
4125 dreg = b5s5_reg (insn);
4127 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS,
4128 pc + MIPS_INSN16_SIZE, NULL);
4129 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
4130 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
4131 /* (D)ADDIU $sp, imm */
4136 case 0x10: /* POOL32I: bits 010000 */
4137 if (b5s5_op (insn) == 0xd
4138 /* LUI: bits 010000 001101 */
4139 && b0s5_reg (insn >> 16) == 28)
4144 case 0x13: /* POOL16D: bits 010011 */
4145 if ((insn & 0x1) == 0x1)
4146 /* ADDIUSP: bits 010011 1 */
4148 offset = micromips_decode_imm9 (b1s9_imm (insn));
4154 /* ADDIUS5: bits 010011 0 */
4156 dreg = b5s5_reg (insn);
4157 offset = (b1s4_imm (insn) ^ 8) - 8;
4158 if (dreg == MIPS_SP_REGNUM && offset < 0)
4159 /* ADDIUS5 $sp, -imm */
4167 else if (mips_about_to_return (gdbarch, start_pc))
4169 /* Skip return and its delay slot. */
4170 start_pc += 2 * MIPS_INSN32_SIZE;
4177 struct mips_objfile_private
4183 /* According to the current ABI, should the type be passed in a
4184 floating-point register (assuming that there is space)? When there
4185 is no FPU, FP are not even considered as possible candidates for
4186 FP registers and, consequently this returns false - forces FP
4187 arguments into integer registers. */
4190 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
4191 struct type *arg_type)
4193 return ((typecode == TYPE_CODE_FLT
4194 || (MIPS_EABI (gdbarch)
4195 && (typecode == TYPE_CODE_STRUCT
4196 || typecode == TYPE_CODE_UNION)
4197 && TYPE_NFIELDS (arg_type) == 1
4198 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
4200 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
4203 /* On o32, argument passing in GPRs depends on the alignment of the type being
4204 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4207 mips_type_needs_double_align (struct type *type)
4209 enum type_code typecode = TYPE_CODE (type);
4211 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
4213 else if (typecode == TYPE_CODE_STRUCT)
4215 if (TYPE_NFIELDS (type) < 1)
4217 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
4219 else if (typecode == TYPE_CODE_UNION)
4223 n = TYPE_NFIELDS (type);
4224 for (i = 0; i < n; i++)
4225 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
4232 /* Adjust the address downward (direction of stack growth) so that it
4233 is correctly aligned for a new stack frame. */
4235 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
4237 return align_down (addr, 16);
4240 /* Implement the "push_dummy_code" gdbarch method. */
4243 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
4244 CORE_ADDR funaddr, struct value **args,
4245 int nargs, struct type *value_type,
4246 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
4247 struct regcache *regcache)
4249 static gdb_byte nop_insn[] = { 0, 0, 0, 0 };
4253 /* Reserve enough room on the stack for our breakpoint instruction. */
4254 bp_slot = sp - sizeof (nop_insn);
4256 /* Return to microMIPS mode if calling microMIPS code to avoid
4257 triggering an address error exception on processors that only
4258 support microMIPS execution. */
4259 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr)
4260 ? make_compact_addr (bp_slot) : bp_slot);
4262 /* The breakpoint layer automatically adjusts the address of
4263 breakpoints inserted in a branch delay slot. With enough
4264 bad luck, the 4 bytes located just before our breakpoint
4265 instruction could look like a branch instruction, and thus
4266 trigger the adjustement, and break the function call entirely.
4267 So, we reserve those 4 bytes and write a nop instruction
4268 to prevent that from happening. */
4269 nop_addr = bp_slot - sizeof (nop_insn);
4270 write_memory (nop_addr, nop_insn, sizeof (nop_insn));
4271 sp = mips_frame_align (gdbarch, nop_addr);
4273 /* Inferior resumes at the function entry point. */
4280 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4281 struct regcache *regcache, CORE_ADDR bp_addr,
4282 int nargs, struct value **args, CORE_ADDR sp,
4283 int struct_return, CORE_ADDR struct_addr)
4289 int stack_offset = 0;
4290 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4291 CORE_ADDR func_addr = find_function_addr (function, NULL);
4292 int regsize = mips_abi_regsize (gdbarch);
4294 /* For shared libraries, "t9" needs to point at the function
4296 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4298 /* Set the return address register to point to the entry point of
4299 the program, where a breakpoint lies in wait. */
4300 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4302 /* First ensure that the stack and structure return address (if any)
4303 are properly aligned. The stack has to be at least 64-bit
4304 aligned even on 32-bit machines, because doubles must be 64-bit
4305 aligned. For n32 and n64, stack frames need to be 128-bit
4306 aligned, so we round to this widest known alignment. */
4308 sp = align_down (sp, 16);
4309 struct_addr = align_down (struct_addr, 16);
4311 /* Now make space on the stack for the args. We allocate more
4312 than necessary for EABI, because the first few arguments are
4313 passed in registers, but that's OK. */
4314 for (argnum = 0; argnum < nargs; argnum++)
4315 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
4316 sp -= align_up (len, 16);
4319 fprintf_unfiltered (gdb_stdlog,
4320 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4321 paddress (gdbarch, sp), (long) align_up (len, 16));
4323 /* Initialize the integer and float register pointers. */
4324 argreg = MIPS_A0_REGNUM;
4325 float_argreg = mips_fpa0_regnum (gdbarch);
4327 /* The struct_return pointer occupies the first parameter-passing reg. */
4331 fprintf_unfiltered (gdb_stdlog,
4332 "mips_eabi_push_dummy_call: "
4333 "struct_return reg=%d %s\n",
4334 argreg, paddress (gdbarch, struct_addr));
4335 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4338 /* Now load as many as possible of the first arguments into
4339 registers, and push the rest onto the stack. Loop thru args
4340 from first to last. */
4341 for (argnum = 0; argnum < nargs; argnum++)
4343 const gdb_byte *val;
4344 gdb_byte valbuf[MAX_REGISTER_SIZE];
4345 struct value *arg = args[argnum];
4346 struct type *arg_type = check_typedef (value_type (arg));
4347 int len = TYPE_LENGTH (arg_type);
4348 enum type_code typecode = TYPE_CODE (arg_type);
4351 fprintf_unfiltered (gdb_stdlog,
4352 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4353 argnum + 1, len, (int) typecode);
4355 /* Function pointer arguments to mips16 code need to be made into
4357 if (typecode == TYPE_CODE_PTR
4358 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
4360 CORE_ADDR addr = extract_signed_integer (value_contents (arg),
4362 if (mips_pc_is_mips (addr))
4363 val = value_contents (arg);
4366 store_signed_integer (valbuf, len, byte_order,
4367 make_compact_addr (addr));
4371 /* The EABI passes structures that do not fit in a register by
4373 else if (len > regsize
4374 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
4376 store_unsigned_integer (valbuf, regsize, byte_order,
4377 value_address (arg));
4378 typecode = TYPE_CODE_PTR;
4382 fprintf_unfiltered (gdb_stdlog, " push");
4385 val = value_contents (arg);
4387 /* 32-bit ABIs always start floating point arguments in an
4388 even-numbered floating point register. Round the FP register
4389 up before the check to see if there are any FP registers
4390 left. Non MIPS_EABI targets also pass the FP in the integer
4391 registers so also round up normal registers. */
4392 if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
4394 if ((float_argreg & 1))
4398 /* Floating point arguments passed in registers have to be
4399 treated specially. On 32-bit architectures, doubles
4400 are passed in register pairs; the even register gets
4401 the low word, and the odd register gets the high word.
4402 On non-EABI processors, the first two floating point arguments are
4403 also copied to general registers, because MIPS16 functions
4404 don't use float registers for arguments. This duplication of
4405 arguments in general registers can't hurt non-MIPS16 functions
4406 because those registers are normally skipped. */
4407 /* MIPS_EABI squeezes a struct that contains a single floating
4408 point value into an FP register instead of pushing it onto the
4410 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4411 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4413 /* EABI32 will pass doubles in consecutive registers, even on
4414 64-bit cores. At one time, we used to check the size of
4415 `float_argreg' to determine whether or not to pass doubles
4416 in consecutive registers, but this is not sufficient for
4417 making the ABI determination. */
4418 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
4420 int low_offset = gdbarch_byte_order (gdbarch)
4421 == BFD_ENDIAN_BIG ? 4 : 0;
4424 /* Write the low word of the double to the even register(s). */
4425 regval = extract_signed_integer (val + low_offset,
4428 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4429 float_argreg, phex (regval, 4));
4430 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4432 /* Write the high word of the double to the odd register(s). */
4433 regval = extract_signed_integer (val + 4 - low_offset,
4436 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4437 float_argreg, phex (regval, 4));
4438 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4442 /* This is a floating point value that fits entirely
4443 in a single register. */
4444 /* On 32 bit ABI's the float_argreg is further adjusted
4445 above to ensure that it is even register aligned. */
4446 LONGEST regval = extract_signed_integer (val, len, byte_order);
4448 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4449 float_argreg, phex (regval, len));
4450 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4455 /* Copy the argument to general registers or the stack in
4456 register-sized pieces. Large arguments are split between
4457 registers and stack. */
4458 /* Note: structs whose size is not a multiple of regsize
4459 are treated specially: Irix cc passes
4460 them in registers where gcc sometimes puts them on the
4461 stack. For maximum compatibility, we will put them in
4463 int odd_sized_struct = (len > regsize && len % regsize != 0);
4465 /* Note: Floating-point values that didn't fit into an FP
4466 register are only written to memory. */
4469 /* Remember if the argument was written to the stack. */
4470 int stack_used_p = 0;
4471 int partial_len = (len < regsize ? len : regsize);
4474 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4477 /* Write this portion of the argument to the stack. */
4478 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4480 || fp_register_arg_p (gdbarch, typecode, arg_type))
4482 /* Should shorter than int integer values be
4483 promoted to int before being stored? */
4484 int longword_offset = 0;
4487 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4490 && (typecode == TYPE_CODE_INT
4491 || typecode == TYPE_CODE_PTR
4492 || typecode == TYPE_CODE_FLT) && len <= 4)
4493 longword_offset = regsize - len;
4494 else if ((typecode == TYPE_CODE_STRUCT
4495 || typecode == TYPE_CODE_UNION)
4496 && TYPE_LENGTH (arg_type) < regsize)
4497 longword_offset = regsize - len;
4502 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4503 paddress (gdbarch, stack_offset));
4504 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4505 paddress (gdbarch, longword_offset));
4508 addr = sp + stack_offset + longword_offset;
4513 fprintf_unfiltered (gdb_stdlog, " @%s ",
4514 paddress (gdbarch, addr));
4515 for (i = 0; i < partial_len; i++)
4517 fprintf_unfiltered (gdb_stdlog, "%02x",
4521 write_memory (addr, val, partial_len);
4524 /* Note!!! This is NOT an else clause. Odd sized
4525 structs may go thru BOTH paths. Floating point
4526 arguments will not. */
4527 /* Write this portion of the argument to a general
4528 purpose register. */
4529 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
4530 && !fp_register_arg_p (gdbarch, typecode, arg_type))
4533 extract_signed_integer (val, partial_len, byte_order);
4536 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4538 phex (regval, regsize));
4539 regcache_cooked_write_signed (regcache, argreg, regval);
4546 /* Compute the offset into the stack at which we will
4547 copy the next parameter.
4549 In the new EABI (and the NABI32), the stack_offset
4550 only needs to be adjusted when it has been used. */
4553 stack_offset += align_up (partial_len, regsize);
4557 fprintf_unfiltered (gdb_stdlog, "\n");
4560 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4562 /* Return adjusted stack pointer. */
4566 /* Determine the return value convention being used. */
4568 static enum return_value_convention
4569 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function,
4570 struct type *type, struct regcache *regcache,
4571 gdb_byte *readbuf, const gdb_byte *writebuf)
4573 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4574 int fp_return_type = 0;
4575 int offset, regnum, xfer;
4577 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
4578 return RETURN_VALUE_STRUCT_CONVENTION;
4580 /* Floating point type? */
4581 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
4583 if (TYPE_CODE (type) == TYPE_CODE_FLT)
4585 /* Structs with a single field of float type
4586 are returned in a floating point register. */
4587 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
4588 || TYPE_CODE (type) == TYPE_CODE_UNION)
4589 && TYPE_NFIELDS (type) == 1)
4591 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
4593 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
4600 /* A floating-point value belongs in the least significant part
4603 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4604 regnum = mips_regnum (gdbarch)->fp0;
4608 /* An integer value goes in V0/V1. */
4610 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
4611 regnum = MIPS_V0_REGNUM;
4614 offset < TYPE_LENGTH (type);
4615 offset += mips_abi_regsize (gdbarch), regnum++)
4617 xfer = mips_abi_regsize (gdbarch);
4618 if (offset + xfer > TYPE_LENGTH (type))
4619 xfer = TYPE_LENGTH (type) - offset;
4620 mips_xfer_register (gdbarch, regcache,
4621 gdbarch_num_regs (gdbarch) + regnum, xfer,
4622 gdbarch_byte_order (gdbarch), readbuf, writebuf,
4626 return RETURN_VALUE_REGISTER_CONVENTION;
4630 /* N32/N64 ABI stuff. */
4632 /* Search for a naturally aligned double at OFFSET inside a struct
4633 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4637 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
4642 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
4645 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
4648 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
4651 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
4654 struct type *field_type;
4656 /* We're only looking at normal fields. */
4657 if (field_is_static (&TYPE_FIELD (arg_type, i))
4658 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
4661 /* If we have gone past the offset, there is no double to pass. */
4662 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
4666 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
4668 /* If this field is entirely before the requested offset, go
4669 on to the next one. */
4670 if (pos + TYPE_LENGTH (field_type) <= offset)
4673 /* If this is our special aligned double, we can stop. */
4674 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
4675 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
4678 /* This field starts at or before the requested offset, and
4679 overlaps it. If it is a structure, recurse inwards. */
4680 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
4687 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4688 struct regcache *regcache, CORE_ADDR bp_addr,
4689 int nargs, struct value **args, CORE_ADDR sp,
4690 int struct_return, CORE_ADDR struct_addr)
4696 int stack_offset = 0;
4697 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4698 CORE_ADDR func_addr = find_function_addr (function, NULL);
4700 /* For shared libraries, "t9" needs to point at the function
4702 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4704 /* Set the return address register to point to the entry point of
4705 the program, where a breakpoint lies in wait. */
4706 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4708 /* First ensure that the stack and structure return address (if any)
4709 are properly aligned. The stack has to be at least 64-bit
4710 aligned even on 32-bit machines, because doubles must be 64-bit
4711 aligned. For n32 and n64, stack frames need to be 128-bit
4712 aligned, so we round to this widest known alignment. */
4714 sp = align_down (sp, 16);
4715 struct_addr = align_down (struct_addr, 16);
4717 /* Now make space on the stack for the args. */
4718 for (argnum = 0; argnum < nargs; argnum++)
4719 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
4720 sp -= align_up (len, 16);
4723 fprintf_unfiltered (gdb_stdlog,
4724 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4725 paddress (gdbarch, sp), (long) align_up (len, 16));
4727 /* Initialize the integer and float register pointers. */
4728 argreg = MIPS_A0_REGNUM;
4729 float_argreg = mips_fpa0_regnum (gdbarch);
4731 /* The struct_return pointer occupies the first parameter-passing reg. */
4735 fprintf_unfiltered (gdb_stdlog,
4736 "mips_n32n64_push_dummy_call: "
4737 "struct_return reg=%d %s\n",
4738 argreg, paddress (gdbarch, struct_addr));
4739 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4742 /* Now load as many as possible of the first arguments into
4743 registers, and push the rest onto the stack. Loop thru args
4744 from first to last. */
4745 for (argnum = 0; argnum < nargs; argnum++)
4747 const gdb_byte *val;
4748 struct value *arg = args[argnum];
4749 struct type *arg_type = check_typedef (value_type (arg));
4750 int len = TYPE_LENGTH (arg_type);
4751 enum type_code typecode = TYPE_CODE (arg_type);
4754 fprintf_unfiltered (gdb_stdlog,
4755 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4756 argnum + 1, len, (int) typecode);
4758 val = value_contents (arg);
4760 /* A 128-bit long double value requires an even-odd pair of
4761 floating-point registers. */
4763 && fp_register_arg_p (gdbarch, typecode, arg_type)
4764 && (float_argreg & 1))
4770 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4771 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4773 /* This is a floating point value that fits entirely
4774 in a single register or a pair of registers. */
4775 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4776 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
4778 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4779 float_argreg, phex (regval, reglen));
4780 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4783 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4784 argreg, phex (regval, reglen));
4785 regcache_cooked_write_unsigned (regcache, argreg, regval);
4790 regval = extract_unsigned_integer (val + reglen,
4791 reglen, byte_order);
4793 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4794 float_argreg, phex (regval, reglen));
4795 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4798 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4799 argreg, phex (regval, reglen));
4800 regcache_cooked_write_unsigned (regcache, argreg, regval);
4807 /* Copy the argument to general registers or the stack in
4808 register-sized pieces. Large arguments are split between
4809 registers and stack. */
4810 /* For N32/N64, structs, unions, or other composite types are
4811 treated as a sequence of doublewords, and are passed in integer
4812 or floating point registers as though they were simple scalar
4813 parameters to the extent that they fit, with any excess on the
4814 stack packed according to the normal memory layout of the
4816 The caller does not reserve space for the register arguments;
4817 the callee is responsible for reserving it if required. */
4818 /* Note: Floating-point values that didn't fit into an FP
4819 register are only written to memory. */
4822 /* Remember if the argument was written to the stack. */
4823 int stack_used_p = 0;
4824 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4827 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4830 if (fp_register_arg_p (gdbarch, typecode, arg_type))
4831 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
4833 /* Write this portion of the argument to the stack. */
4834 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
4836 /* Should shorter than int integer values be
4837 promoted to int before being stored? */
4838 int longword_offset = 0;
4841 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4843 if ((typecode == TYPE_CODE_INT
4844 || typecode == TYPE_CODE_PTR)
4846 longword_offset = MIPS64_REGSIZE - len;
4851 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4852 paddress (gdbarch, stack_offset));
4853 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4854 paddress (gdbarch, longword_offset));
4857 addr = sp + stack_offset + longword_offset;
4862 fprintf_unfiltered (gdb_stdlog, " @%s ",
4863 paddress (gdbarch, addr));
4864 for (i = 0; i < partial_len; i++)
4866 fprintf_unfiltered (gdb_stdlog, "%02x",
4870 write_memory (addr, val, partial_len);
4873 /* Note!!! This is NOT an else clause. Odd sized
4874 structs may go thru BOTH paths. */
4875 /* Write this portion of the argument to a general
4876 purpose register. */
4877 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4881 /* Sign extend pointers, 32-bit integers and signed
4882 16-bit and 8-bit integers; everything else is taken
4885 if ((partial_len == 4
4886 && (typecode == TYPE_CODE_PTR
4887 || typecode == TYPE_CODE_INT))
4889 && typecode == TYPE_CODE_INT
4890 && !TYPE_UNSIGNED (arg_type)))
4891 regval = extract_signed_integer (val, partial_len,
4894 regval = extract_unsigned_integer (val, partial_len,
4897 /* A non-floating-point argument being passed in a
4898 general register. If a struct or union, and if
4899 the remaining length is smaller than the register
4900 size, we have to adjust the register value on
4903 It does not seem to be necessary to do the
4904 same for integral types. */
4906 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
4907 && partial_len < MIPS64_REGSIZE
4908 && (typecode == TYPE_CODE_STRUCT
4909 || typecode == TYPE_CODE_UNION))
4910 regval <<= ((MIPS64_REGSIZE - partial_len)
4914 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4916 phex (regval, MIPS64_REGSIZE));
4917 regcache_cooked_write_unsigned (regcache, argreg, regval);
4919 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
4920 TYPE_LENGTH (arg_type) - len))
4923 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
4925 phex (regval, MIPS64_REGSIZE));
4926 regcache_cooked_write_unsigned (regcache, float_argreg,
4937 /* Compute the offset into the stack at which we will
4938 copy the next parameter.
4940 In N32 (N64?), the stack_offset only needs to be
4941 adjusted when it has been used. */
4944 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
4948 fprintf_unfiltered (gdb_stdlog, "\n");
4951 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4953 /* Return adjusted stack pointer. */
4957 static enum return_value_convention
4958 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function,
4959 struct type *type, struct regcache *regcache,
4960 gdb_byte *readbuf, const gdb_byte *writebuf)
4962 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4964 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4966 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4967 if needed), as appropriate for the type. Composite results (struct,
4968 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4971 * A struct with only one or two floating point fields is returned in $f0
4972 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4975 * Any other composite results of at most 128 bits are returned in
4976 $2 (first 64 bits) and $3 (remainder, if necessary).
4978 * Larger composite results are handled by converting the function to a
4979 procedure with an implicit first parameter, which is a pointer to an area
4980 reserved by the caller to receive the result. [The o32-bit ABI requires
4981 that all composite results be handled by conversion to implicit first
4982 parameters. The MIPS/SGI Fortran implementation has always made a
4983 specific exception to return COMPLEX results in the floating point
4986 if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
4987 return RETURN_VALUE_STRUCT_CONVENTION;
4988 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4989 && TYPE_LENGTH (type) == 16
4990 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4992 /* A 128-bit floating-point value fills both $f0 and $f2. The
4993 two registers are used in the same as memory order, so the
4994 eight bytes with the lower memory address are in $f0. */
4996 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
4997 mips_xfer_register (gdbarch, regcache,
4998 (gdbarch_num_regs (gdbarch)
4999 + mips_regnum (gdbarch)->fp0),
5000 8, gdbarch_byte_order (gdbarch),
5001 readbuf, writebuf, 0);
5002 mips_xfer_register (gdbarch, regcache,
5003 (gdbarch_num_regs (gdbarch)
5004 + mips_regnum (gdbarch)->fp0 + 2),
5005 8, gdbarch_byte_order (gdbarch),
5006 readbuf ? readbuf + 8 : readbuf,
5007 writebuf ? writebuf + 8 : writebuf, 0);
5008 return RETURN_VALUE_REGISTER_CONVENTION;
5010 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5011 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5013 /* A single or double floating-point value that fits in FP0. */
5015 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5016 mips_xfer_register (gdbarch, regcache,
5017 (gdbarch_num_regs (gdbarch)
5018 + mips_regnum (gdbarch)->fp0),
5020 gdbarch_byte_order (gdbarch),
5021 readbuf, writebuf, 0);
5022 return RETURN_VALUE_REGISTER_CONVENTION;
5024 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5025 && TYPE_NFIELDS (type) <= 2
5026 && TYPE_NFIELDS (type) >= 1
5027 && ((TYPE_NFIELDS (type) == 1
5028 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5030 || (TYPE_NFIELDS (type) == 2
5031 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5033 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
5034 == TYPE_CODE_FLT))))
5036 /* A struct that contains one or two floats. Each value is part
5037 in the least significant part of their floating point
5038 register (or GPR, for soft float). */
5041 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
5042 ? mips_regnum (gdbarch)->fp0
5044 field < TYPE_NFIELDS (type); field++, regnum += 2)
5046 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5049 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5051 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
5053 /* A 16-byte long double field goes in two consecutive
5055 mips_xfer_register (gdbarch, regcache,
5056 gdbarch_num_regs (gdbarch) + regnum,
5058 gdbarch_byte_order (gdbarch),
5059 readbuf, writebuf, offset);
5060 mips_xfer_register (gdbarch, regcache,
5061 gdbarch_num_regs (gdbarch) + regnum + 1,
5063 gdbarch_byte_order (gdbarch),
5064 readbuf, writebuf, offset + 8);
5067 mips_xfer_register (gdbarch, regcache,
5068 gdbarch_num_regs (gdbarch) + regnum,
5069 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5070 gdbarch_byte_order (gdbarch),
5071 readbuf, writebuf, offset);
5073 return RETURN_VALUE_REGISTER_CONVENTION;
5075 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5076 || TYPE_CODE (type) == TYPE_CODE_UNION
5077 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5079 /* A composite type. Extract the left justified value,
5080 regardless of the byte order. I.e. DO NOT USE
5084 for (offset = 0, regnum = MIPS_V0_REGNUM;
5085 offset < TYPE_LENGTH (type);
5086 offset += register_size (gdbarch, regnum), regnum++)
5088 int xfer = register_size (gdbarch, regnum);
5089 if (offset + xfer > TYPE_LENGTH (type))
5090 xfer = TYPE_LENGTH (type) - offset;
5092 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5093 offset, xfer, regnum);
5094 mips_xfer_register (gdbarch, regcache,
5095 gdbarch_num_regs (gdbarch) + regnum,
5096 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
5099 return RETURN_VALUE_REGISTER_CONVENTION;
5103 /* A scalar extract each part but least-significant-byte
5107 for (offset = 0, regnum = MIPS_V0_REGNUM;
5108 offset < TYPE_LENGTH (type);
5109 offset += register_size (gdbarch, regnum), regnum++)
5111 int xfer = register_size (gdbarch, regnum);
5112 if (offset + xfer > TYPE_LENGTH (type))
5113 xfer = TYPE_LENGTH (type) - offset;
5115 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5116 offset, xfer, regnum);
5117 mips_xfer_register (gdbarch, regcache,
5118 gdbarch_num_regs (gdbarch) + regnum,
5119 xfer, gdbarch_byte_order (gdbarch),
5120 readbuf, writebuf, offset);
5122 return RETURN_VALUE_REGISTER_CONVENTION;
5126 /* Which registers to use for passing floating-point values between
5127 function calls, one of floating-point, general and both kinds of
5128 registers. O32 and O64 use different register kinds for standard
5129 MIPS and MIPS16 code; to make the handling of cases where we may
5130 not know what kind of code is being used (e.g. no debug information)
5131 easier we sometimes use both kinds. */
5140 /* O32 ABI stuff. */
5143 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5144 struct regcache *regcache, CORE_ADDR bp_addr,
5145 int nargs, struct value **args, CORE_ADDR sp,
5146 int struct_return, CORE_ADDR struct_addr)
5152 int stack_offset = 0;
5153 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5154 CORE_ADDR func_addr = find_function_addr (function, NULL);
5156 /* For shared libraries, "t9" needs to point at the function
5158 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5160 /* Set the return address register to point to the entry point of
5161 the program, where a breakpoint lies in wait. */
5162 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5164 /* First ensure that the stack and structure return address (if any)
5165 are properly aligned. The stack has to be at least 64-bit
5166 aligned even on 32-bit machines, because doubles must be 64-bit
5167 aligned. For n32 and n64, stack frames need to be 128-bit
5168 aligned, so we round to this widest known alignment. */
5170 sp = align_down (sp, 16);
5171 struct_addr = align_down (struct_addr, 16);
5173 /* Now make space on the stack for the args. */
5174 for (argnum = 0; argnum < nargs; argnum++)
5176 struct type *arg_type = check_typedef (value_type (args[argnum]));
5177 int arglen = TYPE_LENGTH (arg_type);
5179 /* Align to double-word if necessary. */
5180 if (mips_type_needs_double_align (arg_type))
5181 len = align_up (len, MIPS32_REGSIZE * 2);
5182 /* Allocate space on the stack. */
5183 len += align_up (arglen, MIPS32_REGSIZE);
5185 sp -= align_up (len, 16);
5188 fprintf_unfiltered (gdb_stdlog,
5189 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5190 paddress (gdbarch, sp), (long) align_up (len, 16));
5192 /* Initialize the integer and float register pointers. */
5193 argreg = MIPS_A0_REGNUM;
5194 float_argreg = mips_fpa0_regnum (gdbarch);
5196 /* The struct_return pointer occupies the first parameter-passing reg. */
5200 fprintf_unfiltered (gdb_stdlog,
5201 "mips_o32_push_dummy_call: "
5202 "struct_return reg=%d %s\n",
5203 argreg, paddress (gdbarch, struct_addr));
5204 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5205 stack_offset += MIPS32_REGSIZE;
5208 /* Now load as many as possible of the first arguments into
5209 registers, and push the rest onto the stack. Loop thru args
5210 from first to last. */
5211 for (argnum = 0; argnum < nargs; argnum++)
5213 const gdb_byte *val;
5214 struct value *arg = args[argnum];
5215 struct type *arg_type = check_typedef (value_type (arg));
5216 int len = TYPE_LENGTH (arg_type);
5217 enum type_code typecode = TYPE_CODE (arg_type);
5220 fprintf_unfiltered (gdb_stdlog,
5221 "mips_o32_push_dummy_call: %d len=%d type=%d",
5222 argnum + 1, len, (int) typecode);
5224 val = value_contents (arg);
5226 /* 32-bit ABIs always start floating point arguments in an
5227 even-numbered floating point register. Round the FP register
5228 up before the check to see if there are any FP registers
5229 left. O32 targets also pass the FP in the integer registers
5230 so also round up normal registers. */
5231 if (fp_register_arg_p (gdbarch, typecode, arg_type))
5233 if ((float_argreg & 1))
5237 /* Floating point arguments passed in registers have to be
5238 treated specially. On 32-bit architectures, doubles are
5239 passed in register pairs; the even FP register gets the
5240 low word, and the odd FP register gets the high word.
5241 On O32, the first two floating point arguments are also
5242 copied to general registers, following their memory order,
5243 because MIPS16 functions don't use float registers for
5244 arguments. This duplication of arguments in general
5245 registers can't hurt non-MIPS16 functions, because those
5246 registers are normally skipped. */
5248 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5249 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5251 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
5253 int freg_offset = gdbarch_byte_order (gdbarch)
5254 == BFD_ENDIAN_BIG ? 1 : 0;
5255 unsigned long regval;
5258 regval = extract_unsigned_integer (val, 4, byte_order);
5260 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5261 float_argreg + freg_offset,
5263 regcache_cooked_write_unsigned (regcache,
5264 float_argreg++ + freg_offset,
5267 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5268 argreg, phex (regval, 4));
5269 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5272 regval = extract_unsigned_integer (val + 4, 4, byte_order);
5274 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5275 float_argreg - freg_offset,
5277 regcache_cooked_write_unsigned (regcache,
5278 float_argreg++ - freg_offset,
5281 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5282 argreg, phex (regval, 4));
5283 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5287 /* This is a floating point value that fits entirely
5288 in a single register. */
5289 /* On 32 bit ABI's the float_argreg is further adjusted
5290 above to ensure that it is even register aligned. */
5291 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5293 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5294 float_argreg, phex (regval, len));
5295 regcache_cooked_write_unsigned (regcache,
5296 float_argreg++, regval);
5297 /* Although two FP registers are reserved for each
5298 argument, only one corresponding integer register is
5301 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5302 argreg, phex (regval, len));
5303 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5305 /* Reserve space for the FP register. */
5306 stack_offset += align_up (len, MIPS32_REGSIZE);
5310 /* Copy the argument to general registers or the stack in
5311 register-sized pieces. Large arguments are split between
5312 registers and stack. */
5313 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5314 are treated specially: Irix cc passes
5315 them in registers where gcc sometimes puts them on the
5316 stack. For maximum compatibility, we will put them in
5318 int odd_sized_struct = (len > MIPS32_REGSIZE
5319 && len % MIPS32_REGSIZE != 0);
5320 /* Structures should be aligned to eight bytes (even arg registers)
5321 on MIPS_ABI_O32, if their first member has double precision. */
5322 if (mips_type_needs_double_align (arg_type))
5327 stack_offset += MIPS32_REGSIZE;
5332 /* Remember if the argument was written to the stack. */
5333 int stack_used_p = 0;
5334 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
5337 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5340 /* Write this portion of the argument to the stack. */
5341 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5342 || odd_sized_struct)
5344 /* Should shorter than int integer values be
5345 promoted to int before being stored? */
5346 int longword_offset = 0;
5352 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5353 paddress (gdbarch, stack_offset));
5354 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5355 paddress (gdbarch, longword_offset));
5358 addr = sp + stack_offset + longword_offset;
5363 fprintf_unfiltered (gdb_stdlog, " @%s ",
5364 paddress (gdbarch, addr));
5365 for (i = 0; i < partial_len; i++)
5367 fprintf_unfiltered (gdb_stdlog, "%02x",
5371 write_memory (addr, val, partial_len);
5374 /* Note!!! This is NOT an else clause. Odd sized
5375 structs may go thru BOTH paths. */
5376 /* Write this portion of the argument to a general
5377 purpose register. */
5378 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5380 LONGEST regval = extract_signed_integer (val, partial_len,
5382 /* Value may need to be sign extended, because
5383 mips_isa_regsize() != mips_abi_regsize(). */
5385 /* A non-floating-point argument being passed in a
5386 general register. If a struct or union, and if
5387 the remaining length is smaller than the register
5388 size, we have to adjust the register value on
5391 It does not seem to be necessary to do the
5392 same for integral types.
5394 Also don't do this adjustment on O64 binaries.
5396 cagney/2001-07-23: gdb/179: Also, GCC, when
5397 outputting LE O32 with sizeof (struct) <
5398 mips_abi_regsize(), generates a left shift
5399 as part of storing the argument in a register
5400 (the left shift isn't generated when
5401 sizeof (struct) >= mips_abi_regsize()). Since
5402 it is quite possible that this is GCC
5403 contradicting the LE/O32 ABI, GDB has not been
5404 adjusted to accommodate this. Either someone
5405 needs to demonstrate that the LE/O32 ABI
5406 specifies such a left shift OR this new ABI gets
5407 identified as such and GDB gets tweaked
5410 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5411 && partial_len < MIPS32_REGSIZE
5412 && (typecode == TYPE_CODE_STRUCT
5413 || typecode == TYPE_CODE_UNION))
5414 regval <<= ((MIPS32_REGSIZE - partial_len)
5418 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5420 phex (regval, MIPS32_REGSIZE));
5421 regcache_cooked_write_unsigned (regcache, argreg, regval);
5424 /* Prevent subsequent floating point arguments from
5425 being passed in floating point registers. */
5426 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
5432 /* Compute the offset into the stack at which we will
5433 copy the next parameter.
5435 In older ABIs, the caller reserved space for
5436 registers that contained arguments. This was loosely
5437 refered to as their "home". Consequently, space is
5438 always allocated. */
5440 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
5444 fprintf_unfiltered (gdb_stdlog, "\n");
5447 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5449 /* Return adjusted stack pointer. */
5453 static enum return_value_convention
5454 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function,
5455 struct type *type, struct regcache *regcache,
5456 gdb_byte *readbuf, const gdb_byte *writebuf)
5458 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
5459 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
5460 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5461 enum mips_fval_reg fval_reg;
5463 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
5464 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5465 || TYPE_CODE (type) == TYPE_CODE_UNION
5466 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5467 return RETURN_VALUE_STRUCT_CONVENTION;
5468 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5469 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5471 /* A single-precision floating-point value. If reading in or copying,
5472 then we get it from/put it to FP0 for standard MIPS code or GPR2
5473 for MIPS16 code. If writing out only, then we put it to both FP0
5474 and GPR2. We do not support reading in with no function known, if
5475 this safety check ever triggers, then we'll have to try harder. */
5476 gdb_assert (function || !readbuf);
5481 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5484 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
5486 case mips_fval_both:
5487 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
5490 if (fval_reg != mips_fval_gpr)
5491 mips_xfer_register (gdbarch, regcache,
5492 (gdbarch_num_regs (gdbarch)
5493 + mips_regnum (gdbarch)->fp0),
5495 gdbarch_byte_order (gdbarch),
5496 readbuf, writebuf, 0);
5497 if (fval_reg != mips_fval_fpr)
5498 mips_xfer_register (gdbarch, regcache,
5499 gdbarch_num_regs (gdbarch) + 2,
5501 gdbarch_byte_order (gdbarch),
5502 readbuf, writebuf, 0);
5503 return RETURN_VALUE_REGISTER_CONVENTION;
5505 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5506 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5508 /* A double-precision floating-point value. If reading in or copying,
5509 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5510 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5511 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5512 no function known, if this safety check ever triggers, then we'll
5513 have to try harder. */
5514 gdb_assert (function || !readbuf);
5519 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
5522 fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n");
5524 case mips_fval_both:
5525 fprintf_unfiltered (gdb_stderr,
5526 "Return float in $fp1/$fp0 and $2/$3\n");
5529 if (fval_reg != mips_fval_gpr)
5531 /* The most significant part goes in FP1, and the least significant
5533 switch (gdbarch_byte_order (gdbarch))
5535 case BFD_ENDIAN_LITTLE:
5536 mips_xfer_register (gdbarch, regcache,
5537 (gdbarch_num_regs (gdbarch)
5538 + mips_regnum (gdbarch)->fp0 + 0),
5539 4, gdbarch_byte_order (gdbarch),
5540 readbuf, writebuf, 0);
5541 mips_xfer_register (gdbarch, regcache,
5542 (gdbarch_num_regs (gdbarch)
5543 + mips_regnum (gdbarch)->fp0 + 1),
5544 4, gdbarch_byte_order (gdbarch),
5545 readbuf, writebuf, 4);
5547 case BFD_ENDIAN_BIG:
5548 mips_xfer_register (gdbarch, regcache,
5549 (gdbarch_num_regs (gdbarch)
5550 + mips_regnum (gdbarch)->fp0 + 1),
5551 4, gdbarch_byte_order (gdbarch),
5552 readbuf, writebuf, 0);
5553 mips_xfer_register (gdbarch, regcache,
5554 (gdbarch_num_regs (gdbarch)
5555 + mips_regnum (gdbarch)->fp0 + 0),
5556 4, gdbarch_byte_order (gdbarch),
5557 readbuf, writebuf, 4);
5560 internal_error (__FILE__, __LINE__, _("bad switch"));
5563 if (fval_reg != mips_fval_fpr)
5565 /* The two 32-bit parts are always placed in GPR2 and GPR3
5566 following these registers' memory order. */
5567 mips_xfer_register (gdbarch, regcache,
5568 gdbarch_num_regs (gdbarch) + 2,
5569 4, gdbarch_byte_order (gdbarch),
5570 readbuf, writebuf, 0);
5571 mips_xfer_register (gdbarch, regcache,
5572 gdbarch_num_regs (gdbarch) + 3,
5573 4, gdbarch_byte_order (gdbarch),
5574 readbuf, writebuf, 4);
5576 return RETURN_VALUE_REGISTER_CONVENTION;
5579 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5580 && TYPE_NFIELDS (type) <= 2
5581 && TYPE_NFIELDS (type) >= 1
5582 && ((TYPE_NFIELDS (type) == 1
5583 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5585 || (TYPE_NFIELDS (type) == 2
5586 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5588 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
5590 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5592 /* A struct that contains one or two floats. Each value is part
5593 in the least significant part of their floating point
5595 gdb_byte reg[MAX_REGISTER_SIZE];
5598 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
5599 field < TYPE_NFIELDS (type); field++, regnum += 2)
5601 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5604 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5606 mips_xfer_register (gdbarch, regcache,
5607 gdbarch_num_regs (gdbarch) + regnum,
5608 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5609 gdbarch_byte_order (gdbarch),
5610 readbuf, writebuf, offset);
5612 return RETURN_VALUE_REGISTER_CONVENTION;
5616 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5617 || TYPE_CODE (type) == TYPE_CODE_UNION)
5619 /* A structure or union. Extract the left justified value,
5620 regardless of the byte order. I.e. DO NOT USE
5624 for (offset = 0, regnum = MIPS_V0_REGNUM;
5625 offset < TYPE_LENGTH (type);
5626 offset += register_size (gdbarch, regnum), regnum++)
5628 int xfer = register_size (gdbarch, regnum);
5629 if (offset + xfer > TYPE_LENGTH (type))
5630 xfer = TYPE_LENGTH (type) - offset;
5632 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5633 offset, xfer, regnum);
5634 mips_xfer_register (gdbarch, regcache,
5635 gdbarch_num_regs (gdbarch) + regnum, xfer,
5636 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
5638 return RETURN_VALUE_REGISTER_CONVENTION;
5643 /* A scalar extract each part but least-significant-byte
5644 justified. o32 thinks registers are 4 byte, regardless of
5648 for (offset = 0, regnum = MIPS_V0_REGNUM;
5649 offset < TYPE_LENGTH (type);
5650 offset += MIPS32_REGSIZE, regnum++)
5652 int xfer = MIPS32_REGSIZE;
5653 if (offset + xfer > TYPE_LENGTH (type))
5654 xfer = TYPE_LENGTH (type) - offset;
5656 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5657 offset, xfer, regnum);
5658 mips_xfer_register (gdbarch, regcache,
5659 gdbarch_num_regs (gdbarch) + regnum, xfer,
5660 gdbarch_byte_order (gdbarch),
5661 readbuf, writebuf, offset);
5663 return RETURN_VALUE_REGISTER_CONVENTION;
5667 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5671 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5672 struct regcache *regcache, CORE_ADDR bp_addr,
5674 struct value **args, CORE_ADDR sp,
5675 int struct_return, CORE_ADDR struct_addr)
5681 int stack_offset = 0;
5682 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5683 CORE_ADDR func_addr = find_function_addr (function, NULL);
5685 /* For shared libraries, "t9" needs to point at the function
5687 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5689 /* Set the return address register to point to the entry point of
5690 the program, where a breakpoint lies in wait. */
5691 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5693 /* First ensure that the stack and structure return address (if any)
5694 are properly aligned. The stack has to be at least 64-bit
5695 aligned even on 32-bit machines, because doubles must be 64-bit
5696 aligned. For n32 and n64, stack frames need to be 128-bit
5697 aligned, so we round to this widest known alignment. */
5699 sp = align_down (sp, 16);
5700 struct_addr = align_down (struct_addr, 16);
5702 /* Now make space on the stack for the args. */
5703 for (argnum = 0; argnum < nargs; argnum++)
5705 struct type *arg_type = check_typedef (value_type (args[argnum]));
5706 int arglen = TYPE_LENGTH (arg_type);
5708 /* Allocate space on the stack. */
5709 len += align_up (arglen, MIPS64_REGSIZE);
5711 sp -= align_up (len, 16);
5714 fprintf_unfiltered (gdb_stdlog,
5715 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5716 paddress (gdbarch, sp), (long) align_up (len, 16));
5718 /* Initialize the integer and float register pointers. */
5719 argreg = MIPS_A0_REGNUM;
5720 float_argreg = mips_fpa0_regnum (gdbarch);
5722 /* The struct_return pointer occupies the first parameter-passing reg. */
5726 fprintf_unfiltered (gdb_stdlog,
5727 "mips_o64_push_dummy_call: "
5728 "struct_return reg=%d %s\n",
5729 argreg, paddress (gdbarch, struct_addr));
5730 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5731 stack_offset += MIPS64_REGSIZE;
5734 /* Now load as many as possible of the first arguments into
5735 registers, and push the rest onto the stack. Loop thru args
5736 from first to last. */
5737 for (argnum = 0; argnum < nargs; argnum++)
5739 const gdb_byte *val;
5740 gdb_byte valbuf[MAX_REGISTER_SIZE];
5741 struct value *arg = args[argnum];
5742 struct type *arg_type = check_typedef (value_type (arg));
5743 int len = TYPE_LENGTH (arg_type);
5744 enum type_code typecode = TYPE_CODE (arg_type);
5747 fprintf_unfiltered (gdb_stdlog,
5748 "mips_o64_push_dummy_call: %d len=%d type=%d",
5749 argnum + 1, len, (int) typecode);
5751 val = value_contents (arg);
5753 /* Function pointer arguments to mips16 code need to be made into
5755 if (typecode == TYPE_CODE_PTR
5756 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
5758 CORE_ADDR addr = extract_signed_integer (value_contents (arg),
5760 if (!mips_pc_is_mips (addr))
5762 store_signed_integer (valbuf, len, byte_order,
5763 make_compact_addr (addr));
5768 /* Floating point arguments passed in registers have to be
5769 treated specially. On 32-bit architectures, doubles are
5770 passed in register pairs; the even FP register gets the
5771 low word, and the odd FP register gets the high word.
5772 On O64, the first two floating point arguments are also
5773 copied to general registers, because MIPS16 functions
5774 don't use float registers for arguments. This duplication
5775 of arguments in general registers can't hurt non-MIPS16
5776 functions because those registers are normally skipped. */
5778 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5779 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5781 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5783 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5784 float_argreg, phex (regval, len));
5785 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
5787 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5788 argreg, phex (regval, len));
5789 regcache_cooked_write_unsigned (regcache, argreg, regval);
5791 /* Reserve space for the FP register. */
5792 stack_offset += align_up (len, MIPS64_REGSIZE);
5796 /* Copy the argument to general registers or the stack in
5797 register-sized pieces. Large arguments are split between
5798 registers and stack. */
5799 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5800 are treated specially: Irix cc passes them in registers
5801 where gcc sometimes puts them on the stack. For maximum
5802 compatibility, we will put them in both places. */
5803 int odd_sized_struct = (len > MIPS64_REGSIZE
5804 && len % MIPS64_REGSIZE != 0);
5807 /* Remember if the argument was written to the stack. */
5808 int stack_used_p = 0;
5809 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
5812 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5815 /* Write this portion of the argument to the stack. */
5816 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5817 || odd_sized_struct)
5819 /* Should shorter than int integer values be
5820 promoted to int before being stored? */
5821 int longword_offset = 0;
5824 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5826 if ((typecode == TYPE_CODE_INT
5827 || typecode == TYPE_CODE_PTR
5828 || typecode == TYPE_CODE_FLT)
5830 longword_offset = MIPS64_REGSIZE - len;
5835 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5836 paddress (gdbarch, stack_offset));
5837 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5838 paddress (gdbarch, longword_offset));
5841 addr = sp + stack_offset + longword_offset;
5846 fprintf_unfiltered (gdb_stdlog, " @%s ",
5847 paddress (gdbarch, addr));
5848 for (i = 0; i < partial_len; i++)
5850 fprintf_unfiltered (gdb_stdlog, "%02x",
5854 write_memory (addr, val, partial_len);
5857 /* Note!!! This is NOT an else clause. Odd sized
5858 structs may go thru BOTH paths. */
5859 /* Write this portion of the argument to a general
5860 purpose register. */
5861 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5863 LONGEST regval = extract_signed_integer (val, partial_len,
5865 /* Value may need to be sign extended, because
5866 mips_isa_regsize() != mips_abi_regsize(). */
5868 /* A non-floating-point argument being passed in a
5869 general register. If a struct or union, and if
5870 the remaining length is smaller than the register
5871 size, we have to adjust the register value on
5874 It does not seem to be necessary to do the
5875 same for integral types. */
5877 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5878 && partial_len < MIPS64_REGSIZE
5879 && (typecode == TYPE_CODE_STRUCT
5880 || typecode == TYPE_CODE_UNION))
5881 regval <<= ((MIPS64_REGSIZE - partial_len)
5885 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5887 phex (regval, MIPS64_REGSIZE));
5888 regcache_cooked_write_unsigned (regcache, argreg, regval);
5891 /* Prevent subsequent floating point arguments from
5892 being passed in floating point registers. */
5893 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
5899 /* Compute the offset into the stack at which we will
5900 copy the next parameter.
5902 In older ABIs, the caller reserved space for
5903 registers that contained arguments. This was loosely
5904 refered to as their "home". Consequently, space is
5905 always allocated. */
5907 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
5911 fprintf_unfiltered (gdb_stdlog, "\n");
5914 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5916 /* Return adjusted stack pointer. */
5920 static enum return_value_convention
5921 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function,
5922 struct type *type, struct regcache *regcache,
5923 gdb_byte *readbuf, const gdb_byte *writebuf)
5925 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
5926 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
5927 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5928 enum mips_fval_reg fval_reg;
5930 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
5931 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5932 || TYPE_CODE (type) == TYPE_CODE_UNION
5933 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5934 return RETURN_VALUE_STRUCT_CONVENTION;
5935 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
5937 /* A floating-point value. If reading in or copying, then we get it
5938 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5939 If writing out only, then we put it to both FP0 and GPR2. We do
5940 not support reading in with no function known, if this safety
5941 check ever triggers, then we'll have to try harder. */
5942 gdb_assert (function || !readbuf);
5947 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5950 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
5952 case mips_fval_both:
5953 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
5956 if (fval_reg != mips_fval_gpr)
5957 mips_xfer_register (gdbarch, regcache,
5958 (gdbarch_num_regs (gdbarch)
5959 + mips_regnum (gdbarch)->fp0),
5961 gdbarch_byte_order (gdbarch),
5962 readbuf, writebuf, 0);
5963 if (fval_reg != mips_fval_fpr)
5964 mips_xfer_register (gdbarch, regcache,
5965 gdbarch_num_regs (gdbarch) + 2,
5967 gdbarch_byte_order (gdbarch),
5968 readbuf, writebuf, 0);
5969 return RETURN_VALUE_REGISTER_CONVENTION;
5973 /* A scalar extract each part but least-significant-byte
5977 for (offset = 0, regnum = MIPS_V0_REGNUM;
5978 offset < TYPE_LENGTH (type);
5979 offset += MIPS64_REGSIZE, regnum++)
5981 int xfer = MIPS64_REGSIZE;
5982 if (offset + xfer > TYPE_LENGTH (type))
5983 xfer = TYPE_LENGTH (type) - offset;
5985 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5986 offset, xfer, regnum);
5987 mips_xfer_register (gdbarch, regcache,
5988 gdbarch_num_regs (gdbarch) + regnum,
5989 xfer, gdbarch_byte_order (gdbarch),
5990 readbuf, writebuf, offset);
5992 return RETURN_VALUE_REGISTER_CONVENTION;
5996 /* Floating point register management.
5998 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5999 64bit operations, these early MIPS cpus treat fp register pairs
6000 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6001 registers and offer a compatibility mode that emulates the MIPS2 fp
6002 model. When operating in MIPS2 fp compat mode, later cpu's split
6003 double precision floats into two 32-bit chunks and store them in
6004 consecutive fp regs. To display 64-bit floats stored in this
6005 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6006 Throw in user-configurable endianness and you have a real mess.
6008 The way this works is:
6009 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6010 double-precision value will be split across two logical registers.
6011 The lower-numbered logical register will hold the low-order bits,
6012 regardless of the processor's endianness.
6013 - If we are on a 64-bit processor, and we are looking for a
6014 single-precision value, it will be in the low ordered bits
6015 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6016 save slot in memory.
6017 - If we are in 64-bit mode, everything is straightforward.
6019 Note that this code only deals with "live" registers at the top of the
6020 stack. We will attempt to deal with saved registers later, when
6021 the raw/cooked register interface is in place. (We need a general
6022 interface that can deal with dynamic saved register sizes -- fp
6023 regs could be 32 bits wide in one frame and 64 on the frame above
6026 /* Copy a 32-bit single-precision value from the current frame
6027 into rare_buffer. */
6030 mips_read_fp_register_single (struct frame_info *frame, int regno,
6031 gdb_byte *rare_buffer)
6033 struct gdbarch *gdbarch = get_frame_arch (frame);
6034 int raw_size = register_size (gdbarch, regno);
6035 gdb_byte *raw_buffer = alloca (raw_size);
6037 if (!frame_register_read (frame, regno, raw_buffer))
6038 error (_("can't read register %d (%s)"),
6039 regno, gdbarch_register_name (gdbarch, regno));
6042 /* We have a 64-bit value for this register. Find the low-order
6046 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6051 memcpy (rare_buffer, raw_buffer + offset, 4);
6055 memcpy (rare_buffer, raw_buffer, 4);
6059 /* Copy a 64-bit double-precision value from the current frame into
6060 rare_buffer. This may include getting half of it from the next
6064 mips_read_fp_register_double (struct frame_info *frame, int regno,
6065 gdb_byte *rare_buffer)
6067 struct gdbarch *gdbarch = get_frame_arch (frame);
6068 int raw_size = register_size (gdbarch, regno);
6070 if (raw_size == 8 && !mips2_fp_compat (frame))
6072 /* We have a 64-bit value for this register, and we should use
6074 if (!frame_register_read (frame, regno, rare_buffer))
6075 error (_("can't read register %d (%s)"),
6076 regno, gdbarch_register_name (gdbarch, regno));
6080 int rawnum = regno % gdbarch_num_regs (gdbarch);
6082 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
6083 internal_error (__FILE__, __LINE__,
6084 _("mips_read_fp_register_double: bad access to "
6085 "odd-numbered FP register"));
6087 /* mips_read_fp_register_single will find the correct 32 bits from
6089 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6091 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
6092 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
6096 mips_read_fp_register_single (frame, regno, rare_buffer);
6097 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
6103 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
6105 { /* Do values for FP (float) regs. */
6106 struct gdbarch *gdbarch = get_frame_arch (frame);
6107 gdb_byte *raw_buffer;
6108 double doub, flt1; /* Doubles extracted from raw hex data. */
6111 raw_buffer = alloca (2 * register_size (gdbarch,
6112 mips_regnum (gdbarch)->fp0));
6114 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
6115 fprintf_filtered (file, "%*s",
6116 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
6119 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
6121 struct value_print_options opts;
6123 /* 4-byte registers: Print hex and floating. Also print even
6124 numbered registers as doubles. */
6125 mips_read_fp_register_single (frame, regnum, raw_buffer);
6126 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
6129 get_formatted_print_options (&opts, 'x');
6130 print_scalar_formatted (raw_buffer,
6131 builtin_type (gdbarch)->builtin_uint32,
6134 fprintf_filtered (file, " flt: ");
6136 fprintf_filtered (file, " <invalid float> ");
6138 fprintf_filtered (file, "%-17.9g", flt1);
6140 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
6142 mips_read_fp_register_double (frame, regnum, raw_buffer);
6143 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
6146 fprintf_filtered (file, " dbl: ");
6148 fprintf_filtered (file, "<invalid double>");
6150 fprintf_filtered (file, "%-24.17g", doub);
6155 struct value_print_options opts;
6157 /* Eight byte registers: print each one as hex, float and double. */
6158 mips_read_fp_register_single (frame, regnum, raw_buffer);
6159 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
6162 mips_read_fp_register_double (frame, regnum, raw_buffer);
6163 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
6166 get_formatted_print_options (&opts, 'x');
6167 print_scalar_formatted (raw_buffer,
6168 builtin_type (gdbarch)->builtin_uint64,
6171 fprintf_filtered (file, " flt: ");
6173 fprintf_filtered (file, "<invalid float>");
6175 fprintf_filtered (file, "%-17.9g", flt1);
6177 fprintf_filtered (file, " dbl: ");
6179 fprintf_filtered (file, "<invalid double>");
6181 fprintf_filtered (file, "%-24.17g", doub);
6186 mips_print_register (struct ui_file *file, struct frame_info *frame,
6189 struct gdbarch *gdbarch = get_frame_arch (frame);
6190 struct value_print_options opts;
6193 if (mips_float_register_p (gdbarch, regnum))
6195 mips_print_fp_register (file, frame, regnum);
6199 val = get_frame_register_value (frame, regnum);
6200 if (value_optimized_out (val))
6202 fprintf_filtered (file, "%s: [Invalid]",
6203 gdbarch_register_name (gdbarch, regnum));
6207 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
6209 /* The problem with printing numeric register names (r26, etc.) is that
6210 the user can't use them on input. Probably the best solution is to
6211 fix it so that either the numeric or the funky (a2, etc.) names
6212 are accepted on input. */
6213 if (regnum < MIPS_NUMREGS)
6214 fprintf_filtered (file, "(r%d): ", regnum);
6216 fprintf_filtered (file, ": ");
6218 get_formatted_print_options (&opts, 'x');
6219 val_print_scalar_formatted (value_type (val),
6220 value_contents_for_printing (val),
6221 value_embedded_offset (val),
6226 /* Replacement for generic do_registers_info.
6227 Print regs in pretty columns. */
6230 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
6233 fprintf_filtered (file, " ");
6234 mips_print_fp_register (file, frame, regnum);
6235 fprintf_filtered (file, "\n");
6240 /* Print a row's worth of GP (int) registers, with name labels above. */
6243 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
6246 struct gdbarch *gdbarch = get_frame_arch (frame);
6247 /* Do values for GP (int) regs. */
6248 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
6249 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols
6254 /* For GP registers, we print a separate row of names above the vals. */
6255 for (col = 0, regnum = start_regnum;
6256 col < ncols && regnum < gdbarch_num_regs (gdbarch)
6257 + gdbarch_num_pseudo_regs (gdbarch);
6260 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6261 continue; /* unused register */
6262 if (mips_float_register_p (gdbarch, regnum))
6263 break; /* End the row: reached FP register. */
6264 /* Large registers are handled separately. */
6265 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6268 break; /* End the row before this register. */
6270 /* Print this register on a row by itself. */
6271 mips_print_register (file, frame, regnum);
6272 fprintf_filtered (file, "\n");
6276 fprintf_filtered (file, " ");
6277 fprintf_filtered (file,
6278 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
6279 gdbarch_register_name (gdbarch, regnum));
6286 /* Print the R0 to R31 names. */
6287 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
6288 fprintf_filtered (file, "\n R%-4d",
6289 start_regnum % gdbarch_num_regs (gdbarch));
6291 fprintf_filtered (file, "\n ");
6293 /* Now print the values in hex, 4 or 8 to the row. */
6294 for (col = 0, regnum = start_regnum;
6295 col < ncols && regnum < gdbarch_num_regs (gdbarch)
6296 + gdbarch_num_pseudo_regs (gdbarch);
6299 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6300 continue; /* unused register */
6301 if (mips_float_register_p (gdbarch, regnum))
6302 break; /* End row: reached FP register. */
6303 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6304 break; /* End row: large register. */
6306 /* OK: get the data in raw format. */
6307 if (!frame_register_read (frame, regnum, raw_buffer))
6308 error (_("can't read register %d (%s)"),
6309 regnum, gdbarch_register_name (gdbarch, regnum));
6310 /* pad small registers */
6312 byte < (mips_abi_regsize (gdbarch)
6313 - register_size (gdbarch, regnum)); byte++)
6314 printf_filtered (" ");
6315 /* Now print the register value in hex, endian order. */
6316 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6318 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
6319 byte < register_size (gdbarch, regnum); byte++)
6320 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6322 for (byte = register_size (gdbarch, regnum) - 1;
6324 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6325 fprintf_filtered (file, " ");
6328 if (col > 0) /* ie. if we actually printed anything... */
6329 fprintf_filtered (file, "\n");
6334 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6337 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
6338 struct frame_info *frame, int regnum, int all)
6340 if (regnum != -1) /* Do one specified register. */
6342 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
6343 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
6344 error (_("Not a valid register for the current processor type"));
6346 mips_print_register (file, frame, regnum);
6347 fprintf_filtered (file, "\n");
6350 /* Do all (or most) registers. */
6352 regnum = gdbarch_num_regs (gdbarch);
6353 while (regnum < gdbarch_num_regs (gdbarch)
6354 + gdbarch_num_pseudo_regs (gdbarch))
6356 if (mips_float_register_p (gdbarch, regnum))
6358 if (all) /* True for "INFO ALL-REGISTERS" command. */
6359 regnum = print_fp_register_row (file, frame, regnum);
6361 regnum += MIPS_NUMREGS; /* Skip floating point regs. */
6364 regnum = print_gp_register_row (file, frame, regnum);
6370 mips_single_step_through_delay (struct gdbarch *gdbarch,
6371 struct frame_info *frame)
6373 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6374 CORE_ADDR pc = get_frame_pc (frame);
6375 struct address_space *aspace;
6381 if ((mips_pc_is_mips (pc)
6382 && !mips32_instruction_has_delay_slot (gdbarch, pc))
6383 || (mips_pc_is_micromips (gdbarch, pc)
6384 && !micromips_instruction_has_delay_slot (gdbarch, pc, 0))
6385 || (mips_pc_is_mips16 (gdbarch, pc)
6386 && !mips16_instruction_has_delay_slot (gdbarch, pc, 0)))
6389 isa = mips_pc_isa (gdbarch, pc);
6390 /* _has_delay_slot above will have validated the read. */
6391 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL);
6392 size = mips_insn_size (isa, insn);
6393 aspace = get_frame_address_space (frame);
6394 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here;
6397 /* To skip prologues, I use this predicate. Returns either PC itself
6398 if the code at PC does not look like a function prologue; otherwise
6399 returns an address that (if we're lucky) follows the prologue. If
6400 LENIENT, then we must skip everything which is involved in setting
6401 up the frame (it's OK to skip more, just so long as we don't skip
6402 anything which might clobber the registers which are being saved.
6403 We must skip more in the case where part of the prologue is in the
6404 delay slot of a non-prologue instruction). */
6407 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
6410 CORE_ADDR func_addr;
6412 /* See if we can determine the end of the prologue via the symbol table.
6413 If so, then return either PC, or the PC after the prologue, whichever
6415 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
6417 CORE_ADDR post_prologue_pc
6418 = skip_prologue_using_sal (gdbarch, func_addr);
6419 if (post_prologue_pc != 0)
6420 return max (pc, post_prologue_pc);
6423 /* Can't determine prologue from the symbol table, need to examine
6426 /* Find an upper limit on the function prologue using the debug
6427 information. If the debug information could not be used to provide
6428 that bound, then use an arbitrary large number as the upper bound. */
6429 limit_pc = skip_prologue_using_sal (gdbarch, pc);
6431 limit_pc = pc + 100; /* Magic. */
6433 if (mips_pc_is_mips16 (gdbarch, pc))
6434 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6435 else if (mips_pc_is_micromips (gdbarch, pc))
6436 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6438 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6441 /* Check whether the PC is in a function epilogue (32-bit version).
6442 This is a helper function for mips_in_function_epilogue_p. */
6444 mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6446 CORE_ADDR func_addr = 0, func_end = 0;
6448 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6450 /* The MIPS epilogue is max. 12 bytes long. */
6451 CORE_ADDR addr = func_end - 12;
6453 if (addr < func_addr + 4)
6454 addr = func_addr + 4;
6458 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
6460 unsigned long high_word;
6463 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
6464 high_word = (inst >> 16) & 0xffff;
6466 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
6467 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
6468 && inst != 0x03e00008 /* jr $ra */
6469 && inst != 0x00000000) /* nop */
6479 /* Check whether the PC is in a function epilogue (microMIPS version).
6480 This is a helper function for mips_in_function_epilogue_p. */
6483 micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6485 CORE_ADDR func_addr = 0;
6486 CORE_ADDR func_end = 0;
6494 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6497 /* The microMIPS epilogue is max. 12 bytes long. */
6498 addr = func_end - 12;
6500 if (addr < func_addr + 2)
6501 addr = func_addr + 2;
6505 for (; pc < func_end; pc += loc)
6508 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
6509 loc += MIPS_INSN16_SIZE;
6510 switch (mips_insn_size (ISA_MICROMIPS, insn))
6512 /* 48-bit instructions. */
6513 case 3 * MIPS_INSN16_SIZE:
6514 /* No epilogue instructions in this category. */
6517 /* 32-bit instructions. */
6518 case 2 * MIPS_INSN16_SIZE:
6520 insn |= mips_fetch_instruction (gdbarch,
6521 ISA_MICROMIPS, pc + loc, NULL);
6522 loc += MIPS_INSN16_SIZE;
6523 switch (micromips_op (insn >> 16))
6525 case 0xc: /* ADDIU: bits 001100 */
6526 case 0x17: /* DADDIU: bits 010111 */
6527 sreg = b0s5_reg (insn >> 16);
6528 dreg = b5s5_reg (insn >> 16);
6529 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
6530 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
6531 /* (D)ADDIU $sp, imm */
6541 /* 16-bit instructions. */
6542 case MIPS_INSN16_SIZE:
6543 switch (micromips_op (insn))
6545 case 0x3: /* MOVE: bits 000011 */
6546 sreg = b0s5_reg (insn);
6547 dreg = b5s5_reg (insn);
6548 if (sreg == 0 && dreg == 0)
6549 /* MOVE $zero, $zero aka NOP */
6553 case 0x11: /* POOL16C: bits 010001 */
6554 if (b5s5_op (insn) == 0x18
6555 /* JRADDIUSP: bits 010011 11000 */
6556 || (b5s5_op (insn) == 0xd
6557 /* JRC: bits 010011 01101 */
6558 && b0s5_reg (insn) == MIPS_RA_REGNUM))
6563 case 0x13: /* POOL16D: bits 010011 */
6564 offset = micromips_decode_imm9 (b1s9_imm (insn));
6565 if ((insn & 0x1) == 0x1
6566 /* ADDIUSP: bits 010011 1 */
6580 /* Check whether the PC is in a function epilogue (16-bit version).
6581 This is a helper function for mips_in_function_epilogue_p. */
6583 mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6585 CORE_ADDR func_addr = 0, func_end = 0;
6587 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6589 /* The MIPS epilogue is max. 12 bytes long. */
6590 CORE_ADDR addr = func_end - 12;
6592 if (addr < func_addr + 4)
6593 addr = func_addr + 4;
6597 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
6599 unsigned short inst;
6601 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL);
6603 if ((inst & 0xf800) == 0xf000) /* extend */
6606 if (inst != 0x6300 /* addiu $sp,offset */
6607 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
6608 && inst != 0xe820 /* jr $ra */
6609 && inst != 0xe8a0 /* jrc $ra */
6610 && inst != 0x6500) /* nop */
6620 /* The epilogue is defined here as the area at the end of a function,
6621 after an instruction which destroys the function's stack frame. */
6623 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6625 if (mips_pc_is_mips16 (gdbarch, pc))
6626 return mips16_in_function_epilogue_p (gdbarch, pc);
6627 else if (mips_pc_is_micromips (gdbarch, pc))
6628 return micromips_in_function_epilogue_p (gdbarch, pc);
6630 return mips32_in_function_epilogue_p (gdbarch, pc);
6633 /* Root of all "set mips "/"show mips " commands. This will eventually be
6634 used for all MIPS-specific commands. */
6637 show_mips_command (char *args, int from_tty)
6639 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
6643 set_mips_command (char *args, int from_tty)
6646 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6647 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
6650 /* Commands to show/set the MIPS FPU type. */
6653 show_mipsfpu_command (char *args, int from_tty)
6657 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
6660 ("The MIPS floating-point coprocessor is unknown "
6661 "because the current architecture is not MIPS.\n");
6665 switch (MIPS_FPU_TYPE (target_gdbarch))
6667 case MIPS_FPU_SINGLE:
6668 fpu = "single-precision";
6670 case MIPS_FPU_DOUBLE:
6671 fpu = "double-precision";
6674 fpu = "absent (none)";
6677 internal_error (__FILE__, __LINE__, _("bad switch"));
6679 if (mips_fpu_type_auto)
6680 printf_unfiltered ("The MIPS floating-point coprocessor "
6681 "is set automatically (currently %s)\n",
6685 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
6690 set_mipsfpu_command (char *args, int from_tty)
6692 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6693 "\"single\",\"none\" or \"auto\".\n");
6694 show_mipsfpu_command (args, from_tty);
6698 set_mipsfpu_single_command (char *args, int from_tty)
6700 struct gdbarch_info info;
6701 gdbarch_info_init (&info);
6702 mips_fpu_type = MIPS_FPU_SINGLE;
6703 mips_fpu_type_auto = 0;
6704 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6705 instead of relying on globals. Doing that would let generic code
6706 handle the search for this specific architecture. */
6707 if (!gdbarch_update_p (info))
6708 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6712 set_mipsfpu_double_command (char *args, int from_tty)
6714 struct gdbarch_info info;
6715 gdbarch_info_init (&info);
6716 mips_fpu_type = MIPS_FPU_DOUBLE;
6717 mips_fpu_type_auto = 0;
6718 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6719 instead of relying on globals. Doing that would let generic code
6720 handle the search for this specific architecture. */
6721 if (!gdbarch_update_p (info))
6722 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6726 set_mipsfpu_none_command (char *args, int from_tty)
6728 struct gdbarch_info info;
6729 gdbarch_info_init (&info);
6730 mips_fpu_type = MIPS_FPU_NONE;
6731 mips_fpu_type_auto = 0;
6732 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6733 instead of relying on globals. Doing that would let generic code
6734 handle the search for this specific architecture. */
6735 if (!gdbarch_update_p (info))
6736 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6740 set_mipsfpu_auto_command (char *args, int from_tty)
6742 mips_fpu_type_auto = 1;
6745 /* Attempt to identify the particular processor model by reading the
6746 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6747 the relevant processor still exists (it dates back to '94) and
6748 secondly this is not the way to do this. The processor type should
6749 be set by forcing an architecture change. */
6752 deprecated_mips_set_processor_regs_hack (void)
6754 struct regcache *regcache = get_current_regcache ();
6755 struct gdbarch *gdbarch = get_regcache_arch (regcache);
6756 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6759 regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid);
6760 if ((prid & ~0xf) == 0x700)
6761 tdep->mips_processor_reg_names = mips_r3041_reg_names;
6764 /* Just like reinit_frame_cache, but with the right arguments to be
6765 callable as an sfunc. */
6768 reinit_frame_cache_sfunc (char *args, int from_tty,
6769 struct cmd_list_element *c)
6771 reinit_frame_cache ();
6775 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
6777 struct gdbarch *gdbarch = info->application_data;
6779 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6780 disassembler needs to be able to locally determine the ISA, and
6781 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6783 if (mips_pc_is_mips16 (gdbarch, memaddr))
6784 info->mach = bfd_mach_mips16;
6785 else if (mips_pc_is_micromips (gdbarch, memaddr))
6786 info->mach = bfd_mach_mips_micromips;
6788 /* Round down the instruction address to the appropriate boundary. */
6789 memaddr &= (info->mach == bfd_mach_mips16
6790 || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3;
6792 /* Set the disassembler options. */
6793 if (!info->disassembler_options)
6794 /* This string is not recognized explicitly by the disassembler,
6795 but it tells the disassembler to not try to guess the ABI from
6796 the bfd elf headers, such that, if the user overrides the ABI
6797 of a program linked as NewABI, the disassembly will follow the
6798 register naming conventions specified by the user. */
6799 info->disassembler_options = "gpr-names=32";
6801 /* Call the appropriate disassembler based on the target endian-ness. */
6802 if (info->endian == BFD_ENDIAN_BIG)
6803 return print_insn_big_mips (memaddr, info);
6805 return print_insn_little_mips (memaddr, info);
6809 gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
6811 /* Set up the disassembler info, so that we get the right
6812 register names from libopcodes. */
6813 info->disassembler_options = "gpr-names=n32";
6814 info->flavour = bfd_target_elf_flavour;
6816 return gdb_print_insn_mips (memaddr, info);
6820 gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
6822 /* Set up the disassembler info, so that we get the right
6823 register names from libopcodes. */
6824 info->disassembler_options = "gpr-names=64";
6825 info->flavour = bfd_target_elf_flavour;
6827 return gdb_print_insn_mips (memaddr, info);
6830 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6831 program counter value to determine whether a 16- or 32-bit breakpoint
6832 should be used. It returns a pointer to a string of bytes that encode a
6833 breakpoint instruction, stores the length of the string to *lenptr, and
6834 adjusts pc (if necessary) to point to the actual memory location where
6835 the breakpoint should be inserted. */
6837 static const gdb_byte *
6838 mips_breakpoint_from_pc (struct gdbarch *gdbarch,
6839 CORE_ADDR *pcptr, int *lenptr)
6841 CORE_ADDR pc = *pcptr;
6843 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6845 if (mips_pc_is_mips16 (gdbarch, pc))
6847 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
6848 *pcptr = unmake_compact_addr (pc);
6849 *lenptr = sizeof (mips16_big_breakpoint);
6850 return mips16_big_breakpoint;
6852 else if (mips_pc_is_micromips (gdbarch, pc))
6854 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 };
6855 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 };
6860 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
6862 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
6863 *pcptr = unmake_compact_addr (pc);
6865 return (size == 2) ? micromips16_big_breakpoint
6866 : micromips32_big_breakpoint;
6870 /* The IDT board uses an unusual breakpoint value, and
6871 sometimes gets confused when it sees the usual MIPS
6872 breakpoint instruction. */
6873 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
6874 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
6875 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
6876 /* Likewise, IRIX appears to expect a different breakpoint,
6877 although this is not apparent until you try to use pthreads. */
6878 static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd };
6880 *lenptr = sizeof (big_breakpoint);
6882 if (strcmp (target_shortname, "mips") == 0)
6883 return idt_big_breakpoint;
6884 else if (strcmp (target_shortname, "ddb") == 0
6885 || strcmp (target_shortname, "pmon") == 0
6886 || strcmp (target_shortname, "lsi") == 0)
6887 return pmon_big_breakpoint;
6888 else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX)
6889 return irix_big_breakpoint;
6891 return big_breakpoint;
6896 if (mips_pc_is_mips16 (gdbarch, pc))
6898 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
6899 *pcptr = unmake_compact_addr (pc);
6900 *lenptr = sizeof (mips16_little_breakpoint);
6901 return mips16_little_breakpoint;
6903 else if (mips_pc_is_micromips (gdbarch, pc))
6905 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 };
6906 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 };
6911 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
6913 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
6914 *pcptr = unmake_compact_addr (pc);
6916 return (size == 2) ? micromips16_little_breakpoint
6917 : micromips32_little_breakpoint;
6921 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
6922 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
6923 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
6925 *lenptr = sizeof (little_breakpoint);
6927 if (strcmp (target_shortname, "mips") == 0)
6928 return idt_little_breakpoint;
6929 else if (strcmp (target_shortname, "ddb") == 0
6930 || strcmp (target_shortname, "pmon") == 0
6931 || strcmp (target_shortname, "lsi") == 0)
6932 return pmon_little_breakpoint;
6934 return little_breakpoint;
6939 /* Determine the remote breakpoint kind suitable for the PC. The following
6942 * 2 -- 16-bit MIPS16 mode breakpoint,
6944 * 3 -- 16-bit microMIPS mode breakpoint,
6946 * 4 -- 32-bit standard MIPS mode breakpoint,
6948 * 5 -- 32-bit microMIPS mode breakpoint. */
6951 mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
6954 CORE_ADDR pc = *pcptr;
6956 if (mips_pc_is_mips16 (gdbarch, pc))
6958 *pcptr = unmake_compact_addr (pc);
6961 else if (mips_pc_is_micromips (gdbarch, pc))
6967 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
6968 size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
6969 *pcptr = unmake_compact_addr (pc);
6970 *kindptr = size | 1;
6976 /* Return non-zero if the ADDR instruction has a branch delay slot
6977 (i.e. it is a jump or branch instruction). This function is based
6978 on mips32_next_pc. */
6981 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr)
6989 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status);
6993 op = itype_op (inst);
6994 if ((inst & 0xe0000000) != 0)
6996 rs = itype_rs (inst);
6997 rt = itype_rt (inst);
6998 return (is_octeon_bbit_op (op, gdbarch)
6999 || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7000 || op == 29 /* JALX: bits 011101 */
7003 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7004 || (rs == 9 && (rt & 0x2) == 0)
7005 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7006 || (rs == 10 && (rt & 0x2) == 0))));
7007 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7010 switch (op & 0x07) /* extract bits 28,27,26 */
7012 case 0: /* SPECIAL */
7013 op = rtype_funct (inst);
7014 return (op == 8 /* JR */
7015 || op == 9); /* JALR */
7016 break; /* end SPECIAL */
7017 case 1: /* REGIMM */
7018 rs = itype_rs (inst);
7019 rt = itype_rt (inst); /* branch condition */
7020 return ((rt & 0xc) == 0
7021 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7022 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7023 || ((rt & 0x1e) == 0x1c && rs == 0));
7024 /* BPOSGE32, BPOSGE64: bits 1110x */
7025 break; /* end REGIMM */
7026 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7032 /* Return non-zero if the ADDR instruction, which must be a 32-bit
7033 instruction if MUSTBE32 is set or can be any instruction otherwise,
7034 has a branch delay slot (i.e. it is a non-compact jump instruction). */
7037 micromips_instruction_has_delay_slot (struct gdbarch *gdbarch,
7038 CORE_ADDR addr, int mustbe32)
7043 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7047 if (!mustbe32) /* 16-bit instructions. */
7048 return (micromips_op (insn) == 0x11
7049 /* POOL16C: bits 010001 */
7050 && (b5s5_op (insn) == 0xc
7051 /* JR16: bits 010001 01100 */
7052 || (b5s5_op (insn) & 0x1e) == 0xe))
7053 /* JALR16, JALRS16: bits 010001 0111x */
7054 || (micromips_op (insn) & 0x37) == 0x23
7055 /* BEQZ16, BNEZ16: bits 10x011 */
7056 || micromips_op (insn) == 0x33;
7057 /* B16: bits 110011 */
7059 /* 32-bit instructions. */
7060 if (micromips_op (insn) == 0x0)
7061 /* POOL32A: bits 000000 */
7064 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7067 return b0s6_op (insn) == 0x3c
7068 /* POOL32Axf: bits 000000 ... 111100 */
7069 && (b6s10_ext (insn) & 0x2bf) == 0x3c;
7070 /* JALR, JALR.HB: 000000 000x111100 111100 */
7071 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7074 return (micromips_op (insn) == 0x10
7075 /* POOL32I: bits 010000 */
7076 && ((b5s5_op (insn) & 0x1c) == 0x0
7077 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7078 || (b5s5_op (insn) & 0x1d) == 0x4
7079 /* BLEZ, BGTZ: bits 010000 001x0 */
7080 || (b5s5_op (insn) & 0x1d) == 0x11
7081 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7082 || ((b5s5_op (insn) & 0x1e) == 0x14
7083 && (insn & 0x3) == 0x0)
7084 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7085 || (b5s5_op (insn) & 0x1e) == 0x1a
7086 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7087 || ((b5s5_op (insn) & 0x1e) == 0x1c
7088 && (insn & 0x3) == 0x0)
7089 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7090 || ((b5s5_op (insn) & 0x1c) == 0x1c
7091 && (insn & 0x3) == 0x1)))
7092 /* BC1ANY*: bits 010000 111xx xxx01 */
7093 || (micromips_op (insn) & 0x1f) == 0x1d
7094 /* JALS, JAL: bits x11101 */
7095 || (micromips_op (insn) & 0x37) == 0x25
7096 /* BEQ, BNE: bits 10x101 */
7097 || micromips_op (insn) == 0x35
7098 /* J: bits 110101 */
7099 || micromips_op (insn) == 0x3c;
7100 /* JALX: bits 111100 */
7104 mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr,
7107 unsigned short inst;
7110 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status);
7115 return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
7116 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7119 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7120 This assumes KSSEG exists. */
7123 mips_segment_boundary (CORE_ADDR bpaddr)
7125 CORE_ADDR mask = CORE_ADDR_MAX;
7128 if (sizeof (CORE_ADDR) == 8)
7129 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7130 a compiler warning produced where CORE_ADDR is a 32-bit type even
7131 though in that case this is dead code). */
7132 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3)
7135 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr)
7136 segsize = 29; /* 32-bit compatibility segment */
7138 segsize = 62; /* xkseg */
7140 case 2: /* xkphys */
7143 default: /* xksseg (1), xkuseg/kuseg (0) */
7147 else if (bpaddr & 0x80000000) /* kernel segment */
7150 segsize = 31; /* user segment */
7152 return bpaddr & mask;
7155 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7156 it backwards if necessary. Return the address of the new location. */
7159 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
7161 CORE_ADDR prev_addr;
7163 CORE_ADDR func_addr;
7165 /* If a breakpoint is set on the instruction in a branch delay slot,
7166 GDB gets confused. When the breakpoint is hit, the PC isn't on
7167 the instruction in the branch delay slot, the PC will point to
7168 the branch instruction. Since the PC doesn't match any known
7169 breakpoints, GDB reports a trap exception.
7171 There are two possible fixes for this problem.
7173 1) When the breakpoint gets hit, see if the BD bit is set in the
7174 Cause register (which indicates the last exception occurred in a
7175 branch delay slot). If the BD bit is set, fix the PC to point to
7176 the instruction in the branch delay slot.
7178 2) When the user sets the breakpoint, don't allow him to set the
7179 breakpoint on the instruction in the branch delay slot. Instead
7180 move the breakpoint to the branch instruction (which will have
7183 The problem with the first solution is that if the user then
7184 single-steps the processor, the branch instruction will get
7185 skipped (since GDB thinks the PC is on the instruction in the
7188 So, we'll use the second solution. To do this we need to know if
7189 the instruction we're trying to set the breakpoint on is in the
7190 branch delay slot. */
7192 boundary = mips_segment_boundary (bpaddr);
7194 /* Make sure we don't scan back before the beginning of the current
7195 function, since we may fetch constant data or insns that look like
7196 a jump. Of course we might do that anyway if the compiler has
7197 moved constants inline. :-( */
7198 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL)
7199 && func_addr > boundary && func_addr <= bpaddr)
7200 boundary = func_addr;
7202 if (mips_pc_is_mips (bpaddr))
7204 if (bpaddr == boundary)
7207 /* If the previous instruction has a branch delay slot, we have
7208 to move the breakpoint to the branch instruction. */
7209 prev_addr = bpaddr - 4;
7210 if (mips32_instruction_has_delay_slot (gdbarch, prev_addr))
7215 int (*instruction_has_delay_slot) (struct gdbarch *, CORE_ADDR, int);
7216 CORE_ADDR addr, jmpaddr;
7219 boundary = unmake_compact_addr (boundary);
7221 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7222 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7223 so try for that first, then try the 2 byte JALR/JR.
7224 The microMIPS ASE has a whole range of jumps and branches
7225 with delay slots, some of which take 4 bytes and some take
7226 2 bytes, so the idea is the same.
7227 FIXME: We have to assume that bpaddr is not the second half
7228 of an extended instruction. */
7229 instruction_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr)
7230 ? micromips_instruction_has_delay_slot
7231 : mips16_instruction_has_delay_slot);
7235 for (i = 1; i < 4; i++)
7237 if (unmake_compact_addr (addr) == boundary)
7239 addr -= MIPS_INSN16_SIZE;
7240 if (i == 1 && instruction_has_delay_slot (gdbarch, addr, 0))
7241 /* Looks like a JR/JALR at [target-1], but it could be
7242 the second word of a previous JAL/JALX, so record it
7243 and check back one more. */
7245 else if (i > 1 && instruction_has_delay_slot (gdbarch, addr, 1))
7248 /* Looks like a JAL/JALX at [target-2], but it could also
7249 be the second word of a previous JAL/JALX, record it,
7250 and check back one more. */
7253 /* Looks like a JAL/JALX at [target-3], so any previously
7254 recorded JAL/JALX or JR/JALR must be wrong, because:
7257 -2: JAL-ext (can't be JAL/JALX)
7258 -1: bdslot (can't be JR/JALR)
7261 Of course it could be another JAL-ext which looks
7262 like a JAL, but in that case we'd have broken out
7263 of this loop at [target-2]:
7267 -2: bdslot (can't be jmp)
7274 /* Not a jump instruction: if we're at [target-1] this
7275 could be the second word of a JAL/JALX, so continue;
7276 otherwise we're done. */
7289 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7290 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7293 mips_is_stub_suffix (const char *suffix, int zero)
7298 return zero && suffix[1] == '\0';
7300 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0');
7305 return suffix[1] == '\0';
7311 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7312 call stubs, one of sf, df, sc, or dc. */
7315 mips_is_stub_mode (const char *mode)
7317 return ((mode[0] == 's' || mode[0] == 'd')
7318 && (mode[1] == 'f' || mode[1] == 'c'));
7321 /* Code at PC is a compiler-generated stub. Such a stub for a function
7322 bar might have a name like __fn_stub_bar, and might look like this:
7329 followed by (or interspersed with):
7336 addiu $25, $25, %lo(bar)
7339 ($1 may be used in old code; for robustness we accept any register)
7342 lui $28, %hi(_gp_disp)
7343 addiu $28, $28, %lo(_gp_disp)
7346 addiu $25, $25, %lo(bar)
7349 In the case of a __call_stub_bar stub, the sequence to set up
7350 arguments might look like this:
7357 followed by (or interspersed with) one of the jump sequences above.
7359 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7360 of J or JR, respectively, followed by:
7366 We are at the beginning of the stub here, and scan down and extract
7367 the target address from the jump immediate instruction or, if a jump
7368 register instruction is used, from the register referred. Return
7369 the value of PC calculated or 0 if inconclusive.
7371 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7374 mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc)
7376 struct gdbarch *gdbarch = get_frame_arch (frame);
7377 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7378 int addrreg = MIPS_ZERO_REGNUM;
7379 CORE_ADDR start_pc = pc;
7380 CORE_ADDR target_pc = 0;
7387 status == 0 && target_pc == 0 && i < 20;
7388 i++, pc += MIPS_INSN32_SIZE)
7390 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
7396 switch (itype_op (inst))
7398 case 0: /* SPECIAL */
7399 switch (rtype_funct (inst))
7403 rs = rtype_rs (inst);
7404 if (rs == MIPS_GP_REGNUM)
7405 target_pc = gp; /* Hmm... */
7406 else if (rs == addrreg)
7410 case 0x21: /* ADDU */
7411 rt = rtype_rt (inst);
7412 rs = rtype_rs (inst);
7413 rd = rtype_rd (inst);
7414 if (rd == MIPS_GP_REGNUM
7415 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM)
7416 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM)))
7424 target_pc = jtype_target (inst) << 2;
7425 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
7429 rt = itype_rt (inst);
7430 rs = itype_rs (inst);
7433 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7434 if (rt == MIPS_GP_REGNUM)
7436 else if (rt == addrreg)
7442 rt = itype_rt (inst);
7443 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16;
7444 if (rt == MIPS_GP_REGNUM)
7446 else if (rt != MIPS_ZERO_REGNUM)
7454 rt = itype_rt (inst);
7455 rs = itype_rs (inst);
7456 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7457 if (gp != 0 && rs == MIPS_GP_REGNUM)
7461 memset (buf, 0, sizeof (buf));
7462 status = target_read_memory (gp + imm, buf, sizeof (buf));
7464 addr = extract_signed_integer (buf, sizeof (buf), byte_order);
7473 /* If PC is in a MIPS16 call or return stub, return the address of the
7474 target PC, which is either the callee or the caller. There are several
7475 cases which must be handled:
7477 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7478 and the target PC is in $31 ($ra).
7479 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7480 and the target PC is in $2.
7481 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7482 i.e. before the JALR instruction, this is effectively a call stub
7483 and the target PC is in $2. Otherwise this is effectively
7484 a return stub and the target PC is in $18.
7485 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7486 JAL or JALR instruction, this is effectively a call stub and the
7487 target PC is buried in the instruction stream. Otherwise this
7488 is effectively a return stub and the target PC is in $18.
7489 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7490 stub and the target PC is buried in the instruction stream.
7492 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7493 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7497 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7499 struct gdbarch *gdbarch = get_frame_arch (frame);
7500 CORE_ADDR start_addr;
7504 /* Find the starting address and name of the function containing the PC. */
7505 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
7508 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7509 and the target PC is in $31 ($ra). */
7510 prefixlen = strlen (mips_str_mips16_ret_stub);
7511 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7512 && mips_is_stub_mode (name + prefixlen)
7513 && name[prefixlen + 2] == '\0')
7514 return get_frame_register_signed
7515 (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
7517 /* If the PC is in __mips16_call_stub_*, this is one of the call
7518 call/return stubs. */
7519 prefixlen = strlen (mips_str_mips16_call_stub);
7520 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0)
7522 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7523 and the target PC is in $2. */
7524 if (mips_is_stub_suffix (name + prefixlen, 0))
7525 return get_frame_register_signed
7526 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7528 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7529 i.e. before the JALR instruction, this is effectively a call stub
7530 and the target PC is in $2. Otherwise this is effectively
7531 a return stub and the target PC is in $18. */
7532 else if (mips_is_stub_mode (name + prefixlen)
7533 && name[prefixlen + 2] == '_'
7534 && mips_is_stub_suffix (name + prefixlen + 3, 0))
7536 if (pc == start_addr)
7537 /* This is the 'call' part of a call stub. The return
7538 address is in $2. */
7539 return get_frame_register_signed
7540 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7542 /* This is the 'return' part of a call stub. The return
7543 address is in $18. */
7544 return get_frame_register_signed
7545 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7548 return 0; /* Not a stub. */
7551 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7552 compiler-generated call or call/return stubs. */
7553 if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0
7554 || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0)
7556 if (pc == start_addr)
7557 /* This is the 'call' part of a call stub. Call this helper
7558 to scan through this code for interesting instructions
7559 and determine the final PC. */
7560 return mips_get_mips16_fn_stub_pc (frame, pc);
7562 /* This is the 'return' part of a call stub. The return address
7564 return get_frame_register_signed
7565 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7568 return 0; /* Not a stub. */
7571 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7572 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7575 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name)
7577 CORE_ADDR start_addr;
7580 /* Find the starting address of the function containing the PC. */
7581 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
7584 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7585 the start, i.e. after the JALR instruction, this is effectively
7587 prefixlen = strlen (mips_str_mips16_call_stub);
7588 if (pc != start_addr
7589 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0
7590 && mips_is_stub_mode (name + prefixlen)
7591 && name[prefixlen + 2] == '_'
7592 && mips_is_stub_suffix (name + prefixlen + 3, 1))
7595 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7596 the JAL or JALR instruction, this is effectively a return stub. */
7597 prefixlen = strlen (mips_str_call_fp_stub);
7598 if (pc != start_addr
7599 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0)
7602 /* Consume the .pic. prefix of any PIC stub, this function must return
7603 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7604 or the call stub path will trigger in handle_inferior_event causing
7606 prefixlen = strlen (mips_str_pic);
7607 if (strncmp (name, mips_str_pic, prefixlen) == 0)
7610 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7611 prefixlen = strlen (mips_str_mips16_ret_stub);
7612 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7613 && mips_is_stub_mode (name + prefixlen)
7614 && name[prefixlen + 2] == '\0')
7617 return 0; /* Not a stub. */
7620 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7621 PC of the stub target. The stub just loads $t9 and jumps to it,
7622 so that $t9 has the correct value at function entry. */
7625 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7627 struct gdbarch *gdbarch = get_frame_arch (frame);
7628 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7629 struct minimal_symbol *msym;
7631 gdb_byte stub_code[16];
7632 int32_t stub_words[4];
7634 /* The stub for foo is named ".pic.foo", and is either two
7635 instructions inserted before foo or a three instruction sequence
7636 which jumps to foo. */
7637 msym = lookup_minimal_symbol_by_pc (pc);
7639 || SYMBOL_VALUE_ADDRESS (msym) != pc
7640 || SYMBOL_LINKAGE_NAME (msym) == NULL
7641 || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0)
7644 /* A two-instruction header. */
7645 if (MSYMBOL_SIZE (msym) == 8)
7648 /* A three-instruction (plus delay slot) trampoline. */
7649 if (MSYMBOL_SIZE (msym) == 16)
7651 if (target_read_memory (pc, stub_code, 16) != 0)
7653 for (i = 0; i < 4; i++)
7654 stub_words[i] = extract_unsigned_integer (stub_code + i * 4,
7657 /* A stub contains these instructions:
7660 addiu t9, t9, %lo(target)
7663 This works even for N64, since stubs are only generated with
7665 if ((stub_words[0] & 0xffff0000U) == 0x3c190000
7666 && (stub_words[1] & 0xfc000000U) == 0x08000000
7667 && (stub_words[2] & 0xffff0000U) == 0x27390000
7668 && stub_words[3] == 0x00000000)
7669 return ((((stub_words[0] & 0x0000ffff) << 16)
7670 + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7673 /* Not a recognized stub. */
7678 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7680 CORE_ADDR requested_pc = pc;
7681 CORE_ADDR target_pc;
7688 new_pc = mips_skip_mips16_trampoline_code (frame, pc);
7692 if (is_compact_addr (pc))
7693 pc = unmake_compact_addr (pc);
7696 new_pc = find_solib_trampoline_target (frame, pc);
7700 if (is_compact_addr (pc))
7701 pc = unmake_compact_addr (pc);
7704 new_pc = mips_skip_pic_trampoline_code (frame, pc);
7708 if (is_compact_addr (pc))
7709 pc = unmake_compact_addr (pc);
7712 while (pc != target_pc);
7714 return pc != requested_pc ? pc : 0;
7717 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7718 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7721 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
7724 if (num >= 0 && num < 32)
7726 else if (num >= 38 && num < 70)
7727 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
7729 regnum = mips_regnum (gdbarch)->hi;
7731 regnum = mips_regnum (gdbarch)->lo;
7732 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78)
7733 regnum = num + mips_regnum (gdbarch)->dspacc - 72;
7735 /* This will hopefully (eventually) provoke a warning. Should
7736 we be calling complaint() here? */
7737 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
7738 return gdbarch_num_regs (gdbarch) + regnum;
7742 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7743 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7746 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
7749 if (num >= 0 && num < 32)
7751 else if (num >= 32 && num < 64)
7752 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
7754 regnum = mips_regnum (gdbarch)->hi;
7756 regnum = mips_regnum (gdbarch)->lo;
7757 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72)
7758 regnum = num + mips_regnum (gdbarch)->dspacc - 66;
7760 /* This will hopefully (eventually) provoke a warning. Should we
7761 be calling complaint() here? */
7762 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
7763 return gdbarch_num_regs (gdbarch) + regnum;
7767 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
7769 /* Only makes sense to supply raw registers. */
7770 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
7771 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7772 decide if it is valid. Should instead define a standard sim/gdb
7773 register numbering scheme. */
7774 if (gdbarch_register_name (gdbarch,
7775 gdbarch_num_regs (gdbarch) + regnum) != NULL
7776 && gdbarch_register_name (gdbarch,
7777 gdbarch_num_regs (gdbarch)
7778 + regnum)[0] != '\0')
7781 return LEGACY_SIM_REGNO_IGNORE;
7785 /* Convert an integer into an address. Extracting the value signed
7786 guarantees a correctly sign extended address. */
7789 mips_integer_to_address (struct gdbarch *gdbarch,
7790 struct type *type, const gdb_byte *buf)
7792 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7793 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
7796 /* Dummy virtual frame pointer method. This is no more or less accurate
7797 than most other architectures; we just need to be explicit about it,
7798 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7799 an assertion failure. */
7802 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
7803 CORE_ADDR pc, int *reg, LONGEST *offset)
7805 *reg = MIPS_SP_REGNUM;
7810 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
7812 enum mips_abi *abip = (enum mips_abi *) obj;
7813 const char *name = bfd_get_section_name (abfd, sect);
7815 if (*abip != MIPS_ABI_UNKNOWN)
7818 if (strncmp (name, ".mdebug.", 8) != 0)
7821 if (strcmp (name, ".mdebug.abi32") == 0)
7822 *abip = MIPS_ABI_O32;
7823 else if (strcmp (name, ".mdebug.abiN32") == 0)
7824 *abip = MIPS_ABI_N32;
7825 else if (strcmp (name, ".mdebug.abi64") == 0)
7826 *abip = MIPS_ABI_N64;
7827 else if (strcmp (name, ".mdebug.abiO64") == 0)
7828 *abip = MIPS_ABI_O64;
7829 else if (strcmp (name, ".mdebug.eabi32") == 0)
7830 *abip = MIPS_ABI_EABI32;
7831 else if (strcmp (name, ".mdebug.eabi64") == 0)
7832 *abip = MIPS_ABI_EABI64;
7834 warning (_("unsupported ABI %s."), name + 8);
7838 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
7840 int *lbp = (int *) obj;
7841 const char *name = bfd_get_section_name (abfd, sect);
7843 if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
7845 else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
7847 else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
7848 warning (_("unrecognized .gcc_compiled_longXX"));
7851 static enum mips_abi
7852 global_mips_abi (void)
7856 for (i = 0; mips_abi_strings[i] != NULL; i++)
7857 if (mips_abi_strings[i] == mips_abi_string)
7858 return (enum mips_abi) i;
7860 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
7863 /* Return the default compressed instruction set, either of MIPS16
7864 or microMIPS, selected when none could have been determined from
7865 the ELF header of the binary being executed (or no binary has been
7868 static enum mips_isa
7869 global_mips_compression (void)
7873 for (i = 0; mips_compression_strings[i] != NULL; i++)
7874 if (mips_compression_strings[i] == mips_compression_string)
7875 return (enum mips_isa) i;
7877 internal_error (__FILE__, __LINE__, _("unknown compressed ISA string"));
7881 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
7883 /* If the size matches the set of 32-bit or 64-bit integer registers,
7884 assume that's what we've got. */
7885 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
7886 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
7888 /* If the size matches the full set of registers GDB traditionally
7889 knows about, including floating point, for either 32-bit or
7890 64-bit, assume that's what we've got. */
7891 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
7892 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
7894 /* Otherwise we don't have a useful guess. */
7897 static struct value *
7898 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
7900 const int *reg_p = baton;
7901 return value_of_register (*reg_p, frame);
7904 static struct gdbarch *
7905 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7907 struct gdbarch *gdbarch;
7908 struct gdbarch_tdep *tdep;
7910 enum mips_abi mips_abi, found_abi, wanted_abi;
7912 enum mips_fpu_type fpu_type;
7913 struct tdesc_arch_data *tdesc_data = NULL;
7914 int elf_fpu_type = 0;
7915 const char **reg_names;
7916 struct mips_regnum mips_regnum, *regnum;
7917 enum mips_isa mips_isa;
7921 /* Fill in the OS dependent register numbers and names. */
7922 if (info.osabi == GDB_OSABI_IRIX)
7924 mips_regnum.fp0 = 32;
7925 mips_regnum.pc = 64;
7926 mips_regnum.cause = 65;
7927 mips_regnum.badvaddr = 66;
7928 mips_regnum.hi = 67;
7929 mips_regnum.lo = 68;
7930 mips_regnum.fp_control_status = 69;
7931 mips_regnum.fp_implementation_revision = 70;
7932 mips_regnum.dspacc = dspacc = -1;
7933 mips_regnum.dspctl = dspctl = -1;
7935 reg_names = mips_irix_reg_names;
7937 else if (info.osabi == GDB_OSABI_LINUX)
7939 mips_regnum.fp0 = 38;
7940 mips_regnum.pc = 37;
7941 mips_regnum.cause = 36;
7942 mips_regnum.badvaddr = 35;
7943 mips_regnum.hi = 34;
7944 mips_regnum.lo = 33;
7945 mips_regnum.fp_control_status = 70;
7946 mips_regnum.fp_implementation_revision = 71;
7947 mips_regnum.dspacc = -1;
7948 mips_regnum.dspctl = -1;
7952 reg_names = mips_linux_reg_names;
7956 mips_regnum.lo = MIPS_EMBED_LO_REGNUM;
7957 mips_regnum.hi = MIPS_EMBED_HI_REGNUM;
7958 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
7959 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM;
7960 mips_regnum.pc = MIPS_EMBED_PC_REGNUM;
7961 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM;
7962 mips_regnum.fp_control_status = 70;
7963 mips_regnum.fp_implementation_revision = 71;
7964 mips_regnum.dspacc = dspacc = -1;
7965 mips_regnum.dspctl = dspctl = -1;
7966 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
7967 if (info.bfd_arch_info != NULL
7968 && info.bfd_arch_info->mach == bfd_mach_mips3900)
7969 reg_names = mips_tx39_reg_names;
7971 reg_names = mips_generic_reg_names;
7974 /* Check any target description for validity. */
7975 if (tdesc_has_registers (info.target_desc))
7977 static const char *const mips_gprs[] = {
7978 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7979 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7980 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7981 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7983 static const char *const mips_fprs[] = {
7984 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7985 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7986 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7987 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
7990 const struct tdesc_feature *feature;
7993 feature = tdesc_find_feature (info.target_desc,
7994 "org.gnu.gdb.mips.cpu");
7995 if (feature == NULL)
7998 tdesc_data = tdesc_data_alloc ();
8001 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
8002 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8006 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8007 mips_regnum.lo, "lo");
8008 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8009 mips_regnum.hi, "hi");
8010 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8011 mips_regnum.pc, "pc");
8015 tdesc_data_cleanup (tdesc_data);
8019 feature = tdesc_find_feature (info.target_desc,
8020 "org.gnu.gdb.mips.cp0");
8021 if (feature == NULL)
8023 tdesc_data_cleanup (tdesc_data);
8028 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8029 mips_regnum.badvaddr, "badvaddr");
8030 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8031 MIPS_PS_REGNUM, "status");
8032 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8033 mips_regnum.cause, "cause");
8037 tdesc_data_cleanup (tdesc_data);
8041 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8042 backend is not prepared for that, though. */
8043 feature = tdesc_find_feature (info.target_desc,
8044 "org.gnu.gdb.mips.fpu");
8045 if (feature == NULL)
8047 tdesc_data_cleanup (tdesc_data);
8052 for (i = 0; i < 32; i++)
8053 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8054 i + mips_regnum.fp0, mips_fprs[i]);
8056 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8057 mips_regnum.fp_control_status,
8060 &= tdesc_numbered_register (feature, tdesc_data,
8061 mips_regnum.fp_implementation_revision,
8066 tdesc_data_cleanup (tdesc_data);
8072 feature = tdesc_find_feature (info.target_desc,
8073 "org.gnu.gdb.mips.dsp");
8074 /* The DSP registers are optional; it's OK if they are absent. */
8075 if (feature != NULL)
8079 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8080 dspacc + i++, "hi1");
8081 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8082 dspacc + i++, "lo1");
8083 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8084 dspacc + i++, "hi2");
8085 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8086 dspacc + i++, "lo2");
8087 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8088 dspacc + i++, "hi3");
8089 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8090 dspacc + i++, "lo3");
8092 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8097 tdesc_data_cleanup (tdesc_data);
8101 mips_regnum.dspacc = dspacc;
8102 mips_regnum.dspctl = dspctl;
8106 /* It would be nice to detect an attempt to use a 64-bit ABI
8107 when only 32-bit registers are provided. */
8111 /* First of all, extract the elf_flags, if available. */
8112 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8113 elf_flags = elf_elfheader (info.abfd)->e_flags;
8114 else if (arches != NULL)
8115 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
8119 fprintf_unfiltered (gdb_stdlog,
8120 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
8122 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8123 switch ((elf_flags & EF_MIPS_ABI))
8125 case E_MIPS_ABI_O32:
8126 found_abi = MIPS_ABI_O32;
8128 case E_MIPS_ABI_O64:
8129 found_abi = MIPS_ABI_O64;
8131 case E_MIPS_ABI_EABI32:
8132 found_abi = MIPS_ABI_EABI32;
8134 case E_MIPS_ABI_EABI64:
8135 found_abi = MIPS_ABI_EABI64;
8138 if ((elf_flags & EF_MIPS_ABI2))
8139 found_abi = MIPS_ABI_N32;
8141 found_abi = MIPS_ABI_UNKNOWN;
8145 /* GCC creates a pseudo-section whose name describes the ABI. */
8146 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
8147 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
8149 /* If we have no useful BFD information, use the ABI from the last
8150 MIPS architecture (if there is one). */
8151 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
8152 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
8154 /* Try the architecture for any hint of the correct ABI. */
8155 if (found_abi == MIPS_ABI_UNKNOWN
8156 && info.bfd_arch_info != NULL
8157 && info.bfd_arch_info->arch == bfd_arch_mips)
8159 switch (info.bfd_arch_info->mach)
8161 case bfd_mach_mips3900:
8162 found_abi = MIPS_ABI_EABI32;
8164 case bfd_mach_mips4100:
8165 case bfd_mach_mips5000:
8166 found_abi = MIPS_ABI_EABI64;
8168 case bfd_mach_mips8000:
8169 case bfd_mach_mips10000:
8170 /* On Irix, ELF64 executables use the N64 ABI. The
8171 pseudo-sections which describe the ABI aren't present
8172 on IRIX. (Even for executables created by gcc.) */
8173 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8174 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8175 found_abi = MIPS_ABI_N64;
8177 found_abi = MIPS_ABI_N32;
8182 /* Default 64-bit objects to N64 instead of O32. */
8183 if (found_abi == MIPS_ABI_UNKNOWN
8184 && info.abfd != NULL
8185 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8186 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8187 found_abi = MIPS_ABI_N64;
8190 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
8193 /* What has the user specified from the command line? */
8194 wanted_abi = global_mips_abi ();
8196 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
8199 /* Now that we have found what the ABI for this binary would be,
8200 check whether the user is overriding it. */
8201 if (wanted_abi != MIPS_ABI_UNKNOWN)
8202 mips_abi = wanted_abi;
8203 else if (found_abi != MIPS_ABI_UNKNOWN)
8204 mips_abi = found_abi;
8206 mips_abi = MIPS_ABI_O32;
8208 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
8211 /* Determine the default compressed ISA. */
8212 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0
8213 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0)
8214 mips_isa = ISA_MICROMIPS;
8215 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0
8216 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0)
8217 mips_isa = ISA_MIPS16;
8219 mips_isa = global_mips_compression ();
8220 mips_compression_string = mips_compression_strings[mips_isa];
8222 /* Also used when doing an architecture lookup. */
8224 fprintf_unfiltered (gdb_stdlog,
8225 "mips_gdbarch_init: "
8226 "mips64_transfers_32bit_regs_p = %d\n",
8227 mips64_transfers_32bit_regs_p);
8229 /* Determine the MIPS FPU type. */
8232 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8233 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
8234 Tag_GNU_MIPS_ABI_FP);
8235 #endif /* HAVE_ELF */
8237 if (!mips_fpu_type_auto)
8238 fpu_type = mips_fpu_type;
8239 else if (elf_fpu_type != 0)
8241 switch (elf_fpu_type)
8244 fpu_type = MIPS_FPU_DOUBLE;
8247 fpu_type = MIPS_FPU_SINGLE;
8251 /* Soft float or unknown. */
8252 fpu_type = MIPS_FPU_NONE;
8256 else if (info.bfd_arch_info != NULL
8257 && info.bfd_arch_info->arch == bfd_arch_mips)
8258 switch (info.bfd_arch_info->mach)
8260 case bfd_mach_mips3900:
8261 case bfd_mach_mips4100:
8262 case bfd_mach_mips4111:
8263 case bfd_mach_mips4120:
8264 fpu_type = MIPS_FPU_NONE;
8266 case bfd_mach_mips4650:
8267 fpu_type = MIPS_FPU_SINGLE;
8270 fpu_type = MIPS_FPU_DOUBLE;
8273 else if (arches != NULL)
8274 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
8276 fpu_type = MIPS_FPU_DOUBLE;
8278 fprintf_unfiltered (gdb_stdlog,
8279 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
8281 /* Check for blatant incompatibilities. */
8283 /* If we have only 32-bit registers, then we can't debug a 64-bit
8285 if (info.target_desc
8286 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
8287 && mips_abi != MIPS_ABI_EABI32
8288 && mips_abi != MIPS_ABI_O32)
8290 if (tdesc_data != NULL)
8291 tdesc_data_cleanup (tdesc_data);
8295 /* Try to find a pre-existing architecture. */
8296 for (arches = gdbarch_list_lookup_by_info (arches, &info);
8298 arches = gdbarch_list_lookup_by_info (arches->next, &info))
8300 /* MIPS needs to be pedantic about which ABI the object is
8302 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
8304 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
8306 /* Need to be pedantic about which register virtual size is
8308 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
8309 != mips64_transfers_32bit_regs_p)
8311 /* Be pedantic about which FPU is selected. */
8312 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
8315 if (tdesc_data != NULL)
8316 tdesc_data_cleanup (tdesc_data);
8317 return arches->gdbarch;
8320 /* Need a new architecture. Fill in a target specific vector. */
8321 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
8322 gdbarch = gdbarch_alloc (&info, tdep);
8323 tdep->elf_flags = elf_flags;
8324 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
8325 tdep->found_abi = found_abi;
8326 tdep->mips_abi = mips_abi;
8327 tdep->mips_isa = mips_isa;
8328 tdep->mips_fpu_type = fpu_type;
8329 tdep->register_size_valid_p = 0;
8330 tdep->register_size = 0;
8331 tdep->gregset = NULL;
8332 tdep->gregset64 = NULL;
8333 tdep->fpregset = NULL;
8334 tdep->fpregset64 = NULL;
8336 if (info.target_desc)
8338 /* Some useful properties can be inferred from the target. */
8339 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
8341 tdep->register_size_valid_p = 1;
8342 tdep->register_size = 4;
8344 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
8346 tdep->register_size_valid_p = 1;
8347 tdep->register_size = 8;
8351 /* Initially set everything according to the default ABI/ISA. */
8352 set_gdbarch_short_bit (gdbarch, 16);
8353 set_gdbarch_int_bit (gdbarch, 32);
8354 set_gdbarch_float_bit (gdbarch, 32);
8355 set_gdbarch_double_bit (gdbarch, 64);
8356 set_gdbarch_long_double_bit (gdbarch, 64);
8357 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
8358 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
8359 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
8361 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8362 mips_ax_pseudo_register_collect);
8363 set_gdbarch_ax_pseudo_register_push_stack
8364 (gdbarch, mips_ax_pseudo_register_push_stack);
8366 set_gdbarch_elf_make_msymbol_special (gdbarch,
8367 mips_elf_make_msymbol_special);
8369 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum);
8370 *regnum = mips_regnum;
8371 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
8372 set_gdbarch_num_regs (gdbarch, num_regs);
8373 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8374 set_gdbarch_register_name (gdbarch, mips_register_name);
8375 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
8376 tdep->mips_processor_reg_names = reg_names;
8377 tdep->regnum = regnum;
8382 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
8383 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
8384 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8385 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8386 tdep->default_mask_address_p = 0;
8387 set_gdbarch_long_bit (gdbarch, 32);
8388 set_gdbarch_ptr_bit (gdbarch, 32);
8389 set_gdbarch_long_long_bit (gdbarch, 64);
8392 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
8393 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
8394 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8395 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8396 tdep->default_mask_address_p = 0;
8397 set_gdbarch_long_bit (gdbarch, 32);
8398 set_gdbarch_ptr_bit (gdbarch, 32);
8399 set_gdbarch_long_long_bit (gdbarch, 64);
8401 case MIPS_ABI_EABI32:
8402 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8403 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8404 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8405 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8406 tdep->default_mask_address_p = 0;
8407 set_gdbarch_long_bit (gdbarch, 32);
8408 set_gdbarch_ptr_bit (gdbarch, 32);
8409 set_gdbarch_long_long_bit (gdbarch, 64);
8411 case MIPS_ABI_EABI64:
8412 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8413 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8414 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8415 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8416 tdep->default_mask_address_p = 0;
8417 set_gdbarch_long_bit (gdbarch, 64);
8418 set_gdbarch_ptr_bit (gdbarch, 64);
8419 set_gdbarch_long_long_bit (gdbarch, 64);
8422 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8423 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8424 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8425 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8426 tdep->default_mask_address_p = 0;
8427 set_gdbarch_long_bit (gdbarch, 32);
8428 set_gdbarch_ptr_bit (gdbarch, 32);
8429 set_gdbarch_long_long_bit (gdbarch, 64);
8430 set_gdbarch_long_double_bit (gdbarch, 128);
8431 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8434 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8435 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8436 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8437 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8438 tdep->default_mask_address_p = 0;
8439 set_gdbarch_long_bit (gdbarch, 64);
8440 set_gdbarch_ptr_bit (gdbarch, 64);
8441 set_gdbarch_long_long_bit (gdbarch, 64);
8442 set_gdbarch_long_double_bit (gdbarch, 128);
8443 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8446 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8449 /* GCC creates a pseudo-section whose name specifies the size of
8450 longs, since -mlong32 or -mlong64 may be used independent of
8451 other options. How those options affect pointer sizes is ABI and
8452 architecture dependent, so use them to override the default sizes
8453 set by the ABI. This table shows the relationship between ABI,
8454 -mlongXX, and size of pointers:
8456 ABI -mlongXX ptr bits
8457 --- -------- --------
8471 Note that for o32 and eabi32, pointers are always 32 bits
8472 regardless of any -mlongXX option. For all others, pointers and
8473 longs are the same, as set by -mlongXX or set by defaults. */
8475 if (info.abfd != NULL)
8479 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
8482 set_gdbarch_long_bit (gdbarch, long_bit);
8486 case MIPS_ABI_EABI32:
8491 case MIPS_ABI_EABI64:
8492 set_gdbarch_ptr_bit (gdbarch, long_bit);
8495 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8500 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8501 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8504 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8505 flag in object files because to do so would make it impossible to
8506 link with libraries compiled without "-gp32". This is
8507 unnecessarily restrictive.
8509 We could solve this problem by adding "-gp32" multilibs to gcc,
8510 but to set this flag before gcc is built with such multilibs will
8511 break too many systems.''
8513 But even more unhelpfully, the default linker output target for
8514 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8515 for 64-bit programs - you need to change the ABI to change this,
8516 and not all gcc targets support that currently. Therefore using
8517 this flag to detect 32-bit mode would do the wrong thing given
8518 the current gcc - it would make GDB treat these 64-bit programs
8519 as 32-bit programs by default. */
8521 set_gdbarch_read_pc (gdbarch, mips_read_pc);
8522 set_gdbarch_write_pc (gdbarch, mips_write_pc);
8524 /* Add/remove bits from an address. The MIPS needs be careful to
8525 ensure that all 32 bit addresses are sign extended to 64 bits. */
8526 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
8528 /* Unwind the frame. */
8529 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
8530 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
8531 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
8533 /* Map debug register numbers onto internal register numbers. */
8534 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
8535 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
8536 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8537 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
8538 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8539 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
8541 /* MIPS version of CALL_DUMMY. */
8543 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8544 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code);
8545 set_gdbarch_frame_align (gdbarch, mips_frame_align);
8547 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
8548 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
8549 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
8551 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8552 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
8553 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
8554 mips_remote_breakpoint_from_pc);
8555 set_gdbarch_adjust_breakpoint_address (gdbarch,
8556 mips_adjust_breakpoint_address);
8558 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
8560 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
8562 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
8563 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
8564 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
8566 set_gdbarch_register_type (gdbarch, mips_register_type);
8568 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
8570 if (mips_abi == MIPS_ABI_N32)
8571 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
8572 else if (mips_abi == MIPS_ABI_N64)
8573 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
8575 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
8577 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8578 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8579 need to all be folded into the target vector. Since they are
8580 being used as guards for target_stopped_by_watchpoint, why not have
8581 target_stopped_by_watchpoint return the type of watchpoint that the code
8583 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
8585 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
8587 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8588 to support MIPS16. This is a bad thing. Make sure not to do it
8589 if we have an OS ABI that actually supports shared libraries, since
8590 shared library support is more important. If we have an OS someday
8591 that supports both shared libraries and MIPS16, we'll have to find
8592 a better place for these.
8593 macro/2012-04-25: But that applies to return trampolines only and
8594 currently no MIPS OS ABI uses shared libraries that have them. */
8595 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
8597 set_gdbarch_single_step_through_delay (gdbarch,
8598 mips_single_step_through_delay);
8600 /* Virtual tables. */
8601 set_gdbarch_vbit_in_delta (gdbarch, 1);
8603 mips_register_g_packet_guesses (gdbarch);
8605 /* Hook in OS ABI-specific overrides, if they have been registered. */
8606 info.tdep_info = (void *) tdesc_data;
8607 gdbarch_init_osabi (info, gdbarch);
8609 /* The hook may have adjusted num_regs, fetch the final value and
8610 set pc_regnum and sp_regnum now that it has been fixed. */
8611 num_regs = gdbarch_num_regs (gdbarch);
8612 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
8613 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8615 /* Unwind the frame. */
8616 dwarf2_append_unwinders (gdbarch);
8617 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
8618 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
8619 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind);
8620 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
8621 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
8622 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
8623 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
8624 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer);
8625 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
8629 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
8630 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
8632 /* Override the normal target description methods to handle our
8633 dual real and pseudo registers. */
8634 set_gdbarch_register_name (gdbarch, mips_register_name);
8635 set_gdbarch_register_reggroup_p (gdbarch,
8636 mips_tdesc_register_reggroup_p);
8638 num_regs = gdbarch_num_regs (gdbarch);
8639 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8640 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
8641 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8644 /* Add ABI-specific aliases for the registers. */
8645 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
8646 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
8647 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
8648 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
8650 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
8651 user_reg_add (gdbarch, mips_o32_aliases[i].name,
8652 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
8654 /* Add some other standard aliases. */
8655 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
8656 user_reg_add (gdbarch, mips_register_aliases[i].name,
8657 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
8659 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)
8660 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,
8661 value_of_mips_user_reg,
8662 &mips_numeric_register_aliases[i].regnum);
8668 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
8670 struct gdbarch_info info;
8672 /* Force the architecture to update, and (if it's a MIPS architecture)
8673 mips_gdbarch_init will take care of the rest. */
8674 gdbarch_info_init (&info);
8675 gdbarch_update_p (info);
8678 /* Print out which MIPS ABI is in use. */
8681 show_mips_abi (struct ui_file *file,
8683 struct cmd_list_element *ignored_cmd,
8684 const char *ignored_value)
8686 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
8689 "The MIPS ABI is unknown because the current architecture "
8693 enum mips_abi global_abi = global_mips_abi ();
8694 enum mips_abi actual_abi = mips_abi (target_gdbarch);
8695 const char *actual_abi_str = mips_abi_strings[actual_abi];
8697 if (global_abi == MIPS_ABI_UNKNOWN)
8700 "The MIPS ABI is set automatically (currently \"%s\").\n",
8702 else if (global_abi == actual_abi)
8705 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8709 /* Probably shouldn't happen... */
8710 fprintf_filtered (file,
8711 "The (auto detected) MIPS ABI \"%s\" is in use "
8712 "even though the user setting was \"%s\".\n",
8713 actual_abi_str, mips_abi_strings[global_abi]);
8718 /* Print out which MIPS compressed ISA encoding is used. */
8721 show_mips_compression (struct ui_file *file, int from_tty,
8722 struct cmd_list_element *c, const char *value)
8724 fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"),
8729 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
8731 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8735 int ef_mips_32bitmode;
8736 /* Determine the ISA. */
8737 switch (tdep->elf_flags & EF_MIPS_ARCH)
8755 /* Determine the size of a pointer. */
8756 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
8757 fprintf_unfiltered (file,
8758 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8760 fprintf_unfiltered (file,
8761 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8763 fprintf_unfiltered (file,
8764 "mips_dump_tdep: ef_mips_arch = %d\n",
8766 fprintf_unfiltered (file,
8767 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8768 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
8769 fprintf_unfiltered (file,
8771 "mips_mask_address_p() %d (default %d)\n",
8772 mips_mask_address_p (tdep),
8773 tdep->default_mask_address_p);
8775 fprintf_unfiltered (file,
8776 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8777 MIPS_DEFAULT_FPU_TYPE,
8778 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
8779 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
8780 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
8782 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
8783 MIPS_EABI (gdbarch));
8784 fprintf_unfiltered (file,
8785 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8786 MIPS_FPU_TYPE (gdbarch),
8787 (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none"
8788 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single"
8789 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double"
8793 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
8796 _initialize_mips_tdep (void)
8798 static struct cmd_list_element *mipsfpulist = NULL;
8799 struct cmd_list_element *c;
8801 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
8802 if (MIPS_ABI_LAST + 1
8803 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
8804 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
8806 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
8808 mips_pdr_data = register_objfile_data ();
8810 /* Create feature sets with the appropriate properties. The values
8811 are not important. */
8812 mips_tdesc_gp32 = allocate_target_description ();
8813 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
8815 mips_tdesc_gp64 = allocate_target_description ();
8816 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
8818 /* Add root prefix command for all "set mips"/"show mips" commands. */
8819 add_prefix_cmd ("mips", no_class, set_mips_command,
8820 _("Various MIPS specific commands."),
8821 &setmipscmdlist, "set mips ", 0, &setlist);
8823 add_prefix_cmd ("mips", no_class, show_mips_command,
8824 _("Various MIPS specific commands."),
8825 &showmipscmdlist, "show mips ", 0, &showlist);
8827 /* Allow the user to override the ABI. */
8828 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
8829 &mips_abi_string, _("\
8830 Set the MIPS ABI used by this program."), _("\
8831 Show the MIPS ABI used by this program."), _("\
8832 This option can be set to one of:\n\
8833 auto - the default ABI associated with the current binary\n\
8842 &setmipscmdlist, &showmipscmdlist);
8844 /* Allow the user to set the ISA to assume for compressed code if ELF
8845 file flags don't tell or there is no program file selected. This
8846 setting is updated whenever unambiguous ELF file flags are interpreted,
8847 and carried over to subsequent sessions. */
8848 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings,
8849 &mips_compression_string, _("\
8850 Set the compressed ISA encoding used by MIPS code."), _("\
8851 Show the compressed ISA encoding used by MIPS code."), _("\
8852 Select the compressed ISA encoding used in functions that have no symbol\n\
8853 information available. The encoding can be set to either of:\n\
8856 and is updated automatically from ELF file flags if available."),
8858 show_mips_compression,
8859 &setmipscmdlist, &showmipscmdlist);
8861 /* Let the user turn off floating point and set the fence post for
8862 heuristic_proc_start. */
8864 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
8865 _("Set use of MIPS floating-point coprocessor."),
8866 &mipsfpulist, "set mipsfpu ", 0, &setlist);
8867 add_cmd ("single", class_support, set_mipsfpu_single_command,
8868 _("Select single-precision MIPS floating-point coprocessor."),
8870 add_cmd ("double", class_support, set_mipsfpu_double_command,
8871 _("Select double-precision MIPS floating-point coprocessor."),
8873 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
8874 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
8875 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
8876 add_cmd ("none", class_support, set_mipsfpu_none_command,
8877 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
8878 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
8879 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
8880 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
8881 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
8882 _("Select MIPS floating-point coprocessor automatically."),
8884 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
8885 _("Show current use of MIPS floating-point coprocessor target."),
8888 /* We really would like to have both "0" and "unlimited" work, but
8889 command.c doesn't deal with that. So make it a var_zinteger
8890 because the user can always use "999999" or some such for unlimited. */
8891 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
8892 &heuristic_fence_post, _("\
8893 Set the distance searched for the start of a function."), _("\
8894 Show the distance searched for the start of a function."), _("\
8895 If you are debugging a stripped executable, GDB needs to search through the\n\
8896 program for the start of a function. This command sets the distance of the\n\
8897 search. The only need to set it is when debugging a stripped executable."),
8898 reinit_frame_cache_sfunc,
8899 NULL, /* FIXME: i18n: The distance searched for
8900 the start of a function is %s. */
8901 &setlist, &showlist);
8903 /* Allow the user to control whether the upper bits of 64-bit
8904 addresses should be zeroed. */
8905 add_setshow_auto_boolean_cmd ("mask-address", no_class,
8906 &mask_address_var, _("\
8907 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
8908 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
8909 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
8910 allow GDB to determine the correct value."),
8911 NULL, show_mask_address,
8912 &setmipscmdlist, &showmipscmdlist);
8914 /* Allow the user to control the size of 32 bit registers within the
8915 raw remote packet. */
8916 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
8917 &mips64_transfers_32bit_regs_p, _("\
8918 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8920 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8922 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
8923 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
8924 64 bits for others. Use \"off\" to disable compatibility mode"),
8925 set_mips64_transfers_32bit_regs,
8926 NULL, /* FIXME: i18n: Compatibility with 64-bit
8927 MIPS target that transfers 32-bit
8928 quantities is %s. */
8929 &setlist, &showlist);
8931 /* Debug this files internals. */
8932 add_setshow_zuinteger_cmd ("mips", class_maintenance,
8934 Set mips debugging."), _("\
8935 Show mips debugging."), _("\
8936 When non-zero, mips specific debugging is enabled."),
8938 NULL, /* FIXME: i18n: Mips debugging is
8940 &setdebuglist, &showdebuglist);