1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE = 4,
57 MIPS_FPU_DOUBLE_REGSIZE = 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string;
76 static const char *mips_abi_strings[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto[] = "auto";
98 static const char size_32[] = "32";
99 static const char size_64[] = "64";
101 static const char *size_enums[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE /* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto = 1;
123 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
125 static int mips_debug = 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi;
135 enum mips_abi found_abi;
136 enum mips_fpu_type mips_fpu_type;
137 int mips_last_arg_regnum;
138 int mips_last_fp_arg_regnum;
139 int mips_default_saved_regsize;
140 int mips_fp_register_double;
141 int mips_default_stack_argsize;
142 int gdb_target_is_mips64;
143 int default_mask_address_p;
145 enum gdb_osabi osabi;
148 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
149 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
151 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
153 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
155 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
159 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
161 static const char *mips_saved_regsize_string = size_auto;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string == size_auto)
169 return MIPS_DEFAULT_SAVED_REGSIZE;
170 else if (mips_saved_regsize_string == size_64)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
177 compatiblity mode. A return value of 1 means that we have
178 physical 64-bit registers, but should treat them as 32-bit registers. */
181 mips2_fp_compat (void)
183 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
185 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
189 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
190 in all the places we deal with FP registers. PR gdb/413. */
191 /* Otherwise check the FR bit in the status register - it controls
192 the FP compatiblity mode. If it is clear we are in compatibility
194 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
201 /* Indicate that the ABI makes use of double-precision registers
202 provided by the FPU (rather than combining pairs of registers to
203 form double-precision values). Do not use "TARGET_IS_MIPS64" to
204 determine if the ABI is using double-precision registers. See also
206 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
208 /* The amount of space reserved on the stack for registers. This is
209 different to MIPS_SAVED_REGSIZE as it determines the alignment of
210 data allocated after the registers have run out. */
212 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
214 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
216 static const char *mips_stack_argsize_string = size_auto;
219 mips_stack_argsize (void)
221 if (mips_stack_argsize_string == size_auto)
222 return MIPS_DEFAULT_STACK_ARGSIZE;
223 else if (mips_stack_argsize_string == size_64)
225 else /* if (mips_stack_argsize_string == size_32) */
229 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
231 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
233 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
235 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
237 static void mips_print_register (int, int);
239 static mips_extra_func_info_t
240 heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int);
242 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
244 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
246 int mips_set_processor_type (char *);
248 static void mips_show_processor_type_command (char *, int);
250 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
252 static mips_extra_func_info_t
253 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame);
255 static CORE_ADDR after_prologue (CORE_ADDR pc,
256 mips_extra_func_info_t proc_desc);
258 static void mips_read_fp_register_single (int regno, char *rare_buffer);
259 static void mips_read_fp_register_double (int regno, char *rare_buffer);
261 static struct type *mips_float_register_type (void);
262 static struct type *mips_double_register_type (void);
264 /* This value is the model of MIPS in use. It is derived from the value
265 of the PrID register. */
267 char *mips_processor_type;
269 char *tmp_mips_processor_type;
271 /* The list of available "set mips " and "show mips " commands */
273 static struct cmd_list_element *setmipscmdlist = NULL;
274 static struct cmd_list_element *showmipscmdlist = NULL;
276 /* A set of original names, to be used when restoring back to generic
277 registers from a specific set. */
279 char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
280 char **mips_processor_reg_names = mips_generic_reg_names;
283 mips_register_name (int i)
285 return mips_processor_reg_names[i];
288 /* Names of IDT R3041 registers. */
290 char *mips_r3041_reg_names[] = {
291 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
292 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
293 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
294 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
295 "sr", "lo", "hi", "bad", "cause","pc",
296 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
297 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
298 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
299 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
300 "fsr", "fir", "fp", "",
301 "", "", "bus", "ccfg", "", "", "", "",
302 "", "", "port", "cmp", "", "", "epc", "prid",
305 /* Names of IDT R3051 registers. */
307 char *mips_r3051_reg_names[] = {
308 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
309 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
310 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
311 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
312 "sr", "lo", "hi", "bad", "cause","pc",
313 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
314 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
315 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
316 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
317 "fsr", "fir", "fp", "",
318 "inx", "rand", "elo", "", "ctxt", "", "", "",
319 "", "", "ehi", "", "", "", "epc", "prid",
322 /* Names of IDT R3081 registers. */
324 char *mips_r3081_reg_names[] = {
325 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
326 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
327 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
328 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
329 "sr", "lo", "hi", "bad", "cause","pc",
330 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
331 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
332 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
333 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
334 "fsr", "fir", "fp", "",
335 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
336 "", "", "ehi", "", "", "", "epc", "prid",
339 /* Names of LSI 33k registers. */
341 char *mips_lsi33k_reg_names[] = {
342 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
343 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
344 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
345 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
346 "epc", "hi", "lo", "sr", "cause","badvaddr",
347 "dcic", "bpc", "bda", "", "", "", "", "",
348 "", "", "", "", "", "", "", "",
349 "", "", "", "", "", "", "", "",
350 "", "", "", "", "", "", "", "",
352 "", "", "", "", "", "", "", "",
353 "", "", "", "", "", "", "", "",
359 } mips_processor_type_table[] = {
360 { "generic", mips_generic_reg_names },
361 { "r3041", mips_r3041_reg_names },
362 { "r3051", mips_r3051_reg_names },
363 { "r3071", mips_r3081_reg_names },
364 { "r3081", mips_r3081_reg_names },
365 { "lsi33k", mips_lsi33k_reg_names },
373 /* Table to translate MIPS16 register field to actual register number. */
374 static int mips16_to_32_reg[8] =
375 {16, 17, 2, 3, 4, 5, 6, 7};
377 /* Heuristic_proc_start may hunt through the text section for a long
378 time across a 2400 baud serial line. Allows the user to limit this
381 static unsigned int heuristic_fence_post = 0;
383 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
384 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
385 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
386 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
387 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
388 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
389 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
390 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
391 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
392 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
393 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
394 this will corrupt pdr.iline. Fortunately we don't use it. */
395 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
396 #define _PROC_MAGIC_ 0x0F0F0F0F
397 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
398 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
400 struct linked_proc_info
402 struct mips_extra_func_info info;
403 struct linked_proc_info *next;
405 *linked_proc_desc_table = NULL;
408 mips_print_extra_frame_info (struct frame_info *fi)
412 && fi->extra_info->proc_desc
413 && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS)
414 printf_filtered (" frame pointer is at %s+%s\n",
415 REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg),
416 paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
419 /* Number of bytes of storage in the actual machine representation for
420 register N. NOTE: This indirectly defines the register size
421 transfered by the GDB protocol. */
423 static int mips64_transfers_32bit_regs_p = 0;
426 mips_register_raw_size (int reg_nr)
428 if (mips64_transfers_32bit_regs_p)
429 return REGISTER_VIRTUAL_SIZE (reg_nr);
430 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
431 && FP_REGISTER_DOUBLE)
432 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
439 /* Convert between RAW and VIRTUAL registers. The RAW register size
440 defines the remote-gdb packet. */
443 mips_register_convertible (int reg_nr)
445 if (mips64_transfers_32bit_regs_p)
448 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
452 mips_register_convert_to_virtual (int n, struct type *virtual_type,
453 char *raw_buf, char *virt_buf)
455 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
457 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
458 TYPE_LENGTH (virtual_type));
462 TYPE_LENGTH (virtual_type));
466 mips_register_convert_to_raw (struct type *virtual_type, int n,
467 char *virt_buf, char *raw_buf)
469 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
470 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
471 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
473 TYPE_LENGTH (virtual_type));
477 TYPE_LENGTH (virtual_type));
480 /* Return the GDB type object for the "standard" data type
481 of data in register REG.
483 Note: kevinb/2002-08-01: The definition below should faithfully
484 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
485 definitions found in config/mips/tm-*.h. I'm concerned about
486 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
487 though. In some cases FP_REGNUM is in this range, and I doubt
488 that this code is correct for the 64-bit case. */
491 mips_register_virtual_type (int reg)
493 if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32)
495 /* Floating point registers... */
496 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
497 return builtin_type_ieee_double_big;
499 return builtin_type_ieee_double_little;
501 else if (reg == PS_REGNUM /* CR */)
502 return builtin_type_uint32;
503 else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM)
504 return builtin_type_uint32;
507 /* Everything else...
508 Return type appropriate for width of register. */
509 if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64))
510 return builtin_type_uint64;
512 return builtin_type_uint32;
516 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
521 return ADDR_BITS_REMOVE (read_register (SP_REGNUM));
524 /* Should the upper word of 64-bit addresses be zeroed? */
525 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
528 mips_mask_address_p (void)
530 switch (mask_address_var)
532 case AUTO_BOOLEAN_TRUE:
534 case AUTO_BOOLEAN_FALSE:
537 case AUTO_BOOLEAN_AUTO:
538 return MIPS_DEFAULT_MASK_ADDRESS_P;
540 internal_error (__FILE__, __LINE__,
541 "mips_mask_address_p: bad switch");
547 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
549 switch (mask_address_var)
551 case AUTO_BOOLEAN_TRUE:
552 printf_filtered ("The 32 bit mips address mask is enabled\n");
554 case AUTO_BOOLEAN_FALSE:
555 printf_filtered ("The 32 bit mips address mask is disabled\n");
557 case AUTO_BOOLEAN_AUTO:
558 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
559 mips_mask_address_p () ? "enabled" : "disabled");
562 internal_error (__FILE__, __LINE__,
563 "show_mask_address: bad switch");
568 /* Should call_function allocate stack space for a struct return? */
571 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
573 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
577 mips_n32n64_use_struct_convention (int gcc_p, struct type *type)
579 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
583 mips_o32_use_struct_convention (int gcc_p, struct type *type)
585 return 1; /* Structures are returned by ref in extra arg0. */
588 /* Should call_function pass struct by reference?
589 For each architecture, structs are passed either by
590 value or by reference, depending on their size. */
593 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
595 enum type_code typecode = TYPE_CODE (check_typedef (type));
596 int len = TYPE_LENGTH (check_typedef (type));
598 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
599 return (len > MIPS_SAVED_REGSIZE);
605 mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type)
607 return 0; /* Assumption: N32/N64 never passes struct by ref. */
611 mips_o32_reg_struct_has_addr (int gcc_p, struct type *type)
613 return 0; /* Assumption: O32/O64 never passes struct by ref. */
616 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
619 pc_is_mips16 (bfd_vma memaddr)
621 struct minimal_symbol *sym;
623 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
624 if (IS_MIPS16_ADDR (memaddr))
627 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
628 the high bit of the info field. Use this to decide if the function is
629 MIPS16 or normal MIPS. */
630 sym = lookup_minimal_symbol_by_pc (memaddr);
632 return MSYMBOL_IS_SPECIAL (sym);
637 /* MIPS believes that the PC has a sign extended value. Perhaphs the
638 all registers should be sign extended for simplicity? */
641 mips_read_pc (ptid_t ptid)
643 return read_signed_register_pid (PC_REGNUM, ptid);
646 /* This returns the PC of the first inst after the prologue. If we can't
647 find the prologue, then return 0. */
650 after_prologue (CORE_ADDR pc,
651 mips_extra_func_info_t proc_desc)
653 struct symtab_and_line sal;
654 CORE_ADDR func_addr, func_end;
656 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
657 to read the stack pointer from the current machine state, because
658 the current machine state has nothing to do with the information
659 we need from the proc_desc; and the process may or may not exist
662 proc_desc = find_proc_desc (pc, NULL, 0);
666 /* If function is frameless, then we need to do it the hard way. I
667 strongly suspect that frameless always means prologueless... */
668 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
669 && PROC_FRAME_OFFSET (proc_desc) == 0)
673 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
674 return 0; /* Unknown */
676 sal = find_pc_line (func_addr, 0);
678 if (sal.end < func_end)
681 /* The line after the prologue is after the end of the function. In this
682 case, tell the caller to find the prologue the hard way. */
687 /* Decode a MIPS32 instruction that saves a register in the stack, and
688 set the appropriate bit in the general register mask or float register mask
689 to indicate which register is saved. This is a helper function
690 for mips_find_saved_regs. */
693 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
694 unsigned long *float_mask)
698 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
699 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
700 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
702 /* It might be possible to use the instruction to
703 find the offset, rather than the code below which
704 is based on things being in a certain order in the
705 frame, but figuring out what the instruction's offset
706 is relative to might be a little tricky. */
707 reg = (inst & 0x001f0000) >> 16;
708 *gen_mask |= (1 << reg);
710 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
711 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
712 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
715 reg = ((inst & 0x001f0000) >> 16);
716 *float_mask |= (1 << reg);
720 /* Decode a MIPS16 instruction that saves a register in the stack, and
721 set the appropriate bit in the general register or float register mask
722 to indicate which register is saved. This is a helper function
723 for mips_find_saved_regs. */
726 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
728 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
730 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
731 *gen_mask |= (1 << reg);
733 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
735 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
736 *gen_mask |= (1 << reg);
738 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
739 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
740 *gen_mask |= (1 << RA_REGNUM);
744 /* Fetch and return instruction from the specified location. If the PC
745 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
748 mips_fetch_instruction (CORE_ADDR addr)
750 char buf[MIPS_INSTLEN];
754 if (pc_is_mips16 (addr))
756 instlen = MIPS16_INSTLEN;
757 addr = UNMAKE_MIPS16_ADDR (addr);
760 instlen = MIPS_INSTLEN;
761 status = read_memory_nobpt (addr, buf, instlen);
763 memory_error (status, addr);
764 return extract_unsigned_integer (buf, instlen);
768 /* These the fields of 32 bit mips instructions */
769 #define mips32_op(x) (x >> 26)
770 #define itype_op(x) (x >> 26)
771 #define itype_rs(x) ((x >> 21) & 0x1f)
772 #define itype_rt(x) ((x >> 16) & 0x1f)
773 #define itype_immediate(x) (x & 0xffff)
775 #define jtype_op(x) (x >> 26)
776 #define jtype_target(x) (x & 0x03ffffff)
778 #define rtype_op(x) (x >> 26)
779 #define rtype_rs(x) ((x >> 21) & 0x1f)
780 #define rtype_rt(x) ((x >> 16) & 0x1f)
781 #define rtype_rd(x) ((x >> 11) & 0x1f)
782 #define rtype_shamt(x) ((x >> 6) & 0x1f)
783 #define rtype_funct(x) (x & 0x3f)
786 mips32_relative_offset (unsigned long inst)
789 x = itype_immediate (inst);
790 if (x & 0x8000) /* sign bit set */
792 x |= 0xffff0000; /* sign extension */
798 /* Determine whate to set a single step breakpoint while considering
801 mips32_next_pc (CORE_ADDR pc)
805 inst = mips_fetch_instruction (pc);
806 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
808 if (itype_op (inst) >> 2 == 5)
809 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
811 op = (itype_op (inst) & 0x03);
826 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
827 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
829 int tf = itype_rt (inst) & 0x01;
830 int cnum = itype_rt (inst) >> 2;
831 int fcrcs = read_signed_register (FCRCS_REGNUM);
832 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
834 if (((cond >> cnum) & 0x01) == tf)
835 pc += mips32_relative_offset (inst) + 4;
840 pc += 4; /* Not a branch, next instruction is easy */
843 { /* This gets way messy */
845 /* Further subdivide into SPECIAL, REGIMM and other */
846 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
848 case 0: /* SPECIAL */
849 op = rtype_funct (inst);
854 /* Set PC to that address */
855 pc = read_signed_register (rtype_rs (inst));
861 break; /* end SPECIAL */
864 op = itype_rt (inst); /* branch condition */
869 case 16: /* BLTZAL */
870 case 18: /* BLTZALL */
872 if (read_signed_register (itype_rs (inst)) < 0)
873 pc += mips32_relative_offset (inst) + 4;
875 pc += 8; /* after the delay slot */
879 case 17: /* BGEZAL */
880 case 19: /* BGEZALL */
881 greater_equal_branch:
882 if (read_signed_register (itype_rs (inst)) >= 0)
883 pc += mips32_relative_offset (inst) + 4;
885 pc += 8; /* after the delay slot */
887 /* All of the other instructions in the REGIMM category */
892 break; /* end REGIMM */
897 reg = jtype_target (inst) << 2;
898 /* Upper four bits get never changed... */
899 pc = reg + ((pc + 4) & 0xf0000000);
902 /* FIXME case JALX : */
905 reg = jtype_target (inst) << 2;
906 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
907 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
909 break; /* The new PC will be alternate mode */
910 case 4: /* BEQ, BEQL */
912 if (read_signed_register (itype_rs (inst)) ==
913 read_signed_register (itype_rt (inst)))
914 pc += mips32_relative_offset (inst) + 4;
918 case 5: /* BNE, BNEL */
920 if (read_signed_register (itype_rs (inst)) !=
921 read_signed_register (itype_rt (inst)))
922 pc += mips32_relative_offset (inst) + 4;
926 case 6: /* BLEZ, BLEZL */
928 if (read_signed_register (itype_rs (inst) <= 0))
929 pc += mips32_relative_offset (inst) + 4;
935 greater_branch: /* BGTZ, BGTZL */
936 if (read_signed_register (itype_rs (inst) > 0))
937 pc += mips32_relative_offset (inst) + 4;
944 } /* mips32_next_pc */
946 /* Decoding the next place to set a breakpoint is irregular for the
947 mips 16 variant, but fortunately, there fewer instructions. We have to cope
948 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
949 We dont want to set a single step instruction on the extend instruction
953 /* Lots of mips16 instruction formats */
954 /* Predicting jumps requires itype,ritype,i8type
955 and their extensions extItype,extritype,extI8type
957 enum mips16_inst_fmts
959 itype, /* 0 immediate 5,10 */
960 ritype, /* 1 5,3,8 */
961 rrtype, /* 2 5,3,3,5 */
962 rritype, /* 3 5,3,3,5 */
963 rrrtype, /* 4 5,3,3,3,2 */
964 rriatype, /* 5 5,3,3,1,4 */
965 shifttype, /* 6 5,3,3,3,2 */
966 i8type, /* 7 5,3,8 */
967 i8movtype, /* 8 5,3,3,5 */
968 i8mov32rtype, /* 9 5,3,5,3 */
969 i64type, /* 10 5,3,8 */
970 ri64type, /* 11 5,3,3,5 */
971 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
972 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
973 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
974 extRRItype, /* 15 5,5,5,5,3,3,5 */
975 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
976 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
977 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
978 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
979 extRi64type, /* 20 5,6,5,5,3,3,5 */
980 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
982 /* I am heaping all the fields of the formats into one structure and
983 then, only the fields which are involved in instruction extension */
987 unsigned int regx; /* Function in i8 type */
992 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
993 for the bits which make up the immediatate extension. */
996 extended_offset (unsigned int extension)
999 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1001 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1003 value |= extension & 0x01f; /* extract 4:0 */
1007 /* Only call this function if you know that this is an extendable
1008 instruction, It wont malfunction, but why make excess remote memory references?
1009 If the immediate operands get sign extended or somthing, do it after
1010 the extension is performed.
1012 /* FIXME: Every one of these cases needs to worry about sign extension
1013 when the offset is to be used in relative addressing */
1017 fetch_mips_16 (CORE_ADDR pc)
1020 pc &= 0xfffffffe; /* clear the low order bit */
1021 target_read_memory (pc, buf, 2);
1022 return extract_unsigned_integer (buf, 2);
1026 unpack_mips16 (CORE_ADDR pc,
1027 unsigned int extension,
1029 enum mips16_inst_fmts insn_format,
1030 struct upk_mips16 *upk)
1035 switch (insn_format)
1042 value = extended_offset (extension);
1043 value = value << 11; /* rom for the original value */
1044 value |= inst & 0x7ff; /* eleven bits from instruction */
1048 value = inst & 0x7ff;
1049 /* FIXME : Consider sign extension */
1058 { /* A register identifier and an offset */
1059 /* Most of the fields are the same as I type but the
1060 immediate value is of a different length */
1064 value = extended_offset (extension);
1065 value = value << 8; /* from the original instruction */
1066 value |= inst & 0xff; /* eleven bits from instruction */
1067 regx = (extension >> 8) & 0x07; /* or i8 funct */
1068 if (value & 0x4000) /* test the sign bit , bit 26 */
1070 value &= ~0x3fff; /* remove the sign bit */
1076 value = inst & 0xff; /* 8 bits */
1077 regx = (inst >> 8) & 0x07; /* or i8 funct */
1078 /* FIXME: Do sign extension , this format needs it */
1079 if (value & 0x80) /* THIS CONFUSES ME */
1081 value &= 0xef; /* remove the sign bit */
1091 unsigned long value;
1092 unsigned int nexthalf;
1093 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1094 value = value << 16;
1095 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1103 internal_error (__FILE__, __LINE__,
1106 upk->offset = offset;
1113 add_offset_16 (CORE_ADDR pc, int offset)
1115 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1119 extended_mips16_next_pc (CORE_ADDR pc,
1120 unsigned int extension,
1123 int op = (insn >> 11);
1126 case 2: /* Branch */
1129 struct upk_mips16 upk;
1130 unpack_mips16 (pc, extension, insn, itype, &upk);
1131 offset = upk.offset;
1137 pc += (offset << 1) + 2;
1140 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1142 struct upk_mips16 upk;
1143 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1144 pc = add_offset_16 (pc, upk.offset);
1145 if ((insn >> 10) & 0x01) /* Exchange mode */
1146 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1153 struct upk_mips16 upk;
1155 unpack_mips16 (pc, extension, insn, ritype, &upk);
1156 reg = read_signed_register (upk.regx);
1158 pc += (upk.offset << 1) + 2;
1165 struct upk_mips16 upk;
1167 unpack_mips16 (pc, extension, insn, ritype, &upk);
1168 reg = read_signed_register (upk.regx);
1170 pc += (upk.offset << 1) + 2;
1175 case 12: /* I8 Formats btez btnez */
1177 struct upk_mips16 upk;
1179 unpack_mips16 (pc, extension, insn, i8type, &upk);
1180 /* upk.regx contains the opcode */
1181 reg = read_signed_register (24); /* Test register is 24 */
1182 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1183 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1184 /* pc = add_offset_16(pc,upk.offset) ; */
1185 pc += (upk.offset << 1) + 2;
1190 case 29: /* RR Formats JR, JALR, JALR-RA */
1192 struct upk_mips16 upk;
1193 /* upk.fmt = rrtype; */
1198 upk.regx = (insn >> 8) & 0x07;
1199 upk.regy = (insn >> 5) & 0x07;
1207 break; /* Function return instruction */
1213 break; /* BOGUS Guess */
1215 pc = read_signed_register (reg);
1222 /* This is an instruction extension. Fetch the real instruction
1223 (which follows the extension) and decode things based on
1227 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1240 mips16_next_pc (CORE_ADDR pc)
1242 unsigned int insn = fetch_mips_16 (pc);
1243 return extended_mips16_next_pc (pc, 0, insn);
1246 /* The mips_next_pc function supports single_step when the remote
1247 target monitor or stub is not developed enough to do a single_step.
1248 It works by decoding the current instruction and predicting where a
1249 branch will go. This isnt hard because all the data is available.
1250 The MIPS32 and MIPS16 variants are quite different */
1252 mips_next_pc (CORE_ADDR pc)
1255 return mips16_next_pc (pc);
1257 return mips32_next_pc (pc);
1260 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1263 Note: kevinb/2002-08-09: The only caller of this function is (and
1264 should remain) mips_frame_init_saved_regs(). In fact,
1265 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1266 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1267 functions should really be combined and now that there is only one
1268 caller, it should be straightforward. (Watch out for multiple returns
1272 mips_find_saved_regs (struct frame_info *fci)
1275 CORE_ADDR reg_position;
1276 /* r0 bit means kernel trap */
1278 /* What registers have been saved? Bitmasks. */
1279 unsigned long gen_mask, float_mask;
1280 mips_extra_func_info_t proc_desc;
1283 frame_saved_regs_zalloc (fci);
1285 /* If it is the frame for sigtramp, the saved registers are located
1286 in a sigcontext structure somewhere on the stack.
1287 If the stack layout for sigtramp changes we might have to change these
1288 constants and the companion fixup_sigtramp in mdebugread.c */
1289 #ifndef SIGFRAME_BASE
1290 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1291 above the sigtramp frame. */
1292 #define SIGFRAME_BASE MIPS_REGSIZE
1293 /* FIXME! Are these correct?? */
1294 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1295 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1296 #define SIGFRAME_FPREGSAVE_OFF \
1297 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1299 #ifndef SIGFRAME_REG_SIZE
1300 /* FIXME! Is this correct?? */
1301 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1303 if (fci->signal_handler_caller)
1305 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1307 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
1308 + ireg * SIGFRAME_REG_SIZE;
1309 fci->saved_regs[ireg] = reg_position;
1311 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1313 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
1314 + ireg * SIGFRAME_REG_SIZE;
1315 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1317 fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
1321 proc_desc = fci->extra_info->proc_desc;
1322 if (proc_desc == NULL)
1323 /* I'm not sure how/whether this can happen. Normally when we can't
1324 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1325 and set the saved_regs right away. */
1328 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1329 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1330 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1332 if ( /* In any frame other than the innermost or a frame interrupted by
1333 a signal, we assume that all registers have been saved.
1334 This assumes that all register saves in a function happen before
1335 the first function call. */
1336 (fci->next == NULL || fci->next->signal_handler_caller)
1338 /* In a dummy frame we know exactly where things are saved. */
1339 && !PROC_DESC_IS_DUMMY (proc_desc)
1341 /* Don't bother unless we are inside a function prologue. Outside the
1342 prologue, we know where everything is. */
1344 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
1346 /* Not sure exactly what kernel_trap means, but if it means
1347 the kernel saves the registers without a prologue doing it,
1348 we better not examine the prologue to see whether registers
1349 have been saved yet. */
1352 /* We need to figure out whether the registers that the proc_desc
1353 claims are saved have been saved yet. */
1357 /* Bitmasks; set if we have found a save for the register. */
1358 unsigned long gen_save_found = 0;
1359 unsigned long float_save_found = 0;
1362 /* If the address is odd, assume this is MIPS16 code. */
1363 addr = PROC_LOW_ADDR (proc_desc);
1364 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1366 /* Scan through this function's instructions preceding the current
1367 PC, and look for those that save registers. */
1368 while (addr < fci->pc)
1370 inst = mips_fetch_instruction (addr);
1371 if (pc_is_mips16 (addr))
1372 mips16_decode_reg_save (inst, &gen_save_found);
1374 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1377 gen_mask = gen_save_found;
1378 float_mask = float_save_found;
1381 /* Fill in the offsets for the registers which gen_mask says
1383 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1384 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1385 if (gen_mask & 0x80000000)
1387 fci->saved_regs[ireg] = reg_position;
1388 reg_position -= MIPS_SAVED_REGSIZE;
1391 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1392 of that normally used by gcc. Therefore, we have to fetch the first
1393 instruction of the function, and if it's an entry instruction that
1394 saves $s0 or $s1, correct their saved addresses. */
1395 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1397 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1398 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1401 int sreg_count = (inst >> 6) & 3;
1403 /* Check if the ra register was pushed on the stack. */
1404 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1406 reg_position -= MIPS_SAVED_REGSIZE;
1408 /* Check if the s0 and s1 registers were pushed on the stack. */
1409 for (reg = 16; reg < sreg_count + 16; reg++)
1411 fci->saved_regs[reg] = reg_position;
1412 reg_position -= MIPS_SAVED_REGSIZE;
1417 /* Fill in the offsets for the registers which float_mask says
1419 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
1421 /* Apparently, the freg_offset gives the offset to the first 64 bit
1424 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1425 designates the first saved 64 bit register.
1427 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1428 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1429 FREG_OFFSET, designates the address of the lower register of the
1430 register pair. Adjust the offset so that it designates the upper
1431 register of the pair -- i.e., the address of the first saved 32
1434 if (MIPS_SAVED_REGSIZE == 4)
1435 reg_position += MIPS_SAVED_REGSIZE;
1437 /* Fill in the offsets for the float registers which float_mask says
1439 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1440 if (float_mask & 0x80000000)
1442 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1443 reg_position -= MIPS_SAVED_REGSIZE;
1446 fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM];
1449 /* Set up the 'saved_regs' array. This is a data structure containing
1450 the addresses on the stack where each register has been saved, for
1451 each stack frame. Registers that have not been saved will have
1452 zero here. The stack pointer register is special: rather than the
1453 address where the stack register has been saved, saved_regs[SP_REGNUM]
1454 will have the actual value of the previous frame's stack register. */
1457 mips_frame_init_saved_regs (struct frame_info *frame)
1459 if (frame->saved_regs == NULL)
1461 mips_find_saved_regs (frame);
1463 frame->saved_regs[SP_REGNUM] = frame->frame;
1467 read_next_frame_reg (struct frame_info *fi, int regno)
1469 for (; fi; fi = fi->next)
1471 /* We have to get the saved sp from the sigcontext
1472 if it is a signal handler frame. */
1473 if (regno == SP_REGNUM && !fi->signal_handler_caller)
1477 if (fi->saved_regs == NULL)
1478 FRAME_INIT_SAVED_REGS (fi);
1479 if (fi->saved_regs[regno])
1480 return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE);
1483 return read_signed_register (regno);
1486 /* mips_addr_bits_remove - remove useless address bits */
1489 mips_addr_bits_remove (CORE_ADDR addr)
1491 if (GDB_TARGET_IS_MIPS64)
1493 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1495 /* This hack is a work-around for existing boards using
1496 PMON, the simulator, and any other 64-bit targets that
1497 doesn't have true 64-bit addressing. On these targets,
1498 the upper 32 bits of addresses are ignored by the
1499 hardware. Thus, the PC or SP are likely to have been
1500 sign extended to all 1s by instruction sequences that
1501 load 32-bit addresses. For example, a typical piece of
1502 code that loads an address is this:
1503 lui $r2, <upper 16 bits>
1504 ori $r2, <lower 16 bits>
1505 But the lui sign-extends the value such that the upper 32
1506 bits may be all 1s. The workaround is simply to mask off
1507 these bits. In the future, gcc may be changed to support
1508 true 64-bit addressing, and this masking will have to be
1510 addr &= (CORE_ADDR) 0xffffffff;
1513 else if (mips_mask_address_p ())
1515 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1516 masking off bits, instead, the actual target should be asking
1517 for the address to be converted to a valid pointer. */
1518 /* Even when GDB is configured for some 32-bit targets
1519 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1520 so CORE_ADDR is 64 bits. So we still have to mask off
1521 useless bits from addresses. */
1522 addr &= (CORE_ADDR) 0xffffffff;
1527 /* mips_software_single_step() is called just before we want to resume
1528 the inferior, if we want to single-step it but there is no hardware
1529 or kernel single-step support (MIPS on GNU/Linux for example). We find
1530 the target of the coming instruction and breakpoint it.
1532 single_step is also called just after the inferior stops. If we had
1533 set up a simulated single-step, we undo our damage. */
1536 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1538 static CORE_ADDR next_pc;
1539 typedef char binsn_quantum[BREAKPOINT_MAX];
1540 static binsn_quantum break_mem;
1543 if (insert_breakpoints_p)
1545 pc = read_register (PC_REGNUM);
1546 next_pc = mips_next_pc (pc);
1548 target_insert_breakpoint (next_pc, break_mem);
1551 target_remove_breakpoint (next_pc, break_mem);
1555 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1559 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
1560 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
1561 tmp = mips_skip_stub (pc);
1562 prev->pc = tmp ? tmp : pc;
1567 mips_frame_saved_pc (struct frame_info *frame)
1570 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
1571 /* We have to get the saved pc from the sigcontext
1572 if it is a signal handler frame. */
1573 int pcreg = frame->signal_handler_caller ? PC_REGNUM
1574 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1576 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1577 saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1579 saved_pc = read_next_frame_reg (frame, pcreg);
1581 return ADDR_BITS_REMOVE (saved_pc);
1584 static struct mips_extra_func_info temp_proc_desc;
1585 static CORE_ADDR temp_saved_regs[NUM_REGS];
1587 /* Set a register's saved stack address in temp_saved_regs. If an address
1588 has already been set for this register, do nothing; this way we will
1589 only recognize the first save of a given register in a function prologue.
1590 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1593 set_reg_offset (int regno, CORE_ADDR offset)
1595 if (temp_saved_regs[regno] == 0)
1596 temp_saved_regs[regno] = offset;
1600 /* Test whether the PC points to the return instruction at the
1601 end of a function. */
1604 mips_about_to_return (CORE_ADDR pc)
1606 if (pc_is_mips16 (pc))
1607 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1608 generates a "jr $ra"; other times it generates code to load
1609 the return address from the stack to an accessible register (such
1610 as $a3), then a "jr" using that register. This second case
1611 is almost impossible to distinguish from an indirect jump
1612 used for switch statements, so we don't even try. */
1613 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1615 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1619 /* This fencepost looks highly suspicious to me. Removing it also
1620 seems suspicious as it could affect remote debugging across serial
1624 heuristic_proc_start (CORE_ADDR pc)
1631 pc = ADDR_BITS_REMOVE (pc);
1633 fence = start_pc - heuristic_fence_post;
1637 if (heuristic_fence_post == UINT_MAX
1638 || fence < VM_MIN_ADDRESS)
1639 fence = VM_MIN_ADDRESS;
1641 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1643 /* search back for previous return */
1644 for (start_pc -= instlen;; start_pc -= instlen)
1645 if (start_pc < fence)
1647 /* It's not clear to me why we reach this point when
1648 stop_soon_quietly, but with this test, at least we
1649 don't print out warnings for every child forked (eg, on
1650 decstation). 22apr93 rich@cygnus.com. */
1651 if (!stop_soon_quietly)
1653 static int blurb_printed = 0;
1655 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1660 /* This actually happens frequently in embedded
1661 development, when you first connect to a board
1662 and your stack pointer and pc are nowhere in
1663 particular. This message needs to give people
1664 in that situation enough information to
1665 determine that it's no big deal. */
1666 printf_filtered ("\n\
1667 GDB is unable to find the start of the function at 0x%s\n\
1668 and thus can't determine the size of that function's stack frame.\n\
1669 This means that GDB may be unable to access that stack frame, or\n\
1670 the frames below it.\n\
1671 This problem is most likely caused by an invalid program counter or\n\
1673 However, if you think GDB should simply search farther back\n\
1674 from 0x%s for code which looks like the beginning of a\n\
1675 function, you can increase the range of the search using the `set\n\
1676 heuristic-fence-post' command.\n",
1677 paddr_nz (pc), paddr_nz (pc));
1684 else if (pc_is_mips16 (start_pc))
1686 unsigned short inst;
1688 /* On MIPS16, any one of the following is likely to be the
1689 start of a function:
1693 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1694 inst = mips_fetch_instruction (start_pc);
1695 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1696 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1697 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1698 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1700 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1701 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1706 else if (mips_about_to_return (start_pc))
1708 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1715 /* Fetch the immediate value from a MIPS16 instruction.
1716 If the previous instruction was an EXTEND, use it to extend
1717 the upper bits of the immediate value. This is a helper function
1718 for mips16_heuristic_proc_desc. */
1721 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1722 unsigned short inst, /* current instruction */
1723 int nbits, /* number of bits in imm field */
1724 int scale, /* scale factor to be applied to imm */
1725 int is_signed) /* is the imm field signed? */
1729 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1731 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1732 if (offset & 0x8000) /* check for negative extend */
1733 offset = 0 - (0x10000 - (offset & 0xffff));
1734 return offset | (inst & 0x1f);
1738 int max_imm = 1 << nbits;
1739 int mask = max_imm - 1;
1740 int sign_bit = max_imm >> 1;
1742 offset = inst & mask;
1743 if (is_signed && (offset & sign_bit))
1744 offset = 0 - (max_imm - offset);
1745 return offset * scale;
1750 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1751 stream from start_pc to limit_pc. */
1754 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1755 struct frame_info *next_frame, CORE_ADDR sp)
1758 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1759 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1760 unsigned inst = 0; /* current instruction */
1761 unsigned entry_inst = 0; /* the entry instruction */
1764 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1765 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1767 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1769 /* Save the previous instruction. If it's an EXTEND, we'll extract
1770 the immediate offset extension from it in mips16_get_imm. */
1773 /* Fetch and decode the instruction. */
1774 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1775 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1776 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1778 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1779 if (offset < 0) /* negative stack adjustment? */
1780 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
1782 /* Exit loop if a positive stack adjustment is found, which
1783 usually means that the stack cleanup code in the function
1784 epilogue is reached. */
1787 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1789 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1790 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1791 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1792 set_reg_offset (reg, sp + offset);
1794 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1796 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1797 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1798 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1799 set_reg_offset (reg, sp + offset);
1801 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1803 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1804 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1805 set_reg_offset (RA_REGNUM, sp + offset);
1807 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1809 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1810 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1811 set_reg_offset (RA_REGNUM, sp + offset);
1813 else if (inst == 0x673d) /* move $s1, $sp */
1816 PROC_FRAME_REG (&temp_proc_desc) = 17;
1818 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1820 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1821 frame_addr = sp + offset;
1822 PROC_FRAME_REG (&temp_proc_desc) = 17;
1823 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1825 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1827 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1828 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1829 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1830 set_reg_offset (reg, frame_addr + offset);
1832 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1834 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1835 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1836 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1837 set_reg_offset (reg, frame_addr + offset);
1839 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1840 entry_inst = inst; /* save for later processing */
1841 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1842 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
1845 /* The entry instruction is typically the first instruction in a function,
1846 and it stores registers at offsets relative to the value of the old SP
1847 (before the prologue). But the value of the sp parameter to this
1848 function is the new SP (after the prologue has been executed). So we
1849 can't calculate those offsets until we've seen the entire prologue,
1850 and can calculate what the old SP must have been. */
1851 if (entry_inst != 0)
1853 int areg_count = (entry_inst >> 8) & 7;
1854 int sreg_count = (entry_inst >> 6) & 3;
1856 /* The entry instruction always subtracts 32 from the SP. */
1857 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
1859 /* Now we can calculate what the SP must have been at the
1860 start of the function prologue. */
1861 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
1863 /* Check if a0-a3 were saved in the caller's argument save area. */
1864 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1866 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1867 set_reg_offset (reg, sp + offset);
1868 offset += MIPS_SAVED_REGSIZE;
1871 /* Check if the ra register was pushed on the stack. */
1873 if (entry_inst & 0x20)
1875 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
1876 set_reg_offset (RA_REGNUM, sp + offset);
1877 offset -= MIPS_SAVED_REGSIZE;
1880 /* Check if the s0 and s1 registers were pushed on the stack. */
1881 for (reg = 16; reg < sreg_count + 16; reg++)
1883 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1884 set_reg_offset (reg, sp + offset);
1885 offset -= MIPS_SAVED_REGSIZE;
1891 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1892 struct frame_info *next_frame, CORE_ADDR sp)
1895 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1897 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
1898 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
1899 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1900 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
1902 unsigned long inst, high_word, low_word;
1905 /* Fetch the instruction. */
1906 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1908 /* Save some code by pre-extracting some useful fields. */
1909 high_word = (inst >> 16) & 0xffff;
1910 low_word = inst & 0xffff;
1911 reg = high_word & 0x1f;
1913 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1914 || high_word == 0x23bd /* addi $sp,$sp,-i */
1915 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1917 if (low_word & 0x8000) /* negative stack adjustment? */
1918 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
1920 /* Exit loop if a positive stack adjustment is found, which
1921 usually means that the stack cleanup code in the function
1922 epilogue is reached. */
1925 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1927 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1928 set_reg_offset (reg, sp + low_word);
1930 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1932 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1933 but the register size used is only 32 bits. Make the address
1934 for the saved register point to the lower 32 bits. */
1935 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1936 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
1938 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1940 /* Old gcc frame, r30 is virtual frame pointer. */
1941 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
1942 frame_addr = sp + low_word;
1943 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1945 unsigned alloca_adjust;
1946 PROC_FRAME_REG (&temp_proc_desc) = 30;
1947 frame_addr = read_next_frame_reg (next_frame, 30);
1948 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1949 if (alloca_adjust > 0)
1951 /* FP > SP + frame_size. This may be because
1952 * of an alloca or somethings similar.
1953 * Fix sp to "pre-alloca" value, and try again.
1955 sp += alloca_adjust;
1960 /* move $30,$sp. With different versions of gas this will be either
1961 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1962 Accept any one of these. */
1963 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1965 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1966 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1968 unsigned alloca_adjust;
1969 PROC_FRAME_REG (&temp_proc_desc) = 30;
1970 frame_addr = read_next_frame_reg (next_frame, 30);
1971 alloca_adjust = (unsigned) (frame_addr - sp);
1972 if (alloca_adjust > 0)
1974 /* FP > SP + frame_size. This may be because
1975 * of an alloca or somethings similar.
1976 * Fix sp to "pre-alloca" value, and try again.
1978 sp += alloca_adjust;
1983 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1985 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1986 set_reg_offset (reg, frame_addr + low_word);
1991 static mips_extra_func_info_t
1992 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1993 struct frame_info *next_frame, int cur_frame)
1998 sp = read_next_frame_reg (next_frame, SP_REGNUM);
2004 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2005 memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2006 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2007 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2008 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2010 if (start_pc + 200 < limit_pc)
2011 limit_pc = start_pc + 200;
2012 if (pc_is_mips16 (start_pc))
2013 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2015 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2016 return &temp_proc_desc;
2019 struct mips_objfile_private
2025 /* Global used to communicate between non_heuristic_proc_desc and
2026 compare_pdr_entries within qsort (). */
2027 static bfd *the_bfd;
2030 compare_pdr_entries (const void *a, const void *b)
2032 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2033 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2037 else if (lhs == rhs)
2043 static mips_extra_func_info_t
2044 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2046 CORE_ADDR startaddr;
2047 mips_extra_func_info_t proc_desc;
2048 struct block *b = block_for_pc (pc);
2050 struct obj_section *sec;
2051 struct mips_objfile_private *priv;
2053 if (PC_IN_CALL_DUMMY (pc, 0, 0))
2056 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2058 *addrptr = startaddr;
2062 sec = find_pc_section (pc);
2065 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2067 /* Search the ".pdr" section generated by GAS. This includes most of
2068 the information normally found in ECOFF PDRs. */
2070 the_bfd = sec->objfile->obfd;
2072 && (the_bfd->format == bfd_object
2073 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2074 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2076 /* Right now GAS only outputs the address as a four-byte sequence.
2077 This means that we should not bother with this method on 64-bit
2078 targets (until that is fixed). */
2080 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2081 sizeof (struct mips_objfile_private));
2083 sec->objfile->obj_private = priv;
2085 else if (priv == NULL)
2089 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2090 sizeof (struct mips_objfile_private));
2092 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2095 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2096 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2098 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2099 priv->contents, 0, priv->size);
2101 /* In general, the .pdr section is sorted. However, in the
2102 presence of multiple code sections (and other corner cases)
2103 it can become unsorted. Sort it so that we can use a faster
2105 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2110 sec->objfile->obj_private = priv;
2114 if (priv->size != 0)
2120 high = priv->size / 32;
2126 mid = (low + high) / 2;
2128 ptr = priv->contents + mid * 32;
2129 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2130 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2131 SECT_OFF_TEXT (sec->objfile));
2132 if (pdr_pc == startaddr)
2134 if (pdr_pc > startaddr)
2139 while (low != high);
2143 struct symbol *sym = find_pc_function (pc);
2145 /* Fill in what we need of the proc_desc. */
2146 proc_desc = (mips_extra_func_info_t)
2147 obstack_alloc (&sec->objfile->psymbol_obstack,
2148 sizeof (struct mips_extra_func_info));
2149 PROC_LOW_ADDR (proc_desc) = startaddr;
2151 /* Only used for dummy frames. */
2152 PROC_HIGH_ADDR (proc_desc) = 0;
2154 PROC_FRAME_OFFSET (proc_desc)
2155 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2156 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2158 PROC_FRAME_ADJUST (proc_desc) = 0;
2159 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2161 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2163 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2165 PROC_FREG_OFFSET (proc_desc)
2166 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2167 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2169 proc_desc->pdr.isym = (long) sym;
2179 if (startaddr > BLOCK_START (b))
2181 /* This is the "pathological" case referred to in a comment in
2182 print_frame_info. It might be better to move this check into
2187 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
2189 /* If we never found a PDR for this function in symbol reading, then
2190 examine prologues to find the information. */
2193 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2194 if (PROC_FRAME_REG (proc_desc) == -1)
2204 static mips_extra_func_info_t
2205 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2207 mips_extra_func_info_t proc_desc;
2208 CORE_ADDR startaddr;
2210 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2214 /* IF this is the topmost frame AND
2215 * (this proc does not have debugging information OR
2216 * the PC is in the procedure prologue)
2217 * THEN create a "heuristic" proc_desc (by analyzing
2218 * the actual code) to replace the "official" proc_desc.
2220 if (next_frame == NULL)
2222 struct symtab_and_line val;
2223 struct symbol *proc_symbol =
2224 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2228 val = find_pc_line (BLOCK_START
2229 (SYMBOL_BLOCK_VALUE (proc_symbol)),
2231 val.pc = val.end ? val.end : pc;
2233 if (!proc_symbol || pc < val.pc)
2235 mips_extra_func_info_t found_heuristic =
2236 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2237 pc, next_frame, cur_frame);
2238 if (found_heuristic)
2239 proc_desc = found_heuristic;
2245 /* Is linked_proc_desc_table really necessary? It only seems to be used
2246 by procedure call dummys. However, the procedures being called ought
2247 to have their own proc_descs, and even if they don't,
2248 heuristic_proc_desc knows how to create them! */
2250 register struct linked_proc_info *link;
2252 for (link = linked_proc_desc_table; link; link = link->next)
2253 if (PROC_LOW_ADDR (&link->info) <= pc
2254 && PROC_HIGH_ADDR (&link->info) > pc)
2258 startaddr = heuristic_proc_start (pc);
2261 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2267 get_frame_pointer (struct frame_info *frame,
2268 mips_extra_func_info_t proc_desc)
2270 return ADDR_BITS_REMOVE (read_next_frame_reg (frame,
2271 PROC_FRAME_REG (proc_desc)) +
2272 PROC_FRAME_OFFSET (proc_desc) -
2273 PROC_FRAME_ADJUST (proc_desc));
2276 mips_extra_func_info_t cached_proc_desc;
2279 mips_frame_chain (struct frame_info *frame)
2281 mips_extra_func_info_t proc_desc;
2283 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
2285 if (saved_pc == 0 || inside_entry_file (saved_pc))
2288 /* Check if the PC is inside a call stub. If it is, fetch the
2289 PC of the caller of that stub. */
2290 if ((tmp = mips_skip_stub (saved_pc)) != 0)
2293 /* Look up the procedure descriptor for this PC. */
2294 proc_desc = find_proc_desc (saved_pc, frame, 1);
2298 cached_proc_desc = proc_desc;
2300 /* If no frame pointer and frame size is zero, we must be at end
2301 of stack (or otherwise hosed). If we don't check frame size,
2302 we loop forever if we see a zero size frame. */
2303 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2304 && PROC_FRAME_OFFSET (proc_desc) == 0
2305 /* The previous frame from a sigtramp frame might be frameless
2306 and have frame size zero. */
2307 && !frame->signal_handler_caller)
2310 return get_frame_pointer (frame, proc_desc);
2314 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2318 /* Use proc_desc calculated in frame_chain */
2319 mips_extra_func_info_t proc_desc =
2320 fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1);
2322 fci->extra_info = (struct frame_extra_info *)
2323 frame_obstack_alloc (sizeof (struct frame_extra_info));
2325 fci->saved_regs = NULL;
2326 fci->extra_info->proc_desc =
2327 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2330 /* Fixup frame-pointer - only needed for top frame */
2331 /* This may not be quite right, if proc has a real frame register.
2332 Get the value of the frame relative sp, procedure might have been
2333 interrupted by a signal at it's very start. */
2334 if (fci->pc == PROC_LOW_ADDR (proc_desc)
2335 && !PROC_DESC_IS_DUMMY (proc_desc))
2336 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
2338 fci->frame = get_frame_pointer (fci->next, proc_desc);
2340 if (proc_desc == &temp_proc_desc)
2344 /* Do not set the saved registers for a sigtramp frame,
2345 mips_find_saved_registers will do that for us.
2346 We can't use fci->signal_handler_caller, it is not yet set. */
2347 find_pc_partial_function (fci->pc, &name,
2348 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2349 if (!PC_IN_SIGTRAMP (fci->pc, name))
2351 frame_saved_regs_zalloc (fci);
2352 memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2353 fci->saved_regs[PC_REGNUM]
2354 = fci->saved_regs[RA_REGNUM];
2355 /* Set value of previous frame's stack pointer. Remember that
2356 saved_regs[SP_REGNUM] is special in that it contains the
2357 value of the stack pointer register. The other saved_regs
2358 values are addresses (in the inferior) at which a given
2359 register's value may be found. */
2360 fci->saved_regs[SP_REGNUM] = fci->frame;
2364 /* hack: if argument regs are saved, guess these contain args */
2365 /* assume we can't tell how many args for now */
2366 fci->extra_info->num_args = -1;
2367 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2369 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2371 fci->extra_info->num_args = regnum - A0_REGNUM + 1;
2378 /* MIPS stack frames are almost impenetrable. When execution stops,
2379 we basically have to look at symbol information for the function
2380 that we stopped in, which tells us *which* register (if any) is
2381 the base of the frame pointer, and what offset from that register
2382 the frame itself is at.
2384 This presents a problem when trying to examine a stack in memory
2385 (that isn't executing at the moment), using the "frame" command. We
2386 don't have a PC, nor do we have any registers except SP.
2388 This routine takes two arguments, SP and PC, and tries to make the
2389 cached frames look as if these two arguments defined a frame on the
2390 cache. This allows the rest of info frame to extract the important
2391 arguments without difficulty. */
2394 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2397 error ("MIPS frame specifications require two arguments: sp and pc");
2399 return create_new_frame (argv[0], argv[1]);
2402 /* According to the current ABI, should the type be passed in a
2403 floating-point register (assuming that there is space)? When there
2404 is no FPU, FP are not even considered as possibile candidates for
2405 FP registers and, consequently this returns false - forces FP
2406 arguments into integer registers. */
2409 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2411 return ((typecode == TYPE_CODE_FLT
2413 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2414 && TYPE_NFIELDS (arg_type) == 1
2415 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2416 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2419 /* On o32, argument passing in GPRs depends on the alignment of the type being
2420 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2423 mips_type_needs_double_align (struct type *type)
2425 enum type_code typecode = TYPE_CODE (type);
2427 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2429 else if (typecode == TYPE_CODE_STRUCT)
2431 if (TYPE_NFIELDS (type) < 1)
2433 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2435 else if (typecode == TYPE_CODE_UNION)
2439 n = TYPE_NFIELDS (type);
2440 for (i = 0; i < n; i++)
2441 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2448 /* Macros to round N up or down to the next A boundary;
2449 A must be a power of two. */
2451 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2452 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2455 mips_eabi_push_arguments (int nargs,
2456 struct value **args,
2459 CORE_ADDR struct_addr)
2465 int stack_offset = 0;
2467 /* First ensure that the stack and structure return address (if any)
2468 are properly aligned. The stack has to be at least 64-bit
2469 aligned even on 32-bit machines, because doubles must be 64-bit
2470 aligned. For n32 and n64, stack frames need to be 128-bit
2471 aligned, so we round to this widest known alignment. */
2473 sp = ROUND_DOWN (sp, 16);
2474 struct_addr = ROUND_DOWN (struct_addr, 16);
2476 /* Now make space on the stack for the args. We allocate more
2477 than necessary for EABI, because the first few arguments are
2478 passed in registers, but that's OK. */
2479 for (argnum = 0; argnum < nargs; argnum++)
2480 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2481 MIPS_STACK_ARGSIZE);
2482 sp -= ROUND_UP (len, 16);
2485 fprintf_unfiltered (gdb_stdlog,
2486 "mips_eabi_push_arguments: sp=0x%s allocated %d\n",
2487 paddr_nz (sp), ROUND_UP (len, 16));
2489 /* Initialize the integer and float register pointers. */
2491 float_argreg = FPA0_REGNUM;
2493 /* The struct_return pointer occupies the first parameter-passing reg. */
2497 fprintf_unfiltered (gdb_stdlog,
2498 "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n",
2499 argreg, paddr_nz (struct_addr));
2500 write_register (argreg++, struct_addr);
2503 /* Now load as many as possible of the first arguments into
2504 registers, and push the rest onto the stack. Loop thru args
2505 from first to last. */
2506 for (argnum = 0; argnum < nargs; argnum++)
2509 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2510 struct value *arg = args[argnum];
2511 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2512 int len = TYPE_LENGTH (arg_type);
2513 enum type_code typecode = TYPE_CODE (arg_type);
2516 fprintf_unfiltered (gdb_stdlog,
2517 "mips_eabi_push_arguments: %d len=%d type=%d",
2518 argnum + 1, len, (int) typecode);
2520 /* The EABI passes structures that do not fit in a register by
2522 if (len > MIPS_SAVED_REGSIZE
2523 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2525 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2526 typecode = TYPE_CODE_PTR;
2527 len = MIPS_SAVED_REGSIZE;
2530 fprintf_unfiltered (gdb_stdlog, " push");
2533 val = (char *) VALUE_CONTENTS (arg);
2535 /* 32-bit ABIs always start floating point arguments in an
2536 even-numbered floating point register. Round the FP register
2537 up before the check to see if there are any FP registers
2538 left. Non MIPS_EABI targets also pass the FP in the integer
2539 registers so also round up normal registers. */
2540 if (!FP_REGISTER_DOUBLE
2541 && fp_register_arg_p (typecode, arg_type))
2543 if ((float_argreg & 1))
2547 /* Floating point arguments passed in registers have to be
2548 treated specially. On 32-bit architectures, doubles
2549 are passed in register pairs; the even register gets
2550 the low word, and the odd register gets the high word.
2551 On non-EABI processors, the first two floating point arguments are
2552 also copied to general registers, because MIPS16 functions
2553 don't use float registers for arguments. This duplication of
2554 arguments in general registers can't hurt non-MIPS16 functions
2555 because those registers are normally skipped. */
2556 /* MIPS_EABI squeezes a struct that contains a single floating
2557 point value into an FP register instead of pushing it onto the
2559 if (fp_register_arg_p (typecode, arg_type)
2560 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2562 if (!FP_REGISTER_DOUBLE && len == 8)
2564 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2565 unsigned long regval;
2567 /* Write the low word of the double to the even register(s). */
2568 regval = extract_unsigned_integer (val + low_offset, 4);
2570 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2571 float_argreg, phex (regval, 4));
2572 write_register (float_argreg++, regval);
2574 /* Write the high word of the double to the odd register(s). */
2575 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2577 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2578 float_argreg, phex (regval, 4));
2579 write_register (float_argreg++, regval);
2583 /* This is a floating point value that fits entirely
2584 in a single register. */
2585 /* On 32 bit ABI's the float_argreg is further adjusted
2586 above to ensure that it is even register aligned. */
2587 LONGEST regval = extract_unsigned_integer (val, len);
2589 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2590 float_argreg, phex (regval, len));
2591 write_register (float_argreg++, regval);
2596 /* Copy the argument to general registers or the stack in
2597 register-sized pieces. Large arguments are split between
2598 registers and stack. */
2599 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2600 are treated specially: Irix cc passes them in registers
2601 where gcc sometimes puts them on the stack. For maximum
2602 compatibility, we will put them in both places. */
2603 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2604 (len % MIPS_SAVED_REGSIZE != 0));
2606 /* Note: Floating-point values that didn't fit into an FP
2607 register are only written to memory. */
2610 /* Remember if the argument was written to the stack. */
2611 int stack_used_p = 0;
2613 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2616 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2619 /* Write this portion of the argument to the stack. */
2620 if (argreg > MIPS_LAST_ARG_REGNUM
2622 || fp_register_arg_p (typecode, arg_type))
2624 /* Should shorter than int integer values be
2625 promoted to int before being stored? */
2626 int longword_offset = 0;
2629 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2631 if (MIPS_STACK_ARGSIZE == 8 &&
2632 (typecode == TYPE_CODE_INT ||
2633 typecode == TYPE_CODE_PTR ||
2634 typecode == TYPE_CODE_FLT) && len <= 4)
2635 longword_offset = MIPS_STACK_ARGSIZE - len;
2636 else if ((typecode == TYPE_CODE_STRUCT ||
2637 typecode == TYPE_CODE_UNION) &&
2638 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2639 longword_offset = MIPS_STACK_ARGSIZE - len;
2644 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2645 paddr_nz (stack_offset));
2646 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2647 paddr_nz (longword_offset));
2650 addr = sp + stack_offset + longword_offset;
2655 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2657 for (i = 0; i < partial_len; i++)
2659 fprintf_unfiltered (gdb_stdlog, "%02x",
2663 write_memory (addr, val, partial_len);
2666 /* Note!!! This is NOT an else clause. Odd sized
2667 structs may go thru BOTH paths. Floating point
2668 arguments will not. */
2669 /* Write this portion of the argument to a general
2670 purpose register. */
2671 if (argreg <= MIPS_LAST_ARG_REGNUM
2672 && !fp_register_arg_p (typecode, arg_type))
2674 LONGEST regval = extract_unsigned_integer (val, partial_len);
2677 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2679 phex (regval, MIPS_SAVED_REGSIZE));
2680 write_register (argreg, regval);
2687 /* Compute the the offset into the stack at which we
2688 will copy the next parameter.
2690 In the new EABI (and the NABI32), the stack_offset
2691 only needs to be adjusted when it has been used. */
2694 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2698 fprintf_unfiltered (gdb_stdlog, "\n");
2701 /* Return adjusted stack pointer. */
2705 /* N32/N64 version of push_arguments. */
2708 mips_n32n64_push_arguments (int nargs,
2709 struct value **args,
2712 CORE_ADDR struct_addr)
2718 int stack_offset = 0;
2720 /* First ensure that the stack and structure return address (if any)
2721 are properly aligned. The stack has to be at least 64-bit
2722 aligned even on 32-bit machines, because doubles must be 64-bit
2723 aligned. For n32 and n64, stack frames need to be 128-bit
2724 aligned, so we round to this widest known alignment. */
2726 sp = ROUND_DOWN (sp, 16);
2727 struct_addr = ROUND_DOWN (struct_addr, 16);
2729 /* Now make space on the stack for the args. */
2730 for (argnum = 0; argnum < nargs; argnum++)
2731 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2732 MIPS_STACK_ARGSIZE);
2733 sp -= ROUND_UP (len, 16);
2736 fprintf_unfiltered (gdb_stdlog,
2737 "mips_n32n64_push_arguments: sp=0x%s allocated %d\n",
2738 paddr_nz (sp), ROUND_UP (len, 16));
2740 /* Initialize the integer and float register pointers. */
2742 float_argreg = FPA0_REGNUM;
2744 /* The struct_return pointer occupies the first parameter-passing reg. */
2748 fprintf_unfiltered (gdb_stdlog,
2749 "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n",
2750 argreg, paddr_nz (struct_addr));
2751 write_register (argreg++, struct_addr);
2754 /* Now load as many as possible of the first arguments into
2755 registers, and push the rest onto the stack. Loop thru args
2756 from first to last. */
2757 for (argnum = 0; argnum < nargs; argnum++)
2760 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2761 struct value *arg = args[argnum];
2762 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2763 int len = TYPE_LENGTH (arg_type);
2764 enum type_code typecode = TYPE_CODE (arg_type);
2767 fprintf_unfiltered (gdb_stdlog,
2768 "mips_n32n64_push_arguments: %d len=%d type=%d",
2769 argnum + 1, len, (int) typecode);
2771 val = (char *) VALUE_CONTENTS (arg);
2773 if (fp_register_arg_p (typecode, arg_type)
2774 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2776 /* This is a floating point value that fits entirely
2777 in a single register. */
2778 /* On 32 bit ABI's the float_argreg is further adjusted
2779 above to ensure that it is even register aligned. */
2780 LONGEST regval = extract_unsigned_integer (val, len);
2782 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2783 float_argreg, phex (regval, len));
2784 write_register (float_argreg++, regval);
2787 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2788 argreg, phex (regval, len));
2789 write_register (argreg, regval);
2794 /* Copy the argument to general registers or the stack in
2795 register-sized pieces. Large arguments are split between
2796 registers and stack. */
2797 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2798 are treated specially: Irix cc passes them in registers
2799 where gcc sometimes puts them on the stack. For maximum
2800 compatibility, we will put them in both places. */
2801 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2802 (len % MIPS_SAVED_REGSIZE != 0));
2803 /* Note: Floating-point values that didn't fit into an FP
2804 register are only written to memory. */
2807 /* Rememer if the argument was written to the stack. */
2808 int stack_used_p = 0;
2809 int partial_len = len < MIPS_SAVED_REGSIZE ?
2810 len : MIPS_SAVED_REGSIZE;
2813 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2816 /* Write this portion of the argument to the stack. */
2817 if (argreg > MIPS_LAST_ARG_REGNUM
2819 || fp_register_arg_p (typecode, arg_type))
2821 /* Should shorter than int integer values be
2822 promoted to int before being stored? */
2823 int longword_offset = 0;
2826 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2828 if (MIPS_STACK_ARGSIZE == 8 &&
2829 (typecode == TYPE_CODE_INT ||
2830 typecode == TYPE_CODE_PTR ||
2831 typecode == TYPE_CODE_FLT) && len <= 4)
2832 longword_offset = MIPS_STACK_ARGSIZE - len;
2833 else if ((typecode == TYPE_CODE_STRUCT ||
2834 typecode == TYPE_CODE_UNION) &&
2835 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2836 longword_offset = MIPS_STACK_ARGSIZE - len;
2841 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2842 paddr_nz (stack_offset));
2843 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2844 paddr_nz (longword_offset));
2847 addr = sp + stack_offset + longword_offset;
2852 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2854 for (i = 0; i < partial_len; i++)
2856 fprintf_unfiltered (gdb_stdlog, "%02x",
2860 write_memory (addr, val, partial_len);
2863 /* Note!!! This is NOT an else clause. Odd sized
2864 structs may go thru BOTH paths. Floating point
2865 arguments will not. */
2866 /* Write this portion of the argument to a general
2867 purpose register. */
2868 if (argreg <= MIPS_LAST_ARG_REGNUM
2869 && !fp_register_arg_p (typecode, arg_type))
2871 LONGEST regval = extract_unsigned_integer (val, partial_len);
2873 /* A non-floating-point argument being passed in a
2874 general register. If a struct or union, and if
2875 the remaining length is smaller than the register
2876 size, we have to adjust the register value on
2879 It does not seem to be necessary to do the
2880 same for integral types.
2882 cagney/2001-07-23: gdb/179: Also, GCC, when
2883 outputting LE O32 with sizeof (struct) <
2884 MIPS_SAVED_REGSIZE, generates a left shift as
2885 part of storing the argument in a register a
2886 register (the left shift isn't generated when
2887 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2888 is quite possible that this is GCC contradicting
2889 the LE/O32 ABI, GDB has not been adjusted to
2890 accommodate this. Either someone needs to
2891 demonstrate that the LE/O32 ABI specifies such a
2892 left shift OR this new ABI gets identified as
2893 such and GDB gets tweaked accordingly. */
2895 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2896 && partial_len < MIPS_SAVED_REGSIZE
2897 && (typecode == TYPE_CODE_STRUCT ||
2898 typecode == TYPE_CODE_UNION))
2899 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
2903 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2905 phex (regval, MIPS_SAVED_REGSIZE));
2906 write_register (argreg, regval);
2913 /* Compute the the offset into the stack at which we
2914 will copy the next parameter.
2916 In N32 (N64?), the stack_offset only needs to be
2917 adjusted when it has been used. */
2920 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2924 fprintf_unfiltered (gdb_stdlog, "\n");
2927 /* Return adjusted stack pointer. */
2931 /* O32/O64 version of push_arguments. */
2934 mips_o32o64_push_arguments (int nargs,
2935 struct value **args,
2938 CORE_ADDR struct_addr)
2944 int stack_offset = 0;
2946 /* First ensure that the stack and structure return address (if any)
2947 are properly aligned. The stack has to be at least 64-bit
2948 aligned even on 32-bit machines, because doubles must be 64-bit
2949 aligned. For n32 and n64, stack frames need to be 128-bit
2950 aligned, so we round to this widest known alignment. */
2952 sp = ROUND_DOWN (sp, 16);
2953 struct_addr = ROUND_DOWN (struct_addr, 16);
2955 /* Now make space on the stack for the args. */
2956 for (argnum = 0; argnum < nargs; argnum++)
2957 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2958 MIPS_STACK_ARGSIZE);
2959 sp -= ROUND_UP (len, 16);
2962 fprintf_unfiltered (gdb_stdlog,
2963 "mips_o32o64_push_arguments: sp=0x%s allocated %d\n",
2964 paddr_nz (sp), ROUND_UP (len, 16));
2966 /* Initialize the integer and float register pointers. */
2968 float_argreg = FPA0_REGNUM;
2970 /* The struct_return pointer occupies the first parameter-passing reg. */
2974 fprintf_unfiltered (gdb_stdlog,
2975 "mips_o32o64_push_arguments: struct_return reg=%d 0x%s\n",
2976 argreg, paddr_nz (struct_addr));
2977 write_register (argreg++, struct_addr);
2978 stack_offset += MIPS_STACK_ARGSIZE;
2981 /* Now load as many as possible of the first arguments into
2982 registers, and push the rest onto the stack. Loop thru args
2983 from first to last. */
2984 for (argnum = 0; argnum < nargs; argnum++)
2987 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2988 struct value *arg = args[argnum];
2989 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2990 int len = TYPE_LENGTH (arg_type);
2991 enum type_code typecode = TYPE_CODE (arg_type);
2994 fprintf_unfiltered (gdb_stdlog,
2995 "mips_o32o64_push_arguments: %d len=%d type=%d",
2996 argnum + 1, len, (int) typecode);
2998 val = (char *) VALUE_CONTENTS (arg);
3000 /* 32-bit ABIs always start floating point arguments in an
3001 even-numbered floating point register. Round the FP register
3002 up before the check to see if there are any FP registers
3003 left. O32/O64 targets also pass the FP in the integer
3004 registers so also round up normal registers. */
3005 if (!FP_REGISTER_DOUBLE
3006 && fp_register_arg_p (typecode, arg_type))
3008 if ((float_argreg & 1))
3012 /* Floating point arguments passed in registers have to be
3013 treated specially. On 32-bit architectures, doubles
3014 are passed in register pairs; the even register gets
3015 the low word, and the odd register gets the high word.
3016 On O32/O64, the first two floating point arguments are
3017 also copied to general registers, because MIPS16 functions
3018 don't use float registers for arguments. This duplication of
3019 arguments in general registers can't hurt non-MIPS16 functions
3020 because those registers are normally skipped. */
3022 if (fp_register_arg_p (typecode, arg_type)
3023 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3025 if (!FP_REGISTER_DOUBLE && len == 8)
3027 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3028 unsigned long regval;
3030 /* Write the low word of the double to the even register(s). */
3031 regval = extract_unsigned_integer (val + low_offset, 4);
3033 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3034 float_argreg, phex (regval, 4));
3035 write_register (float_argreg++, regval);
3037 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3038 argreg, phex (regval, 4));
3039 write_register (argreg++, regval);
3041 /* Write the high word of the double to the odd register(s). */
3042 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3044 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3045 float_argreg, phex (regval, 4));
3046 write_register (float_argreg++, regval);
3049 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3050 argreg, phex (regval, 4));
3051 write_register (argreg++, regval);
3055 /* This is a floating point value that fits entirely
3056 in a single register. */
3057 /* On 32 bit ABI's the float_argreg is further adjusted
3058 above to ensure that it is even register aligned. */
3059 LONGEST regval = extract_unsigned_integer (val, len);
3061 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3062 float_argreg, phex (regval, len));
3063 write_register (float_argreg++, regval);
3064 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3065 registers for each argument. The below is (my
3066 guess) to ensure that the corresponding integer
3067 register has reserved the same space. */
3069 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3070 argreg, phex (regval, len));
3071 write_register (argreg, regval);
3072 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3074 /* Reserve space for the FP register. */
3075 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3079 /* Copy the argument to general registers or the stack in
3080 register-sized pieces. Large arguments are split between
3081 registers and stack. */
3082 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3083 are treated specially: Irix cc passes them in registers
3084 where gcc sometimes puts them on the stack. For maximum
3085 compatibility, we will put them in both places. */
3086 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3087 (len % MIPS_SAVED_REGSIZE != 0));
3088 /* Structures should be aligned to eight bytes (even arg registers)
3089 on MIPS_ABI_O32, if their first member has double precision. */
3090 if (MIPS_SAVED_REGSIZE < 8
3091 && mips_type_needs_double_align (arg_type))
3096 /* Note: Floating-point values that didn't fit into an FP
3097 register are only written to memory. */
3100 /* Remember if the argument was written to the stack. */
3101 int stack_used_p = 0;
3103 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3106 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3109 /* Write this portion of the argument to the stack. */
3110 if (argreg > MIPS_LAST_ARG_REGNUM
3112 || fp_register_arg_p (typecode, arg_type))
3114 /* Should shorter than int integer values be
3115 promoted to int before being stored? */
3116 int longword_offset = 0;
3119 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3121 if (MIPS_STACK_ARGSIZE == 8 &&
3122 (typecode == TYPE_CODE_INT ||
3123 typecode == TYPE_CODE_PTR ||
3124 typecode == TYPE_CODE_FLT) && len <= 4)
3125 longword_offset = MIPS_STACK_ARGSIZE - len;
3130 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3131 paddr_nz (stack_offset));
3132 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3133 paddr_nz (longword_offset));
3136 addr = sp + stack_offset + longword_offset;
3141 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3143 for (i = 0; i < partial_len; i++)
3145 fprintf_unfiltered (gdb_stdlog, "%02x",
3149 write_memory (addr, val, partial_len);
3152 /* Note!!! This is NOT an else clause. Odd sized
3153 structs may go thru BOTH paths. Floating point
3154 arguments will not. */
3155 /* Write this portion of the argument to a general
3156 purpose register. */
3157 if (argreg <= MIPS_LAST_ARG_REGNUM
3158 && !fp_register_arg_p (typecode, arg_type))
3160 LONGEST regval = extract_signed_integer (val, partial_len);
3161 /* Value may need to be sign extended, because
3162 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3164 /* A non-floating-point argument being passed in a
3165 general register. If a struct or union, and if
3166 the remaining length is smaller than the register
3167 size, we have to adjust the register value on
3170 It does not seem to be necessary to do the
3171 same for integral types.
3173 Also don't do this adjustment on O64 binaries.
3175 cagney/2001-07-23: gdb/179: Also, GCC, when
3176 outputting LE O32 with sizeof (struct) <
3177 MIPS_SAVED_REGSIZE, generates a left shift as
3178 part of storing the argument in a register a
3179 register (the left shift isn't generated when
3180 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3181 is quite possible that this is GCC contradicting
3182 the LE/O32 ABI, GDB has not been adjusted to
3183 accommodate this. Either someone needs to
3184 demonstrate that the LE/O32 ABI specifies such a
3185 left shift OR this new ABI gets identified as
3186 such and GDB gets tweaked accordingly. */
3188 if (MIPS_SAVED_REGSIZE < 8
3189 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3190 && partial_len < MIPS_SAVED_REGSIZE
3191 && (typecode == TYPE_CODE_STRUCT ||
3192 typecode == TYPE_CODE_UNION))
3193 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3197 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3199 phex (regval, MIPS_SAVED_REGSIZE));
3200 write_register (argreg, regval);
3203 /* Prevent subsequent floating point arguments from
3204 being passed in floating point registers. */
3205 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3211 /* Compute the the offset into the stack at which we
3212 will copy the next parameter.
3214 In older ABIs, the caller reserved space for
3215 registers that contained arguments. This was loosely
3216 refered to as their "home". Consequently, space is
3217 always allocated. */
3219 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3223 fprintf_unfiltered (gdb_stdlog, "\n");
3226 /* Return adjusted stack pointer. */
3231 mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
3233 /* Set the return address register to point to the entry
3234 point of the program, where a breakpoint lies in wait. */
3235 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
3240 mips_push_register (CORE_ADDR * sp, int regno)
3242 char *buffer = alloca (MAX_REGISTER_RAW_SIZE);
3245 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
3247 regsize = MIPS_SAVED_REGSIZE;
3248 offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3249 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
3254 regsize = REGISTER_RAW_SIZE (regno);
3258 read_register_gen (regno, buffer);
3259 write_memory (*sp, buffer + offset, regsize);
3262 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
3263 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
3266 mips_push_dummy_frame (void)
3269 struct linked_proc_info *link = (struct linked_proc_info *)
3270 xmalloc (sizeof (struct linked_proc_info));
3271 mips_extra_func_info_t proc_desc = &link->info;
3272 CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
3273 CORE_ADDR old_sp = sp;
3274 link->next = linked_proc_desc_table;
3275 linked_proc_desc_table = link;
3277 /* FIXME! are these correct ? */
3278 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
3279 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
3280 #define FLOAT_REG_SAVE_MASK MASK(0,19)
3281 #define FLOAT_SINGLE_REG_SAVE_MASK \
3282 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
3284 * The registers we must save are all those not preserved across
3285 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
3286 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
3287 * and FP Control/Status registers.
3290 * Dummy frame layout:
3293 * Saved MMHI, MMLO, FPC_CSR
3298 * Saved D18 (i.e. F19, F18)
3300 * Saved D0 (i.e. F1, F0)
3301 * Argument build area and stack arguments written via mips_push_arguments
3305 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
3306 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
3307 PROC_FRAME_OFFSET (proc_desc) = 0;
3308 PROC_FRAME_ADJUST (proc_desc) = 0;
3309 mips_push_register (&sp, PC_REGNUM);
3310 mips_push_register (&sp, HI_REGNUM);
3311 mips_push_register (&sp, LO_REGNUM);
3312 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
3314 /* Save general CPU registers */
3315 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
3316 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
3317 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
3318 for (ireg = 32; --ireg >= 0;)
3319 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
3320 mips_push_register (&sp, ireg);
3322 /* Save floating point registers starting with high order word */
3323 PROC_FREG_MASK (proc_desc) =
3324 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
3325 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
3326 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
3328 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
3329 for (ireg = 32; --ireg >= 0;)
3330 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
3331 mips_push_register (&sp, ireg + FP0_REGNUM);
3333 /* Update the frame pointer for the call dummy and the stack pointer.
3334 Set the procedure's starting and ending addresses to point to the
3335 call dummy address at the entry point. */
3336 write_register (PUSH_FP_REGNUM, old_sp);
3337 write_register (SP_REGNUM, sp);
3338 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
3339 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
3340 SET_PROC_DESC_IS_DUMMY (proc_desc);
3341 PROC_PC_REG (proc_desc) = RA_REGNUM;
3345 mips_pop_frame (void)
3347 register int regnum;
3348 struct frame_info *frame = get_current_frame ();
3349 CORE_ADDR new_sp = FRAME_FP (frame);
3351 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
3353 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
3354 if (frame->saved_regs == NULL)
3355 FRAME_INIT_SAVED_REGS (frame);
3356 for (regnum = 0; regnum < NUM_REGS; regnum++)
3358 if (regnum != SP_REGNUM && regnum != PC_REGNUM
3359 && frame->saved_regs[regnum])
3360 write_register (regnum,
3361 read_memory_integer (frame->saved_regs[regnum],
3362 MIPS_SAVED_REGSIZE));
3364 write_register (SP_REGNUM, new_sp);
3365 flush_cached_frames ();
3367 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
3369 struct linked_proc_info *pi_ptr, *prev_ptr;
3371 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
3373 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
3375 if (&pi_ptr->info == proc_desc)
3380 error ("Can't locate dummy extra frame info\n");
3382 if (prev_ptr != NULL)
3383 prev_ptr->next = pi_ptr->next;
3385 linked_proc_desc_table = pi_ptr->next;
3389 write_register (HI_REGNUM,
3390 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
3391 MIPS_SAVED_REGSIZE));
3392 write_register (LO_REGNUM,
3393 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
3394 MIPS_SAVED_REGSIZE));
3395 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
3396 write_register (FCRCS_REGNUM,
3397 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
3398 MIPS_SAVED_REGSIZE));
3402 /* Floating point register management.
3404 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3405 64bit operations, these early MIPS cpus treat fp register pairs
3406 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3407 registers and offer a compatibility mode that emulates the MIPS2 fp
3408 model. When operating in MIPS2 fp compat mode, later cpu's split
3409 double precision floats into two 32-bit chunks and store them in
3410 consecutive fp regs. To display 64-bit floats stored in this
3411 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3412 Throw in user-configurable endianness and you have a real mess.
3414 The way this works is:
3415 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3416 double-precision value will be split across two logical registers.
3417 The lower-numbered logical register will hold the low-order bits,
3418 regardless of the processor's endianness.
3419 - If we are on a 64-bit processor, and we are looking for a
3420 single-precision value, it will be in the low ordered bits
3421 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3422 save slot in memory.
3423 - If we are in 64-bit mode, everything is straightforward.
3425 Note that this code only deals with "live" registers at the top of the
3426 stack. We will attempt to deal with saved registers later, when
3427 the raw/cooked register interface is in place. (We need a general
3428 interface that can deal with dynamic saved register sizes -- fp
3429 regs could be 32 bits wide in one frame and 64 on the frame above
3432 static struct type *
3433 mips_float_register_type (void)
3435 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3436 return builtin_type_ieee_single_big;
3438 return builtin_type_ieee_single_little;
3441 static struct type *
3442 mips_double_register_type (void)
3444 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3445 return builtin_type_ieee_double_big;
3447 return builtin_type_ieee_double_little;
3450 /* Copy a 32-bit single-precision value from the current frame
3451 into rare_buffer. */
3454 mips_read_fp_register_single (int regno, char *rare_buffer)
3456 int raw_size = REGISTER_RAW_SIZE (regno);
3457 char *raw_buffer = alloca (raw_size);
3459 if (!frame_register_read (selected_frame, regno, raw_buffer))
3460 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3463 /* We have a 64-bit value for this register. Find the low-order
3467 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3472 memcpy (rare_buffer, raw_buffer + offset, 4);
3476 memcpy (rare_buffer, raw_buffer, 4);
3480 /* Copy a 64-bit double-precision value from the current frame into
3481 rare_buffer. This may include getting half of it from the next
3485 mips_read_fp_register_double (int regno, char *rare_buffer)
3487 int raw_size = REGISTER_RAW_SIZE (regno);
3489 if (raw_size == 8 && !mips2_fp_compat ())
3491 /* We have a 64-bit value for this register, and we should use
3493 if (!frame_register_read (selected_frame, regno, rare_buffer))
3494 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3498 if ((regno - FP0_REGNUM) & 1)
3499 internal_error (__FILE__, __LINE__,
3500 "mips_read_fp_register_double: bad access to "
3501 "odd-numbered FP register");
3503 /* mips_read_fp_register_single will find the correct 32 bits from
3505 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3507 mips_read_fp_register_single (regno, rare_buffer + 4);
3508 mips_read_fp_register_single (regno + 1, rare_buffer);
3512 mips_read_fp_register_single (regno, rare_buffer);
3513 mips_read_fp_register_single (regno + 1, rare_buffer + 4);
3519 mips_print_register (int regnum, int all)
3521 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
3523 /* Get the data in raw format. */
3524 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3526 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
3530 /* If we have a actual 32-bit floating point register (or we are in
3531 32-bit compatibility mode), and the register is even-numbered,
3532 also print it as a double (spanning two registers). */
3533 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
3534 && (REGISTER_RAW_SIZE (regnum) == 4
3535 || mips2_fp_compat ())
3536 && !((regnum - FP0_REGNUM) & 1))
3538 char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE);
3540 mips_read_fp_register_double (regnum, dbuffer);
3542 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
3543 val_print (mips_double_register_type (), dbuffer, 0, 0,
3544 gdb_stdout, 0, 1, 0, Val_pretty_default);
3545 printf_filtered ("); ");
3547 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3549 /* The problem with printing numeric register names (r26, etc.) is that
3550 the user can't use them on input. Probably the best solution is to
3551 fix it so that either the numeric or the funky (a2, etc.) names
3552 are accepted on input. */
3553 if (regnum < MIPS_NUMREGS)
3554 printf_filtered ("(r%d): ", regnum);
3556 printf_filtered (": ");
3558 /* If virtual format is floating, print it that way. */
3559 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3560 if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
3562 /* We have a meaningful 64-bit value in this register. Show
3563 it as a 32-bit float and a 64-bit double. */
3564 int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
3566 printf_filtered (" (float) ");
3567 val_print (mips_float_register_type (), raw_buffer + offset, 0, 0,
3568 gdb_stdout, 0, 1, 0, Val_pretty_default);
3569 printf_filtered (", (double) ");
3570 val_print (mips_double_register_type (), raw_buffer, 0, 0,
3571 gdb_stdout, 0, 1, 0, Val_pretty_default);
3574 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
3575 gdb_stdout, 0, 1, 0, Val_pretty_default);
3576 /* Else print as integer in hex. */
3581 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3582 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
3586 print_scalar_formatted (raw_buffer + offset,
3587 REGISTER_VIRTUAL_TYPE (regnum),
3588 'x', 0, gdb_stdout);
3592 /* Replacement for generic do_registers_info.
3593 Print regs in pretty columns. */
3596 do_fp_register_row (int regnum)
3597 { /* do values for FP (float) regs */
3599 double doub, flt1, flt2; /* doubles extracted from raw hex data */
3600 int inv1, inv2, inv3;
3602 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
3604 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
3606 /* 4-byte registers: we can fit two registers per row. */
3607 /* Also print every pair of 4-byte regs as an 8-byte double. */
3608 mips_read_fp_register_single (regnum, raw_buffer);
3609 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
3611 mips_read_fp_register_single (regnum + 1, raw_buffer);
3612 flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2);
3614 mips_read_fp_register_double (regnum, raw_buffer);
3615 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
3617 printf_filtered (" %-5s", REGISTER_NAME (regnum));
3619 printf_filtered (": <invalid float>");
3621 printf_filtered ("%-17.9g", flt1);
3623 printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
3625 printf_filtered (": <invalid float>");
3627 printf_filtered ("%-17.9g", flt2);
3629 printf_filtered (" dbl: ");
3631 printf_filtered ("<invalid double>");
3633 printf_filtered ("%-24.17g", doub);
3634 printf_filtered ("\n");
3636 /* may want to do hex display here (future enhancement) */
3641 /* Eight byte registers: print each one as float AND as double. */
3642 mips_read_fp_register_single (regnum, raw_buffer);
3643 flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1);
3645 mips_read_fp_register_double (regnum, raw_buffer);
3646 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
3648 printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
3650 printf_filtered ("<invalid float>");
3652 printf_filtered ("flt: %-17.9g", flt1);
3654 printf_filtered (" dbl: ");
3656 printf_filtered ("<invalid double>");
3658 printf_filtered ("%-24.17g", doub);
3660 printf_filtered ("\n");
3661 /* may want to do hex display here (future enhancement) */
3667 /* Print a row's worth of GP (int) registers, with name labels above */
3670 do_gp_register_row (int regnum)
3672 /* do values for GP (int) regs */
3673 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
3674 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
3676 int start_regnum = regnum;
3677 int numregs = NUM_REGS;
3680 /* For GP registers, we print a separate row of names above the vals */
3681 printf_filtered (" ");
3682 for (col = 0; col < ncols && regnum < numregs; regnum++)
3684 if (*REGISTER_NAME (regnum) == '\0')
3685 continue; /* unused register */
3686 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3687 break; /* end the row: reached FP register */
3688 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
3689 REGISTER_NAME (regnum));
3692 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
3693 start_regnum); /* print the R0 to R31 names */
3695 regnum = start_regnum; /* go back to start of row */
3696 /* now print the values in hex, 4 or 8 to the row */
3697 for (col = 0; col < ncols && regnum < numregs; regnum++)
3699 if (*REGISTER_NAME (regnum) == '\0')
3700 continue; /* unused register */
3701 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3702 break; /* end row: reached FP register */
3703 /* OK: get the data in raw format. */
3704 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3705 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3706 /* pad small registers */
3707 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
3708 printf_filtered (" ");
3709 /* Now print the register value in hex, endian order. */
3710 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3711 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
3712 byte < REGISTER_RAW_SIZE (regnum);
3714 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
3716 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
3719 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
3720 printf_filtered (" ");
3723 if (col > 0) /* ie. if we actually printed anything... */
3724 printf_filtered ("\n");
3729 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3732 mips_do_registers_info (int regnum, int fpregs)
3734 if (regnum != -1) /* do one specified register */
3736 if (*(REGISTER_NAME (regnum)) == '\0')
3737 error ("Not a valid register for the current processor type");
3739 mips_print_register (regnum, 0);
3740 printf_filtered ("\n");
3743 /* do all (or most) registers */
3746 while (regnum < NUM_REGS)
3748 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3749 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
3750 regnum = do_fp_register_row (regnum); /* FP regs */
3752 regnum += MIPS_NUMREGS; /* skip floating point regs */
3754 regnum = do_gp_register_row (regnum); /* GP (int) regs */
3759 /* Return number of args passed to a frame. described by FIP.
3760 Can return -1, meaning no way to tell. */
3763 mips_frame_num_args (struct frame_info *frame)
3768 /* Is this a branch with a delay slot? */
3770 static int is_delayed (unsigned long);
3773 is_delayed (unsigned long insn)
3776 for (i = 0; i < NUMOPCODES; ++i)
3777 if (mips_opcodes[i].pinfo != INSN_MACRO
3778 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
3780 return (i < NUMOPCODES
3781 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
3782 | INSN_COND_BRANCH_DELAY
3783 | INSN_COND_BRANCH_LIKELY)));
3787 mips_step_skips_delay (CORE_ADDR pc)
3789 char buf[MIPS_INSTLEN];
3791 /* There is no branch delay slot on MIPS16. */
3792 if (pc_is_mips16 (pc))
3795 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
3796 /* If error reading memory, guess that it is not a delayed branch. */
3798 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
3802 /* Skip the PC past function prologue instructions (32-bit version).
3803 This is a helper function for mips_skip_prologue. */
3806 mips32_skip_prologue (CORE_ADDR pc)
3810 int seen_sp_adjust = 0;
3811 int load_immediate_bytes = 0;
3813 /* Skip the typical prologue instructions. These are the stack adjustment
3814 instruction and the instructions that save registers on the stack
3815 or in the gcc frame. */
3816 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
3818 unsigned long high_word;
3820 inst = mips_fetch_instruction (pc);
3821 high_word = (inst >> 16) & 0xffff;
3823 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
3824 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
3826 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
3827 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
3829 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3830 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3831 && (inst & 0x001F0000)) /* reg != $zero */
3834 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3836 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
3838 continue; /* reg != $zero */
3840 /* move $s8,$sp. With different versions of gas this will be either
3841 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3842 Accept any one of these. */
3843 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3846 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3848 else if (high_word == 0x3c1c) /* lui $gp,n */
3850 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
3852 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3853 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
3855 /* The following instructions load $at or $t0 with an immediate
3856 value in preparation for a stack adjustment via
3857 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3858 a local variable, so we accept them only before a stack adjustment
3859 instruction was seen. */
3860 else if (!seen_sp_adjust)
3862 if (high_word == 0x3c01 || /* lui $at,n */
3863 high_word == 0x3c08) /* lui $t0,n */
3865 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
3868 else if (high_word == 0x3421 || /* ori $at,$at,n */
3869 high_word == 0x3508 || /* ori $t0,$t0,n */
3870 high_word == 0x3401 || /* ori $at,$zero,n */
3871 high_word == 0x3408) /* ori $t0,$zero,n */
3873 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
3883 /* In a frameless function, we might have incorrectly
3884 skipped some load immediate instructions. Undo the skipping
3885 if the load immediate was not followed by a stack adjustment. */
3886 if (load_immediate_bytes && !seen_sp_adjust)
3887 pc -= load_immediate_bytes;
3891 /* Skip the PC past function prologue instructions (16-bit version).
3892 This is a helper function for mips_skip_prologue. */
3895 mips16_skip_prologue (CORE_ADDR pc)
3898 int extend_bytes = 0;
3899 int prev_extend_bytes;
3901 /* Table of instructions likely to be found in a function prologue. */
3904 unsigned short inst;
3905 unsigned short mask;
3912 , /* addiu $sp,offset */
3916 , /* daddiu $sp,offset */
3920 , /* sw reg,n($sp) */
3924 , /* sd reg,n($sp) */
3928 , /* sw $ra,n($sp) */
3932 , /* sd $ra,n($sp) */
3940 , /* sw $a0-$a3,n($s1) */
3944 , /* move reg,$a0-$a3 */
3948 , /* entry pseudo-op */
3952 , /* addiu $s1,$sp,n */
3955 } /* end of table marker */
3958 /* Skip the typical prologue instructions. These are the stack adjustment
3959 instruction and the instructions that save registers on the stack
3960 or in the gcc frame. */
3961 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
3963 unsigned short inst;
3966 inst = mips_fetch_instruction (pc);
3968 /* Normally we ignore an extend instruction. However, if it is
3969 not followed by a valid prologue instruction, we must adjust
3970 the pc back over the extend so that it won't be considered
3971 part of the prologue. */
3972 if ((inst & 0xf800) == 0xf000) /* extend */
3974 extend_bytes = MIPS16_INSTLEN;
3977 prev_extend_bytes = extend_bytes;
3980 /* Check for other valid prologue instructions besides extend. */
3981 for (i = 0; table[i].mask != 0; i++)
3982 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
3984 if (table[i].mask != 0) /* it was in table? */
3985 continue; /* ignore it */
3989 /* Return the current pc, adjusted backwards by 2 if
3990 the previous instruction was an extend. */
3991 return pc - prev_extend_bytes;
3997 /* To skip prologues, I use this predicate. Returns either PC itself
3998 if the code at PC does not look like a function prologue; otherwise
3999 returns an address that (if we're lucky) follows the prologue. If
4000 LENIENT, then we must skip everything which is involved in setting
4001 up the frame (it's OK to skip more, just so long as we don't skip
4002 anything which might clobber the registers which are being saved.
4003 We must skip more in the case where part of the prologue is in the
4004 delay slot of a non-prologue instruction). */
4007 mips_skip_prologue (CORE_ADDR pc)
4009 /* See if we can determine the end of the prologue via the symbol table.
4010 If so, then return either PC, or the PC after the prologue, whichever
4013 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4015 if (post_prologue_pc != 0)
4016 return max (pc, post_prologue_pc);
4018 /* Can't determine prologue from the symbol table, need to examine
4021 if (pc_is_mips16 (pc))
4022 return mips16_skip_prologue (pc);
4024 return mips32_skip_prologue (pc);
4027 /* Determine how a return value is stored within the MIPS register
4028 file, given the return type `valtype'. */
4030 struct return_value_word
4039 return_value_location (struct type *valtype,
4040 struct return_value_word *hi,
4041 struct return_value_word *lo)
4043 int len = TYPE_LENGTH (valtype);
4045 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
4046 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
4047 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
4049 if (!FP_REGISTER_DOUBLE && len == 8)
4051 /* We need to break a 64bit float in two 32 bit halves and
4052 spread them across a floating-point register pair. */
4053 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
4054 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
4055 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4056 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
4058 hi->reg_offset = lo->reg_offset;
4059 lo->reg = FP0_REGNUM + 0;
4060 hi->reg = FP0_REGNUM + 1;
4066 /* The floating point value fits in a single floating-point
4068 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4069 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
4072 lo->reg = FP0_REGNUM;
4083 /* Locate a result possibly spread across two registers. */
4085 lo->reg = regnum + 0;
4086 hi->reg = regnum + 1;
4087 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4088 && len < MIPS_SAVED_REGSIZE)
4090 /* "un-left-justify" the value in the low register */
4091 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
4096 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4097 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
4098 && len < MIPS_SAVED_REGSIZE * 2
4099 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
4100 TYPE_CODE (valtype) == TYPE_CODE_UNION))
4102 /* "un-left-justify" the value spread across two registers. */
4103 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
4104 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
4106 hi->len = len - lo->len;
4110 /* Only perform a partial copy of the second register. */
4113 if (len > MIPS_SAVED_REGSIZE)
4115 lo->len = MIPS_SAVED_REGSIZE;
4116 hi->len = len - MIPS_SAVED_REGSIZE;
4124 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4125 && REGISTER_RAW_SIZE (regnum) == 8
4126 && MIPS_SAVED_REGSIZE == 4)
4128 /* Account for the fact that only the least-signficant part
4129 of the register is being used */
4130 lo->reg_offset += 4;
4131 hi->reg_offset += 4;
4134 hi->buf_offset = lo->len;
4138 /* Given a return value in `regbuf' with a type `valtype', extract and
4139 copy its value into `valbuf'. */
4142 mips_extract_return_value (struct type *valtype,
4143 char regbuf[REGISTER_BYTES],
4146 struct return_value_word lo;
4147 struct return_value_word hi;
4148 return_value_location (valtype, &hi, &lo);
4150 memcpy (valbuf + lo.buf_offset,
4151 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4155 memcpy (valbuf + hi.buf_offset,
4156 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4160 /* Given a return value in `valbuf' with a type `valtype', write it's
4161 value into the appropriate register. */
4164 mips_store_return_value (struct type *valtype, char *valbuf)
4166 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4167 struct return_value_word lo;
4168 struct return_value_word hi;
4169 return_value_location (valtype, &hi, &lo);
4171 memset (raw_buffer, 0, sizeof (raw_buffer));
4172 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4173 write_register_bytes (REGISTER_BYTE (lo.reg),
4175 REGISTER_RAW_SIZE (lo.reg));
4179 memset (raw_buffer, 0, sizeof (raw_buffer));
4180 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4181 write_register_bytes (REGISTER_BYTE (hi.reg),
4183 REGISTER_RAW_SIZE (hi.reg));
4187 /* Exported procedure: Is PC in the signal trampoline code */
4190 in_sigtramp (CORE_ADDR pc, char *ignore)
4192 if (sigtramp_address == 0)
4194 return (pc >= sigtramp_address && pc < sigtramp_end);
4197 /* Root of all "set mips "/"show mips " commands. This will eventually be
4198 used for all MIPS-specific commands. */
4201 show_mips_command (char *args, int from_tty)
4203 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4207 set_mips_command (char *args, int from_tty)
4209 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4210 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4213 /* Commands to show/set the MIPS FPU type. */
4216 show_mipsfpu_command (char *args, int from_tty)
4219 switch (MIPS_FPU_TYPE)
4221 case MIPS_FPU_SINGLE:
4222 fpu = "single-precision";
4224 case MIPS_FPU_DOUBLE:
4225 fpu = "double-precision";
4228 fpu = "absent (none)";
4231 internal_error (__FILE__, __LINE__, "bad switch");
4233 if (mips_fpu_type_auto)
4234 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4237 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
4243 set_mipsfpu_command (char *args, int from_tty)
4245 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4246 show_mipsfpu_command (args, from_tty);
4250 set_mipsfpu_single_command (char *args, int from_tty)
4252 mips_fpu_type = MIPS_FPU_SINGLE;
4253 mips_fpu_type_auto = 0;
4254 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
4258 set_mipsfpu_double_command (char *args, int from_tty)
4260 mips_fpu_type = MIPS_FPU_DOUBLE;
4261 mips_fpu_type_auto = 0;
4262 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
4266 set_mipsfpu_none_command (char *args, int from_tty)
4268 mips_fpu_type = MIPS_FPU_NONE;
4269 mips_fpu_type_auto = 0;
4270 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
4274 set_mipsfpu_auto_command (char *args, int from_tty)
4276 mips_fpu_type_auto = 1;
4279 /* Command to set the processor type. */
4282 mips_set_processor_type_command (char *args, int from_tty)
4286 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
4288 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
4289 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
4290 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
4292 /* Restore the value. */
4293 tmp_mips_processor_type = xstrdup (mips_processor_type);
4298 if (!mips_set_processor_type (tmp_mips_processor_type))
4300 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
4301 /* Restore its value. */
4302 tmp_mips_processor_type = xstrdup (mips_processor_type);
4307 mips_show_processor_type_command (char *args, int from_tty)
4311 /* Modify the actual processor type. */
4314 mips_set_processor_type (char *str)
4321 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
4323 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
4325 mips_processor_type = str;
4326 mips_processor_reg_names = mips_processor_type_table[i].regnames;
4328 /* FIXME tweak fpu flag too */
4335 /* Attempt to identify the particular processor model by reading the
4339 mips_read_processor_type (void)
4343 prid = read_register (PRID_REGNUM);
4345 if ((prid & ~0xf) == 0x700)
4346 return savestring ("r3041", strlen ("r3041"));
4351 /* Just like reinit_frame_cache, but with the right arguments to be
4352 callable as an sfunc. */
4355 reinit_frame_cache_sfunc (char *args, int from_tty,
4356 struct cmd_list_element *c)
4358 reinit_frame_cache ();
4362 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
4364 mips_extra_func_info_t proc_desc;
4366 /* Search for the function containing this address. Set the low bit
4367 of the address when searching, in case we were given an even address
4368 that is the start of a 16-bit function. If we didn't do this,
4369 the search would fail because the symbol table says the function
4370 starts at an odd address, i.e. 1 byte past the given address. */
4371 memaddr = ADDR_BITS_REMOVE (memaddr);
4372 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
4374 /* Make an attempt to determine if this is a 16-bit function. If
4375 the procedure descriptor exists and the address therein is odd,
4376 it's definitely a 16-bit function. Otherwise, we have to just
4377 guess that if the address passed in is odd, it's 16-bits. */
4379 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
4380 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
4382 info->mach = pc_is_mips16 (memaddr) ?
4383 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
4385 /* Round down the instruction address to the appropriate boundary. */
4386 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4388 /* Call the appropriate disassembler based on the target endian-ness. */
4389 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4390 return print_insn_big_mips (memaddr, info);
4392 return print_insn_little_mips (memaddr, info);
4395 /* Old-style breakpoint macros.
4396 The IDT board uses an unusual breakpoint value, and sometimes gets
4397 confused when it sees the usual MIPS breakpoint instruction. */
4399 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
4400 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
4401 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
4402 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
4403 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
4404 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
4405 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
4406 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
4408 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4409 counter value to determine whether a 16- or 32-bit breakpoint should be
4410 used. It returns a pointer to a string of bytes that encode a breakpoint
4411 instruction, stores the length of the string to *lenptr, and adjusts pc
4412 (if necessary) to point to the actual memory location where the
4413 breakpoint should be inserted. */
4415 const unsigned char *
4416 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
4418 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4420 if (pc_is_mips16 (*pcptr))
4422 static unsigned char mips16_big_breakpoint[] =
4423 MIPS16_BIG_BREAKPOINT;
4424 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
4425 *lenptr = sizeof (mips16_big_breakpoint);
4426 return mips16_big_breakpoint;
4430 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
4431 static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
4432 static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
4434 *lenptr = sizeof (big_breakpoint);
4436 if (strcmp (target_shortname, "mips") == 0)
4437 return idt_big_breakpoint;
4438 else if (strcmp (target_shortname, "ddb") == 0
4439 || strcmp (target_shortname, "pmon") == 0
4440 || strcmp (target_shortname, "lsi") == 0)
4441 return pmon_big_breakpoint;
4443 return big_breakpoint;
4448 if (pc_is_mips16 (*pcptr))
4450 static unsigned char mips16_little_breakpoint[] =
4451 MIPS16_LITTLE_BREAKPOINT;
4452 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
4453 *lenptr = sizeof (mips16_little_breakpoint);
4454 return mips16_little_breakpoint;
4458 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
4459 static unsigned char pmon_little_breakpoint[] =
4460 PMON_LITTLE_BREAKPOINT;
4461 static unsigned char idt_little_breakpoint[] =
4462 IDT_LITTLE_BREAKPOINT;
4464 *lenptr = sizeof (little_breakpoint);
4466 if (strcmp (target_shortname, "mips") == 0)
4467 return idt_little_breakpoint;
4468 else if (strcmp (target_shortname, "ddb") == 0
4469 || strcmp (target_shortname, "pmon") == 0
4470 || strcmp (target_shortname, "lsi") == 0)
4471 return pmon_little_breakpoint;
4473 return little_breakpoint;
4478 /* If PC is in a mips16 call or return stub, return the address of the target
4479 PC, which is either the callee or the caller. There are several
4480 cases which must be handled:
4482 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4483 target PC is in $31 ($ra).
4484 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4485 and the target PC is in $2.
4486 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4487 before the jal instruction, this is effectively a call stub
4488 and the the target PC is in $2. Otherwise this is effectively
4489 a return stub and the target PC is in $18.
4491 See the source code for the stubs in gcc/config/mips/mips16.S for
4494 This function implements the SKIP_TRAMPOLINE_CODE macro.
4498 mips_skip_stub (CORE_ADDR pc)
4501 CORE_ADDR start_addr;
4503 /* Find the starting address and name of the function containing the PC. */
4504 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
4507 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4508 target PC is in $31 ($ra). */
4509 if (strcmp (name, "__mips16_ret_sf") == 0
4510 || strcmp (name, "__mips16_ret_df") == 0)
4511 return read_signed_register (RA_REGNUM);
4513 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
4515 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4516 and the target PC is in $2. */
4517 if (name[19] >= '0' && name[19] <= '9')
4518 return read_signed_register (2);
4520 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4521 before the jal instruction, this is effectively a call stub
4522 and the the target PC is in $2. Otherwise this is effectively
4523 a return stub and the target PC is in $18. */
4524 else if (name[19] == 's' || name[19] == 'd')
4526 if (pc == start_addr)
4528 /* Check if the target of the stub is a compiler-generated
4529 stub. Such a stub for a function bar might have a name
4530 like __fn_stub_bar, and might look like this:
4535 la $1,bar (becomes a lui/addiu pair)
4537 So scan down to the lui/addi and extract the target
4538 address from those two instructions. */
4540 CORE_ADDR target_pc = read_signed_register (2);
4544 /* See if the name of the target function is __fn_stub_*. */
4545 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
4547 if (strncmp (name, "__fn_stub_", 10) != 0
4548 && strcmp (name, "etext") != 0
4549 && strcmp (name, "_etext") != 0)
4552 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4553 The limit on the search is arbitrarily set to 20
4554 instructions. FIXME. */
4555 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
4557 inst = mips_fetch_instruction (target_pc);
4558 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
4559 pc = (inst << 16) & 0xffff0000; /* high word */
4560 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
4561 return pc | (inst & 0xffff); /* low word */
4564 /* Couldn't find the lui/addui pair, so return stub address. */
4568 /* This is the 'return' part of a call stub. The return
4569 address is in $r18. */
4570 return read_signed_register (18);
4573 return 0; /* not a stub */
4577 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4578 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4581 mips_in_call_stub (CORE_ADDR pc, char *name)
4583 CORE_ADDR start_addr;
4585 /* Find the starting address of the function containing the PC. If the
4586 caller didn't give us a name, look it up at the same time. */
4587 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
4590 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
4592 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4593 if (name[19] >= '0' && name[19] <= '9')
4595 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4596 before the jal instruction, this is effectively a call stub. */
4597 else if (name[19] == 's' || name[19] == 'd')
4598 return pc == start_addr;
4601 return 0; /* not a stub */
4605 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4606 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4609 mips_in_return_stub (CORE_ADDR pc, char *name)
4611 CORE_ADDR start_addr;
4613 /* Find the starting address of the function containing the PC. */
4614 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
4617 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4618 if (strcmp (name, "__mips16_ret_sf") == 0
4619 || strcmp (name, "__mips16_ret_df") == 0)
4622 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4623 i.e. after the jal instruction, this is effectively a return stub. */
4624 if (strncmp (name, "__mips16_call_stub_", 19) == 0
4625 && (name[19] == 's' || name[19] == 'd')
4626 && pc != start_addr)
4629 return 0; /* not a stub */
4633 /* Return non-zero if the PC is in a library helper function that should
4634 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4637 mips_ignore_helper (CORE_ADDR pc)
4641 /* Find the starting address and name of the function containing the PC. */
4642 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
4645 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4646 that we want to ignore. */
4647 return (strcmp (name, "__mips16_ret_sf") == 0
4648 || strcmp (name, "__mips16_ret_df") == 0);
4652 /* Return a location where we can set a breakpoint that will be hit
4653 when an inferior function call returns. This is normally the
4654 program's entry point. Executables that don't have an entry
4655 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4656 whose address is the location where the breakpoint should be placed. */
4659 mips_call_dummy_address (void)
4661 struct minimal_symbol *sym;
4663 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
4665 return SYMBOL_VALUE_ADDRESS (sym);
4667 return entry_point_address ();
4671 /* If the current gcc for this target does not produce correct debugging
4672 information for float parameters, both prototyped and unprototyped, then
4673 define this macro. This forces gdb to always assume that floats are
4674 passed as doubles and then converted in the callee.
4676 For the mips chip, it appears that the debug info marks the parameters as
4677 floats regardless of whether the function is prototyped, but the actual
4678 values are passed as doubles for the non-prototyped case and floats for
4679 the prototyped case. Thus we choose to make the non-prototyped case work
4680 for C and break the prototyped case, since the non-prototyped case is
4681 probably much more common. (FIXME). */
4684 mips_coerce_float_to_double (struct type *formal, struct type *actual)
4686 return current_language->la_language == language_c;
4689 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4690 the register stored on the stack (32) is different to its real raw
4691 size (64). The below ensures that registers are fetched from the
4692 stack using their ABI size and then stored into the RAW_BUFFER
4693 using their raw size.
4695 The alternative to adding this function would be to add an ABI
4696 macro - REGISTER_STACK_SIZE(). */
4699 mips_get_saved_register (char *raw_buffer,
4702 struct frame_info *frame,
4704 enum lval_type *lval)
4708 if (!target_has_registers)
4709 error ("No registers.");
4711 /* Normal systems don't optimize out things with register numbers. */
4712 if (optimized != NULL)
4714 addr = find_saved_register (frame, regnum);
4718 *lval = lval_memory;
4719 if (regnum == SP_REGNUM)
4721 if (raw_buffer != NULL)
4723 /* Put it back in target format. */
4724 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
4731 if (raw_buffer != NULL)
4735 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4737 val = read_memory_integer (addr, MIPS_SAVED_REGSIZE);
4739 val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum));
4740 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
4746 *lval = lval_register;
4747 addr = REGISTER_BYTE (regnum);
4748 if (raw_buffer != NULL)
4749 read_register_gen (regnum, raw_buffer);
4755 /* Immediately after a function call, return the saved pc.
4756 Can't always go through the frames for this because on some machines
4757 the new frame is not set up until the new function executes
4758 some instructions. */
4761 mips_saved_pc_after_call (struct frame_info *frame)
4763 return read_signed_register (RA_REGNUM);
4767 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4771 mips_stab_reg_to_regnum (int num)
4776 return num + FP0_REGNUM - 38;
4779 /* Convert a ecoff register number to a gdb REGNUM */
4782 mips_ecoff_reg_to_regnum (int num)
4787 return num + FP0_REGNUM - 32;
4790 /* Convert an integer into an address. By first converting the value
4791 into a pointer and then extracting it signed, the address is
4792 guarenteed to be correctly sign extended. */
4795 mips_integer_to_address (struct type *type, void *buf)
4797 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
4798 LONGEST val = unpack_long (type, buf);
4799 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
4800 return extract_signed_integer (tmp,
4801 TYPE_LENGTH (builtin_type_void_data_ptr));
4805 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
4807 enum mips_abi *abip = (enum mips_abi *) obj;
4808 const char *name = bfd_get_section_name (abfd, sect);
4810 if (*abip != MIPS_ABI_UNKNOWN)
4813 if (strncmp (name, ".mdebug.", 8) != 0)
4816 if (strcmp (name, ".mdebug.abi32") == 0)
4817 *abip = MIPS_ABI_O32;
4818 else if (strcmp (name, ".mdebug.abiN32") == 0)
4819 *abip = MIPS_ABI_N32;
4820 else if (strcmp (name, ".mdebug.abiN64") == 0)
4821 *abip = MIPS_ABI_N64;
4822 else if (strcmp (name, ".mdebug.abiO64") == 0)
4823 *abip = MIPS_ABI_O64;
4824 else if (strcmp (name, ".mdebug.eabi32") == 0)
4825 *abip = MIPS_ABI_EABI32;
4826 else if (strcmp (name, ".mdebug.eabi64") == 0)
4827 *abip = MIPS_ABI_EABI64;
4829 warning ("unsupported ABI %s.", name + 8);
4832 static enum mips_abi
4833 global_mips_abi (void)
4837 for (i = 0; mips_abi_strings[i] != NULL; i++)
4838 if (mips_abi_strings[i] == mips_abi_string)
4839 return (enum mips_abi) i;
4841 internal_error (__FILE__, __LINE__,
4842 "unknown ABI string");
4845 static struct gdbarch *
4846 mips_gdbarch_init (struct gdbarch_info info,
4847 struct gdbarch_list *arches)
4849 static LONGEST mips_call_dummy_words[] =
4851 struct gdbarch *gdbarch;
4852 struct gdbarch_tdep *tdep;
4854 enum mips_abi mips_abi, found_abi, wanted_abi;
4855 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
4857 /* Reset the disassembly info, in case it was set to something
4859 tm_print_insn_info.flavour = bfd_target_unknown_flavour;
4860 tm_print_insn_info.arch = bfd_arch_unknown;
4861 tm_print_insn_info.mach = 0;
4867 /* First of all, extract the elf_flags, if available. */
4868 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
4869 elf_flags = elf_elfheader (info.abfd)->e_flags;
4871 /* Try to determine the OS ABI of the object we are loading. If
4872 we end up with `unknown', just leave it that way. */
4873 osabi = gdbarch_lookup_osabi (info.abfd);
4876 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4877 switch ((elf_flags & EF_MIPS_ABI))
4879 case E_MIPS_ABI_O32:
4880 mips_abi = MIPS_ABI_O32;
4882 case E_MIPS_ABI_O64:
4883 mips_abi = MIPS_ABI_O64;
4885 case E_MIPS_ABI_EABI32:
4886 mips_abi = MIPS_ABI_EABI32;
4888 case E_MIPS_ABI_EABI64:
4889 mips_abi = MIPS_ABI_EABI64;
4892 if ((elf_flags & EF_MIPS_ABI2))
4893 mips_abi = MIPS_ABI_N32;
4895 mips_abi = MIPS_ABI_UNKNOWN;
4899 /* GCC creates a pseudo-section whose name describes the ABI. */
4900 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
4901 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
4903 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
4904 Use the ABI from the last architecture if there is one. */
4905 if (info.abfd == NULL && arches != NULL)
4906 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
4908 /* Try the architecture for any hint of the correct ABI. */
4909 if (mips_abi == MIPS_ABI_UNKNOWN
4910 && info.bfd_arch_info != NULL
4911 && info.bfd_arch_info->arch == bfd_arch_mips)
4913 switch (info.bfd_arch_info->mach)
4915 case bfd_mach_mips3900:
4916 mips_abi = MIPS_ABI_EABI32;
4918 case bfd_mach_mips4100:
4919 case bfd_mach_mips5000:
4920 mips_abi = MIPS_ABI_EABI64;
4922 case bfd_mach_mips8000:
4923 case bfd_mach_mips10000:
4924 /* On Irix, ELF64 executables use the N64 ABI. The
4925 pseudo-sections which describe the ABI aren't present
4926 on IRIX. (Even for executables created by gcc.) */
4927 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
4928 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
4929 mips_abi = MIPS_ABI_N64;
4931 mips_abi = MIPS_ABI_N32;
4936 #ifdef MIPS_DEFAULT_ABI
4937 if (mips_abi == MIPS_ABI_UNKNOWN)
4938 mips_abi = MIPS_DEFAULT_ABI;
4941 if (mips_abi == MIPS_ABI_UNKNOWN)
4942 mips_abi = MIPS_ABI_O32;
4944 /* Now that we have found what the ABI for this binary would be,
4945 check whether the user is overriding it. */
4946 found_abi = mips_abi;
4947 wanted_abi = global_mips_abi ();
4948 if (wanted_abi != MIPS_ABI_UNKNOWN)
4949 mips_abi = wanted_abi;
4953 fprintf_unfiltered (gdb_stdlog,
4954 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4956 fprintf_unfiltered (gdb_stdlog,
4957 "mips_gdbarch_init: mips_abi = %d\n",
4959 fprintf_unfiltered (gdb_stdlog,
4960 "mips_gdbarch_init: found_mips_abi = %d\n",
4964 /* try to find a pre-existing architecture */
4965 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4967 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4969 /* MIPS needs to be pedantic about which ABI the object is
4971 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
4973 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
4975 if (gdbarch_tdep (arches->gdbarch)->osabi == osabi)
4976 return arches->gdbarch;
4979 /* Need a new architecture. Fill in a target specific vector. */
4980 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4981 gdbarch = gdbarch_alloc (&info, tdep);
4982 tdep->elf_flags = elf_flags;
4983 tdep->osabi = osabi;
4985 /* Initially set everything according to the default ABI/ISA. */
4986 set_gdbarch_short_bit (gdbarch, 16);
4987 set_gdbarch_int_bit (gdbarch, 32);
4988 set_gdbarch_float_bit (gdbarch, 32);
4989 set_gdbarch_double_bit (gdbarch, 64);
4990 set_gdbarch_long_double_bit (gdbarch, 64);
4991 set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size);
4992 set_gdbarch_max_register_raw_size (gdbarch, 8);
4993 set_gdbarch_max_register_virtual_size (gdbarch, 8);
4994 tdep->found_abi = found_abi;
4995 tdep->mips_abi = mips_abi;
5000 set_gdbarch_push_arguments (gdbarch, mips_o32o64_push_arguments);
5001 tdep->mips_default_saved_regsize = 4;
5002 tdep->mips_default_stack_argsize = 4;
5003 tdep->mips_fp_register_double = 0;
5004 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5005 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5006 tdep->gdb_target_is_mips64 = 0;
5007 tdep->default_mask_address_p = 0;
5008 set_gdbarch_long_bit (gdbarch, 32);
5009 set_gdbarch_ptr_bit (gdbarch, 32);
5010 set_gdbarch_long_long_bit (gdbarch, 64);
5011 set_gdbarch_reg_struct_has_addr (gdbarch,
5012 mips_o32_reg_struct_has_addr);
5013 set_gdbarch_use_struct_convention (gdbarch,
5014 mips_o32_use_struct_convention);
5017 set_gdbarch_push_arguments (gdbarch, mips_o32o64_push_arguments);
5018 tdep->mips_default_saved_regsize = 8;
5019 tdep->mips_default_stack_argsize = 8;
5020 tdep->mips_fp_register_double = 1;
5021 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5022 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5023 tdep->gdb_target_is_mips64 = 1;
5024 tdep->default_mask_address_p = 0;
5025 set_gdbarch_long_bit (gdbarch, 32);
5026 set_gdbarch_ptr_bit (gdbarch, 32);
5027 set_gdbarch_long_long_bit (gdbarch, 64);
5028 set_gdbarch_reg_struct_has_addr (gdbarch,
5029 mips_o32_reg_struct_has_addr);
5030 set_gdbarch_use_struct_convention (gdbarch,
5031 mips_o32_use_struct_convention);
5033 case MIPS_ABI_EABI32:
5034 set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments);
5035 tdep->mips_default_saved_regsize = 4;
5036 tdep->mips_default_stack_argsize = 4;
5037 tdep->mips_fp_register_double = 0;
5038 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5039 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5040 tdep->gdb_target_is_mips64 = 0;
5041 tdep->default_mask_address_p = 0;
5042 set_gdbarch_long_bit (gdbarch, 32);
5043 set_gdbarch_ptr_bit (gdbarch, 32);
5044 set_gdbarch_long_long_bit (gdbarch, 64);
5045 set_gdbarch_reg_struct_has_addr (gdbarch,
5046 mips_eabi_reg_struct_has_addr);
5047 set_gdbarch_use_struct_convention (gdbarch,
5048 mips_eabi_use_struct_convention);
5050 case MIPS_ABI_EABI64:
5051 set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments);
5052 tdep->mips_default_saved_regsize = 8;
5053 tdep->mips_default_stack_argsize = 8;
5054 tdep->mips_fp_register_double = 1;
5055 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5056 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5057 tdep->gdb_target_is_mips64 = 1;
5058 tdep->default_mask_address_p = 0;
5059 set_gdbarch_long_bit (gdbarch, 64);
5060 set_gdbarch_ptr_bit (gdbarch, 64);
5061 set_gdbarch_long_long_bit (gdbarch, 64);
5062 set_gdbarch_reg_struct_has_addr (gdbarch,
5063 mips_eabi_reg_struct_has_addr);
5064 set_gdbarch_use_struct_convention (gdbarch,
5065 mips_eabi_use_struct_convention);
5068 set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments);
5069 tdep->mips_default_saved_regsize = 8;
5070 tdep->mips_default_stack_argsize = 8;
5071 tdep->mips_fp_register_double = 1;
5072 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5073 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5074 tdep->gdb_target_is_mips64 = 1;
5075 tdep->default_mask_address_p = 0;
5076 set_gdbarch_long_bit (gdbarch, 32);
5077 set_gdbarch_ptr_bit (gdbarch, 32);
5078 set_gdbarch_long_long_bit (gdbarch, 64);
5080 /* Set up the disassembler info, so that we get the right
5081 register names from libopcodes. */
5082 tm_print_insn_info.flavour = bfd_target_elf_flavour;
5083 tm_print_insn_info.arch = bfd_arch_mips;
5084 if (info.bfd_arch_info != NULL
5085 && info.bfd_arch_info->arch == bfd_arch_mips
5086 && info.bfd_arch_info->mach)
5087 tm_print_insn_info.mach = info.bfd_arch_info->mach;
5089 tm_print_insn_info.mach = bfd_mach_mips8000;
5091 set_gdbarch_use_struct_convention (gdbarch,
5092 mips_n32n64_use_struct_convention);
5093 set_gdbarch_reg_struct_has_addr (gdbarch,
5094 mips_n32n64_reg_struct_has_addr);
5097 set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments);
5098 tdep->mips_default_saved_regsize = 8;
5099 tdep->mips_default_stack_argsize = 8;
5100 tdep->mips_fp_register_double = 1;
5101 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5102 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5103 tdep->gdb_target_is_mips64 = 1;
5104 tdep->default_mask_address_p = 0;
5105 set_gdbarch_long_bit (gdbarch, 64);
5106 set_gdbarch_ptr_bit (gdbarch, 64);
5107 set_gdbarch_long_long_bit (gdbarch, 64);
5109 /* Set up the disassembler info, so that we get the right
5110 register names from libopcodes. */
5111 tm_print_insn_info.flavour = bfd_target_elf_flavour;
5112 tm_print_insn_info.arch = bfd_arch_mips;
5113 if (info.bfd_arch_info != NULL
5114 && info.bfd_arch_info->arch == bfd_arch_mips
5115 && info.bfd_arch_info->mach)
5116 tm_print_insn_info.mach = info.bfd_arch_info->mach;
5118 tm_print_insn_info.mach = bfd_mach_mips8000;
5120 set_gdbarch_use_struct_convention (gdbarch,
5121 mips_n32n64_use_struct_convention);
5122 set_gdbarch_reg_struct_has_addr (gdbarch,
5123 mips_n32n64_reg_struct_has_addr);
5126 internal_error (__FILE__, __LINE__,
5127 "unknown ABI in switch");
5130 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5131 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5134 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5135 flag in object files because to do so would make it impossible to
5136 link with libraries compiled without "-gp32". This is
5137 unnecessarily restrictive.
5139 We could solve this problem by adding "-gp32" multilibs to gcc,
5140 but to set this flag before gcc is built with such multilibs will
5141 break too many systems.''
5143 But even more unhelpfully, the default linker output target for
5144 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5145 for 64-bit programs - you need to change the ABI to change this,
5146 and not all gcc targets support that currently. Therefore using
5147 this flag to detect 32-bit mode would do the wrong thing given
5148 the current gcc - it would make GDB treat these 64-bit programs
5149 as 32-bit programs by default. */
5151 /* enable/disable the MIPS FPU */
5152 if (!mips_fpu_type_auto)
5153 tdep->mips_fpu_type = mips_fpu_type;
5154 else if (info.bfd_arch_info != NULL
5155 && info.bfd_arch_info->arch == bfd_arch_mips)
5156 switch (info.bfd_arch_info->mach)
5158 case bfd_mach_mips3900:
5159 case bfd_mach_mips4100:
5160 case bfd_mach_mips4111:
5161 tdep->mips_fpu_type = MIPS_FPU_NONE;
5163 case bfd_mach_mips4650:
5164 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
5167 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5171 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5173 /* MIPS version of register names. NOTE: At present the MIPS
5174 register name management is part way between the old -
5175 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5176 Further work on it is required. */
5177 set_gdbarch_register_name (gdbarch, mips_register_name);
5178 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5179 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
5180 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
5181 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5182 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
5184 /* Add/remove bits from an address. The MIPS needs be careful to
5185 ensure that all 32 bit addresses are sign extended to 64 bits. */
5186 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5188 /* There's a mess in stack frame creation. See comments in
5189 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
5190 set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
5191 set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop);
5193 /* Map debug register numbers onto internal register numbers. */
5194 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5195 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum);
5197 /* Initialize a frame */
5198 set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
5199 set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs);
5201 /* MIPS version of CALL_DUMMY */
5203 set_gdbarch_call_dummy_p (gdbarch, 1);
5204 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
5205 set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
5206 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
5207 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
5208 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
5209 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
5210 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
5211 set_gdbarch_call_dummy_length (gdbarch, 0);
5212 set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
5213 set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
5214 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
5215 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
5216 set_gdbarch_register_convertible (gdbarch, mips_register_convertible);
5217 set_gdbarch_register_convert_to_virtual (gdbarch,
5218 mips_register_convert_to_virtual);
5219 set_gdbarch_register_convert_to_raw (gdbarch,
5220 mips_register_convert_to_raw);
5222 set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double);
5224 set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
5225 set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
5227 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5228 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5229 set_gdbarch_decr_pc_after_break (gdbarch, 0);
5231 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5232 set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
5234 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5235 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5236 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5238 /* There are MIPS targets which do not yet use this since they still
5239 define REGISTER_VIRTUAL_TYPE. */
5240 set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type);
5242 set_gdbarch_do_registers_info (gdbarch, mips_do_registers_info);
5244 /* Hook in OS ABI-specific overrides, if they have been registered. */
5245 gdbarch_init_osabi (info, gdbarch, osabi);
5251 mips_abi_update (char *ignore_args, int from_tty,
5252 struct cmd_list_element *c)
5254 struct gdbarch_info info;
5256 /* Force the architecture to update, and (if it's a MIPS architecture)
5257 mips_gdbarch_init will take care of the rest. */
5258 gdbarch_info_init (&info);
5259 gdbarch_update_p (info);
5263 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
5265 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
5269 int ef_mips_32bitmode;
5270 /* determine the ISA */
5271 switch (tdep->elf_flags & EF_MIPS_ARCH)
5289 /* determine the size of a pointer */
5290 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
5291 fprintf_unfiltered (file,
5292 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5294 fprintf_unfiltered (file,
5295 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5297 fprintf_unfiltered (file,
5298 "mips_dump_tdep: ef_mips_arch = %d\n",
5300 fprintf_unfiltered (file,
5301 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5303 mips_abi_strings[tdep->mips_abi]);
5304 fprintf_unfiltered (file,
5305 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5306 mips_mask_address_p (),
5307 tdep->default_mask_address_p);
5309 fprintf_unfiltered (file,
5310 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5311 FP_REGISTER_DOUBLE);
5312 fprintf_unfiltered (file,
5313 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5314 MIPS_DEFAULT_FPU_TYPE,
5315 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
5316 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5317 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5319 fprintf_unfiltered (file,
5320 "mips_dump_tdep: MIPS_EABI = %d\n",
5322 fprintf_unfiltered (file,
5323 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
5324 MIPS_LAST_FP_ARG_REGNUM,
5325 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
5326 fprintf_unfiltered (file,
5327 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5329 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
5330 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5331 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5333 fprintf_unfiltered (file,
5334 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
5335 MIPS_DEFAULT_SAVED_REGSIZE);
5336 fprintf_unfiltered (file,
5337 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5338 FP_REGISTER_DOUBLE);
5339 fprintf_unfiltered (file,
5340 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
5341 MIPS_DEFAULT_STACK_ARGSIZE);
5342 fprintf_unfiltered (file,
5343 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
5344 MIPS_STACK_ARGSIZE);
5345 fprintf_unfiltered (file,
5346 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
5348 fprintf_unfiltered (file,
5349 "mips_dump_tdep: A0_REGNUM = %d\n",
5351 fprintf_unfiltered (file,
5352 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5353 XSTRING (ADDR_BITS_REMOVE(ADDR)));
5354 fprintf_unfiltered (file,
5355 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5356 XSTRING (ATTACH_DETACH));
5357 fprintf_unfiltered (file,
5358 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
5360 fprintf_unfiltered (file,
5361 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
5362 fprintf_unfiltered (file,
5363 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
5365 fprintf_unfiltered (file,
5366 "mips_dump_tdep: CPLUS_MARKER = %c\n",
5368 fprintf_unfiltered (file,
5369 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
5371 fprintf_unfiltered (file,
5372 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
5373 XSTRING (DO_REGISTERS_INFO));
5374 fprintf_unfiltered (file,
5375 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5376 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
5377 fprintf_unfiltered (file,
5378 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5379 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
5380 fprintf_unfiltered (file,
5381 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
5382 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM)));
5383 fprintf_unfiltered (file,
5384 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
5386 fprintf_unfiltered (file,
5387 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
5389 fprintf_unfiltered (file,
5390 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5391 FIRST_EMBED_REGNUM);
5392 fprintf_unfiltered (file,
5393 "mips_dump_tdep: FPA0_REGNUM = %d\n",
5395 fprintf_unfiltered (file,
5396 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
5397 GDB_TARGET_IS_MIPS64);
5398 fprintf_unfiltered (file,
5399 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
5400 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC)));
5401 fprintf_unfiltered (file,
5402 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
5403 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC)));
5404 fprintf_unfiltered (file,
5405 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
5407 fprintf_unfiltered (file,
5408 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
5409 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
5410 fprintf_unfiltered (file,
5411 "mips_dump_tdep: HI_REGNUM = %d\n",
5413 fprintf_unfiltered (file,
5414 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
5415 fprintf_unfiltered (file,
5416 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
5417 fprintf_unfiltered (file,
5418 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5419 XSTRING (IGNORE_HELPER_CALL (PC)));
5420 fprintf_unfiltered (file,
5421 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5422 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
5423 fprintf_unfiltered (file,
5424 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5425 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
5426 fprintf_unfiltered (file,
5427 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
5428 fprintf_unfiltered (file,
5429 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5431 fprintf_unfiltered (file,
5432 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
5433 fprintf_unfiltered (file,
5434 "mips_dump_tdep: LO_REGNUM = %d\n",
5436 #ifdef MACHINE_CPROC_FP_OFFSET
5437 fprintf_unfiltered (file,
5438 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5439 MACHINE_CPROC_FP_OFFSET);
5441 #ifdef MACHINE_CPROC_PC_OFFSET
5442 fprintf_unfiltered (file,
5443 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5444 MACHINE_CPROC_PC_OFFSET);
5446 #ifdef MACHINE_CPROC_SP_OFFSET
5447 fprintf_unfiltered (file,
5448 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5449 MACHINE_CPROC_SP_OFFSET);
5451 fprintf_unfiltered (file,
5452 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
5453 fprintf_unfiltered (file,
5454 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
5455 fprintf_unfiltered (file,
5456 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5458 fprintf_unfiltered (file,
5459 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
5460 fprintf_unfiltered (file,
5461 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5462 fprintf_unfiltered (file,
5463 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5464 fprintf_unfiltered (file,
5465 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
5467 fprintf_unfiltered (file,
5468 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5469 MIPS_LAST_ARG_REGNUM,
5470 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
5471 fprintf_unfiltered (file,
5472 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
5474 fprintf_unfiltered (file,
5475 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
5476 fprintf_unfiltered (file,
5477 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
5478 MIPS_SAVED_REGSIZE);
5479 fprintf_unfiltered (file,
5480 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
5481 fprintf_unfiltered (file,
5482 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
5483 XSTRING (MSYMBOL_SIZE (MSYM)));
5484 fprintf_unfiltered (file,
5485 "mips_dump_tdep: OP_LDFPR = used?\n");
5486 fprintf_unfiltered (file,
5487 "mips_dump_tdep: OP_LDGPR = used?\n");
5488 fprintf_unfiltered (file,
5489 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
5490 fprintf_unfiltered (file,
5491 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
5492 fprintf_unfiltered (file,
5493 "mips_dump_tdep: PRID_REGNUM = %d\n",
5495 fprintf_unfiltered (file,
5496 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
5497 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
5498 fprintf_unfiltered (file,
5499 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5500 fprintf_unfiltered (file,
5501 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5502 fprintf_unfiltered (file,
5503 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5504 fprintf_unfiltered (file,
5505 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5506 fprintf_unfiltered (file,
5507 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5508 fprintf_unfiltered (file,
5509 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5510 fprintf_unfiltered (file,
5511 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5512 fprintf_unfiltered (file,
5513 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5514 fprintf_unfiltered (file,
5515 "mips_dump_tdep: PROC_PC_REG = function?\n");
5516 fprintf_unfiltered (file,
5517 "mips_dump_tdep: PROC_REG_MASK = function?\n");
5518 fprintf_unfiltered (file,
5519 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5520 fprintf_unfiltered (file,
5521 "mips_dump_tdep: PROC_SYMBOL = function?\n");
5522 fprintf_unfiltered (file,
5523 "mips_dump_tdep: PS_REGNUM = %d\n",
5525 fprintf_unfiltered (file,
5526 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
5528 fprintf_unfiltered (file,
5529 "mips_dump_tdep: RA_REGNUM = %d\n",
5531 fprintf_unfiltered (file,
5532 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
5533 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
5534 fprintf_unfiltered (file,
5535 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
5536 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
5537 fprintf_unfiltered (file,
5538 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
5539 fprintf_unfiltered (file,
5540 "mips_dump_tdep: ROUND_DOWN = function?\n");
5541 fprintf_unfiltered (file,
5542 "mips_dump_tdep: ROUND_UP = function?\n");
5544 fprintf_unfiltered (file,
5545 "mips_dump_tdep: SAVED_BYTES = %d\n",
5549 fprintf_unfiltered (file,
5550 "mips_dump_tdep: SAVED_FP = %d\n",
5554 fprintf_unfiltered (file,
5555 "mips_dump_tdep: SAVED_PC = %d\n",
5558 fprintf_unfiltered (file,
5559 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5560 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
5561 fprintf_unfiltered (file,
5562 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
5563 fprintf_unfiltered (file,
5564 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
5566 fprintf_unfiltered (file,
5567 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
5568 SIGFRAME_FPREGSAVE_OFF);
5569 fprintf_unfiltered (file,
5570 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
5572 fprintf_unfiltered (file,
5573 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
5574 SIGFRAME_REGSAVE_OFF);
5575 fprintf_unfiltered (file,
5576 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
5578 fprintf_unfiltered (file,
5579 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
5580 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
5581 fprintf_unfiltered (file,
5582 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5583 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
5584 fprintf_unfiltered (file,
5585 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5586 SOFTWARE_SINGLE_STEP_P ());
5587 fprintf_unfiltered (file,
5588 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5589 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
5590 #ifdef STACK_END_ADDR
5591 fprintf_unfiltered (file,
5592 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5595 fprintf_unfiltered (file,
5596 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5597 XSTRING (STEP_SKIPS_DELAY (PC)));
5598 fprintf_unfiltered (file,
5599 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5600 STEP_SKIPS_DELAY_P);
5601 fprintf_unfiltered (file,
5602 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5603 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
5604 fprintf_unfiltered (file,
5605 "mips_dump_tdep: T9_REGNUM = %d\n",
5607 fprintf_unfiltered (file,
5608 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5609 fprintf_unfiltered (file,
5610 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5611 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
5612 fprintf_unfiltered (file,
5613 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
5614 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
5615 fprintf_unfiltered (file,
5616 "mips_dump_tdep: TARGET_MIPS = used?\n");
5617 fprintf_unfiltered (file,
5618 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
5619 XSTRING (TM_PRINT_INSN_MACH));
5621 fprintf_unfiltered (file,
5622 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5623 XSTRING (TRACE_CLEAR (THREAD, STATE)));
5626 fprintf_unfiltered (file,
5627 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
5630 #ifdef TRACE_FLAVOR_SIZE
5631 fprintf_unfiltered (file,
5632 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5636 fprintf_unfiltered (file,
5637 "mips_dump_tdep: TRACE_SET # %s\n",
5638 XSTRING (TRACE_SET (X,STATE)));
5640 fprintf_unfiltered (file,
5641 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
5642 #ifdef UNUSED_REGNUM
5643 fprintf_unfiltered (file,
5644 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
5647 fprintf_unfiltered (file,
5648 "mips_dump_tdep: V0_REGNUM = %d\n",
5650 fprintf_unfiltered (file,
5651 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5652 (long) VM_MIN_ADDRESS);
5654 fprintf_unfiltered (file,
5655 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
5658 fprintf_unfiltered (file,
5659 "mips_dump_tdep: ZERO_REGNUM = %d\n",
5661 fprintf_unfiltered (file,
5662 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
5665 fprintf_unfiltered (file,
5666 "mips_dump_tdep: OS ABI = %s\n",
5667 gdbarch_osabi_name (tdep->osabi));
5671 _initialize_mips_tdep (void)
5673 static struct cmd_list_element *mipsfpulist = NULL;
5674 struct cmd_list_element *c;
5676 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
5677 if (MIPS_ABI_LAST + 1
5678 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
5679 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
5681 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
5682 if (!tm_print_insn) /* Someone may have already set it */
5683 tm_print_insn = gdb_print_insn_mips;
5685 /* Add root prefix command for all "set mips"/"show mips" commands */
5686 add_prefix_cmd ("mips", no_class, set_mips_command,
5687 "Various MIPS specific commands.",
5688 &setmipscmdlist, "set mips ", 0, &setlist);
5690 add_prefix_cmd ("mips", no_class, show_mips_command,
5691 "Various MIPS specific commands.",
5692 &showmipscmdlist, "show mips ", 0, &showlist);
5694 /* Allow the user to override the saved register size. */
5695 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5698 &mips_saved_regsize_string, "\
5699 Set size of general purpose registers saved on the stack.\n\
5700 This option can be set to one of:\n\
5701 32 - Force GDB to treat saved GP registers as 32-bit\n\
5702 64 - Force GDB to treat saved GP registers as 64-bit\n\
5703 auto - Allow GDB to use the target's default setting or autodetect the\n\
5704 saved GP register size from information contained in the executable.\n\
5709 /* Allow the user to override the argument stack size. */
5710 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5713 &mips_stack_argsize_string, "\
5714 Set the amount of stack space reserved for each argument.\n\
5715 This option can be set to one of:\n\
5716 32 - Force GDB to allocate 32-bit chunks per argument\n\
5717 64 - Force GDB to allocate 64-bit chunks per argument\n\
5718 auto - Allow GDB to determine the correct setting from the current\n\
5719 target and executable (default)",
5723 /* Allow the user to override the ABI. */
5724 c = add_set_enum_cmd
5725 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
5726 "Set the ABI used by this program.\n"
5727 "This option can be set to one of:\n"
5728 " auto - the default ABI associated with the current binary\n"
5736 add_show_from_set (c, &showmipscmdlist);
5737 set_cmd_sfunc (c, mips_abi_update);
5739 /* Let the user turn off floating point and set the fence post for
5740 heuristic_proc_start. */
5742 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
5743 "Set use of MIPS floating-point coprocessor.",
5744 &mipsfpulist, "set mipsfpu ", 0, &setlist);
5745 add_cmd ("single", class_support, set_mipsfpu_single_command,
5746 "Select single-precision MIPS floating-point coprocessor.",
5748 add_cmd ("double", class_support, set_mipsfpu_double_command,
5749 "Select double-precision MIPS floating-point coprocessor.",
5751 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
5752 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
5753 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
5754 add_cmd ("none", class_support, set_mipsfpu_none_command,
5755 "Select no MIPS floating-point coprocessor.",
5757 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
5758 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
5759 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
5760 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
5761 "Select MIPS floating-point coprocessor automatically.",
5763 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
5764 "Show current use of MIPS floating-point coprocessor target.",
5767 /* We really would like to have both "0" and "unlimited" work, but
5768 command.c doesn't deal with that. So make it a var_zinteger
5769 because the user can always use "999999" or some such for unlimited. */
5770 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
5771 (char *) &heuristic_fence_post,
5773 Set the distance searched for the start of a function.\n\
5774 If you are debugging a stripped executable, GDB needs to search through the\n\
5775 program for the start of a function. This command sets the distance of the\n\
5776 search. The only need to set it is when debugging a stripped executable.",
5778 /* We need to throw away the frame cache when we set this, since it
5779 might change our ability to get backtraces. */
5780 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
5781 add_show_from_set (c, &showlist);
5783 /* Allow the user to control whether the upper bits of 64-bit
5784 addresses should be zeroed. */
5785 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
5786 Set zeroing of upper 32 bits of 64-bit addresses.\n\
5787 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5788 allow GDB to determine the correct value.\n", "\
5789 Show zeroing of upper 32 bits of 64-bit addresses.",
5790 NULL, show_mask_address,
5791 &setmipscmdlist, &showmipscmdlist);
5793 /* Allow the user to control the size of 32 bit registers within the
5794 raw remote packet. */
5795 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5798 (char *)&mips64_transfers_32bit_regs_p, "\
5799 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5800 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5801 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5802 64 bits for others. Use \"off\" to disable compatibility mode",
5806 /* Debug this files internals. */
5807 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
5808 &mips_debug, "Set mips debugging.\n\
5809 When non-zero, mips specific debugging is enabled.", &setdebuglist),