1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE = 4,
57 MIPS_FPU_DOUBLE_REGSIZE = 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string;
76 static const char *mips_abi_strings[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto[] = "auto";
98 static const char size_32[] = "32";
99 static const char size_64[] = "64";
101 static const char *size_enums[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE /* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto = 1;
123 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
125 static int mips_debug = 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi;
135 enum mips_abi found_abi;
136 enum mips_fpu_type mips_fpu_type;
137 int mips_last_arg_regnum;
138 int mips_last_fp_arg_regnum;
139 int mips_default_saved_regsize;
140 int mips_fp_register_double;
141 int mips_regs_have_home_p;
142 int mips_default_stack_argsize;
143 int gdb_target_is_mips64;
144 int default_mask_address_p;
146 enum gdb_osabi osabi;
149 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
150 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
152 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
154 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
156 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
158 /* Return the currently configured (or set) saved register size. */
160 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
162 static const char *mips_saved_regsize_string = size_auto;
164 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
167 mips_saved_regsize (void)
169 if (mips_saved_regsize_string == size_auto)
170 return MIPS_DEFAULT_SAVED_REGSIZE;
171 else if (mips_saved_regsize_string == size_64)
173 else /* if (mips_saved_regsize_string == size_32) */
177 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
178 compatiblity mode. A return value of 1 means that we have
179 physical 64-bit registers, but should treat them as 32-bit registers. */
182 mips2_fp_compat (void)
184 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
186 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
190 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
191 in all the places we deal with FP registers. PR gdb/413. */
192 /* Otherwise check the FR bit in the status register - it controls
193 the FP compatiblity mode. If it is clear we are in compatibility
195 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
202 /* Indicate that the ABI makes use of double-precision registers
203 provided by the FPU (rather than combining pairs of registers to
204 form double-precision values). Do not use "TARGET_IS_MIPS64" to
205 determine if the ABI is using double-precision registers. See also
207 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
209 /* Does the caller allocate a ``home'' for each register used in the
210 function call? The N32 ABI and MIPS_EABI do not, the others do. */
212 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
214 /* The amount of space reserved on the stack for registers. This is
215 different to MIPS_SAVED_REGSIZE as it determines the alignment of
216 data allocated after the registers have run out. */
218 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
220 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
222 static const char *mips_stack_argsize_string = size_auto;
225 mips_stack_argsize (void)
227 if (mips_stack_argsize_string == size_auto)
228 return MIPS_DEFAULT_STACK_ARGSIZE;
229 else if (mips_stack_argsize_string == size_64)
231 else /* if (mips_stack_argsize_string == size_32) */
235 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
237 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
239 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
241 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
243 static void mips_print_register (int, int);
245 static mips_extra_func_info_t
246 heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int);
248 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
250 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
252 int mips_set_processor_type (char *);
254 static void mips_show_processor_type_command (char *, int);
256 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
258 static mips_extra_func_info_t
259 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame);
261 static CORE_ADDR after_prologue (CORE_ADDR pc,
262 mips_extra_func_info_t proc_desc);
264 static void mips_read_fp_register_single (int regno, char *rare_buffer);
265 static void mips_read_fp_register_double (int regno, char *rare_buffer);
267 static struct type *mips_float_register_type (void);
268 static struct type *mips_double_register_type (void);
270 /* This value is the model of MIPS in use. It is derived from the value
271 of the PrID register. */
273 char *mips_processor_type;
275 char *tmp_mips_processor_type;
277 /* The list of available "set mips " and "show mips " commands */
279 static struct cmd_list_element *setmipscmdlist = NULL;
280 static struct cmd_list_element *showmipscmdlist = NULL;
282 /* A set of original names, to be used when restoring back to generic
283 registers from a specific set. */
285 char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
286 char **mips_processor_reg_names = mips_generic_reg_names;
289 mips_register_name (int i)
291 return mips_processor_reg_names[i];
294 /* Names of IDT R3041 registers. */
296 char *mips_r3041_reg_names[] = {
297 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
298 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
299 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
300 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
301 "sr", "lo", "hi", "bad", "cause","pc",
302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
306 "fsr", "fir", "fp", "",
307 "", "", "bus", "ccfg", "", "", "", "",
308 "", "", "port", "cmp", "", "", "epc", "prid",
311 /* Names of IDT R3051 registers. */
313 char *mips_r3051_reg_names[] = {
314 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
315 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
316 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
317 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
318 "sr", "lo", "hi", "bad", "cause","pc",
319 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
320 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
321 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
322 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
323 "fsr", "fir", "fp", "",
324 "inx", "rand", "elo", "", "ctxt", "", "", "",
325 "", "", "ehi", "", "", "", "epc", "prid",
328 /* Names of IDT R3081 registers. */
330 char *mips_r3081_reg_names[] = {
331 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
332 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
333 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
334 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
335 "sr", "lo", "hi", "bad", "cause","pc",
336 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
337 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
338 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
339 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
340 "fsr", "fir", "fp", "",
341 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
342 "", "", "ehi", "", "", "", "epc", "prid",
345 /* Names of LSI 33k registers. */
347 char *mips_lsi33k_reg_names[] = {
348 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
349 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
350 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
351 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
352 "epc", "hi", "lo", "sr", "cause","badvaddr",
353 "dcic", "bpc", "bda", "", "", "", "", "",
354 "", "", "", "", "", "", "", "",
355 "", "", "", "", "", "", "", "",
356 "", "", "", "", "", "", "", "",
358 "", "", "", "", "", "", "", "",
359 "", "", "", "", "", "", "", "",
365 } mips_processor_type_table[] = {
366 { "generic", mips_generic_reg_names },
367 { "r3041", mips_r3041_reg_names },
368 { "r3051", mips_r3051_reg_names },
369 { "r3071", mips_r3081_reg_names },
370 { "r3081", mips_r3081_reg_names },
371 { "lsi33k", mips_lsi33k_reg_names },
379 /* Table to translate MIPS16 register field to actual register number. */
380 static int mips16_to_32_reg[8] =
381 {16, 17, 2, 3, 4, 5, 6, 7};
383 /* Heuristic_proc_start may hunt through the text section for a long
384 time across a 2400 baud serial line. Allows the user to limit this
387 static unsigned int heuristic_fence_post = 0;
389 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
390 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
391 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
392 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
393 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
394 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
395 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
396 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
397 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
398 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
399 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
400 this will corrupt pdr.iline. Fortunately we don't use it. */
401 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
402 #define _PROC_MAGIC_ 0x0F0F0F0F
403 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
404 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
406 struct linked_proc_info
408 struct mips_extra_func_info info;
409 struct linked_proc_info *next;
411 *linked_proc_desc_table = NULL;
414 mips_print_extra_frame_info (struct frame_info *fi)
418 && fi->extra_info->proc_desc
419 && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS)
420 printf_filtered (" frame pointer is at %s+%s\n",
421 REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg),
422 paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
425 /* Number of bytes of storage in the actual machine representation for
426 register N. NOTE: This indirectly defines the register size
427 transfered by the GDB protocol. */
429 static int mips64_transfers_32bit_regs_p = 0;
432 mips_register_raw_size (int reg_nr)
434 if (mips64_transfers_32bit_regs_p)
435 return REGISTER_VIRTUAL_SIZE (reg_nr);
436 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
437 && FP_REGISTER_DOUBLE)
438 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
445 /* Convert between RAW and VIRTUAL registers. The RAW register size
446 defines the remote-gdb packet. */
449 mips_register_convertible (int reg_nr)
451 if (mips64_transfers_32bit_regs_p)
454 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
458 mips_register_convert_to_virtual (int n, struct type *virtual_type,
459 char *raw_buf, char *virt_buf)
461 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
463 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
464 TYPE_LENGTH (virtual_type));
468 TYPE_LENGTH (virtual_type));
472 mips_register_convert_to_raw (struct type *virtual_type, int n,
473 char *virt_buf, char *raw_buf)
475 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
476 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
477 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
479 TYPE_LENGTH (virtual_type));
483 TYPE_LENGTH (virtual_type));
486 /* Return the GDB type object for the "standard" data type
487 of data in register REG.
489 Note: kevinb/2002-08-01: The definition below should faithfully
490 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
491 definitions found in config/mips/tm-*.h. I'm concerned about
492 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
493 though. In some cases FP_REGNUM is in this range, and I doubt
494 that this code is correct for the 64-bit case. */
497 mips_register_virtual_type (int reg)
499 if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32)
501 /* Floating point registers... */
502 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
503 return builtin_type_ieee_double_big;
505 return builtin_type_ieee_double_little;
507 else if (reg == PS_REGNUM /* CR */)
508 return builtin_type_uint32;
509 else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM)
510 return builtin_type_uint32;
513 /* Everything else...
514 Return type appropriate for width of register. */
515 if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64))
516 return builtin_type_uint64;
518 return builtin_type_uint32;
522 /* Should the upper word of 64-bit addresses be zeroed? */
523 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
526 mips_mask_address_p (void)
528 switch (mask_address_var)
530 case AUTO_BOOLEAN_TRUE:
532 case AUTO_BOOLEAN_FALSE:
535 case AUTO_BOOLEAN_AUTO:
536 return MIPS_DEFAULT_MASK_ADDRESS_P;
538 internal_error (__FILE__, __LINE__,
539 "mips_mask_address_p: bad switch");
545 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
547 switch (mask_address_var)
549 case AUTO_BOOLEAN_TRUE:
550 printf_filtered ("The 32 bit mips address mask is enabled\n");
552 case AUTO_BOOLEAN_FALSE:
553 printf_filtered ("The 32 bit mips address mask is disabled\n");
555 case AUTO_BOOLEAN_AUTO:
556 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
557 mips_mask_address_p () ? "enabled" : "disabled");
560 internal_error (__FILE__, __LINE__,
561 "show_mask_address: bad switch");
566 /* Should call_function allocate stack space for a struct return? */
569 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
571 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
575 mips_n32n64_use_struct_convention (int gcc_p, struct type *type)
577 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
581 mips_o32_use_struct_convention (int gcc_p, struct type *type)
583 return 1; /* Structures are returned by ref in extra arg0. */
586 /* Should call_function pass struct by reference?
587 For each architecture, structs are passed either by
588 value or by reference, depending on their size. */
591 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
593 enum type_code typecode = TYPE_CODE (check_typedef (type));
594 int len = TYPE_LENGTH (check_typedef (type));
596 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
597 return (len > MIPS_SAVED_REGSIZE);
603 mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type)
605 return 0; /* Assumption: N32/N64 never passes struct by ref. */
609 mips_o32_reg_struct_has_addr (int gcc_p, struct type *type)
611 return 0; /* Assumption: O32/O64 never passes struct by ref. */
614 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
617 pc_is_mips16 (bfd_vma memaddr)
619 struct minimal_symbol *sym;
621 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
622 if (IS_MIPS16_ADDR (memaddr))
625 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
626 the high bit of the info field. Use this to decide if the function is
627 MIPS16 or normal MIPS. */
628 sym = lookup_minimal_symbol_by_pc (memaddr);
630 return MSYMBOL_IS_SPECIAL (sym);
635 /* MIPS believes that the PC has a sign extended value. Perhaphs the
636 all registers should be sign extended for simplicity? */
639 mips_read_pc (ptid_t ptid)
641 return read_signed_register_pid (PC_REGNUM, ptid);
644 /* This returns the PC of the first inst after the prologue. If we can't
645 find the prologue, then return 0. */
648 after_prologue (CORE_ADDR pc,
649 mips_extra_func_info_t proc_desc)
651 struct symtab_and_line sal;
652 CORE_ADDR func_addr, func_end;
654 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
655 to read the stack pointer from the current machine state, because
656 the current machine state has nothing to do with the information
657 we need from the proc_desc; and the process may or may not exist
660 proc_desc = find_proc_desc (pc, NULL, 0);
664 /* If function is frameless, then we need to do it the hard way. I
665 strongly suspect that frameless always means prologueless... */
666 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
667 && PROC_FRAME_OFFSET (proc_desc) == 0)
671 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
672 return 0; /* Unknown */
674 sal = find_pc_line (func_addr, 0);
676 if (sal.end < func_end)
679 /* The line after the prologue is after the end of the function. In this
680 case, tell the caller to find the prologue the hard way. */
685 /* Decode a MIPS32 instruction that saves a register in the stack, and
686 set the appropriate bit in the general register mask or float register mask
687 to indicate which register is saved. This is a helper function
688 for mips_find_saved_regs. */
691 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
692 unsigned long *float_mask)
696 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
697 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
698 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
700 /* It might be possible to use the instruction to
701 find the offset, rather than the code below which
702 is based on things being in a certain order in the
703 frame, but figuring out what the instruction's offset
704 is relative to might be a little tricky. */
705 reg = (inst & 0x001f0000) >> 16;
706 *gen_mask |= (1 << reg);
708 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
709 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
710 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
713 reg = ((inst & 0x001f0000) >> 16);
714 *float_mask |= (1 << reg);
718 /* Decode a MIPS16 instruction that saves a register in the stack, and
719 set the appropriate bit in the general register or float register mask
720 to indicate which register is saved. This is a helper function
721 for mips_find_saved_regs. */
724 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
726 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
728 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
729 *gen_mask |= (1 << reg);
731 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
733 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
734 *gen_mask |= (1 << reg);
736 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
737 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
738 *gen_mask |= (1 << RA_REGNUM);
742 /* Fetch and return instruction from the specified location. If the PC
743 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
746 mips_fetch_instruction (CORE_ADDR addr)
748 char buf[MIPS_INSTLEN];
752 if (pc_is_mips16 (addr))
754 instlen = MIPS16_INSTLEN;
755 addr = UNMAKE_MIPS16_ADDR (addr);
758 instlen = MIPS_INSTLEN;
759 status = read_memory_nobpt (addr, buf, instlen);
761 memory_error (status, addr);
762 return extract_unsigned_integer (buf, instlen);
766 /* These the fields of 32 bit mips instructions */
767 #define mips32_op(x) (x >> 26)
768 #define itype_op(x) (x >> 26)
769 #define itype_rs(x) ((x >> 21) & 0x1f)
770 #define itype_rt(x) ((x >> 16) & 0x1f)
771 #define itype_immediate(x) (x & 0xffff)
773 #define jtype_op(x) (x >> 26)
774 #define jtype_target(x) (x & 0x03ffffff)
776 #define rtype_op(x) (x >> 26)
777 #define rtype_rs(x) ((x >> 21) & 0x1f)
778 #define rtype_rt(x) ((x >> 16) & 0x1f)
779 #define rtype_rd(x) ((x >> 11) & 0x1f)
780 #define rtype_shamt(x) ((x >> 6) & 0x1f)
781 #define rtype_funct(x) (x & 0x3f)
784 mips32_relative_offset (unsigned long inst)
787 x = itype_immediate (inst);
788 if (x & 0x8000) /* sign bit set */
790 x |= 0xffff0000; /* sign extension */
796 /* Determine whate to set a single step breakpoint while considering
799 mips32_next_pc (CORE_ADDR pc)
803 inst = mips_fetch_instruction (pc);
804 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
806 if (itype_op (inst) >> 2 == 5)
807 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
809 op = (itype_op (inst) & 0x03);
824 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
825 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
827 int tf = itype_rt (inst) & 0x01;
828 int cnum = itype_rt (inst) >> 2;
829 int fcrcs = read_signed_register (FCRCS_REGNUM);
830 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
832 if (((cond >> cnum) & 0x01) == tf)
833 pc += mips32_relative_offset (inst) + 4;
838 pc += 4; /* Not a branch, next instruction is easy */
841 { /* This gets way messy */
843 /* Further subdivide into SPECIAL, REGIMM and other */
844 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
846 case 0: /* SPECIAL */
847 op = rtype_funct (inst);
852 /* Set PC to that address */
853 pc = read_signed_register (rtype_rs (inst));
859 break; /* end SPECIAL */
862 op = itype_rt (inst); /* branch condition */
867 case 16: /* BLTZAL */
868 case 18: /* BLTZALL */
870 if (read_signed_register (itype_rs (inst)) < 0)
871 pc += mips32_relative_offset (inst) + 4;
873 pc += 8; /* after the delay slot */
877 case 17: /* BGEZAL */
878 case 19: /* BGEZALL */
879 greater_equal_branch:
880 if (read_signed_register (itype_rs (inst)) >= 0)
881 pc += mips32_relative_offset (inst) + 4;
883 pc += 8; /* after the delay slot */
885 /* All of the other instructions in the REGIMM category */
890 break; /* end REGIMM */
895 reg = jtype_target (inst) << 2;
896 /* Upper four bits get never changed... */
897 pc = reg + ((pc + 4) & 0xf0000000);
900 /* FIXME case JALX : */
903 reg = jtype_target (inst) << 2;
904 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
905 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
907 break; /* The new PC will be alternate mode */
908 case 4: /* BEQ, BEQL */
910 if (read_signed_register (itype_rs (inst)) ==
911 read_signed_register (itype_rt (inst)))
912 pc += mips32_relative_offset (inst) + 4;
916 case 5: /* BNE, BNEL */
918 if (read_signed_register (itype_rs (inst)) !=
919 read_signed_register (itype_rt (inst)))
920 pc += mips32_relative_offset (inst) + 4;
924 case 6: /* BLEZ, BLEZL */
926 if (read_signed_register (itype_rs (inst) <= 0))
927 pc += mips32_relative_offset (inst) + 4;
933 greater_branch: /* BGTZ, BGTZL */
934 if (read_signed_register (itype_rs (inst) > 0))
935 pc += mips32_relative_offset (inst) + 4;
942 } /* mips32_next_pc */
944 /* Decoding the next place to set a breakpoint is irregular for the
945 mips 16 variant, but fortunately, there fewer instructions. We have to cope
946 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
947 We dont want to set a single step instruction on the extend instruction
951 /* Lots of mips16 instruction formats */
952 /* Predicting jumps requires itype,ritype,i8type
953 and their extensions extItype,extritype,extI8type
955 enum mips16_inst_fmts
957 itype, /* 0 immediate 5,10 */
958 ritype, /* 1 5,3,8 */
959 rrtype, /* 2 5,3,3,5 */
960 rritype, /* 3 5,3,3,5 */
961 rrrtype, /* 4 5,3,3,3,2 */
962 rriatype, /* 5 5,3,3,1,4 */
963 shifttype, /* 6 5,3,3,3,2 */
964 i8type, /* 7 5,3,8 */
965 i8movtype, /* 8 5,3,3,5 */
966 i8mov32rtype, /* 9 5,3,5,3 */
967 i64type, /* 10 5,3,8 */
968 ri64type, /* 11 5,3,3,5 */
969 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
970 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
971 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
972 extRRItype, /* 15 5,5,5,5,3,3,5 */
973 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
974 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
975 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
976 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
977 extRi64type, /* 20 5,6,5,5,3,3,5 */
978 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
980 /* I am heaping all the fields of the formats into one structure and
981 then, only the fields which are involved in instruction extension */
985 unsigned int regx; /* Function in i8 type */
990 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
991 for the bits which make up the immediatate extension. */
994 extended_offset (unsigned int extension)
997 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
999 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1001 value |= extension & 0x01f; /* extract 4:0 */
1005 /* Only call this function if you know that this is an extendable
1006 instruction, It wont malfunction, but why make excess remote memory references?
1007 If the immediate operands get sign extended or somthing, do it after
1008 the extension is performed.
1010 /* FIXME: Every one of these cases needs to worry about sign extension
1011 when the offset is to be used in relative addressing */
1015 fetch_mips_16 (CORE_ADDR pc)
1018 pc &= 0xfffffffe; /* clear the low order bit */
1019 target_read_memory (pc, buf, 2);
1020 return extract_unsigned_integer (buf, 2);
1024 unpack_mips16 (CORE_ADDR pc,
1025 unsigned int extension,
1027 enum mips16_inst_fmts insn_format,
1028 struct upk_mips16 *upk)
1033 switch (insn_format)
1040 value = extended_offset (extension);
1041 value = value << 11; /* rom for the original value */
1042 value |= inst & 0x7ff; /* eleven bits from instruction */
1046 value = inst & 0x7ff;
1047 /* FIXME : Consider sign extension */
1056 { /* A register identifier and an offset */
1057 /* Most of the fields are the same as I type but the
1058 immediate value is of a different length */
1062 value = extended_offset (extension);
1063 value = value << 8; /* from the original instruction */
1064 value |= inst & 0xff; /* eleven bits from instruction */
1065 regx = (extension >> 8) & 0x07; /* or i8 funct */
1066 if (value & 0x4000) /* test the sign bit , bit 26 */
1068 value &= ~0x3fff; /* remove the sign bit */
1074 value = inst & 0xff; /* 8 bits */
1075 regx = (inst >> 8) & 0x07; /* or i8 funct */
1076 /* FIXME: Do sign extension , this format needs it */
1077 if (value & 0x80) /* THIS CONFUSES ME */
1079 value &= 0xef; /* remove the sign bit */
1089 unsigned long value;
1090 unsigned int nexthalf;
1091 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1092 value = value << 16;
1093 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1101 internal_error (__FILE__, __LINE__,
1104 upk->offset = offset;
1111 add_offset_16 (CORE_ADDR pc, int offset)
1113 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1117 extended_mips16_next_pc (CORE_ADDR pc,
1118 unsigned int extension,
1121 int op = (insn >> 11);
1124 case 2: /* Branch */
1127 struct upk_mips16 upk;
1128 unpack_mips16 (pc, extension, insn, itype, &upk);
1129 offset = upk.offset;
1135 pc += (offset << 1) + 2;
1138 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1140 struct upk_mips16 upk;
1141 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1142 pc = add_offset_16 (pc, upk.offset);
1143 if ((insn >> 10) & 0x01) /* Exchange mode */
1144 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1151 struct upk_mips16 upk;
1153 unpack_mips16 (pc, extension, insn, ritype, &upk);
1154 reg = read_signed_register (upk.regx);
1156 pc += (upk.offset << 1) + 2;
1163 struct upk_mips16 upk;
1165 unpack_mips16 (pc, extension, insn, ritype, &upk);
1166 reg = read_signed_register (upk.regx);
1168 pc += (upk.offset << 1) + 2;
1173 case 12: /* I8 Formats btez btnez */
1175 struct upk_mips16 upk;
1177 unpack_mips16 (pc, extension, insn, i8type, &upk);
1178 /* upk.regx contains the opcode */
1179 reg = read_signed_register (24); /* Test register is 24 */
1180 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1181 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1182 /* pc = add_offset_16(pc,upk.offset) ; */
1183 pc += (upk.offset << 1) + 2;
1188 case 29: /* RR Formats JR, JALR, JALR-RA */
1190 struct upk_mips16 upk;
1191 /* upk.fmt = rrtype; */
1196 upk.regx = (insn >> 8) & 0x07;
1197 upk.regy = (insn >> 5) & 0x07;
1205 break; /* Function return instruction */
1211 break; /* BOGUS Guess */
1213 pc = read_signed_register (reg);
1220 /* This is an instruction extension. Fetch the real instruction
1221 (which follows the extension) and decode things based on
1225 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1238 mips16_next_pc (CORE_ADDR pc)
1240 unsigned int insn = fetch_mips_16 (pc);
1241 return extended_mips16_next_pc (pc, 0, insn);
1244 /* The mips_next_pc function supports single_step when the remote
1245 target monitor or stub is not developed enough to do a single_step.
1246 It works by decoding the current instruction and predicting where a
1247 branch will go. This isnt hard because all the data is available.
1248 The MIPS32 and MIPS16 variants are quite different */
1250 mips_next_pc (CORE_ADDR pc)
1253 return mips16_next_pc (pc);
1255 return mips32_next_pc (pc);
1258 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1261 Note: kevinb/2002-08-09: The only caller of this function is (and
1262 should remain) mips_frame_init_saved_regs(). In fact,
1263 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1264 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1265 functions should really be combined and now that there is only one
1266 caller, it should be straightforward. (Watch out for multiple returns
1270 mips_find_saved_regs (struct frame_info *fci)
1273 CORE_ADDR reg_position;
1274 /* r0 bit means kernel trap */
1276 /* What registers have been saved? Bitmasks. */
1277 unsigned long gen_mask, float_mask;
1278 mips_extra_func_info_t proc_desc;
1281 frame_saved_regs_zalloc (fci);
1283 /* If it is the frame for sigtramp, the saved registers are located
1284 in a sigcontext structure somewhere on the stack.
1285 If the stack layout for sigtramp changes we might have to change these
1286 constants and the companion fixup_sigtramp in mdebugread.c */
1287 #ifndef SIGFRAME_BASE
1288 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1289 above the sigtramp frame. */
1290 #define SIGFRAME_BASE MIPS_REGSIZE
1291 /* FIXME! Are these correct?? */
1292 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1293 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1294 #define SIGFRAME_FPREGSAVE_OFF \
1295 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1297 #ifndef SIGFRAME_REG_SIZE
1298 /* FIXME! Is this correct?? */
1299 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1301 if (fci->signal_handler_caller)
1303 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1305 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
1306 + ireg * SIGFRAME_REG_SIZE;
1307 fci->saved_regs[ireg] = reg_position;
1309 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1311 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
1312 + ireg * SIGFRAME_REG_SIZE;
1313 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1315 fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
1319 proc_desc = fci->extra_info->proc_desc;
1320 if (proc_desc == NULL)
1321 /* I'm not sure how/whether this can happen. Normally when we can't
1322 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1323 and set the saved_regs right away. */
1326 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1327 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1328 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1330 if ( /* In any frame other than the innermost or a frame interrupted by
1331 a signal, we assume that all registers have been saved.
1332 This assumes that all register saves in a function happen before
1333 the first function call. */
1334 (fci->next == NULL || fci->next->signal_handler_caller)
1336 /* In a dummy frame we know exactly where things are saved. */
1337 && !PROC_DESC_IS_DUMMY (proc_desc)
1339 /* Don't bother unless we are inside a function prologue. Outside the
1340 prologue, we know where everything is. */
1342 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
1344 /* Not sure exactly what kernel_trap means, but if it means
1345 the kernel saves the registers without a prologue doing it,
1346 we better not examine the prologue to see whether registers
1347 have been saved yet. */
1350 /* We need to figure out whether the registers that the proc_desc
1351 claims are saved have been saved yet. */
1355 /* Bitmasks; set if we have found a save for the register. */
1356 unsigned long gen_save_found = 0;
1357 unsigned long float_save_found = 0;
1360 /* If the address is odd, assume this is MIPS16 code. */
1361 addr = PROC_LOW_ADDR (proc_desc);
1362 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1364 /* Scan through this function's instructions preceding the current
1365 PC, and look for those that save registers. */
1366 while (addr < fci->pc)
1368 inst = mips_fetch_instruction (addr);
1369 if (pc_is_mips16 (addr))
1370 mips16_decode_reg_save (inst, &gen_save_found);
1372 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1375 gen_mask = gen_save_found;
1376 float_mask = float_save_found;
1379 /* Fill in the offsets for the registers which gen_mask says
1381 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1382 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1383 if (gen_mask & 0x80000000)
1385 fci->saved_regs[ireg] = reg_position;
1386 reg_position -= MIPS_SAVED_REGSIZE;
1389 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1390 of that normally used by gcc. Therefore, we have to fetch the first
1391 instruction of the function, and if it's an entry instruction that
1392 saves $s0 or $s1, correct their saved addresses. */
1393 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1395 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1396 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1399 int sreg_count = (inst >> 6) & 3;
1401 /* Check if the ra register was pushed on the stack. */
1402 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1404 reg_position -= MIPS_SAVED_REGSIZE;
1406 /* Check if the s0 and s1 registers were pushed on the stack. */
1407 for (reg = 16; reg < sreg_count + 16; reg++)
1409 fci->saved_regs[reg] = reg_position;
1410 reg_position -= MIPS_SAVED_REGSIZE;
1415 /* Fill in the offsets for the registers which float_mask says
1417 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
1419 /* Apparently, the freg_offset gives the offset to the first 64 bit
1422 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1423 designates the first saved 64 bit register.
1425 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1426 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1427 FREG_OFFSET, designates the address of the lower register of the
1428 register pair. Adjust the offset so that it designates the upper
1429 register of the pair -- i.e., the address of the first saved 32
1432 if (MIPS_SAVED_REGSIZE == 4)
1433 reg_position += MIPS_SAVED_REGSIZE;
1435 /* Fill in the offsets for the float registers which float_mask says
1437 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1438 if (float_mask & 0x80000000)
1440 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1441 reg_position -= MIPS_SAVED_REGSIZE;
1444 fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM];
1447 /* Set up the 'saved_regs' array. This is a data structure containing
1448 the addresses on the stack where each register has been saved, for
1449 each stack frame. Registers that have not been saved will have
1450 zero here. The stack pointer register is special: rather than the
1451 address where the stack register has been saved, saved_regs[SP_REGNUM]
1452 will have the actual value of the previous frame's stack register. */
1455 mips_frame_init_saved_regs (struct frame_info *frame)
1457 if (frame->saved_regs == NULL)
1459 mips_find_saved_regs (frame);
1461 frame->saved_regs[SP_REGNUM] = frame->frame;
1465 read_next_frame_reg (struct frame_info *fi, int regno)
1467 for (; fi; fi = fi->next)
1469 /* We have to get the saved sp from the sigcontext
1470 if it is a signal handler frame. */
1471 if (regno == SP_REGNUM && !fi->signal_handler_caller)
1475 if (fi->saved_regs == NULL)
1476 FRAME_INIT_SAVED_REGS (fi);
1477 if (fi->saved_regs[regno])
1478 return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE);
1481 return read_signed_register (regno);
1484 /* mips_addr_bits_remove - remove useless address bits */
1487 mips_addr_bits_remove (CORE_ADDR addr)
1489 if (GDB_TARGET_IS_MIPS64)
1491 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1493 /* This hack is a work-around for existing boards using
1494 PMON, the simulator, and any other 64-bit targets that
1495 doesn't have true 64-bit addressing. On these targets,
1496 the upper 32 bits of addresses are ignored by the
1497 hardware. Thus, the PC or SP are likely to have been
1498 sign extended to all 1s by instruction sequences that
1499 load 32-bit addresses. For example, a typical piece of
1500 code that loads an address is this:
1501 lui $r2, <upper 16 bits>
1502 ori $r2, <lower 16 bits>
1503 But the lui sign-extends the value such that the upper 32
1504 bits may be all 1s. The workaround is simply to mask off
1505 these bits. In the future, gcc may be changed to support
1506 true 64-bit addressing, and this masking will have to be
1508 addr &= (CORE_ADDR) 0xffffffff;
1511 else if (mips_mask_address_p ())
1513 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1514 masking off bits, instead, the actual target should be asking
1515 for the address to be converted to a valid pointer. */
1516 /* Even when GDB is configured for some 32-bit targets
1517 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1518 so CORE_ADDR is 64 bits. So we still have to mask off
1519 useless bits from addresses. */
1520 addr &= (CORE_ADDR) 0xffffffff;
1525 /* mips_software_single_step() is called just before we want to resume
1526 the inferior, if we want to single-step it but there is no hardware
1527 or kernel single-step support (MIPS on GNU/Linux for example). We find
1528 the target of the coming instruction and breakpoint it.
1530 single_step is also called just after the inferior stops. If we had
1531 set up a simulated single-step, we undo our damage. */
1534 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1536 static CORE_ADDR next_pc;
1537 typedef char binsn_quantum[BREAKPOINT_MAX];
1538 static binsn_quantum break_mem;
1541 if (insert_breakpoints_p)
1543 pc = read_register (PC_REGNUM);
1544 next_pc = mips_next_pc (pc);
1546 target_insert_breakpoint (next_pc, break_mem);
1549 target_remove_breakpoint (next_pc, break_mem);
1553 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1557 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
1558 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
1559 tmp = mips_skip_stub (pc);
1560 prev->pc = tmp ? tmp : pc;
1565 mips_frame_saved_pc (struct frame_info *frame)
1568 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
1569 /* We have to get the saved pc from the sigcontext
1570 if it is a signal handler frame. */
1571 int pcreg = frame->signal_handler_caller ? PC_REGNUM
1572 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1574 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1575 saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1577 saved_pc = read_next_frame_reg (frame, pcreg);
1579 return ADDR_BITS_REMOVE (saved_pc);
1582 static struct mips_extra_func_info temp_proc_desc;
1583 static CORE_ADDR temp_saved_regs[NUM_REGS];
1585 /* Set a register's saved stack address in temp_saved_regs. If an address
1586 has already been set for this register, do nothing; this way we will
1587 only recognize the first save of a given register in a function prologue.
1588 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1591 set_reg_offset (int regno, CORE_ADDR offset)
1593 if (temp_saved_regs[regno] == 0)
1594 temp_saved_regs[regno] = offset;
1598 /* Test whether the PC points to the return instruction at the
1599 end of a function. */
1602 mips_about_to_return (CORE_ADDR pc)
1604 if (pc_is_mips16 (pc))
1605 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1606 generates a "jr $ra"; other times it generates code to load
1607 the return address from the stack to an accessible register (such
1608 as $a3), then a "jr" using that register. This second case
1609 is almost impossible to distinguish from an indirect jump
1610 used for switch statements, so we don't even try. */
1611 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1613 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1617 /* This fencepost looks highly suspicious to me. Removing it also
1618 seems suspicious as it could affect remote debugging across serial
1622 heuristic_proc_start (CORE_ADDR pc)
1629 pc = ADDR_BITS_REMOVE (pc);
1631 fence = start_pc - heuristic_fence_post;
1635 if (heuristic_fence_post == UINT_MAX
1636 || fence < VM_MIN_ADDRESS)
1637 fence = VM_MIN_ADDRESS;
1639 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1641 /* search back for previous return */
1642 for (start_pc -= instlen;; start_pc -= instlen)
1643 if (start_pc < fence)
1645 /* It's not clear to me why we reach this point when
1646 stop_soon_quietly, but with this test, at least we
1647 don't print out warnings for every child forked (eg, on
1648 decstation). 22apr93 rich@cygnus.com. */
1649 if (!stop_soon_quietly)
1651 static int blurb_printed = 0;
1653 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1658 /* This actually happens frequently in embedded
1659 development, when you first connect to a board
1660 and your stack pointer and pc are nowhere in
1661 particular. This message needs to give people
1662 in that situation enough information to
1663 determine that it's no big deal. */
1664 printf_filtered ("\n\
1665 GDB is unable to find the start of the function at 0x%s\n\
1666 and thus can't determine the size of that function's stack frame.\n\
1667 This means that GDB may be unable to access that stack frame, or\n\
1668 the frames below it.\n\
1669 This problem is most likely caused by an invalid program counter or\n\
1671 However, if you think GDB should simply search farther back\n\
1672 from 0x%s for code which looks like the beginning of a\n\
1673 function, you can increase the range of the search using the `set\n\
1674 heuristic-fence-post' command.\n",
1675 paddr_nz (pc), paddr_nz (pc));
1682 else if (pc_is_mips16 (start_pc))
1684 unsigned short inst;
1686 /* On MIPS16, any one of the following is likely to be the
1687 start of a function:
1691 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1692 inst = mips_fetch_instruction (start_pc);
1693 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1694 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1695 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1696 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1698 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1699 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1704 else if (mips_about_to_return (start_pc))
1706 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1713 /* Fetch the immediate value from a MIPS16 instruction.
1714 If the previous instruction was an EXTEND, use it to extend
1715 the upper bits of the immediate value. This is a helper function
1716 for mips16_heuristic_proc_desc. */
1719 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1720 unsigned short inst, /* current instruction */
1721 int nbits, /* number of bits in imm field */
1722 int scale, /* scale factor to be applied to imm */
1723 int is_signed) /* is the imm field signed? */
1727 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1729 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1730 if (offset & 0x8000) /* check for negative extend */
1731 offset = 0 - (0x10000 - (offset & 0xffff));
1732 return offset | (inst & 0x1f);
1736 int max_imm = 1 << nbits;
1737 int mask = max_imm - 1;
1738 int sign_bit = max_imm >> 1;
1740 offset = inst & mask;
1741 if (is_signed && (offset & sign_bit))
1742 offset = 0 - (max_imm - offset);
1743 return offset * scale;
1748 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1749 stream from start_pc to limit_pc. */
1752 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1753 struct frame_info *next_frame, CORE_ADDR sp)
1756 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1757 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1758 unsigned inst = 0; /* current instruction */
1759 unsigned entry_inst = 0; /* the entry instruction */
1762 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1763 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1765 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1767 /* Save the previous instruction. If it's an EXTEND, we'll extract
1768 the immediate offset extension from it in mips16_get_imm. */
1771 /* Fetch and decode the instruction. */
1772 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1773 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1774 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1776 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1777 if (offset < 0) /* negative stack adjustment? */
1778 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
1780 /* Exit loop if a positive stack adjustment is found, which
1781 usually means that the stack cleanup code in the function
1782 epilogue is reached. */
1785 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1787 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1788 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1789 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1790 set_reg_offset (reg, sp + offset);
1792 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1794 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1795 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1796 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1797 set_reg_offset (reg, sp + offset);
1799 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1801 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1802 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1803 set_reg_offset (RA_REGNUM, sp + offset);
1805 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1807 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1808 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1809 set_reg_offset (RA_REGNUM, sp + offset);
1811 else if (inst == 0x673d) /* move $s1, $sp */
1814 PROC_FRAME_REG (&temp_proc_desc) = 17;
1816 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1818 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1819 frame_addr = sp + offset;
1820 PROC_FRAME_REG (&temp_proc_desc) = 17;
1821 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1823 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1825 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1826 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1827 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1828 set_reg_offset (reg, frame_addr + offset);
1830 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1832 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1833 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1834 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1835 set_reg_offset (reg, frame_addr + offset);
1837 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1838 entry_inst = inst; /* save for later processing */
1839 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1840 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
1843 /* The entry instruction is typically the first instruction in a function,
1844 and it stores registers at offsets relative to the value of the old SP
1845 (before the prologue). But the value of the sp parameter to this
1846 function is the new SP (after the prologue has been executed). So we
1847 can't calculate those offsets until we've seen the entire prologue,
1848 and can calculate what the old SP must have been. */
1849 if (entry_inst != 0)
1851 int areg_count = (entry_inst >> 8) & 7;
1852 int sreg_count = (entry_inst >> 6) & 3;
1854 /* The entry instruction always subtracts 32 from the SP. */
1855 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
1857 /* Now we can calculate what the SP must have been at the
1858 start of the function prologue. */
1859 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
1861 /* Check if a0-a3 were saved in the caller's argument save area. */
1862 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1864 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1865 set_reg_offset (reg, sp + offset);
1866 offset += MIPS_SAVED_REGSIZE;
1869 /* Check if the ra register was pushed on the stack. */
1871 if (entry_inst & 0x20)
1873 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
1874 set_reg_offset (RA_REGNUM, sp + offset);
1875 offset -= MIPS_SAVED_REGSIZE;
1878 /* Check if the s0 and s1 registers were pushed on the stack. */
1879 for (reg = 16; reg < sreg_count + 16; reg++)
1881 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1882 set_reg_offset (reg, sp + offset);
1883 offset -= MIPS_SAVED_REGSIZE;
1889 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1890 struct frame_info *next_frame, CORE_ADDR sp)
1893 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1895 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
1896 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
1897 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1898 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
1900 unsigned long inst, high_word, low_word;
1903 /* Fetch the instruction. */
1904 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1906 /* Save some code by pre-extracting some useful fields. */
1907 high_word = (inst >> 16) & 0xffff;
1908 low_word = inst & 0xffff;
1909 reg = high_word & 0x1f;
1911 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1912 || high_word == 0x23bd /* addi $sp,$sp,-i */
1913 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1915 if (low_word & 0x8000) /* negative stack adjustment? */
1916 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
1918 /* Exit loop if a positive stack adjustment is found, which
1919 usually means that the stack cleanup code in the function
1920 epilogue is reached. */
1923 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1925 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1926 set_reg_offset (reg, sp + low_word);
1928 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1930 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1931 but the register size used is only 32 bits. Make the address
1932 for the saved register point to the lower 32 bits. */
1933 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1934 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
1936 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1938 /* Old gcc frame, r30 is virtual frame pointer. */
1939 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
1940 frame_addr = sp + low_word;
1941 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1943 unsigned alloca_adjust;
1944 PROC_FRAME_REG (&temp_proc_desc) = 30;
1945 frame_addr = read_next_frame_reg (next_frame, 30);
1946 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1947 if (alloca_adjust > 0)
1949 /* FP > SP + frame_size. This may be because
1950 * of an alloca or somethings similar.
1951 * Fix sp to "pre-alloca" value, and try again.
1953 sp += alloca_adjust;
1958 /* move $30,$sp. With different versions of gas this will be either
1959 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1960 Accept any one of these. */
1961 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1963 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1964 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1966 unsigned alloca_adjust;
1967 PROC_FRAME_REG (&temp_proc_desc) = 30;
1968 frame_addr = read_next_frame_reg (next_frame, 30);
1969 alloca_adjust = (unsigned) (frame_addr - sp);
1970 if (alloca_adjust > 0)
1972 /* FP > SP + frame_size. This may be because
1973 * of an alloca or somethings similar.
1974 * Fix sp to "pre-alloca" value, and try again.
1976 sp += alloca_adjust;
1981 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1983 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1984 set_reg_offset (reg, frame_addr + low_word);
1989 static mips_extra_func_info_t
1990 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1991 struct frame_info *next_frame, int cur_frame)
1996 sp = read_next_frame_reg (next_frame, SP_REGNUM);
2002 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2003 memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2004 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2005 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2006 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2008 if (start_pc + 200 < limit_pc)
2009 limit_pc = start_pc + 200;
2010 if (pc_is_mips16 (start_pc))
2011 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2013 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2014 return &temp_proc_desc;
2017 struct mips_objfile_private
2023 /* Global used to communicate between non_heuristic_proc_desc and
2024 compare_pdr_entries within qsort (). */
2025 static bfd *the_bfd;
2028 compare_pdr_entries (const void *a, const void *b)
2030 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2031 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2035 else if (lhs == rhs)
2041 static mips_extra_func_info_t
2042 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2044 CORE_ADDR startaddr;
2045 mips_extra_func_info_t proc_desc;
2046 struct block *b = block_for_pc (pc);
2048 struct obj_section *sec;
2049 struct mips_objfile_private *priv;
2051 if (PC_IN_CALL_DUMMY (pc, 0, 0))
2054 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2056 *addrptr = startaddr;
2060 sec = find_pc_section (pc);
2063 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2065 /* Search the ".pdr" section generated by GAS. This includes most of
2066 the information normally found in ECOFF PDRs. */
2068 the_bfd = sec->objfile->obfd;
2070 && (the_bfd->format == bfd_object
2071 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2072 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2074 /* Right now GAS only outputs the address as a four-byte sequence.
2075 This means that we should not bother with this method on 64-bit
2076 targets (until that is fixed). */
2078 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2079 sizeof (struct mips_objfile_private));
2081 sec->objfile->obj_private = priv;
2083 else if (priv == NULL)
2087 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2088 sizeof (struct mips_objfile_private));
2090 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2093 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2094 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2096 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2097 priv->contents, 0, priv->size);
2099 /* In general, the .pdr section is sorted. However, in the
2100 presence of multiple code sections (and other corner cases)
2101 it can become unsorted. Sort it so that we can use a faster
2103 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2108 sec->objfile->obj_private = priv;
2112 if (priv->size != 0)
2118 high = priv->size / 32;
2124 mid = (low + high) / 2;
2126 ptr = priv->contents + mid * 32;
2127 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2128 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2129 SECT_OFF_TEXT (sec->objfile));
2130 if (pdr_pc == startaddr)
2132 if (pdr_pc > startaddr)
2137 while (low != high);
2141 struct symbol *sym = find_pc_function (pc);
2143 /* Fill in what we need of the proc_desc. */
2144 proc_desc = (mips_extra_func_info_t)
2145 obstack_alloc (&sec->objfile->psymbol_obstack,
2146 sizeof (struct mips_extra_func_info));
2147 PROC_LOW_ADDR (proc_desc) = startaddr;
2149 /* Only used for dummy frames. */
2150 PROC_HIGH_ADDR (proc_desc) = 0;
2152 PROC_FRAME_OFFSET (proc_desc)
2153 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2154 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2156 PROC_FRAME_ADJUST (proc_desc) = 0;
2157 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2159 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2161 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2163 PROC_FREG_OFFSET (proc_desc)
2164 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2165 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2167 proc_desc->pdr.isym = (long) sym;
2177 if (startaddr > BLOCK_START (b))
2179 /* This is the "pathological" case referred to in a comment in
2180 print_frame_info. It might be better to move this check into
2185 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
2187 /* If we never found a PDR for this function in symbol reading, then
2188 examine prologues to find the information. */
2191 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2192 if (PROC_FRAME_REG (proc_desc) == -1)
2202 static mips_extra_func_info_t
2203 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2205 mips_extra_func_info_t proc_desc;
2206 CORE_ADDR startaddr;
2208 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2212 /* IF this is the topmost frame AND
2213 * (this proc does not have debugging information OR
2214 * the PC is in the procedure prologue)
2215 * THEN create a "heuristic" proc_desc (by analyzing
2216 * the actual code) to replace the "official" proc_desc.
2218 if (next_frame == NULL)
2220 struct symtab_and_line val;
2221 struct symbol *proc_symbol =
2222 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2226 val = find_pc_line (BLOCK_START
2227 (SYMBOL_BLOCK_VALUE (proc_symbol)),
2229 val.pc = val.end ? val.end : pc;
2231 if (!proc_symbol || pc < val.pc)
2233 mips_extra_func_info_t found_heuristic =
2234 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2235 pc, next_frame, cur_frame);
2236 if (found_heuristic)
2237 proc_desc = found_heuristic;
2243 /* Is linked_proc_desc_table really necessary? It only seems to be used
2244 by procedure call dummys. However, the procedures being called ought
2245 to have their own proc_descs, and even if they don't,
2246 heuristic_proc_desc knows how to create them! */
2248 register struct linked_proc_info *link;
2250 for (link = linked_proc_desc_table; link; link = link->next)
2251 if (PROC_LOW_ADDR (&link->info) <= pc
2252 && PROC_HIGH_ADDR (&link->info) > pc)
2256 startaddr = heuristic_proc_start (pc);
2259 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2265 get_frame_pointer (struct frame_info *frame,
2266 mips_extra_func_info_t proc_desc)
2268 return ADDR_BITS_REMOVE (read_next_frame_reg (frame,
2269 PROC_FRAME_REG (proc_desc)) +
2270 PROC_FRAME_OFFSET (proc_desc) -
2271 PROC_FRAME_ADJUST (proc_desc));
2274 mips_extra_func_info_t cached_proc_desc;
2277 mips_frame_chain (struct frame_info *frame)
2279 mips_extra_func_info_t proc_desc;
2281 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
2283 if (saved_pc == 0 || inside_entry_file (saved_pc))
2286 /* Check if the PC is inside a call stub. If it is, fetch the
2287 PC of the caller of that stub. */
2288 if ((tmp = mips_skip_stub (saved_pc)) != 0)
2291 /* Look up the procedure descriptor for this PC. */
2292 proc_desc = find_proc_desc (saved_pc, frame, 1);
2296 cached_proc_desc = proc_desc;
2298 /* If no frame pointer and frame size is zero, we must be at end
2299 of stack (or otherwise hosed). If we don't check frame size,
2300 we loop forever if we see a zero size frame. */
2301 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2302 && PROC_FRAME_OFFSET (proc_desc) == 0
2303 /* The previous frame from a sigtramp frame might be frameless
2304 and have frame size zero. */
2305 && !frame->signal_handler_caller)
2308 return get_frame_pointer (frame, proc_desc);
2312 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2316 /* Use proc_desc calculated in frame_chain */
2317 mips_extra_func_info_t proc_desc =
2318 fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1);
2320 fci->extra_info = (struct frame_extra_info *)
2321 frame_obstack_alloc (sizeof (struct frame_extra_info));
2323 fci->saved_regs = NULL;
2324 fci->extra_info->proc_desc =
2325 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2328 /* Fixup frame-pointer - only needed for top frame */
2329 /* This may not be quite right, if proc has a real frame register.
2330 Get the value of the frame relative sp, procedure might have been
2331 interrupted by a signal at it's very start. */
2332 if (fci->pc == PROC_LOW_ADDR (proc_desc)
2333 && !PROC_DESC_IS_DUMMY (proc_desc))
2334 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
2336 fci->frame = get_frame_pointer (fci->next, proc_desc);
2338 if (proc_desc == &temp_proc_desc)
2342 /* Do not set the saved registers for a sigtramp frame,
2343 mips_find_saved_registers will do that for us.
2344 We can't use fci->signal_handler_caller, it is not yet set. */
2345 find_pc_partial_function (fci->pc, &name,
2346 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2347 if (!PC_IN_SIGTRAMP (fci->pc, name))
2349 frame_saved_regs_zalloc (fci);
2350 memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2351 fci->saved_regs[PC_REGNUM]
2352 = fci->saved_regs[RA_REGNUM];
2353 /* Set value of previous frame's stack pointer. Remember that
2354 saved_regs[SP_REGNUM] is special in that it contains the
2355 value of the stack pointer register. The other saved_regs
2356 values are addresses (in the inferior) at which a given
2357 register's value may be found. */
2358 fci->saved_regs[SP_REGNUM] = fci->frame;
2362 /* hack: if argument regs are saved, guess these contain args */
2363 /* assume we can't tell how many args for now */
2364 fci->extra_info->num_args = -1;
2365 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2367 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2369 fci->extra_info->num_args = regnum - A0_REGNUM + 1;
2376 /* MIPS stack frames are almost impenetrable. When execution stops,
2377 we basically have to look at symbol information for the function
2378 that we stopped in, which tells us *which* register (if any) is
2379 the base of the frame pointer, and what offset from that register
2380 the frame itself is at.
2382 This presents a problem when trying to examine a stack in memory
2383 (that isn't executing at the moment), using the "frame" command. We
2384 don't have a PC, nor do we have any registers except SP.
2386 This routine takes two arguments, SP and PC, and tries to make the
2387 cached frames look as if these two arguments defined a frame on the
2388 cache. This allows the rest of info frame to extract the important
2389 arguments without difficulty. */
2392 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2395 error ("MIPS frame specifications require two arguments: sp and pc");
2397 return create_new_frame (argv[0], argv[1]);
2400 /* According to the current ABI, should the type be passed in a
2401 floating-point register (assuming that there is space)? When there
2402 is no FPU, FP are not even considered as possibile candidates for
2403 FP registers and, consequently this returns false - forces FP
2404 arguments into integer registers. */
2407 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2409 return ((typecode == TYPE_CODE_FLT
2411 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2412 && TYPE_NFIELDS (arg_type) == 1
2413 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2414 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2417 /* On o32, argument passing in GPRs depends on the alignment of the type being
2418 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2421 mips_type_needs_double_align (struct type *type)
2423 enum type_code typecode = TYPE_CODE (type);
2425 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2427 else if (typecode == TYPE_CODE_STRUCT)
2429 if (TYPE_NFIELDS (type) < 1)
2431 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2433 else if (typecode == TYPE_CODE_UNION)
2437 n = TYPE_NFIELDS (type);
2438 for (i = 0; i < n; i++)
2439 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2447 mips_push_arguments (int nargs,
2448 struct value **args,
2451 CORE_ADDR struct_addr)
2457 int stack_offset = 0;
2458 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2460 /* Macros to round N up or down to the next A boundary; A must be
2462 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2463 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2465 /* First ensure that the stack and structure return address (if any)
2466 are properly aligned. The stack has to be at least 64-bit aligned
2467 even on 32-bit machines, because doubles must be 64-bit aligned.
2468 On at least one MIPS variant, stack frames need to be 128-bit
2469 aligned, so we round to this widest known alignment. */
2470 sp = ROUND_DOWN (sp, 16);
2471 struct_addr = ROUND_DOWN (struct_addr, 16);
2473 /* Now make space on the stack for the args. We allocate more
2474 than necessary for EABI, because the first few arguments are
2475 passed in registers, but that's OK. */
2476 for (argnum = 0; argnum < nargs; argnum++)
2477 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_STACK_ARGSIZE);
2478 sp -= ROUND_UP (len, 16);
2481 fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n",
2482 (long) sp, ROUND_UP (len, 16));
2484 /* Initialize the integer and float register pointers. */
2486 float_argreg = FPA0_REGNUM;
2488 /* the struct_return pointer occupies the first parameter-passing reg */
2492 fprintf_unfiltered (gdb_stdlog,
2493 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2494 argreg, (long) struct_addr);
2495 write_register (argreg++, struct_addr);
2496 if (MIPS_REGS_HAVE_HOME_P)
2497 stack_offset += MIPS_STACK_ARGSIZE;
2500 /* Now load as many as possible of the first arguments into
2501 registers, and push the rest onto the stack. Loop thru args
2502 from first to last. */
2503 for (argnum = 0; argnum < nargs; argnum++)
2506 char valbuf[MAX_REGISTER_RAW_SIZE];
2507 struct value *arg = args[argnum];
2508 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2509 int len = TYPE_LENGTH (arg_type);
2510 enum type_code typecode = TYPE_CODE (arg_type);
2513 fprintf_unfiltered (gdb_stdlog,
2514 "mips_push_arguments: %d len=%d type=%d",
2515 argnum + 1, len, (int) typecode);
2517 /* The EABI passes structures that do not fit in a register by
2518 reference. In all other cases, pass the structure by value. */
2520 && len > MIPS_SAVED_REGSIZE
2521 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2523 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2524 typecode = TYPE_CODE_PTR;
2525 len = MIPS_SAVED_REGSIZE;
2528 fprintf_unfiltered (gdb_stdlog, " push");
2531 val = (char *) VALUE_CONTENTS (arg);
2533 /* 32-bit ABIs always start floating point arguments in an
2534 even-numbered floating point register. Round the FP register
2535 up before the check to see if there are any FP registers
2536 left. Non MIPS_EABI targets also pass the FP in the integer
2537 registers so also round up normal registers. */
2538 if (!FP_REGISTER_DOUBLE
2539 && fp_register_arg_p (typecode, arg_type))
2541 if ((float_argreg & 1))
2545 /* Floating point arguments passed in registers have to be
2546 treated specially. On 32-bit architectures, doubles
2547 are passed in register pairs; the even register gets
2548 the low word, and the odd register gets the high word.
2549 On non-EABI processors, the first two floating point arguments are
2550 also copied to general registers, because MIPS16 functions
2551 don't use float registers for arguments. This duplication of
2552 arguments in general registers can't hurt non-MIPS16 functions
2553 because those registers are normally skipped. */
2554 /* MIPS_EABI squeezes a struct that contains a single floating
2555 point value into an FP register instead of pushing it onto the
2557 if (fp_register_arg_p (typecode, arg_type)
2558 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2560 if (!FP_REGISTER_DOUBLE && len == 8)
2562 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2563 unsigned long regval;
2565 /* Write the low word of the double to the even register(s). */
2566 regval = extract_unsigned_integer (val + low_offset, 4);
2568 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2569 float_argreg, phex (regval, 4));
2570 write_register (float_argreg++, regval);
2574 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2575 argreg, phex (regval, 4));
2576 write_register (argreg++, regval);
2579 /* Write the high word of the double to the odd register(s). */
2580 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2582 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2583 float_argreg, phex (regval, 4));
2584 write_register (float_argreg++, regval);
2588 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2589 argreg, phex (regval, 4));
2590 write_register (argreg++, regval);
2596 /* This is a floating point value that fits entirely
2597 in a single register. */
2598 /* On 32 bit ABI's the float_argreg is further adjusted
2599 above to ensure that it is even register aligned. */
2600 LONGEST regval = extract_unsigned_integer (val, len);
2602 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2603 float_argreg, phex (regval, len));
2604 write_register (float_argreg++, regval);
2607 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2608 registers for each argument. The below is (my
2609 guess) to ensure that the corresponding integer
2610 register has reserved the same space. */
2612 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2613 argreg, phex (regval, len));
2614 write_register (argreg, regval);
2615 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
2618 /* Reserve space for the FP register. */
2619 if (MIPS_REGS_HAVE_HOME_P)
2620 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
2624 /* Copy the argument to general registers or the stack in
2625 register-sized pieces. Large arguments are split between
2626 registers and stack. */
2627 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2628 are treated specially: Irix cc passes them in registers
2629 where gcc sometimes puts them on the stack. For maximum
2630 compatibility, we will put them in both places. */
2631 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2632 (len % MIPS_SAVED_REGSIZE != 0));
2633 /* Structures should be aligned to eight bytes (even arg registers)
2634 on MIPS_ABI_O32 if their first member has double precision. */
2635 if (tdep->mips_abi == MIPS_ABI_O32
2636 && mips_type_needs_double_align (arg_type))
2641 /* Note: Floating-point values that didn't fit into an FP
2642 register are only written to memory. */
2645 /* Rememer if the argument was written to the stack. */
2646 int stack_used_p = 0;
2647 int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2650 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2653 /* Write this portion of the argument to the stack. */
2654 if (argreg > MIPS_LAST_ARG_REGNUM
2656 || fp_register_arg_p (typecode, arg_type))
2658 /* Should shorter than int integer values be
2659 promoted to int before being stored? */
2660 int longword_offset = 0;
2663 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2665 if (MIPS_STACK_ARGSIZE == 8 &&
2666 (typecode == TYPE_CODE_INT ||
2667 typecode == TYPE_CODE_PTR ||
2668 typecode == TYPE_CODE_FLT) && len <= 4)
2669 longword_offset = MIPS_STACK_ARGSIZE - len;
2670 else if ((typecode == TYPE_CODE_STRUCT ||
2671 typecode == TYPE_CODE_UNION) &&
2672 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2673 longword_offset = MIPS_STACK_ARGSIZE - len;
2678 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%lx",
2679 (long) stack_offset);
2680 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx",
2681 (long) longword_offset);
2684 addr = sp + stack_offset + longword_offset;
2689 fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr);
2690 for (i = 0; i < partial_len; i++)
2692 fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff);
2695 write_memory (addr, val, partial_len);
2698 /* Note!!! This is NOT an else clause. Odd sized
2699 structs may go thru BOTH paths. Floating point
2700 arguments will not. */
2701 /* Write this portion of the argument to a general
2702 purpose register. */
2703 if (argreg <= MIPS_LAST_ARG_REGNUM
2704 && !fp_register_arg_p (typecode, arg_type))
2706 LONGEST regval = extract_unsigned_integer (val, partial_len);
2708 /* A non-floating-point argument being passed in a
2709 general register. If a struct or union, and if
2710 the remaining length is smaller than the register
2711 size, we have to adjust the register value on
2714 It does not seem to be necessary to do the
2715 same for integral types.
2717 Also don't do this adjustment on EABI and O64
2720 cagney/2001-07-23: gdb/179: Also, GCC, when
2721 outputting LE O32 with sizeof (struct) <
2722 MIPS_SAVED_REGSIZE, generates a left shift as
2723 part of storing the argument in a register a
2724 register (the left shift isn't generated when
2725 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2726 is quite possible that this is GCC contradicting
2727 the LE/O32 ABI, GDB has not been adjusted to
2728 accommodate this. Either someone needs to
2729 demonstrate that the LE/O32 ABI specifies such a
2730 left shift OR this new ABI gets identified as
2731 such and GDB gets tweaked accordingly. */
2734 && MIPS_SAVED_REGSIZE < 8
2735 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2736 && partial_len < MIPS_SAVED_REGSIZE
2737 && (typecode == TYPE_CODE_STRUCT ||
2738 typecode == TYPE_CODE_UNION))
2739 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
2743 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2745 phex (regval, MIPS_SAVED_REGSIZE));
2746 write_register (argreg, regval);
2749 /* If this is the old ABI, prevent subsequent floating
2750 point arguments from being passed in floating point
2753 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
2759 /* Compute the the offset into the stack at which we
2760 will copy the next parameter.
2762 In older ABIs, the caller reserved space for
2763 registers that contained arguments. This was loosely
2764 refered to as their "home". Consequently, space is
2767 In the new EABI (and the NABI32), the stack_offset
2768 only needs to be adjusted when it has been used.. */
2770 if (MIPS_REGS_HAVE_HOME_P || stack_used_p)
2771 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2775 fprintf_unfiltered (gdb_stdlog, "\n");
2778 /* Return adjusted stack pointer. */
2783 mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2785 /* Set the return address register to point to the entry
2786 point of the program, where a breakpoint lies in wait. */
2787 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
2792 mips_push_register (CORE_ADDR * sp, int regno)
2794 char buffer[MAX_REGISTER_RAW_SIZE];
2797 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
2799 regsize = MIPS_SAVED_REGSIZE;
2800 offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2801 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
2806 regsize = REGISTER_RAW_SIZE (regno);
2810 read_register_gen (regno, buffer);
2811 write_memory (*sp, buffer + offset, regsize);
2814 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2815 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2818 mips_push_dummy_frame (void)
2821 struct linked_proc_info *link = (struct linked_proc_info *)
2822 xmalloc (sizeof (struct linked_proc_info));
2823 mips_extra_func_info_t proc_desc = &link->info;
2824 CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
2825 CORE_ADDR old_sp = sp;
2826 link->next = linked_proc_desc_table;
2827 linked_proc_desc_table = link;
2829 /* FIXME! are these correct ? */
2830 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2831 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2832 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2833 #define FLOAT_SINGLE_REG_SAVE_MASK \
2834 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2836 * The registers we must save are all those not preserved across
2837 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2838 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2839 * and FP Control/Status registers.
2842 * Dummy frame layout:
2845 * Saved MMHI, MMLO, FPC_CSR
2850 * Saved D18 (i.e. F19, F18)
2852 * Saved D0 (i.e. F1, F0)
2853 * Argument build area and stack arguments written via mips_push_arguments
2857 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2858 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
2859 PROC_FRAME_OFFSET (proc_desc) = 0;
2860 PROC_FRAME_ADJUST (proc_desc) = 0;
2861 mips_push_register (&sp, PC_REGNUM);
2862 mips_push_register (&sp, HI_REGNUM);
2863 mips_push_register (&sp, LO_REGNUM);
2864 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
2866 /* Save general CPU registers */
2867 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
2868 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2869 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
2870 for (ireg = 32; --ireg >= 0;)
2871 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
2872 mips_push_register (&sp, ireg);
2874 /* Save floating point registers starting with high order word */
2875 PROC_FREG_MASK (proc_desc) =
2876 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
2877 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
2878 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2880 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
2881 for (ireg = 32; --ireg >= 0;)
2882 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
2883 mips_push_register (&sp, ireg + FP0_REGNUM);
2885 /* Update the frame pointer for the call dummy and the stack pointer.
2886 Set the procedure's starting and ending addresses to point to the
2887 call dummy address at the entry point. */
2888 write_register (PUSH_FP_REGNUM, old_sp);
2889 write_register (SP_REGNUM, sp);
2890 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
2891 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
2892 SET_PROC_DESC_IS_DUMMY (proc_desc);
2893 PROC_PC_REG (proc_desc) = RA_REGNUM;
2897 mips_pop_frame (void)
2899 register int regnum;
2900 struct frame_info *frame = get_current_frame ();
2901 CORE_ADDR new_sp = FRAME_FP (frame);
2903 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
2905 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
2906 if (frame->saved_regs == NULL)
2907 FRAME_INIT_SAVED_REGS (frame);
2908 for (regnum = 0; regnum < NUM_REGS; regnum++)
2910 if (regnum != SP_REGNUM && regnum != PC_REGNUM
2911 && frame->saved_regs[regnum])
2912 write_register (regnum,
2913 read_memory_integer (frame->saved_regs[regnum],
2914 MIPS_SAVED_REGSIZE));
2916 write_register (SP_REGNUM, new_sp);
2917 flush_cached_frames ();
2919 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
2921 struct linked_proc_info *pi_ptr, *prev_ptr;
2923 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
2925 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
2927 if (&pi_ptr->info == proc_desc)
2932 error ("Can't locate dummy extra frame info\n");
2934 if (prev_ptr != NULL)
2935 prev_ptr->next = pi_ptr->next;
2937 linked_proc_desc_table = pi_ptr->next;
2941 write_register (HI_REGNUM,
2942 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
2943 MIPS_SAVED_REGSIZE));
2944 write_register (LO_REGNUM,
2945 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
2946 MIPS_SAVED_REGSIZE));
2947 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
2948 write_register (FCRCS_REGNUM,
2949 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
2950 MIPS_SAVED_REGSIZE));
2954 /* Floating point register management.
2956 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2957 64bit operations, these early MIPS cpus treat fp register pairs
2958 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2959 registers and offer a compatibility mode that emulates the MIPS2 fp
2960 model. When operating in MIPS2 fp compat mode, later cpu's split
2961 double precision floats into two 32-bit chunks and store them in
2962 consecutive fp regs. To display 64-bit floats stored in this
2963 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2964 Throw in user-configurable endianness and you have a real mess.
2966 The way this works is:
2967 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2968 double-precision value will be split across two logical registers.
2969 The lower-numbered logical register will hold the low-order bits,
2970 regardless of the processor's endianness.
2971 - If we are on a 64-bit processor, and we are looking for a
2972 single-precision value, it will be in the low ordered bits
2973 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2974 save slot in memory.
2975 - If we are in 64-bit mode, everything is straightforward.
2977 Note that this code only deals with "live" registers at the top of the
2978 stack. We will attempt to deal with saved registers later, when
2979 the raw/cooked register interface is in place. (We need a general
2980 interface that can deal with dynamic saved register sizes -- fp
2981 regs could be 32 bits wide in one frame and 64 on the frame above
2984 static struct type *
2985 mips_float_register_type (void)
2987 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2988 return builtin_type_ieee_single_big;
2990 return builtin_type_ieee_single_little;
2993 static struct type *
2994 mips_double_register_type (void)
2996 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2997 return builtin_type_ieee_double_big;
2999 return builtin_type_ieee_double_little;
3002 /* Copy a 32-bit single-precision value from the current frame
3003 into rare_buffer. */
3006 mips_read_fp_register_single (int regno, char *rare_buffer)
3008 int raw_size = REGISTER_RAW_SIZE (regno);
3009 char *raw_buffer = alloca (raw_size);
3011 if (!frame_register_read (selected_frame, regno, raw_buffer))
3012 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3015 /* We have a 64-bit value for this register. Find the low-order
3019 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3024 memcpy (rare_buffer, raw_buffer + offset, 4);
3028 memcpy (rare_buffer, raw_buffer, 4);
3032 /* Copy a 64-bit double-precision value from the current frame into
3033 rare_buffer. This may include getting half of it from the next
3037 mips_read_fp_register_double (int regno, char *rare_buffer)
3039 int raw_size = REGISTER_RAW_SIZE (regno);
3041 if (raw_size == 8 && !mips2_fp_compat ())
3043 /* We have a 64-bit value for this register, and we should use
3045 if (!frame_register_read (selected_frame, regno, rare_buffer))
3046 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3050 if ((regno - FP0_REGNUM) & 1)
3051 internal_error (__FILE__, __LINE__,
3052 "mips_read_fp_register_double: bad access to "
3053 "odd-numbered FP register");
3055 /* mips_read_fp_register_single will find the correct 32 bits from
3057 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3059 mips_read_fp_register_single (regno, rare_buffer + 4);
3060 mips_read_fp_register_single (regno + 1, rare_buffer);
3064 mips_read_fp_register_single (regno, rare_buffer);
3065 mips_read_fp_register_single (regno + 1, rare_buffer + 4);
3071 mips_print_register (int regnum, int all)
3073 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3075 /* Get the data in raw format. */
3076 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3078 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
3082 /* If we have a actual 32-bit floating point register (or we are in
3083 32-bit compatibility mode), and the register is even-numbered,
3084 also print it as a double (spanning two registers). */
3085 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
3086 && (REGISTER_RAW_SIZE (regnum) == 4
3087 || mips2_fp_compat ())
3088 && !((regnum - FP0_REGNUM) & 1))
3090 char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
3092 mips_read_fp_register_double (regnum, dbuffer);
3094 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
3095 val_print (mips_double_register_type (), dbuffer, 0, 0,
3096 gdb_stdout, 0, 1, 0, Val_pretty_default);
3097 printf_filtered ("); ");
3099 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3101 /* The problem with printing numeric register names (r26, etc.) is that
3102 the user can't use them on input. Probably the best solution is to
3103 fix it so that either the numeric or the funky (a2, etc.) names
3104 are accepted on input. */
3105 if (regnum < MIPS_NUMREGS)
3106 printf_filtered ("(r%d): ", regnum);
3108 printf_filtered (": ");
3110 /* If virtual format is floating, print it that way. */
3111 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3112 if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
3114 /* We have a meaningful 64-bit value in this register. Show
3115 it as a 32-bit float and a 64-bit double. */
3116 int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
3118 printf_filtered (" (float) ");
3119 val_print (mips_float_register_type (), raw_buffer + offset, 0, 0,
3120 gdb_stdout, 0, 1, 0, Val_pretty_default);
3121 printf_filtered (", (double) ");
3122 val_print (mips_double_register_type (), raw_buffer, 0, 0,
3123 gdb_stdout, 0, 1, 0, Val_pretty_default);
3126 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
3127 gdb_stdout, 0, 1, 0, Val_pretty_default);
3128 /* Else print as integer in hex. */
3133 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3134 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
3138 print_scalar_formatted (raw_buffer + offset,
3139 REGISTER_VIRTUAL_TYPE (regnum),
3140 'x', 0, gdb_stdout);
3144 /* Replacement for generic do_registers_info.
3145 Print regs in pretty columns. */
3148 do_fp_register_row (int regnum)
3149 { /* do values for FP (float) regs */
3151 double doub, flt1, flt2; /* doubles extracted from raw hex data */
3152 int inv1, inv2, inv3;
3154 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
3156 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
3158 /* 4-byte registers: we can fit two registers per row. */
3159 /* Also print every pair of 4-byte regs as an 8-byte double. */
3160 mips_read_fp_register_single (regnum, raw_buffer);
3161 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
3163 mips_read_fp_register_single (regnum + 1, raw_buffer);
3164 flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2);
3166 mips_read_fp_register_double (regnum, raw_buffer);
3167 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
3169 printf_filtered (" %-5s", REGISTER_NAME (regnum));
3171 printf_filtered (": <invalid float>");
3173 printf_filtered ("%-17.9g", flt1);
3175 printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
3177 printf_filtered (": <invalid float>");
3179 printf_filtered ("%-17.9g", flt2);
3181 printf_filtered (" dbl: ");
3183 printf_filtered ("<invalid double>");
3185 printf_filtered ("%-24.17g", doub);
3186 printf_filtered ("\n");
3188 /* may want to do hex display here (future enhancement) */
3193 /* Eight byte registers: print each one as float AND as double. */
3194 mips_read_fp_register_single (regnum, raw_buffer);
3195 flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1);
3197 mips_read_fp_register_double (regnum, raw_buffer);
3198 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
3200 printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
3202 printf_filtered ("<invalid float>");
3204 printf_filtered ("flt: %-17.9g", flt1);
3206 printf_filtered (" dbl: ");
3208 printf_filtered ("<invalid double>");
3210 printf_filtered ("%-24.17g", doub);
3212 printf_filtered ("\n");
3213 /* may want to do hex display here (future enhancement) */
3219 /* Print a row's worth of GP (int) registers, with name labels above */
3222 do_gp_register_row (int regnum)
3224 /* do values for GP (int) regs */
3225 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3226 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
3228 int start_regnum = regnum;
3229 int numregs = NUM_REGS;
3232 /* For GP registers, we print a separate row of names above the vals */
3233 printf_filtered (" ");
3234 for (col = 0; col < ncols && regnum < numregs; regnum++)
3236 if (*REGISTER_NAME (regnum) == '\0')
3237 continue; /* unused register */
3238 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3239 break; /* end the row: reached FP register */
3240 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
3241 REGISTER_NAME (regnum));
3244 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
3245 start_regnum); /* print the R0 to R31 names */
3247 regnum = start_regnum; /* go back to start of row */
3248 /* now print the values in hex, 4 or 8 to the row */
3249 for (col = 0; col < ncols && regnum < numregs; regnum++)
3251 if (*REGISTER_NAME (regnum) == '\0')
3252 continue; /* unused register */
3253 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3254 break; /* end row: reached FP register */
3255 /* OK: get the data in raw format. */
3256 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3257 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3258 /* pad small registers */
3259 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
3260 printf_filtered (" ");
3261 /* Now print the register value in hex, endian order. */
3262 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3263 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
3264 byte < REGISTER_RAW_SIZE (regnum);
3266 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
3268 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
3271 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
3272 printf_filtered (" ");
3275 if (col > 0) /* ie. if we actually printed anything... */
3276 printf_filtered ("\n");
3281 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3284 mips_do_registers_info (int regnum, int fpregs)
3286 if (regnum != -1) /* do one specified register */
3288 if (*(REGISTER_NAME (regnum)) == '\0')
3289 error ("Not a valid register for the current processor type");
3291 mips_print_register (regnum, 0);
3292 printf_filtered ("\n");
3295 /* do all (or most) registers */
3298 while (regnum < NUM_REGS)
3300 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3301 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
3302 regnum = do_fp_register_row (regnum); /* FP regs */
3304 regnum += MIPS_NUMREGS; /* skip floating point regs */
3306 regnum = do_gp_register_row (regnum); /* GP (int) regs */
3311 /* Return number of args passed to a frame. described by FIP.
3312 Can return -1, meaning no way to tell. */
3315 mips_frame_num_args (struct frame_info *frame)
3320 /* Is this a branch with a delay slot? */
3322 static int is_delayed (unsigned long);
3325 is_delayed (unsigned long insn)
3328 for (i = 0; i < NUMOPCODES; ++i)
3329 if (mips_opcodes[i].pinfo != INSN_MACRO
3330 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
3332 return (i < NUMOPCODES
3333 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
3334 | INSN_COND_BRANCH_DELAY
3335 | INSN_COND_BRANCH_LIKELY)));
3339 mips_step_skips_delay (CORE_ADDR pc)
3341 char buf[MIPS_INSTLEN];
3343 /* There is no branch delay slot on MIPS16. */
3344 if (pc_is_mips16 (pc))
3347 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
3348 /* If error reading memory, guess that it is not a delayed branch. */
3350 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
3354 /* Skip the PC past function prologue instructions (32-bit version).
3355 This is a helper function for mips_skip_prologue. */
3358 mips32_skip_prologue (CORE_ADDR pc)
3362 int seen_sp_adjust = 0;
3363 int load_immediate_bytes = 0;
3365 /* Skip the typical prologue instructions. These are the stack adjustment
3366 instruction and the instructions that save registers on the stack
3367 or in the gcc frame. */
3368 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
3370 unsigned long high_word;
3372 inst = mips_fetch_instruction (pc);
3373 high_word = (inst >> 16) & 0xffff;
3375 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
3376 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
3378 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
3379 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
3381 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3382 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3383 && (inst & 0x001F0000)) /* reg != $zero */
3386 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3388 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
3390 continue; /* reg != $zero */
3392 /* move $s8,$sp. With different versions of gas this will be either
3393 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3394 Accept any one of these. */
3395 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3398 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3400 else if (high_word == 0x3c1c) /* lui $gp,n */
3402 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
3404 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3405 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
3407 /* The following instructions load $at or $t0 with an immediate
3408 value in preparation for a stack adjustment via
3409 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3410 a local variable, so we accept them only before a stack adjustment
3411 instruction was seen. */
3412 else if (!seen_sp_adjust)
3414 if (high_word == 0x3c01 || /* lui $at,n */
3415 high_word == 0x3c08) /* lui $t0,n */
3417 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
3420 else if (high_word == 0x3421 || /* ori $at,$at,n */
3421 high_word == 0x3508 || /* ori $t0,$t0,n */
3422 high_word == 0x3401 || /* ori $at,$zero,n */
3423 high_word == 0x3408) /* ori $t0,$zero,n */
3425 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
3435 /* In a frameless function, we might have incorrectly
3436 skipped some load immediate instructions. Undo the skipping
3437 if the load immediate was not followed by a stack adjustment. */
3438 if (load_immediate_bytes && !seen_sp_adjust)
3439 pc -= load_immediate_bytes;
3443 /* Skip the PC past function prologue instructions (16-bit version).
3444 This is a helper function for mips_skip_prologue. */
3447 mips16_skip_prologue (CORE_ADDR pc)
3450 int extend_bytes = 0;
3451 int prev_extend_bytes;
3453 /* Table of instructions likely to be found in a function prologue. */
3456 unsigned short inst;
3457 unsigned short mask;
3464 , /* addiu $sp,offset */
3468 , /* daddiu $sp,offset */
3472 , /* sw reg,n($sp) */
3476 , /* sd reg,n($sp) */
3480 , /* sw $ra,n($sp) */
3484 , /* sd $ra,n($sp) */
3492 , /* sw $a0-$a3,n($s1) */
3496 , /* move reg,$a0-$a3 */
3500 , /* entry pseudo-op */
3504 , /* addiu $s1,$sp,n */
3507 } /* end of table marker */
3510 /* Skip the typical prologue instructions. These are the stack adjustment
3511 instruction and the instructions that save registers on the stack
3512 or in the gcc frame. */
3513 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
3515 unsigned short inst;
3518 inst = mips_fetch_instruction (pc);
3520 /* Normally we ignore an extend instruction. However, if it is
3521 not followed by a valid prologue instruction, we must adjust
3522 the pc back over the extend so that it won't be considered
3523 part of the prologue. */
3524 if ((inst & 0xf800) == 0xf000) /* extend */
3526 extend_bytes = MIPS16_INSTLEN;
3529 prev_extend_bytes = extend_bytes;
3532 /* Check for other valid prologue instructions besides extend. */
3533 for (i = 0; table[i].mask != 0; i++)
3534 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
3536 if (table[i].mask != 0) /* it was in table? */
3537 continue; /* ignore it */
3541 /* Return the current pc, adjusted backwards by 2 if
3542 the previous instruction was an extend. */
3543 return pc - prev_extend_bytes;
3549 /* To skip prologues, I use this predicate. Returns either PC itself
3550 if the code at PC does not look like a function prologue; otherwise
3551 returns an address that (if we're lucky) follows the prologue. If
3552 LENIENT, then we must skip everything which is involved in setting
3553 up the frame (it's OK to skip more, just so long as we don't skip
3554 anything which might clobber the registers which are being saved.
3555 We must skip more in the case where part of the prologue is in the
3556 delay slot of a non-prologue instruction). */
3559 mips_skip_prologue (CORE_ADDR pc)
3561 /* See if we can determine the end of the prologue via the symbol table.
3562 If so, then return either PC, or the PC after the prologue, whichever
3565 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
3567 if (post_prologue_pc != 0)
3568 return max (pc, post_prologue_pc);
3570 /* Can't determine prologue from the symbol table, need to examine
3573 if (pc_is_mips16 (pc))
3574 return mips16_skip_prologue (pc);
3576 return mips32_skip_prologue (pc);
3579 /* Determine how a return value is stored within the MIPS register
3580 file, given the return type `valtype'. */
3582 struct return_value_word
3591 return_value_location (struct type *valtype,
3592 struct return_value_word *hi,
3593 struct return_value_word *lo)
3595 int len = TYPE_LENGTH (valtype);
3597 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
3598 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
3599 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
3601 if (!FP_REGISTER_DOUBLE && len == 8)
3603 /* We need to break a 64bit float in two 32 bit halves and
3604 spread them across a floating-point register pair. */
3605 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3606 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
3607 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3608 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
3610 hi->reg_offset = lo->reg_offset;
3611 lo->reg = FP0_REGNUM + 0;
3612 hi->reg = FP0_REGNUM + 1;
3618 /* The floating point value fits in a single floating-point
3620 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3621 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
3624 lo->reg = FP0_REGNUM;
3635 /* Locate a result possibly spread across two registers. */
3637 lo->reg = regnum + 0;
3638 hi->reg = regnum + 1;
3639 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3640 && len < MIPS_SAVED_REGSIZE)
3642 /* "un-left-justify" the value in the low register */
3643 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
3648 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3649 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
3650 && len < MIPS_SAVED_REGSIZE * 2
3651 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
3652 TYPE_CODE (valtype) == TYPE_CODE_UNION))
3654 /* "un-left-justify" the value spread across two registers. */
3655 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
3656 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
3658 hi->len = len - lo->len;
3662 /* Only perform a partial copy of the second register. */
3665 if (len > MIPS_SAVED_REGSIZE)
3667 lo->len = MIPS_SAVED_REGSIZE;
3668 hi->len = len - MIPS_SAVED_REGSIZE;
3676 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3677 && REGISTER_RAW_SIZE (regnum) == 8
3678 && MIPS_SAVED_REGSIZE == 4)
3680 /* Account for the fact that only the least-signficant part
3681 of the register is being used */
3682 lo->reg_offset += 4;
3683 hi->reg_offset += 4;
3686 hi->buf_offset = lo->len;
3690 /* Given a return value in `regbuf' with a type `valtype', extract and
3691 copy its value into `valbuf'. */
3694 mips_extract_return_value (struct type *valtype,
3695 char regbuf[REGISTER_BYTES],
3698 struct return_value_word lo;
3699 struct return_value_word hi;
3700 return_value_location (valtype, &hi, &lo);
3702 memcpy (valbuf + lo.buf_offset,
3703 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
3707 memcpy (valbuf + hi.buf_offset,
3708 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
3712 /* Given a return value in `valbuf' with a type `valtype', write it's
3713 value into the appropriate register. */
3716 mips_store_return_value (struct type *valtype, char *valbuf)
3718 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3719 struct return_value_word lo;
3720 struct return_value_word hi;
3721 return_value_location (valtype, &hi, &lo);
3723 memset (raw_buffer, 0, sizeof (raw_buffer));
3724 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
3725 write_register_bytes (REGISTER_BYTE (lo.reg),
3727 REGISTER_RAW_SIZE (lo.reg));
3731 memset (raw_buffer, 0, sizeof (raw_buffer));
3732 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
3733 write_register_bytes (REGISTER_BYTE (hi.reg),
3735 REGISTER_RAW_SIZE (hi.reg));
3739 /* Exported procedure: Is PC in the signal trampoline code */
3742 in_sigtramp (CORE_ADDR pc, char *ignore)
3744 if (sigtramp_address == 0)
3746 return (pc >= sigtramp_address && pc < sigtramp_end);
3749 /* Root of all "set mips "/"show mips " commands. This will eventually be
3750 used for all MIPS-specific commands. */
3753 show_mips_command (char *args, int from_tty)
3755 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
3759 set_mips_command (char *args, int from_tty)
3761 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3762 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
3765 /* Commands to show/set the MIPS FPU type. */
3768 show_mipsfpu_command (char *args, int from_tty)
3771 switch (MIPS_FPU_TYPE)
3773 case MIPS_FPU_SINGLE:
3774 fpu = "single-precision";
3776 case MIPS_FPU_DOUBLE:
3777 fpu = "double-precision";
3780 fpu = "absent (none)";
3783 internal_error (__FILE__, __LINE__, "bad switch");
3785 if (mips_fpu_type_auto)
3786 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3789 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3795 set_mipsfpu_command (char *args, int from_tty)
3797 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3798 show_mipsfpu_command (args, from_tty);
3802 set_mipsfpu_single_command (char *args, int from_tty)
3804 mips_fpu_type = MIPS_FPU_SINGLE;
3805 mips_fpu_type_auto = 0;
3806 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
3810 set_mipsfpu_double_command (char *args, int from_tty)
3812 mips_fpu_type = MIPS_FPU_DOUBLE;
3813 mips_fpu_type_auto = 0;
3814 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
3818 set_mipsfpu_none_command (char *args, int from_tty)
3820 mips_fpu_type = MIPS_FPU_NONE;
3821 mips_fpu_type_auto = 0;
3822 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
3826 set_mipsfpu_auto_command (char *args, int from_tty)
3828 mips_fpu_type_auto = 1;
3831 /* Command to set the processor type. */
3834 mips_set_processor_type_command (char *args, int from_tty)
3838 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
3840 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3841 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3842 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
3844 /* Restore the value. */
3845 tmp_mips_processor_type = xstrdup (mips_processor_type);
3850 if (!mips_set_processor_type (tmp_mips_processor_type))
3852 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
3853 /* Restore its value. */
3854 tmp_mips_processor_type = xstrdup (mips_processor_type);
3859 mips_show_processor_type_command (char *args, int from_tty)
3863 /* Modify the actual processor type. */
3866 mips_set_processor_type (char *str)
3873 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3875 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
3877 mips_processor_type = str;
3878 mips_processor_reg_names = mips_processor_type_table[i].regnames;
3880 /* FIXME tweak fpu flag too */
3887 /* Attempt to identify the particular processor model by reading the
3891 mips_read_processor_type (void)
3895 prid = read_register (PRID_REGNUM);
3897 if ((prid & ~0xf) == 0x700)
3898 return savestring ("r3041", strlen ("r3041"));
3903 /* Just like reinit_frame_cache, but with the right arguments to be
3904 callable as an sfunc. */
3907 reinit_frame_cache_sfunc (char *args, int from_tty,
3908 struct cmd_list_element *c)
3910 reinit_frame_cache ();
3914 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
3916 mips_extra_func_info_t proc_desc;
3918 /* Search for the function containing this address. Set the low bit
3919 of the address when searching, in case we were given an even address
3920 that is the start of a 16-bit function. If we didn't do this,
3921 the search would fail because the symbol table says the function
3922 starts at an odd address, i.e. 1 byte past the given address. */
3923 memaddr = ADDR_BITS_REMOVE (memaddr);
3924 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
3926 /* Make an attempt to determine if this is a 16-bit function. If
3927 the procedure descriptor exists and the address therein is odd,
3928 it's definitely a 16-bit function. Otherwise, we have to just
3929 guess that if the address passed in is odd, it's 16-bits. */
3931 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
3932 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
3934 info->mach = pc_is_mips16 (memaddr) ?
3935 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
3937 /* Round down the instruction address to the appropriate boundary. */
3938 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
3940 /* Call the appropriate disassembler based on the target endian-ness. */
3941 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3942 return print_insn_big_mips (memaddr, info);
3944 return print_insn_little_mips (memaddr, info);
3947 /* Old-style breakpoint macros.
3948 The IDT board uses an unusual breakpoint value, and sometimes gets
3949 confused when it sees the usual MIPS breakpoint instruction. */
3951 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3952 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3953 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3954 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3955 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3956 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3957 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3958 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3960 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3961 counter value to determine whether a 16- or 32-bit breakpoint should be
3962 used. It returns a pointer to a string of bytes that encode a breakpoint
3963 instruction, stores the length of the string to *lenptr, and adjusts pc
3964 (if necessary) to point to the actual memory location where the
3965 breakpoint should be inserted. */
3967 const unsigned char *
3968 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
3970 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3972 if (pc_is_mips16 (*pcptr))
3974 static unsigned char mips16_big_breakpoint[] =
3975 MIPS16_BIG_BREAKPOINT;
3976 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
3977 *lenptr = sizeof (mips16_big_breakpoint);
3978 return mips16_big_breakpoint;
3982 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
3983 static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
3984 static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
3986 *lenptr = sizeof (big_breakpoint);
3988 if (strcmp (target_shortname, "mips") == 0)
3989 return idt_big_breakpoint;
3990 else if (strcmp (target_shortname, "ddb") == 0
3991 || strcmp (target_shortname, "pmon") == 0
3992 || strcmp (target_shortname, "lsi") == 0)
3993 return pmon_big_breakpoint;
3995 return big_breakpoint;
4000 if (pc_is_mips16 (*pcptr))
4002 static unsigned char mips16_little_breakpoint[] =
4003 MIPS16_LITTLE_BREAKPOINT;
4004 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
4005 *lenptr = sizeof (mips16_little_breakpoint);
4006 return mips16_little_breakpoint;
4010 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
4011 static unsigned char pmon_little_breakpoint[] =
4012 PMON_LITTLE_BREAKPOINT;
4013 static unsigned char idt_little_breakpoint[] =
4014 IDT_LITTLE_BREAKPOINT;
4016 *lenptr = sizeof (little_breakpoint);
4018 if (strcmp (target_shortname, "mips") == 0)
4019 return idt_little_breakpoint;
4020 else if (strcmp (target_shortname, "ddb") == 0
4021 || strcmp (target_shortname, "pmon") == 0
4022 || strcmp (target_shortname, "lsi") == 0)
4023 return pmon_little_breakpoint;
4025 return little_breakpoint;
4030 /* If PC is in a mips16 call or return stub, return the address of the target
4031 PC, which is either the callee or the caller. There are several
4032 cases which must be handled:
4034 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4035 target PC is in $31 ($ra).
4036 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4037 and the target PC is in $2.
4038 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4039 before the jal instruction, this is effectively a call stub
4040 and the the target PC is in $2. Otherwise this is effectively
4041 a return stub and the target PC is in $18.
4043 See the source code for the stubs in gcc/config/mips/mips16.S for
4046 This function implements the SKIP_TRAMPOLINE_CODE macro.
4050 mips_skip_stub (CORE_ADDR pc)
4053 CORE_ADDR start_addr;
4055 /* Find the starting address and name of the function containing the PC. */
4056 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
4059 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4060 target PC is in $31 ($ra). */
4061 if (strcmp (name, "__mips16_ret_sf") == 0
4062 || strcmp (name, "__mips16_ret_df") == 0)
4063 return read_signed_register (RA_REGNUM);
4065 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
4067 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4068 and the target PC is in $2. */
4069 if (name[19] >= '0' && name[19] <= '9')
4070 return read_signed_register (2);
4072 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4073 before the jal instruction, this is effectively a call stub
4074 and the the target PC is in $2. Otherwise this is effectively
4075 a return stub and the target PC is in $18. */
4076 else if (name[19] == 's' || name[19] == 'd')
4078 if (pc == start_addr)
4080 /* Check if the target of the stub is a compiler-generated
4081 stub. Such a stub for a function bar might have a name
4082 like __fn_stub_bar, and might look like this:
4087 la $1,bar (becomes a lui/addiu pair)
4089 So scan down to the lui/addi and extract the target
4090 address from those two instructions. */
4092 CORE_ADDR target_pc = read_signed_register (2);
4096 /* See if the name of the target function is __fn_stub_*. */
4097 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
4099 if (strncmp (name, "__fn_stub_", 10) != 0
4100 && strcmp (name, "etext") != 0
4101 && strcmp (name, "_etext") != 0)
4104 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4105 The limit on the search is arbitrarily set to 20
4106 instructions. FIXME. */
4107 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
4109 inst = mips_fetch_instruction (target_pc);
4110 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
4111 pc = (inst << 16) & 0xffff0000; /* high word */
4112 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
4113 return pc | (inst & 0xffff); /* low word */
4116 /* Couldn't find the lui/addui pair, so return stub address. */
4120 /* This is the 'return' part of a call stub. The return
4121 address is in $r18. */
4122 return read_signed_register (18);
4125 return 0; /* not a stub */
4129 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4130 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4133 mips_in_call_stub (CORE_ADDR pc, char *name)
4135 CORE_ADDR start_addr;
4137 /* Find the starting address of the function containing the PC. If the
4138 caller didn't give us a name, look it up at the same time. */
4139 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
4142 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
4144 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4145 if (name[19] >= '0' && name[19] <= '9')
4147 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4148 before the jal instruction, this is effectively a call stub. */
4149 else if (name[19] == 's' || name[19] == 'd')
4150 return pc == start_addr;
4153 return 0; /* not a stub */
4157 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4158 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4161 mips_in_return_stub (CORE_ADDR pc, char *name)
4163 CORE_ADDR start_addr;
4165 /* Find the starting address of the function containing the PC. */
4166 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
4169 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4170 if (strcmp (name, "__mips16_ret_sf") == 0
4171 || strcmp (name, "__mips16_ret_df") == 0)
4174 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4175 i.e. after the jal instruction, this is effectively a return stub. */
4176 if (strncmp (name, "__mips16_call_stub_", 19) == 0
4177 && (name[19] == 's' || name[19] == 'd')
4178 && pc != start_addr)
4181 return 0; /* not a stub */
4185 /* Return non-zero if the PC is in a library helper function that should
4186 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4189 mips_ignore_helper (CORE_ADDR pc)
4193 /* Find the starting address and name of the function containing the PC. */
4194 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
4197 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4198 that we want to ignore. */
4199 return (strcmp (name, "__mips16_ret_sf") == 0
4200 || strcmp (name, "__mips16_ret_df") == 0);
4204 /* Return a location where we can set a breakpoint that will be hit
4205 when an inferior function call returns. This is normally the
4206 program's entry point. Executables that don't have an entry
4207 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4208 whose address is the location where the breakpoint should be placed. */
4211 mips_call_dummy_address (void)
4213 struct minimal_symbol *sym;
4215 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
4217 return SYMBOL_VALUE_ADDRESS (sym);
4219 return entry_point_address ();
4223 /* If the current gcc for this target does not produce correct debugging
4224 information for float parameters, both prototyped and unprototyped, then
4225 define this macro. This forces gdb to always assume that floats are
4226 passed as doubles and then converted in the callee.
4228 For the mips chip, it appears that the debug info marks the parameters as
4229 floats regardless of whether the function is prototyped, but the actual
4230 values are passed as doubles for the non-prototyped case and floats for
4231 the prototyped case. Thus we choose to make the non-prototyped case work
4232 for C and break the prototyped case, since the non-prototyped case is
4233 probably much more common. (FIXME). */
4236 mips_coerce_float_to_double (struct type *formal, struct type *actual)
4238 return current_language->la_language == language_c;
4241 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4242 the register stored on the stack (32) is different to its real raw
4243 size (64). The below ensures that registers are fetched from the
4244 stack using their ABI size and then stored into the RAW_BUFFER
4245 using their raw size.
4247 The alternative to adding this function would be to add an ABI
4248 macro - REGISTER_STACK_SIZE(). */
4251 mips_get_saved_register (char *raw_buffer,
4254 struct frame_info *frame,
4256 enum lval_type *lval)
4260 if (!target_has_registers)
4261 error ("No registers.");
4263 /* Normal systems don't optimize out things with register numbers. */
4264 if (optimized != NULL)
4266 addr = find_saved_register (frame, regnum);
4270 *lval = lval_memory;
4271 if (regnum == SP_REGNUM)
4273 if (raw_buffer != NULL)
4275 /* Put it back in target format. */
4276 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
4283 if (raw_buffer != NULL)
4287 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4289 val = read_memory_integer (addr, MIPS_SAVED_REGSIZE);
4291 val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum));
4292 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
4298 *lval = lval_register;
4299 addr = REGISTER_BYTE (regnum);
4300 if (raw_buffer != NULL)
4301 read_register_gen (regnum, raw_buffer);
4307 /* Immediately after a function call, return the saved pc.
4308 Can't always go through the frames for this because on some machines
4309 the new frame is not set up until the new function executes
4310 some instructions. */
4313 mips_saved_pc_after_call (struct frame_info *frame)
4315 return read_signed_register (RA_REGNUM);
4319 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4323 mips_stab_reg_to_regnum (int num)
4328 return num + FP0_REGNUM - 38;
4331 /* Convert a ecoff register number to a gdb REGNUM */
4334 mips_ecoff_reg_to_regnum (int num)
4339 return num + FP0_REGNUM - 32;
4342 /* Convert an integer into an address. By first converting the value
4343 into a pointer and then extracting it signed, the address is
4344 guarenteed to be correctly sign extended. */
4347 mips_integer_to_address (struct type *type, void *buf)
4349 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
4350 LONGEST val = unpack_long (type, buf);
4351 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
4352 return extract_signed_integer (tmp,
4353 TYPE_LENGTH (builtin_type_void_data_ptr));
4357 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
4359 enum mips_abi *abip = (enum mips_abi *) obj;
4360 const char *name = bfd_get_section_name (abfd, sect);
4362 if (*abip != MIPS_ABI_UNKNOWN)
4365 if (strncmp (name, ".mdebug.", 8) != 0)
4368 if (strcmp (name, ".mdebug.abi32") == 0)
4369 *abip = MIPS_ABI_O32;
4370 else if (strcmp (name, ".mdebug.abiN32") == 0)
4371 *abip = MIPS_ABI_N32;
4372 else if (strcmp (name, ".mdebug.abiN64") == 0)
4373 *abip = MIPS_ABI_N64;
4374 else if (strcmp (name, ".mdebug.abiO64") == 0)
4375 *abip = MIPS_ABI_O64;
4376 else if (strcmp (name, ".mdebug.eabi32") == 0)
4377 *abip = MIPS_ABI_EABI32;
4378 else if (strcmp (name, ".mdebug.eabi64") == 0)
4379 *abip = MIPS_ABI_EABI64;
4381 warning ("unsupported ABI %s.", name + 8);
4384 static enum mips_abi
4385 global_mips_abi (void)
4389 for (i = 0; mips_abi_strings[i] != NULL; i++)
4390 if (mips_abi_strings[i] == mips_abi_string)
4391 return (enum mips_abi) i;
4393 internal_error (__FILE__, __LINE__,
4394 "unknown ABI string");
4397 static struct gdbarch *
4398 mips_gdbarch_init (struct gdbarch_info info,
4399 struct gdbarch_list *arches)
4401 static LONGEST mips_call_dummy_words[] =
4403 struct gdbarch *gdbarch;
4404 struct gdbarch_tdep *tdep;
4406 enum mips_abi mips_abi, found_abi, wanted_abi;
4407 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
4409 /* Reset the disassembly info, in case it was set to something
4411 tm_print_insn_info.flavour = bfd_target_unknown_flavour;
4412 tm_print_insn_info.arch = bfd_arch_unknown;
4413 tm_print_insn_info.mach = 0;
4419 /* First of all, extract the elf_flags, if available. */
4420 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
4421 elf_flags = elf_elfheader (info.abfd)->e_flags;
4423 /* Try to determine the OS ABI of the object we are loading. If
4424 we end up with `unknown', just leave it that way. */
4425 osabi = gdbarch_lookup_osabi (info.abfd);
4428 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4429 switch ((elf_flags & EF_MIPS_ABI))
4431 case E_MIPS_ABI_O32:
4432 mips_abi = MIPS_ABI_O32;
4434 case E_MIPS_ABI_O64:
4435 mips_abi = MIPS_ABI_O64;
4437 case E_MIPS_ABI_EABI32:
4438 mips_abi = MIPS_ABI_EABI32;
4440 case E_MIPS_ABI_EABI64:
4441 mips_abi = MIPS_ABI_EABI64;
4444 if ((elf_flags & EF_MIPS_ABI2))
4445 mips_abi = MIPS_ABI_N32;
4447 mips_abi = MIPS_ABI_UNKNOWN;
4451 /* GCC creates a pseudo-section whose name describes the ABI. */
4452 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
4453 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
4455 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
4456 Use the ABI from the last architecture if there is one. */
4457 if (info.abfd == NULL && arches != NULL)
4458 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
4460 /* Try the architecture for any hint of the correct ABI. */
4461 if (mips_abi == MIPS_ABI_UNKNOWN
4462 && info.bfd_arch_info != NULL
4463 && info.bfd_arch_info->arch == bfd_arch_mips)
4465 switch (info.bfd_arch_info->mach)
4467 case bfd_mach_mips3900:
4468 mips_abi = MIPS_ABI_EABI32;
4470 case bfd_mach_mips4100:
4471 case bfd_mach_mips5000:
4472 mips_abi = MIPS_ABI_EABI64;
4474 case bfd_mach_mips8000:
4475 case bfd_mach_mips10000:
4476 /* On Irix, ELF64 executables use the N64 ABI. The
4477 pseudo-sections which describe the ABI aren't present
4478 on IRIX. (Even for executables created by gcc.) */
4479 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
4480 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
4481 mips_abi = MIPS_ABI_N64;
4483 mips_abi = MIPS_ABI_N32;
4488 #ifdef MIPS_DEFAULT_ABI
4489 if (mips_abi == MIPS_ABI_UNKNOWN)
4490 mips_abi = MIPS_DEFAULT_ABI;
4493 if (mips_abi == MIPS_ABI_UNKNOWN)
4494 mips_abi = MIPS_ABI_O32;
4496 /* Now that we have found what the ABI for this binary would be,
4497 check whether the user is overriding it. */
4498 found_abi = mips_abi;
4499 wanted_abi = global_mips_abi ();
4500 if (wanted_abi != MIPS_ABI_UNKNOWN)
4501 mips_abi = wanted_abi;
4505 fprintf_unfiltered (gdb_stdlog,
4506 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4508 fprintf_unfiltered (gdb_stdlog,
4509 "mips_gdbarch_init: mips_abi = %d\n",
4511 fprintf_unfiltered (gdb_stdlog,
4512 "mips_gdbarch_init: found_mips_abi = %d\n",
4516 /* try to find a pre-existing architecture */
4517 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4519 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4521 /* MIPS needs to be pedantic about which ABI the object is
4523 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
4525 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
4527 if (gdbarch_tdep (arches->gdbarch)->osabi == osabi)
4528 return arches->gdbarch;
4531 /* Need a new architecture. Fill in a target specific vector. */
4532 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4533 gdbarch = gdbarch_alloc (&info, tdep);
4534 tdep->elf_flags = elf_flags;
4535 tdep->osabi = osabi;
4537 /* Initially set everything according to the default ABI/ISA. */
4538 set_gdbarch_short_bit (gdbarch, 16);
4539 set_gdbarch_int_bit (gdbarch, 32);
4540 set_gdbarch_float_bit (gdbarch, 32);
4541 set_gdbarch_double_bit (gdbarch, 64);
4542 set_gdbarch_long_double_bit (gdbarch, 64);
4543 set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size);
4544 tdep->found_abi = found_abi;
4545 tdep->mips_abi = mips_abi;
4550 tdep->mips_default_saved_regsize = 4;
4551 tdep->mips_default_stack_argsize = 4;
4552 tdep->mips_fp_register_double = 0;
4553 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
4554 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
4555 tdep->mips_regs_have_home_p = 1;
4556 tdep->gdb_target_is_mips64 = 0;
4557 tdep->default_mask_address_p = 0;
4558 set_gdbarch_long_bit (gdbarch, 32);
4559 set_gdbarch_ptr_bit (gdbarch, 32);
4560 set_gdbarch_long_long_bit (gdbarch, 64);
4561 set_gdbarch_reg_struct_has_addr (gdbarch,
4562 mips_o32_reg_struct_has_addr);
4563 set_gdbarch_use_struct_convention (gdbarch,
4564 mips_o32_use_struct_convention);
4567 tdep->mips_default_saved_regsize = 8;
4568 tdep->mips_default_stack_argsize = 8;
4569 tdep->mips_fp_register_double = 1;
4570 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
4571 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
4572 tdep->mips_regs_have_home_p = 1;
4573 tdep->gdb_target_is_mips64 = 1;
4574 tdep->default_mask_address_p = 0;
4575 set_gdbarch_long_bit (gdbarch, 32);
4576 set_gdbarch_ptr_bit (gdbarch, 32);
4577 set_gdbarch_long_long_bit (gdbarch, 64);
4578 set_gdbarch_reg_struct_has_addr (gdbarch,
4579 mips_o32_reg_struct_has_addr);
4580 set_gdbarch_use_struct_convention (gdbarch,
4581 mips_o32_use_struct_convention);
4583 case MIPS_ABI_EABI32:
4584 tdep->mips_default_saved_regsize = 4;
4585 tdep->mips_default_stack_argsize = 4;
4586 tdep->mips_fp_register_double = 0;
4587 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4588 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4589 tdep->mips_regs_have_home_p = 0;
4590 tdep->gdb_target_is_mips64 = 0;
4591 tdep->default_mask_address_p = 0;
4592 set_gdbarch_long_bit (gdbarch, 32);
4593 set_gdbarch_ptr_bit (gdbarch, 32);
4594 set_gdbarch_long_long_bit (gdbarch, 64);
4595 set_gdbarch_reg_struct_has_addr (gdbarch,
4596 mips_eabi_reg_struct_has_addr);
4597 set_gdbarch_use_struct_convention (gdbarch,
4598 mips_eabi_use_struct_convention);
4600 case MIPS_ABI_EABI64:
4601 tdep->mips_default_saved_regsize = 8;
4602 tdep->mips_default_stack_argsize = 8;
4603 tdep->mips_fp_register_double = 1;
4604 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4605 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4606 tdep->mips_regs_have_home_p = 0;
4607 tdep->gdb_target_is_mips64 = 1;
4608 tdep->default_mask_address_p = 0;
4609 set_gdbarch_long_bit (gdbarch, 64);
4610 set_gdbarch_ptr_bit (gdbarch, 64);
4611 set_gdbarch_long_long_bit (gdbarch, 64);
4612 set_gdbarch_reg_struct_has_addr (gdbarch,
4613 mips_eabi_reg_struct_has_addr);
4614 set_gdbarch_use_struct_convention (gdbarch,
4615 mips_eabi_use_struct_convention);
4618 tdep->mips_default_saved_regsize = 8;
4619 tdep->mips_default_stack_argsize = 8;
4620 tdep->mips_fp_register_double = 1;
4621 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4622 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4623 tdep->mips_regs_have_home_p = 0;
4624 tdep->gdb_target_is_mips64 = 1;
4625 tdep->default_mask_address_p = 0;
4626 set_gdbarch_long_bit (gdbarch, 32);
4627 set_gdbarch_ptr_bit (gdbarch, 32);
4628 set_gdbarch_long_long_bit (gdbarch, 64);
4630 /* Set up the disassembler info, so that we get the right
4631 register names from libopcodes. */
4632 tm_print_insn_info.flavour = bfd_target_elf_flavour;
4633 tm_print_insn_info.arch = bfd_arch_mips;
4634 if (info.bfd_arch_info != NULL
4635 && info.bfd_arch_info->arch == bfd_arch_mips
4636 && info.bfd_arch_info->mach)
4637 tm_print_insn_info.mach = info.bfd_arch_info->mach;
4639 tm_print_insn_info.mach = bfd_mach_mips8000;
4641 set_gdbarch_use_struct_convention (gdbarch,
4642 mips_n32n64_use_struct_convention);
4643 set_gdbarch_reg_struct_has_addr (gdbarch,
4644 mips_n32n64_reg_struct_has_addr);
4647 tdep->mips_default_saved_regsize = 8;
4648 tdep->mips_default_stack_argsize = 8;
4649 tdep->mips_fp_register_double = 1;
4650 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4651 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4652 tdep->mips_regs_have_home_p = 0;
4653 tdep->gdb_target_is_mips64 = 1;
4654 tdep->default_mask_address_p = 0;
4655 set_gdbarch_long_bit (gdbarch, 64);
4656 set_gdbarch_ptr_bit (gdbarch, 64);
4657 set_gdbarch_long_long_bit (gdbarch, 64);
4659 /* Set up the disassembler info, so that we get the right
4660 register names from libopcodes. */
4661 tm_print_insn_info.flavour = bfd_target_elf_flavour;
4662 tm_print_insn_info.arch = bfd_arch_mips;
4663 if (info.bfd_arch_info != NULL
4664 && info.bfd_arch_info->arch == bfd_arch_mips
4665 && info.bfd_arch_info->mach)
4666 tm_print_insn_info.mach = info.bfd_arch_info->mach;
4668 tm_print_insn_info.mach = bfd_mach_mips8000;
4670 set_gdbarch_use_struct_convention (gdbarch,
4671 mips_n32n64_use_struct_convention);
4672 set_gdbarch_reg_struct_has_addr (gdbarch,
4673 mips_n32n64_reg_struct_has_addr);
4676 internal_error (__FILE__, __LINE__,
4677 "unknown ABI in switch");
4680 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4681 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4684 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4685 flag in object files because to do so would make it impossible to
4686 link with libraries compiled without "-gp32". This is
4687 unnecessarily restrictive.
4689 We could solve this problem by adding "-gp32" multilibs to gcc,
4690 but to set this flag before gcc is built with such multilibs will
4691 break too many systems.''
4693 But even more unhelpfully, the default linker output target for
4694 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4695 for 64-bit programs - you need to change the ABI to change this,
4696 and not all gcc targets support that currently. Therefore using
4697 this flag to detect 32-bit mode would do the wrong thing given
4698 the current gcc - it would make GDB treat these 64-bit programs
4699 as 32-bit programs by default. */
4701 /* enable/disable the MIPS FPU */
4702 if (!mips_fpu_type_auto)
4703 tdep->mips_fpu_type = mips_fpu_type;
4704 else if (info.bfd_arch_info != NULL
4705 && info.bfd_arch_info->arch == bfd_arch_mips)
4706 switch (info.bfd_arch_info->mach)
4708 case bfd_mach_mips3900:
4709 case bfd_mach_mips4100:
4710 case bfd_mach_mips4111:
4711 tdep->mips_fpu_type = MIPS_FPU_NONE;
4713 case bfd_mach_mips4650:
4714 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
4717 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
4721 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
4723 /* MIPS version of register names. NOTE: At present the MIPS
4724 register name management is part way between the old -
4725 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4726 Further work on it is required. */
4727 set_gdbarch_register_name (gdbarch, mips_register_name);
4728 set_gdbarch_read_pc (gdbarch, mips_read_pc);
4729 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4730 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
4731 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4732 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4734 /* Add/remove bits from an address. The MIPS needs be careful to
4735 ensure that all 32 bit addresses are sign extended to 64 bits. */
4736 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
4738 /* There's a mess in stack frame creation. See comments in
4739 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4740 set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
4741 set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop);
4743 /* Map debug register numbers onto internal register numbers. */
4744 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
4745 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum);
4747 /* Initialize a frame */
4748 set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
4749 set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs);
4751 /* MIPS version of CALL_DUMMY */
4753 set_gdbarch_call_dummy_p (gdbarch, 1);
4754 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
4755 set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
4756 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
4757 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
4758 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
4759 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
4760 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4761 set_gdbarch_call_dummy_length (gdbarch, 0);
4762 set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
4763 set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
4764 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
4765 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
4766 set_gdbarch_push_arguments (gdbarch, mips_push_arguments);
4767 set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not);
4768 set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double);
4770 set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
4771 set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
4773 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4774 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
4775 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4777 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
4778 set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
4780 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
4781 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
4782 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
4784 /* There are MIPS targets which do not yet use this since they still
4785 define REGISTER_VIRTUAL_TYPE. */
4786 set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type);
4788 /* Hook in OS ABI-specific overrides, if they have been registered. */
4789 gdbarch_init_osabi (info, gdbarch, osabi);
4795 mips_abi_update (char *ignore_args, int from_tty,
4796 struct cmd_list_element *c)
4798 struct gdbarch_info info;
4800 /* Force the architecture to update, and (if it's a MIPS architecture)
4801 mips_gdbarch_init will take care of the rest. */
4802 gdbarch_info_init (&info);
4803 gdbarch_update_p (info);
4807 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4809 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4813 int ef_mips_32bitmode;
4814 /* determine the ISA */
4815 switch (tdep->elf_flags & EF_MIPS_ARCH)
4833 /* determine the size of a pointer */
4834 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
4835 fprintf_unfiltered (file,
4836 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4838 fprintf_unfiltered (file,
4839 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4841 fprintf_unfiltered (file,
4842 "mips_dump_tdep: ef_mips_arch = %d\n",
4844 fprintf_unfiltered (file,
4845 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4847 mips_abi_strings[tdep->mips_abi]);
4848 fprintf_unfiltered (file,
4849 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4850 mips_mask_address_p (),
4851 tdep->default_mask_address_p);
4853 fprintf_unfiltered (file,
4854 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4855 FP_REGISTER_DOUBLE);
4856 fprintf_unfiltered (file,
4857 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4858 MIPS_DEFAULT_FPU_TYPE,
4859 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
4860 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
4861 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
4863 fprintf_unfiltered (file,
4864 "mips_dump_tdep: MIPS_EABI = %d\n",
4866 fprintf_unfiltered (file,
4867 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4868 MIPS_LAST_FP_ARG_REGNUM,
4869 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
4870 fprintf_unfiltered (file,
4871 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4873 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
4874 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
4875 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
4877 fprintf_unfiltered (file,
4878 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4879 MIPS_DEFAULT_SAVED_REGSIZE);
4880 fprintf_unfiltered (file,
4881 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4882 FP_REGISTER_DOUBLE);
4883 fprintf_unfiltered (file,
4884 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4885 MIPS_REGS_HAVE_HOME_P);
4886 fprintf_unfiltered (file,
4887 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4888 MIPS_DEFAULT_STACK_ARGSIZE);
4889 fprintf_unfiltered (file,
4890 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4891 MIPS_STACK_ARGSIZE);
4892 fprintf_unfiltered (file,
4893 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4895 fprintf_unfiltered (file,
4896 "mips_dump_tdep: A0_REGNUM = %d\n",
4898 fprintf_unfiltered (file,
4899 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4900 XSTRING (ADDR_BITS_REMOVE(ADDR)));
4901 fprintf_unfiltered (file,
4902 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4903 XSTRING (ATTACH_DETACH));
4904 fprintf_unfiltered (file,
4905 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4907 fprintf_unfiltered (file,
4908 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4909 fprintf_unfiltered (file,
4910 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4912 fprintf_unfiltered (file,
4913 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4915 fprintf_unfiltered (file,
4916 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4918 fprintf_unfiltered (file,
4919 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4920 XSTRING (DO_REGISTERS_INFO));
4921 fprintf_unfiltered (file,
4922 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4923 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
4924 fprintf_unfiltered (file,
4925 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4926 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
4927 fprintf_unfiltered (file,
4928 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4929 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM)));
4930 fprintf_unfiltered (file,
4931 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4933 fprintf_unfiltered (file,
4934 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4936 fprintf_unfiltered (file,
4937 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4938 FIRST_EMBED_REGNUM);
4939 fprintf_unfiltered (file,
4940 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4942 fprintf_unfiltered (file,
4943 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4944 GDB_TARGET_IS_MIPS64);
4945 fprintf_unfiltered (file,
4946 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4947 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC)));
4948 fprintf_unfiltered (file,
4949 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4950 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC)));
4951 fprintf_unfiltered (file,
4952 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4954 fprintf_unfiltered (file,
4955 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4956 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
4957 fprintf_unfiltered (file,
4958 "mips_dump_tdep: HI_REGNUM = %d\n",
4960 fprintf_unfiltered (file,
4961 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4962 fprintf_unfiltered (file,
4963 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4964 fprintf_unfiltered (file,
4965 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4966 XSTRING (IGNORE_HELPER_CALL (PC)));
4967 fprintf_unfiltered (file,
4968 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4969 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
4970 fprintf_unfiltered (file,
4971 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4972 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
4973 fprintf_unfiltered (file,
4974 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4975 fprintf_unfiltered (file,
4976 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4978 fprintf_unfiltered (file,
4979 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4980 fprintf_unfiltered (file,
4981 "mips_dump_tdep: LO_REGNUM = %d\n",
4983 #ifdef MACHINE_CPROC_FP_OFFSET
4984 fprintf_unfiltered (file,
4985 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4986 MACHINE_CPROC_FP_OFFSET);
4988 #ifdef MACHINE_CPROC_PC_OFFSET
4989 fprintf_unfiltered (file,
4990 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4991 MACHINE_CPROC_PC_OFFSET);
4993 #ifdef MACHINE_CPROC_SP_OFFSET
4994 fprintf_unfiltered (file,
4995 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4996 MACHINE_CPROC_SP_OFFSET);
4998 fprintf_unfiltered (file,
4999 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
5000 fprintf_unfiltered (file,
5001 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
5002 fprintf_unfiltered (file,
5003 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5005 fprintf_unfiltered (file,
5006 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
5007 fprintf_unfiltered (file,
5008 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5009 fprintf_unfiltered (file,
5010 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5011 fprintf_unfiltered (file,
5012 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
5014 fprintf_unfiltered (file,
5015 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5016 MIPS_LAST_ARG_REGNUM,
5017 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
5018 fprintf_unfiltered (file,
5019 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
5021 fprintf_unfiltered (file,
5022 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
5023 fprintf_unfiltered (file,
5024 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
5025 MIPS_SAVED_REGSIZE);
5026 fprintf_unfiltered (file,
5027 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
5028 fprintf_unfiltered (file,
5029 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
5030 XSTRING (MSYMBOL_SIZE (MSYM)));
5031 fprintf_unfiltered (file,
5032 "mips_dump_tdep: OP_LDFPR = used?\n");
5033 fprintf_unfiltered (file,
5034 "mips_dump_tdep: OP_LDGPR = used?\n");
5035 fprintf_unfiltered (file,
5036 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
5037 fprintf_unfiltered (file,
5038 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
5039 fprintf_unfiltered (file,
5040 "mips_dump_tdep: PRID_REGNUM = %d\n",
5042 fprintf_unfiltered (file,
5043 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
5044 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
5045 fprintf_unfiltered (file,
5046 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5047 fprintf_unfiltered (file,
5048 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5049 fprintf_unfiltered (file,
5050 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5051 fprintf_unfiltered (file,
5052 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5053 fprintf_unfiltered (file,
5054 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5055 fprintf_unfiltered (file,
5056 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5057 fprintf_unfiltered (file,
5058 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5059 fprintf_unfiltered (file,
5060 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5061 fprintf_unfiltered (file,
5062 "mips_dump_tdep: PROC_PC_REG = function?\n");
5063 fprintf_unfiltered (file,
5064 "mips_dump_tdep: PROC_REG_MASK = function?\n");
5065 fprintf_unfiltered (file,
5066 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5067 fprintf_unfiltered (file,
5068 "mips_dump_tdep: PROC_SYMBOL = function?\n");
5069 fprintf_unfiltered (file,
5070 "mips_dump_tdep: PS_REGNUM = %d\n",
5072 fprintf_unfiltered (file,
5073 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
5075 fprintf_unfiltered (file,
5076 "mips_dump_tdep: RA_REGNUM = %d\n",
5078 fprintf_unfiltered (file,
5079 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
5080 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
5081 fprintf_unfiltered (file,
5082 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
5083 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
5084 fprintf_unfiltered (file,
5085 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
5086 fprintf_unfiltered (file,
5087 "mips_dump_tdep: ROUND_DOWN = function?\n");
5088 fprintf_unfiltered (file,
5089 "mips_dump_tdep: ROUND_UP = function?\n");
5091 fprintf_unfiltered (file,
5092 "mips_dump_tdep: SAVED_BYTES = %d\n",
5096 fprintf_unfiltered (file,
5097 "mips_dump_tdep: SAVED_FP = %d\n",
5101 fprintf_unfiltered (file,
5102 "mips_dump_tdep: SAVED_PC = %d\n",
5105 fprintf_unfiltered (file,
5106 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5107 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
5108 fprintf_unfiltered (file,
5109 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
5110 fprintf_unfiltered (file,
5111 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
5113 fprintf_unfiltered (file,
5114 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
5115 SIGFRAME_FPREGSAVE_OFF);
5116 fprintf_unfiltered (file,
5117 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
5119 fprintf_unfiltered (file,
5120 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
5121 SIGFRAME_REGSAVE_OFF);
5122 fprintf_unfiltered (file,
5123 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
5125 fprintf_unfiltered (file,
5126 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
5127 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
5128 fprintf_unfiltered (file,
5129 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5130 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
5131 fprintf_unfiltered (file,
5132 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5133 SOFTWARE_SINGLE_STEP_P ());
5134 fprintf_unfiltered (file,
5135 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5136 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
5137 #ifdef STACK_END_ADDR
5138 fprintf_unfiltered (file,
5139 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5142 fprintf_unfiltered (file,
5143 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5144 XSTRING (STEP_SKIPS_DELAY (PC)));
5145 fprintf_unfiltered (file,
5146 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5147 STEP_SKIPS_DELAY_P);
5148 fprintf_unfiltered (file,
5149 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5150 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
5151 fprintf_unfiltered (file,
5152 "mips_dump_tdep: T9_REGNUM = %d\n",
5154 fprintf_unfiltered (file,
5155 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5156 fprintf_unfiltered (file,
5157 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5158 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
5159 fprintf_unfiltered (file,
5160 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
5161 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
5162 fprintf_unfiltered (file,
5163 "mips_dump_tdep: TARGET_MIPS = used?\n");
5164 fprintf_unfiltered (file,
5165 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
5166 XSTRING (TM_PRINT_INSN_MACH));
5168 fprintf_unfiltered (file,
5169 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5170 XSTRING (TRACE_CLEAR (THREAD, STATE)));
5173 fprintf_unfiltered (file,
5174 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
5177 #ifdef TRACE_FLAVOR_SIZE
5178 fprintf_unfiltered (file,
5179 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5183 fprintf_unfiltered (file,
5184 "mips_dump_tdep: TRACE_SET # %s\n",
5185 XSTRING (TRACE_SET (X,STATE)));
5187 fprintf_unfiltered (file,
5188 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
5189 #ifdef UNUSED_REGNUM
5190 fprintf_unfiltered (file,
5191 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
5194 fprintf_unfiltered (file,
5195 "mips_dump_tdep: V0_REGNUM = %d\n",
5197 fprintf_unfiltered (file,
5198 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5199 (long) VM_MIN_ADDRESS);
5201 fprintf_unfiltered (file,
5202 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
5205 fprintf_unfiltered (file,
5206 "mips_dump_tdep: ZERO_REGNUM = %d\n",
5208 fprintf_unfiltered (file,
5209 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
5212 fprintf_unfiltered (file,
5213 "mips_dump_tdep: OS ABI = %s\n",
5214 gdbarch_osabi_name (tdep->osabi));
5218 _initialize_mips_tdep (void)
5220 static struct cmd_list_element *mipsfpulist = NULL;
5221 struct cmd_list_element *c;
5223 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
5224 if (MIPS_ABI_LAST + 1
5225 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
5226 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
5228 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
5229 if (!tm_print_insn) /* Someone may have already set it */
5230 tm_print_insn = gdb_print_insn_mips;
5232 /* Add root prefix command for all "set mips"/"show mips" commands */
5233 add_prefix_cmd ("mips", no_class, set_mips_command,
5234 "Various MIPS specific commands.",
5235 &setmipscmdlist, "set mips ", 0, &setlist);
5237 add_prefix_cmd ("mips", no_class, show_mips_command,
5238 "Various MIPS specific commands.",
5239 &showmipscmdlist, "show mips ", 0, &showlist);
5241 /* Allow the user to override the saved register size. */
5242 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5245 &mips_saved_regsize_string, "\
5246 Set size of general purpose registers saved on the stack.\n\
5247 This option can be set to one of:\n\
5248 32 - Force GDB to treat saved GP registers as 32-bit\n\
5249 64 - Force GDB to treat saved GP registers as 64-bit\n\
5250 auto - Allow GDB to use the target's default setting or autodetect the\n\
5251 saved GP register size from information contained in the executable.\n\
5256 /* Allow the user to override the argument stack size. */
5257 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5260 &mips_stack_argsize_string, "\
5261 Set the amount of stack space reserved for each argument.\n\
5262 This option can be set to one of:\n\
5263 32 - Force GDB to allocate 32-bit chunks per argument\n\
5264 64 - Force GDB to allocate 64-bit chunks per argument\n\
5265 auto - Allow GDB to determine the correct setting from the current\n\
5266 target and executable (default)",
5270 /* Allow the user to override the ABI. */
5271 c = add_set_enum_cmd
5272 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
5273 "Set the ABI used by this program.\n"
5274 "This option can be set to one of:\n"
5275 " auto - the default ABI associated with the current binary\n"
5283 add_show_from_set (c, &showmipscmdlist);
5284 set_cmd_sfunc (c, mips_abi_update);
5286 /* Let the user turn off floating point and set the fence post for
5287 heuristic_proc_start. */
5289 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
5290 "Set use of MIPS floating-point coprocessor.",
5291 &mipsfpulist, "set mipsfpu ", 0, &setlist);
5292 add_cmd ("single", class_support, set_mipsfpu_single_command,
5293 "Select single-precision MIPS floating-point coprocessor.",
5295 add_cmd ("double", class_support, set_mipsfpu_double_command,
5296 "Select double-precision MIPS floating-point coprocessor.",
5298 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
5299 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
5300 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
5301 add_cmd ("none", class_support, set_mipsfpu_none_command,
5302 "Select no MIPS floating-point coprocessor.",
5304 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
5305 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
5306 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
5307 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
5308 "Select MIPS floating-point coprocessor automatically.",
5310 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
5311 "Show current use of MIPS floating-point coprocessor target.",
5314 /* We really would like to have both "0" and "unlimited" work, but
5315 command.c doesn't deal with that. So make it a var_zinteger
5316 because the user can always use "999999" or some such for unlimited. */
5317 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
5318 (char *) &heuristic_fence_post,
5320 Set the distance searched for the start of a function.\n\
5321 If you are debugging a stripped executable, GDB needs to search through the\n\
5322 program for the start of a function. This command sets the distance of the\n\
5323 search. The only need to set it is when debugging a stripped executable.",
5325 /* We need to throw away the frame cache when we set this, since it
5326 might change our ability to get backtraces. */
5327 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
5328 add_show_from_set (c, &showlist);
5330 /* Allow the user to control whether the upper bits of 64-bit
5331 addresses should be zeroed. */
5332 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
5333 Set zeroing of upper 32 bits of 64-bit addresses.\n\
5334 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5335 allow GDB to determine the correct value.\n", "\
5336 Show zeroing of upper 32 bits of 64-bit addresses.",
5337 NULL, show_mask_address,
5338 &setmipscmdlist, &showmipscmdlist);
5340 /* Allow the user to control the size of 32 bit registers within the
5341 raw remote packet. */
5342 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5345 (char *)&mips64_transfers_32bit_regs_p, "\
5346 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5347 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5348 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5349 64 bits for others. Use \"off\" to disable compatibility mode",
5353 /* Debug this files internals. */
5354 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
5355 &mips_debug, "Set mips debugging.\n\
5356 When non-zero, mips specific debugging is enabled.", &setdebuglist),