1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack;
44 /* FIXME! this code assumes 4-byte instructions. */
45 #define MIPS_INSTLEN 4 /* Length of an instruction */
46 #define MIPS_NUMREGS 32 /* Number of integer or float registers */
47 typedef unsigned long t_inst; /* Integer big enough to hold an instruction */
50 static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR));
53 static int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *));
55 static void mips_print_register PARAMS ((int, int));
57 static mips_extra_func_info_t
58 heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *));
60 static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR));
62 static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int));
64 static void mips_set_fpu_command PARAMS ((char *, int,
65 struct cmd_list_element *));
67 static void mips_show_fpu_command PARAMS ((char *, int,
68 struct cmd_list_element *));
70 void mips_set_processor_type_command PARAMS ((char *, int));
72 int mips_set_processor_type PARAMS ((char *));
74 static void mips_show_processor_type_command PARAMS ((char *, int));
76 static void reinit_frame_cache_sfunc PARAMS ((char *, int,
77 struct cmd_list_element *));
79 static mips_extra_func_info_t
80 find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame));
82 static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc,
83 mips_extra_func_info_t proc_desc));
85 /* This value is the model of MIPS in use. It is derived from the value
86 of the PrID register. */
88 char *mips_processor_type;
90 char *tmp_mips_processor_type;
92 /* Some MIPS boards don't support floating point, so we permit the
93 user to turn it off. */
95 enum mips_fpu_type mips_fpu;
97 static char *mips_fpu_string;
99 /* A set of original names, to be used when restoring back to generic
100 registers from a specific set. */
102 char *mips_generic_reg_names[] = REGISTER_NAMES;
104 /* Names of IDT R3041 registers. */
106 char *mips_r3041_reg_names[] = {
107 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
108 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
109 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
110 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
111 "sr", "lo", "hi", "bad", "cause","pc",
112 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
113 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
114 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
115 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
116 "fsr", "fir", "fp", "",
117 "", "", "bus", "ccfg", "", "", "", "",
118 "", "", "port", "cmp", "", "", "epc", "prid",
121 /* Names of IDT R3051 registers. */
123 char *mips_r3051_reg_names[] = {
124 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
125 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
126 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
127 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
128 "sr", "lo", "hi", "bad", "cause","pc",
129 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
130 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
131 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
132 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
133 "fsr", "fir", "fp", "",
134 "inx", "rand", "elo", "", "ctxt", "", "", "",
135 "", "", "ehi", "", "", "", "epc", "prid",
138 /* Names of IDT R3081 registers. */
140 char *mips_r3081_reg_names[] = {
141 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
142 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
143 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
144 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
145 "sr", "lo", "hi", "bad", "cause","pc",
146 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
147 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
148 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
149 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
150 "fsr", "fir", "fp", "",
151 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
152 "", "", "ehi", "", "", "", "epc", "prid",
155 /* Names of LSI 33k registers. */
157 char *mips_lsi33k_reg_names[] = {
158 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
159 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
160 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
161 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
162 "epc", "hi", "lo", "sr", "cause","badvaddr",
163 "dcic", "bpc", "bda", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
165 "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "",
168 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "",
175 } mips_processor_type_table[] = {
176 { "generic", mips_generic_reg_names },
177 { "r3041", mips_r3041_reg_names },
178 { "r3051", mips_r3051_reg_names },
179 { "r3071", mips_r3081_reg_names },
180 { "r3081", mips_r3081_reg_names },
181 { "lsi33k", mips_lsi33k_reg_names },
185 /* Heuristic_proc_start may hunt through the text section for a long
186 time across a 2400 baud serial line. Allows the user to limit this
189 static unsigned int heuristic_fence_post = 0;
191 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
192 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
193 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
194 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
195 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
196 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
197 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
198 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
199 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
200 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
201 #define _PROC_MAGIC_ 0x0F0F0F0F
202 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
203 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
205 struct linked_proc_info
207 struct mips_extra_func_info info;
208 struct linked_proc_info *next;
209 } *linked_proc_desc_table = NULL;
212 /* This returns the PC of the first inst after the prologue. If we can't
213 find the prologue, then return 0. */
216 after_prologue (pc, proc_desc)
218 mips_extra_func_info_t proc_desc;
220 struct symtab_and_line sal;
221 CORE_ADDR func_addr, func_end;
224 proc_desc = find_proc_desc (pc, NULL);
228 /* If function is frameless, then we need to do it the hard way. I
229 strongly suspect that frameless always means prologueless... */
230 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
231 && PROC_FRAME_OFFSET (proc_desc) == 0)
235 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
236 return 0; /* Unknown */
238 sal = find_pc_line (func_addr, 0);
240 if (sal.end < func_end)
243 /* The line after the prologue is after the end of the function. In this
244 case, tell the caller to find the prologue the hard way. */
249 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
253 mips_find_saved_regs (fci)
254 struct frame_info *fci;
257 CORE_ADDR reg_position;
258 /* r0 bit means kernel trap */
260 /* What registers have been saved? Bitmasks. */
261 unsigned long gen_mask, float_mask;
262 mips_extra_func_info_t proc_desc;
264 fci->saved_regs = (struct frame_saved_regs *)
265 obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs));
266 memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs));
268 /* If it is the frame for sigtramp, the saved registers are located
269 in a sigcontext structure somewhere on the stack.
270 If the stack layout for sigtramp changes we might have to change these
271 constants and the companion fixup_sigtramp in mdebugread.c */
272 #ifndef SIGFRAME_BASE
273 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
274 above the sigtramp frame. */
275 #define SIGFRAME_BASE MIPS_REGSIZE
276 /* FIXME! Are these correct?? */
277 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
278 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
279 #define SIGFRAME_FPREGSAVE_OFF \
280 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
282 #ifndef SIGFRAME_REG_SIZE
283 /* FIXME! Is this correct?? */
284 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
286 if (fci->signal_handler_caller)
288 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
290 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
291 + ireg * SIGFRAME_REG_SIZE;
292 fci->saved_regs->regs[ireg] = reg_position;
294 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
296 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
297 + ireg * SIGFRAME_REG_SIZE;
298 fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position;
300 fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
304 proc_desc = fci->proc_desc;
305 if (proc_desc == NULL)
306 /* I'm not sure how/whether this can happen. Normally when we can't
307 find a proc_desc, we "synthesize" one using heuristic_proc_desc
308 and set the saved_regs right away. */
311 kernel_trap = PROC_REG_MASK(proc_desc) & 1;
312 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc);
313 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc);
315 if (/* In any frame other than the innermost, we assume that all
316 registers have been saved. This assumes that all register
317 saves in a function happen before the first function
321 /* In a dummy frame we know exactly where things are saved. */
322 && !PROC_DESC_IS_DUMMY (proc_desc)
324 /* Don't bother unless we are inside a function prologue. Outside the
325 prologue, we know where everything is. */
327 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
329 /* Not sure exactly what kernel_trap means, but if it means
330 the kernel saves the registers without a prologue doing it,
331 we better not examine the prologue to see whether registers
332 have been saved yet. */
335 /* We need to figure out whether the registers that the proc_desc
336 claims are saved have been saved yet. */
340 char buf[MIPS_INSTLEN];
343 /* Bitmasks; set if we have found a save for the register. */
344 unsigned long gen_save_found = 0;
345 unsigned long float_save_found = 0;
347 for (addr = PROC_LOW_ADDR (proc_desc);
348 addr < fci->pc /*&& (gen_mask != gen_save_found
349 || float_mask != float_save_found)*/;
350 addr += MIPS_INSTLEN)
352 status = read_memory_nobpt (addr, buf, MIPS_INSTLEN);
354 memory_error (status, addr);
355 inst = extract_unsigned_integer (buf, MIPS_INSTLEN);
356 if (/* sw reg,n($sp) */
357 (inst & 0xffe00000) == 0xafa00000
360 || (inst & 0xffe00000) == 0xafc00000
363 || (inst & 0xffe00000) == 0xffa00000)
365 /* It might be possible to use the instruction to
366 find the offset, rather than the code below which
367 is based on things being in a certain order in the
368 frame, but figuring out what the instruction's offset
369 is relative to might be a little tricky. */
370 int reg = (inst & 0x001f0000) >> 16;
371 gen_save_found |= (1 << reg);
373 else if (/* swc1 freg,n($sp) */
374 (inst & 0xffe00000) == 0xe7a00000
376 /* swc1 freg,n($r30) */
377 || (inst & 0xffe00000) == 0xe7c00000
379 /* sdc1 freg,n($sp) */
380 || (inst & 0xffe00000) == 0xf7a00000)
383 int reg = ((inst & 0x001f0000) >> 16);
384 float_save_found |= (1 << reg);
387 gen_mask = gen_save_found;
388 float_mask = float_save_found;
391 /* Fill in the offsets for the registers which gen_mask says
393 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
394 for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1)
395 if (gen_mask & 0x80000000)
397 fci->saved_regs->regs[ireg] = reg_position;
398 reg_position -= MIPS_REGSIZE;
400 /* Fill in the offsets for the registers which float_mask says
402 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
404 /* The freg_offset points to where the first *double* register
405 is saved. So skip to the high-order word. */
406 if (! GDB_TARGET_IS_MIPS64)
409 /* FIXME! this code looks scary...
410 * Looks like it's trying to do stuff with a register,
413 for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1)
414 if (float_mask & 0x80000000)
416 fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position;
417 reg_position -= MIPS_REGSIZE;
420 fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM];
424 read_next_frame_reg(fi, regno)
425 struct frame_info *fi;
428 for (; fi; fi = fi->next)
430 /* We have to get the saved sp from the sigcontext
431 if it is a signal handler frame. */
432 if (regno == SP_REGNUM && !fi->signal_handler_caller)
436 if (fi->saved_regs == NULL)
437 mips_find_saved_regs (fi);
438 if (fi->saved_regs->regs[regno])
439 return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE);
442 return read_register (regno);
445 /* mips_addr_bits_remove - remove useless address bits */
448 mips_addr_bits_remove (addr)
451 #if GDB_TARGET_IS_MIPS64
452 if ((addr >> 32 == (CORE_ADDR)0xffffffff)
453 && (strcmp(target_shortname,"pmon")==0
454 || strcmp(target_shortname,"ddb")==0
455 || strcmp(target_shortname,"sim")==0))
457 /* This hack is a work-around for existing boards using PMON,
458 the simulator, and any other 64-bit targets that doesn't have
459 true 64-bit addressing. On these targets, the upper 32 bits
460 of addresses are ignored by the hardware. Thus, the PC or SP
461 are likely to have been sign extended to all 1s by instruction
462 sequences that load 32-bit addresses. For example, a typical
463 piece of code that loads an address is this:
464 lui $r2, <upper 16 bits>
465 ori $r2, <lower 16 bits>
466 But the lui sign-extends the value such that the upper 32 bits
467 may be all 1s. The workaround is simply to mask off these bits.
468 In the future, gcc may be changed to support true 64-bit
469 addressing, and this masking will have to be disabled. */
470 addr &= (CORE_ADDR)0xffffffff;
478 mips_frame_saved_pc(frame)
479 struct frame_info *frame;
482 mips_extra_func_info_t proc_desc = frame->proc_desc;
483 /* We have to get the saved pc from the sigcontext
484 if it is a signal handler frame. */
485 int pcreg = frame->signal_handler_caller ? PC_REGNUM
486 : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM);
488 if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc))
489 saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE);
491 saved_pc = read_next_frame_reg(frame, pcreg);
493 return ADDR_BITS_REMOVE (saved_pc);
496 static struct mips_extra_func_info temp_proc_desc;
497 static struct frame_saved_regs temp_saved_regs;
499 /* This fencepost looks highly suspicious to me. Removing it also
500 seems suspicious as it could affect remote debugging across serial
504 heuristic_proc_start(pc)
507 CORE_ADDR start_pc = pc;
508 CORE_ADDR fence = start_pc - heuristic_fence_post;
510 if (start_pc == 0) return 0;
512 if (heuristic_fence_post == UINT_MAX
513 || fence < VM_MIN_ADDRESS)
514 fence = VM_MIN_ADDRESS;
516 /* search back for previous return */
517 for (start_pc -= MIPS_INSTLEN; ; start_pc -= MIPS_INSTLEN) /* FIXME!! */
518 if (start_pc < fence)
520 /* It's not clear to me why we reach this point when
521 stop_soon_quietly, but with this test, at least we
522 don't print out warnings for every child forked (eg, on
523 decstation). 22apr93 rich@cygnus.com. */
524 if (!stop_soon_quietly)
526 static int blurb_printed = 0;
528 if (fence == VM_MIN_ADDRESS)
529 warning("Hit beginning of text section without finding");
531 warning("Hit heuristic-fence-post without finding");
533 warning("enclosing function for address 0x%s", paddr (pc));
537 This warning occurs if you are debugging a function without any symbols\n\
538 (for example, in a stripped executable). In that case, you may wish to\n\
539 increase the size of the search with the `set heuristic-fence-post' command.\n\
541 Otherwise, you told GDB there was a function where there isn't one, or\n\
542 (more likely) you have encountered a bug in GDB.\n");
549 else if (ABOUT_TO_RETURN(start_pc))
552 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
554 /* skip nops (usually 1) 0 - is this */
555 while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0)
556 start_pc += MIPS_INSTLEN;
561 static mips_extra_func_info_t
562 heuristic_proc_desc(start_pc, limit_pc, next_frame)
563 CORE_ADDR start_pc, limit_pc;
564 struct frame_info *next_frame;
566 CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM);
568 unsigned long frame_size;
569 unsigned long r30_frame_size = 0;
570 int has_frame_reg = 0;
571 CORE_ADDR reg30 = 0; /* Value of $r30. Used by gcc for frame-pointer */
572 unsigned long reg_mask = 0;
574 if (start_pc == 0) return NULL;
575 memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc));
576 memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs));
577 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
579 if (start_pc + 200 < limit_pc)
580 limit_pc = start_pc + 200;
583 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) {
584 char buf[MIPS_INSTLEN];
588 status = (unsigned long) read_memory_nobpt (cur_pc, buf, MIPS_INSTLEN); /* FIXME!! */
589 if (status) memory_error (status, cur_pc);
590 word = (unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN); /* FIXME!! */
592 if ((word & 0xFFFF0000) == 0x27bd0000 /* addiu $sp,$sp,-i */
593 || (word & 0xFFFF0000) == 0x23bd0000 /* addi $sp,$sp,-i */
594 || (word & 0xFFFF0000) == 0x67bd0000) { /* daddiu $sp,$sp,-i */
596 frame_size += (-word) & 0xffff;
598 /* Exit loop if a positive stack adjustment is found, which
599 usually means that the stack cleanup code in the function
600 epilogue is reached. */
603 else if ((word & 0xFFE00000) == 0xafa00000) { /* sw reg,offset($sp) */
604 int reg = (word & 0x001F0000) >> 16;
605 reg_mask |= 1 << reg;
606 temp_saved_regs.regs[reg] = sp + (word & 0xffff);
608 else if ((word & 0xFFE00000) == 0xffa00000) { /* sd reg,offset($sp) */
609 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
610 but the register size used is only 32 bits. Make the address
611 for the saved register point to the lower 32 bits. */
612 int reg = (word & 0x001F0000) >> 16;
613 reg_mask |= 1 << reg;
614 temp_saved_regs.regs[reg] = sp + (word & 0xffff) + 8 - MIPS_REGSIZE;
616 else if ((word & 0xFFFF0000) == 0x27be0000) { /* addiu $30,$sp,size */
617 /* Old gcc frame, r30 is virtual frame pointer. */
618 if ((word & 0xffff) != frame_size)
619 reg30 = sp + (word & 0xffff);
620 else if (!has_frame_reg) {
621 unsigned alloca_adjust;
623 reg30 = read_next_frame_reg(next_frame, 30);
624 alloca_adjust = (unsigned)(reg30 - (sp + (word & 0xffff)));
625 if (alloca_adjust > 0) {
626 /* FP > SP + frame_size. This may be because
627 * of an alloca or somethings similar.
628 * Fix sp to "pre-alloca" value, and try again.
635 else if ((word & 0xFFFFFFFB) == 0x03a0f021) { /* mov $30,$sp */
636 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
637 if (!has_frame_reg) {
638 unsigned alloca_adjust;
640 reg30 = read_next_frame_reg(next_frame, 30);
641 r30_frame_size = frame_size;
642 alloca_adjust = (unsigned)(reg30 - sp);
643 if (alloca_adjust > 0) {
644 /* FP > SP + frame_size. This may be because
645 * of an alloca or somethings similar.
646 * Fix sp to "pre-alloca" value, and try again.
653 else if ((word & 0xFFE00000) == 0xafc00000) { /* sw reg,offset($30) */
654 int reg = (word & 0x001F0000) >> 16;
655 reg_mask |= 1 << reg;
656 temp_saved_regs.regs[reg] = reg30 + (word & 0xffff);
660 PROC_FRAME_REG(&temp_proc_desc) = 30;
661 PROC_FRAME_OFFSET(&temp_proc_desc) = r30_frame_size;
664 PROC_FRAME_REG(&temp_proc_desc) = SP_REGNUM;
665 PROC_FRAME_OFFSET(&temp_proc_desc) = frame_size;
667 PROC_REG_MASK(&temp_proc_desc) = reg_mask;
668 PROC_PC_REG(&temp_proc_desc) = RA_REGNUM;
669 return &temp_proc_desc;
672 static mips_extra_func_info_t
673 find_proc_desc (pc, next_frame)
675 struct frame_info *next_frame;
677 mips_extra_func_info_t proc_desc;
678 struct block *b = block_for_pc(pc);
682 find_pc_partial_function (pc, NULL, &startaddr, NULL);
683 if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0))
687 if (startaddr > BLOCK_START (b))
688 /* This is the "pathological" case referred to in a comment in
689 print_frame_info. It might be better to move this check into
693 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE,
697 /* If we never found a PDR for this function in symbol reading, then
698 examine prologues to find the information. */
699 if (sym && ((mips_extra_func_info_t) SYMBOL_VALUE (sym))->pdr.framereg == -1)
704 /* IF this is the topmost frame AND
705 * (this proc does not have debugging information OR
706 * the PC is in the procedure prologue)
707 * THEN create a "heuristic" proc_desc (by analyzing
708 * the actual code) to replace the "official" proc_desc.
710 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
711 if (next_frame == NULL) {
712 struct symtab_and_line val;
713 struct symbol *proc_symbol =
714 PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc);
717 val = find_pc_line (BLOCK_START
718 (SYMBOL_BLOCK_VALUE(proc_symbol)),
720 val.pc = val.end ? val.end : pc;
722 if (!proc_symbol || pc < val.pc) {
723 mips_extra_func_info_t found_heuristic =
724 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
727 proc_desc = found_heuristic;
733 /* Is linked_proc_desc_table really necessary? It only seems to be used
734 by procedure call dummys. However, the procedures being called ought
735 to have their own proc_descs, and even if they don't,
736 heuristic_proc_desc knows how to create them! */
738 register struct linked_proc_info *link;
740 for (link = linked_proc_desc_table; link; link = link->next)
741 if (PROC_LOW_ADDR(&link->info) <= pc
742 && PROC_HIGH_ADDR(&link->info) > pc)
746 startaddr = heuristic_proc_start (pc);
749 heuristic_proc_desc (startaddr, pc, next_frame);
755 get_frame_pointer(frame, proc_desc)
756 struct frame_info *frame;
757 mips_extra_func_info_t proc_desc;
759 return ADDR_BITS_REMOVE (read_next_frame_reg (frame,
760 PROC_FRAME_REG(proc_desc)) + PROC_FRAME_OFFSET(proc_desc));
763 mips_extra_func_info_t cached_proc_desc;
766 mips_frame_chain(frame)
767 struct frame_info *frame;
769 mips_extra_func_info_t proc_desc;
770 CORE_ADDR saved_pc = FRAME_SAVED_PC(frame);
772 if (saved_pc == 0 || inside_entry_file (saved_pc))
775 proc_desc = find_proc_desc(saved_pc, frame);
779 cached_proc_desc = proc_desc;
781 /* If no frame pointer and frame size is zero, we must be at end
782 of stack (or otherwise hosed). If we don't check frame size,
783 we loop forever if we see a zero size frame. */
784 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
785 && PROC_FRAME_OFFSET (proc_desc) == 0
786 /* The previous frame from a sigtramp frame might be frameless
787 and have frame size zero. */
788 && !frame->signal_handler_caller)
791 return get_frame_pointer (frame, proc_desc);
795 init_extra_frame_info(fci)
796 struct frame_info *fci;
800 /* Use proc_desc calculated in frame_chain */
801 mips_extra_func_info_t proc_desc =
802 fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next);
804 fci->saved_regs = NULL;
806 proc_desc == &temp_proc_desc ? 0 : proc_desc;
809 /* Fixup frame-pointer - only needed for top frame */
810 /* This may not be quite right, if proc has a real frame register.
811 Get the value of the frame relative sp, procedure might have been
812 interrupted by a signal at it's very start. */
813 if (fci->pc == PROC_LOW_ADDR (proc_desc)
814 && !PROC_DESC_IS_DUMMY (proc_desc))
815 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
817 fci->frame = get_frame_pointer (fci->next, proc_desc);
819 if (proc_desc == &temp_proc_desc)
823 /* Do not set the saved registers for a sigtramp frame,
824 mips_find_saved_registers will do that for us.
825 We can't use fci->signal_handler_caller, it is not yet set. */
826 find_pc_partial_function (fci->pc, &name,
827 (CORE_ADDR *)NULL,(CORE_ADDR *)NULL);
828 if (!IN_SIGTRAMP (fci->pc, name))
830 fci->saved_regs = (struct frame_saved_regs*)
831 obstack_alloc (&frame_cache_obstack,
832 sizeof (struct frame_saved_regs));
833 *fci->saved_regs = temp_saved_regs;
834 fci->saved_regs->regs[PC_REGNUM]
835 = fci->saved_regs->regs[RA_REGNUM];
839 /* hack: if argument regs are saved, guess these contain args */
840 fci->num_args = -1; /* assume we can't tell how many args for now */
841 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
843 if (PROC_REG_MASK(proc_desc) & (1 << regnum))
845 fci->num_args = regnum - A0_REGNUM + 1;
852 /* MIPS stack frames are almost impenetrable. When execution stops,
853 we basically have to look at symbol information for the function
854 that we stopped in, which tells us *which* register (if any) is
855 the base of the frame pointer, and what offset from that register
856 the frame itself is at.
858 This presents a problem when trying to examine a stack in memory
859 (that isn't executing at the moment), using the "frame" command. We
860 don't have a PC, nor do we have any registers except SP.
862 This routine takes two arguments, SP and PC, and tries to make the
863 cached frames look as if these two arguments defined a frame on the
864 cache. This allows the rest of info frame to extract the important
865 arguments without difficulty. */
868 setup_arbitrary_frame (argc, argv)
873 error ("MIPS frame specifications require two arguments: sp and pc");
875 return create_new_frame (argv[0], argv[1]);
880 mips_pc_in_call_dummy (pc)
883 return pc >= CALL_DUMMY_ADDRESS ()
884 && pc <= CALL_DUMMY_ADDRESS () + DECR_PC_AFTER_BREAK;
888 mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
893 CORE_ADDR struct_addr;
901 /* Macros to round N up or down to the next A boundary; A must be
903 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
904 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
906 /* First ensure that the stack and structure return address (if any)
907 are properly aligned. The stack has to be 64-bit aligned even
908 on 32-bit machines, because doubles must be 64-bit aligned. */
909 sp = ROUND_DOWN (sp, 8);
910 struct_addr = ROUND_DOWN (struct_addr, MIPS_REGSIZE);
912 /* Now make space on the stack for the args. We allocate more
913 than necessary for EABI, because the first few arguments are
914 passed in registers, but that's OK. */
915 for (argnum = 0; argnum < nargs; argnum++)
916 len += ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args[argnum])), MIPS_REGSIZE);
917 sp -= ROUND_UP (len, MIPS_REGSIZE);
919 /* Initialize the integer and float register pointers. */
921 float_argreg = FPA0_REGNUM;
923 /* the struct_return pointer occupies the first parameter-passing reg */
925 write_register (argreg++, struct_addr);
927 /* The offset onto the stack at which we will start copying parameters
928 (after the registers are used up) begins at 16 in the old ABI.
929 This leaves room for the "home" area for register parameters. */
930 stack_offset = MIPS_EABI ? 0 : MIPS_REGSIZE * 4;
932 /* Now load as many as possible of the first arguments into
933 registers, and push the rest onto the stack. Loop thru args
934 from first to last. */
935 for (argnum = 0; argnum < nargs; argnum++)
938 char valbuf[REGISTER_RAW_SIZE(A0_REGNUM)];
939 value_ptr arg = args[argnum];
940 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
941 int len = TYPE_LENGTH (arg_type);
942 enum type_code typecode = TYPE_CODE (arg_type);
944 /* The EABI passes structures that fit in a register by value.
945 In all other cases, pass the structure by reference. */
946 if (typecode == TYPE_CODE_STRUCT && (!MIPS_EABI || len > MIPS_REGSIZE))
948 store_address (valbuf, MIPS_REGSIZE, VALUE_ADDRESS (arg));
953 val = (char *)VALUE_CONTENTS (arg);
955 /* 32-bit ABIs always start floating point arguments in an
956 even-numbered floating point register. */
957 if (!GDB_TARGET_IS_MIPS64 && typecode == TYPE_CODE_FLT
958 && (float_argreg & 1))
961 /* Floating point arguments passed in registers have to be
962 treated specially. On 32-bit architectures, doubles
963 are passed in register pairs; the even register gets
964 the low word, and the odd register gets the high word. */
965 if (typecode == TYPE_CODE_FLT
966 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM
967 && mips_fpu != MIPS_FPU_NONE)
969 if (!GDB_TARGET_IS_MIPS64 && len == 8)
971 int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0;
972 unsigned long regval;
974 regval = extract_unsigned_integer (val+low_offset, 4);
975 write_register (float_argreg++, regval); /* low word */
976 regval = extract_unsigned_integer (val+4-low_offset, 4);
977 write_register (float_argreg++, regval); /* high word */
982 CORE_ADDR regval = extract_address (val, len);
983 write_register (float_argreg++, regval);
986 /* If this is the old ABI, skip one or two general registers. */
988 argreg += GDB_TARGET_IS_MIPS64 ? 1 : 2;
992 /* Copy the argument to general registers or the stack in
993 register-sized pieces. Large arguments are split between
994 registers and stack. */
997 int partial_len = len < MIPS_REGSIZE ? len : MIPS_REGSIZE;
998 CORE_ADDR regval = extract_address (val, partial_len);
1000 if (argreg <= MIPS_LAST_ARG_REGNUM)
1002 /* It's a simple argument being passed in a general register. */
1003 write_register (argreg, regval);
1006 /* If this is the old ABI, prevent subsequent floating
1007 point arguments from being passed in floating point
1010 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
1014 /* Promote this portion of the argument to a register-sized
1015 chunk before pushing it on the stack. */
1016 char partial_buf[MIPS_REGSIZE];
1017 store_address (partial_buf, MIPS_REGSIZE, regval);
1018 write_memory (sp + stack_offset, partial_buf, MIPS_REGSIZE);
1019 stack_offset += MIPS_REGSIZE;
1028 /* Set the return address register to point to the entry
1029 point of the program, where a breakpoint lies in wait. */
1030 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS());
1032 /* Return adjusted stack pointer. */
1037 mips_push_register(CORE_ADDR *sp, int regno)
1039 char buffer[MAX_REGISTER_RAW_SIZE];
1040 int regsize = REGISTER_RAW_SIZE (regno);
1043 read_register_gen (regno, buffer);
1044 write_memory (*sp, buffer, regsize);
1047 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1048 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1051 mips_push_dummy_frame()
1054 struct linked_proc_info *link = (struct linked_proc_info*)
1055 xmalloc(sizeof(struct linked_proc_info));
1056 mips_extra_func_info_t proc_desc = &link->info;
1057 CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM));
1058 CORE_ADDR old_sp = sp;
1059 link->next = linked_proc_desc_table;
1060 linked_proc_desc_table = link;
1062 /* FIXME! are these correct ? */
1063 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1064 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1065 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1066 #define FLOAT_SINGLE_REG_SAVE_MASK \
1067 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1069 * The registers we must save are all those not preserved across
1070 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1071 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1072 * and FP Control/Status registers.
1075 * Dummy frame layout:
1078 * Saved MMHI, MMLO, FPC_CSR
1083 * Saved D18 (i.e. F19, F18)
1085 * Saved D0 (i.e. F1, F0)
1086 * CALL_DUMMY (subroutine stub; see tm-mips.h)
1087 * Parameter build area (not yet implemented)
1091 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1092 write_register (PUSH_FP_REGNUM, sp);
1093 PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM;
1094 PROC_FRAME_OFFSET(proc_desc) = 0;
1095 mips_push_register (&sp, PC_REGNUM);
1096 mips_push_register (&sp, HI_REGNUM);
1097 mips_push_register (&sp, LO_REGNUM);
1098 mips_push_register (&sp, mips_fpu == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
1100 /* Save general CPU registers */
1101 PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK;
1102 PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */
1103 for (ireg = 32; --ireg >= 0; )
1104 if (PROC_REG_MASK(proc_desc) & (1 << ireg))
1105 mips_push_register (&sp, ireg);
1107 /* Save floating point registers starting with high order word */
1108 PROC_FREG_MASK(proc_desc) =
1109 mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
1110 : mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
1111 PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */
1112 for (ireg = 32; --ireg >= 0; )
1113 if (PROC_FREG_MASK(proc_desc) & (1 << ireg))
1114 mips_push_register (&sp, ireg + FP0_REGNUM);
1116 /* Update the stack pointer. Set the procedure's starting and ending
1117 addresses to point to the place on the stack where we'll be writing the
1118 dummy code (in mips_push_arguments). */
1119 write_register (SP_REGNUM, sp);
1120 PROC_LOW_ADDR(proc_desc) = CALL_DUMMY_ADDRESS();
1121 PROC_HIGH_ADDR(proc_desc) = CALL_DUMMY_ADDRESS() + 4;
1122 SET_PROC_DESC_IS_DUMMY(proc_desc);
1123 PROC_PC_REG(proc_desc) = RA_REGNUM;
1129 register int regnum;
1130 struct frame_info *frame = get_current_frame ();
1131 CORE_ADDR new_sp = FRAME_FP (frame);
1133 mips_extra_func_info_t proc_desc = frame->proc_desc;
1135 write_register (PC_REGNUM, FRAME_SAVED_PC(frame));
1136 if (frame->saved_regs == NULL)
1137 mips_find_saved_regs (frame);
1140 for (regnum = MIPS_NUMREGS; --regnum >= 0; )
1141 if (PROC_REG_MASK(proc_desc) & (1 << regnum))
1142 write_register (regnum,
1143 read_memory_integer (frame->saved_regs->regs[regnum],
1145 for (regnum = MIPS_NUMREGS; --regnum >= 0; )
1146 if (PROC_FREG_MASK(proc_desc) & (1 << regnum))
1147 write_register (regnum + FP0_REGNUM,
1148 read_memory_integer (frame->saved_regs->regs[regnum + FP0_REGNUM], MIPS_REGSIZE));
1150 write_register (SP_REGNUM, new_sp);
1151 flush_cached_frames ();
1153 if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc))
1155 struct linked_proc_info *pi_ptr, *prev_ptr;
1157 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
1159 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
1161 if (&pi_ptr->info == proc_desc)
1166 error ("Can't locate dummy extra frame info\n");
1168 if (prev_ptr != NULL)
1169 prev_ptr->next = pi_ptr->next;
1171 linked_proc_desc_table = pi_ptr->next;
1175 write_register (HI_REGNUM,
1176 read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE));
1177 write_register (LO_REGNUM,
1178 read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE));
1179 if (mips_fpu != MIPS_FPU_NONE)
1180 write_register (FCRCS_REGNUM,
1181 read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE));
1186 mips_print_register (regnum, all)
1189 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1191 /* Get the data in raw format. */
1192 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1194 printf_filtered ("%s: [Invalid]", reg_names[regnum]);
1198 /* If an even floating pointer register, also print as double. */
1199 if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+MIPS_NUMREGS
1200 && !((regnum-FP0_REGNUM) & 1))
1202 char dbuffer[MAX_REGISTER_RAW_SIZE];
1204 read_relative_register_raw_bytes (regnum, dbuffer);
1205 read_relative_register_raw_bytes (regnum+1, dbuffer+4); /* FIXME!! */
1206 #ifdef REGISTER_CONVERT_TO_TYPE
1207 REGISTER_CONVERT_TO_TYPE(regnum, builtin_type_double, dbuffer);
1209 printf_filtered ("(d%d: ", regnum-FP0_REGNUM);
1210 val_print (builtin_type_double, dbuffer, 0,
1211 gdb_stdout, 0, 1, 0, Val_pretty_default);
1212 printf_filtered ("); ");
1214 fputs_filtered (reg_names[regnum], gdb_stdout);
1216 /* The problem with printing numeric register names (r26, etc.) is that
1217 the user can't use them on input. Probably the best solution is to
1218 fix it so that either the numeric or the funky (a2, etc.) names
1219 are accepted on input. */
1220 if (regnum < MIPS_NUMREGS)
1221 printf_filtered ("(r%d): ", regnum);
1223 printf_filtered (": ");
1225 /* If virtual format is floating, print it that way. */
1226 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1227 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0,
1228 gdb_stdout, 0, 1, 0, Val_pretty_default);
1229 /* Else print as integer in hex. */
1231 print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum),
1232 'x', 0, gdb_stdout);
1235 /* Replacement for generic do_registers_info. */
1238 mips_do_registers_info (regnum, fpregs)
1244 if (*(reg_names[regnum]) == '\0')
1245 error ("Not a valid register for the current processor type");
1247 mips_print_register (regnum, 0);
1248 printf_filtered ("\n");
1252 int did_newline = 0;
1254 for (regnum = 0; regnum < NUM_REGS; )
1256 if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM)
1257 || *(reg_names[regnum]) == '\0')
1262 mips_print_register (regnum, 1);
1264 printf_filtered ("; ");
1266 if ((regnum & 3) == 0)
1268 printf_filtered ("\n");
1273 printf_filtered ("\n");
1277 /* Return number of args passed to a frame. described by FIP.
1278 Can return -1, meaning no way to tell. */
1281 mips_frame_num_args (frame)
1282 struct frame_info *frame;
1284 #if 0 /* FIXME Use or lose this! */
1285 struct chain_info_t *p;
1287 p = mips_find_cached_frame (FRAME_FP (frame));
1289 return p->the_info.numargs;
1294 /* Is this a branch with a delay slot? */
1296 static int is_delayed PARAMS ((unsigned long));
1303 for (i = 0; i < NUMOPCODES; ++i)
1304 if (mips_opcodes[i].pinfo != INSN_MACRO
1305 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
1307 return (i < NUMOPCODES
1308 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
1309 | INSN_COND_BRANCH_DELAY
1310 | INSN_COND_BRANCH_LIKELY)));
1314 mips_step_skips_delay (pc)
1317 char buf[MIPS_INSTLEN];
1319 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
1320 /* If error reading memory, guess that it is not a delayed branch. */
1322 return is_delayed ((unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN));
1325 /* To skip prologues, I use this predicate. Returns either PC itself
1326 if the code at PC does not look like a function prologue; otherwise
1327 returns an address that (if we're lucky) follows the prologue. If
1328 LENIENT, then we must skip everything which is involved in setting
1329 up the frame (it's OK to skip more, just so long as we don't skip
1330 anything which might clobber the registers which are being saved.
1331 We must skip more in the case where part of the prologue is in the
1332 delay slot of a non-prologue instruction). */
1335 mips_skip_prologue (pc, lenient)
1341 int seen_sp_adjust = 0;
1342 int load_immediate_bytes = 0;
1343 CORE_ADDR post_prologue_pc;
1345 /* See if we can determine the end of the prologue via the symbol table.
1346 If so, then return either PC, or the PC after the prologue, whichever
1349 post_prologue_pc = after_prologue (pc, NULL);
1351 if (post_prologue_pc != 0)
1352 return max (pc, post_prologue_pc);
1354 /* Can't determine prologue from the symbol table, need to examine
1357 /* Skip the typical prologue instructions. These are the stack adjustment
1358 instruction and the instructions that save registers on the stack
1359 or in the gcc frame. */
1360 for (offset = 0; offset < 100; offset += MIPS_INSTLEN)
1362 char buf[MIPS_INSTLEN];
1365 status = read_memory_nobpt (pc + offset, buf, MIPS_INSTLEN);
1367 memory_error (status, pc + offset);
1368 inst = (unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN);
1371 if (lenient && is_delayed (inst))
1375 if ((inst & 0xffff0000) == 0x27bd0000 /* addiu $sp,$sp,offset */
1376 || (inst & 0xffff0000) == 0x67bd0000) /* daddiu $sp,$sp,offset */
1378 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
1379 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
1381 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
1382 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
1383 && (inst & 0x001F0000)) /* reg != $zero */
1386 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1388 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
1390 continue; /* reg != $zero */
1392 /* move $s8,$sp. With different versions of gas this will be either
1393 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero'. Accept either. */
1394 else if (inst == 0x03A0F021 || inst == 0x03a0f025)
1397 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1399 else if ((inst & 0xffff0000) == 0x3c1c0000) /* lui $gp,n */
1401 else if ((inst & 0xffff0000) == 0x279c0000) /* addiu $gp,$gp,n */
1403 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
1404 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
1406 /* The following instructions load $at or $t0 with an immediate
1407 value in preparation for a stack adjustment via
1408 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1409 a local variable, so we accept them only before a stack adjustment
1410 instruction was seen. */
1411 else if (!seen_sp_adjust)
1413 if ((inst & 0xffff0000) == 0x3c010000 || /* lui $at,n */
1414 (inst & 0xffff0000) == 0x3c080000) /* lui $t0,n */
1416 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
1419 else if ((inst & 0xffff0000) == 0x34210000 || /* ori $at,$at,n */
1420 (inst & 0xffff0000) == 0x35080000 || /* ori $t0,$t0,n */
1421 (inst & 0xffff0000) == 0x34010000 || /* ori $at,$zero,n */
1422 (inst & 0xffff0000) == 0x34080000) /* ori $t0,$zero,n */
1424 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
1434 /* In a frameless function, we might have incorrectly
1435 skipped some load immediate instructions. Undo the skipping
1436 if the load immediate was not followed by a stack adjustment. */
1437 if (load_immediate_bytes && !seen_sp_adjust)
1438 offset -= load_immediate_bytes;
1443 /* The lenient prologue stuff should be superceded by the code in
1444 init_extra_frame_info which looks to see whether the stores mentioned
1445 in the proc_desc have actually taken place. */
1447 /* Is address PC in the prologue (loosely defined) for function at
1451 mips_in_lenient_prologue (startaddr, pc)
1452 CORE_ADDR startaddr;
1455 CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1);
1456 return pc >= startaddr && pc < end_prologue;
1460 /* Given a return value in `regbuf' with a type `valtype',
1461 extract and copy its value into `valbuf'. */
1463 mips_extract_return_value (valtype, regbuf, valbuf)
1464 struct type *valtype;
1465 char regbuf[REGISTER_BYTES];
1472 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1473 && (mips_fpu == MIPS_FPU_DOUBLE
1474 || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */
1475 regnum = FP0_REGNUM;
1477 if (TARGET_BYTE_ORDER == BIG_ENDIAN
1478 && TYPE_CODE (valtype) != TYPE_CODE_FLT
1479 && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (regnum))
1480 offset = REGISTER_RAW_SIZE (regnum) - TYPE_LENGTH (valtype);
1482 memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset,
1483 TYPE_LENGTH (valtype));
1484 #ifdef REGISTER_CONVERT_TO_TYPE
1485 REGISTER_CONVERT_TO_TYPE(regnum, valtype, valbuf);
1489 /* Given a return value in `regbuf' with a type `valtype',
1490 write it's value into the appropriate register. */
1492 mips_store_return_value (valtype, valbuf)
1493 struct type *valtype;
1497 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1500 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1501 && (mips_fpu == MIPS_FPU_DOUBLE
1502 || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */
1503 regnum = FP0_REGNUM;
1505 memcpy(raw_buffer, valbuf, TYPE_LENGTH (valtype));
1507 #ifdef REGISTER_CONVERT_FROM_TYPE
1508 REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer);
1511 write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, TYPE_LENGTH (valtype));
1514 /* Exported procedure: Is PC in the signal trampoline code */
1517 in_sigtramp (pc, ignore)
1519 char *ignore; /* function name */
1521 if (sigtramp_address == 0)
1523 return (pc >= sigtramp_address && pc < sigtramp_end);
1526 /* Command to set FPU type. mips_fpu_string will have been set to the
1527 user's argument. Set mips_fpu based on mips_fpu_string, and then
1528 canonicalize mips_fpu_string. */
1532 mips_set_fpu_command (args, from_tty, c)
1535 struct cmd_list_element *c;
1539 if (mips_fpu_string == NULL || *mips_fpu_string == '\0')
1540 mips_fpu = MIPS_FPU_DOUBLE;
1541 else if (strcasecmp (mips_fpu_string, "double") == 0
1542 || strcasecmp (mips_fpu_string, "on") == 0
1543 || strcasecmp (mips_fpu_string, "1") == 0
1544 || strcasecmp (mips_fpu_string, "yes") == 0)
1545 mips_fpu = MIPS_FPU_DOUBLE;
1546 else if (strcasecmp (mips_fpu_string, "none") == 0
1547 || strcasecmp (mips_fpu_string, "off") == 0
1548 || strcasecmp (mips_fpu_string, "0") == 0
1549 || strcasecmp (mips_fpu_string, "no") == 0)
1550 mips_fpu = MIPS_FPU_NONE;
1551 else if (strcasecmp (mips_fpu_string, "single") == 0)
1552 mips_fpu = MIPS_FPU_SINGLE;
1554 err = strsave (mips_fpu_string);
1556 if (mips_fpu_string != NULL)
1557 free (mips_fpu_string);
1561 case MIPS_FPU_DOUBLE:
1562 mips_fpu_string = strsave ("double");
1564 case MIPS_FPU_SINGLE:
1565 mips_fpu_string = strsave ("single");
1568 mips_fpu_string = strsave ("none");
1574 struct cleanup *cleanups = make_cleanup (free, err);
1575 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
1577 do_cleanups (cleanups);
1582 mips_show_fpu_command (args, from_tty, c)
1585 struct cmd_list_element *c;
1589 /* Command to set the processor type. */
1592 mips_set_processor_type_command (args, from_tty)
1598 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
1600 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
1601 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
1602 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
1604 /* Restore the value. */
1605 tmp_mips_processor_type = strsave (mips_processor_type);
1610 if (!mips_set_processor_type (tmp_mips_processor_type))
1612 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
1613 /* Restore its value. */
1614 tmp_mips_processor_type = strsave (mips_processor_type);
1619 mips_show_processor_type_command (args, from_tty)
1625 /* Modify the actual processor type. */
1628 mips_set_processor_type (str)
1636 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
1638 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
1640 mips_processor_type = str;
1642 for (j = 0; j < NUM_REGS; ++j)
1643 reg_names[j] = mips_processor_type_table[i].regnames[j];
1647 /* FIXME tweak fpu flag too */
1654 /* Attempt to identify the particular processor model by reading the
1658 mips_read_processor_type ()
1662 prid = read_register (PRID_REGNUM);
1664 if ((prid & ~0xf) == 0x700)
1665 return savestring ("r3041", strlen("r3041"));
1670 /* Just like reinit_frame_cache, but with the right arguments to be
1671 callable as an sfunc. */
1674 reinit_frame_cache_sfunc (args, from_tty, c)
1677 struct cmd_list_element *c;
1679 reinit_frame_cache ();
1683 gdb_print_insn_mips (memaddr, info)
1685 disassemble_info *info;
1687 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1688 return print_insn_big_mips (memaddr, info);
1690 return print_insn_little_mips (memaddr, info);
1694 _initialize_mips_tdep ()
1696 struct cmd_list_element *c;
1698 tm_print_insn = gdb_print_insn_mips;
1700 /* Let the user turn off floating point and set the fence post for
1701 heuristic_proc_start. */
1703 c = add_set_cmd ("mipsfpu", class_support, var_string_noescape,
1704 (char *) &mips_fpu_string,
1705 "Set use of floating point coprocessor.\n\
1706 Set to `none' to avoid using floating point instructions when calling\n\
1707 functions or dealing with return values. Set to `single' to use only\n\
1708 single precision floating point as on the R4650. Set to `double' for\n\
1709 normal floating point support.",
1711 c->function.sfunc = mips_set_fpu_command;
1712 c = add_show_from_set (c, &showlist);
1713 c->function.sfunc = mips_show_fpu_command;
1715 mips_fpu = MIPS_FPU_DOUBLE;
1716 mips_fpu_string = strsave ("double");
1718 c = add_set_cmd ("processor", class_support, var_string_noescape,
1719 (char *) &tmp_mips_processor_type,
1720 "Set the type of MIPS processor in use.\n\
1721 Set this to be able to access processor-type-specific registers.\n\
1724 c->function.cfunc = mips_set_processor_type_command;
1725 c = add_show_from_set (c, &showlist);
1726 c->function.cfunc = mips_show_processor_type_command;
1728 tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE);
1729 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0);
1731 /* We really would like to have both "0" and "unlimited" work, but
1732 command.c doesn't deal with that. So make it a var_zinteger
1733 because the user can always use "999999" or some such for unlimited. */
1734 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
1735 (char *) &heuristic_fence_post,
1737 Set the distance searched for the start of a function.\n\
1738 If you are debugging a stripped executable, GDB needs to search through the\n\
1739 program for the start of a function. This command sets the distance of the\n\
1740 search. The only need to set it is when debugging a stripped executable.",
1742 /* We need to throw away the frame cache when we set this, since it
1743 might change our ability to get backtraces. */
1744 c->function.sfunc = reinit_frame_cache_sfunc;
1745 add_show_from_set (c, &showlist);