1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data *mips_pdr_data;
63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE = 4,
74 MIPS_FPU_DOUBLE_REGSIZE = 8
83 static const char *mips_abi_string;
85 static const char *mips_abi_strings[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM },
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE /* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto = 1;
159 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
161 static int mips_debug = 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc *mips_tdesc_gp32;
169 struct target_desc *mips_tdesc_gp64;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi;
179 enum mips_abi found_abi;
180 enum mips_fpu_type mips_fpu_type;
181 int mips_last_arg_regnum;
182 int mips_last_fp_arg_regnum;
183 int default_mask_address_p;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum *regnum;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p;
203 n32n64_floatformat_always_valid (const struct floatformat *fmt,
209 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
210 They are implemented as a pair of 64bit doubles where the high
211 part holds the result of the operation rounded to double, and
212 the low double holds the difference between the exact result and
213 the rounded result. So "high" + "low" contains the result with
214 added precision. Unfortunately, the floatformat structure used
215 by GDB is not powerful enough to describe this format. As a temporary
216 measure, we define a 128bit floatformat that only uses the high part.
217 We lose a bit of precision but that's probably the best we can do
218 for now with the current infrastructure. */
220 static const struct floatformat floatformat_n32n64_long_double_big =
222 floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52,
223 floatformat_intbit_no,
224 "floatformat_n32n64_long_double_big",
225 n32n64_floatformat_always_valid
228 static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] =
230 &floatformat_n32n64_long_double_big,
231 &floatformat_n32n64_long_double_big
234 const struct mips_regnum *
235 mips_regnum (struct gdbarch *gdbarch)
237 return gdbarch_tdep (gdbarch)->regnum;
241 mips_fpa0_regnum (struct gdbarch *gdbarch)
243 return mips_regnum (gdbarch)->fp0 + 12;
246 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
247 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
249 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
251 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
253 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
255 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
256 functions to test, set, or clear bit 0 of addresses. */
259 is_mips16_addr (CORE_ADDR addr)
265 unmake_mips16_addr (CORE_ADDR addr)
267 return ((addr) & ~(CORE_ADDR) 1);
270 /* Return the MIPS ABI associated with GDBARCH. */
272 mips_abi (struct gdbarch *gdbarch)
274 return gdbarch_tdep (gdbarch)->mips_abi;
278 mips_isa_regsize (struct gdbarch *gdbarch)
280 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
282 /* If we know how big the registers are, use that size. */
283 if (tdep->register_size_valid_p)
284 return tdep->register_size;
286 /* Fall back to the previous behavior. */
287 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
288 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
291 /* Return the currently configured (or set) saved register size. */
294 mips_abi_regsize (struct gdbarch *gdbarch)
296 switch (mips_abi (gdbarch))
298 case MIPS_ABI_EABI32:
304 case MIPS_ABI_EABI64:
306 case MIPS_ABI_UNKNOWN:
309 internal_error (__FILE__, __LINE__, _("bad switch"));
313 /* Functions for setting and testing a bit in a minimal symbol that
314 marks it as 16-bit function. The MSB of the minimal symbol's
315 "info" field is used for this purpose.
317 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
318 i.e. refers to a 16-bit function, and sets a "special" bit in a
319 minimal symbol to mark it as a 16-bit function
321 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
324 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
326 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
328 MSYMBOL_INFO (msym) = (char *)
329 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
330 SYMBOL_VALUE_ADDRESS (msym) |= 1;
335 msymbol_is_special (struct minimal_symbol *msym)
337 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
340 /* XFER a value from the big/little/left end of the register.
341 Depending on the size of the value it might occupy the entire
342 register or just part of it. Make an allowance for this, aligning
343 things accordingly. */
346 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
347 enum bfd_endian endian, gdb_byte *in,
348 const gdb_byte *out, int buf_offset)
351 struct gdbarch *gdbarch = get_regcache_arch (regcache);
353 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
354 /* Need to transfer the left or right part of the register, based on
355 the targets byte order. */
359 reg_offset = register_size (gdbarch, reg_num) - length;
361 case BFD_ENDIAN_LITTLE:
364 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
368 internal_error (__FILE__, __LINE__, _("bad switch"));
371 fprintf_unfiltered (gdb_stderr,
372 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
373 reg_num, reg_offset, buf_offset, length);
374 if (mips_debug && out != NULL)
377 fprintf_unfiltered (gdb_stdlog, "out ");
378 for (i = 0; i < length; i++)
379 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
382 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
385 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
387 if (mips_debug && in != NULL)
390 fprintf_unfiltered (gdb_stdlog, "in ");
391 for (i = 0; i < length; i++)
392 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
395 fprintf_unfiltered (gdb_stdlog, "\n");
398 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
399 compatiblity mode. A return value of 1 means that we have
400 physical 64-bit registers, but should treat them as 32-bit registers. */
403 mips2_fp_compat (struct frame_info *frame)
405 struct gdbarch *gdbarch = get_frame_arch (frame);
406 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
408 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
412 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
413 in all the places we deal with FP registers. PR gdb/413. */
414 /* Otherwise check the FR bit in the status register - it controls
415 the FP compatiblity mode. If it is clear we are in compatibility
417 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
424 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
426 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
428 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
430 static struct type *mips_float_register_type (void);
431 static struct type *mips_double_register_type (void);
433 /* The list of available "set mips " and "show mips " commands */
435 static struct cmd_list_element *setmipscmdlist = NULL;
436 static struct cmd_list_element *showmipscmdlist = NULL;
438 /* Integer registers 0 thru 31 are handled explicitly by
439 mips_register_name(). Processor specific registers 32 and above
440 are listed in the following tables. */
443 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
447 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
448 "sr", "lo", "hi", "bad", "cause", "pc",
449 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
450 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
451 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
452 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
453 "fsr", "fir", "" /*"fp" */ , "",
454 "", "", "", "", "", "", "", "",
455 "", "", "", "", "", "", "", "",
458 /* Names of IDT R3041 registers. */
460 static const char *mips_r3041_reg_names[] = {
461 "sr", "lo", "hi", "bad", "cause", "pc",
462 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
463 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
464 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
465 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
466 "fsr", "fir", "", /*"fp" */ "",
467 "", "", "bus", "ccfg", "", "", "", "",
468 "", "", "port", "cmp", "", "", "epc", "prid",
471 /* Names of tx39 registers. */
473 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
474 "sr", "lo", "hi", "bad", "cause", "pc",
475 "", "", "", "", "", "", "", "",
476 "", "", "", "", "", "", "", "",
477 "", "", "", "", "", "", "", "",
478 "", "", "", "", "", "", "", "",
480 "", "", "", "", "", "", "", "",
481 "", "", "config", "cache", "debug", "depc", "epc", ""
484 /* Names of IRIX registers. */
485 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
486 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
487 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
488 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
489 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
490 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
494 /* Return the name of the register corresponding to REGNO. */
496 mips_register_name (int regno)
498 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
499 /* GPR names for all ABIs other than n32/n64. */
500 static char *mips_gpr_names[] = {
501 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
502 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
503 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
504 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
507 /* GPR names for n32 and n64 ABIs. */
508 static char *mips_n32_n64_gpr_names[] = {
509 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
510 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
511 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
512 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
515 enum mips_abi abi = mips_abi (current_gdbarch);
517 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
518 but then don't make the raw register names visible. */
519 int rawnum = regno % gdbarch_num_regs (current_gdbarch);
520 if (regno < gdbarch_num_regs (current_gdbarch))
523 /* The MIPS integer registers are always mapped from 0 to 31. The
524 names of the registers (which reflects the conventions regarding
525 register use) vary depending on the ABI. */
526 if (0 <= rawnum && rawnum < 32)
528 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
529 return mips_n32_n64_gpr_names[rawnum];
531 return mips_gpr_names[rawnum];
533 else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch)))
534 return tdesc_register_name (rawnum);
535 else if (32 <= rawnum && rawnum < gdbarch_num_regs (current_gdbarch))
537 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
538 return tdep->mips_processor_reg_names[rawnum - 32];
541 internal_error (__FILE__, __LINE__,
542 _("mips_register_name: bad register number %d"), rawnum);
545 /* Return the groups that a MIPS register can be categorised into. */
548 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
549 struct reggroup *reggroup)
554 int rawnum = regnum % gdbarch_num_regs (gdbarch);
555 int pseudo = regnum / gdbarch_num_regs (gdbarch);
556 if (reggroup == all_reggroup)
558 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
559 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
560 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
561 (gdbarch), as not all architectures are multi-arch. */
562 raw_p = rawnum < gdbarch_num_regs (gdbarch);
563 if (gdbarch_register_name (gdbarch, regnum) == NULL
564 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
566 if (reggroup == float_reggroup)
567 return float_p && pseudo;
568 if (reggroup == vector_reggroup)
569 return vector_p && pseudo;
570 if (reggroup == general_reggroup)
571 return (!vector_p && !float_p) && pseudo;
572 /* Save the pseudo registers. Need to make certain that any code
573 extracting register values from a saved register cache also uses
575 if (reggroup == save_reggroup)
576 return raw_p && pseudo;
577 /* Restore the same pseudo register. */
578 if (reggroup == restore_reggroup)
579 return raw_p && pseudo;
583 /* Return the groups that a MIPS register can be categorised into.
584 This version is only used if we have a target description which
585 describes real registers (and their groups). */
588 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
589 struct reggroup *reggroup)
591 int rawnum = regnum % gdbarch_num_regs (gdbarch);
592 int pseudo = regnum / gdbarch_num_regs (gdbarch);
595 /* Only save, restore, and display the pseudo registers. Need to
596 make certain that any code extracting register values from a
597 saved register cache also uses pseudo registers.
599 Note: saving and restoring the pseudo registers is slightly
600 strange; if we have 64 bits, we should save and restore all
601 64 bits. But this is hard and has little benefit. */
605 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
609 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
612 /* Map the symbol table registers which live in the range [1 *
613 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
614 registers. Take care of alignment and size problems. */
617 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
618 int cookednum, gdb_byte *buf)
620 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
621 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
622 && cookednum < 2 * gdbarch_num_regs (gdbarch));
623 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
624 regcache_raw_read (regcache, rawnum, buf);
625 else if (register_size (gdbarch, rawnum) >
626 register_size (gdbarch, cookednum))
628 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
629 || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
630 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
632 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
635 internal_error (__FILE__, __LINE__, _("bad register size"));
639 mips_pseudo_register_write (struct gdbarch *gdbarch,
640 struct regcache *regcache, int cookednum,
643 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
644 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
645 && cookednum < 2 * gdbarch_num_regs (gdbarch));
646 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
647 regcache_raw_write (regcache, rawnum, buf);
648 else if (register_size (gdbarch, rawnum) >
649 register_size (gdbarch, cookednum))
651 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
652 || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
653 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
655 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
658 internal_error (__FILE__, __LINE__, _("bad register size"));
661 /* Table to translate MIPS16 register field to actual register number. */
662 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
664 /* Heuristic_proc_start may hunt through the text section for a long
665 time across a 2400 baud serial line. Allows the user to limit this
668 static unsigned int heuristic_fence_post = 0;
670 /* Number of bytes of storage in the actual machine representation for
671 register N. NOTE: This defines the pseudo register type so need to
672 rebuild the architecture vector. */
674 static int mips64_transfers_32bit_regs_p = 0;
677 set_mips64_transfers_32bit_regs (char *args, int from_tty,
678 struct cmd_list_element *c)
680 struct gdbarch_info info;
681 gdbarch_info_init (&info);
682 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
683 instead of relying on globals. Doing that would let generic code
684 handle the search for this specific architecture. */
685 if (!gdbarch_update_p (info))
687 mips64_transfers_32bit_regs_p = 0;
688 error (_("32-bit compatibility mode not supported"));
692 /* Convert to/from a register and the corresponding memory value. */
695 mips_convert_register_p (int regnum, struct type *type)
697 return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
698 && register_size (current_gdbarch, regnum) == 4
699 && (regnum % gdbarch_num_regs (current_gdbarch))
700 >= mips_regnum (current_gdbarch)->fp0
701 && (regnum % gdbarch_num_regs (current_gdbarch))
702 < mips_regnum (current_gdbarch)->fp0 + 32
703 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
707 mips_register_to_value (struct frame_info *frame, int regnum,
708 struct type *type, gdb_byte *to)
710 get_frame_register (frame, regnum + 0, to + 4);
711 get_frame_register (frame, regnum + 1, to + 0);
715 mips_value_to_register (struct frame_info *frame, int regnum,
716 struct type *type, const gdb_byte *from)
718 put_frame_register (frame, regnum + 0, from + 4);
719 put_frame_register (frame, regnum + 1, from + 0);
722 /* Return the GDB type object for the "standard" data type of data in
726 mips_register_type (struct gdbarch *gdbarch, int regnum)
728 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
729 if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0
730 && (regnum % gdbarch_num_regs (gdbarch))
731 < mips_regnum (gdbarch)->fp0 + 32)
733 /* The floating-point registers raw, or cooked, always match
734 mips_isa_regsize(), and also map 1:1, byte for byte. */
735 if (mips_isa_regsize (gdbarch) == 4)
736 return builtin_type_ieee_single;
738 return builtin_type_ieee_double;
740 else if (regnum < gdbarch_num_regs (gdbarch))
742 /* The raw or ISA registers. These are all sized according to
744 if (mips_isa_regsize (gdbarch) == 4)
745 return builtin_type_int32;
747 return builtin_type_int64;
751 /* The cooked or ABI registers. These are sized according to
752 the ABI (with a few complications). */
753 if (regnum >= (gdbarch_num_regs (gdbarch)
754 + mips_regnum (gdbarch)->fp_control_status)
755 && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM)
756 /* The pseudo/cooked view of the embedded registers is always
757 32-bit. The raw view is handled below. */
758 return builtin_type_int32;
759 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
760 /* The target, while possibly using a 64-bit register buffer,
761 is only transfering 32-bits of each integer register.
762 Reflect this in the cooked/pseudo (ABI) register value. */
763 return builtin_type_int32;
764 else if (mips_abi_regsize (gdbarch) == 4)
765 /* The ABI is restricted to 32-bit registers (the ISA could be
767 return builtin_type_int32;
770 return builtin_type_int64;
774 /* Return the GDB type for the pseudo register REGNUM, which is the
775 ABI-level view. This function is only called if there is a target
776 description which includes registers, so we know precisely the
777 types of hardware registers. */
780 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
782 const int num_regs = gdbarch_num_regs (gdbarch);
783 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
784 int rawnum = regnum % num_regs;
785 struct type *rawtype;
787 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
789 /* Absent registers are still absent. */
790 rawtype = gdbarch_register_type (gdbarch, rawnum);
791 if (TYPE_LENGTH (rawtype) == 0)
794 if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32)
795 /* Present the floating point registers however the hardware did;
796 do not try to convert between FPU layouts. */
799 if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM)
801 /* The pseudo/cooked view of embedded registers is always
802 32-bit, even if the target transfers 64-bit values for them.
803 New targets relying on XML descriptions should only transfer
804 the necessary 32 bits, but older versions of GDB expected 64,
805 so allow the target to provide 64 bits without interfering
806 with the displayed type. */
807 return builtin_type_int32;
810 /* Use pointer types for registers if we can. For n32 we can not,
811 since we do not have a 64-bit pointer type. */
812 if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr))
814 if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM)
815 return builtin_type_void_data_ptr;
816 else if (rawnum == MIPS_EMBED_PC_REGNUM)
817 return builtin_type_void_func_ptr;
820 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
821 && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM)
822 return builtin_type_int32;
824 /* For all other registers, pass through the hardware type. */
828 /* Should the upper word of 64-bit addresses be zeroed? */
829 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
832 mips_mask_address_p (struct gdbarch_tdep *tdep)
834 switch (mask_address_var)
836 case AUTO_BOOLEAN_TRUE:
838 case AUTO_BOOLEAN_FALSE:
841 case AUTO_BOOLEAN_AUTO:
842 return tdep->default_mask_address_p;
844 internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch"));
850 show_mask_address (struct ui_file *file, int from_tty,
851 struct cmd_list_element *c, const char *value)
853 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
855 deprecated_show_value_hack (file, from_tty, c, value);
856 switch (mask_address_var)
858 case AUTO_BOOLEAN_TRUE:
859 printf_filtered ("The 32 bit mips address mask is enabled\n");
861 case AUTO_BOOLEAN_FALSE:
862 printf_filtered ("The 32 bit mips address mask is disabled\n");
864 case AUTO_BOOLEAN_AUTO:
866 ("The 32 bit address mask is set automatically. Currently %s\n",
867 mips_mask_address_p (tdep) ? "enabled" : "disabled");
870 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
875 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
878 mips_pc_is_mips16 (CORE_ADDR memaddr)
880 struct minimal_symbol *sym;
882 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
883 if (is_mips16_addr (memaddr))
886 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
887 the high bit of the info field. Use this to decide if the function is
888 MIPS16 or normal MIPS. */
889 sym = lookup_minimal_symbol_by_pc (memaddr);
891 return msymbol_is_special (sym);
896 /* MIPS believes that the PC has a sign extended value. Perhaps the
897 all registers should be sign extended for simplicity? */
900 mips_read_pc (struct regcache *regcache)
903 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
904 regcache_cooked_read_signed (regcache, regnum, &pc);
909 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
911 return frame_unwind_register_signed
912 (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc);
916 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
918 return frame_unwind_register_signed
919 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
922 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
923 dummy frame. The frame ID's base needs to match the TOS value
924 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
927 static struct frame_id
928 mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
930 return frame_id_build
931 (frame_unwind_register_signed (next_frame,
932 gdbarch_num_regs (gdbarch)
934 frame_pc_unwind (next_frame));
938 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
940 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
941 regcache_cooked_write_unsigned (regcache, regnum, pc);
944 /* Fetch and return instruction from the specified location. If the PC
945 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
948 mips_fetch_instruction (CORE_ADDR addr)
950 gdb_byte buf[MIPS_INSN32_SIZE];
954 if (mips_pc_is_mips16 (addr))
956 instlen = MIPS_INSN16_SIZE;
957 addr = unmake_mips16_addr (addr);
960 instlen = MIPS_INSN32_SIZE;
961 status = read_memory_nobpt (addr, buf, instlen);
963 memory_error (status, addr);
964 return extract_unsigned_integer (buf, instlen);
967 /* These the fields of 32 bit mips instructions */
968 #define mips32_op(x) (x >> 26)
969 #define itype_op(x) (x >> 26)
970 #define itype_rs(x) ((x >> 21) & 0x1f)
971 #define itype_rt(x) ((x >> 16) & 0x1f)
972 #define itype_immediate(x) (x & 0xffff)
974 #define jtype_op(x) (x >> 26)
975 #define jtype_target(x) (x & 0x03ffffff)
977 #define rtype_op(x) (x >> 26)
978 #define rtype_rs(x) ((x >> 21) & 0x1f)
979 #define rtype_rt(x) ((x >> 16) & 0x1f)
980 #define rtype_rd(x) ((x >> 11) & 0x1f)
981 #define rtype_shamt(x) ((x >> 6) & 0x1f)
982 #define rtype_funct(x) (x & 0x3f)
985 mips32_relative_offset (ULONGEST inst)
987 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
990 /* Determine where to set a single step breakpoint while considering
991 branch prediction. */
993 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
997 inst = mips_fetch_instruction (pc);
998 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1000 if (itype_op (inst) >> 2 == 5)
1001 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1003 op = (itype_op (inst) & 0x03);
1013 goto greater_branch;
1018 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
1019 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1021 int tf = itype_rt (inst) & 0x01;
1022 int cnum = itype_rt (inst) >> 2;
1024 get_frame_register_signed (frame,
1025 mips_regnum (get_frame_arch (frame))->
1027 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
1029 if (((cond >> cnum) & 0x01) == tf)
1030 pc += mips32_relative_offset (inst) + 4;
1035 pc += 4; /* Not a branch, next instruction is easy */
1038 { /* This gets way messy */
1040 /* Further subdivide into SPECIAL, REGIMM and other */
1041 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
1043 case 0: /* SPECIAL */
1044 op = rtype_funct (inst);
1049 /* Set PC to that address */
1050 pc = get_frame_register_signed (frame, rtype_rs (inst));
1056 break; /* end SPECIAL */
1057 case 1: /* REGIMM */
1059 op = itype_rt (inst); /* branch condition */
1064 case 16: /* BLTZAL */
1065 case 18: /* BLTZALL */
1067 if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1068 pc += mips32_relative_offset (inst) + 4;
1070 pc += 8; /* after the delay slot */
1074 case 17: /* BGEZAL */
1075 case 19: /* BGEZALL */
1076 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1077 pc += mips32_relative_offset (inst) + 4;
1079 pc += 8; /* after the delay slot */
1081 /* All of the other instructions in the REGIMM category */
1086 break; /* end REGIMM */
1091 reg = jtype_target (inst) << 2;
1092 /* Upper four bits get never changed... */
1093 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1096 /* FIXME case JALX : */
1099 reg = jtype_target (inst) << 2;
1100 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */
1101 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1103 break; /* The new PC will be alternate mode */
1104 case 4: /* BEQ, BEQL */
1106 if (get_frame_register_signed (frame, itype_rs (inst)) ==
1107 get_frame_register_signed (frame, itype_rt (inst)))
1108 pc += mips32_relative_offset (inst) + 4;
1112 case 5: /* BNE, BNEL */
1114 if (get_frame_register_signed (frame, itype_rs (inst)) !=
1115 get_frame_register_signed (frame, itype_rt (inst)))
1116 pc += mips32_relative_offset (inst) + 4;
1120 case 6: /* BLEZ, BLEZL */
1121 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1122 pc += mips32_relative_offset (inst) + 4;
1128 greater_branch: /* BGTZ, BGTZL */
1129 if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1130 pc += mips32_relative_offset (inst) + 4;
1137 } /* mips32_next_pc */
1139 /* Decoding the next place to set a breakpoint is irregular for the
1140 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1141 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1142 We dont want to set a single step instruction on the extend instruction
1146 /* Lots of mips16 instruction formats */
1147 /* Predicting jumps requires itype,ritype,i8type
1148 and their extensions extItype,extritype,extI8type
1150 enum mips16_inst_fmts
1152 itype, /* 0 immediate 5,10 */
1153 ritype, /* 1 5,3,8 */
1154 rrtype, /* 2 5,3,3,5 */
1155 rritype, /* 3 5,3,3,5 */
1156 rrrtype, /* 4 5,3,3,3,2 */
1157 rriatype, /* 5 5,3,3,1,4 */
1158 shifttype, /* 6 5,3,3,3,2 */
1159 i8type, /* 7 5,3,8 */
1160 i8movtype, /* 8 5,3,3,5 */
1161 i8mov32rtype, /* 9 5,3,5,3 */
1162 i64type, /* 10 5,3,8 */
1163 ri64type, /* 11 5,3,3,5 */
1164 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1165 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1166 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1167 extRRItype, /* 15 5,5,5,5,3,3,5 */
1168 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1169 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1170 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1171 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1172 extRi64type, /* 20 5,6,5,5,3,3,5 */
1173 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1175 /* I am heaping all the fields of the formats into one structure and
1176 then, only the fields which are involved in instruction extension */
1180 unsigned int regx; /* Function in i8 type */
1185 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1186 for the bits which make up the immediatate extension. */
1189 extended_offset (unsigned int extension)
1192 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1194 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1196 value |= extension & 0x01f; /* extract 4:0 */
1200 /* Only call this function if you know that this is an extendable
1201 instruction. It won't malfunction, but why make excess remote memory
1202 references? If the immediate operands get sign extended or something,
1203 do it after the extension is performed. */
1204 /* FIXME: Every one of these cases needs to worry about sign extension
1205 when the offset is to be used in relative addressing. */
1208 fetch_mips_16 (CORE_ADDR pc)
1211 pc &= 0xfffffffe; /* clear the low order bit */
1212 target_read_memory (pc, buf, 2);
1213 return extract_unsigned_integer (buf, 2);
1217 unpack_mips16 (CORE_ADDR pc,
1218 unsigned int extension,
1220 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1225 switch (insn_format)
1232 value = extended_offset (extension);
1233 value = value << 11; /* rom for the original value */
1234 value |= inst & 0x7ff; /* eleven bits from instruction */
1238 value = inst & 0x7ff;
1239 /* FIXME : Consider sign extension */
1248 { /* A register identifier and an offset */
1249 /* Most of the fields are the same as I type but the
1250 immediate value is of a different length */
1254 value = extended_offset (extension);
1255 value = value << 8; /* from the original instruction */
1256 value |= inst & 0xff; /* eleven bits from instruction */
1257 regx = (extension >> 8) & 0x07; /* or i8 funct */
1258 if (value & 0x4000) /* test the sign bit , bit 26 */
1260 value &= ~0x3fff; /* remove the sign bit */
1266 value = inst & 0xff; /* 8 bits */
1267 regx = (inst >> 8) & 0x07; /* or i8 funct */
1268 /* FIXME: Do sign extension , this format needs it */
1269 if (value & 0x80) /* THIS CONFUSES ME */
1271 value &= 0xef; /* remove the sign bit */
1281 unsigned long value;
1282 unsigned int nexthalf;
1283 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1284 value = value << 16;
1285 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1293 internal_error (__FILE__, __LINE__, _("bad switch"));
1295 upk->offset = offset;
1302 add_offset_16 (CORE_ADDR pc, int offset)
1304 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
1308 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
1309 unsigned int extension, unsigned int insn)
1311 int op = (insn >> 11);
1314 case 2: /* Branch */
1317 struct upk_mips16 upk;
1318 unpack_mips16 (pc, extension, insn, itype, &upk);
1319 offset = upk.offset;
1325 pc += (offset << 1) + 2;
1328 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1330 struct upk_mips16 upk;
1331 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1332 pc = add_offset_16 (pc, upk.offset);
1333 if ((insn >> 10) & 0x01) /* Exchange mode */
1334 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1341 struct upk_mips16 upk;
1343 unpack_mips16 (pc, extension, insn, ritype, &upk);
1344 reg = get_frame_register_signed (frame, upk.regx);
1346 pc += (upk.offset << 1) + 2;
1353 struct upk_mips16 upk;
1355 unpack_mips16 (pc, extension, insn, ritype, &upk);
1356 reg = get_frame_register_signed (frame, upk.regx);
1358 pc += (upk.offset << 1) + 2;
1363 case 12: /* I8 Formats btez btnez */
1365 struct upk_mips16 upk;
1367 unpack_mips16 (pc, extension, insn, i8type, &upk);
1368 /* upk.regx contains the opcode */
1369 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
1370 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1371 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1372 /* pc = add_offset_16(pc,upk.offset) ; */
1373 pc += (upk.offset << 1) + 2;
1378 case 29: /* RR Formats JR, JALR, JALR-RA */
1380 struct upk_mips16 upk;
1381 /* upk.fmt = rrtype; */
1386 upk.regx = (insn >> 8) & 0x07;
1387 upk.regy = (insn >> 5) & 0x07;
1395 break; /* Function return instruction */
1401 break; /* BOGUS Guess */
1403 pc = get_frame_register_signed (frame, reg);
1410 /* This is an instruction extension. Fetch the real instruction
1411 (which follows the extension) and decode things based on
1415 pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc));
1428 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
1430 unsigned int insn = fetch_mips_16 (pc);
1431 return extended_mips16_next_pc (frame, pc, 0, insn);
1434 /* The mips_next_pc function supports single_step when the remote
1435 target monitor or stub is not developed enough to do a single_step.
1436 It works by decoding the current instruction and predicting where a
1437 branch will go. This isnt hard because all the data is available.
1438 The MIPS32 and MIPS16 variants are quite different. */
1440 mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1442 if (is_mips16_addr (pc))
1443 return mips16_next_pc (frame, pc);
1445 return mips32_next_pc (frame, pc);
1448 struct mips_frame_cache
1451 struct trad_frame_saved_reg *saved_regs;
1454 /* Set a register's saved stack address in temp_saved_regs. If an
1455 address has already been set for this register, do nothing; this
1456 way we will only recognize the first save of a given register in a
1459 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1460 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1461 Strictly speaking, only the second range is used as it is only second
1462 range (the ABI instead of ISA registers) that comes into play when finding
1463 saved registers in a frame. */
1466 set_reg_offset (struct mips_frame_cache *this_cache, int regnum,
1469 if (this_cache != NULL
1470 && this_cache->saved_regs[regnum].addr == -1)
1472 this_cache->saved_regs[regnum
1473 + 0 * gdbarch_num_regs (current_gdbarch)].addr
1475 this_cache->saved_regs[regnum
1476 + 1 * gdbarch_num_regs (current_gdbarch)].addr
1482 /* Fetch the immediate value from a MIPS16 instruction.
1483 If the previous instruction was an EXTEND, use it to extend
1484 the upper bits of the immediate value. This is a helper function
1485 for mips16_scan_prologue. */
1488 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1489 unsigned short inst, /* current instruction */
1490 int nbits, /* number of bits in imm field */
1491 int scale, /* scale factor to be applied to imm */
1492 int is_signed) /* is the imm field signed? */
1496 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1498 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1499 if (offset & 0x8000) /* check for negative extend */
1500 offset = 0 - (0x10000 - (offset & 0xffff));
1501 return offset | (inst & 0x1f);
1505 int max_imm = 1 << nbits;
1506 int mask = max_imm - 1;
1507 int sign_bit = max_imm >> 1;
1509 offset = inst & mask;
1510 if (is_signed && (offset & sign_bit))
1511 offset = 0 - (max_imm - offset);
1512 return offset * scale;
1517 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1518 the associated FRAME_CACHE if not null.
1519 Return the address of the first instruction past the prologue. */
1522 mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1523 struct frame_info *next_frame,
1524 struct mips_frame_cache *this_cache)
1527 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1529 long frame_offset = 0; /* Size of stack frame. */
1530 long frame_adjust = 0; /* Offset of FP from SP. */
1531 int frame_reg = MIPS_SP_REGNUM;
1532 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1533 unsigned inst = 0; /* current instruction */
1534 unsigned entry_inst = 0; /* the entry instruction */
1537 int extend_bytes = 0;
1538 int prev_extend_bytes;
1539 CORE_ADDR end_prologue_addr = 0;
1540 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1542 /* Can be called when there's no process, and hence when there's no
1544 if (next_frame != NULL)
1545 sp = frame_unwind_register_signed (next_frame,
1546 gdbarch_num_regs (gdbarch)
1551 if (limit_pc > start_pc + 200)
1552 limit_pc = start_pc + 200;
1554 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
1556 /* Save the previous instruction. If it's an EXTEND, we'll extract
1557 the immediate offset extension from it in mips16_get_imm. */
1560 /* Fetch and decode the instruction. */
1561 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1563 /* Normally we ignore extend instructions. However, if it is
1564 not followed by a valid prologue instruction, then this
1565 instruction is not part of the prologue either. We must
1566 remember in this case to adjust the end_prologue_addr back
1568 if ((inst & 0xf800) == 0xf000) /* extend */
1570 extend_bytes = MIPS_INSN16_SIZE;
1574 prev_extend_bytes = extend_bytes;
1577 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1578 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1580 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1581 if (offset < 0) /* negative stack adjustment? */
1582 frame_offset -= offset;
1584 /* Exit loop if a positive stack adjustment is found, which
1585 usually means that the stack cleanup code in the function
1586 epilogue is reached. */
1589 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1591 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1592 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1593 set_reg_offset (this_cache, reg, sp + offset);
1595 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1597 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1598 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1599 set_reg_offset (this_cache, reg, sp + offset);
1601 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1603 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1604 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1606 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1608 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1609 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1611 else if (inst == 0x673d) /* move $s1, $sp */
1616 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1618 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1619 frame_addr = sp + offset;
1621 frame_adjust = offset;
1623 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1625 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1626 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1627 set_reg_offset (this_cache, reg, frame_addr + offset);
1629 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1631 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1632 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1633 set_reg_offset (this_cache, reg, frame_addr + offset);
1635 else if ((inst & 0xf81f) == 0xe809
1636 && (inst & 0x700) != 0x700) /* entry */
1637 entry_inst = inst; /* save for later processing */
1638 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1639 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
1640 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1642 /* This instruction is part of the prologue, but we don't
1643 need to do anything special to handle it. */
1647 /* This instruction is not an instruction typically found
1648 in a prologue, so we must have reached the end of the
1650 if (end_prologue_addr == 0)
1651 end_prologue_addr = cur_pc - prev_extend_bytes;
1655 /* The entry instruction is typically the first instruction in a function,
1656 and it stores registers at offsets relative to the value of the old SP
1657 (before the prologue). But the value of the sp parameter to this
1658 function is the new SP (after the prologue has been executed). So we
1659 can't calculate those offsets until we've seen the entire prologue,
1660 and can calculate what the old SP must have been. */
1661 if (entry_inst != 0)
1663 int areg_count = (entry_inst >> 8) & 7;
1664 int sreg_count = (entry_inst >> 6) & 3;
1666 /* The entry instruction always subtracts 32 from the SP. */
1669 /* Now we can calculate what the SP must have been at the
1670 start of the function prologue. */
1673 /* Check if a0-a3 were saved in the caller's argument save area. */
1674 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1676 set_reg_offset (this_cache, reg, sp + offset);
1677 offset += mips_abi_regsize (gdbarch);
1680 /* Check if the ra register was pushed on the stack. */
1682 if (entry_inst & 0x20)
1684 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1685 offset -= mips_abi_regsize (gdbarch);
1688 /* Check if the s0 and s1 registers were pushed on the stack. */
1689 for (reg = 16; reg < sreg_count + 16; reg++)
1691 set_reg_offset (this_cache, reg, sp + offset);
1692 offset -= mips_abi_regsize (gdbarch);
1696 if (this_cache != NULL)
1699 (frame_unwind_register_signed (next_frame,
1700 gdbarch_num_regs (gdbarch) + frame_reg)
1701 + frame_offset - frame_adjust);
1702 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1703 be able to get rid of the assignment below, evetually. But it's
1704 still needed for now. */
1705 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
1706 + mips_regnum (gdbarch)->pc]
1707 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
1710 /* If we didn't reach the end of the prologue when scanning the function
1711 instructions, then set end_prologue_addr to the address of the
1712 instruction immediately after the last one we scanned. */
1713 if (end_prologue_addr == 0)
1714 end_prologue_addr = cur_pc;
1716 return end_prologue_addr;
1719 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1720 Procedures that use the 32-bit instruction set are handled by the
1721 mips_insn32 unwinder. */
1723 static struct mips_frame_cache *
1724 mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache)
1726 struct mips_frame_cache *cache;
1728 if ((*this_cache) != NULL)
1729 return (*this_cache);
1730 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1731 (*this_cache) = cache;
1732 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1734 /* Analyze the function prologue. */
1736 const CORE_ADDR pc =
1737 frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
1738 CORE_ADDR start_addr;
1740 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1741 if (start_addr == 0)
1742 start_addr = heuristic_proc_start (pc);
1743 /* We can't analyze the prologue if we couldn't find the begining
1745 if (start_addr == 0)
1748 mips16_scan_prologue (start_addr, pc, next_frame, *this_cache);
1751 /* gdbarch_sp_regnum contains the value and not the address. */
1752 trad_frame_set_value (cache->saved_regs,
1753 gdbarch_num_regs (get_frame_arch (next_frame))
1757 return (*this_cache);
1761 mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache,
1762 struct frame_id *this_id)
1764 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1766 (*this_id) = frame_id_build (info->base,
1767 frame_func_unwind (next_frame, NORMAL_FRAME));
1771 mips_insn16_frame_prev_register (struct frame_info *next_frame,
1773 int regnum, int *optimizedp,
1774 enum lval_type *lvalp, CORE_ADDR *addrp,
1775 int *realnump, gdb_byte *valuep)
1777 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1779 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
1780 optimizedp, lvalp, addrp, realnump, valuep);
1783 static const struct frame_unwind mips_insn16_frame_unwind =
1786 mips_insn16_frame_this_id,
1787 mips_insn16_frame_prev_register
1790 static const struct frame_unwind *
1791 mips_insn16_frame_sniffer (struct frame_info *next_frame)
1793 CORE_ADDR pc = frame_pc_unwind (next_frame);
1794 if (mips_pc_is_mips16 (pc))
1795 return &mips_insn16_frame_unwind;
1800 mips_insn16_frame_base_address (struct frame_info *next_frame,
1803 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1808 static const struct frame_base mips_insn16_frame_base =
1810 &mips_insn16_frame_unwind,
1811 mips_insn16_frame_base_address,
1812 mips_insn16_frame_base_address,
1813 mips_insn16_frame_base_address
1816 static const struct frame_base *
1817 mips_insn16_frame_base_sniffer (struct frame_info *next_frame)
1819 if (mips_insn16_frame_sniffer (next_frame) != NULL)
1820 return &mips_insn16_frame_base;
1825 /* Mark all the registers as unset in the saved_regs array
1826 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1829 reset_saved_regs (struct mips_frame_cache *this_cache)
1831 if (this_cache == NULL || this_cache->saved_regs == NULL)
1835 const int num_regs = gdbarch_num_regs (current_gdbarch);
1838 for (i = 0; i < num_regs; i++)
1840 this_cache->saved_regs[i].addr = -1;
1845 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1846 the associated FRAME_CACHE if not null.
1847 Return the address of the first instruction past the prologue. */
1850 mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1851 struct frame_info *next_frame,
1852 struct mips_frame_cache *this_cache)
1855 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1858 int frame_reg = MIPS_SP_REGNUM;
1860 CORE_ADDR end_prologue_addr = 0;
1861 int seen_sp_adjust = 0;
1862 int load_immediate_bytes = 0;
1863 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1865 /* Can be called when there's no process, and hence when there's no
1867 if (next_frame != NULL)
1868 sp = frame_unwind_register_signed (next_frame,
1869 gdbarch_num_regs (gdbarch)
1874 if (limit_pc > start_pc + 200)
1875 limit_pc = start_pc + 200;
1880 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
1882 unsigned long inst, high_word, low_word;
1885 /* Fetch the instruction. */
1886 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1888 /* Save some code by pre-extracting some useful fields. */
1889 high_word = (inst >> 16) & 0xffff;
1890 low_word = inst & 0xffff;
1891 reg = high_word & 0x1f;
1893 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1894 || high_word == 0x23bd /* addi $sp,$sp,-i */
1895 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1897 if (low_word & 0x8000) /* negative stack adjustment? */
1898 frame_offset += 0x10000 - low_word;
1900 /* Exit loop if a positive stack adjustment is found, which
1901 usually means that the stack cleanup code in the function
1902 epilogue is reached. */
1906 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1908 set_reg_offset (this_cache, reg, sp + low_word);
1910 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1912 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1913 set_reg_offset (this_cache, reg, sp + low_word);
1915 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1917 /* Old gcc frame, r30 is virtual frame pointer. */
1918 if ((long) low_word != frame_offset)
1919 frame_addr = sp + low_word;
1920 else if (next_frame && frame_reg == MIPS_SP_REGNUM)
1922 unsigned alloca_adjust;
1925 frame_addr = frame_unwind_register_signed
1926 (next_frame, gdbarch_num_regs (gdbarch) + 30);
1928 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1929 if (alloca_adjust > 0)
1931 /* FP > SP + frame_size. This may be because of
1932 an alloca or somethings similar. Fix sp to
1933 "pre-alloca" value, and try again. */
1934 sp += alloca_adjust;
1935 /* Need to reset the status of all registers. Otherwise,
1936 we will hit a guard that prevents the new address
1937 for each register to be recomputed during the second
1939 reset_saved_regs (this_cache);
1944 /* move $30,$sp. With different versions of gas this will be either
1945 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1946 Accept any one of these. */
1947 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1949 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1950 if (next_frame && frame_reg == MIPS_SP_REGNUM)
1952 unsigned alloca_adjust;
1955 frame_addr = frame_unwind_register_signed
1956 (next_frame, gdbarch_num_regs (gdbarch) + 30);
1958 alloca_adjust = (unsigned) (frame_addr - sp);
1959 if (alloca_adjust > 0)
1961 /* FP > SP + frame_size. This may be because of
1962 an alloca or somethings similar. Fix sp to
1963 "pre-alloca" value, and try again. */
1965 /* Need to reset the status of all registers. Otherwise,
1966 we will hit a guard that prevents the new address
1967 for each register to be recomputed during the second
1969 reset_saved_regs (this_cache);
1974 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1976 set_reg_offset (this_cache, reg, frame_addr + low_word);
1978 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1979 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1980 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1981 || high_word == 0x3c1c /* lui $gp,n */
1982 || high_word == 0x279c /* addiu $gp,$gp,n */
1983 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
1984 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
1987 /* These instructions are part of the prologue, but we don't
1988 need to do anything special to handle them. */
1990 /* The instructions below load $at or $t0 with an immediate
1991 value in preparation for a stack adjustment via
1992 subu $sp,$sp,[$at,$t0]. These instructions could also
1993 initialize a local variable, so we accept them only before
1994 a stack adjustment instruction was seen. */
1995 else if (!seen_sp_adjust
1996 && (high_word == 0x3c01 /* lui $at,n */
1997 || high_word == 0x3c08 /* lui $t0,n */
1998 || high_word == 0x3421 /* ori $at,$at,n */
1999 || high_word == 0x3508 /* ori $t0,$t0,n */
2000 || high_word == 0x3401 /* ori $at,$zero,n */
2001 || high_word == 0x3408 /* ori $t0,$zero,n */
2004 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
2008 /* This instruction is not an instruction typically found
2009 in a prologue, so we must have reached the end of the
2011 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2012 loop now? Why would we need to continue scanning the function
2014 if (end_prologue_addr == 0)
2015 end_prologue_addr = cur_pc;
2019 if (this_cache != NULL)
2022 (frame_unwind_register_signed (next_frame,
2023 gdbarch_num_regs (gdbarch) + frame_reg)
2025 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2026 this assignment below, eventually. But it's still needed
2028 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2029 + mips_regnum (gdbarch)->pc]
2030 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2034 /* If we didn't reach the end of the prologue when scanning the function
2035 instructions, then set end_prologue_addr to the address of the
2036 instruction immediately after the last one we scanned. */
2037 /* brobecker/2004-10-10: I don't think this would ever happen, but
2038 we may as well be careful and do our best if we have a null
2039 end_prologue_addr. */
2040 if (end_prologue_addr == 0)
2041 end_prologue_addr = cur_pc;
2043 /* In a frameless function, we might have incorrectly
2044 skipped some load immediate instructions. Undo the skipping
2045 if the load immediate was not followed by a stack adjustment. */
2046 if (load_immediate_bytes && !seen_sp_adjust)
2047 end_prologue_addr -= load_immediate_bytes;
2049 return end_prologue_addr;
2052 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2053 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2054 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2057 static struct mips_frame_cache *
2058 mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
2060 struct mips_frame_cache *cache;
2062 if ((*this_cache) != NULL)
2063 return (*this_cache);
2065 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2066 (*this_cache) = cache;
2067 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2069 /* Analyze the function prologue. */
2071 const CORE_ADDR pc =
2072 frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
2073 CORE_ADDR start_addr;
2075 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2076 if (start_addr == 0)
2077 start_addr = heuristic_proc_start (pc);
2078 /* We can't analyze the prologue if we couldn't find the begining
2080 if (start_addr == 0)
2083 mips32_scan_prologue (start_addr, pc, next_frame, *this_cache);
2086 /* gdbarch_sp_regnum contains the value and not the address. */
2087 trad_frame_set_value (cache->saved_regs,
2088 gdbarch_num_regs (get_frame_arch (next_frame))
2092 return (*this_cache);
2096 mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache,
2097 struct frame_id *this_id)
2099 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
2101 (*this_id) = frame_id_build (info->base,
2102 frame_func_unwind (next_frame, NORMAL_FRAME));
2106 mips_insn32_frame_prev_register (struct frame_info *next_frame,
2108 int regnum, int *optimizedp,
2109 enum lval_type *lvalp, CORE_ADDR *addrp,
2110 int *realnump, gdb_byte *valuep)
2112 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
2114 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
2115 optimizedp, lvalp, addrp, realnump, valuep);
2118 static const struct frame_unwind mips_insn32_frame_unwind =
2121 mips_insn32_frame_this_id,
2122 mips_insn32_frame_prev_register
2125 static const struct frame_unwind *
2126 mips_insn32_frame_sniffer (struct frame_info *next_frame)
2128 CORE_ADDR pc = frame_pc_unwind (next_frame);
2129 if (! mips_pc_is_mips16 (pc))
2130 return &mips_insn32_frame_unwind;
2135 mips_insn32_frame_base_address (struct frame_info *next_frame,
2138 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
2143 static const struct frame_base mips_insn32_frame_base =
2145 &mips_insn32_frame_unwind,
2146 mips_insn32_frame_base_address,
2147 mips_insn32_frame_base_address,
2148 mips_insn32_frame_base_address
2151 static const struct frame_base *
2152 mips_insn32_frame_base_sniffer (struct frame_info *next_frame)
2154 if (mips_insn32_frame_sniffer (next_frame) != NULL)
2155 return &mips_insn32_frame_base;
2160 static struct trad_frame_cache *
2161 mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache)
2164 CORE_ADDR start_addr;
2165 CORE_ADDR stack_addr;
2166 struct trad_frame_cache *this_trad_cache;
2167 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2169 if ((*this_cache) != NULL)
2170 return (*this_cache);
2171 this_trad_cache = trad_frame_cache_zalloc (next_frame);
2172 (*this_cache) = this_trad_cache;
2174 /* The return address is in the link register. */
2175 trad_frame_set_reg_realreg (this_trad_cache,
2176 gdbarch_pc_regnum (gdbarch),
2177 (gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM));
2179 /* Frame ID, since it's a frameless / stackless function, no stack
2180 space is allocated and SP on entry is the current SP. */
2181 pc = frame_pc_unwind (next_frame);
2182 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2183 stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM);
2184 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
2186 /* Assume that the frame's base is the same as the
2188 trad_frame_set_this_base (this_trad_cache, stack_addr);
2190 return this_trad_cache;
2194 mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache,
2195 struct frame_id *this_id)
2197 struct trad_frame_cache *this_trad_cache
2198 = mips_stub_frame_cache (next_frame, this_cache);
2199 trad_frame_get_id (this_trad_cache, this_id);
2203 mips_stub_frame_prev_register (struct frame_info *next_frame,
2205 int regnum, int *optimizedp,
2206 enum lval_type *lvalp, CORE_ADDR *addrp,
2207 int *realnump, gdb_byte *valuep)
2209 struct trad_frame_cache *this_trad_cache
2210 = mips_stub_frame_cache (next_frame, this_cache);
2211 trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp,
2212 lvalp, addrp, realnump, valuep);
2215 static const struct frame_unwind mips_stub_frame_unwind =
2218 mips_stub_frame_this_id,
2219 mips_stub_frame_prev_register
2222 static const struct frame_unwind *
2223 mips_stub_frame_sniffer (struct frame_info *next_frame)
2226 struct obj_section *s;
2227 CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
2229 /* Use the stub unwinder for unreadable code. */
2230 if (target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0)
2231 return &mips_stub_frame_unwind;
2233 if (in_plt_section (pc, NULL))
2234 return &mips_stub_frame_unwind;
2236 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2237 s = find_pc_section (pc);
2240 && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
2241 ".MIPS.stubs") == 0)
2242 return &mips_stub_frame_unwind;
2248 mips_stub_frame_base_address (struct frame_info *next_frame,
2251 struct trad_frame_cache *this_trad_cache
2252 = mips_stub_frame_cache (next_frame, this_cache);
2253 return trad_frame_get_this_base (this_trad_cache);
2256 static const struct frame_base mips_stub_frame_base =
2258 &mips_stub_frame_unwind,
2259 mips_stub_frame_base_address,
2260 mips_stub_frame_base_address,
2261 mips_stub_frame_base_address
2264 static const struct frame_base *
2265 mips_stub_frame_base_sniffer (struct frame_info *next_frame)
2267 if (mips_stub_frame_sniffer (next_frame) != NULL)
2268 return &mips_stub_frame_base;
2273 /* mips_addr_bits_remove - remove useless address bits */
2276 mips_addr_bits_remove (CORE_ADDR addr)
2278 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2279 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
2280 /* This hack is a work-around for existing boards using PMON, the
2281 simulator, and any other 64-bit targets that doesn't have true
2282 64-bit addressing. On these targets, the upper 32 bits of
2283 addresses are ignored by the hardware. Thus, the PC or SP are
2284 likely to have been sign extended to all 1s by instruction
2285 sequences that load 32-bit addresses. For example, a typical
2286 piece of code that loads an address is this:
2288 lui $r2, <upper 16 bits>
2289 ori $r2, <lower 16 bits>
2291 But the lui sign-extends the value such that the upper 32 bits
2292 may be all 1s. The workaround is simply to mask off these
2293 bits. In the future, gcc may be changed to support true 64-bit
2294 addressing, and this masking will have to be disabled. */
2295 return addr &= 0xffffffffUL;
2300 /* mips_software_single_step() is called just before we want to resume
2301 the inferior, if we want to single-step it but there is no hardware
2302 or kernel single-step support (MIPS on GNU/Linux for example). We find
2303 the target of the coming instruction and breakpoint it. */
2306 mips_software_single_step (struct frame_info *frame)
2308 CORE_ADDR pc, next_pc;
2310 pc = get_frame_pc (frame);
2311 next_pc = mips_next_pc (frame, pc);
2313 insert_single_step_breakpoint (next_pc);
2317 /* Test whether the PC points to the return instruction at the
2318 end of a function. */
2321 mips_about_to_return (CORE_ADDR pc)
2323 if (mips_pc_is_mips16 (pc))
2324 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2325 generates a "jr $ra"; other times it generates code to load
2326 the return address from the stack to an accessible register (such
2327 as $a3), then a "jr" using that register. This second case
2328 is almost impossible to distinguish from an indirect jump
2329 used for switch statements, so we don't even try. */
2330 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
2332 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
2336 /* This fencepost looks highly suspicious to me. Removing it also
2337 seems suspicious as it could affect remote debugging across serial
2341 heuristic_proc_start (CORE_ADDR pc)
2348 pc = gdbarch_addr_bits_remove (current_gdbarch, pc);
2350 fence = start_pc - heuristic_fence_post;
2354 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
2355 fence = VM_MIN_ADDRESS;
2357 instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE;
2359 /* search back for previous return */
2360 for (start_pc -= instlen;; start_pc -= instlen)
2361 if (start_pc < fence)
2363 /* It's not clear to me why we reach this point when
2364 stop_soon, but with this test, at least we
2365 don't print out warnings for every child forked (eg, on
2366 decstation). 22apr93 rich@cygnus.com. */
2367 if (stop_soon == NO_STOP_QUIETLY)
2369 static int blurb_printed = 0;
2371 warning (_("GDB can't find the start of the function at 0x%s."),
2376 /* This actually happens frequently in embedded
2377 development, when you first connect to a board
2378 and your stack pointer and pc are nowhere in
2379 particular. This message needs to give people
2380 in that situation enough information to
2381 determine that it's no big deal. */
2382 printf_filtered ("\n\
2383 GDB is unable to find the start of the function at 0x%s\n\
2384 and thus can't determine the size of that function's stack frame.\n\
2385 This means that GDB may be unable to access that stack frame, or\n\
2386 the frames below it.\n\
2387 This problem is most likely caused by an invalid program counter or\n\
2389 However, if you think GDB should simply search farther back\n\
2390 from 0x%s for code which looks like the beginning of a\n\
2391 function, you can increase the range of the search using the `set\n\
2392 heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
2399 else if (mips_pc_is_mips16 (start_pc))
2401 unsigned short inst;
2403 /* On MIPS16, any one of the following is likely to be the
2404 start of a function:
2410 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2411 inst = mips_fetch_instruction (start_pc);
2412 if ((inst & 0xff80) == 0x6480) /* save */
2414 if (start_pc - instlen >= fence)
2416 inst = mips_fetch_instruction (start_pc - instlen);
2417 if ((inst & 0xf800) == 0xf000) /* extend */
2418 start_pc -= instlen;
2422 else if (((inst & 0xf81f) == 0xe809
2423 && (inst & 0x700) != 0x700) /* entry */
2424 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
2425 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
2426 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
2428 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
2429 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2434 else if (mips_about_to_return (start_pc))
2436 /* Skip return and its delay slot. */
2437 start_pc += 2 * MIPS_INSN32_SIZE;
2444 struct mips_objfile_private
2450 /* According to the current ABI, should the type be passed in a
2451 floating-point register (assuming that there is space)? When there
2452 is no FPU, FP are not even considered as possible candidates for
2453 FP registers and, consequently this returns false - forces FP
2454 arguments into integer registers. */
2457 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2459 return ((typecode == TYPE_CODE_FLT
2461 && (typecode == TYPE_CODE_STRUCT
2462 || typecode == TYPE_CODE_UNION)
2463 && TYPE_NFIELDS (arg_type) == 1
2464 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
2466 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2469 /* On o32, argument passing in GPRs depends on the alignment of the type being
2470 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2473 mips_type_needs_double_align (struct type *type)
2475 enum type_code typecode = TYPE_CODE (type);
2477 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2479 else if (typecode == TYPE_CODE_STRUCT)
2481 if (TYPE_NFIELDS (type) < 1)
2483 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2485 else if (typecode == TYPE_CODE_UNION)
2489 n = TYPE_NFIELDS (type);
2490 for (i = 0; i < n; i++)
2491 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2498 /* Adjust the address downward (direction of stack growth) so that it
2499 is correctly aligned for a new stack frame. */
2501 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2503 return align_down (addr, 16);
2507 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2508 struct regcache *regcache, CORE_ADDR bp_addr,
2509 int nargs, struct value **args, CORE_ADDR sp,
2510 int struct_return, CORE_ADDR struct_addr)
2516 int stack_offset = 0;
2517 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2518 CORE_ADDR func_addr = find_function_addr (function, NULL);
2519 int regsize = mips_abi_regsize (gdbarch);
2521 /* For shared libraries, "t9" needs to point at the function
2523 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2525 /* Set the return address register to point to the entry point of
2526 the program, where a breakpoint lies in wait. */
2527 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2529 /* First ensure that the stack and structure return address (if any)
2530 are properly aligned. The stack has to be at least 64-bit
2531 aligned even on 32-bit machines, because doubles must be 64-bit
2532 aligned. For n32 and n64, stack frames need to be 128-bit
2533 aligned, so we round to this widest known alignment. */
2535 sp = align_down (sp, 16);
2536 struct_addr = align_down (struct_addr, 16);
2538 /* Now make space on the stack for the args. We allocate more
2539 than necessary for EABI, because the first few arguments are
2540 passed in registers, but that's OK. */
2541 for (argnum = 0; argnum < nargs; argnum++)
2542 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
2543 sp -= align_up (len, 16);
2546 fprintf_unfiltered (gdb_stdlog,
2547 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2548 paddr_nz (sp), (long) align_up (len, 16));
2550 /* Initialize the integer and float register pointers. */
2551 argreg = MIPS_A0_REGNUM;
2552 float_argreg = mips_fpa0_regnum (gdbarch);
2554 /* The struct_return pointer occupies the first parameter-passing reg. */
2558 fprintf_unfiltered (gdb_stdlog,
2559 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2560 argreg, paddr_nz (struct_addr));
2561 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
2564 /* Now load as many as possible of the first arguments into
2565 registers, and push the rest onto the stack. Loop thru args
2566 from first to last. */
2567 for (argnum = 0; argnum < nargs; argnum++)
2569 const gdb_byte *val;
2570 gdb_byte valbuf[MAX_REGISTER_SIZE];
2571 struct value *arg = args[argnum];
2572 struct type *arg_type = check_typedef (value_type (arg));
2573 int len = TYPE_LENGTH (arg_type);
2574 enum type_code typecode = TYPE_CODE (arg_type);
2577 fprintf_unfiltered (gdb_stdlog,
2578 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2579 argnum + 1, len, (int) typecode);
2581 /* The EABI passes structures that do not fit in a register by
2584 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2586 store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg));
2587 typecode = TYPE_CODE_PTR;
2591 fprintf_unfiltered (gdb_stdlog, " push");
2594 val = value_contents (arg);
2596 /* 32-bit ABIs always start floating point arguments in an
2597 even-numbered floating point register. Round the FP register
2598 up before the check to see if there are any FP registers
2599 left. Non MIPS_EABI targets also pass the FP in the integer
2600 registers so also round up normal registers. */
2601 if (regsize < 8 && fp_register_arg_p (typecode, arg_type))
2603 if ((float_argreg & 1))
2607 /* Floating point arguments passed in registers have to be
2608 treated specially. On 32-bit architectures, doubles
2609 are passed in register pairs; the even register gets
2610 the low word, and the odd register gets the high word.
2611 On non-EABI processors, the first two floating point arguments are
2612 also copied to general registers, because MIPS16 functions
2613 don't use float registers for arguments. This duplication of
2614 arguments in general registers can't hurt non-MIPS16 functions
2615 because those registers are normally skipped. */
2616 /* MIPS_EABI squeezes a struct that contains a single floating
2617 point value into an FP register instead of pushing it onto the
2619 if (fp_register_arg_p (typecode, arg_type)
2620 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2622 /* EABI32 will pass doubles in consecutive registers, even on
2623 64-bit cores. At one time, we used to check the size of
2624 `float_argreg' to determine whether or not to pass doubles
2625 in consecutive registers, but this is not sufficient for
2626 making the ABI determination. */
2627 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
2629 int low_offset = gdbarch_byte_order (gdbarch)
2630 == BFD_ENDIAN_BIG ? 4 : 0;
2631 unsigned long regval;
2633 /* Write the low word of the double to the even register(s). */
2634 regval = extract_unsigned_integer (val + low_offset, 4);
2636 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2637 float_argreg, phex (regval, 4));
2638 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2640 /* Write the high word of the double to the odd register(s). */
2641 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2643 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2644 float_argreg, phex (regval, 4));
2645 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2649 /* This is a floating point value that fits entirely
2650 in a single register. */
2651 /* On 32 bit ABI's the float_argreg is further adjusted
2652 above to ensure that it is even register aligned. */
2653 LONGEST regval = extract_unsigned_integer (val, len);
2655 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2656 float_argreg, phex (regval, len));
2657 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2662 /* Copy the argument to general registers or the stack in
2663 register-sized pieces. Large arguments are split between
2664 registers and stack. */
2665 /* Note: structs whose size is not a multiple of regsize
2666 are treated specially: Irix cc passes
2667 them in registers where gcc sometimes puts them on the
2668 stack. For maximum compatibility, we will put them in
2670 int odd_sized_struct = (len > regsize && len % regsize != 0);
2672 /* Note: Floating-point values that didn't fit into an FP
2673 register are only written to memory. */
2676 /* Remember if the argument was written to the stack. */
2677 int stack_used_p = 0;
2678 int partial_len = (len < regsize ? len : regsize);
2681 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2684 /* Write this portion of the argument to the stack. */
2685 if (argreg > MIPS_LAST_ARG_REGNUM
2687 || fp_register_arg_p (typecode, arg_type))
2689 /* Should shorter than int integer values be
2690 promoted to int before being stored? */
2691 int longword_offset = 0;
2694 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2697 && (typecode == TYPE_CODE_INT
2698 || typecode == TYPE_CODE_PTR
2699 || typecode == TYPE_CODE_FLT) && len <= 4)
2700 longword_offset = regsize - len;
2701 else if ((typecode == TYPE_CODE_STRUCT
2702 || typecode == TYPE_CODE_UNION)
2703 && TYPE_LENGTH (arg_type) < regsize)
2704 longword_offset = regsize - len;
2709 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2710 paddr_nz (stack_offset));
2711 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2712 paddr_nz (longword_offset));
2715 addr = sp + stack_offset + longword_offset;
2720 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2722 for (i = 0; i < partial_len; i++)
2724 fprintf_unfiltered (gdb_stdlog, "%02x",
2728 write_memory (addr, val, partial_len);
2731 /* Note!!! This is NOT an else clause. Odd sized
2732 structs may go thru BOTH paths. Floating point
2733 arguments will not. */
2734 /* Write this portion of the argument to a general
2735 purpose register. */
2736 if (argreg <= MIPS_LAST_ARG_REGNUM
2737 && !fp_register_arg_p (typecode, arg_type))
2740 extract_unsigned_integer (val, partial_len);
2743 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2745 phex (regval, regsize));
2746 regcache_cooked_write_unsigned (regcache, argreg, regval);
2753 /* Compute the the offset into the stack at which we
2754 will copy the next parameter.
2756 In the new EABI (and the NABI32), the stack_offset
2757 only needs to be adjusted when it has been used. */
2760 stack_offset += align_up (partial_len, regsize);
2764 fprintf_unfiltered (gdb_stdlog, "\n");
2767 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2769 /* Return adjusted stack pointer. */
2773 /* Determine the return value convention being used. */
2775 static enum return_value_convention
2776 mips_eabi_return_value (struct gdbarch *gdbarch,
2777 struct type *type, struct regcache *regcache,
2778 gdb_byte *readbuf, const gdb_byte *writebuf)
2780 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2781 return RETURN_VALUE_STRUCT_CONVENTION;
2783 memset (readbuf, 0, TYPE_LENGTH (type));
2784 return RETURN_VALUE_REGISTER_CONVENTION;
2788 /* N32/N64 ABI stuff. */
2790 /* Search for a naturally aligned double at OFFSET inside a struct
2791 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2795 mips_n32n64_fp_arg_chunk_p (struct type *arg_type, int offset)
2799 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
2802 if (MIPS_FPU_TYPE != MIPS_FPU_DOUBLE)
2805 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
2808 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
2811 struct type *field_type;
2813 /* We're only looking at normal fields. */
2814 if (TYPE_FIELD_STATIC (arg_type, i)
2815 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
2818 /* If we have gone past the offset, there is no double to pass. */
2819 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
2823 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
2825 /* If this field is entirely before the requested offset, go
2826 on to the next one. */
2827 if (pos + TYPE_LENGTH (field_type) <= offset)
2830 /* If this is our special aligned double, we can stop. */
2831 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
2832 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
2835 /* This field starts at or before the requested offset, and
2836 overlaps it. If it is a structure, recurse inwards. */
2837 return mips_n32n64_fp_arg_chunk_p (field_type, offset - pos);
2844 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2845 struct regcache *regcache, CORE_ADDR bp_addr,
2846 int nargs, struct value **args, CORE_ADDR sp,
2847 int struct_return, CORE_ADDR struct_addr)
2853 int stack_offset = 0;
2854 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2855 CORE_ADDR func_addr = find_function_addr (function, NULL);
2857 /* For shared libraries, "t9" needs to point at the function
2859 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2861 /* Set the return address register to point to the entry point of
2862 the program, where a breakpoint lies in wait. */
2863 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2865 /* First ensure that the stack and structure return address (if any)
2866 are properly aligned. The stack has to be at least 64-bit
2867 aligned even on 32-bit machines, because doubles must be 64-bit
2868 aligned. For n32 and n64, stack frames need to be 128-bit
2869 aligned, so we round to this widest known alignment. */
2871 sp = align_down (sp, 16);
2872 struct_addr = align_down (struct_addr, 16);
2874 /* Now make space on the stack for the args. */
2875 for (argnum = 0; argnum < nargs; argnum++)
2876 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
2877 sp -= align_up (len, 16);
2880 fprintf_unfiltered (gdb_stdlog,
2881 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2882 paddr_nz (sp), (long) align_up (len, 16));
2884 /* Initialize the integer and float register pointers. */
2885 argreg = MIPS_A0_REGNUM;
2886 float_argreg = mips_fpa0_regnum (gdbarch);
2888 /* The struct_return pointer occupies the first parameter-passing reg. */
2892 fprintf_unfiltered (gdb_stdlog,
2893 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2894 argreg, paddr_nz (struct_addr));
2895 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
2898 /* Now load as many as possible of the first arguments into
2899 registers, and push the rest onto the stack. Loop thru args
2900 from first to last. */
2901 for (argnum = 0; argnum < nargs; argnum++)
2903 const gdb_byte *val;
2904 struct value *arg = args[argnum];
2905 struct type *arg_type = check_typedef (value_type (arg));
2906 int len = TYPE_LENGTH (arg_type);
2907 enum type_code typecode = TYPE_CODE (arg_type);
2910 fprintf_unfiltered (gdb_stdlog,
2911 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2912 argnum + 1, len, (int) typecode);
2914 val = value_contents (arg);
2916 if (fp_register_arg_p (typecode, arg_type)
2917 && argreg <= MIPS_LAST_ARG_REGNUM)
2919 /* This is a floating point value that fits entirely
2920 in a single register. */
2921 LONGEST regval = extract_unsigned_integer (val, len);
2923 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2924 float_argreg, phex (regval, len));
2925 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
2928 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2929 argreg, phex (regval, len));
2930 regcache_cooked_write_unsigned (regcache, argreg, regval);
2936 /* Copy the argument to general registers or the stack in
2937 register-sized pieces. Large arguments are split between
2938 registers and stack. */
2939 /* For N32/N64, structs, unions, or other composite types are
2940 treated as a sequence of doublewords, and are passed in integer
2941 or floating point registers as though they were simple scalar
2942 parameters to the extent that they fit, with any excess on the
2943 stack packed according to the normal memory layout of the
2945 The caller does not reserve space for the register arguments;
2946 the callee is responsible for reserving it if required. */
2947 /* Note: Floating-point values that didn't fit into an FP
2948 register are only written to memory. */
2951 /* Remember if the argument was written to the stack. */
2952 int stack_used_p = 0;
2953 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
2956 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2959 if (fp_register_arg_p (typecode, arg_type))
2960 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM);
2962 /* Write this portion of the argument to the stack. */
2963 if (argreg > MIPS_LAST_ARG_REGNUM)
2965 /* Should shorter than int integer values be
2966 promoted to int before being stored? */
2967 int longword_offset = 0;
2970 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2972 if ((typecode == TYPE_CODE_INT
2973 || typecode == TYPE_CODE_PTR
2974 || typecode == TYPE_CODE_FLT)
2976 longword_offset = MIPS64_REGSIZE - len;
2981 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2982 paddr_nz (stack_offset));
2983 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2984 paddr_nz (longword_offset));
2987 addr = sp + stack_offset + longword_offset;
2992 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2994 for (i = 0; i < partial_len; i++)
2996 fprintf_unfiltered (gdb_stdlog, "%02x",
3000 write_memory (addr, val, partial_len);
3003 /* Note!!! This is NOT an else clause. Odd sized
3004 structs may go thru BOTH paths. */
3005 /* Write this portion of the argument to a general
3006 purpose register. */
3007 if (argreg <= MIPS_LAST_ARG_REGNUM)
3010 extract_unsigned_integer (val, partial_len);
3012 /* A non-floating-point argument being passed in a
3013 general register. If a struct or union, and if
3014 the remaining length is smaller than the register
3015 size, we have to adjust the register value on
3018 It does not seem to be necessary to do the
3019 same for integral types. */
3021 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3022 && partial_len < MIPS64_REGSIZE
3023 && (typecode == TYPE_CODE_STRUCT
3024 || typecode == TYPE_CODE_UNION))
3025 regval <<= ((MIPS64_REGSIZE - partial_len)
3029 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3031 phex (regval, MIPS64_REGSIZE));
3032 regcache_cooked_write_unsigned (regcache, argreg, regval);
3034 if (mips_n32n64_fp_arg_chunk_p (arg_type,
3035 TYPE_LENGTH (arg_type) - len))
3038 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
3040 phex (regval, MIPS64_REGSIZE));
3041 regcache_cooked_write_unsigned (regcache, float_argreg,
3052 /* Compute the the offset into the stack at which we
3053 will copy the next parameter.
3055 In N32 (N64?), the stack_offset only needs to be
3056 adjusted when it has been used. */
3059 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
3063 fprintf_unfiltered (gdb_stdlog, "\n");
3066 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3068 /* Return adjusted stack pointer. */
3072 static enum return_value_convention
3073 mips_n32n64_return_value (struct gdbarch *gdbarch,
3074 struct type *type, struct regcache *regcache,
3075 gdb_byte *readbuf, const gdb_byte *writebuf)
3077 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3079 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3081 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3082 if needed), as appropriate for the type. Composite results (struct,
3083 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3086 * A struct with only one or two floating point fields is returned in $f0
3087 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3090 * Any other struct or union results of at most 128 bits are returned in
3091 $2 (first 64 bits) and $3 (remainder, if necessary).
3093 * Larger composite results are handled by converting the function to a
3094 procedure with an implicit first parameter, which is a pointer to an area
3095 reserved by the caller to receive the result. [The o32-bit ABI requires
3096 that all composite results be handled by conversion to implicit first
3097 parameters. The MIPS/SGI Fortran implementation has always made a
3098 specific exception to return COMPLEX results in the floating point
3101 if (TYPE_CODE (type) == TYPE_CODE_ARRAY
3102 || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
3103 return RETURN_VALUE_STRUCT_CONVENTION;
3104 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3105 && TYPE_LENGTH (type) == 16
3106 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3108 /* A 128-bit floating-point value fills both $f0 and $f2. The
3109 two registers are used in the same as memory order, so the
3110 eight bytes with the lower memory address are in $f0. */
3112 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
3113 mips_xfer_register (regcache,
3114 gdbarch_num_regs (gdbarch)
3115 + mips_regnum (gdbarch)->fp0,
3116 8, gdbarch_byte_order (gdbarch),
3117 readbuf, writebuf, 0);
3118 mips_xfer_register (regcache,
3119 gdbarch_num_regs (gdbarch)
3120 + mips_regnum (gdbarch)->fp0 + 2,
3121 8, gdbarch_byte_order (gdbarch),
3122 readbuf ? readbuf + 8 : readbuf,
3123 writebuf ? writebuf + 8 : writebuf, 0);
3124 return RETURN_VALUE_REGISTER_CONVENTION;
3126 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3127 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3129 /* A single or double floating-point value that fits in FP0. */
3131 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3132 mips_xfer_register (regcache,
3133 gdbarch_num_regs (gdbarch)
3134 + mips_regnum (gdbarch)->fp0,
3136 gdbarch_byte_order (gdbarch),
3137 readbuf, writebuf, 0);
3138 return RETURN_VALUE_REGISTER_CONVENTION;
3140 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3141 && TYPE_NFIELDS (type) <= 2
3142 && TYPE_NFIELDS (type) >= 1
3143 && ((TYPE_NFIELDS (type) == 1
3144 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3146 || (TYPE_NFIELDS (type) == 2
3147 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3149 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
3151 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3153 /* A struct that contains one or two floats. Each value is part
3154 in the least significant part of their floating point
3158 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
3159 field < TYPE_NFIELDS (type); field++, regnum += 2)
3161 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3164 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3166 mips_xfer_register (regcache, gdbarch_num_regs (gdbarch)
3168 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3169 gdbarch_byte_order (gdbarch),
3170 readbuf, writebuf, offset);
3172 return RETURN_VALUE_REGISTER_CONVENTION;
3174 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3175 || TYPE_CODE (type) == TYPE_CODE_UNION)
3177 /* A structure or union. Extract the left justified value,
3178 regardless of the byte order. I.e. DO NOT USE
3182 for (offset = 0, regnum = MIPS_V0_REGNUM;
3183 offset < TYPE_LENGTH (type);
3184 offset += register_size (gdbarch, regnum), regnum++)
3186 int xfer = register_size (gdbarch, regnum);
3187 if (offset + xfer > TYPE_LENGTH (type))
3188 xfer = TYPE_LENGTH (type) - offset;
3190 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3191 offset, xfer, regnum);
3192 mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) + regnum,
3193 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
3196 return RETURN_VALUE_REGISTER_CONVENTION;
3200 /* A scalar extract each part but least-significant-byte
3204 for (offset = 0, regnum = MIPS_V0_REGNUM;
3205 offset < TYPE_LENGTH (type);
3206 offset += register_size (gdbarch, regnum), regnum++)
3208 int xfer = register_size (gdbarch, regnum);
3209 if (offset + xfer > TYPE_LENGTH (type))
3210 xfer = TYPE_LENGTH (type) - offset;
3212 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3213 offset, xfer, regnum);
3214 mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) + regnum,
3215 xfer, gdbarch_byte_order (gdbarch),
3216 readbuf, writebuf, offset);
3218 return RETURN_VALUE_REGISTER_CONVENTION;
3222 /* O32 ABI stuff. */
3225 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3226 struct regcache *regcache, CORE_ADDR bp_addr,
3227 int nargs, struct value **args, CORE_ADDR sp,
3228 int struct_return, CORE_ADDR struct_addr)
3234 int stack_offset = 0;
3235 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3236 CORE_ADDR func_addr = find_function_addr (function, NULL);
3238 /* For shared libraries, "t9" needs to point at the function
3240 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3242 /* Set the return address register to point to the entry point of
3243 the program, where a breakpoint lies in wait. */
3244 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3246 /* First ensure that the stack and structure return address (if any)
3247 are properly aligned. The stack has to be at least 64-bit
3248 aligned even on 32-bit machines, because doubles must be 64-bit
3249 aligned. For n32 and n64, stack frames need to be 128-bit
3250 aligned, so we round to this widest known alignment. */
3252 sp = align_down (sp, 16);
3253 struct_addr = align_down (struct_addr, 16);
3255 /* Now make space on the stack for the args. */
3256 for (argnum = 0; argnum < nargs; argnum++)
3258 struct type *arg_type = check_typedef (value_type (args[argnum]));
3259 int arglen = TYPE_LENGTH (arg_type);
3261 /* Align to double-word if necessary. */
3262 if (mips_type_needs_double_align (arg_type))
3263 len = align_up (len, MIPS32_REGSIZE * 2);
3264 /* Allocate space on the stack. */
3265 len += align_up (arglen, MIPS32_REGSIZE);
3267 sp -= align_up (len, 16);
3270 fprintf_unfiltered (gdb_stdlog,
3271 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3272 paddr_nz (sp), (long) align_up (len, 16));
3274 /* Initialize the integer and float register pointers. */
3275 argreg = MIPS_A0_REGNUM;
3276 float_argreg = mips_fpa0_regnum (gdbarch);
3278 /* The struct_return pointer occupies the first parameter-passing reg. */
3282 fprintf_unfiltered (gdb_stdlog,
3283 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3284 argreg, paddr_nz (struct_addr));
3285 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3286 stack_offset += MIPS32_REGSIZE;
3289 /* Now load as many as possible of the first arguments into
3290 registers, and push the rest onto the stack. Loop thru args
3291 from first to last. */
3292 for (argnum = 0; argnum < nargs; argnum++)
3294 const gdb_byte *val;
3295 struct value *arg = args[argnum];
3296 struct type *arg_type = check_typedef (value_type (arg));
3297 int len = TYPE_LENGTH (arg_type);
3298 enum type_code typecode = TYPE_CODE (arg_type);
3301 fprintf_unfiltered (gdb_stdlog,
3302 "mips_o32_push_dummy_call: %d len=%d type=%d",
3303 argnum + 1, len, (int) typecode);
3305 val = value_contents (arg);
3307 /* 32-bit ABIs always start floating point arguments in an
3308 even-numbered floating point register. Round the FP register
3309 up before the check to see if there are any FP registers
3310 left. O32/O64 targets also pass the FP in the integer
3311 registers so also round up normal registers. */
3312 if (fp_register_arg_p (typecode, arg_type))
3314 if ((float_argreg & 1))
3318 /* Floating point arguments passed in registers have to be
3319 treated specially. On 32-bit architectures, doubles
3320 are passed in register pairs; the even register gets
3321 the low word, and the odd register gets the high word.
3322 On O32/O64, the first two floating point arguments are
3323 also copied to general registers, because MIPS16 functions
3324 don't use float registers for arguments. This duplication of
3325 arguments in general registers can't hurt non-MIPS16 functions
3326 because those registers are normally skipped. */
3328 if (fp_register_arg_p (typecode, arg_type)
3329 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3331 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
3333 int low_offset = gdbarch_byte_order (gdbarch)
3334 == BFD_ENDIAN_BIG ? 4 : 0;
3335 unsigned long regval;
3337 /* Write the low word of the double to the even register(s). */
3338 regval = extract_unsigned_integer (val + low_offset, 4);
3340 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3341 float_argreg, phex (regval, 4));
3342 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3344 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3345 argreg, phex (regval, 4));
3346 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3348 /* Write the high word of the double to the odd register(s). */
3349 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3351 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3352 float_argreg, phex (regval, 4));
3353 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3356 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3357 argreg, phex (regval, 4));
3358 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3362 /* This is a floating point value that fits entirely
3363 in a single register. */
3364 /* On 32 bit ABI's the float_argreg is further adjusted
3365 above to ensure that it is even register aligned. */
3366 LONGEST regval = extract_unsigned_integer (val, len);
3368 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3369 float_argreg, phex (regval, len));
3370 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3371 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3372 registers for each argument. The below is (my
3373 guess) to ensure that the corresponding integer
3374 register has reserved the same space. */
3376 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3377 argreg, phex (regval, len));
3378 regcache_cooked_write_unsigned (regcache, argreg, regval);
3381 /* Reserve space for the FP register. */
3382 stack_offset += align_up (len, MIPS32_REGSIZE);
3386 /* Copy the argument to general registers or the stack in
3387 register-sized pieces. Large arguments are split between
3388 registers and stack. */
3389 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3390 are treated specially: Irix cc passes
3391 them in registers where gcc sometimes puts them on the
3392 stack. For maximum compatibility, we will put them in
3394 int odd_sized_struct = (len > MIPS32_REGSIZE
3395 && len % MIPS32_REGSIZE != 0);
3396 /* Structures should be aligned to eight bytes (even arg registers)
3397 on MIPS_ABI_O32, if their first member has double precision. */
3398 if (mips_type_needs_double_align (arg_type))
3403 stack_offset += MIPS32_REGSIZE;
3408 /* Remember if the argument was written to the stack. */
3409 int stack_used_p = 0;
3410 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
3413 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3416 /* Write this portion of the argument to the stack. */
3417 if (argreg > MIPS_LAST_ARG_REGNUM
3418 || odd_sized_struct)
3420 /* Should shorter than int integer values be
3421 promoted to int before being stored? */
3422 int longword_offset = 0;
3428 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3429 paddr_nz (stack_offset));
3430 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3431 paddr_nz (longword_offset));
3434 addr = sp + stack_offset + longword_offset;
3439 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3441 for (i = 0; i < partial_len; i++)
3443 fprintf_unfiltered (gdb_stdlog, "%02x",
3447 write_memory (addr, val, partial_len);
3450 /* Note!!! This is NOT an else clause. Odd sized
3451 structs may go thru BOTH paths. */
3452 /* Write this portion of the argument to a general
3453 purpose register. */
3454 if (argreg <= MIPS_LAST_ARG_REGNUM)
3456 LONGEST regval = extract_signed_integer (val, partial_len);
3457 /* Value may need to be sign extended, because
3458 mips_isa_regsize() != mips_abi_regsize(). */
3460 /* A non-floating-point argument being passed in a
3461 general register. If a struct or union, and if
3462 the remaining length is smaller than the register
3463 size, we have to adjust the register value on
3466 It does not seem to be necessary to do the
3467 same for integral types.
3469 Also don't do this adjustment on O64 binaries.
3471 cagney/2001-07-23: gdb/179: Also, GCC, when
3472 outputting LE O32 with sizeof (struct) <
3473 mips_abi_regsize(), generates a left shift
3474 as part of storing the argument in a register
3475 (the left shift isn't generated when
3476 sizeof (struct) >= mips_abi_regsize()). Since
3477 it is quite possible that this is GCC
3478 contradicting the LE/O32 ABI, GDB has not been
3479 adjusted to accommodate this. Either someone
3480 needs to demonstrate that the LE/O32 ABI
3481 specifies such a left shift OR this new ABI gets
3482 identified as such and GDB gets tweaked
3485 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3486 && partial_len < MIPS32_REGSIZE
3487 && (typecode == TYPE_CODE_STRUCT
3488 || typecode == TYPE_CODE_UNION))
3489 regval <<= ((MIPS32_REGSIZE - partial_len)
3493 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3495 phex (regval, MIPS32_REGSIZE));
3496 regcache_cooked_write_unsigned (regcache, argreg, regval);
3499 /* Prevent subsequent floating point arguments from
3500 being passed in floating point registers. */
3501 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3507 /* Compute the the offset into the stack at which we
3508 will copy the next parameter.
3510 In older ABIs, the caller reserved space for
3511 registers that contained arguments. This was loosely
3512 refered to as their "home". Consequently, space is
3513 always allocated. */
3515 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
3519 fprintf_unfiltered (gdb_stdlog, "\n");
3522 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3524 /* Return adjusted stack pointer. */
3528 static enum return_value_convention
3529 mips_o32_return_value (struct gdbarch *gdbarch, struct type *type,
3530 struct regcache *regcache,
3531 gdb_byte *readbuf, const gdb_byte *writebuf)
3533 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3535 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3536 || TYPE_CODE (type) == TYPE_CODE_UNION
3537 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3538 return RETURN_VALUE_STRUCT_CONVENTION;
3539 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3540 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3542 /* A single-precision floating-point value. It fits in the
3543 least significant part of FP0. */
3545 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3546 mips_xfer_register (regcache,
3547 gdbarch_num_regs (gdbarch)
3548 + mips_regnum (gdbarch)->fp0,
3550 gdbarch_byte_order (gdbarch),
3551 readbuf, writebuf, 0);
3552 return RETURN_VALUE_REGISTER_CONVENTION;
3554 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3555 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3557 /* A double-precision floating-point value. The most
3558 significant part goes in FP1, and the least significant in
3561 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3562 switch (gdbarch_byte_order (gdbarch))
3564 case BFD_ENDIAN_LITTLE:
3565 mips_xfer_register (regcache,
3566 gdbarch_num_regs (gdbarch)
3567 + mips_regnum (gdbarch)->fp0 +
3568 0, 4, gdbarch_byte_order (gdbarch),
3569 readbuf, writebuf, 0);
3570 mips_xfer_register (regcache,
3571 gdbarch_num_regs (gdbarch)
3572 + mips_regnum (gdbarch)->fp0 + 1,
3573 4, gdbarch_byte_order (gdbarch),
3574 readbuf, writebuf, 4);
3576 case BFD_ENDIAN_BIG:
3577 mips_xfer_register (regcache,
3578 gdbarch_num_regs (gdbarch)
3579 + mips_regnum (gdbarch)->fp0 + 1,
3580 4, gdbarch_byte_order (gdbarch),
3581 readbuf, writebuf, 0);
3582 mips_xfer_register (regcache,
3583 gdbarch_num_regs (gdbarch)
3584 + mips_regnum (gdbarch)->fp0 + 0,
3585 4, gdbarch_byte_order (gdbarch),
3586 readbuf, writebuf, 4);
3589 internal_error (__FILE__, __LINE__, _("bad switch"));
3591 return RETURN_VALUE_REGISTER_CONVENTION;
3594 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3595 && TYPE_NFIELDS (type) <= 2
3596 && TYPE_NFIELDS (type) >= 1
3597 && ((TYPE_NFIELDS (type) == 1
3598 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3600 || (TYPE_NFIELDS (type) == 2
3601 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3603 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3605 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3607 /* A struct that contains one or two floats. Each value is part
3608 in the least significant part of their floating point
3610 gdb_byte reg[MAX_REGISTER_SIZE];
3613 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
3614 field < TYPE_NFIELDS (type); field++, regnum += 2)
3616 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3619 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3621 mips_xfer_register (regcache, gdbarch_num_regs (gdbarch)
3623 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3624 gdbarch_byte_order (gdbarch),
3625 readbuf, writebuf, offset);
3627 return RETURN_VALUE_REGISTER_CONVENTION;
3631 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3632 || TYPE_CODE (type) == TYPE_CODE_UNION)
3634 /* A structure or union. Extract the left justified value,
3635 regardless of the byte order. I.e. DO NOT USE
3639 for (offset = 0, regnum = MIPS_V0_REGNUM;
3640 offset < TYPE_LENGTH (type);
3641 offset += register_size (gdbarch, regnum), regnum++)
3643 int xfer = register_size (gdbarch, regnum);
3644 if (offset + xfer > TYPE_LENGTH (type))
3645 xfer = TYPE_LENGTH (type) - offset;
3647 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3648 offset, xfer, regnum);
3649 mips_xfer_register (regcache, gdbarch_num_regs (gdbarch)
3651 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3653 return RETURN_VALUE_REGISTER_CONVENTION;
3658 /* A scalar extract each part but least-significant-byte
3659 justified. o32 thinks registers are 4 byte, regardless of
3663 for (offset = 0, regnum = MIPS_V0_REGNUM;
3664 offset < TYPE_LENGTH (type);
3665 offset += MIPS32_REGSIZE, regnum++)
3667 int xfer = MIPS32_REGSIZE;
3668 if (offset + xfer > TYPE_LENGTH (type))
3669 xfer = TYPE_LENGTH (type) - offset;
3671 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3672 offset, xfer, regnum);
3673 mips_xfer_register (regcache, gdbarch_num_regs (gdbarch)
3675 gdbarch_byte_order (gdbarch),
3676 readbuf, writebuf, offset);
3678 return RETURN_VALUE_REGISTER_CONVENTION;
3682 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3686 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3687 struct regcache *regcache, CORE_ADDR bp_addr,
3689 struct value **args, CORE_ADDR sp,
3690 int struct_return, CORE_ADDR struct_addr)
3696 int stack_offset = 0;
3697 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3698 CORE_ADDR func_addr = find_function_addr (function, NULL);
3700 /* For shared libraries, "t9" needs to point at the function
3702 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3704 /* Set the return address register to point to the entry point of
3705 the program, where a breakpoint lies in wait. */
3706 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3708 /* First ensure that the stack and structure return address (if any)
3709 are properly aligned. The stack has to be at least 64-bit
3710 aligned even on 32-bit machines, because doubles must be 64-bit
3711 aligned. For n32 and n64, stack frames need to be 128-bit
3712 aligned, so we round to this widest known alignment. */
3714 sp = align_down (sp, 16);
3715 struct_addr = align_down (struct_addr, 16);
3717 /* Now make space on the stack for the args. */
3718 for (argnum = 0; argnum < nargs; argnum++)
3720 struct type *arg_type = check_typedef (value_type (args[argnum]));
3721 int arglen = TYPE_LENGTH (arg_type);
3723 /* Allocate space on the stack. */
3724 len += align_up (arglen, MIPS64_REGSIZE);
3726 sp -= align_up (len, 16);
3729 fprintf_unfiltered (gdb_stdlog,
3730 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3731 paddr_nz (sp), (long) align_up (len, 16));
3733 /* Initialize the integer and float register pointers. */
3734 argreg = MIPS_A0_REGNUM;
3735 float_argreg = mips_fpa0_regnum (gdbarch);
3737 /* The struct_return pointer occupies the first parameter-passing reg. */
3741 fprintf_unfiltered (gdb_stdlog,
3742 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3743 argreg, paddr_nz (struct_addr));
3744 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3745 stack_offset += MIPS64_REGSIZE;
3748 /* Now load as many as possible of the first arguments into
3749 registers, and push the rest onto the stack. Loop thru args
3750 from first to last. */
3751 for (argnum = 0; argnum < nargs; argnum++)
3753 const gdb_byte *val;
3754 struct value *arg = args[argnum];
3755 struct type *arg_type = check_typedef (value_type (arg));
3756 int len = TYPE_LENGTH (arg_type);
3757 enum type_code typecode = TYPE_CODE (arg_type);
3760 fprintf_unfiltered (gdb_stdlog,
3761 "mips_o64_push_dummy_call: %d len=%d type=%d",
3762 argnum + 1, len, (int) typecode);
3764 val = value_contents (arg);
3766 /* Floating point arguments passed in registers have to be
3767 treated specially. On 32-bit architectures, doubles
3768 are passed in register pairs; the even register gets
3769 the low word, and the odd register gets the high word.
3770 On O32/O64, the first two floating point arguments are
3771 also copied to general registers, because MIPS16 functions
3772 don't use float registers for arguments. This duplication of
3773 arguments in general registers can't hurt non-MIPS16 functions
3774 because those registers are normally skipped. */
3776 if (fp_register_arg_p (typecode, arg_type)
3777 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3779 LONGEST regval = extract_unsigned_integer (val, len);
3781 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3782 float_argreg, phex (regval, len));
3783 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3785 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3786 argreg, phex (regval, len));
3787 regcache_cooked_write_unsigned (regcache, argreg, regval);
3789 /* Reserve space for the FP register. */
3790 stack_offset += align_up (len, MIPS64_REGSIZE);
3794 /* Copy the argument to general registers or the stack in
3795 register-sized pieces. Large arguments are split between
3796 registers and stack. */
3797 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3798 are treated specially: Irix cc passes them in registers
3799 where gcc sometimes puts them on the stack. For maximum
3800 compatibility, we will put them in both places. */
3801 int odd_sized_struct = (len > MIPS64_REGSIZE
3802 && len % MIPS64_REGSIZE != 0);
3805 /* Remember if the argument was written to the stack. */
3806 int stack_used_p = 0;
3807 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3810 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3813 /* Write this portion of the argument to the stack. */
3814 if (argreg > MIPS_LAST_ARG_REGNUM
3815 || odd_sized_struct)
3817 /* Should shorter than int integer values be
3818 promoted to int before being stored? */
3819 int longword_offset = 0;
3822 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
3824 if ((typecode == TYPE_CODE_INT
3825 || typecode == TYPE_CODE_PTR
3826 || typecode == TYPE_CODE_FLT)
3828 longword_offset = MIPS64_REGSIZE - len;
3833 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3834 paddr_nz (stack_offset));
3835 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3836 paddr_nz (longword_offset));
3839 addr = sp + stack_offset + longword_offset;
3844 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3846 for (i = 0; i < partial_len; i++)
3848 fprintf_unfiltered (gdb_stdlog, "%02x",
3852 write_memory (addr, val, partial_len);
3855 /* Note!!! This is NOT an else clause. Odd sized
3856 structs may go thru BOTH paths. */
3857 /* Write this portion of the argument to a general
3858 purpose register. */
3859 if (argreg <= MIPS_LAST_ARG_REGNUM)
3861 LONGEST regval = extract_signed_integer (val, partial_len);
3862 /* Value may need to be sign extended, because
3863 mips_isa_regsize() != mips_abi_regsize(). */
3865 /* A non-floating-point argument being passed in a
3866 general register. If a struct or union, and if
3867 the remaining length is smaller than the register
3868 size, we have to adjust the register value on
3871 It does not seem to be necessary to do the
3872 same for integral types. */
3874 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3875 && partial_len < MIPS64_REGSIZE
3876 && (typecode == TYPE_CODE_STRUCT
3877 || typecode == TYPE_CODE_UNION))
3878 regval <<= ((MIPS64_REGSIZE - partial_len)
3882 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3884 phex (regval, MIPS64_REGSIZE));
3885 regcache_cooked_write_unsigned (regcache, argreg, regval);
3888 /* Prevent subsequent floating point arguments from
3889 being passed in floating point registers. */
3890 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3896 /* Compute the the offset into the stack at which we
3897 will copy the next parameter.
3899 In older ABIs, the caller reserved space for
3900 registers that contained arguments. This was loosely
3901 refered to as their "home". Consequently, space is
3902 always allocated. */
3904 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
3908 fprintf_unfiltered (gdb_stdlog, "\n");
3911 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3913 /* Return adjusted stack pointer. */
3917 static enum return_value_convention
3918 mips_o64_return_value (struct gdbarch *gdbarch,
3919 struct type *type, struct regcache *regcache,
3920 gdb_byte *readbuf, const gdb_byte *writebuf)
3922 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3924 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3925 || TYPE_CODE (type) == TYPE_CODE_UNION
3926 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3927 return RETURN_VALUE_STRUCT_CONVENTION;
3928 else if (fp_register_arg_p (TYPE_CODE (type), type))
3930 /* A floating-point value. It fits in the least significant
3933 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3934 mips_xfer_register (regcache,
3935 gdbarch_num_regs (gdbarch)
3936 + mips_regnum (gdbarch)->fp0,
3938 gdbarch_byte_order (gdbarch),
3939 readbuf, writebuf, 0);
3940 return RETURN_VALUE_REGISTER_CONVENTION;
3944 /* A scalar extract each part but least-significant-byte
3948 for (offset = 0, regnum = MIPS_V0_REGNUM;
3949 offset < TYPE_LENGTH (type);
3950 offset += MIPS64_REGSIZE, regnum++)
3952 int xfer = MIPS64_REGSIZE;
3953 if (offset + xfer > TYPE_LENGTH (type))
3954 xfer = TYPE_LENGTH (type) - offset;
3956 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3957 offset, xfer, regnum);
3958 mips_xfer_register (regcache, gdbarch_num_regs (gdbarch) + regnum,
3959 xfer, gdbarch_byte_order (gdbarch),
3960 readbuf, writebuf, offset);
3962 return RETURN_VALUE_REGISTER_CONVENTION;
3966 /* Floating point register management.
3968 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3969 64bit operations, these early MIPS cpus treat fp register pairs
3970 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3971 registers and offer a compatibility mode that emulates the MIPS2 fp
3972 model. When operating in MIPS2 fp compat mode, later cpu's split
3973 double precision floats into two 32-bit chunks and store them in
3974 consecutive fp regs. To display 64-bit floats stored in this
3975 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3976 Throw in user-configurable endianness and you have a real mess.
3978 The way this works is:
3979 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3980 double-precision value will be split across two logical registers.
3981 The lower-numbered logical register will hold the low-order bits,
3982 regardless of the processor's endianness.
3983 - If we are on a 64-bit processor, and we are looking for a
3984 single-precision value, it will be in the low ordered bits
3985 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3986 save slot in memory.
3987 - If we are in 64-bit mode, everything is straightforward.
3989 Note that this code only deals with "live" registers at the top of the
3990 stack. We will attempt to deal with saved registers later, when
3991 the raw/cooked register interface is in place. (We need a general
3992 interface that can deal with dynamic saved register sizes -- fp
3993 regs could be 32 bits wide in one frame and 64 on the frame above
3996 static struct type *
3997 mips_float_register_type (void)
3999 return builtin_type_ieee_single;
4002 static struct type *
4003 mips_double_register_type (void)
4005 return builtin_type_ieee_double;
4008 /* Copy a 32-bit single-precision value from the current frame
4009 into rare_buffer. */
4012 mips_read_fp_register_single (struct frame_info *frame, int regno,
4013 gdb_byte *rare_buffer)
4015 struct gdbarch *gdbarch = get_frame_arch (frame);
4016 int raw_size = register_size (gdbarch, regno);
4017 gdb_byte *raw_buffer = alloca (raw_size);
4019 if (!frame_register_read (frame, regno, raw_buffer))
4020 error (_("can't read register %d (%s)"),
4021 regno, gdbarch_register_name (gdbarch, regno));
4024 /* We have a 64-bit value for this register. Find the low-order
4028 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4033 memcpy (rare_buffer, raw_buffer + offset, 4);
4037 memcpy (rare_buffer, raw_buffer, 4);
4041 /* Copy a 64-bit double-precision value from the current frame into
4042 rare_buffer. This may include getting half of it from the next
4046 mips_read_fp_register_double (struct frame_info *frame, int regno,
4047 gdb_byte *rare_buffer)
4049 struct gdbarch *gdbarch = get_frame_arch (frame);
4050 int raw_size = register_size (gdbarch, regno);
4052 if (raw_size == 8 && !mips2_fp_compat (frame))
4054 /* We have a 64-bit value for this register, and we should use
4056 if (!frame_register_read (frame, regno, rare_buffer))
4057 error (_("can't read register %d (%s)"),
4058 regno, gdbarch_register_name (gdbarch, regno));
4062 int rawnum = regno % gdbarch_num_regs (gdbarch);
4064 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
4065 internal_error (__FILE__, __LINE__,
4066 _("mips_read_fp_register_double: bad access to "
4067 "odd-numbered FP register"));
4069 /* mips_read_fp_register_single will find the correct 32 bits from
4071 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4073 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4074 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4078 mips_read_fp_register_single (frame, regno, rare_buffer);
4079 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4085 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4087 { /* do values for FP (float) regs */
4088 struct gdbarch *gdbarch = get_frame_arch (frame);
4089 gdb_byte *raw_buffer;
4090 double doub, flt1; /* doubles extracted from raw hex data */
4093 raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0));
4095 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
4096 fprintf_filtered (file, "%*s",
4097 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
4100 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
4102 /* 4-byte registers: Print hex and floating. Also print even
4103 numbered registers as doubles. */
4104 mips_read_fp_register_single (frame, regnum, raw_buffer);
4105 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4107 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
4110 fprintf_filtered (file, " flt: ");
4112 fprintf_filtered (file, " <invalid float> ");
4114 fprintf_filtered (file, "%-17.9g", flt1);
4116 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
4118 mips_read_fp_register_double (frame, regnum, raw_buffer);
4119 doub = unpack_double (mips_double_register_type (), raw_buffer,
4122 fprintf_filtered (file, " dbl: ");
4124 fprintf_filtered (file, "<invalid double>");
4126 fprintf_filtered (file, "%-24.17g", doub);
4131 /* Eight byte registers: print each one as hex, float and double. */
4132 mips_read_fp_register_single (frame, regnum, raw_buffer);
4133 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4135 mips_read_fp_register_double (frame, regnum, raw_buffer);
4136 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4139 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
4142 fprintf_filtered (file, " flt: ");
4144 fprintf_filtered (file, "<invalid float>");
4146 fprintf_filtered (file, "%-17.9g", flt1);
4148 fprintf_filtered (file, " dbl: ");
4150 fprintf_filtered (file, "<invalid double>");
4152 fprintf_filtered (file, "%-24.17g", doub);
4157 mips_print_register (struct ui_file *file, struct frame_info *frame,
4160 struct gdbarch *gdbarch = get_frame_arch (frame);
4161 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4164 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4166 mips_print_fp_register (file, frame, regnum);
4170 /* Get the data in raw format. */
4171 if (!frame_register_read (frame, regnum, raw_buffer))
4173 fprintf_filtered (file, "%s: [Invalid]",
4174 gdbarch_register_name (gdbarch, regnum));
4178 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
4180 /* The problem with printing numeric register names (r26, etc.) is that
4181 the user can't use them on input. Probably the best solution is to
4182 fix it so that either the numeric or the funky (a2, etc.) names
4183 are accepted on input. */
4184 if (regnum < MIPS_NUMREGS)
4185 fprintf_filtered (file, "(r%d): ", regnum);
4187 fprintf_filtered (file, ": ");
4189 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4191 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4195 print_scalar_formatted (raw_buffer + offset,
4196 register_type (gdbarch, regnum), 'x', 0,
4200 /* Replacement for generic do_registers_info.
4201 Print regs in pretty columns. */
4204 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4207 fprintf_filtered (file, " ");
4208 mips_print_fp_register (file, frame, regnum);
4209 fprintf_filtered (file, "\n");
4214 /* Print a row's worth of GP (int) registers, with name labels above */
4217 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4220 struct gdbarch *gdbarch = get_frame_arch (frame);
4221 /* do values for GP (int) regs */
4222 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4223 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4227 /* For GP registers, we print a separate row of names above the vals */
4228 for (col = 0, regnum = start_regnum;
4229 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4230 + gdbarch_num_pseudo_regs (gdbarch);
4233 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4234 continue; /* unused register */
4235 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4237 break; /* end the row: reached FP register */
4238 /* Large registers are handled separately. */
4239 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4242 break; /* End the row before this register. */
4244 /* Print this register on a row by itself. */
4245 mips_print_register (file, frame, regnum);
4246 fprintf_filtered (file, "\n");
4250 fprintf_filtered (file, " ");
4251 fprintf_filtered (file,
4252 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
4253 gdbarch_register_name (gdbarch, regnum));
4260 /* print the R0 to R31 names */
4261 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
4262 fprintf_filtered (file, "\n R%-4d",
4263 start_regnum % gdbarch_num_regs (gdbarch));
4265 fprintf_filtered (file, "\n ");
4267 /* now print the values in hex, 4 or 8 to the row */
4268 for (col = 0, regnum = start_regnum;
4269 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4270 + gdbarch_num_pseudo_regs (gdbarch);
4273 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4274 continue; /* unused register */
4275 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4277 break; /* end row: reached FP register */
4278 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4279 break; /* End row: large register. */
4281 /* OK: get the data in raw format. */
4282 if (!frame_register_read (frame, regnum, raw_buffer))
4283 error (_("can't read register %d (%s)"),
4284 regnum, gdbarch_register_name (gdbarch, regnum));
4285 /* pad small registers */
4287 byte < (mips_abi_regsize (gdbarch)
4288 - register_size (gdbarch, regnum)); byte++)
4289 printf_filtered (" ");
4290 /* Now print the register value in hex, endian order. */
4291 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4293 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4294 byte < register_size (gdbarch, regnum); byte++)
4295 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4297 for (byte = register_size (gdbarch, regnum) - 1;
4299 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4300 fprintf_filtered (file, " ");
4303 if (col > 0) /* ie. if we actually printed anything... */
4304 fprintf_filtered (file, "\n");
4309 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4312 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4313 struct frame_info *frame, int regnum, int all)
4315 if (regnum != -1) /* do one specified register */
4317 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
4318 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
4319 error (_("Not a valid register for the current processor type"));
4321 mips_print_register (file, frame, regnum);
4322 fprintf_filtered (file, "\n");
4325 /* do all (or most) registers */
4327 regnum = gdbarch_num_regs (gdbarch);
4328 while (regnum < gdbarch_num_regs (gdbarch)
4329 + gdbarch_num_pseudo_regs (gdbarch))
4331 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4334 if (all) /* true for "INFO ALL-REGISTERS" command */
4335 regnum = print_fp_register_row (file, frame, regnum);
4337 regnum += MIPS_NUMREGS; /* skip floating point regs */
4340 regnum = print_gp_register_row (file, frame, regnum);
4345 /* Is this a branch with a delay slot? */
4348 is_delayed (unsigned long insn)
4351 for (i = 0; i < NUMOPCODES; ++i)
4352 if (mips_opcodes[i].pinfo != INSN_MACRO
4353 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4355 return (i < NUMOPCODES
4356 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4357 | INSN_COND_BRANCH_DELAY
4358 | INSN_COND_BRANCH_LIKELY)));
4362 mips_single_step_through_delay (struct gdbarch *gdbarch,
4363 struct frame_info *frame)
4365 CORE_ADDR pc = get_frame_pc (frame);
4366 gdb_byte buf[MIPS_INSN32_SIZE];
4368 /* There is no branch delay slot on MIPS16. */
4369 if (mips_pc_is_mips16 (pc))
4372 if (!breakpoint_here_p (pc + 4))
4375 if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf))
4376 /* If error reading memory, guess that it is not a delayed
4379 return is_delayed (extract_unsigned_integer (buf, sizeof buf));
4382 /* To skip prologues, I use this predicate. Returns either PC itself
4383 if the code at PC does not look like a function prologue; otherwise
4384 returns an address that (if we're lucky) follows the prologue. If
4385 LENIENT, then we must skip everything which is involved in setting
4386 up the frame (it's OK to skip more, just so long as we don't skip
4387 anything which might clobber the registers which are being saved.
4388 We must skip more in the case where part of the prologue is in the
4389 delay slot of a non-prologue instruction). */
4392 mips_skip_prologue (CORE_ADDR pc)
4395 CORE_ADDR func_addr;
4397 /* See if we can determine the end of the prologue via the symbol table.
4398 If so, then return either PC, or the PC after the prologue, whichever
4400 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
4402 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
4403 if (post_prologue_pc != 0)
4404 return max (pc, post_prologue_pc);
4407 /* Can't determine prologue from the symbol table, need to examine
4410 /* Find an upper limit on the function prologue using the debug
4411 information. If the debug information could not be used to provide
4412 that bound, then use an arbitrary large number as the upper bound. */
4413 limit_pc = skip_prologue_using_sal (pc);
4415 limit_pc = pc + 100; /* Magic. */
4417 if (mips_pc_is_mips16 (pc))
4418 return mips16_scan_prologue (pc, limit_pc, NULL, NULL);
4420 return mips32_scan_prologue (pc, limit_pc, NULL, NULL);
4423 /* Check whether the PC is in a function epilogue (32-bit version).
4424 This is a helper function for mips_in_function_epilogue_p. */
4426 mips32_in_function_epilogue_p (CORE_ADDR pc)
4428 CORE_ADDR func_addr = 0, func_end = 0;
4430 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4432 /* The MIPS epilogue is max. 12 bytes long. */
4433 CORE_ADDR addr = func_end - 12;
4435 if (addr < func_addr + 4)
4436 addr = func_addr + 4;
4440 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
4442 unsigned long high_word;
4445 inst = mips_fetch_instruction (pc);
4446 high_word = (inst >> 16) & 0xffff;
4448 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
4449 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
4450 && inst != 0x03e00008 /* jr $ra */
4451 && inst != 0x00000000) /* nop */
4461 /* Check whether the PC is in a function epilogue (16-bit version).
4462 This is a helper function for mips_in_function_epilogue_p. */
4464 mips16_in_function_epilogue_p (CORE_ADDR pc)
4466 CORE_ADDR func_addr = 0, func_end = 0;
4468 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4470 /* The MIPS epilogue is max. 12 bytes long. */
4471 CORE_ADDR addr = func_end - 12;
4473 if (addr < func_addr + 4)
4474 addr = func_addr + 4;
4478 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
4480 unsigned short inst;
4482 inst = mips_fetch_instruction (pc);
4484 if ((inst & 0xf800) == 0xf000) /* extend */
4487 if (inst != 0x6300 /* addiu $sp,offset */
4488 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
4489 && inst != 0xe820 /* jr $ra */
4490 && inst != 0xe8a0 /* jrc $ra */
4491 && inst != 0x6500) /* nop */
4501 /* The epilogue is defined here as the area at the end of a function,
4502 after an instruction which destroys the function's stack frame. */
4504 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4506 if (mips_pc_is_mips16 (pc))
4507 return mips16_in_function_epilogue_p (pc);
4509 return mips32_in_function_epilogue_p (pc);
4512 /* Root of all "set mips "/"show mips " commands. This will eventually be
4513 used for all MIPS-specific commands. */
4516 show_mips_command (char *args, int from_tty)
4518 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4522 set_mips_command (char *args, int from_tty)
4525 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4526 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4529 /* Commands to show/set the MIPS FPU type. */
4532 show_mipsfpu_command (char *args, int from_tty)
4535 switch (MIPS_FPU_TYPE)
4537 case MIPS_FPU_SINGLE:
4538 fpu = "single-precision";
4540 case MIPS_FPU_DOUBLE:
4541 fpu = "double-precision";
4544 fpu = "absent (none)";
4547 internal_error (__FILE__, __LINE__, _("bad switch"));
4549 if (mips_fpu_type_auto)
4551 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4555 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4560 set_mipsfpu_command (char *args, int from_tty)
4563 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4564 show_mipsfpu_command (args, from_tty);
4568 set_mipsfpu_single_command (char *args, int from_tty)
4570 struct gdbarch_info info;
4571 gdbarch_info_init (&info);
4572 mips_fpu_type = MIPS_FPU_SINGLE;
4573 mips_fpu_type_auto = 0;
4574 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4575 instead of relying on globals. Doing that would let generic code
4576 handle the search for this specific architecture. */
4577 if (!gdbarch_update_p (info))
4578 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4582 set_mipsfpu_double_command (char *args, int from_tty)
4584 struct gdbarch_info info;
4585 gdbarch_info_init (&info);
4586 mips_fpu_type = MIPS_FPU_DOUBLE;
4587 mips_fpu_type_auto = 0;
4588 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4589 instead of relying on globals. Doing that would let generic code
4590 handle the search for this specific architecture. */
4591 if (!gdbarch_update_p (info))
4592 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4596 set_mipsfpu_none_command (char *args, int from_tty)
4598 struct gdbarch_info info;
4599 gdbarch_info_init (&info);
4600 mips_fpu_type = MIPS_FPU_NONE;
4601 mips_fpu_type_auto = 0;
4602 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4603 instead of relying on globals. Doing that would let generic code
4604 handle the search for this specific architecture. */
4605 if (!gdbarch_update_p (info))
4606 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4610 set_mipsfpu_auto_command (char *args, int from_tty)
4612 mips_fpu_type_auto = 1;
4615 /* Attempt to identify the particular processor model by reading the
4616 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4617 the relevant processor still exists (it dates back to '94) and
4618 secondly this is not the way to do this. The processor type should
4619 be set by forcing an architecture change. */
4622 deprecated_mips_set_processor_regs_hack (void)
4624 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4627 regcache_cooked_read_unsigned (get_current_regcache (),
4628 MIPS_PRID_REGNUM, &prid);
4629 if ((prid & ~0xf) == 0x700)
4630 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4633 /* Just like reinit_frame_cache, but with the right arguments to be
4634 callable as an sfunc. */
4637 reinit_frame_cache_sfunc (char *args, int from_tty,
4638 struct cmd_list_element *c)
4640 reinit_frame_cache ();
4644 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4646 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4648 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4649 disassembler needs to be able to locally determine the ISA, and
4650 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4652 if (mips_pc_is_mips16 (memaddr))
4653 info->mach = bfd_mach_mips16;
4655 /* Round down the instruction address to the appropriate boundary. */
4656 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4658 /* Set the disassembler options. */
4659 if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64)
4661 /* Set up the disassembler info, so that we get the right
4662 register names from libopcodes. */
4663 if (tdep->mips_abi == MIPS_ABI_N32)
4664 info->disassembler_options = "gpr-names=n32";
4666 info->disassembler_options = "gpr-names=64";
4667 info->flavour = bfd_target_elf_flavour;
4670 /* This string is not recognized explicitly by the disassembler,
4671 but it tells the disassembler to not try to guess the ABI from
4672 the bfd elf headers, such that, if the user overrides the ABI
4673 of a program linked as NewABI, the disassembly will follow the
4674 register naming conventions specified by the user. */
4675 info->disassembler_options = "gpr-names=32";
4677 /* Call the appropriate disassembler based on the target endian-ness. */
4678 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
4679 return print_insn_big_mips (memaddr, info);
4681 return print_insn_little_mips (memaddr, info);
4684 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4685 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4686 It returns a pointer to a string of bytes that encode a breakpoint
4687 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4688 necessary) to point to the actual memory location where the breakpoint
4689 should be inserted. */
4691 static const gdb_byte *
4692 mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
4694 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
4696 if (mips_pc_is_mips16 (*pcptr))
4698 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
4699 *pcptr = unmake_mips16_addr (*pcptr);
4700 *lenptr = sizeof (mips16_big_breakpoint);
4701 return mips16_big_breakpoint;
4705 /* The IDT board uses an unusual breakpoint value, and
4706 sometimes gets confused when it sees the usual MIPS
4707 breakpoint instruction. */
4708 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
4709 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
4710 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
4712 *lenptr = sizeof (big_breakpoint);
4714 if (strcmp (target_shortname, "mips") == 0)
4715 return idt_big_breakpoint;
4716 else if (strcmp (target_shortname, "ddb") == 0
4717 || strcmp (target_shortname, "pmon") == 0
4718 || strcmp (target_shortname, "lsi") == 0)
4719 return pmon_big_breakpoint;
4721 return big_breakpoint;
4726 if (mips_pc_is_mips16 (*pcptr))
4728 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
4729 *pcptr = unmake_mips16_addr (*pcptr);
4730 *lenptr = sizeof (mips16_little_breakpoint);
4731 return mips16_little_breakpoint;
4735 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
4736 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
4737 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
4739 *lenptr = sizeof (little_breakpoint);
4741 if (strcmp (target_shortname, "mips") == 0)
4742 return idt_little_breakpoint;
4743 else if (strcmp (target_shortname, "ddb") == 0
4744 || strcmp (target_shortname, "pmon") == 0
4745 || strcmp (target_shortname, "lsi") == 0)
4746 return pmon_little_breakpoint;
4748 return little_breakpoint;
4753 /* If PC is in a mips16 call or return stub, return the address of the target
4754 PC, which is either the callee or the caller. There are several
4755 cases which must be handled:
4757 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4758 target PC is in $31 ($ra).
4759 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4760 and the target PC is in $2.
4761 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4762 before the jal instruction, this is effectively a call stub
4763 and the the target PC is in $2. Otherwise this is effectively
4764 a return stub and the target PC is in $18.
4766 See the source code for the stubs in gcc/config/mips/mips16.S for
4770 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
4773 CORE_ADDR start_addr;
4775 /* Find the starting address and name of the function containing the PC. */
4776 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
4779 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4780 target PC is in $31 ($ra). */
4781 if (strcmp (name, "__mips16_ret_sf") == 0
4782 || strcmp (name, "__mips16_ret_df") == 0)
4783 return get_frame_register_signed (frame, MIPS_RA_REGNUM);
4785 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
4787 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4788 and the target PC is in $2. */
4789 if (name[19] >= '0' && name[19] <= '9')
4790 return get_frame_register_signed (frame, 2);
4792 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4793 before the jal instruction, this is effectively a call stub
4794 and the the target PC is in $2. Otherwise this is effectively
4795 a return stub and the target PC is in $18. */
4796 else if (name[19] == 's' || name[19] == 'd')
4798 if (pc == start_addr)
4800 /* Check if the target of the stub is a compiler-generated
4801 stub. Such a stub for a function bar might have a name
4802 like __fn_stub_bar, and might look like this:
4807 la $1,bar (becomes a lui/addiu pair)
4809 So scan down to the lui/addi and extract the target
4810 address from those two instructions. */
4812 CORE_ADDR target_pc = get_frame_register_signed (frame, 2);
4816 /* See if the name of the target function is __fn_stub_*. */
4817 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
4820 if (strncmp (name, "__fn_stub_", 10) != 0
4821 && strcmp (name, "etext") != 0
4822 && strcmp (name, "_etext") != 0)
4825 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4826 The limit on the search is arbitrarily set to 20
4827 instructions. FIXME. */
4828 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE)
4830 inst = mips_fetch_instruction (target_pc);
4831 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
4832 pc = (inst << 16) & 0xffff0000; /* high word */
4833 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
4834 return pc | (inst & 0xffff); /* low word */
4837 /* Couldn't find the lui/addui pair, so return stub address. */
4841 /* This is the 'return' part of a call stub. The return
4842 address is in $r18. */
4843 return get_frame_register_signed (frame, 18);
4846 return 0; /* not a stub */
4849 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4850 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4853 mips_stab_reg_to_regnum (int num)
4856 if (num >= 0 && num < 32)
4858 else if (num >= 38 && num < 70)
4859 regnum = num + mips_regnum (current_gdbarch)->fp0 - 38;
4861 regnum = mips_regnum (current_gdbarch)->hi;
4863 regnum = mips_regnum (current_gdbarch)->lo;
4865 /* This will hopefully (eventually) provoke a warning. Should
4866 we be calling complaint() here? */
4867 return gdbarch_num_regs (current_gdbarch)
4868 + gdbarch_num_pseudo_regs (current_gdbarch);
4869 return gdbarch_num_regs (current_gdbarch) + regnum;
4873 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4874 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4877 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
4880 if (num >= 0 && num < 32)
4882 else if (num >= 32 && num < 64)
4883 regnum = num + mips_regnum (current_gdbarch)->fp0 - 32;
4885 regnum = mips_regnum (current_gdbarch)->hi;
4887 regnum = mips_regnum (current_gdbarch)->lo;
4889 /* This will hopefully (eventually) provoke a warning. Should we
4890 be calling complaint() here? */
4891 return gdbarch_num_regs (current_gdbarch)
4892 + gdbarch_num_pseudo_regs (current_gdbarch);
4893 return gdbarch_num_regs (current_gdbarch) + regnum;
4897 mips_register_sim_regno (int regnum)
4899 /* Only makes sense to supply raw registers. */
4900 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch));
4901 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4902 decide if it is valid. Should instead define a standard sim/gdb
4903 register numbering scheme. */
4904 if (gdbarch_register_name (current_gdbarch,
4906 (current_gdbarch) + regnum) != NULL
4907 && gdbarch_register_name (current_gdbarch,
4909 (current_gdbarch) + regnum)[0] != '\0')
4912 return LEGACY_SIM_REGNO_IGNORE;
4916 /* Convert an integer into an address. Extracting the value signed
4917 guarantees a correctly sign extended address. */
4920 mips_integer_to_address (struct gdbarch *gdbarch,
4921 struct type *type, const gdb_byte *buf)
4923 return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type));
4926 /* Dummy virtual frame pointer method. This is no more or less accurate
4927 than most other architectures; we just need to be explicit about it,
4928 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
4929 an assertion failure. */
4932 mips_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset)
4934 *reg = MIPS_SP_REGNUM;
4939 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
4941 enum mips_abi *abip = (enum mips_abi *) obj;
4942 const char *name = bfd_get_section_name (abfd, sect);
4944 if (*abip != MIPS_ABI_UNKNOWN)
4947 if (strncmp (name, ".mdebug.", 8) != 0)
4950 if (strcmp (name, ".mdebug.abi32") == 0)
4951 *abip = MIPS_ABI_O32;
4952 else if (strcmp (name, ".mdebug.abiN32") == 0)
4953 *abip = MIPS_ABI_N32;
4954 else if (strcmp (name, ".mdebug.abi64") == 0)
4955 *abip = MIPS_ABI_N64;
4956 else if (strcmp (name, ".mdebug.abiO64") == 0)
4957 *abip = MIPS_ABI_O64;
4958 else if (strcmp (name, ".mdebug.eabi32") == 0)
4959 *abip = MIPS_ABI_EABI32;
4960 else if (strcmp (name, ".mdebug.eabi64") == 0)
4961 *abip = MIPS_ABI_EABI64;
4963 warning (_("unsupported ABI %s."), name + 8);
4967 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
4969 int *lbp = (int *) obj;
4970 const char *name = bfd_get_section_name (abfd, sect);
4972 if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
4974 else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
4976 else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
4977 warning (_("unrecognized .gcc_compiled_longXX"));
4980 static enum mips_abi
4981 global_mips_abi (void)
4985 for (i = 0; mips_abi_strings[i] != NULL; i++)
4986 if (mips_abi_strings[i] == mips_abi_string)
4987 return (enum mips_abi) i;
4989 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
4993 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
4995 /* If the size matches the set of 32-bit or 64-bit integer registers,
4996 assume that's what we've got. */
4997 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
4998 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
5000 /* If the size matches the full set of registers GDB traditionally
5001 knows about, including floating point, for either 32-bit or
5002 64-bit, assume that's what we've got. */
5003 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
5004 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
5006 /* Otherwise we don't have a useful guess. */
5009 static struct value *
5010 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
5012 const int *reg_p = baton;
5013 return value_of_register (*reg_p, frame);
5016 static struct gdbarch *
5017 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5019 struct gdbarch *gdbarch;
5020 struct gdbarch_tdep *tdep;
5022 enum mips_abi mips_abi, found_abi, wanted_abi;
5024 enum mips_fpu_type fpu_type;
5025 struct tdesc_arch_data *tdesc_data = NULL;
5026 int elf_fpu_type = 0;
5028 /* Check any target description for validity. */
5029 if (tdesc_has_registers (info.target_desc))
5031 static const char *const mips_gprs[] = {
5032 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5033 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5034 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5035 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5037 static const char *const mips_fprs[] = {
5038 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5039 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5040 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5041 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5044 const struct tdesc_feature *feature;
5047 feature = tdesc_find_feature (info.target_desc,
5048 "org.gnu.gdb.mips.cpu");
5049 if (feature == NULL)
5052 tdesc_data = tdesc_data_alloc ();
5055 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
5056 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
5060 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5061 MIPS_EMBED_LO_REGNUM, "lo");
5062 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5063 MIPS_EMBED_HI_REGNUM, "hi");
5064 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5065 MIPS_EMBED_PC_REGNUM, "pc");
5069 tdesc_data_cleanup (tdesc_data);
5073 feature = tdesc_find_feature (info.target_desc,
5074 "org.gnu.gdb.mips.cp0");
5075 if (feature == NULL)
5077 tdesc_data_cleanup (tdesc_data);
5082 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5083 MIPS_EMBED_BADVADDR_REGNUM,
5085 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5086 MIPS_PS_REGNUM, "status");
5087 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5088 MIPS_EMBED_CAUSE_REGNUM, "cause");
5092 tdesc_data_cleanup (tdesc_data);
5096 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5097 backend is not prepared for that, though. */
5098 feature = tdesc_find_feature (info.target_desc,
5099 "org.gnu.gdb.mips.fpu");
5100 if (feature == NULL)
5102 tdesc_data_cleanup (tdesc_data);
5107 for (i = 0; i < 32; i++)
5108 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5109 i + MIPS_EMBED_FP0_REGNUM,
5112 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5113 MIPS_EMBED_FP0_REGNUM + 32, "fcsr");
5114 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5115 MIPS_EMBED_FP0_REGNUM + 33, "fir");
5119 tdesc_data_cleanup (tdesc_data);
5123 /* It would be nice to detect an attempt to use a 64-bit ABI
5124 when only 32-bit registers are provided. */
5127 /* First of all, extract the elf_flags, if available. */
5128 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5129 elf_flags = elf_elfheader (info.abfd)->e_flags;
5130 else if (arches != NULL)
5131 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5135 fprintf_unfiltered (gdb_stdlog,
5136 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5138 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5139 switch ((elf_flags & EF_MIPS_ABI))
5141 case E_MIPS_ABI_O32:
5142 found_abi = MIPS_ABI_O32;
5144 case E_MIPS_ABI_O64:
5145 found_abi = MIPS_ABI_O64;
5147 case E_MIPS_ABI_EABI32:
5148 found_abi = MIPS_ABI_EABI32;
5150 case E_MIPS_ABI_EABI64:
5151 found_abi = MIPS_ABI_EABI64;
5154 if ((elf_flags & EF_MIPS_ABI2))
5155 found_abi = MIPS_ABI_N32;
5157 found_abi = MIPS_ABI_UNKNOWN;
5161 /* GCC creates a pseudo-section whose name describes the ABI. */
5162 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5163 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5165 /* If we have no useful BFD information, use the ABI from the last
5166 MIPS architecture (if there is one). */
5167 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5168 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5170 /* Try the architecture for any hint of the correct ABI. */
5171 if (found_abi == MIPS_ABI_UNKNOWN
5172 && info.bfd_arch_info != NULL
5173 && info.bfd_arch_info->arch == bfd_arch_mips)
5175 switch (info.bfd_arch_info->mach)
5177 case bfd_mach_mips3900:
5178 found_abi = MIPS_ABI_EABI32;
5180 case bfd_mach_mips4100:
5181 case bfd_mach_mips5000:
5182 found_abi = MIPS_ABI_EABI64;
5184 case bfd_mach_mips8000:
5185 case bfd_mach_mips10000:
5186 /* On Irix, ELF64 executables use the N64 ABI. The
5187 pseudo-sections which describe the ABI aren't present
5188 on IRIX. (Even for executables created by gcc.) */
5189 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5190 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5191 found_abi = MIPS_ABI_N64;
5193 found_abi = MIPS_ABI_N32;
5198 /* Default 64-bit objects to N64 instead of O32. */
5199 if (found_abi == MIPS_ABI_UNKNOWN
5200 && info.abfd != NULL
5201 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5202 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5203 found_abi = MIPS_ABI_N64;
5206 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5209 /* What has the user specified from the command line? */
5210 wanted_abi = global_mips_abi ();
5212 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5215 /* Now that we have found what the ABI for this binary would be,
5216 check whether the user is overriding it. */
5217 if (wanted_abi != MIPS_ABI_UNKNOWN)
5218 mips_abi = wanted_abi;
5219 else if (found_abi != MIPS_ABI_UNKNOWN)
5220 mips_abi = found_abi;
5222 mips_abi = MIPS_ABI_O32;
5224 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5227 /* Also used when doing an architecture lookup. */
5229 fprintf_unfiltered (gdb_stdlog,
5230 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5231 mips64_transfers_32bit_regs_p);
5233 /* Determine the MIPS FPU type. */
5236 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5237 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5238 Tag_GNU_MIPS_ABI_FP);
5239 #endif /* HAVE_ELF */
5241 if (!mips_fpu_type_auto)
5242 fpu_type = mips_fpu_type;
5243 else if (elf_fpu_type != 0)
5245 switch (elf_fpu_type)
5248 fpu_type = MIPS_FPU_DOUBLE;
5251 fpu_type = MIPS_FPU_SINGLE;
5255 /* Soft float or unknown. */
5256 fpu_type = MIPS_FPU_NONE;
5260 else if (info.bfd_arch_info != NULL
5261 && info.bfd_arch_info->arch == bfd_arch_mips)
5262 switch (info.bfd_arch_info->mach)
5264 case bfd_mach_mips3900:
5265 case bfd_mach_mips4100:
5266 case bfd_mach_mips4111:
5267 case bfd_mach_mips4120:
5268 fpu_type = MIPS_FPU_NONE;
5270 case bfd_mach_mips4650:
5271 fpu_type = MIPS_FPU_SINGLE;
5274 fpu_type = MIPS_FPU_DOUBLE;
5277 else if (arches != NULL)
5278 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5280 fpu_type = MIPS_FPU_DOUBLE;
5282 fprintf_unfiltered (gdb_stdlog,
5283 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5285 /* Check for blatant incompatibilities. */
5287 /* If we have only 32-bit registers, then we can't debug a 64-bit
5289 if (info.target_desc
5290 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
5291 && mips_abi != MIPS_ABI_EABI32
5292 && mips_abi != MIPS_ABI_O32)
5294 if (tdesc_data != NULL)
5295 tdesc_data_cleanup (tdesc_data);
5299 /* try to find a pre-existing architecture */
5300 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5302 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5304 /* MIPS needs to be pedantic about which ABI the object is
5306 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5308 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5310 /* Need to be pedantic about which register virtual size is
5312 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5313 != mips64_transfers_32bit_regs_p)
5315 /* Be pedantic about which FPU is selected. */
5316 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5319 if (tdesc_data != NULL)
5320 tdesc_data_cleanup (tdesc_data);
5321 return arches->gdbarch;
5324 /* Need a new architecture. Fill in a target specific vector. */
5325 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5326 gdbarch = gdbarch_alloc (&info, tdep);
5327 tdep->elf_flags = elf_flags;
5328 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5329 tdep->found_abi = found_abi;
5330 tdep->mips_abi = mips_abi;
5331 tdep->mips_fpu_type = fpu_type;
5332 tdep->register_size_valid_p = 0;
5333 tdep->register_size = 0;
5335 if (info.target_desc)
5337 /* Some useful properties can be inferred from the target. */
5338 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
5340 tdep->register_size_valid_p = 1;
5341 tdep->register_size = 4;
5343 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
5345 tdep->register_size_valid_p = 1;
5346 tdep->register_size = 8;
5350 /* Initially set everything according to the default ABI/ISA. */
5351 set_gdbarch_short_bit (gdbarch, 16);
5352 set_gdbarch_int_bit (gdbarch, 32);
5353 set_gdbarch_float_bit (gdbarch, 32);
5354 set_gdbarch_double_bit (gdbarch, 64);
5355 set_gdbarch_long_double_bit (gdbarch, 64);
5356 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5357 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5358 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5360 set_gdbarch_elf_make_msymbol_special (gdbarch,
5361 mips_elf_make_msymbol_special);
5363 /* Fill in the OS dependant register numbers and names. */
5365 const char **reg_names;
5366 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
5367 struct mips_regnum);
5368 if (tdesc_has_registers (info.target_desc))
5370 regnum->lo = MIPS_EMBED_LO_REGNUM;
5371 regnum->hi = MIPS_EMBED_HI_REGNUM;
5372 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5373 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5374 regnum->pc = MIPS_EMBED_PC_REGNUM;
5375 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5376 regnum->fp_control_status = 70;
5377 regnum->fp_implementation_revision = 71;
5378 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
5381 else if (info.osabi == GDB_OSABI_IRIX)
5386 regnum->badvaddr = 66;
5389 regnum->fp_control_status = 69;
5390 regnum->fp_implementation_revision = 70;
5392 reg_names = mips_irix_reg_names;
5396 regnum->lo = MIPS_EMBED_LO_REGNUM;
5397 regnum->hi = MIPS_EMBED_HI_REGNUM;
5398 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5399 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5400 regnum->pc = MIPS_EMBED_PC_REGNUM;
5401 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5402 regnum->fp_control_status = 70;
5403 regnum->fp_implementation_revision = 71;
5405 if (info.bfd_arch_info != NULL
5406 && info.bfd_arch_info->mach == bfd_mach_mips3900)
5407 reg_names = mips_tx39_reg_names;
5409 reg_names = mips_generic_reg_names;
5411 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5412 replaced by read_pc? */
5413 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
5414 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
5415 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
5416 set_gdbarch_num_regs (gdbarch, num_regs);
5417 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5418 set_gdbarch_register_name (gdbarch, mips_register_name);
5419 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
5420 tdep->mips_processor_reg_names = reg_names;
5421 tdep->regnum = regnum;
5427 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5428 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
5429 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5430 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5431 tdep->default_mask_address_p = 0;
5432 set_gdbarch_long_bit (gdbarch, 32);
5433 set_gdbarch_ptr_bit (gdbarch, 32);
5434 set_gdbarch_long_long_bit (gdbarch, 64);
5437 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5438 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
5439 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5440 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5441 tdep->default_mask_address_p = 0;
5442 set_gdbarch_long_bit (gdbarch, 32);
5443 set_gdbarch_ptr_bit (gdbarch, 32);
5444 set_gdbarch_long_long_bit (gdbarch, 64);
5446 case MIPS_ABI_EABI32:
5447 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5448 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5449 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5450 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5451 tdep->default_mask_address_p = 0;
5452 set_gdbarch_long_bit (gdbarch, 32);
5453 set_gdbarch_ptr_bit (gdbarch, 32);
5454 set_gdbarch_long_long_bit (gdbarch, 64);
5456 case MIPS_ABI_EABI64:
5457 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5458 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5459 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5460 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5461 tdep->default_mask_address_p = 0;
5462 set_gdbarch_long_bit (gdbarch, 64);
5463 set_gdbarch_ptr_bit (gdbarch, 64);
5464 set_gdbarch_long_long_bit (gdbarch, 64);
5467 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5468 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5469 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5470 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5471 tdep->default_mask_address_p = 0;
5472 set_gdbarch_long_bit (gdbarch, 32);
5473 set_gdbarch_ptr_bit (gdbarch, 32);
5474 set_gdbarch_long_long_bit (gdbarch, 64);
5475 set_gdbarch_long_double_bit (gdbarch, 128);
5476 set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long);
5479 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5480 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5481 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5482 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5483 tdep->default_mask_address_p = 0;
5484 set_gdbarch_long_bit (gdbarch, 64);
5485 set_gdbarch_ptr_bit (gdbarch, 64);
5486 set_gdbarch_long_long_bit (gdbarch, 64);
5487 set_gdbarch_long_double_bit (gdbarch, 128);
5488 set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long);
5491 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5494 /* GCC creates a pseudo-section whose name specifies the size of
5495 longs, since -mlong32 or -mlong64 may be used independent of
5496 other options. How those options affect pointer sizes is ABI and
5497 architecture dependent, so use them to override the default sizes
5498 set by the ABI. This table shows the relationship between ABI,
5499 -mlongXX, and size of pointers:
5501 ABI -mlongXX ptr bits
5502 --- -------- --------
5516 Note that for o32 and eabi32, pointers are always 32 bits
5517 regardless of any -mlongXX option. For all others, pointers and
5518 longs are the same, as set by -mlongXX or set by defaults.
5521 if (info.abfd != NULL)
5525 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
5528 set_gdbarch_long_bit (gdbarch, long_bit);
5532 case MIPS_ABI_EABI32:
5537 case MIPS_ABI_EABI64:
5538 set_gdbarch_ptr_bit (gdbarch, long_bit);
5541 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5546 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5547 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5550 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5551 flag in object files because to do so would make it impossible to
5552 link with libraries compiled without "-gp32". This is
5553 unnecessarily restrictive.
5555 We could solve this problem by adding "-gp32" multilibs to gcc,
5556 but to set this flag before gcc is built with such multilibs will
5557 break too many systems.''
5559 But even more unhelpfully, the default linker output target for
5560 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5561 for 64-bit programs - you need to change the ABI to change this,
5562 and not all gcc targets support that currently. Therefore using
5563 this flag to detect 32-bit mode would do the wrong thing given
5564 the current gcc - it would make GDB treat these 64-bit programs
5565 as 32-bit programs by default. */
5567 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5568 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5570 /* Add/remove bits from an address. The MIPS needs be careful to
5571 ensure that all 32 bit addresses are sign extended to 64 bits. */
5572 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5574 /* Unwind the frame. */
5575 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5576 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
5577 set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id);
5579 /* Map debug register numbers onto internal register numbers. */
5580 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5581 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5582 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5583 set_gdbarch_dwarf_reg_to_regnum (gdbarch,
5584 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5585 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5586 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5587 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5589 /* MIPS version of CALL_DUMMY */
5591 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5592 replaced by a command, and all targets will default to on stack
5593 (regardless of the stack's execute status). */
5594 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5595 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5597 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
5598 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
5599 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
5601 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5602 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5604 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5606 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
5608 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5609 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5610 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5612 set_gdbarch_register_type (gdbarch, mips_register_type);
5614 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5616 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
5618 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5619 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5620 need to all be folded into the target vector. Since they are
5621 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5622 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5624 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
5626 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
5628 set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay);
5630 /* Virtual tables. */
5631 set_gdbarch_vbit_in_delta (gdbarch, 1);
5633 mips_register_g_packet_guesses (gdbarch);
5635 /* Hook in OS ABI-specific overrides, if they have been registered. */
5636 info.tdep_info = (void *) tdesc_data;
5637 gdbarch_init_osabi (info, gdbarch);
5639 /* Unwind the frame. */
5640 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
5641 frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer);
5642 frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer);
5643 frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer);
5644 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
5645 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
5646 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
5647 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
5651 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
5652 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
5654 /* Override the normal target description methods to handle our
5655 dual real and pseudo registers. */
5656 set_gdbarch_register_name (gdbarch, mips_register_name);
5657 set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p);
5659 num_regs = gdbarch_num_regs (gdbarch);
5660 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5661 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
5662 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
5665 /* Add ABI-specific aliases for the registers. */
5666 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
5667 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
5668 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
5669 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
5671 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
5672 user_reg_add (gdbarch, mips_o32_aliases[i].name,
5673 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
5675 /* Add some other standard aliases. */
5676 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
5677 user_reg_add (gdbarch, mips_register_aliases[i].name,
5678 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
5684 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
5686 struct gdbarch_info info;
5688 /* Force the architecture to update, and (if it's a MIPS architecture)
5689 mips_gdbarch_init will take care of the rest. */
5690 gdbarch_info_init (&info);
5691 gdbarch_update_p (info);
5694 /* Print out which MIPS ABI is in use. */
5697 show_mips_abi (struct ui_file *file,
5699 struct cmd_list_element *ignored_cmd,
5700 const char *ignored_value)
5702 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
5705 "The MIPS ABI is unknown because the current architecture "
5709 enum mips_abi global_abi = global_mips_abi ();
5710 enum mips_abi actual_abi = mips_abi (current_gdbarch);
5711 const char *actual_abi_str = mips_abi_strings[actual_abi];
5713 if (global_abi == MIPS_ABI_UNKNOWN)
5716 "The MIPS ABI is set automatically (currently \"%s\").\n",
5718 else if (global_abi == actual_abi)
5721 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5725 /* Probably shouldn't happen... */
5728 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5729 actual_abi_str, mips_abi_strings[global_abi]);
5735 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
5737 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5741 int ef_mips_32bitmode;
5742 /* Determine the ISA. */
5743 switch (tdep->elf_flags & EF_MIPS_ARCH)
5761 /* Determine the size of a pointer. */
5762 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
5763 fprintf_unfiltered (file,
5764 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5766 fprintf_unfiltered (file,
5767 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5769 fprintf_unfiltered (file,
5770 "mips_dump_tdep: ef_mips_arch = %d\n",
5772 fprintf_unfiltered (file,
5773 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5774 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
5775 fprintf_unfiltered (file,
5776 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5777 mips_mask_address_p (tdep),
5778 tdep->default_mask_address_p);
5780 fprintf_unfiltered (file,
5781 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5782 MIPS_DEFAULT_FPU_TYPE,
5783 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
5784 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5785 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5787 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI);
5788 fprintf_unfiltered (file,
5789 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5791 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
5792 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5793 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5797 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
5800 _initialize_mips_tdep (void)
5802 static struct cmd_list_element *mipsfpulist = NULL;
5803 struct cmd_list_element *c;
5805 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
5806 if (MIPS_ABI_LAST + 1
5807 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
5808 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
5810 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
5812 mips_pdr_data = register_objfile_data ();
5814 /* Create feature sets with the appropriate properties. The values
5815 are not important. */
5816 mips_tdesc_gp32 = allocate_target_description ();
5817 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
5819 mips_tdesc_gp64 = allocate_target_description ();
5820 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
5822 /* Add root prefix command for all "set mips"/"show mips" commands */
5823 add_prefix_cmd ("mips", no_class, set_mips_command,
5824 _("Various MIPS specific commands."),
5825 &setmipscmdlist, "set mips ", 0, &setlist);
5827 add_prefix_cmd ("mips", no_class, show_mips_command,
5828 _("Various MIPS specific commands."),
5829 &showmipscmdlist, "show mips ", 0, &showlist);
5831 /* Allow the user to override the ABI. */
5832 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
5833 &mips_abi_string, _("\
5834 Set the MIPS ABI used by this program."), _("\
5835 Show the MIPS ABI used by this program."), _("\
5836 This option can be set to one of:\n\
5837 auto - the default ABI associated with the current binary\n\
5846 &setmipscmdlist, &showmipscmdlist);
5848 /* Let the user turn off floating point and set the fence post for
5849 heuristic_proc_start. */
5851 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
5852 _("Set use of MIPS floating-point coprocessor."),
5853 &mipsfpulist, "set mipsfpu ", 0, &setlist);
5854 add_cmd ("single", class_support, set_mipsfpu_single_command,
5855 _("Select single-precision MIPS floating-point coprocessor."),
5857 add_cmd ("double", class_support, set_mipsfpu_double_command,
5858 _("Select double-precision MIPS floating-point coprocessor."),
5860 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
5861 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
5862 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
5863 add_cmd ("none", class_support, set_mipsfpu_none_command,
5864 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
5865 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
5866 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
5867 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
5868 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
5869 _("Select MIPS floating-point coprocessor automatically."),
5871 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
5872 _("Show current use of MIPS floating-point coprocessor target."),
5875 /* We really would like to have both "0" and "unlimited" work, but
5876 command.c doesn't deal with that. So make it a var_zinteger
5877 because the user can always use "999999" or some such for unlimited. */
5878 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
5879 &heuristic_fence_post, _("\
5880 Set the distance searched for the start of a function."), _("\
5881 Show the distance searched for the start of a function."), _("\
5882 If you are debugging a stripped executable, GDB needs to search through the\n\
5883 program for the start of a function. This command sets the distance of the\n\
5884 search. The only need to set it is when debugging a stripped executable."),
5885 reinit_frame_cache_sfunc,
5886 NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5887 &setlist, &showlist);
5889 /* Allow the user to control whether the upper bits of 64-bit
5890 addresses should be zeroed. */
5891 add_setshow_auto_boolean_cmd ("mask-address", no_class,
5892 &mask_address_var, _("\
5893 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5894 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5895 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5896 allow GDB to determine the correct value."),
5897 NULL, show_mask_address,
5898 &setmipscmdlist, &showmipscmdlist);
5900 /* Allow the user to control the size of 32 bit registers within the
5901 raw remote packet. */
5902 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
5903 &mips64_transfers_32bit_regs_p, _("\
5904 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5906 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5908 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5909 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5910 64 bits for others. Use \"off\" to disable compatibility mode"),
5911 set_mips64_transfers_32bit_regs,
5912 NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5913 &setlist, &showlist);
5915 /* Debug this files internals. */
5916 add_setshow_zinteger_cmd ("mips", class_maintenance,
5918 Set mips debugging."), _("\
5919 Show mips debugging."), _("\
5920 When non-zero, mips specific debugging is enabled."),
5922 NULL, /* FIXME: i18n: Mips debugging is currently %s. */
5923 &setdebuglist, &showdebuglist);