1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE = 4,
57 MIPS_FPU_DOUBLE_REGSIZE = 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string;
76 static const char *mips_abi_strings[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto[] = "auto";
98 static const char size_32[] = "32";
99 static const char size_64[] = "64";
101 static const char *size_enums[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE /* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto = 1;
123 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
125 static int mips_debug = 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi;
135 enum mips_abi found_abi;
136 enum mips_fpu_type mips_fpu_type;
137 int mips_last_arg_regnum;
138 int mips_last_fp_arg_regnum;
139 int mips_default_saved_regsize;
140 int mips_fp_register_double;
141 int mips_default_stack_argsize;
142 int gdb_target_is_mips64;
143 int default_mask_address_p;
145 enum gdb_osabi osabi;
148 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
149 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
151 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
153 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
155 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
159 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
161 static const char *mips_saved_regsize_string = size_auto;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string == size_auto)
169 return MIPS_DEFAULT_SAVED_REGSIZE;
170 else if (mips_saved_regsize_string == size_64)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* XFER a value from the big/little/left end of the register.
177 Depending on the size of the value it might occupy the entire
178 register or just part of it. Make an allowance for this, aligning
179 things accordingly. */
182 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
183 enum bfd_endian endian, bfd_byte *in, const bfd_byte *out,
186 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
188 /* Need to transfer the left or right part of the register, based on
189 the targets byte order. */
193 reg_offset = REGISTER_RAW_SIZE (reg_num) - length;
195 case BFD_ENDIAN_LITTLE:
198 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
202 internal_error (__FILE__, __LINE__, "bad switch");
205 fprintf_unfiltered (gdb_stderr,
206 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
207 reg_num, reg_offset, buf_offset, length);
208 if (mips_debug && out != NULL)
211 fprintf_unfiltered (gdb_stdlog, "out ");
212 for (i = 0; i < length; i++)
213 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
216 regcache_raw_read_part (regcache, reg_num, reg_offset, length, in + buf_offset);
218 regcache_raw_write_part (regcache, reg_num, reg_offset, length, out + buf_offset);
219 if (mips_debug && in != NULL)
222 fprintf_unfiltered (gdb_stdlog, "in ");
223 for (i = 0; i < length; i++)
224 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
227 fprintf_unfiltered (gdb_stdlog, "\n");
230 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
231 compatiblity mode. A return value of 1 means that we have
232 physical 64-bit registers, but should treat them as 32-bit registers. */
235 mips2_fp_compat (void)
237 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
239 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
243 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
244 in all the places we deal with FP registers. PR gdb/413. */
245 /* Otherwise check the FR bit in the status register - it controls
246 the FP compatiblity mode. If it is clear we are in compatibility
248 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
255 /* Indicate that the ABI makes use of double-precision registers
256 provided by the FPU (rather than combining pairs of registers to
257 form double-precision values). Do not use "TARGET_IS_MIPS64" to
258 determine if the ABI is using double-precision registers. See also
260 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
262 /* The amount of space reserved on the stack for registers. This is
263 different to MIPS_SAVED_REGSIZE as it determines the alignment of
264 data allocated after the registers have run out. */
266 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
268 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
270 static const char *mips_stack_argsize_string = size_auto;
273 mips_stack_argsize (void)
275 if (mips_stack_argsize_string == size_auto)
276 return MIPS_DEFAULT_STACK_ARGSIZE;
277 else if (mips_stack_argsize_string == size_64)
279 else /* if (mips_stack_argsize_string == size_32) */
283 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
285 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
287 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
289 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
291 static void mips_print_register (int, int);
293 static mips_extra_func_info_t
294 heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int);
296 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
298 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
300 int mips_set_processor_type (char *);
302 static void mips_show_processor_type_command (char *, int);
304 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
306 static mips_extra_func_info_t
307 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame);
309 static CORE_ADDR after_prologue (CORE_ADDR pc,
310 mips_extra_func_info_t proc_desc);
312 static void mips_read_fp_register_single (int regno, char *rare_buffer);
313 static void mips_read_fp_register_double (int regno, char *rare_buffer);
315 static struct type *mips_float_register_type (void);
316 static struct type *mips_double_register_type (void);
318 /* This value is the model of MIPS in use. It is derived from the value
319 of the PrID register. */
321 char *mips_processor_type;
323 char *tmp_mips_processor_type;
325 /* The list of available "set mips " and "show mips " commands */
327 static struct cmd_list_element *setmipscmdlist = NULL;
328 static struct cmd_list_element *showmipscmdlist = NULL;
330 /* A set of original names, to be used when restoring back to generic
331 registers from a specific set. */
333 char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
334 char **mips_processor_reg_names = mips_generic_reg_names;
337 mips_register_name (int i)
339 return mips_processor_reg_names[i];
342 /* Names of IDT R3041 registers. */
344 char *mips_r3041_reg_names[] = {
345 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
346 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
347 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
348 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
349 "sr", "lo", "hi", "bad", "cause","pc",
350 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
351 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
352 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
353 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
354 "fsr", "fir", "fp", "",
355 "", "", "bus", "ccfg", "", "", "", "",
356 "", "", "port", "cmp", "", "", "epc", "prid",
359 /* Names of IDT R3051 registers. */
361 char *mips_r3051_reg_names[] = {
362 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
363 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
364 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
365 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
366 "sr", "lo", "hi", "bad", "cause","pc",
367 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
368 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
369 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
370 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
371 "fsr", "fir", "fp", "",
372 "inx", "rand", "elo", "", "ctxt", "", "", "",
373 "", "", "ehi", "", "", "", "epc", "prid",
376 /* Names of IDT R3081 registers. */
378 char *mips_r3081_reg_names[] = {
379 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
380 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
381 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
382 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
383 "sr", "lo", "hi", "bad", "cause","pc",
384 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
385 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
386 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
387 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
388 "fsr", "fir", "fp", "",
389 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
390 "", "", "ehi", "", "", "", "epc", "prid",
393 /* Names of LSI 33k registers. */
395 char *mips_lsi33k_reg_names[] = {
396 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
397 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
398 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
399 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
400 "epc", "hi", "lo", "sr", "cause","badvaddr",
401 "dcic", "bpc", "bda", "", "", "", "", "",
402 "", "", "", "", "", "", "", "",
403 "", "", "", "", "", "", "", "",
404 "", "", "", "", "", "", "", "",
406 "", "", "", "", "", "", "", "",
407 "", "", "", "", "", "", "", "",
413 } mips_processor_type_table[] = {
414 { "generic", mips_generic_reg_names },
415 { "r3041", mips_r3041_reg_names },
416 { "r3051", mips_r3051_reg_names },
417 { "r3071", mips_r3081_reg_names },
418 { "r3081", mips_r3081_reg_names },
419 { "lsi33k", mips_lsi33k_reg_names },
427 /* Table to translate MIPS16 register field to actual register number. */
428 static int mips16_to_32_reg[8] =
429 {16, 17, 2, 3, 4, 5, 6, 7};
431 /* Heuristic_proc_start may hunt through the text section for a long
432 time across a 2400 baud serial line. Allows the user to limit this
435 static unsigned int heuristic_fence_post = 0;
437 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
438 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
439 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
440 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
441 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
442 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
443 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
444 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
445 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
446 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
447 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
448 this will corrupt pdr.iline. Fortunately we don't use it. */
449 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
450 #define _PROC_MAGIC_ 0x0F0F0F0F
451 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
452 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
454 struct linked_proc_info
456 struct mips_extra_func_info info;
457 struct linked_proc_info *next;
459 *linked_proc_desc_table = NULL;
462 mips_print_extra_frame_info (struct frame_info *fi)
466 && fi->extra_info->proc_desc
467 && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS)
468 printf_filtered (" frame pointer is at %s+%s\n",
469 REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg),
470 paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
473 /* Number of bytes of storage in the actual machine representation for
474 register N. NOTE: This indirectly defines the register size
475 transfered by the GDB protocol. */
477 static int mips64_transfers_32bit_regs_p = 0;
480 mips_register_raw_size (int reg_nr)
482 if (mips64_transfers_32bit_regs_p)
483 return REGISTER_VIRTUAL_SIZE (reg_nr);
484 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
485 && FP_REGISTER_DOUBLE)
486 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
493 /* Convert between RAW and VIRTUAL registers. The RAW register size
494 defines the remote-gdb packet. */
497 mips_register_convertible (int reg_nr)
499 if (mips64_transfers_32bit_regs_p)
502 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
506 mips_register_convert_to_virtual (int n, struct type *virtual_type,
507 char *raw_buf, char *virt_buf)
509 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
511 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
512 TYPE_LENGTH (virtual_type));
516 TYPE_LENGTH (virtual_type));
520 mips_register_convert_to_raw (struct type *virtual_type, int n,
521 char *virt_buf, char *raw_buf)
523 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
524 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
525 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
527 TYPE_LENGTH (virtual_type));
531 TYPE_LENGTH (virtual_type));
535 mips_register_convert_to_type (int regnum, struct type *type, char *buffer)
537 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
538 && REGISTER_RAW_SIZE (regnum) == 4
539 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
540 && TYPE_CODE(type) == TYPE_CODE_FLT
541 && TYPE_LENGTH(type) == 8)
544 memcpy (temp, ((char *)(buffer))+4, 4);
545 memcpy (((char *)(buffer))+4, (buffer), 4);
546 memcpy (((char *)(buffer)), temp, 4);
551 mips_register_convert_from_type (int regnum, struct type *type, char *buffer)
553 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
554 && REGISTER_RAW_SIZE (regnum) == 4
555 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
556 && TYPE_CODE(type) == TYPE_CODE_FLT
557 && TYPE_LENGTH(type) == 8)
560 memcpy (temp, ((char *)(buffer))+4, 4);
561 memcpy (((char *)(buffer))+4, (buffer), 4);
562 memcpy (((char *)(buffer)), temp, 4);
566 /* Return the GDB type object for the "standard" data type
567 of data in register REG.
569 Note: kevinb/2002-08-01: The definition below should faithfully
570 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
571 definitions found in config/mips/tm-*.h. I'm concerned about
572 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
573 though. In some cases FP_REGNUM is in this range, and I doubt
574 that this code is correct for the 64-bit case. */
577 mips_register_virtual_type (int reg)
579 if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32)
581 /* Floating point registers... */
582 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
583 return builtin_type_ieee_double_big;
585 return builtin_type_ieee_double_little;
587 else if (reg == PS_REGNUM /* CR */)
588 return builtin_type_uint32;
589 else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM)
590 return builtin_type_uint32;
593 /* Everything else...
594 Return type appropriate for width of register. */
595 if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64))
596 return builtin_type_uint64;
598 return builtin_type_uint32;
602 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
607 return ADDR_BITS_REMOVE (read_register (SP_REGNUM));
610 /* Should the upper word of 64-bit addresses be zeroed? */
611 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
614 mips_mask_address_p (void)
616 switch (mask_address_var)
618 case AUTO_BOOLEAN_TRUE:
620 case AUTO_BOOLEAN_FALSE:
623 case AUTO_BOOLEAN_AUTO:
624 return MIPS_DEFAULT_MASK_ADDRESS_P;
626 internal_error (__FILE__, __LINE__,
627 "mips_mask_address_p: bad switch");
633 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
635 switch (mask_address_var)
637 case AUTO_BOOLEAN_TRUE:
638 printf_filtered ("The 32 bit mips address mask is enabled\n");
640 case AUTO_BOOLEAN_FALSE:
641 printf_filtered ("The 32 bit mips address mask is disabled\n");
643 case AUTO_BOOLEAN_AUTO:
644 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
645 mips_mask_address_p () ? "enabled" : "disabled");
648 internal_error (__FILE__, __LINE__,
649 "show_mask_address: bad switch");
654 /* Should call_function allocate stack space for a struct return? */
657 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
659 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
663 mips_n32n64_use_struct_convention (int gcc_p, struct type *type)
665 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
669 mips_o32_use_struct_convention (int gcc_p, struct type *type)
671 return 1; /* Structures are returned by ref in extra arg0. */
674 /* Should call_function pass struct by reference?
675 For each architecture, structs are passed either by
676 value or by reference, depending on their size. */
679 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
681 enum type_code typecode = TYPE_CODE (check_typedef (type));
682 int len = TYPE_LENGTH (check_typedef (type));
684 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
685 return (len > MIPS_SAVED_REGSIZE);
691 mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type)
693 return 0; /* Assumption: N32/N64 never passes struct by ref. */
697 mips_o32_reg_struct_has_addr (int gcc_p, struct type *type)
699 return 0; /* Assumption: O32/O64 never passes struct by ref. */
702 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
705 pc_is_mips16 (bfd_vma memaddr)
707 struct minimal_symbol *sym;
709 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
710 if (IS_MIPS16_ADDR (memaddr))
713 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
714 the high bit of the info field. Use this to decide if the function is
715 MIPS16 or normal MIPS. */
716 sym = lookup_minimal_symbol_by_pc (memaddr);
718 return MSYMBOL_IS_SPECIAL (sym);
723 /* ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
724 i.e. refers to a 16-bit function, and sets a "special" bit in a
725 minimal symbol to mark it as a 16-bit function. */
728 mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
730 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16)
732 MSYMBOL_INFO (msym) = (char *)
733 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
734 SYMBOL_VALUE_ADDRESS (msym) |= 1;
738 /* MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol. */
741 mips_msymbol_is_special (struct minimal_symbol *msym)
743 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
746 /* MSYMBOL_SIZE returns the size of the minimal symbol, i.e. the
747 "info" field with the "special" bit masked out. */
750 mips_msymbol_size (struct minimal_symbol *msym)
752 return ((long) MSYMBOL_INFO (msym) & 0x7fffffff);
755 /* MIPS believes that the PC has a sign extended value. Perhaphs the
756 all registers should be sign extended for simplicity? */
759 mips_read_pc (ptid_t ptid)
761 return read_signed_register_pid (PC_REGNUM, ptid);
764 /* This returns the PC of the first inst after the prologue. If we can't
765 find the prologue, then return 0. */
768 after_prologue (CORE_ADDR pc,
769 mips_extra_func_info_t proc_desc)
771 struct symtab_and_line sal;
772 CORE_ADDR func_addr, func_end;
774 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
775 to read the stack pointer from the current machine state, because
776 the current machine state has nothing to do with the information
777 we need from the proc_desc; and the process may or may not exist
780 proc_desc = find_proc_desc (pc, NULL, 0);
784 /* If function is frameless, then we need to do it the hard way. I
785 strongly suspect that frameless always means prologueless... */
786 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
787 && PROC_FRAME_OFFSET (proc_desc) == 0)
791 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
792 return 0; /* Unknown */
794 sal = find_pc_line (func_addr, 0);
796 if (sal.end < func_end)
799 /* The line after the prologue is after the end of the function. In this
800 case, tell the caller to find the prologue the hard way. */
805 /* Decode a MIPS32 instruction that saves a register in the stack, and
806 set the appropriate bit in the general register mask or float register mask
807 to indicate which register is saved. This is a helper function
808 for mips_find_saved_regs. */
811 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
812 unsigned long *float_mask)
816 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
817 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
818 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
820 /* It might be possible to use the instruction to
821 find the offset, rather than the code below which
822 is based on things being in a certain order in the
823 frame, but figuring out what the instruction's offset
824 is relative to might be a little tricky. */
825 reg = (inst & 0x001f0000) >> 16;
826 *gen_mask |= (1 << reg);
828 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
829 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
830 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
833 reg = ((inst & 0x001f0000) >> 16);
834 *float_mask |= (1 << reg);
838 /* Decode a MIPS16 instruction that saves a register in the stack, and
839 set the appropriate bit in the general register or float register mask
840 to indicate which register is saved. This is a helper function
841 for mips_find_saved_regs. */
844 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
846 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
848 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
849 *gen_mask |= (1 << reg);
851 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
853 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
854 *gen_mask |= (1 << reg);
856 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
857 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
858 *gen_mask |= (1 << RA_REGNUM);
862 /* Fetch and return instruction from the specified location. If the PC
863 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
866 mips_fetch_instruction (CORE_ADDR addr)
868 char buf[MIPS_INSTLEN];
872 if (pc_is_mips16 (addr))
874 instlen = MIPS16_INSTLEN;
875 addr = UNMAKE_MIPS16_ADDR (addr);
878 instlen = MIPS_INSTLEN;
879 status = read_memory_nobpt (addr, buf, instlen);
881 memory_error (status, addr);
882 return extract_unsigned_integer (buf, instlen);
886 /* These the fields of 32 bit mips instructions */
887 #define mips32_op(x) (x >> 26)
888 #define itype_op(x) (x >> 26)
889 #define itype_rs(x) ((x >> 21) & 0x1f)
890 #define itype_rt(x) ((x >> 16) & 0x1f)
891 #define itype_immediate(x) (x & 0xffff)
893 #define jtype_op(x) (x >> 26)
894 #define jtype_target(x) (x & 0x03ffffff)
896 #define rtype_op(x) (x >> 26)
897 #define rtype_rs(x) ((x >> 21) & 0x1f)
898 #define rtype_rt(x) ((x >> 16) & 0x1f)
899 #define rtype_rd(x) ((x >> 11) & 0x1f)
900 #define rtype_shamt(x) ((x >> 6) & 0x1f)
901 #define rtype_funct(x) (x & 0x3f)
904 mips32_relative_offset (unsigned long inst)
907 x = itype_immediate (inst);
908 if (x & 0x8000) /* sign bit set */
910 x |= 0xffff0000; /* sign extension */
916 /* Determine whate to set a single step breakpoint while considering
919 mips32_next_pc (CORE_ADDR pc)
923 inst = mips_fetch_instruction (pc);
924 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
926 if (itype_op (inst) >> 2 == 5)
927 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
929 op = (itype_op (inst) & 0x03);
944 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
945 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
947 int tf = itype_rt (inst) & 0x01;
948 int cnum = itype_rt (inst) >> 2;
949 int fcrcs = read_signed_register (FCRCS_REGNUM);
950 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
952 if (((cond >> cnum) & 0x01) == tf)
953 pc += mips32_relative_offset (inst) + 4;
958 pc += 4; /* Not a branch, next instruction is easy */
961 { /* This gets way messy */
963 /* Further subdivide into SPECIAL, REGIMM and other */
964 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
966 case 0: /* SPECIAL */
967 op = rtype_funct (inst);
972 /* Set PC to that address */
973 pc = read_signed_register (rtype_rs (inst));
979 break; /* end SPECIAL */
982 op = itype_rt (inst); /* branch condition */
987 case 16: /* BLTZAL */
988 case 18: /* BLTZALL */
990 if (read_signed_register (itype_rs (inst)) < 0)
991 pc += mips32_relative_offset (inst) + 4;
993 pc += 8; /* after the delay slot */
997 case 17: /* BGEZAL */
998 case 19: /* BGEZALL */
999 greater_equal_branch:
1000 if (read_signed_register (itype_rs (inst)) >= 0)
1001 pc += mips32_relative_offset (inst) + 4;
1003 pc += 8; /* after the delay slot */
1005 /* All of the other instructions in the REGIMM category */
1010 break; /* end REGIMM */
1015 reg = jtype_target (inst) << 2;
1016 /* Upper four bits get never changed... */
1017 pc = reg + ((pc + 4) & 0xf0000000);
1020 /* FIXME case JALX : */
1023 reg = jtype_target (inst) << 2;
1024 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
1025 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1027 break; /* The new PC will be alternate mode */
1028 case 4: /* BEQ, BEQL */
1030 if (read_signed_register (itype_rs (inst)) ==
1031 read_signed_register (itype_rt (inst)))
1032 pc += mips32_relative_offset (inst) + 4;
1036 case 5: /* BNE, BNEL */
1038 if (read_signed_register (itype_rs (inst)) !=
1039 read_signed_register (itype_rt (inst)))
1040 pc += mips32_relative_offset (inst) + 4;
1044 case 6: /* BLEZ, BLEZL */
1046 if (read_signed_register (itype_rs (inst) <= 0))
1047 pc += mips32_relative_offset (inst) + 4;
1053 greater_branch: /* BGTZ, BGTZL */
1054 if (read_signed_register (itype_rs (inst) > 0))
1055 pc += mips32_relative_offset (inst) + 4;
1062 } /* mips32_next_pc */
1064 /* Decoding the next place to set a breakpoint is irregular for the
1065 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1066 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1067 We dont want to set a single step instruction on the extend instruction
1071 /* Lots of mips16 instruction formats */
1072 /* Predicting jumps requires itype,ritype,i8type
1073 and their extensions extItype,extritype,extI8type
1075 enum mips16_inst_fmts
1077 itype, /* 0 immediate 5,10 */
1078 ritype, /* 1 5,3,8 */
1079 rrtype, /* 2 5,3,3,5 */
1080 rritype, /* 3 5,3,3,5 */
1081 rrrtype, /* 4 5,3,3,3,2 */
1082 rriatype, /* 5 5,3,3,1,4 */
1083 shifttype, /* 6 5,3,3,3,2 */
1084 i8type, /* 7 5,3,8 */
1085 i8movtype, /* 8 5,3,3,5 */
1086 i8mov32rtype, /* 9 5,3,5,3 */
1087 i64type, /* 10 5,3,8 */
1088 ri64type, /* 11 5,3,3,5 */
1089 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1090 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1091 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1092 extRRItype, /* 15 5,5,5,5,3,3,5 */
1093 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1094 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1095 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1096 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1097 extRi64type, /* 20 5,6,5,5,3,3,5 */
1098 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1100 /* I am heaping all the fields of the formats into one structure and
1101 then, only the fields which are involved in instruction extension */
1105 unsigned int regx; /* Function in i8 type */
1110 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1111 for the bits which make up the immediatate extension. */
1114 extended_offset (unsigned int extension)
1117 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1119 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1121 value |= extension & 0x01f; /* extract 4:0 */
1125 /* Only call this function if you know that this is an extendable
1126 instruction, It wont malfunction, but why make excess remote memory references?
1127 If the immediate operands get sign extended or somthing, do it after
1128 the extension is performed.
1130 /* FIXME: Every one of these cases needs to worry about sign extension
1131 when the offset is to be used in relative addressing */
1135 fetch_mips_16 (CORE_ADDR pc)
1138 pc &= 0xfffffffe; /* clear the low order bit */
1139 target_read_memory (pc, buf, 2);
1140 return extract_unsigned_integer (buf, 2);
1144 unpack_mips16 (CORE_ADDR pc,
1145 unsigned int extension,
1147 enum mips16_inst_fmts insn_format,
1148 struct upk_mips16 *upk)
1153 switch (insn_format)
1160 value = extended_offset (extension);
1161 value = value << 11; /* rom for the original value */
1162 value |= inst & 0x7ff; /* eleven bits from instruction */
1166 value = inst & 0x7ff;
1167 /* FIXME : Consider sign extension */
1176 { /* A register identifier and an offset */
1177 /* Most of the fields are the same as I type but the
1178 immediate value is of a different length */
1182 value = extended_offset (extension);
1183 value = value << 8; /* from the original instruction */
1184 value |= inst & 0xff; /* eleven bits from instruction */
1185 regx = (extension >> 8) & 0x07; /* or i8 funct */
1186 if (value & 0x4000) /* test the sign bit , bit 26 */
1188 value &= ~0x3fff; /* remove the sign bit */
1194 value = inst & 0xff; /* 8 bits */
1195 regx = (inst >> 8) & 0x07; /* or i8 funct */
1196 /* FIXME: Do sign extension , this format needs it */
1197 if (value & 0x80) /* THIS CONFUSES ME */
1199 value &= 0xef; /* remove the sign bit */
1209 unsigned long value;
1210 unsigned int nexthalf;
1211 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1212 value = value << 16;
1213 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1221 internal_error (__FILE__, __LINE__,
1224 upk->offset = offset;
1231 add_offset_16 (CORE_ADDR pc, int offset)
1233 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1237 extended_mips16_next_pc (CORE_ADDR pc,
1238 unsigned int extension,
1241 int op = (insn >> 11);
1244 case 2: /* Branch */
1247 struct upk_mips16 upk;
1248 unpack_mips16 (pc, extension, insn, itype, &upk);
1249 offset = upk.offset;
1255 pc += (offset << 1) + 2;
1258 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1260 struct upk_mips16 upk;
1261 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1262 pc = add_offset_16 (pc, upk.offset);
1263 if ((insn >> 10) & 0x01) /* Exchange mode */
1264 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1271 struct upk_mips16 upk;
1273 unpack_mips16 (pc, extension, insn, ritype, &upk);
1274 reg = read_signed_register (upk.regx);
1276 pc += (upk.offset << 1) + 2;
1283 struct upk_mips16 upk;
1285 unpack_mips16 (pc, extension, insn, ritype, &upk);
1286 reg = read_signed_register (upk.regx);
1288 pc += (upk.offset << 1) + 2;
1293 case 12: /* I8 Formats btez btnez */
1295 struct upk_mips16 upk;
1297 unpack_mips16 (pc, extension, insn, i8type, &upk);
1298 /* upk.regx contains the opcode */
1299 reg = read_signed_register (24); /* Test register is 24 */
1300 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1301 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1302 /* pc = add_offset_16(pc,upk.offset) ; */
1303 pc += (upk.offset << 1) + 2;
1308 case 29: /* RR Formats JR, JALR, JALR-RA */
1310 struct upk_mips16 upk;
1311 /* upk.fmt = rrtype; */
1316 upk.regx = (insn >> 8) & 0x07;
1317 upk.regy = (insn >> 5) & 0x07;
1325 break; /* Function return instruction */
1331 break; /* BOGUS Guess */
1333 pc = read_signed_register (reg);
1340 /* This is an instruction extension. Fetch the real instruction
1341 (which follows the extension) and decode things based on
1345 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1358 mips16_next_pc (CORE_ADDR pc)
1360 unsigned int insn = fetch_mips_16 (pc);
1361 return extended_mips16_next_pc (pc, 0, insn);
1364 /* The mips_next_pc function supports single_step when the remote
1365 target monitor or stub is not developed enough to do a single_step.
1366 It works by decoding the current instruction and predicting where a
1367 branch will go. This isnt hard because all the data is available.
1368 The MIPS32 and MIPS16 variants are quite different */
1370 mips_next_pc (CORE_ADDR pc)
1373 return mips16_next_pc (pc);
1375 return mips32_next_pc (pc);
1378 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1381 Note: kevinb/2002-08-09: The only caller of this function is (and
1382 should remain) mips_frame_init_saved_regs(). In fact,
1383 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1384 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1385 functions should really be combined and now that there is only one
1386 caller, it should be straightforward. (Watch out for multiple returns
1390 mips_find_saved_regs (struct frame_info *fci)
1393 CORE_ADDR reg_position;
1394 /* r0 bit means kernel trap */
1396 /* What registers have been saved? Bitmasks. */
1397 unsigned long gen_mask, float_mask;
1398 mips_extra_func_info_t proc_desc;
1401 frame_saved_regs_zalloc (fci);
1403 /* If it is the frame for sigtramp, the saved registers are located
1404 in a sigcontext structure somewhere on the stack.
1405 If the stack layout for sigtramp changes we might have to change these
1406 constants and the companion fixup_sigtramp in mdebugread.c */
1407 #ifndef SIGFRAME_BASE
1408 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1409 above the sigtramp frame. */
1410 #define SIGFRAME_BASE MIPS_REGSIZE
1411 /* FIXME! Are these correct?? */
1412 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1413 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1414 #define SIGFRAME_FPREGSAVE_OFF \
1415 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1417 #ifndef SIGFRAME_REG_SIZE
1418 /* FIXME! Is this correct?? */
1419 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1421 if (fci->signal_handler_caller)
1423 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1425 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
1426 + ireg * SIGFRAME_REG_SIZE;
1427 fci->saved_regs[ireg] = reg_position;
1429 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1431 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
1432 + ireg * SIGFRAME_REG_SIZE;
1433 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1435 fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
1439 proc_desc = fci->extra_info->proc_desc;
1440 if (proc_desc == NULL)
1441 /* I'm not sure how/whether this can happen. Normally when we can't
1442 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1443 and set the saved_regs right away. */
1446 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1447 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1448 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1450 if ( /* In any frame other than the innermost or a frame interrupted by
1451 a signal, we assume that all registers have been saved.
1452 This assumes that all register saves in a function happen before
1453 the first function call. */
1454 (fci->next == NULL || fci->next->signal_handler_caller)
1456 /* In a dummy frame we know exactly where things are saved. */
1457 && !PROC_DESC_IS_DUMMY (proc_desc)
1459 /* Don't bother unless we are inside a function prologue. Outside the
1460 prologue, we know where everything is. */
1462 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
1464 /* Not sure exactly what kernel_trap means, but if it means
1465 the kernel saves the registers without a prologue doing it,
1466 we better not examine the prologue to see whether registers
1467 have been saved yet. */
1470 /* We need to figure out whether the registers that the proc_desc
1471 claims are saved have been saved yet. */
1475 /* Bitmasks; set if we have found a save for the register. */
1476 unsigned long gen_save_found = 0;
1477 unsigned long float_save_found = 0;
1480 /* If the address is odd, assume this is MIPS16 code. */
1481 addr = PROC_LOW_ADDR (proc_desc);
1482 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1484 /* Scan through this function's instructions preceding the current
1485 PC, and look for those that save registers. */
1486 while (addr < fci->pc)
1488 inst = mips_fetch_instruction (addr);
1489 if (pc_is_mips16 (addr))
1490 mips16_decode_reg_save (inst, &gen_save_found);
1492 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1495 gen_mask = gen_save_found;
1496 float_mask = float_save_found;
1499 /* Fill in the offsets for the registers which gen_mask says
1501 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1502 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1503 if (gen_mask & 0x80000000)
1505 fci->saved_regs[ireg] = reg_position;
1506 reg_position -= MIPS_SAVED_REGSIZE;
1509 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1510 of that normally used by gcc. Therefore, we have to fetch the first
1511 instruction of the function, and if it's an entry instruction that
1512 saves $s0 or $s1, correct their saved addresses. */
1513 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1515 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1516 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1519 int sreg_count = (inst >> 6) & 3;
1521 /* Check if the ra register was pushed on the stack. */
1522 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1524 reg_position -= MIPS_SAVED_REGSIZE;
1526 /* Check if the s0 and s1 registers were pushed on the stack. */
1527 for (reg = 16; reg < sreg_count + 16; reg++)
1529 fci->saved_regs[reg] = reg_position;
1530 reg_position -= MIPS_SAVED_REGSIZE;
1535 /* Fill in the offsets for the registers which float_mask says
1537 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
1539 /* Apparently, the freg_offset gives the offset to the first 64 bit
1542 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1543 designates the first saved 64 bit register.
1545 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1546 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1547 FREG_OFFSET, designates the address of the lower register of the
1548 register pair. Adjust the offset so that it designates the upper
1549 register of the pair -- i.e., the address of the first saved 32
1552 if (MIPS_SAVED_REGSIZE == 4)
1553 reg_position += MIPS_SAVED_REGSIZE;
1555 /* Fill in the offsets for the float registers which float_mask says
1557 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1558 if (float_mask & 0x80000000)
1560 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1561 reg_position -= MIPS_SAVED_REGSIZE;
1564 fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM];
1567 /* Set up the 'saved_regs' array. This is a data structure containing
1568 the addresses on the stack where each register has been saved, for
1569 each stack frame. Registers that have not been saved will have
1570 zero here. The stack pointer register is special: rather than the
1571 address where the stack register has been saved, saved_regs[SP_REGNUM]
1572 will have the actual value of the previous frame's stack register. */
1575 mips_frame_init_saved_regs (struct frame_info *frame)
1577 if (frame->saved_regs == NULL)
1579 mips_find_saved_regs (frame);
1581 frame->saved_regs[SP_REGNUM] = frame->frame;
1585 read_next_frame_reg (struct frame_info *fi, int regno)
1587 for (; fi; fi = fi->next)
1589 /* We have to get the saved sp from the sigcontext
1590 if it is a signal handler frame. */
1591 if (regno == SP_REGNUM && !fi->signal_handler_caller)
1595 if (fi->saved_regs == NULL)
1596 FRAME_INIT_SAVED_REGS (fi);
1597 if (fi->saved_regs[regno])
1598 return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE);
1601 return read_signed_register (regno);
1604 /* mips_addr_bits_remove - remove useless address bits */
1607 mips_addr_bits_remove (CORE_ADDR addr)
1609 if (GDB_TARGET_IS_MIPS64)
1611 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1613 /* This hack is a work-around for existing boards using
1614 PMON, the simulator, and any other 64-bit targets that
1615 doesn't have true 64-bit addressing. On these targets,
1616 the upper 32 bits of addresses are ignored by the
1617 hardware. Thus, the PC or SP are likely to have been
1618 sign extended to all 1s by instruction sequences that
1619 load 32-bit addresses. For example, a typical piece of
1620 code that loads an address is this:
1621 lui $r2, <upper 16 bits>
1622 ori $r2, <lower 16 bits>
1623 But the lui sign-extends the value such that the upper 32
1624 bits may be all 1s. The workaround is simply to mask off
1625 these bits. In the future, gcc may be changed to support
1626 true 64-bit addressing, and this masking will have to be
1628 addr &= (CORE_ADDR) 0xffffffff;
1631 else if (mips_mask_address_p ())
1633 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1634 masking off bits, instead, the actual target should be asking
1635 for the address to be converted to a valid pointer. */
1636 /* Even when GDB is configured for some 32-bit targets
1637 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1638 so CORE_ADDR is 64 bits. So we still have to mask off
1639 useless bits from addresses. */
1640 addr &= (CORE_ADDR) 0xffffffff;
1645 /* mips_software_single_step() is called just before we want to resume
1646 the inferior, if we want to single-step it but there is no hardware
1647 or kernel single-step support (MIPS on GNU/Linux for example). We find
1648 the target of the coming instruction and breakpoint it.
1650 single_step is also called just after the inferior stops. If we had
1651 set up a simulated single-step, we undo our damage. */
1654 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1656 static CORE_ADDR next_pc;
1657 typedef char binsn_quantum[BREAKPOINT_MAX];
1658 static binsn_quantum break_mem;
1661 if (insert_breakpoints_p)
1663 pc = read_register (PC_REGNUM);
1664 next_pc = mips_next_pc (pc);
1666 target_insert_breakpoint (next_pc, break_mem);
1669 target_remove_breakpoint (next_pc, break_mem);
1673 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1677 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
1678 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
1679 tmp = mips_skip_stub (pc);
1680 prev->pc = tmp ? tmp : pc;
1685 mips_frame_saved_pc (struct frame_info *frame)
1688 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
1689 /* We have to get the saved pc from the sigcontext
1690 if it is a signal handler frame. */
1691 int pcreg = frame->signal_handler_caller ? PC_REGNUM
1692 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1694 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1695 saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1697 saved_pc = read_next_frame_reg (frame, pcreg);
1699 return ADDR_BITS_REMOVE (saved_pc);
1702 static struct mips_extra_func_info temp_proc_desc;
1703 static CORE_ADDR temp_saved_regs[NUM_REGS];
1705 /* Set a register's saved stack address in temp_saved_regs. If an address
1706 has already been set for this register, do nothing; this way we will
1707 only recognize the first save of a given register in a function prologue.
1708 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1711 set_reg_offset (int regno, CORE_ADDR offset)
1713 if (temp_saved_regs[regno] == 0)
1714 temp_saved_regs[regno] = offset;
1718 /* Test whether the PC points to the return instruction at the
1719 end of a function. */
1722 mips_about_to_return (CORE_ADDR pc)
1724 if (pc_is_mips16 (pc))
1725 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1726 generates a "jr $ra"; other times it generates code to load
1727 the return address from the stack to an accessible register (such
1728 as $a3), then a "jr" using that register. This second case
1729 is almost impossible to distinguish from an indirect jump
1730 used for switch statements, so we don't even try. */
1731 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1733 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1737 /* This fencepost looks highly suspicious to me. Removing it also
1738 seems suspicious as it could affect remote debugging across serial
1742 heuristic_proc_start (CORE_ADDR pc)
1749 pc = ADDR_BITS_REMOVE (pc);
1751 fence = start_pc - heuristic_fence_post;
1755 if (heuristic_fence_post == UINT_MAX
1756 || fence < VM_MIN_ADDRESS)
1757 fence = VM_MIN_ADDRESS;
1759 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1761 /* search back for previous return */
1762 for (start_pc -= instlen;; start_pc -= instlen)
1763 if (start_pc < fence)
1765 /* It's not clear to me why we reach this point when
1766 stop_soon_quietly, but with this test, at least we
1767 don't print out warnings for every child forked (eg, on
1768 decstation). 22apr93 rich@cygnus.com. */
1769 if (!stop_soon_quietly)
1771 static int blurb_printed = 0;
1773 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1778 /* This actually happens frequently in embedded
1779 development, when you first connect to a board
1780 and your stack pointer and pc are nowhere in
1781 particular. This message needs to give people
1782 in that situation enough information to
1783 determine that it's no big deal. */
1784 printf_filtered ("\n\
1785 GDB is unable to find the start of the function at 0x%s\n\
1786 and thus can't determine the size of that function's stack frame.\n\
1787 This means that GDB may be unable to access that stack frame, or\n\
1788 the frames below it.\n\
1789 This problem is most likely caused by an invalid program counter or\n\
1791 However, if you think GDB should simply search farther back\n\
1792 from 0x%s for code which looks like the beginning of a\n\
1793 function, you can increase the range of the search using the `set\n\
1794 heuristic-fence-post' command.\n",
1795 paddr_nz (pc), paddr_nz (pc));
1802 else if (pc_is_mips16 (start_pc))
1804 unsigned short inst;
1806 /* On MIPS16, any one of the following is likely to be the
1807 start of a function:
1811 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1812 inst = mips_fetch_instruction (start_pc);
1813 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1814 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1815 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1816 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1818 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1819 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1824 else if (mips_about_to_return (start_pc))
1826 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1833 /* Fetch the immediate value from a MIPS16 instruction.
1834 If the previous instruction was an EXTEND, use it to extend
1835 the upper bits of the immediate value. This is a helper function
1836 for mips16_heuristic_proc_desc. */
1839 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1840 unsigned short inst, /* current instruction */
1841 int nbits, /* number of bits in imm field */
1842 int scale, /* scale factor to be applied to imm */
1843 int is_signed) /* is the imm field signed? */
1847 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1849 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1850 if (offset & 0x8000) /* check for negative extend */
1851 offset = 0 - (0x10000 - (offset & 0xffff));
1852 return offset | (inst & 0x1f);
1856 int max_imm = 1 << nbits;
1857 int mask = max_imm - 1;
1858 int sign_bit = max_imm >> 1;
1860 offset = inst & mask;
1861 if (is_signed && (offset & sign_bit))
1862 offset = 0 - (max_imm - offset);
1863 return offset * scale;
1868 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1869 stream from start_pc to limit_pc. */
1872 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1873 struct frame_info *next_frame, CORE_ADDR sp)
1876 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1877 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1878 unsigned inst = 0; /* current instruction */
1879 unsigned entry_inst = 0; /* the entry instruction */
1882 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1883 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1885 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1887 /* Save the previous instruction. If it's an EXTEND, we'll extract
1888 the immediate offset extension from it in mips16_get_imm. */
1891 /* Fetch and decode the instruction. */
1892 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1893 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1894 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1896 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1897 if (offset < 0) /* negative stack adjustment? */
1898 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
1900 /* Exit loop if a positive stack adjustment is found, which
1901 usually means that the stack cleanup code in the function
1902 epilogue is reached. */
1905 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1907 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1908 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1909 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1910 set_reg_offset (reg, sp + offset);
1912 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1914 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1915 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1916 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1917 set_reg_offset (reg, sp + offset);
1919 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1921 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1922 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1923 set_reg_offset (RA_REGNUM, sp + offset);
1925 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1927 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1928 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1929 set_reg_offset (RA_REGNUM, sp + offset);
1931 else if (inst == 0x673d) /* move $s1, $sp */
1934 PROC_FRAME_REG (&temp_proc_desc) = 17;
1936 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1938 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1939 frame_addr = sp + offset;
1940 PROC_FRAME_REG (&temp_proc_desc) = 17;
1941 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1943 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1945 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1946 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1947 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1948 set_reg_offset (reg, frame_addr + offset);
1950 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1952 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1953 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1954 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1955 set_reg_offset (reg, frame_addr + offset);
1957 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1958 entry_inst = inst; /* save for later processing */
1959 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1960 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
1963 /* The entry instruction is typically the first instruction in a function,
1964 and it stores registers at offsets relative to the value of the old SP
1965 (before the prologue). But the value of the sp parameter to this
1966 function is the new SP (after the prologue has been executed). So we
1967 can't calculate those offsets until we've seen the entire prologue,
1968 and can calculate what the old SP must have been. */
1969 if (entry_inst != 0)
1971 int areg_count = (entry_inst >> 8) & 7;
1972 int sreg_count = (entry_inst >> 6) & 3;
1974 /* The entry instruction always subtracts 32 from the SP. */
1975 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
1977 /* Now we can calculate what the SP must have been at the
1978 start of the function prologue. */
1979 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
1981 /* Check if a0-a3 were saved in the caller's argument save area. */
1982 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1984 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1985 set_reg_offset (reg, sp + offset);
1986 offset += MIPS_SAVED_REGSIZE;
1989 /* Check if the ra register was pushed on the stack. */
1991 if (entry_inst & 0x20)
1993 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
1994 set_reg_offset (RA_REGNUM, sp + offset);
1995 offset -= MIPS_SAVED_REGSIZE;
1998 /* Check if the s0 and s1 registers were pushed on the stack. */
1999 for (reg = 16; reg < sreg_count + 16; reg++)
2001 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2002 set_reg_offset (reg, sp + offset);
2003 offset -= MIPS_SAVED_REGSIZE;
2009 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2010 struct frame_info *next_frame, CORE_ADDR sp)
2013 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
2015 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2016 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
2017 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2018 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2020 unsigned long inst, high_word, low_word;
2023 /* Fetch the instruction. */
2024 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2026 /* Save some code by pre-extracting some useful fields. */
2027 high_word = (inst >> 16) & 0xffff;
2028 low_word = inst & 0xffff;
2029 reg = high_word & 0x1f;
2031 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2032 || high_word == 0x23bd /* addi $sp,$sp,-i */
2033 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2035 if (low_word & 0x8000) /* negative stack adjustment? */
2036 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
2038 /* Exit loop if a positive stack adjustment is found, which
2039 usually means that the stack cleanup code in the function
2040 epilogue is reached. */
2043 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2045 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2046 set_reg_offset (reg, sp + low_word);
2048 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2050 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2051 but the register size used is only 32 bits. Make the address
2052 for the saved register point to the lower 32 bits. */
2053 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2054 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
2056 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2058 /* Old gcc frame, r30 is virtual frame pointer. */
2059 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2060 frame_addr = sp + low_word;
2061 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2063 unsigned alloca_adjust;
2064 PROC_FRAME_REG (&temp_proc_desc) = 30;
2065 frame_addr = read_next_frame_reg (next_frame, 30);
2066 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2067 if (alloca_adjust > 0)
2069 /* FP > SP + frame_size. This may be because
2070 * of an alloca or somethings similar.
2071 * Fix sp to "pre-alloca" value, and try again.
2073 sp += alloca_adjust;
2078 /* move $30,$sp. With different versions of gas this will be either
2079 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2080 Accept any one of these. */
2081 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2083 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2084 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2086 unsigned alloca_adjust;
2087 PROC_FRAME_REG (&temp_proc_desc) = 30;
2088 frame_addr = read_next_frame_reg (next_frame, 30);
2089 alloca_adjust = (unsigned) (frame_addr - sp);
2090 if (alloca_adjust > 0)
2092 /* FP > SP + frame_size. This may be because
2093 * of an alloca or somethings similar.
2094 * Fix sp to "pre-alloca" value, and try again.
2096 sp += alloca_adjust;
2101 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2103 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2104 set_reg_offset (reg, frame_addr + low_word);
2109 static mips_extra_func_info_t
2110 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2111 struct frame_info *next_frame, int cur_frame)
2116 sp = read_next_frame_reg (next_frame, SP_REGNUM);
2122 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2123 memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2124 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2125 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2126 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2128 if (start_pc + 200 < limit_pc)
2129 limit_pc = start_pc + 200;
2130 if (pc_is_mips16 (start_pc))
2131 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2133 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2134 return &temp_proc_desc;
2137 struct mips_objfile_private
2143 /* Global used to communicate between non_heuristic_proc_desc and
2144 compare_pdr_entries within qsort (). */
2145 static bfd *the_bfd;
2148 compare_pdr_entries (const void *a, const void *b)
2150 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2151 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2155 else if (lhs == rhs)
2161 static mips_extra_func_info_t
2162 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2164 CORE_ADDR startaddr;
2165 mips_extra_func_info_t proc_desc;
2166 struct block *b = block_for_pc (pc);
2168 struct obj_section *sec;
2169 struct mips_objfile_private *priv;
2171 if (PC_IN_CALL_DUMMY (pc, 0, 0))
2174 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2176 *addrptr = startaddr;
2180 sec = find_pc_section (pc);
2183 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2185 /* Search the ".pdr" section generated by GAS. This includes most of
2186 the information normally found in ECOFF PDRs. */
2188 the_bfd = sec->objfile->obfd;
2190 && (the_bfd->format == bfd_object
2191 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2192 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2194 /* Right now GAS only outputs the address as a four-byte sequence.
2195 This means that we should not bother with this method on 64-bit
2196 targets (until that is fixed). */
2198 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2199 sizeof (struct mips_objfile_private));
2201 sec->objfile->obj_private = priv;
2203 else if (priv == NULL)
2207 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2208 sizeof (struct mips_objfile_private));
2210 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2213 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2214 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2216 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2217 priv->contents, 0, priv->size);
2219 /* In general, the .pdr section is sorted. However, in the
2220 presence of multiple code sections (and other corner cases)
2221 it can become unsorted. Sort it so that we can use a faster
2223 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2228 sec->objfile->obj_private = priv;
2232 if (priv->size != 0)
2238 high = priv->size / 32;
2244 mid = (low + high) / 2;
2246 ptr = priv->contents + mid * 32;
2247 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2248 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2249 SECT_OFF_TEXT (sec->objfile));
2250 if (pdr_pc == startaddr)
2252 if (pdr_pc > startaddr)
2257 while (low != high);
2261 struct symbol *sym = find_pc_function (pc);
2263 /* Fill in what we need of the proc_desc. */
2264 proc_desc = (mips_extra_func_info_t)
2265 obstack_alloc (&sec->objfile->psymbol_obstack,
2266 sizeof (struct mips_extra_func_info));
2267 PROC_LOW_ADDR (proc_desc) = startaddr;
2269 /* Only used for dummy frames. */
2270 PROC_HIGH_ADDR (proc_desc) = 0;
2272 PROC_FRAME_OFFSET (proc_desc)
2273 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2274 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2276 PROC_FRAME_ADJUST (proc_desc) = 0;
2277 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2279 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2281 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2283 PROC_FREG_OFFSET (proc_desc)
2284 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2285 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2287 proc_desc->pdr.isym = (long) sym;
2297 if (startaddr > BLOCK_START (b))
2299 /* This is the "pathological" case referred to in a comment in
2300 print_frame_info. It might be better to move this check into
2305 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
2307 /* If we never found a PDR for this function in symbol reading, then
2308 examine prologues to find the information. */
2311 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2312 if (PROC_FRAME_REG (proc_desc) == -1)
2322 static mips_extra_func_info_t
2323 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2325 mips_extra_func_info_t proc_desc;
2326 CORE_ADDR startaddr;
2328 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2332 /* IF this is the topmost frame AND
2333 * (this proc does not have debugging information OR
2334 * the PC is in the procedure prologue)
2335 * THEN create a "heuristic" proc_desc (by analyzing
2336 * the actual code) to replace the "official" proc_desc.
2338 if (next_frame == NULL)
2340 struct symtab_and_line val;
2341 struct symbol *proc_symbol =
2342 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2346 val = find_pc_line (BLOCK_START
2347 (SYMBOL_BLOCK_VALUE (proc_symbol)),
2349 val.pc = val.end ? val.end : pc;
2351 if (!proc_symbol || pc < val.pc)
2353 mips_extra_func_info_t found_heuristic =
2354 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2355 pc, next_frame, cur_frame);
2356 if (found_heuristic)
2357 proc_desc = found_heuristic;
2363 /* Is linked_proc_desc_table really necessary? It only seems to be used
2364 by procedure call dummys. However, the procedures being called ought
2365 to have their own proc_descs, and even if they don't,
2366 heuristic_proc_desc knows how to create them! */
2368 register struct linked_proc_info *link;
2370 for (link = linked_proc_desc_table; link; link = link->next)
2371 if (PROC_LOW_ADDR (&link->info) <= pc
2372 && PROC_HIGH_ADDR (&link->info) > pc)
2376 startaddr = heuristic_proc_start (pc);
2379 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2385 get_frame_pointer (struct frame_info *frame,
2386 mips_extra_func_info_t proc_desc)
2388 return ADDR_BITS_REMOVE (read_next_frame_reg (frame,
2389 PROC_FRAME_REG (proc_desc)) +
2390 PROC_FRAME_OFFSET (proc_desc) -
2391 PROC_FRAME_ADJUST (proc_desc));
2394 mips_extra_func_info_t cached_proc_desc;
2397 mips_frame_chain (struct frame_info *frame)
2399 mips_extra_func_info_t proc_desc;
2401 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
2403 if (saved_pc == 0 || inside_entry_file (saved_pc))
2406 /* Check if the PC is inside a call stub. If it is, fetch the
2407 PC of the caller of that stub. */
2408 if ((tmp = mips_skip_stub (saved_pc)) != 0)
2411 /* Look up the procedure descriptor for this PC. */
2412 proc_desc = find_proc_desc (saved_pc, frame, 1);
2416 cached_proc_desc = proc_desc;
2418 /* If no frame pointer and frame size is zero, we must be at end
2419 of stack (or otherwise hosed). If we don't check frame size,
2420 we loop forever if we see a zero size frame. */
2421 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2422 && PROC_FRAME_OFFSET (proc_desc) == 0
2423 /* The previous frame from a sigtramp frame might be frameless
2424 and have frame size zero. */
2425 && !frame->signal_handler_caller
2426 /* Check if this is a call dummy frame. */
2427 && frame->pc != CALL_DUMMY_ADDRESS ())
2430 return get_frame_pointer (frame, proc_desc);
2434 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2438 /* Use proc_desc calculated in frame_chain */
2439 mips_extra_func_info_t proc_desc =
2440 fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1);
2442 fci->extra_info = (struct frame_extra_info *)
2443 frame_obstack_alloc (sizeof (struct frame_extra_info));
2445 fci->saved_regs = NULL;
2446 fci->extra_info->proc_desc =
2447 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2450 /* Fixup frame-pointer - only needed for top frame */
2451 /* This may not be quite right, if proc has a real frame register.
2452 Get the value of the frame relative sp, procedure might have been
2453 interrupted by a signal at it's very start. */
2454 if (fci->pc == PROC_LOW_ADDR (proc_desc)
2455 && !PROC_DESC_IS_DUMMY (proc_desc))
2456 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
2458 fci->frame = get_frame_pointer (fci->next, proc_desc);
2460 if (proc_desc == &temp_proc_desc)
2464 /* Do not set the saved registers for a sigtramp frame,
2465 mips_find_saved_registers will do that for us.
2466 We can't use fci->signal_handler_caller, it is not yet set. */
2467 find_pc_partial_function (fci->pc, &name,
2468 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2469 if (!PC_IN_SIGTRAMP (fci->pc, name))
2471 frame_saved_regs_zalloc (fci);
2472 memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2473 fci->saved_regs[PC_REGNUM]
2474 = fci->saved_regs[RA_REGNUM];
2475 /* Set value of previous frame's stack pointer. Remember that
2476 saved_regs[SP_REGNUM] is special in that it contains the
2477 value of the stack pointer register. The other saved_regs
2478 values are addresses (in the inferior) at which a given
2479 register's value may be found. */
2480 fci->saved_regs[SP_REGNUM] = fci->frame;
2484 /* hack: if argument regs are saved, guess these contain args */
2485 /* assume we can't tell how many args for now */
2486 fci->extra_info->num_args = -1;
2487 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2489 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2491 fci->extra_info->num_args = regnum - A0_REGNUM + 1;
2498 /* MIPS stack frames are almost impenetrable. When execution stops,
2499 we basically have to look at symbol information for the function
2500 that we stopped in, which tells us *which* register (if any) is
2501 the base of the frame pointer, and what offset from that register
2502 the frame itself is at.
2504 This presents a problem when trying to examine a stack in memory
2505 (that isn't executing at the moment), using the "frame" command. We
2506 don't have a PC, nor do we have any registers except SP.
2508 This routine takes two arguments, SP and PC, and tries to make the
2509 cached frames look as if these two arguments defined a frame on the
2510 cache. This allows the rest of info frame to extract the important
2511 arguments without difficulty. */
2514 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2517 error ("MIPS frame specifications require two arguments: sp and pc");
2519 return create_new_frame (argv[0], argv[1]);
2522 /* According to the current ABI, should the type be passed in a
2523 floating-point register (assuming that there is space)? When there
2524 is no FPU, FP are not even considered as possibile candidates for
2525 FP registers and, consequently this returns false - forces FP
2526 arguments into integer registers. */
2529 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2531 return ((typecode == TYPE_CODE_FLT
2533 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2534 && TYPE_NFIELDS (arg_type) == 1
2535 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2536 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2539 /* On o32, argument passing in GPRs depends on the alignment of the type being
2540 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2543 mips_type_needs_double_align (struct type *type)
2545 enum type_code typecode = TYPE_CODE (type);
2547 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2549 else if (typecode == TYPE_CODE_STRUCT)
2551 if (TYPE_NFIELDS (type) < 1)
2553 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2555 else if (typecode == TYPE_CODE_UNION)
2559 n = TYPE_NFIELDS (type);
2560 for (i = 0; i < n; i++)
2561 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2568 /* Macros to round N up or down to the next A boundary;
2569 A must be a power of two. */
2571 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2572 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2575 mips_eabi_push_arguments (int nargs,
2576 struct value **args,
2579 CORE_ADDR struct_addr)
2585 int stack_offset = 0;
2587 /* First ensure that the stack and structure return address (if any)
2588 are properly aligned. The stack has to be at least 64-bit
2589 aligned even on 32-bit machines, because doubles must be 64-bit
2590 aligned. For n32 and n64, stack frames need to be 128-bit
2591 aligned, so we round to this widest known alignment. */
2593 sp = ROUND_DOWN (sp, 16);
2594 struct_addr = ROUND_DOWN (struct_addr, 16);
2596 /* Now make space on the stack for the args. We allocate more
2597 than necessary for EABI, because the first few arguments are
2598 passed in registers, but that's OK. */
2599 for (argnum = 0; argnum < nargs; argnum++)
2600 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2601 MIPS_STACK_ARGSIZE);
2602 sp -= ROUND_UP (len, 16);
2605 fprintf_unfiltered (gdb_stdlog,
2606 "mips_eabi_push_arguments: sp=0x%s allocated %d\n",
2607 paddr_nz (sp), ROUND_UP (len, 16));
2609 /* Initialize the integer and float register pointers. */
2611 float_argreg = FPA0_REGNUM;
2613 /* The struct_return pointer occupies the first parameter-passing reg. */
2617 fprintf_unfiltered (gdb_stdlog,
2618 "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n",
2619 argreg, paddr_nz (struct_addr));
2620 write_register (argreg++, struct_addr);
2623 /* Now load as many as possible of the first arguments into
2624 registers, and push the rest onto the stack. Loop thru args
2625 from first to last. */
2626 for (argnum = 0; argnum < nargs; argnum++)
2629 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2630 struct value *arg = args[argnum];
2631 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2632 int len = TYPE_LENGTH (arg_type);
2633 enum type_code typecode = TYPE_CODE (arg_type);
2636 fprintf_unfiltered (gdb_stdlog,
2637 "mips_eabi_push_arguments: %d len=%d type=%d",
2638 argnum + 1, len, (int) typecode);
2640 /* The EABI passes structures that do not fit in a register by
2642 if (len > MIPS_SAVED_REGSIZE
2643 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2645 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2646 typecode = TYPE_CODE_PTR;
2647 len = MIPS_SAVED_REGSIZE;
2650 fprintf_unfiltered (gdb_stdlog, " push");
2653 val = (char *) VALUE_CONTENTS (arg);
2655 /* 32-bit ABIs always start floating point arguments in an
2656 even-numbered floating point register. Round the FP register
2657 up before the check to see if there are any FP registers
2658 left. Non MIPS_EABI targets also pass the FP in the integer
2659 registers so also round up normal registers. */
2660 if (!FP_REGISTER_DOUBLE
2661 && fp_register_arg_p (typecode, arg_type))
2663 if ((float_argreg & 1))
2667 /* Floating point arguments passed in registers have to be
2668 treated specially. On 32-bit architectures, doubles
2669 are passed in register pairs; the even register gets
2670 the low word, and the odd register gets the high word.
2671 On non-EABI processors, the first two floating point arguments are
2672 also copied to general registers, because MIPS16 functions
2673 don't use float registers for arguments. This duplication of
2674 arguments in general registers can't hurt non-MIPS16 functions
2675 because those registers are normally skipped. */
2676 /* MIPS_EABI squeezes a struct that contains a single floating
2677 point value into an FP register instead of pushing it onto the
2679 if (fp_register_arg_p (typecode, arg_type)
2680 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2682 if (!FP_REGISTER_DOUBLE && len == 8)
2684 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2685 unsigned long regval;
2687 /* Write the low word of the double to the even register(s). */
2688 regval = extract_unsigned_integer (val + low_offset, 4);
2690 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2691 float_argreg, phex (regval, 4));
2692 write_register (float_argreg++, regval);
2694 /* Write the high word of the double to the odd register(s). */
2695 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2697 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2698 float_argreg, phex (regval, 4));
2699 write_register (float_argreg++, regval);
2703 /* This is a floating point value that fits entirely
2704 in a single register. */
2705 /* On 32 bit ABI's the float_argreg is further adjusted
2706 above to ensure that it is even register aligned. */
2707 LONGEST regval = extract_unsigned_integer (val, len);
2709 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2710 float_argreg, phex (regval, len));
2711 write_register (float_argreg++, regval);
2716 /* Copy the argument to general registers or the stack in
2717 register-sized pieces. Large arguments are split between
2718 registers and stack. */
2719 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2720 are treated specially: Irix cc passes them in registers
2721 where gcc sometimes puts them on the stack. For maximum
2722 compatibility, we will put them in both places. */
2723 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2724 (len % MIPS_SAVED_REGSIZE != 0));
2726 /* Note: Floating-point values that didn't fit into an FP
2727 register are only written to memory. */
2730 /* Remember if the argument was written to the stack. */
2731 int stack_used_p = 0;
2733 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2736 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2739 /* Write this portion of the argument to the stack. */
2740 if (argreg > MIPS_LAST_ARG_REGNUM
2742 || fp_register_arg_p (typecode, arg_type))
2744 /* Should shorter than int integer values be
2745 promoted to int before being stored? */
2746 int longword_offset = 0;
2749 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2751 if (MIPS_STACK_ARGSIZE == 8 &&
2752 (typecode == TYPE_CODE_INT ||
2753 typecode == TYPE_CODE_PTR ||
2754 typecode == TYPE_CODE_FLT) && len <= 4)
2755 longword_offset = MIPS_STACK_ARGSIZE - len;
2756 else if ((typecode == TYPE_CODE_STRUCT ||
2757 typecode == TYPE_CODE_UNION) &&
2758 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2759 longword_offset = MIPS_STACK_ARGSIZE - len;
2764 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2765 paddr_nz (stack_offset));
2766 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2767 paddr_nz (longword_offset));
2770 addr = sp + stack_offset + longword_offset;
2775 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2777 for (i = 0; i < partial_len; i++)
2779 fprintf_unfiltered (gdb_stdlog, "%02x",
2783 write_memory (addr, val, partial_len);
2786 /* Note!!! This is NOT an else clause. Odd sized
2787 structs may go thru BOTH paths. Floating point
2788 arguments will not. */
2789 /* Write this portion of the argument to a general
2790 purpose register. */
2791 if (argreg <= MIPS_LAST_ARG_REGNUM
2792 && !fp_register_arg_p (typecode, arg_type))
2794 LONGEST regval = extract_unsigned_integer (val, partial_len);
2797 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2799 phex (regval, MIPS_SAVED_REGSIZE));
2800 write_register (argreg, regval);
2807 /* Compute the the offset into the stack at which we
2808 will copy the next parameter.
2810 In the new EABI (and the NABI32), the stack_offset
2811 only needs to be adjusted when it has been used. */
2814 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2818 fprintf_unfiltered (gdb_stdlog, "\n");
2821 /* Return adjusted stack pointer. */
2825 /* N32/N64 version of push_arguments. */
2828 mips_n32n64_push_arguments (int nargs,
2829 struct value **args,
2832 CORE_ADDR struct_addr)
2838 int stack_offset = 0;
2840 /* First ensure that the stack and structure return address (if any)
2841 are properly aligned. The stack has to be at least 64-bit
2842 aligned even on 32-bit machines, because doubles must be 64-bit
2843 aligned. For n32 and n64, stack frames need to be 128-bit
2844 aligned, so we round to this widest known alignment. */
2846 sp = ROUND_DOWN (sp, 16);
2847 struct_addr = ROUND_DOWN (struct_addr, 16);
2849 /* Now make space on the stack for the args. */
2850 for (argnum = 0; argnum < nargs; argnum++)
2851 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2852 MIPS_STACK_ARGSIZE);
2853 sp -= ROUND_UP (len, 16);
2856 fprintf_unfiltered (gdb_stdlog,
2857 "mips_n32n64_push_arguments: sp=0x%s allocated %d\n",
2858 paddr_nz (sp), ROUND_UP (len, 16));
2860 /* Initialize the integer and float register pointers. */
2862 float_argreg = FPA0_REGNUM;
2864 /* The struct_return pointer occupies the first parameter-passing reg. */
2868 fprintf_unfiltered (gdb_stdlog,
2869 "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n",
2870 argreg, paddr_nz (struct_addr));
2871 write_register (argreg++, struct_addr);
2874 /* Now load as many as possible of the first arguments into
2875 registers, and push the rest onto the stack. Loop thru args
2876 from first to last. */
2877 for (argnum = 0; argnum < nargs; argnum++)
2880 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2881 struct value *arg = args[argnum];
2882 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2883 int len = TYPE_LENGTH (arg_type);
2884 enum type_code typecode = TYPE_CODE (arg_type);
2887 fprintf_unfiltered (gdb_stdlog,
2888 "mips_n32n64_push_arguments: %d len=%d type=%d",
2889 argnum + 1, len, (int) typecode);
2891 val = (char *) VALUE_CONTENTS (arg);
2893 if (fp_register_arg_p (typecode, arg_type)
2894 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2896 /* This is a floating point value that fits entirely
2897 in a single register. */
2898 /* On 32 bit ABI's the float_argreg is further adjusted
2899 above to ensure that it is even register aligned. */
2900 LONGEST regval = extract_unsigned_integer (val, len);
2902 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2903 float_argreg, phex (regval, len));
2904 write_register (float_argreg++, regval);
2907 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2908 argreg, phex (regval, len));
2909 write_register (argreg, regval);
2914 /* Copy the argument to general registers or the stack in
2915 register-sized pieces. Large arguments are split between
2916 registers and stack. */
2917 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2918 are treated specially: Irix cc passes them in registers
2919 where gcc sometimes puts them on the stack. For maximum
2920 compatibility, we will put them in both places. */
2921 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2922 (len % MIPS_SAVED_REGSIZE != 0));
2923 /* Note: Floating-point values that didn't fit into an FP
2924 register are only written to memory. */
2927 /* Rememer if the argument was written to the stack. */
2928 int stack_used_p = 0;
2929 int partial_len = len < MIPS_SAVED_REGSIZE ?
2930 len : MIPS_SAVED_REGSIZE;
2933 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2936 /* Write this portion of the argument to the stack. */
2937 if (argreg > MIPS_LAST_ARG_REGNUM
2939 || fp_register_arg_p (typecode, arg_type))
2941 /* Should shorter than int integer values be
2942 promoted to int before being stored? */
2943 int longword_offset = 0;
2946 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2948 if (MIPS_STACK_ARGSIZE == 8 &&
2949 (typecode == TYPE_CODE_INT ||
2950 typecode == TYPE_CODE_PTR ||
2951 typecode == TYPE_CODE_FLT) && len <= 4)
2952 longword_offset = MIPS_STACK_ARGSIZE - len;
2953 else if ((typecode == TYPE_CODE_STRUCT ||
2954 typecode == TYPE_CODE_UNION) &&
2955 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2956 longword_offset = MIPS_STACK_ARGSIZE - len;
2961 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2962 paddr_nz (stack_offset));
2963 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2964 paddr_nz (longword_offset));
2967 addr = sp + stack_offset + longword_offset;
2972 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2974 for (i = 0; i < partial_len; i++)
2976 fprintf_unfiltered (gdb_stdlog, "%02x",
2980 write_memory (addr, val, partial_len);
2983 /* Note!!! This is NOT an else clause. Odd sized
2984 structs may go thru BOTH paths. Floating point
2985 arguments will not. */
2986 /* Write this portion of the argument to a general
2987 purpose register. */
2988 if (argreg <= MIPS_LAST_ARG_REGNUM
2989 && !fp_register_arg_p (typecode, arg_type))
2991 LONGEST regval = extract_unsigned_integer (val, partial_len);
2993 /* A non-floating-point argument being passed in a
2994 general register. If a struct or union, and if
2995 the remaining length is smaller than the register
2996 size, we have to adjust the register value on
2999 It does not seem to be necessary to do the
3000 same for integral types.
3002 cagney/2001-07-23: gdb/179: Also, GCC, when
3003 outputting LE O32 with sizeof (struct) <
3004 MIPS_SAVED_REGSIZE, generates a left shift as
3005 part of storing the argument in a register a
3006 register (the left shift isn't generated when
3007 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3008 is quite possible that this is GCC contradicting
3009 the LE/O32 ABI, GDB has not been adjusted to
3010 accommodate this. Either someone needs to
3011 demonstrate that the LE/O32 ABI specifies such a
3012 left shift OR this new ABI gets identified as
3013 such and GDB gets tweaked accordingly. */
3015 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3016 && partial_len < MIPS_SAVED_REGSIZE
3017 && (typecode == TYPE_CODE_STRUCT ||
3018 typecode == TYPE_CODE_UNION))
3019 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3023 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3025 phex (regval, MIPS_SAVED_REGSIZE));
3026 write_register (argreg, regval);
3033 /* Compute the the offset into the stack at which we
3034 will copy the next parameter.
3036 In N32 (N64?), the stack_offset only needs to be
3037 adjusted when it has been used. */
3040 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3044 fprintf_unfiltered (gdb_stdlog, "\n");
3047 /* Return adjusted stack pointer. */
3051 /* O32 version of push_arguments. */
3054 mips_o32_push_arguments (int nargs,
3055 struct value **args,
3058 CORE_ADDR struct_addr)
3064 int stack_offset = 0;
3066 /* First ensure that the stack and structure return address (if any)
3067 are properly aligned. The stack has to be at least 64-bit
3068 aligned even on 32-bit machines, because doubles must be 64-bit
3069 aligned. For n32 and n64, stack frames need to be 128-bit
3070 aligned, so we round to this widest known alignment. */
3072 sp = ROUND_DOWN (sp, 16);
3073 struct_addr = ROUND_DOWN (struct_addr, 16);
3075 /* Now make space on the stack for the args. */
3076 for (argnum = 0; argnum < nargs; argnum++)
3077 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3078 MIPS_STACK_ARGSIZE);
3079 sp -= ROUND_UP (len, 16);
3082 fprintf_unfiltered (gdb_stdlog,
3083 "mips_o32_push_arguments: sp=0x%s allocated %d\n",
3084 paddr_nz (sp), ROUND_UP (len, 16));
3086 /* Initialize the integer and float register pointers. */
3088 float_argreg = FPA0_REGNUM;
3090 /* The struct_return pointer occupies the first parameter-passing reg. */
3094 fprintf_unfiltered (gdb_stdlog,
3095 "mips_o32_push_arguments: struct_return reg=%d 0x%s\n",
3096 argreg, paddr_nz (struct_addr));
3097 write_register (argreg++, struct_addr);
3098 stack_offset += MIPS_STACK_ARGSIZE;
3101 /* Now load as many as possible of the first arguments into
3102 registers, and push the rest onto the stack. Loop thru args
3103 from first to last. */
3104 for (argnum = 0; argnum < nargs; argnum++)
3107 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
3108 struct value *arg = args[argnum];
3109 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3110 int len = TYPE_LENGTH (arg_type);
3111 enum type_code typecode = TYPE_CODE (arg_type);
3114 fprintf_unfiltered (gdb_stdlog,
3115 "mips_o32_push_arguments: %d len=%d type=%d",
3116 argnum + 1, len, (int) typecode);
3118 val = (char *) VALUE_CONTENTS (arg);
3120 /* 32-bit ABIs always start floating point arguments in an
3121 even-numbered floating point register. Round the FP register
3122 up before the check to see if there are any FP registers
3123 left. O32/O64 targets also pass the FP in the integer
3124 registers so also round up normal registers. */
3125 if (!FP_REGISTER_DOUBLE
3126 && fp_register_arg_p (typecode, arg_type))
3128 if ((float_argreg & 1))
3132 /* Floating point arguments passed in registers have to be
3133 treated specially. On 32-bit architectures, doubles
3134 are passed in register pairs; the even register gets
3135 the low word, and the odd register gets the high word.
3136 On O32/O64, the first two floating point arguments are
3137 also copied to general registers, because MIPS16 functions
3138 don't use float registers for arguments. This duplication of
3139 arguments in general registers can't hurt non-MIPS16 functions
3140 because those registers are normally skipped. */
3142 if (fp_register_arg_p (typecode, arg_type)
3143 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3145 if (!FP_REGISTER_DOUBLE && len == 8)
3147 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3148 unsigned long regval;
3150 /* Write the low word of the double to the even register(s). */
3151 regval = extract_unsigned_integer (val + low_offset, 4);
3153 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3154 float_argreg, phex (regval, 4));
3155 write_register (float_argreg++, regval);
3157 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3158 argreg, phex (regval, 4));
3159 write_register (argreg++, regval);
3161 /* Write the high word of the double to the odd register(s). */
3162 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3164 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3165 float_argreg, phex (regval, 4));
3166 write_register (float_argreg++, regval);
3169 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3170 argreg, phex (regval, 4));
3171 write_register (argreg++, regval);
3175 /* This is a floating point value that fits entirely
3176 in a single register. */
3177 /* On 32 bit ABI's the float_argreg is further adjusted
3178 above to ensure that it is even register aligned. */
3179 LONGEST regval = extract_unsigned_integer (val, len);
3181 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3182 float_argreg, phex (regval, len));
3183 write_register (float_argreg++, regval);
3184 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3185 registers for each argument. The below is (my
3186 guess) to ensure that the corresponding integer
3187 register has reserved the same space. */
3189 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3190 argreg, phex (regval, len));
3191 write_register (argreg, regval);
3192 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3194 /* Reserve space for the FP register. */
3195 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3199 /* Copy the argument to general registers or the stack in
3200 register-sized pieces. Large arguments are split between
3201 registers and stack. */
3202 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3203 are treated specially: Irix cc passes them in registers
3204 where gcc sometimes puts them on the stack. For maximum
3205 compatibility, we will put them in both places. */
3206 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3207 (len % MIPS_SAVED_REGSIZE != 0));
3208 /* Structures should be aligned to eight bytes (even arg registers)
3209 on MIPS_ABI_O32, if their first member has double precision. */
3210 if (MIPS_SAVED_REGSIZE < 8
3211 && mips_type_needs_double_align (arg_type))
3216 /* Note: Floating-point values that didn't fit into an FP
3217 register are only written to memory. */
3220 /* Remember if the argument was written to the stack. */
3221 int stack_used_p = 0;
3223 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3226 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3229 /* Write this portion of the argument to the stack. */
3230 if (argreg > MIPS_LAST_ARG_REGNUM
3232 || fp_register_arg_p (typecode, arg_type))
3234 /* Should shorter than int integer values be
3235 promoted to int before being stored? */
3236 int longword_offset = 0;
3239 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3241 if (MIPS_STACK_ARGSIZE == 8 &&
3242 (typecode == TYPE_CODE_INT ||
3243 typecode == TYPE_CODE_PTR ||
3244 typecode == TYPE_CODE_FLT) && len <= 4)
3245 longword_offset = MIPS_STACK_ARGSIZE - len;
3250 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3251 paddr_nz (stack_offset));
3252 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3253 paddr_nz (longword_offset));
3256 addr = sp + stack_offset + longword_offset;
3261 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3263 for (i = 0; i < partial_len; i++)
3265 fprintf_unfiltered (gdb_stdlog, "%02x",
3269 write_memory (addr, val, partial_len);
3272 /* Note!!! This is NOT an else clause. Odd sized
3273 structs may go thru BOTH paths. Floating point
3274 arguments will not. */
3275 /* Write this portion of the argument to a general
3276 purpose register. */
3277 if (argreg <= MIPS_LAST_ARG_REGNUM
3278 && !fp_register_arg_p (typecode, arg_type))
3280 LONGEST regval = extract_signed_integer (val, partial_len);
3281 /* Value may need to be sign extended, because
3282 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3284 /* A non-floating-point argument being passed in a
3285 general register. If a struct or union, and if
3286 the remaining length is smaller than the register
3287 size, we have to adjust the register value on
3290 It does not seem to be necessary to do the
3291 same for integral types.
3293 Also don't do this adjustment on O64 binaries.
3295 cagney/2001-07-23: gdb/179: Also, GCC, when
3296 outputting LE O32 with sizeof (struct) <
3297 MIPS_SAVED_REGSIZE, generates a left shift as
3298 part of storing the argument in a register a
3299 register (the left shift isn't generated when
3300 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3301 is quite possible that this is GCC contradicting
3302 the LE/O32 ABI, GDB has not been adjusted to
3303 accommodate this. Either someone needs to
3304 demonstrate that the LE/O32 ABI specifies such a
3305 left shift OR this new ABI gets identified as
3306 such and GDB gets tweaked accordingly. */
3308 if (MIPS_SAVED_REGSIZE < 8
3309 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3310 && partial_len < MIPS_SAVED_REGSIZE
3311 && (typecode == TYPE_CODE_STRUCT ||
3312 typecode == TYPE_CODE_UNION))
3313 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3317 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3319 phex (regval, MIPS_SAVED_REGSIZE));
3320 write_register (argreg, regval);
3323 /* Prevent subsequent floating point arguments from
3324 being passed in floating point registers. */
3325 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3331 /* Compute the the offset into the stack at which we
3332 will copy the next parameter.
3334 In older ABIs, the caller reserved space for
3335 registers that contained arguments. This was loosely
3336 refered to as their "home". Consequently, space is
3337 always allocated. */
3339 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3343 fprintf_unfiltered (gdb_stdlog, "\n");
3346 /* Return adjusted stack pointer. */
3350 /* O64 version of push_arguments. */
3353 mips_o64_push_arguments (int nargs,
3354 struct value **args,
3357 CORE_ADDR struct_addr)
3363 int stack_offset = 0;
3365 /* First ensure that the stack and structure return address (if any)
3366 are properly aligned. The stack has to be at least 64-bit
3367 aligned even on 32-bit machines, because doubles must be 64-bit
3368 aligned. For n32 and n64, stack frames need to be 128-bit
3369 aligned, so we round to this widest known alignment. */
3371 sp = ROUND_DOWN (sp, 16);
3372 struct_addr = ROUND_DOWN (struct_addr, 16);
3374 /* Now make space on the stack for the args. */
3375 for (argnum = 0; argnum < nargs; argnum++)
3376 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3377 MIPS_STACK_ARGSIZE);
3378 sp -= ROUND_UP (len, 16);
3381 fprintf_unfiltered (gdb_stdlog,
3382 "mips_o64_push_arguments: sp=0x%s allocated %d\n",
3383 paddr_nz (sp), ROUND_UP (len, 16));
3385 /* Initialize the integer and float register pointers. */
3387 float_argreg = FPA0_REGNUM;
3389 /* The struct_return pointer occupies the first parameter-passing reg. */
3393 fprintf_unfiltered (gdb_stdlog,
3394 "mips_o64_push_arguments: struct_return reg=%d 0x%s\n",
3395 argreg, paddr_nz (struct_addr));
3396 write_register (argreg++, struct_addr);
3397 stack_offset += MIPS_STACK_ARGSIZE;
3400 /* Now load as many as possible of the first arguments into
3401 registers, and push the rest onto the stack. Loop thru args
3402 from first to last. */
3403 for (argnum = 0; argnum < nargs; argnum++)
3406 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
3407 struct value *arg = args[argnum];
3408 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3409 int len = TYPE_LENGTH (arg_type);
3410 enum type_code typecode = TYPE_CODE (arg_type);
3413 fprintf_unfiltered (gdb_stdlog,
3414 "mips_o64_push_arguments: %d len=%d type=%d",
3415 argnum + 1, len, (int) typecode);
3417 val = (char *) VALUE_CONTENTS (arg);
3419 /* 32-bit ABIs always start floating point arguments in an
3420 even-numbered floating point register. Round the FP register
3421 up before the check to see if there are any FP registers
3422 left. O32/O64 targets also pass the FP in the integer
3423 registers so also round up normal registers. */
3424 if (!FP_REGISTER_DOUBLE
3425 && fp_register_arg_p (typecode, arg_type))
3427 if ((float_argreg & 1))
3431 /* Floating point arguments passed in registers have to be
3432 treated specially. On 32-bit architectures, doubles
3433 are passed in register pairs; the even register gets
3434 the low word, and the odd register gets the high word.
3435 On O32/O64, the first two floating point arguments are
3436 also copied to general registers, because MIPS16 functions
3437 don't use float registers for arguments. This duplication of
3438 arguments in general registers can't hurt non-MIPS16 functions
3439 because those registers are normally skipped. */
3441 if (fp_register_arg_p (typecode, arg_type)
3442 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3444 if (!FP_REGISTER_DOUBLE && len == 8)
3446 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3447 unsigned long regval;
3449 /* Write the low word of the double to the even register(s). */
3450 regval = extract_unsigned_integer (val + low_offset, 4);
3452 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3453 float_argreg, phex (regval, 4));
3454 write_register (float_argreg++, regval);
3456 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3457 argreg, phex (regval, 4));
3458 write_register (argreg++, regval);
3460 /* Write the high word of the double to the odd register(s). */
3461 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3463 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3464 float_argreg, phex (regval, 4));
3465 write_register (float_argreg++, regval);
3468 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3469 argreg, phex (regval, 4));
3470 write_register (argreg++, regval);
3474 /* This is a floating point value that fits entirely
3475 in a single register. */
3476 /* On 32 bit ABI's the float_argreg is further adjusted
3477 above to ensure that it is even register aligned. */
3478 LONGEST regval = extract_unsigned_integer (val, len);
3480 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3481 float_argreg, phex (regval, len));
3482 write_register (float_argreg++, regval);
3483 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3484 registers for each argument. The below is (my
3485 guess) to ensure that the corresponding integer
3486 register has reserved the same space. */
3488 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3489 argreg, phex (regval, len));
3490 write_register (argreg, regval);
3491 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3493 /* Reserve space for the FP register. */
3494 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3498 /* Copy the argument to general registers or the stack in
3499 register-sized pieces. Large arguments are split between
3500 registers and stack. */
3501 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3502 are treated specially: Irix cc passes them in registers
3503 where gcc sometimes puts them on the stack. For maximum
3504 compatibility, we will put them in both places. */
3505 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3506 (len % MIPS_SAVED_REGSIZE != 0));
3507 /* Structures should be aligned to eight bytes (even arg registers)
3508 on MIPS_ABI_O32, if their first member has double precision. */
3509 if (MIPS_SAVED_REGSIZE < 8
3510 && mips_type_needs_double_align (arg_type))
3515 /* Note: Floating-point values that didn't fit into an FP
3516 register are only written to memory. */
3519 /* Remember if the argument was written to the stack. */
3520 int stack_used_p = 0;
3522 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3525 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3528 /* Write this portion of the argument to the stack. */
3529 if (argreg > MIPS_LAST_ARG_REGNUM
3531 || fp_register_arg_p (typecode, arg_type))
3533 /* Should shorter than int integer values be
3534 promoted to int before being stored? */
3535 int longword_offset = 0;
3538 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3540 if (MIPS_STACK_ARGSIZE == 8 &&
3541 (typecode == TYPE_CODE_INT ||
3542 typecode == TYPE_CODE_PTR ||
3543 typecode == TYPE_CODE_FLT) && len <= 4)
3544 longword_offset = MIPS_STACK_ARGSIZE - len;
3549 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3550 paddr_nz (stack_offset));
3551 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3552 paddr_nz (longword_offset));
3555 addr = sp + stack_offset + longword_offset;
3560 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3562 for (i = 0; i < partial_len; i++)
3564 fprintf_unfiltered (gdb_stdlog, "%02x",
3568 write_memory (addr, val, partial_len);
3571 /* Note!!! This is NOT an else clause. Odd sized
3572 structs may go thru BOTH paths. Floating point
3573 arguments will not. */
3574 /* Write this portion of the argument to a general
3575 purpose register. */
3576 if (argreg <= MIPS_LAST_ARG_REGNUM
3577 && !fp_register_arg_p (typecode, arg_type))
3579 LONGEST regval = extract_signed_integer (val, partial_len);
3580 /* Value may need to be sign extended, because
3581 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3583 /* A non-floating-point argument being passed in a
3584 general register. If a struct or union, and if
3585 the remaining length is smaller than the register
3586 size, we have to adjust the register value on
3589 It does not seem to be necessary to do the
3590 same for integral types.
3592 Also don't do this adjustment on O64 binaries.
3594 cagney/2001-07-23: gdb/179: Also, GCC, when
3595 outputting LE O32 with sizeof (struct) <
3596 MIPS_SAVED_REGSIZE, generates a left shift as
3597 part of storing the argument in a register a
3598 register (the left shift isn't generated when
3599 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3600 is quite possible that this is GCC contradicting
3601 the LE/O32 ABI, GDB has not been adjusted to
3602 accommodate this. Either someone needs to
3603 demonstrate that the LE/O32 ABI specifies such a
3604 left shift OR this new ABI gets identified as
3605 such and GDB gets tweaked accordingly. */
3607 if (MIPS_SAVED_REGSIZE < 8
3608 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3609 && partial_len < MIPS_SAVED_REGSIZE
3610 && (typecode == TYPE_CODE_STRUCT ||
3611 typecode == TYPE_CODE_UNION))
3612 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3616 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3618 phex (regval, MIPS_SAVED_REGSIZE));
3619 write_register (argreg, regval);
3622 /* Prevent subsequent floating point arguments from
3623 being passed in floating point registers. */
3624 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3630 /* Compute the the offset into the stack at which we
3631 will copy the next parameter.
3633 In older ABIs, the caller reserved space for
3634 registers that contained arguments. This was loosely
3635 refered to as their "home". Consequently, space is
3636 always allocated. */
3638 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3642 fprintf_unfiltered (gdb_stdlog, "\n");
3645 /* Return adjusted stack pointer. */
3650 mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
3652 /* Set the return address register to point to the entry
3653 point of the program, where a breakpoint lies in wait. */
3654 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
3659 mips_push_register (CORE_ADDR * sp, int regno)
3661 char *buffer = alloca (MAX_REGISTER_RAW_SIZE);
3664 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
3666 regsize = MIPS_SAVED_REGSIZE;
3667 offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3668 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
3673 regsize = REGISTER_RAW_SIZE (regno);
3677 read_register_gen (regno, buffer);
3678 write_memory (*sp, buffer + offset, regsize);
3681 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
3682 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
3685 mips_push_dummy_frame (void)
3688 struct linked_proc_info *link = (struct linked_proc_info *)
3689 xmalloc (sizeof (struct linked_proc_info));
3690 mips_extra_func_info_t proc_desc = &link->info;
3691 CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
3692 CORE_ADDR old_sp = sp;
3693 link->next = linked_proc_desc_table;
3694 linked_proc_desc_table = link;
3696 /* FIXME! are these correct ? */
3697 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
3698 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
3699 #define FLOAT_REG_SAVE_MASK MASK(0,19)
3700 #define FLOAT_SINGLE_REG_SAVE_MASK \
3701 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
3703 * The registers we must save are all those not preserved across
3704 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
3705 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
3706 * and FP Control/Status registers.
3709 * Dummy frame layout:
3712 * Saved MMHI, MMLO, FPC_CSR
3717 * Saved D18 (i.e. F19, F18)
3719 * Saved D0 (i.e. F1, F0)
3720 * Argument build area and stack arguments written via mips_push_arguments
3724 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
3725 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
3726 PROC_FRAME_OFFSET (proc_desc) = 0;
3727 PROC_FRAME_ADJUST (proc_desc) = 0;
3728 mips_push_register (&sp, PC_REGNUM);
3729 mips_push_register (&sp, HI_REGNUM);
3730 mips_push_register (&sp, LO_REGNUM);
3731 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
3733 /* Save general CPU registers */
3734 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
3735 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
3736 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
3737 for (ireg = 32; --ireg >= 0;)
3738 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
3739 mips_push_register (&sp, ireg);
3741 /* Save floating point registers starting with high order word */
3742 PROC_FREG_MASK (proc_desc) =
3743 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
3744 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
3745 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
3747 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
3748 for (ireg = 32; --ireg >= 0;)
3749 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
3750 mips_push_register (&sp, ireg + FP0_REGNUM);
3752 /* Update the frame pointer for the call dummy and the stack pointer.
3753 Set the procedure's starting and ending addresses to point to the
3754 call dummy address at the entry point. */
3755 write_register (PUSH_FP_REGNUM, old_sp);
3756 write_register (SP_REGNUM, sp);
3757 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
3758 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
3759 SET_PROC_DESC_IS_DUMMY (proc_desc);
3760 PROC_PC_REG (proc_desc) = RA_REGNUM;
3764 mips_pop_frame (void)
3766 register int regnum;
3767 struct frame_info *frame = get_current_frame ();
3768 CORE_ADDR new_sp = FRAME_FP (frame);
3770 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
3772 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
3773 if (frame->saved_regs == NULL)
3774 FRAME_INIT_SAVED_REGS (frame);
3775 for (regnum = 0; regnum < NUM_REGS; regnum++)
3776 if (regnum != SP_REGNUM && regnum != PC_REGNUM
3777 && frame->saved_regs[regnum])
3779 /* Floating point registers must not be sign extended,
3780 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3782 if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32)
3783 write_register (regnum,
3784 read_memory_unsigned_integer (frame->saved_regs[regnum],
3785 MIPS_SAVED_REGSIZE));
3787 write_register (regnum,
3788 read_memory_integer (frame->saved_regs[regnum],
3789 MIPS_SAVED_REGSIZE));
3792 write_register (SP_REGNUM, new_sp);
3793 flush_cached_frames ();
3795 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
3797 struct linked_proc_info *pi_ptr, *prev_ptr;
3799 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
3801 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
3803 if (&pi_ptr->info == proc_desc)
3808 error ("Can't locate dummy extra frame info\n");
3810 if (prev_ptr != NULL)
3811 prev_ptr->next = pi_ptr->next;
3813 linked_proc_desc_table = pi_ptr->next;
3817 write_register (HI_REGNUM,
3818 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
3819 MIPS_SAVED_REGSIZE));
3820 write_register (LO_REGNUM,
3821 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
3822 MIPS_SAVED_REGSIZE));
3823 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
3824 write_register (FCRCS_REGNUM,
3825 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
3826 MIPS_SAVED_REGSIZE));
3831 mips_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
3832 struct value **args, struct type *type, int gcc_p)
3834 write_register(T9_REGNUM, fun);
3837 /* Floating point register management.
3839 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3840 64bit operations, these early MIPS cpus treat fp register pairs
3841 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3842 registers and offer a compatibility mode that emulates the MIPS2 fp
3843 model. When operating in MIPS2 fp compat mode, later cpu's split
3844 double precision floats into two 32-bit chunks and store them in
3845 consecutive fp regs. To display 64-bit floats stored in this
3846 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3847 Throw in user-configurable endianness and you have a real mess.
3849 The way this works is:
3850 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3851 double-precision value will be split across two logical registers.
3852 The lower-numbered logical register will hold the low-order bits,
3853 regardless of the processor's endianness.
3854 - If we are on a 64-bit processor, and we are looking for a
3855 single-precision value, it will be in the low ordered bits
3856 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3857 save slot in memory.
3858 - If we are in 64-bit mode, everything is straightforward.
3860 Note that this code only deals with "live" registers at the top of the
3861 stack. We will attempt to deal with saved registers later, when
3862 the raw/cooked register interface is in place. (We need a general
3863 interface that can deal with dynamic saved register sizes -- fp
3864 regs could be 32 bits wide in one frame and 64 on the frame above
3867 static struct type *
3868 mips_float_register_type (void)
3870 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3871 return builtin_type_ieee_single_big;
3873 return builtin_type_ieee_single_little;
3876 static struct type *
3877 mips_double_register_type (void)
3879 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3880 return builtin_type_ieee_double_big;
3882 return builtin_type_ieee_double_little;
3885 /* Copy a 32-bit single-precision value from the current frame
3886 into rare_buffer. */
3889 mips_read_fp_register_single (int regno, char *rare_buffer)
3891 int raw_size = REGISTER_RAW_SIZE (regno);
3892 char *raw_buffer = alloca (raw_size);
3894 if (!frame_register_read (selected_frame, regno, raw_buffer))
3895 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3898 /* We have a 64-bit value for this register. Find the low-order
3902 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3907 memcpy (rare_buffer, raw_buffer + offset, 4);
3911 memcpy (rare_buffer, raw_buffer, 4);
3915 /* Copy a 64-bit double-precision value from the current frame into
3916 rare_buffer. This may include getting half of it from the next
3920 mips_read_fp_register_double (int regno, char *rare_buffer)
3922 int raw_size = REGISTER_RAW_SIZE (regno);
3924 if (raw_size == 8 && !mips2_fp_compat ())
3926 /* We have a 64-bit value for this register, and we should use
3928 if (!frame_register_read (selected_frame, regno, rare_buffer))
3929 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3933 if ((regno - FP0_REGNUM) & 1)
3934 internal_error (__FILE__, __LINE__,
3935 "mips_read_fp_register_double: bad access to "
3936 "odd-numbered FP register");
3938 /* mips_read_fp_register_single will find the correct 32 bits from
3940 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3942 mips_read_fp_register_single (regno, rare_buffer + 4);
3943 mips_read_fp_register_single (regno + 1, rare_buffer);
3947 mips_read_fp_register_single (regno, rare_buffer);
3948 mips_read_fp_register_single (regno + 1, rare_buffer + 4);
3954 mips_print_register (int regnum, int all)
3956 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
3958 /* Get the data in raw format. */
3959 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3961 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
3965 /* If we have a actual 32-bit floating point register (or we are in
3966 32-bit compatibility mode), and the register is even-numbered,
3967 also print it as a double (spanning two registers). */
3968 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
3969 && (REGISTER_RAW_SIZE (regnum) == 4
3970 || mips2_fp_compat ())
3971 && !((regnum - FP0_REGNUM) & 1))
3973 char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE);
3975 mips_read_fp_register_double (regnum, dbuffer);
3977 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
3978 val_print (mips_double_register_type (), dbuffer, 0, 0,
3979 gdb_stdout, 0, 1, 0, Val_pretty_default);
3980 printf_filtered ("); ");
3982 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3984 /* The problem with printing numeric register names (r26, etc.) is that
3985 the user can't use them on input. Probably the best solution is to
3986 fix it so that either the numeric or the funky (a2, etc.) names
3987 are accepted on input. */
3988 if (regnum < MIPS_NUMREGS)
3989 printf_filtered ("(r%d): ", regnum);
3991 printf_filtered (": ");
3993 /* If virtual format is floating, print it that way. */
3994 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3995 if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
3997 /* We have a meaningful 64-bit value in this register. Show
3998 it as a 32-bit float and a 64-bit double. */
3999 int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
4001 printf_filtered (" (float) ");
4002 val_print (mips_float_register_type (), raw_buffer + offset, 0, 0,
4003 gdb_stdout, 0, 1, 0, Val_pretty_default);
4004 printf_filtered (", (double) ");
4005 val_print (mips_double_register_type (), raw_buffer, 0, 0,
4006 gdb_stdout, 0, 1, 0, Val_pretty_default);
4009 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4010 gdb_stdout, 0, 1, 0, Val_pretty_default);
4011 /* Else print as integer in hex. */
4016 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4017 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4021 print_scalar_formatted (raw_buffer + offset,
4022 REGISTER_VIRTUAL_TYPE (regnum),
4023 'x', 0, gdb_stdout);
4027 /* Replacement for generic do_registers_info.
4028 Print regs in pretty columns. */
4031 do_fp_register_row (int regnum)
4032 { /* do values for FP (float) regs */
4034 double doub, flt1, flt2; /* doubles extracted from raw hex data */
4035 int inv1, inv2, inv3;
4037 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
4039 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
4041 /* 4-byte registers: we can fit two registers per row. */
4042 /* Also print every pair of 4-byte regs as an 8-byte double. */
4043 mips_read_fp_register_single (regnum, raw_buffer);
4044 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4046 mips_read_fp_register_single (regnum + 1, raw_buffer);
4047 flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2);
4049 mips_read_fp_register_double (regnum, raw_buffer);
4050 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
4052 printf_filtered (" %-5s", REGISTER_NAME (regnum));
4054 printf_filtered (": <invalid float>");
4056 printf_filtered ("%-17.9g", flt1);
4058 printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
4060 printf_filtered (": <invalid float>");
4062 printf_filtered ("%-17.9g", flt2);
4064 printf_filtered (" dbl: ");
4066 printf_filtered ("<invalid double>");
4068 printf_filtered ("%-24.17g", doub);
4069 printf_filtered ("\n");
4071 /* may want to do hex display here (future enhancement) */
4076 /* Eight byte registers: print each one as float AND as double. */
4077 mips_read_fp_register_single (regnum, raw_buffer);
4078 flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1);
4080 mips_read_fp_register_double (regnum, raw_buffer);
4081 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
4083 printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
4085 printf_filtered ("<invalid float>");
4087 printf_filtered ("flt: %-17.9g", flt1);
4089 printf_filtered (" dbl: ");
4091 printf_filtered ("<invalid double>");
4093 printf_filtered ("%-24.17g", doub);
4095 printf_filtered ("\n");
4096 /* may want to do hex display here (future enhancement) */
4102 /* Print a row's worth of GP (int) registers, with name labels above */
4105 do_gp_register_row (int regnum)
4107 /* do values for GP (int) regs */
4108 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4109 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
4111 int start_regnum = regnum;
4112 int numregs = NUM_REGS;
4115 /* For GP registers, we print a separate row of names above the vals */
4116 printf_filtered (" ");
4117 for (col = 0; col < ncols && regnum < numregs; regnum++)
4119 if (*REGISTER_NAME (regnum) == '\0')
4120 continue; /* unused register */
4121 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4122 break; /* end the row: reached FP register */
4123 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
4124 REGISTER_NAME (regnum));
4127 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
4128 start_regnum); /* print the R0 to R31 names */
4130 regnum = start_regnum; /* go back to start of row */
4131 /* now print the values in hex, 4 or 8 to the row */
4132 for (col = 0; col < ncols && regnum < numregs; regnum++)
4134 if (*REGISTER_NAME (regnum) == '\0')
4135 continue; /* unused register */
4136 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4137 break; /* end row: reached FP register */
4138 /* OK: get the data in raw format. */
4139 if (!frame_register_read (selected_frame, regnum, raw_buffer))
4140 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4141 /* pad small registers */
4142 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
4143 printf_filtered (" ");
4144 /* Now print the register value in hex, endian order. */
4145 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4146 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4147 byte < REGISTER_RAW_SIZE (regnum);
4149 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
4151 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
4154 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
4155 printf_filtered (" ");
4158 if (col > 0) /* ie. if we actually printed anything... */
4159 printf_filtered ("\n");
4164 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4167 mips_do_registers_info (int regnum, int fpregs)
4169 if (regnum != -1) /* do one specified register */
4171 if (*(REGISTER_NAME (regnum)) == '\0')
4172 error ("Not a valid register for the current processor type");
4174 mips_print_register (regnum, 0);
4175 printf_filtered ("\n");
4178 /* do all (or most) registers */
4181 while (regnum < NUM_REGS)
4183 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4184 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
4185 regnum = do_fp_register_row (regnum); /* FP regs */
4187 regnum += MIPS_NUMREGS; /* skip floating point regs */
4189 regnum = do_gp_register_row (regnum); /* GP (int) regs */
4194 /* Is this a branch with a delay slot? */
4196 static int is_delayed (unsigned long);
4199 is_delayed (unsigned long insn)
4202 for (i = 0; i < NUMOPCODES; ++i)
4203 if (mips_opcodes[i].pinfo != INSN_MACRO
4204 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4206 return (i < NUMOPCODES
4207 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4208 | INSN_COND_BRANCH_DELAY
4209 | INSN_COND_BRANCH_LIKELY)));
4213 mips_step_skips_delay (CORE_ADDR pc)
4215 char buf[MIPS_INSTLEN];
4217 /* There is no branch delay slot on MIPS16. */
4218 if (pc_is_mips16 (pc))
4221 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4222 /* If error reading memory, guess that it is not a delayed branch. */
4224 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
4228 /* Skip the PC past function prologue instructions (32-bit version).
4229 This is a helper function for mips_skip_prologue. */
4232 mips32_skip_prologue (CORE_ADDR pc)
4236 int seen_sp_adjust = 0;
4237 int load_immediate_bytes = 0;
4239 /* Skip the typical prologue instructions. These are the stack adjustment
4240 instruction and the instructions that save registers on the stack
4241 or in the gcc frame. */
4242 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
4244 unsigned long high_word;
4246 inst = mips_fetch_instruction (pc);
4247 high_word = (inst >> 16) & 0xffff;
4249 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4250 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4252 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4253 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4255 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4256 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4257 && (inst & 0x001F0000)) /* reg != $zero */
4260 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4262 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4264 continue; /* reg != $zero */
4266 /* move $s8,$sp. With different versions of gas this will be either
4267 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4268 Accept any one of these. */
4269 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4272 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4274 else if (high_word == 0x3c1c) /* lui $gp,n */
4276 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4278 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4279 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4281 /* The following instructions load $at or $t0 with an immediate
4282 value in preparation for a stack adjustment via
4283 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4284 a local variable, so we accept them only before a stack adjustment
4285 instruction was seen. */
4286 else if (!seen_sp_adjust)
4288 if (high_word == 0x3c01 || /* lui $at,n */
4289 high_word == 0x3c08) /* lui $t0,n */
4291 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4294 else if (high_word == 0x3421 || /* ori $at,$at,n */
4295 high_word == 0x3508 || /* ori $t0,$t0,n */
4296 high_word == 0x3401 || /* ori $at,$zero,n */
4297 high_word == 0x3408) /* ori $t0,$zero,n */
4299 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4309 /* In a frameless function, we might have incorrectly
4310 skipped some load immediate instructions. Undo the skipping
4311 if the load immediate was not followed by a stack adjustment. */
4312 if (load_immediate_bytes && !seen_sp_adjust)
4313 pc -= load_immediate_bytes;
4317 /* Skip the PC past function prologue instructions (16-bit version).
4318 This is a helper function for mips_skip_prologue. */
4321 mips16_skip_prologue (CORE_ADDR pc)
4324 int extend_bytes = 0;
4325 int prev_extend_bytes;
4327 /* Table of instructions likely to be found in a function prologue. */
4330 unsigned short inst;
4331 unsigned short mask;
4338 , /* addiu $sp,offset */
4342 , /* daddiu $sp,offset */
4346 , /* sw reg,n($sp) */
4350 , /* sd reg,n($sp) */
4354 , /* sw $ra,n($sp) */
4358 , /* sd $ra,n($sp) */
4366 , /* sw $a0-$a3,n($s1) */
4370 , /* move reg,$a0-$a3 */
4374 , /* entry pseudo-op */
4378 , /* addiu $s1,$sp,n */
4381 } /* end of table marker */
4384 /* Skip the typical prologue instructions. These are the stack adjustment
4385 instruction and the instructions that save registers on the stack
4386 or in the gcc frame. */
4387 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
4389 unsigned short inst;
4392 inst = mips_fetch_instruction (pc);
4394 /* Normally we ignore an extend instruction. However, if it is
4395 not followed by a valid prologue instruction, we must adjust
4396 the pc back over the extend so that it won't be considered
4397 part of the prologue. */
4398 if ((inst & 0xf800) == 0xf000) /* extend */
4400 extend_bytes = MIPS16_INSTLEN;
4403 prev_extend_bytes = extend_bytes;
4406 /* Check for other valid prologue instructions besides extend. */
4407 for (i = 0; table[i].mask != 0; i++)
4408 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4410 if (table[i].mask != 0) /* it was in table? */
4411 continue; /* ignore it */
4415 /* Return the current pc, adjusted backwards by 2 if
4416 the previous instruction was an extend. */
4417 return pc - prev_extend_bytes;
4423 /* To skip prologues, I use this predicate. Returns either PC itself
4424 if the code at PC does not look like a function prologue; otherwise
4425 returns an address that (if we're lucky) follows the prologue. If
4426 LENIENT, then we must skip everything which is involved in setting
4427 up the frame (it's OK to skip more, just so long as we don't skip
4428 anything which might clobber the registers which are being saved.
4429 We must skip more in the case where part of the prologue is in the
4430 delay slot of a non-prologue instruction). */
4433 mips_skip_prologue (CORE_ADDR pc)
4435 /* See if we can determine the end of the prologue via the symbol table.
4436 If so, then return either PC, or the PC after the prologue, whichever
4439 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4441 if (post_prologue_pc != 0)
4442 return max (pc, post_prologue_pc);
4444 /* Can't determine prologue from the symbol table, need to examine
4447 if (pc_is_mips16 (pc))
4448 return mips16_skip_prologue (pc);
4450 return mips32_skip_prologue (pc);
4453 /* Determine how a return value is stored within the MIPS register
4454 file, given the return type `valtype'. */
4456 struct return_value_word
4465 return_value_location (struct type *valtype,
4466 struct return_value_word *hi,
4467 struct return_value_word *lo)
4469 int len = TYPE_LENGTH (valtype);
4471 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
4472 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
4473 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
4475 if (!FP_REGISTER_DOUBLE && len == 8)
4477 /* We need to break a 64bit float in two 32 bit halves and
4478 spread them across a floating-point register pair. */
4479 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
4480 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
4481 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4482 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
4484 hi->reg_offset = lo->reg_offset;
4485 lo->reg = FP0_REGNUM + 0;
4486 hi->reg = FP0_REGNUM + 1;
4492 /* The floating point value fits in a single floating-point
4494 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4495 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
4498 lo->reg = FP0_REGNUM;
4509 /* Locate a result possibly spread across two registers. */
4511 lo->reg = regnum + 0;
4512 hi->reg = regnum + 1;
4513 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4514 && len < MIPS_SAVED_REGSIZE)
4516 /* "un-left-justify" the value in the low register */
4517 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
4522 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4523 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
4524 && len < MIPS_SAVED_REGSIZE * 2
4525 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
4526 TYPE_CODE (valtype) == TYPE_CODE_UNION))
4528 /* "un-left-justify" the value spread across two registers. */
4529 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
4530 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
4532 hi->len = len - lo->len;
4536 /* Only perform a partial copy of the second register. */
4539 if (len > MIPS_SAVED_REGSIZE)
4541 lo->len = MIPS_SAVED_REGSIZE;
4542 hi->len = len - MIPS_SAVED_REGSIZE;
4550 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4551 && REGISTER_RAW_SIZE (regnum) == 8
4552 && MIPS_SAVED_REGSIZE == 4)
4554 /* Account for the fact that only the least-signficant part
4555 of the register is being used */
4556 lo->reg_offset += 4;
4557 hi->reg_offset += 4;
4560 hi->buf_offset = lo->len;
4564 /* Given a return value in `regbuf' with a type `valtype', extract and
4565 copy its value into `valbuf'. */
4568 mips_eabi_extract_return_value (struct type *valtype,
4569 char regbuf[REGISTER_BYTES],
4572 struct return_value_word lo;
4573 struct return_value_word hi;
4574 return_value_location (valtype, &hi, &lo);
4576 memcpy (valbuf + lo.buf_offset,
4577 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4581 memcpy (valbuf + hi.buf_offset,
4582 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4587 mips_o64_extract_return_value (struct type *valtype,
4588 char regbuf[REGISTER_BYTES],
4591 struct return_value_word lo;
4592 struct return_value_word hi;
4593 return_value_location (valtype, &hi, &lo);
4595 memcpy (valbuf + lo.buf_offset,
4596 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4600 memcpy (valbuf + hi.buf_offset,
4601 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4605 /* Given a return value in `valbuf' with a type `valtype', write it's
4606 value into the appropriate register. */
4609 mips_eabi_store_return_value (struct type *valtype, char *valbuf)
4611 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4612 struct return_value_word lo;
4613 struct return_value_word hi;
4614 return_value_location (valtype, &hi, &lo);
4616 memset (raw_buffer, 0, sizeof (raw_buffer));
4617 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4618 write_register_bytes (REGISTER_BYTE (lo.reg),
4620 REGISTER_RAW_SIZE (lo.reg));
4624 memset (raw_buffer, 0, sizeof (raw_buffer));
4625 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4626 write_register_bytes (REGISTER_BYTE (hi.reg),
4628 REGISTER_RAW_SIZE (hi.reg));
4633 mips_o64_store_return_value (struct type *valtype, char *valbuf)
4635 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4636 struct return_value_word lo;
4637 struct return_value_word hi;
4638 return_value_location (valtype, &hi, &lo);
4640 memset (raw_buffer, 0, sizeof (raw_buffer));
4641 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4642 write_register_bytes (REGISTER_BYTE (lo.reg),
4644 REGISTER_RAW_SIZE (lo.reg));
4648 memset (raw_buffer, 0, sizeof (raw_buffer));
4649 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4650 write_register_bytes (REGISTER_BYTE (hi.reg),
4652 REGISTER_RAW_SIZE (hi.reg));
4656 /* O32 ABI stuff. */
4659 mips_o32_xfer_return_value (struct type *type,
4660 struct regcache *regcache,
4661 bfd_byte *in, const bfd_byte *out)
4663 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4664 if (TYPE_CODE (type) == TYPE_CODE_FLT
4665 && TYPE_LENGTH (type) == 4
4666 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4668 /* A single-precision floating-point value. It fits in the
4669 least significant part of FP0. */
4671 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4672 mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type),
4673 TARGET_BYTE_ORDER, in, out, 0);
4675 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4676 && TYPE_LENGTH (type) == 8
4677 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4679 /* A double-precision floating-point value. It fits in the
4680 least significant part of FP0/FP1 but with byte ordering
4681 based on the target (???). */
4683 fprintf_unfiltered (gdb_stderr, "Return float in $fp0/$fp1\n");
4684 switch (TARGET_BYTE_ORDER)
4686 case BFD_ENDIAN_LITTLE:
4687 mips_xfer_register (regcache, FP0_REGNUM + 0, 4,
4688 TARGET_BYTE_ORDER, in, out, 0);
4689 mips_xfer_register (regcache, FP0_REGNUM + 1, 4,
4690 TARGET_BYTE_ORDER, in, out, 4);
4692 case BFD_ENDIAN_BIG:
4693 mips_xfer_register (regcache, FP0_REGNUM + 1, 4,
4694 TARGET_BYTE_ORDER, in, out, 0);
4695 mips_xfer_register (regcache, FP0_REGNUM + 0, 4,
4696 TARGET_BYTE_ORDER, in, out, 4);
4699 internal_error (__FILE__, __LINE__, "bad switch");
4703 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4704 && TYPE_NFIELDS (type) <= 2
4705 && TYPE_NFIELDS (type) >= 1
4706 && ((TYPE_NFIELDS (type) == 1
4707 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4709 || (TYPE_NFIELDS (type) == 2
4710 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4712 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4714 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4716 /* A struct that contains one or two floats. Each value is part
4717 in the least significant part of their floating point
4719 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
4722 for (field = 0, regnum = FP0_REGNUM;
4723 field < TYPE_NFIELDS (type);
4724 field++, regnum += 2)
4726 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4729 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4730 mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4731 TARGET_BYTE_ORDER, in, out, offset);
4736 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4737 || TYPE_CODE (type) == TYPE_CODE_UNION)
4739 /* A structure or union. Extract the left justified value,
4740 regardless of the byte order. I.e. DO NOT USE
4744 for (offset = 0, regnum = V0_REGNUM;
4745 offset < TYPE_LENGTH (type);
4746 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4748 int xfer = REGISTER_RAW_SIZE (regnum);
4749 if (offset + xfer > TYPE_LENGTH (type))
4750 xfer = TYPE_LENGTH (type) - offset;
4752 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4753 offset, xfer, regnum);
4754 mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN,
4761 /* A scalar extract each part but least-significant-byte
4762 justified. o32 thinks registers are 4 byte, regardless of
4763 the ISA. mips_stack_argsize controls this. */
4766 for (offset = 0, regnum = V0_REGNUM;
4767 offset < TYPE_LENGTH (type);
4768 offset += mips_stack_argsize (), regnum++)
4770 int xfer = mips_stack_argsize ();
4772 if (offset + xfer > TYPE_LENGTH (type))
4773 xfer = TYPE_LENGTH (type) - offset;
4775 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4776 offset, xfer, regnum);
4777 mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER,
4784 mips_o32_extract_return_value (struct type *type,
4785 struct regcache *regcache,
4788 mips_o32_xfer_return_value (type, regcache, valbuf, NULL);
4792 mips_o32_store_return_value (struct type *type, char *valbuf)
4794 mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf);
4797 /* N32/N44 ABI stuff. */
4800 mips_n32n64_xfer_return_value (struct type *type,
4801 struct regcache *regcache,
4802 bfd_byte *in, const bfd_byte *out)
4804 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4805 if (TYPE_CODE (type) == TYPE_CODE_FLT
4806 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4808 /* A floating-point value belongs in the least significant part
4811 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4812 mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type),
4813 TARGET_BYTE_ORDER, in, out, 0);
4815 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4816 && TYPE_NFIELDS (type) <= 2
4817 && TYPE_NFIELDS (type) >= 1
4818 && ((TYPE_NFIELDS (type) == 1
4819 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4821 || (TYPE_NFIELDS (type) == 2
4822 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4824 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4826 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4828 /* A struct that contains one or two floats. Each value is part
4829 in the least significant part of their floating point
4831 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
4834 for (field = 0, regnum = FP0_REGNUM;
4835 field < TYPE_NFIELDS (type);
4836 field++, regnum += 2)
4838 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4841 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4842 mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4843 TARGET_BYTE_ORDER, in, out, offset);
4846 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4847 || TYPE_CODE (type) == TYPE_CODE_UNION)
4849 /* A structure or union. Extract the left justified value,
4850 regardless of the byte order. I.e. DO NOT USE
4854 for (offset = 0, regnum = V0_REGNUM;
4855 offset < TYPE_LENGTH (type);
4856 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4858 int xfer = REGISTER_RAW_SIZE (regnum);
4859 if (offset + xfer > TYPE_LENGTH (type))
4860 xfer = TYPE_LENGTH (type) - offset;
4862 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4863 offset, xfer, regnum);
4864 mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN,
4870 /* A scalar extract each part but least-significant-byte
4874 for (offset = 0, regnum = V0_REGNUM;
4875 offset < TYPE_LENGTH (type);
4876 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4878 int xfer = REGISTER_RAW_SIZE (regnum);
4880 if (offset + xfer > TYPE_LENGTH (type))
4881 xfer = TYPE_LENGTH (type) - offset;
4883 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4884 offset, xfer, regnum);
4885 mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER,
4892 mips_n32n64_extract_return_value (struct type *type,
4893 struct regcache *regcache,
4896 mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL);
4900 mips_n32n64_store_return_value (struct type *type, char *valbuf)
4902 mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf);
4906 mips_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
4908 /* Nothing to do -- push_arguments does all the work. */
4912 mips_extract_struct_value_address (struct regcache *ignore)
4914 /* FIXME: This will only work at random. The caller passes the
4915 struct_return address in V0, but it is not preserved. It may
4916 still be there, or this may be a random value. */
4917 return read_register (V0_REGNUM);
4920 /* Exported procedure: Is PC in the signal trampoline code */
4923 mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore)
4925 if (sigtramp_address == 0)
4927 return (pc >= sigtramp_address && pc < sigtramp_end);
4930 /* Root of all "set mips "/"show mips " commands. This will eventually be
4931 used for all MIPS-specific commands. */
4934 show_mips_command (char *args, int from_tty)
4936 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4940 set_mips_command (char *args, int from_tty)
4942 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4943 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4946 /* Commands to show/set the MIPS FPU type. */
4949 show_mipsfpu_command (char *args, int from_tty)
4952 switch (MIPS_FPU_TYPE)
4954 case MIPS_FPU_SINGLE:
4955 fpu = "single-precision";
4957 case MIPS_FPU_DOUBLE:
4958 fpu = "double-precision";
4961 fpu = "absent (none)";
4964 internal_error (__FILE__, __LINE__, "bad switch");
4966 if (mips_fpu_type_auto)
4967 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4970 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
4976 set_mipsfpu_command (char *args, int from_tty)
4978 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4979 show_mipsfpu_command (args, from_tty);
4983 set_mipsfpu_single_command (char *args, int from_tty)
4985 mips_fpu_type = MIPS_FPU_SINGLE;
4986 mips_fpu_type_auto = 0;
4987 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
4991 set_mipsfpu_double_command (char *args, int from_tty)
4993 mips_fpu_type = MIPS_FPU_DOUBLE;
4994 mips_fpu_type_auto = 0;
4995 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
4999 set_mipsfpu_none_command (char *args, int from_tty)
5001 mips_fpu_type = MIPS_FPU_NONE;
5002 mips_fpu_type_auto = 0;
5003 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
5007 set_mipsfpu_auto_command (char *args, int from_tty)
5009 mips_fpu_type_auto = 1;
5012 /* Command to set the processor type. */
5015 mips_set_processor_type_command (char *args, int from_tty)
5019 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
5021 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5022 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5023 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
5025 /* Restore the value. */
5026 tmp_mips_processor_type = xstrdup (mips_processor_type);
5031 if (!mips_set_processor_type (tmp_mips_processor_type))
5033 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
5034 /* Restore its value. */
5035 tmp_mips_processor_type = xstrdup (mips_processor_type);
5040 mips_show_processor_type_command (char *args, int from_tty)
5044 /* Modify the actual processor type. */
5047 mips_set_processor_type (char *str)
5054 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5056 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
5058 mips_processor_type = str;
5059 mips_processor_reg_names = mips_processor_type_table[i].regnames;
5061 /* FIXME tweak fpu flag too */
5068 /* Attempt to identify the particular processor model by reading the
5072 mips_read_processor_type (void)
5076 prid = read_register (PRID_REGNUM);
5078 if ((prid & ~0xf) == 0x700)
5079 return savestring ("r3041", strlen ("r3041"));
5084 /* Just like reinit_frame_cache, but with the right arguments to be
5085 callable as an sfunc. */
5088 reinit_frame_cache_sfunc (char *args, int from_tty,
5089 struct cmd_list_element *c)
5091 reinit_frame_cache ();
5095 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
5097 mips_extra_func_info_t proc_desc;
5099 /* Search for the function containing this address. Set the low bit
5100 of the address when searching, in case we were given an even address
5101 that is the start of a 16-bit function. If we didn't do this,
5102 the search would fail because the symbol table says the function
5103 starts at an odd address, i.e. 1 byte past the given address. */
5104 memaddr = ADDR_BITS_REMOVE (memaddr);
5105 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
5107 /* Make an attempt to determine if this is a 16-bit function. If
5108 the procedure descriptor exists and the address therein is odd,
5109 it's definitely a 16-bit function. Otherwise, we have to just
5110 guess that if the address passed in is odd, it's 16-bits. */
5112 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
5113 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
5115 info->mach = pc_is_mips16 (memaddr) ?
5116 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
5118 /* Round down the instruction address to the appropriate boundary. */
5119 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
5121 /* Call the appropriate disassembler based on the target endian-ness. */
5122 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5123 return print_insn_big_mips (memaddr, info);
5125 return print_insn_little_mips (memaddr, info);
5128 /* Old-style breakpoint macros.
5129 The IDT board uses an unusual breakpoint value, and sometimes gets
5130 confused when it sees the usual MIPS breakpoint instruction. */
5132 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
5133 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
5134 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
5135 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
5136 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
5137 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
5138 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
5139 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
5141 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5142 counter value to determine whether a 16- or 32-bit breakpoint should be
5143 used. It returns a pointer to a string of bytes that encode a breakpoint
5144 instruction, stores the length of the string to *lenptr, and adjusts pc
5145 (if necessary) to point to the actual memory location where the
5146 breakpoint should be inserted. */
5148 static const unsigned char *
5149 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
5151 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5153 if (pc_is_mips16 (*pcptr))
5155 static unsigned char mips16_big_breakpoint[] =
5156 MIPS16_BIG_BREAKPOINT;
5157 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
5158 *lenptr = sizeof (mips16_big_breakpoint);
5159 return mips16_big_breakpoint;
5163 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
5164 static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
5165 static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
5167 *lenptr = sizeof (big_breakpoint);
5169 if (strcmp (target_shortname, "mips") == 0)
5170 return idt_big_breakpoint;
5171 else if (strcmp (target_shortname, "ddb") == 0
5172 || strcmp (target_shortname, "pmon") == 0
5173 || strcmp (target_shortname, "lsi") == 0)
5174 return pmon_big_breakpoint;
5176 return big_breakpoint;
5181 if (pc_is_mips16 (*pcptr))
5183 static unsigned char mips16_little_breakpoint[] =
5184 MIPS16_LITTLE_BREAKPOINT;
5185 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
5186 *lenptr = sizeof (mips16_little_breakpoint);
5187 return mips16_little_breakpoint;
5191 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
5192 static unsigned char pmon_little_breakpoint[] =
5193 PMON_LITTLE_BREAKPOINT;
5194 static unsigned char idt_little_breakpoint[] =
5195 IDT_LITTLE_BREAKPOINT;
5197 *lenptr = sizeof (little_breakpoint);
5199 if (strcmp (target_shortname, "mips") == 0)
5200 return idt_little_breakpoint;
5201 else if (strcmp (target_shortname, "ddb") == 0
5202 || strcmp (target_shortname, "pmon") == 0
5203 || strcmp (target_shortname, "lsi") == 0)
5204 return pmon_little_breakpoint;
5206 return little_breakpoint;
5211 /* If PC is in a mips16 call or return stub, return the address of the target
5212 PC, which is either the callee or the caller. There are several
5213 cases which must be handled:
5215 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5216 target PC is in $31 ($ra).
5217 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5218 and the target PC is in $2.
5219 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5220 before the jal instruction, this is effectively a call stub
5221 and the the target PC is in $2. Otherwise this is effectively
5222 a return stub and the target PC is in $18.
5224 See the source code for the stubs in gcc/config/mips/mips16.S for
5227 This function implements the SKIP_TRAMPOLINE_CODE macro.
5231 mips_skip_stub (CORE_ADDR pc)
5234 CORE_ADDR start_addr;
5236 /* Find the starting address and name of the function containing the PC. */
5237 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5240 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5241 target PC is in $31 ($ra). */
5242 if (strcmp (name, "__mips16_ret_sf") == 0
5243 || strcmp (name, "__mips16_ret_df") == 0)
5244 return read_signed_register (RA_REGNUM);
5246 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5248 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5249 and the target PC is in $2. */
5250 if (name[19] >= '0' && name[19] <= '9')
5251 return read_signed_register (2);
5253 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5254 before the jal instruction, this is effectively a call stub
5255 and the the target PC is in $2. Otherwise this is effectively
5256 a return stub and the target PC is in $18. */
5257 else if (name[19] == 's' || name[19] == 'd')
5259 if (pc == start_addr)
5261 /* Check if the target of the stub is a compiler-generated
5262 stub. Such a stub for a function bar might have a name
5263 like __fn_stub_bar, and might look like this:
5268 la $1,bar (becomes a lui/addiu pair)
5270 So scan down to the lui/addi and extract the target
5271 address from those two instructions. */
5273 CORE_ADDR target_pc = read_signed_register (2);
5277 /* See if the name of the target function is __fn_stub_*. */
5278 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
5280 if (strncmp (name, "__fn_stub_", 10) != 0
5281 && strcmp (name, "etext") != 0
5282 && strcmp (name, "_etext") != 0)
5285 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5286 The limit on the search is arbitrarily set to 20
5287 instructions. FIXME. */
5288 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5290 inst = mips_fetch_instruction (target_pc);
5291 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5292 pc = (inst << 16) & 0xffff0000; /* high word */
5293 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5294 return pc | (inst & 0xffff); /* low word */
5297 /* Couldn't find the lui/addui pair, so return stub address. */
5301 /* This is the 'return' part of a call stub. The return
5302 address is in $r18. */
5303 return read_signed_register (18);
5306 return 0; /* not a stub */
5310 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5311 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5314 mips_in_call_stub (CORE_ADDR pc, char *name)
5316 CORE_ADDR start_addr;
5318 /* Find the starting address of the function containing the PC. If the
5319 caller didn't give us a name, look it up at the same time. */
5320 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
5323 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5325 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5326 if (name[19] >= '0' && name[19] <= '9')
5328 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5329 before the jal instruction, this is effectively a call stub. */
5330 else if (name[19] == 's' || name[19] == 'd')
5331 return pc == start_addr;
5334 return 0; /* not a stub */
5338 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5339 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5342 mips_in_return_stub (CORE_ADDR pc, char *name)
5344 CORE_ADDR start_addr;
5346 /* Find the starting address of the function containing the PC. */
5347 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5350 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5351 if (strcmp (name, "__mips16_ret_sf") == 0
5352 || strcmp (name, "__mips16_ret_df") == 0)
5355 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5356 i.e. after the jal instruction, this is effectively a return stub. */
5357 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5358 && (name[19] == 's' || name[19] == 'd')
5359 && pc != start_addr)
5362 return 0; /* not a stub */
5366 /* Return non-zero if the PC is in a library helper function that should
5367 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5370 mips_ignore_helper (CORE_ADDR pc)
5374 /* Find the starting address and name of the function containing the PC. */
5375 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5378 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5379 that we want to ignore. */
5380 return (strcmp (name, "__mips16_ret_sf") == 0
5381 || strcmp (name, "__mips16_ret_df") == 0);
5385 /* Return a location where we can set a breakpoint that will be hit
5386 when an inferior function call returns. This is normally the
5387 program's entry point. Executables that don't have an entry
5388 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
5389 whose address is the location where the breakpoint should be placed. */
5392 mips_call_dummy_address (void)
5394 struct minimal_symbol *sym;
5396 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
5398 return SYMBOL_VALUE_ADDRESS (sym);
5400 return entry_point_address ();
5404 /* If the current gcc for this target does not produce correct debugging
5405 information for float parameters, both prototyped and unprototyped, then
5406 define this macro. This forces gdb to always assume that floats are
5407 passed as doubles and then converted in the callee.
5409 For the mips chip, it appears that the debug info marks the parameters as
5410 floats regardless of whether the function is prototyped, but the actual
5411 values are passed as doubles for the non-prototyped case and floats for
5412 the prototyped case. Thus we choose to make the non-prototyped case work
5413 for C and break the prototyped case, since the non-prototyped case is
5414 probably much more common. (FIXME). */
5417 mips_coerce_float_to_double (struct type *formal, struct type *actual)
5419 return current_language->la_language == language_c;
5422 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5423 the register stored on the stack (32) is different to its real raw
5424 size (64). The below ensures that registers are fetched from the
5425 stack using their ABI size and then stored into the RAW_BUFFER
5426 using their raw size.
5428 The alternative to adding this function would be to add an ABI
5429 macro - REGISTER_STACK_SIZE(). */
5432 mips_get_saved_register (char *raw_buffer,
5435 struct frame_info *frame,
5437 enum lval_type *lval)
5441 if (!target_has_registers)
5442 error ("No registers.");
5444 /* Normal systems don't optimize out things with register numbers. */
5445 if (optimized != NULL)
5447 addr = find_saved_register (frame, regnum);
5451 *lval = lval_memory;
5452 if (regnum == SP_REGNUM)
5454 if (raw_buffer != NULL)
5456 /* Put it back in target format. */
5457 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
5464 if (raw_buffer != NULL)
5468 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
5470 val = read_memory_integer (addr, MIPS_SAVED_REGSIZE);
5472 val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum));
5473 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
5479 *lval = lval_register;
5480 addr = REGISTER_BYTE (regnum);
5481 if (raw_buffer != NULL)
5482 read_register_gen (regnum, raw_buffer);
5488 /* Immediately after a function call, return the saved pc.
5489 Can't always go through the frames for this because on some machines
5490 the new frame is not set up until the new function executes
5491 some instructions. */
5494 mips_saved_pc_after_call (struct frame_info *frame)
5496 return read_signed_register (RA_REGNUM);
5500 /* Convert a dbx stab register number (from `r' declaration) to a gdb
5504 mips_stab_reg_to_regnum (int num)
5509 return num + FP0_REGNUM - 38;
5512 /* Convert a ecoff register number to a gdb REGNUM */
5515 mips_ecoff_reg_to_regnum (int num)
5520 return num + FP0_REGNUM - 32;
5523 /* Convert an integer into an address. By first converting the value
5524 into a pointer and then extracting it signed, the address is
5525 guarenteed to be correctly sign extended. */
5528 mips_integer_to_address (struct type *type, void *buf)
5530 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5531 LONGEST val = unpack_long (type, buf);
5532 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5533 return extract_signed_integer (tmp,
5534 TYPE_LENGTH (builtin_type_void_data_ptr));
5538 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5540 enum mips_abi *abip = (enum mips_abi *) obj;
5541 const char *name = bfd_get_section_name (abfd, sect);
5543 if (*abip != MIPS_ABI_UNKNOWN)
5546 if (strncmp (name, ".mdebug.", 8) != 0)
5549 if (strcmp (name, ".mdebug.abi32") == 0)
5550 *abip = MIPS_ABI_O32;
5551 else if (strcmp (name, ".mdebug.abiN32") == 0)
5552 *abip = MIPS_ABI_N32;
5553 else if (strcmp (name, ".mdebug.abiN64") == 0)
5554 *abip = MIPS_ABI_N64;
5555 else if (strcmp (name, ".mdebug.abiO64") == 0)
5556 *abip = MIPS_ABI_O64;
5557 else if (strcmp (name, ".mdebug.eabi32") == 0)
5558 *abip = MIPS_ABI_EABI32;
5559 else if (strcmp (name, ".mdebug.eabi64") == 0)
5560 *abip = MIPS_ABI_EABI64;
5562 warning ("unsupported ABI %s.", name + 8);
5565 static enum mips_abi
5566 global_mips_abi (void)
5570 for (i = 0; mips_abi_strings[i] != NULL; i++)
5571 if (mips_abi_strings[i] == mips_abi_string)
5572 return (enum mips_abi) i;
5574 internal_error (__FILE__, __LINE__,
5575 "unknown ABI string");
5578 static struct gdbarch *
5579 mips_gdbarch_init (struct gdbarch_info info,
5580 struct gdbarch_list *arches)
5582 static LONGEST mips_call_dummy_words[] =
5584 struct gdbarch *gdbarch;
5585 struct gdbarch_tdep *tdep;
5587 enum mips_abi mips_abi, found_abi, wanted_abi;
5588 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
5590 /* Reset the disassembly info, in case it was set to something
5592 tm_print_insn_info.flavour = bfd_target_unknown_flavour;
5593 tm_print_insn_info.arch = bfd_arch_unknown;
5594 tm_print_insn_info.mach = 0;
5600 /* First of all, extract the elf_flags, if available. */
5601 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5602 elf_flags = elf_elfheader (info.abfd)->e_flags;
5604 /* Try to determine the OS ABI of the object we are loading. If
5605 we end up with `unknown', just leave it that way. */
5606 osabi = gdbarch_lookup_osabi (info.abfd);
5609 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5610 switch ((elf_flags & EF_MIPS_ABI))
5612 case E_MIPS_ABI_O32:
5613 mips_abi = MIPS_ABI_O32;
5615 case E_MIPS_ABI_O64:
5616 mips_abi = MIPS_ABI_O64;
5618 case E_MIPS_ABI_EABI32:
5619 mips_abi = MIPS_ABI_EABI32;
5621 case E_MIPS_ABI_EABI64:
5622 mips_abi = MIPS_ABI_EABI64;
5625 if ((elf_flags & EF_MIPS_ABI2))
5626 mips_abi = MIPS_ABI_N32;
5628 mips_abi = MIPS_ABI_UNKNOWN;
5632 /* GCC creates a pseudo-section whose name describes the ABI. */
5633 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5634 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
5636 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5637 Use the ABI from the last architecture if there is one. */
5638 if (info.abfd == NULL && arches != NULL)
5639 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5641 /* Try the architecture for any hint of the correct ABI. */
5642 if (mips_abi == MIPS_ABI_UNKNOWN
5643 && info.bfd_arch_info != NULL
5644 && info.bfd_arch_info->arch == bfd_arch_mips)
5646 switch (info.bfd_arch_info->mach)
5648 case bfd_mach_mips3900:
5649 mips_abi = MIPS_ABI_EABI32;
5651 case bfd_mach_mips4100:
5652 case bfd_mach_mips5000:
5653 mips_abi = MIPS_ABI_EABI64;
5655 case bfd_mach_mips8000:
5656 case bfd_mach_mips10000:
5657 /* On Irix, ELF64 executables use the N64 ABI. The
5658 pseudo-sections which describe the ABI aren't present
5659 on IRIX. (Even for executables created by gcc.) */
5660 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5661 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5662 mips_abi = MIPS_ABI_N64;
5664 mips_abi = MIPS_ABI_N32;
5669 if (mips_abi == MIPS_ABI_UNKNOWN)
5670 mips_abi = MIPS_ABI_O32;
5672 /* Now that we have found what the ABI for this binary would be,
5673 check whether the user is overriding it. */
5674 found_abi = mips_abi;
5675 wanted_abi = global_mips_abi ();
5676 if (wanted_abi != MIPS_ABI_UNKNOWN)
5677 mips_abi = wanted_abi;
5681 fprintf_unfiltered (gdb_stdlog,
5682 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5684 fprintf_unfiltered (gdb_stdlog,
5685 "mips_gdbarch_init: mips_abi = %d\n",
5687 fprintf_unfiltered (gdb_stdlog,
5688 "mips_gdbarch_init: found_mips_abi = %d\n",
5692 /* try to find a pre-existing architecture */
5693 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5695 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5697 /* MIPS needs to be pedantic about which ABI the object is
5699 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5701 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5703 if (gdbarch_tdep (arches->gdbarch)->osabi == osabi)
5704 return arches->gdbarch;
5707 /* Need a new architecture. Fill in a target specific vector. */
5708 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5709 gdbarch = gdbarch_alloc (&info, tdep);
5710 tdep->elf_flags = elf_flags;
5711 tdep->osabi = osabi;
5713 /* Initially set everything according to the default ABI/ISA. */
5714 set_gdbarch_short_bit (gdbarch, 16);
5715 set_gdbarch_int_bit (gdbarch, 32);
5716 set_gdbarch_float_bit (gdbarch, 32);
5717 set_gdbarch_double_bit (gdbarch, 64);
5718 set_gdbarch_long_double_bit (gdbarch, 64);
5719 set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size);
5720 set_gdbarch_max_register_raw_size (gdbarch, 8);
5721 set_gdbarch_max_register_virtual_size (gdbarch, 8);
5722 tdep->found_abi = found_abi;
5723 tdep->mips_abi = mips_abi;
5725 set_gdbarch_elf_make_msymbol_special (gdbarch,
5726 mips_elf_make_msymbol_special);
5731 set_gdbarch_push_arguments (gdbarch, mips_o32_push_arguments);
5732 set_gdbarch_store_return_value (gdbarch, mips_o32_store_return_value);
5733 set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value);
5734 tdep->mips_default_saved_regsize = 4;
5735 tdep->mips_default_stack_argsize = 4;
5736 tdep->mips_fp_register_double = 0;
5737 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5738 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5739 tdep->gdb_target_is_mips64 = 0;
5740 tdep->default_mask_address_p = 0;
5741 set_gdbarch_long_bit (gdbarch, 32);
5742 set_gdbarch_ptr_bit (gdbarch, 32);
5743 set_gdbarch_long_long_bit (gdbarch, 64);
5744 set_gdbarch_reg_struct_has_addr (gdbarch,
5745 mips_o32_reg_struct_has_addr);
5746 set_gdbarch_use_struct_convention (gdbarch,
5747 mips_o32_use_struct_convention);
5750 set_gdbarch_push_arguments (gdbarch, mips_o64_push_arguments);
5751 set_gdbarch_store_return_value (gdbarch, mips_o64_store_return_value);
5752 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value);
5753 tdep->mips_default_saved_regsize = 8;
5754 tdep->mips_default_stack_argsize = 8;
5755 tdep->mips_fp_register_double = 1;
5756 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5757 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5758 tdep->gdb_target_is_mips64 = 1;
5759 tdep->default_mask_address_p = 0;
5760 set_gdbarch_long_bit (gdbarch, 32);
5761 set_gdbarch_ptr_bit (gdbarch, 32);
5762 set_gdbarch_long_long_bit (gdbarch, 64);
5763 set_gdbarch_reg_struct_has_addr (gdbarch,
5764 mips_o32_reg_struct_has_addr);
5765 set_gdbarch_use_struct_convention (gdbarch,
5766 mips_o32_use_struct_convention);
5768 case MIPS_ABI_EABI32:
5769 set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments);
5770 set_gdbarch_store_return_value (gdbarch, mips_eabi_store_return_value);
5771 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5772 tdep->mips_default_saved_regsize = 4;
5773 tdep->mips_default_stack_argsize = 4;
5774 tdep->mips_fp_register_double = 0;
5775 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5776 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5777 tdep->gdb_target_is_mips64 = 0;
5778 tdep->default_mask_address_p = 0;
5779 set_gdbarch_long_bit (gdbarch, 32);
5780 set_gdbarch_ptr_bit (gdbarch, 32);
5781 set_gdbarch_long_long_bit (gdbarch, 64);
5782 set_gdbarch_reg_struct_has_addr (gdbarch,
5783 mips_eabi_reg_struct_has_addr);
5784 set_gdbarch_use_struct_convention (gdbarch,
5785 mips_eabi_use_struct_convention);
5787 case MIPS_ABI_EABI64:
5788 set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments);
5789 set_gdbarch_store_return_value (gdbarch, mips_eabi_store_return_value);
5790 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5791 tdep->mips_default_saved_regsize = 8;
5792 tdep->mips_default_stack_argsize = 8;
5793 tdep->mips_fp_register_double = 1;
5794 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5795 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5796 tdep->gdb_target_is_mips64 = 1;
5797 tdep->default_mask_address_p = 0;
5798 set_gdbarch_long_bit (gdbarch, 64);
5799 set_gdbarch_ptr_bit (gdbarch, 64);
5800 set_gdbarch_long_long_bit (gdbarch, 64);
5801 set_gdbarch_reg_struct_has_addr (gdbarch,
5802 mips_eabi_reg_struct_has_addr);
5803 set_gdbarch_use_struct_convention (gdbarch,
5804 mips_eabi_use_struct_convention);
5807 set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments);
5808 set_gdbarch_store_return_value (gdbarch, mips_n32n64_store_return_value);
5809 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5810 tdep->mips_default_saved_regsize = 8;
5811 tdep->mips_default_stack_argsize = 8;
5812 tdep->mips_fp_register_double = 1;
5813 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5814 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5815 tdep->gdb_target_is_mips64 = 1;
5816 tdep->default_mask_address_p = 0;
5817 set_gdbarch_long_bit (gdbarch, 32);
5818 set_gdbarch_ptr_bit (gdbarch, 32);
5819 set_gdbarch_long_long_bit (gdbarch, 64);
5821 /* Set up the disassembler info, so that we get the right
5822 register names from libopcodes. */
5823 tm_print_insn_info.flavour = bfd_target_elf_flavour;
5824 tm_print_insn_info.arch = bfd_arch_mips;
5825 if (info.bfd_arch_info != NULL
5826 && info.bfd_arch_info->arch == bfd_arch_mips
5827 && info.bfd_arch_info->mach)
5828 tm_print_insn_info.mach = info.bfd_arch_info->mach;
5830 tm_print_insn_info.mach = bfd_mach_mips8000;
5832 set_gdbarch_use_struct_convention (gdbarch,
5833 mips_n32n64_use_struct_convention);
5834 set_gdbarch_reg_struct_has_addr (gdbarch,
5835 mips_n32n64_reg_struct_has_addr);
5838 set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments);
5839 set_gdbarch_store_return_value (gdbarch, mips_n32n64_store_return_value);
5840 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5841 tdep->mips_default_saved_regsize = 8;
5842 tdep->mips_default_stack_argsize = 8;
5843 tdep->mips_fp_register_double = 1;
5844 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5845 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5846 tdep->gdb_target_is_mips64 = 1;
5847 tdep->default_mask_address_p = 0;
5848 set_gdbarch_long_bit (gdbarch, 64);
5849 set_gdbarch_ptr_bit (gdbarch, 64);
5850 set_gdbarch_long_long_bit (gdbarch, 64);
5852 /* Set up the disassembler info, so that we get the right
5853 register names from libopcodes. */
5854 tm_print_insn_info.flavour = bfd_target_elf_flavour;
5855 tm_print_insn_info.arch = bfd_arch_mips;
5856 if (info.bfd_arch_info != NULL
5857 && info.bfd_arch_info->arch == bfd_arch_mips
5858 && info.bfd_arch_info->mach)
5859 tm_print_insn_info.mach = info.bfd_arch_info->mach;
5861 tm_print_insn_info.mach = bfd_mach_mips8000;
5863 set_gdbarch_use_struct_convention (gdbarch,
5864 mips_n32n64_use_struct_convention);
5865 set_gdbarch_reg_struct_has_addr (gdbarch,
5866 mips_n32n64_reg_struct_has_addr);
5869 internal_error (__FILE__, __LINE__,
5870 "unknown ABI in switch");
5873 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5874 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5877 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5878 flag in object files because to do so would make it impossible to
5879 link with libraries compiled without "-gp32". This is
5880 unnecessarily restrictive.
5882 We could solve this problem by adding "-gp32" multilibs to gcc,
5883 but to set this flag before gcc is built with such multilibs will
5884 break too many systems.''
5886 But even more unhelpfully, the default linker output target for
5887 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5888 for 64-bit programs - you need to change the ABI to change this,
5889 and not all gcc targets support that currently. Therefore using
5890 this flag to detect 32-bit mode would do the wrong thing given
5891 the current gcc - it would make GDB treat these 64-bit programs
5892 as 32-bit programs by default. */
5894 /* enable/disable the MIPS FPU */
5895 if (!mips_fpu_type_auto)
5896 tdep->mips_fpu_type = mips_fpu_type;
5897 else if (info.bfd_arch_info != NULL
5898 && info.bfd_arch_info->arch == bfd_arch_mips)
5899 switch (info.bfd_arch_info->mach)
5901 case bfd_mach_mips3900:
5902 case bfd_mach_mips4100:
5903 case bfd_mach_mips4111:
5904 tdep->mips_fpu_type = MIPS_FPU_NONE;
5906 case bfd_mach_mips4650:
5907 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
5910 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5914 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5916 /* MIPS version of register names. NOTE: At present the MIPS
5917 register name management is part way between the old -
5918 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5919 Further work on it is required. */
5920 set_gdbarch_register_name (gdbarch, mips_register_name);
5921 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5922 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
5923 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
5924 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5925 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
5927 /* Add/remove bits from an address. The MIPS needs be careful to
5928 ensure that all 32 bit addresses are sign extended to 64 bits. */
5929 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5931 /* There's a mess in stack frame creation. See comments in
5932 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
5933 set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
5934 set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop);
5936 /* Map debug register numbers onto internal register numbers. */
5937 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5938 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum);
5940 /* Initialize a frame */
5941 set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
5942 set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs);
5944 /* MIPS version of CALL_DUMMY */
5946 set_gdbarch_call_dummy_p (gdbarch, 1);
5947 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
5948 set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
5949 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
5950 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
5951 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
5952 set_gdbarch_push_dummy_frame (gdbarch, mips_push_dummy_frame);
5953 set_gdbarch_pop_frame (gdbarch, mips_pop_frame);
5954 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
5955 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
5956 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
5957 set_gdbarch_call_dummy_length (gdbarch, 0);
5958 set_gdbarch_fix_call_dummy (gdbarch, mips_fix_call_dummy);
5959 set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
5960 set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
5961 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
5962 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
5963 set_gdbarch_register_convertible (gdbarch, mips_register_convertible);
5964 set_gdbarch_register_convert_to_virtual (gdbarch,
5965 mips_register_convert_to_virtual);
5966 set_gdbarch_register_convert_to_raw (gdbarch,
5967 mips_register_convert_to_raw);
5969 set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double);
5971 set_gdbarch_frame_chain (gdbarch, mips_frame_chain);
5972 set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
5973 set_gdbarch_frameless_function_invocation (gdbarch,
5974 generic_frameless_function_invocation_not);
5975 set_gdbarch_frame_saved_pc (gdbarch, mips_frame_saved_pc);
5976 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
5977 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
5978 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
5979 set_gdbarch_frame_args_skip (gdbarch, 0);
5981 set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
5983 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5984 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5985 set_gdbarch_decr_pc_after_break (gdbarch, 0);
5987 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5988 set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
5990 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5991 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5992 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5994 set_gdbarch_function_start_offset (gdbarch, 0);
5996 /* There are MIPS targets which do not yet use this since they still
5997 define REGISTER_VIRTUAL_TYPE. */
5998 set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type);
5999 set_gdbarch_register_virtual_size (gdbarch, generic_register_size);
6001 set_gdbarch_do_registers_info (gdbarch, mips_do_registers_info);
6002 set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp);
6004 /* Hook in OS ABI-specific overrides, if they have been registered. */
6005 gdbarch_init_osabi (info, gdbarch, osabi);
6007 set_gdbarch_store_struct_return (gdbarch, mips_store_struct_return);
6008 set_gdbarch_extract_struct_value_address (gdbarch,
6009 mips_extract_struct_value_address);
6011 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
6013 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
6014 /* set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); */
6020 mips_abi_update (char *ignore_args, int from_tty,
6021 struct cmd_list_element *c)
6023 struct gdbarch_info info;
6025 /* Force the architecture to update, and (if it's a MIPS architecture)
6026 mips_gdbarch_init will take care of the rest. */
6027 gdbarch_info_init (&info);
6028 gdbarch_update_p (info);
6032 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
6034 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
6038 int ef_mips_32bitmode;
6039 /* determine the ISA */
6040 switch (tdep->elf_flags & EF_MIPS_ARCH)
6058 /* determine the size of a pointer */
6059 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6060 fprintf_unfiltered (file,
6061 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6063 fprintf_unfiltered (file,
6064 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6066 fprintf_unfiltered (file,
6067 "mips_dump_tdep: ef_mips_arch = %d\n",
6069 fprintf_unfiltered (file,
6070 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6072 mips_abi_strings[tdep->mips_abi]);
6073 fprintf_unfiltered (file,
6074 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6075 mips_mask_address_p (),
6076 tdep->default_mask_address_p);
6078 fprintf_unfiltered (file,
6079 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6080 FP_REGISTER_DOUBLE);
6081 fprintf_unfiltered (file,
6082 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6083 MIPS_DEFAULT_FPU_TYPE,
6084 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6085 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6086 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6088 fprintf_unfiltered (file,
6089 "mips_dump_tdep: MIPS_EABI = %d\n",
6091 fprintf_unfiltered (file,
6092 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6093 MIPS_LAST_FP_ARG_REGNUM,
6094 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
6095 fprintf_unfiltered (file,
6096 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6098 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
6099 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6100 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6102 fprintf_unfiltered (file,
6103 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6104 MIPS_DEFAULT_SAVED_REGSIZE);
6105 fprintf_unfiltered (file,
6106 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6107 FP_REGISTER_DOUBLE);
6108 fprintf_unfiltered (file,
6109 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6110 MIPS_DEFAULT_STACK_ARGSIZE);
6111 fprintf_unfiltered (file,
6112 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6113 MIPS_STACK_ARGSIZE);
6114 fprintf_unfiltered (file,
6115 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
6117 fprintf_unfiltered (file,
6118 "mips_dump_tdep: A0_REGNUM = %d\n",
6120 fprintf_unfiltered (file,
6121 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6122 XSTRING (ADDR_BITS_REMOVE(ADDR)));
6123 fprintf_unfiltered (file,
6124 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6125 XSTRING (ATTACH_DETACH));
6126 fprintf_unfiltered (file,
6127 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6129 fprintf_unfiltered (file,
6130 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
6131 fprintf_unfiltered (file,
6132 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6134 fprintf_unfiltered (file,
6135 "mips_dump_tdep: CPLUS_MARKER = %c\n",
6137 fprintf_unfiltered (file,
6138 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
6140 fprintf_unfiltered (file,
6141 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
6142 XSTRING (DO_REGISTERS_INFO));
6143 fprintf_unfiltered (file,
6144 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6145 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
6146 fprintf_unfiltered (file,
6147 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6148 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
6149 fprintf_unfiltered (file,
6150 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
6151 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM)));
6152 fprintf_unfiltered (file,
6153 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6155 fprintf_unfiltered (file,
6156 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6158 fprintf_unfiltered (file,
6159 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6160 FIRST_EMBED_REGNUM);
6161 fprintf_unfiltered (file,
6162 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6164 fprintf_unfiltered (file,
6165 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6166 GDB_TARGET_IS_MIPS64);
6167 fprintf_unfiltered (file,
6168 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
6169 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC)));
6170 fprintf_unfiltered (file,
6171 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
6172 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC)));
6173 fprintf_unfiltered (file,
6174 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
6176 fprintf_unfiltered (file,
6177 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
6178 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
6179 fprintf_unfiltered (file,
6180 "mips_dump_tdep: HI_REGNUM = %d\n",
6182 fprintf_unfiltered (file,
6183 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
6184 fprintf_unfiltered (file,
6185 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
6186 fprintf_unfiltered (file,
6187 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6188 XSTRING (IGNORE_HELPER_CALL (PC)));
6189 fprintf_unfiltered (file,
6190 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6191 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
6192 fprintf_unfiltered (file,
6193 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6194 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
6195 fprintf_unfiltered (file,
6196 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
6197 fprintf_unfiltered (file,
6198 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6200 fprintf_unfiltered (file,
6201 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
6202 fprintf_unfiltered (file,
6203 "mips_dump_tdep: LO_REGNUM = %d\n",
6205 #ifdef MACHINE_CPROC_FP_OFFSET
6206 fprintf_unfiltered (file,
6207 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6208 MACHINE_CPROC_FP_OFFSET);
6210 #ifdef MACHINE_CPROC_PC_OFFSET
6211 fprintf_unfiltered (file,
6212 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6213 MACHINE_CPROC_PC_OFFSET);
6215 #ifdef MACHINE_CPROC_SP_OFFSET
6216 fprintf_unfiltered (file,
6217 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6218 MACHINE_CPROC_SP_OFFSET);
6220 fprintf_unfiltered (file,
6221 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
6222 fprintf_unfiltered (file,
6223 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
6224 fprintf_unfiltered (file,
6225 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6227 fprintf_unfiltered (file,
6228 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
6229 fprintf_unfiltered (file,
6230 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6231 fprintf_unfiltered (file,
6232 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6233 fprintf_unfiltered (file,
6234 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6236 fprintf_unfiltered (file,
6237 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6238 MIPS_LAST_ARG_REGNUM,
6239 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
6240 fprintf_unfiltered (file,
6241 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6243 fprintf_unfiltered (file,
6244 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6245 fprintf_unfiltered (file,
6246 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6247 MIPS_SAVED_REGSIZE);
6248 fprintf_unfiltered (file,
6249 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
6250 fprintf_unfiltered (file,
6251 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
6252 XSTRING (MSYMBOL_SIZE (MSYM)));
6253 fprintf_unfiltered (file,
6254 "mips_dump_tdep: OP_LDFPR = used?\n");
6255 fprintf_unfiltered (file,
6256 "mips_dump_tdep: OP_LDGPR = used?\n");
6257 fprintf_unfiltered (file,
6258 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
6259 fprintf_unfiltered (file,
6260 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
6261 fprintf_unfiltered (file,
6262 "mips_dump_tdep: PRID_REGNUM = %d\n",
6264 fprintf_unfiltered (file,
6265 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
6266 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
6267 fprintf_unfiltered (file,
6268 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6269 fprintf_unfiltered (file,
6270 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6271 fprintf_unfiltered (file,
6272 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6273 fprintf_unfiltered (file,
6274 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6275 fprintf_unfiltered (file,
6276 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6277 fprintf_unfiltered (file,
6278 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6279 fprintf_unfiltered (file,
6280 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6281 fprintf_unfiltered (file,
6282 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6283 fprintf_unfiltered (file,
6284 "mips_dump_tdep: PROC_PC_REG = function?\n");
6285 fprintf_unfiltered (file,
6286 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6287 fprintf_unfiltered (file,
6288 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6289 fprintf_unfiltered (file,
6290 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6291 fprintf_unfiltered (file,
6292 "mips_dump_tdep: PS_REGNUM = %d\n",
6294 fprintf_unfiltered (file,
6295 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
6297 fprintf_unfiltered (file,
6298 "mips_dump_tdep: RA_REGNUM = %d\n",
6300 fprintf_unfiltered (file,
6301 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
6302 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
6303 fprintf_unfiltered (file,
6304 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
6305 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
6306 fprintf_unfiltered (file,
6307 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
6308 fprintf_unfiltered (file,
6309 "mips_dump_tdep: ROUND_DOWN = function?\n");
6310 fprintf_unfiltered (file,
6311 "mips_dump_tdep: ROUND_UP = function?\n");
6313 fprintf_unfiltered (file,
6314 "mips_dump_tdep: SAVED_BYTES = %d\n",
6318 fprintf_unfiltered (file,
6319 "mips_dump_tdep: SAVED_FP = %d\n",
6323 fprintf_unfiltered (file,
6324 "mips_dump_tdep: SAVED_PC = %d\n",
6327 fprintf_unfiltered (file,
6328 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6329 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
6330 fprintf_unfiltered (file,
6331 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6332 fprintf_unfiltered (file,
6333 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6335 fprintf_unfiltered (file,
6336 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6337 SIGFRAME_FPREGSAVE_OFF);
6338 fprintf_unfiltered (file,
6339 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6341 fprintf_unfiltered (file,
6342 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6343 SIGFRAME_REGSAVE_OFF);
6344 fprintf_unfiltered (file,
6345 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6347 fprintf_unfiltered (file,
6348 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6349 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
6350 fprintf_unfiltered (file,
6351 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6352 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
6353 fprintf_unfiltered (file,
6354 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6355 SOFTWARE_SINGLE_STEP_P ());
6356 fprintf_unfiltered (file,
6357 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6358 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6359 #ifdef STACK_END_ADDR
6360 fprintf_unfiltered (file,
6361 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6364 fprintf_unfiltered (file,
6365 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6366 XSTRING (STEP_SKIPS_DELAY (PC)));
6367 fprintf_unfiltered (file,
6368 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6369 STEP_SKIPS_DELAY_P);
6370 fprintf_unfiltered (file,
6371 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6372 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6373 fprintf_unfiltered (file,
6374 "mips_dump_tdep: T9_REGNUM = %d\n",
6376 fprintf_unfiltered (file,
6377 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6378 fprintf_unfiltered (file,
6379 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6380 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
6381 fprintf_unfiltered (file,
6382 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6383 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
6384 fprintf_unfiltered (file,
6385 "mips_dump_tdep: TARGET_MIPS = used?\n");
6386 fprintf_unfiltered (file,
6387 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
6388 XSTRING (TM_PRINT_INSN_MACH));
6390 fprintf_unfiltered (file,
6391 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6392 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6395 fprintf_unfiltered (file,
6396 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6399 #ifdef TRACE_FLAVOR_SIZE
6400 fprintf_unfiltered (file,
6401 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6405 fprintf_unfiltered (file,
6406 "mips_dump_tdep: TRACE_SET # %s\n",
6407 XSTRING (TRACE_SET (X,STATE)));
6409 fprintf_unfiltered (file,
6410 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
6411 #ifdef UNUSED_REGNUM
6412 fprintf_unfiltered (file,
6413 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6416 fprintf_unfiltered (file,
6417 "mips_dump_tdep: V0_REGNUM = %d\n",
6419 fprintf_unfiltered (file,
6420 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6421 (long) VM_MIN_ADDRESS);
6423 fprintf_unfiltered (file,
6424 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
6427 fprintf_unfiltered (file,
6428 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6430 fprintf_unfiltered (file,
6431 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6434 fprintf_unfiltered (file,
6435 "mips_dump_tdep: OS ABI = %s\n",
6436 gdbarch_osabi_name (tdep->osabi));
6440 _initialize_mips_tdep (void)
6442 static struct cmd_list_element *mipsfpulist = NULL;
6443 struct cmd_list_element *c;
6445 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
6446 if (MIPS_ABI_LAST + 1
6447 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6448 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6450 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6451 if (!tm_print_insn) /* Someone may have already set it */
6452 tm_print_insn = gdb_print_insn_mips;
6454 /* Add root prefix command for all "set mips"/"show mips" commands */
6455 add_prefix_cmd ("mips", no_class, set_mips_command,
6456 "Various MIPS specific commands.",
6457 &setmipscmdlist, "set mips ", 0, &setlist);
6459 add_prefix_cmd ("mips", no_class, show_mips_command,
6460 "Various MIPS specific commands.",
6461 &showmipscmdlist, "show mips ", 0, &showlist);
6463 /* Allow the user to override the saved register size. */
6464 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6467 &mips_saved_regsize_string, "\
6468 Set size of general purpose registers saved on the stack.\n\
6469 This option can be set to one of:\n\
6470 32 - Force GDB to treat saved GP registers as 32-bit\n\
6471 64 - Force GDB to treat saved GP registers as 64-bit\n\
6472 auto - Allow GDB to use the target's default setting or autodetect the\n\
6473 saved GP register size from information contained in the executable.\n\
6478 /* Allow the user to override the argument stack size. */
6479 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6482 &mips_stack_argsize_string, "\
6483 Set the amount of stack space reserved for each argument.\n\
6484 This option can be set to one of:\n\
6485 32 - Force GDB to allocate 32-bit chunks per argument\n\
6486 64 - Force GDB to allocate 64-bit chunks per argument\n\
6487 auto - Allow GDB to determine the correct setting from the current\n\
6488 target and executable (default)",
6492 /* Allow the user to override the ABI. */
6493 c = add_set_enum_cmd
6494 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6495 "Set the ABI used by this program.\n"
6496 "This option can be set to one of:\n"
6497 " auto - the default ABI associated with the current binary\n"
6505 add_show_from_set (c, &showmipscmdlist);
6506 set_cmd_sfunc (c, mips_abi_update);
6508 /* Let the user turn off floating point and set the fence post for
6509 heuristic_proc_start. */
6511 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6512 "Set use of MIPS floating-point coprocessor.",
6513 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6514 add_cmd ("single", class_support, set_mipsfpu_single_command,
6515 "Select single-precision MIPS floating-point coprocessor.",
6517 add_cmd ("double", class_support, set_mipsfpu_double_command,
6518 "Select double-precision MIPS floating-point coprocessor.",
6520 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6521 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6522 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6523 add_cmd ("none", class_support, set_mipsfpu_none_command,
6524 "Select no MIPS floating-point coprocessor.",
6526 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6527 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6528 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6529 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6530 "Select MIPS floating-point coprocessor automatically.",
6532 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6533 "Show current use of MIPS floating-point coprocessor target.",
6536 /* We really would like to have both "0" and "unlimited" work, but
6537 command.c doesn't deal with that. So make it a var_zinteger
6538 because the user can always use "999999" or some such for unlimited. */
6539 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6540 (char *) &heuristic_fence_post,
6542 Set the distance searched for the start of a function.\n\
6543 If you are debugging a stripped executable, GDB needs to search through the\n\
6544 program for the start of a function. This command sets the distance of the\n\
6545 search. The only need to set it is when debugging a stripped executable.",
6547 /* We need to throw away the frame cache when we set this, since it
6548 might change our ability to get backtraces. */
6549 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
6550 add_show_from_set (c, &showlist);
6552 /* Allow the user to control whether the upper bits of 64-bit
6553 addresses should be zeroed. */
6554 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6555 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6556 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6557 allow GDB to determine the correct value.\n", "\
6558 Show zeroing of upper 32 bits of 64-bit addresses.",
6559 NULL, show_mask_address,
6560 &setmipscmdlist, &showmipscmdlist);
6562 /* Allow the user to control the size of 32 bit registers within the
6563 raw remote packet. */
6564 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6567 (char *)&mips64_transfers_32bit_regs_p, "\
6568 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6569 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6570 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6571 64 bits for others. Use \"off\" to disable compatibility mode",
6575 /* Debug this files internals. */
6576 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6577 &mips_debug, "Set mips debugging.\n\
6578 When non-zero, mips specific debugging is enabled.", &setdebuglist),