1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE = 4,
57 MIPS_FPU_DOUBLE_REGSIZE = 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string;
76 static const char *mips_abi_strings[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto[] = "auto";
98 static const char size_32[] = "32";
99 static const char size_64[] = "64";
101 static const char *size_enums[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE /* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto = 1;
123 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
125 static int mips_debug = 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi;
135 enum mips_abi found_abi;
136 enum mips_fpu_type mips_fpu_type;
137 int mips_last_arg_regnum;
138 int mips_last_fp_arg_regnum;
139 int mips_default_saved_regsize;
140 int mips_fp_register_double;
141 int mips_regs_have_home_p;
142 int mips_default_stack_argsize;
143 int gdb_target_is_mips64;
144 int default_mask_address_p;
146 enum gdb_osabi osabi;
149 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
150 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
152 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
154 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
156 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
158 /* Return the currently configured (or set) saved register size. */
160 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
162 static const char *mips_saved_regsize_string = size_auto;
164 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
167 mips_saved_regsize (void)
169 if (mips_saved_regsize_string == size_auto)
170 return MIPS_DEFAULT_SAVED_REGSIZE;
171 else if (mips_saved_regsize_string == size_64)
173 else /* if (mips_saved_regsize_string == size_32) */
177 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
178 compatiblity mode. A return value of 1 means that we have
179 physical 64-bit registers, but should treat them as 32-bit registers. */
182 mips2_fp_compat (void)
184 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
186 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
190 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
191 in all the places we deal with FP registers. PR gdb/413. */
192 /* Otherwise check the FR bit in the status register - it controls
193 the FP compatiblity mode. If it is clear we are in compatibility
195 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
202 /* Indicate that the ABI makes use of double-precision registers
203 provided by the FPU (rather than combining pairs of registers to
204 form double-precision values). Do not use "TARGET_IS_MIPS64" to
205 determine if the ABI is using double-precision registers. See also
207 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
209 /* Does the caller allocate a ``home'' for each register used in the
210 function call? The N32 ABI and MIPS_EABI do not, the others do. */
212 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
214 /* The amount of space reserved on the stack for registers. This is
215 different to MIPS_SAVED_REGSIZE as it determines the alignment of
216 data allocated after the registers have run out. */
218 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
220 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
222 static const char *mips_stack_argsize_string = size_auto;
225 mips_stack_argsize (void)
227 if (mips_stack_argsize_string == size_auto)
228 return MIPS_DEFAULT_STACK_ARGSIZE;
229 else if (mips_stack_argsize_string == size_64)
231 else /* if (mips_stack_argsize_string == size_32) */
235 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
237 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
239 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
241 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
243 static void mips_print_register (int, int);
245 static mips_extra_func_info_t
246 heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int);
248 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
250 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
252 int mips_set_processor_type (char *);
254 static void mips_show_processor_type_command (char *, int);
256 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
258 static mips_extra_func_info_t
259 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame);
261 static CORE_ADDR after_prologue (CORE_ADDR pc,
262 mips_extra_func_info_t proc_desc);
264 static void mips_read_fp_register_single (int regno, char *rare_buffer);
265 static void mips_read_fp_register_double (int regno, char *rare_buffer);
267 static struct type *mips_float_register_type (void);
268 static struct type *mips_double_register_type (void);
270 /* This value is the model of MIPS in use. It is derived from the value
271 of the PrID register. */
273 char *mips_processor_type;
275 char *tmp_mips_processor_type;
277 /* The list of available "set mips " and "show mips " commands */
279 static struct cmd_list_element *setmipscmdlist = NULL;
280 static struct cmd_list_element *showmipscmdlist = NULL;
282 /* A set of original names, to be used when restoring back to generic
283 registers from a specific set. */
285 char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
286 char **mips_processor_reg_names = mips_generic_reg_names;
289 mips_register_name (int i)
291 return mips_processor_reg_names[i];
294 /* Names of IDT R3041 registers. */
296 char *mips_r3041_reg_names[] = {
297 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
298 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
299 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
300 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
301 "sr", "lo", "hi", "bad", "cause","pc",
302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
306 "fsr", "fir", "fp", "",
307 "", "", "bus", "ccfg", "", "", "", "",
308 "", "", "port", "cmp", "", "", "epc", "prid",
311 /* Names of IDT R3051 registers. */
313 char *mips_r3051_reg_names[] = {
314 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
315 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
316 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
317 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
318 "sr", "lo", "hi", "bad", "cause","pc",
319 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
320 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
321 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
322 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
323 "fsr", "fir", "fp", "",
324 "inx", "rand", "elo", "", "ctxt", "", "", "",
325 "", "", "ehi", "", "", "", "epc", "prid",
328 /* Names of IDT R3081 registers. */
330 char *mips_r3081_reg_names[] = {
331 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
332 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
333 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
334 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
335 "sr", "lo", "hi", "bad", "cause","pc",
336 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
337 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
338 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
339 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
340 "fsr", "fir", "fp", "",
341 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
342 "", "", "ehi", "", "", "", "epc", "prid",
345 /* Names of LSI 33k registers. */
347 char *mips_lsi33k_reg_names[] = {
348 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
349 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
350 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
351 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
352 "epc", "hi", "lo", "sr", "cause","badvaddr",
353 "dcic", "bpc", "bda", "", "", "", "", "",
354 "", "", "", "", "", "", "", "",
355 "", "", "", "", "", "", "", "",
356 "", "", "", "", "", "", "", "",
358 "", "", "", "", "", "", "", "",
359 "", "", "", "", "", "", "", "",
365 } mips_processor_type_table[] = {
366 { "generic", mips_generic_reg_names },
367 { "r3041", mips_r3041_reg_names },
368 { "r3051", mips_r3051_reg_names },
369 { "r3071", mips_r3081_reg_names },
370 { "r3081", mips_r3081_reg_names },
371 { "lsi33k", mips_lsi33k_reg_names },
379 /* Table to translate MIPS16 register field to actual register number. */
380 static int mips16_to_32_reg[8] =
381 {16, 17, 2, 3, 4, 5, 6, 7};
383 /* Heuristic_proc_start may hunt through the text section for a long
384 time across a 2400 baud serial line. Allows the user to limit this
387 static unsigned int heuristic_fence_post = 0;
389 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
390 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
391 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
392 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
393 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
394 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
395 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
396 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
397 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
398 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
399 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
400 this will corrupt pdr.iline. Fortunately we don't use it. */
401 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
402 #define _PROC_MAGIC_ 0x0F0F0F0F
403 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
404 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
406 struct linked_proc_info
408 struct mips_extra_func_info info;
409 struct linked_proc_info *next;
411 *linked_proc_desc_table = NULL;
414 mips_print_extra_frame_info (struct frame_info *fi)
418 && fi->extra_info->proc_desc
419 && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS)
420 printf_filtered (" frame pointer is at %s+%s\n",
421 REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg),
422 paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
425 /* Number of bytes of storage in the actual machine representation for
426 register N. NOTE: This indirectly defines the register size
427 transfered by the GDB protocol. */
429 static int mips64_transfers_32bit_regs_p = 0;
432 mips_register_raw_size (int reg_nr)
434 if (mips64_transfers_32bit_regs_p)
435 return REGISTER_VIRTUAL_SIZE (reg_nr);
436 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
437 && FP_REGISTER_DOUBLE)
438 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
445 /* Convert between RAW and VIRTUAL registers. The RAW register size
446 defines the remote-gdb packet. */
449 mips_register_convertible (int reg_nr)
451 if (mips64_transfers_32bit_regs_p)
454 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
458 mips_register_convert_to_virtual (int n, struct type *virtual_type,
459 char *raw_buf, char *virt_buf)
461 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
463 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
464 TYPE_LENGTH (virtual_type));
468 TYPE_LENGTH (virtual_type));
472 mips_register_convert_to_raw (struct type *virtual_type, int n,
473 char *virt_buf, char *raw_buf)
475 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
476 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
477 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
479 TYPE_LENGTH (virtual_type));
483 TYPE_LENGTH (virtual_type));
486 /* Return the GDB type object for the "standard" data type
487 of data in register REG.
489 Note: kevinb/2002-08-01: The definition below should faithfully
490 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
491 definitions found in config/mips/tm-*.h. I'm concerned about
492 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
493 though. In some cases FP_REGNUM is in this range, and I doubt
494 that this code is correct for the 64-bit case. */
497 mips_register_virtual_type (int reg)
499 if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32)
501 /* Floating point registers... */
502 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
503 return builtin_type_ieee_double_big;
505 return builtin_type_ieee_double_little;
507 else if (reg == PS_REGNUM /* CR */)
508 return builtin_type_uint32;
509 else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM)
510 return builtin_type_uint32;
513 /* Everything else...
514 Return type appropriate for width of register. */
515 if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64))
516 return builtin_type_uint64;
518 return builtin_type_uint32;
522 /* Should the upper word of 64-bit addresses be zeroed? */
523 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
526 mips_mask_address_p (void)
528 switch (mask_address_var)
530 case AUTO_BOOLEAN_TRUE:
532 case AUTO_BOOLEAN_FALSE:
535 case AUTO_BOOLEAN_AUTO:
536 return MIPS_DEFAULT_MASK_ADDRESS_P;
538 internal_error (__FILE__, __LINE__,
539 "mips_mask_address_p: bad switch");
545 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
547 switch (mask_address_var)
549 case AUTO_BOOLEAN_TRUE:
550 printf_filtered ("The 32 bit mips address mask is enabled\n");
552 case AUTO_BOOLEAN_FALSE:
553 printf_filtered ("The 32 bit mips address mask is disabled\n");
555 case AUTO_BOOLEAN_AUTO:
556 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
557 mips_mask_address_p () ? "enabled" : "disabled");
560 internal_error (__FILE__, __LINE__,
561 "show_mask_address: bad switch");
566 /* Should call_function allocate stack space for a struct return? */
568 mips_use_struct_convention (int gcc_p, struct type *type)
571 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
573 return 1; /* Structures are returned by ref in extra arg0 */
576 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
579 pc_is_mips16 (bfd_vma memaddr)
581 struct minimal_symbol *sym;
583 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
584 if (IS_MIPS16_ADDR (memaddr))
587 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
588 the high bit of the info field. Use this to decide if the function is
589 MIPS16 or normal MIPS. */
590 sym = lookup_minimal_symbol_by_pc (memaddr);
592 return MSYMBOL_IS_SPECIAL (sym);
597 /* MIPS believes that the PC has a sign extended value. Perhaphs the
598 all registers should be sign extended for simplicity? */
601 mips_read_pc (ptid_t ptid)
603 return read_signed_register_pid (PC_REGNUM, ptid);
606 /* This returns the PC of the first inst after the prologue. If we can't
607 find the prologue, then return 0. */
610 after_prologue (CORE_ADDR pc,
611 mips_extra_func_info_t proc_desc)
613 struct symtab_and_line sal;
614 CORE_ADDR func_addr, func_end;
616 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
617 to read the stack pointer from the current machine state, because
618 the current machine state has nothing to do with the information
619 we need from the proc_desc; and the process may or may not exist
622 proc_desc = find_proc_desc (pc, NULL, 0);
626 /* If function is frameless, then we need to do it the hard way. I
627 strongly suspect that frameless always means prologueless... */
628 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
629 && PROC_FRAME_OFFSET (proc_desc) == 0)
633 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
634 return 0; /* Unknown */
636 sal = find_pc_line (func_addr, 0);
638 if (sal.end < func_end)
641 /* The line after the prologue is after the end of the function. In this
642 case, tell the caller to find the prologue the hard way. */
647 /* Decode a MIPS32 instruction that saves a register in the stack, and
648 set the appropriate bit in the general register mask or float register mask
649 to indicate which register is saved. This is a helper function
650 for mips_find_saved_regs. */
653 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
654 unsigned long *float_mask)
658 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
659 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
660 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
662 /* It might be possible to use the instruction to
663 find the offset, rather than the code below which
664 is based on things being in a certain order in the
665 frame, but figuring out what the instruction's offset
666 is relative to might be a little tricky. */
667 reg = (inst & 0x001f0000) >> 16;
668 *gen_mask |= (1 << reg);
670 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
671 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
672 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
675 reg = ((inst & 0x001f0000) >> 16);
676 *float_mask |= (1 << reg);
680 /* Decode a MIPS16 instruction that saves a register in the stack, and
681 set the appropriate bit in the general register or float register mask
682 to indicate which register is saved. This is a helper function
683 for mips_find_saved_regs. */
686 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
688 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
690 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
691 *gen_mask |= (1 << reg);
693 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
695 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
696 *gen_mask |= (1 << reg);
698 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
699 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
700 *gen_mask |= (1 << RA_REGNUM);
704 /* Fetch and return instruction from the specified location. If the PC
705 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
708 mips_fetch_instruction (CORE_ADDR addr)
710 char buf[MIPS_INSTLEN];
714 if (pc_is_mips16 (addr))
716 instlen = MIPS16_INSTLEN;
717 addr = UNMAKE_MIPS16_ADDR (addr);
720 instlen = MIPS_INSTLEN;
721 status = read_memory_nobpt (addr, buf, instlen);
723 memory_error (status, addr);
724 return extract_unsigned_integer (buf, instlen);
728 /* These the fields of 32 bit mips instructions */
729 #define mips32_op(x) (x >> 26)
730 #define itype_op(x) (x >> 26)
731 #define itype_rs(x) ((x >> 21) & 0x1f)
732 #define itype_rt(x) ((x >> 16) & 0x1f)
733 #define itype_immediate(x) (x & 0xffff)
735 #define jtype_op(x) (x >> 26)
736 #define jtype_target(x) (x & 0x03ffffff)
738 #define rtype_op(x) (x >> 26)
739 #define rtype_rs(x) ((x >> 21) & 0x1f)
740 #define rtype_rt(x) ((x >> 16) & 0x1f)
741 #define rtype_rd(x) ((x >> 11) & 0x1f)
742 #define rtype_shamt(x) ((x >> 6) & 0x1f)
743 #define rtype_funct(x) (x & 0x3f)
746 mips32_relative_offset (unsigned long inst)
749 x = itype_immediate (inst);
750 if (x & 0x8000) /* sign bit set */
752 x |= 0xffff0000; /* sign extension */
758 /* Determine whate to set a single step breakpoint while considering
761 mips32_next_pc (CORE_ADDR pc)
765 inst = mips_fetch_instruction (pc);
766 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
768 if (itype_op (inst) >> 2 == 5)
769 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
771 op = (itype_op (inst) & 0x03);
786 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
787 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
789 int tf = itype_rt (inst) & 0x01;
790 int cnum = itype_rt (inst) >> 2;
791 int fcrcs = read_signed_register (FCRCS_REGNUM);
792 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
794 if (((cond >> cnum) & 0x01) == tf)
795 pc += mips32_relative_offset (inst) + 4;
800 pc += 4; /* Not a branch, next instruction is easy */
803 { /* This gets way messy */
805 /* Further subdivide into SPECIAL, REGIMM and other */
806 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
808 case 0: /* SPECIAL */
809 op = rtype_funct (inst);
814 /* Set PC to that address */
815 pc = read_signed_register (rtype_rs (inst));
821 break; /* end SPECIAL */
824 op = itype_rt (inst); /* branch condition */
829 case 16: /* BLTZAL */
830 case 18: /* BLTZALL */
832 if (read_signed_register (itype_rs (inst)) < 0)
833 pc += mips32_relative_offset (inst) + 4;
835 pc += 8; /* after the delay slot */
839 case 17: /* BGEZAL */
840 case 19: /* BGEZALL */
841 greater_equal_branch:
842 if (read_signed_register (itype_rs (inst)) >= 0)
843 pc += mips32_relative_offset (inst) + 4;
845 pc += 8; /* after the delay slot */
847 /* All of the other instructions in the REGIMM category */
852 break; /* end REGIMM */
857 reg = jtype_target (inst) << 2;
858 /* Upper four bits get never changed... */
859 pc = reg + ((pc + 4) & 0xf0000000);
862 /* FIXME case JALX : */
865 reg = jtype_target (inst) << 2;
866 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
867 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
869 break; /* The new PC will be alternate mode */
870 case 4: /* BEQ, BEQL */
872 if (read_signed_register (itype_rs (inst)) ==
873 read_signed_register (itype_rt (inst)))
874 pc += mips32_relative_offset (inst) + 4;
878 case 5: /* BNE, BNEL */
880 if (read_signed_register (itype_rs (inst)) !=
881 read_signed_register (itype_rt (inst)))
882 pc += mips32_relative_offset (inst) + 4;
886 case 6: /* BLEZ, BLEZL */
888 if (read_signed_register (itype_rs (inst) <= 0))
889 pc += mips32_relative_offset (inst) + 4;
895 greater_branch: /* BGTZ, BGTZL */
896 if (read_signed_register (itype_rs (inst) > 0))
897 pc += mips32_relative_offset (inst) + 4;
904 } /* mips32_next_pc */
906 /* Decoding the next place to set a breakpoint is irregular for the
907 mips 16 variant, but fortunately, there fewer instructions. We have to cope
908 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
909 We dont want to set a single step instruction on the extend instruction
913 /* Lots of mips16 instruction formats */
914 /* Predicting jumps requires itype,ritype,i8type
915 and their extensions extItype,extritype,extI8type
917 enum mips16_inst_fmts
919 itype, /* 0 immediate 5,10 */
920 ritype, /* 1 5,3,8 */
921 rrtype, /* 2 5,3,3,5 */
922 rritype, /* 3 5,3,3,5 */
923 rrrtype, /* 4 5,3,3,3,2 */
924 rriatype, /* 5 5,3,3,1,4 */
925 shifttype, /* 6 5,3,3,3,2 */
926 i8type, /* 7 5,3,8 */
927 i8movtype, /* 8 5,3,3,5 */
928 i8mov32rtype, /* 9 5,3,5,3 */
929 i64type, /* 10 5,3,8 */
930 ri64type, /* 11 5,3,3,5 */
931 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
932 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
933 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
934 extRRItype, /* 15 5,5,5,5,3,3,5 */
935 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
936 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
937 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
938 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
939 extRi64type, /* 20 5,6,5,5,3,3,5 */
940 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
942 /* I am heaping all the fields of the formats into one structure and
943 then, only the fields which are involved in instruction extension */
947 unsigned int regx; /* Function in i8 type */
952 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
953 for the bits which make up the immediatate extension. */
956 extended_offset (unsigned int extension)
959 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
961 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
963 value |= extension & 0x01f; /* extract 4:0 */
967 /* Only call this function if you know that this is an extendable
968 instruction, It wont malfunction, but why make excess remote memory references?
969 If the immediate operands get sign extended or somthing, do it after
970 the extension is performed.
972 /* FIXME: Every one of these cases needs to worry about sign extension
973 when the offset is to be used in relative addressing */
977 fetch_mips_16 (CORE_ADDR pc)
980 pc &= 0xfffffffe; /* clear the low order bit */
981 target_read_memory (pc, buf, 2);
982 return extract_unsigned_integer (buf, 2);
986 unpack_mips16 (CORE_ADDR pc,
987 unsigned int extension,
989 enum mips16_inst_fmts insn_format,
990 struct upk_mips16 *upk)
1002 value = extended_offset (extension);
1003 value = value << 11; /* rom for the original value */
1004 value |= inst & 0x7ff; /* eleven bits from instruction */
1008 value = inst & 0x7ff;
1009 /* FIXME : Consider sign extension */
1018 { /* A register identifier and an offset */
1019 /* Most of the fields are the same as I type but the
1020 immediate value is of a different length */
1024 value = extended_offset (extension);
1025 value = value << 8; /* from the original instruction */
1026 value |= inst & 0xff; /* eleven bits from instruction */
1027 regx = (extension >> 8) & 0x07; /* or i8 funct */
1028 if (value & 0x4000) /* test the sign bit , bit 26 */
1030 value &= ~0x3fff; /* remove the sign bit */
1036 value = inst & 0xff; /* 8 bits */
1037 regx = (inst >> 8) & 0x07; /* or i8 funct */
1038 /* FIXME: Do sign extension , this format needs it */
1039 if (value & 0x80) /* THIS CONFUSES ME */
1041 value &= 0xef; /* remove the sign bit */
1051 unsigned long value;
1052 unsigned int nexthalf;
1053 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1054 value = value << 16;
1055 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1063 internal_error (__FILE__, __LINE__,
1066 upk->offset = offset;
1073 add_offset_16 (CORE_ADDR pc, int offset)
1075 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1080 extended_mips16_next_pc (CORE_ADDR pc,
1081 unsigned int extension,
1084 int op = (insn >> 11);
1087 case 2: /* Branch */
1090 struct upk_mips16 upk;
1091 unpack_mips16 (pc, extension, insn, itype, &upk);
1092 offset = upk.offset;
1098 pc += (offset << 1) + 2;
1101 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1103 struct upk_mips16 upk;
1104 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1105 pc = add_offset_16 (pc, upk.offset);
1106 if ((insn >> 10) & 0x01) /* Exchange mode */
1107 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1114 struct upk_mips16 upk;
1116 unpack_mips16 (pc, extension, insn, ritype, &upk);
1117 reg = read_signed_register (upk.regx);
1119 pc += (upk.offset << 1) + 2;
1126 struct upk_mips16 upk;
1128 unpack_mips16 (pc, extension, insn, ritype, &upk);
1129 reg = read_signed_register (upk.regx);
1131 pc += (upk.offset << 1) + 2;
1136 case 12: /* I8 Formats btez btnez */
1138 struct upk_mips16 upk;
1140 unpack_mips16 (pc, extension, insn, i8type, &upk);
1141 /* upk.regx contains the opcode */
1142 reg = read_signed_register (24); /* Test register is 24 */
1143 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1144 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1145 /* pc = add_offset_16(pc,upk.offset) ; */
1146 pc += (upk.offset << 1) + 2;
1151 case 29: /* RR Formats JR, JALR, JALR-RA */
1153 struct upk_mips16 upk;
1154 /* upk.fmt = rrtype; */
1159 upk.regx = (insn >> 8) & 0x07;
1160 upk.regy = (insn >> 5) & 0x07;
1168 break; /* Function return instruction */
1174 break; /* BOGUS Guess */
1176 pc = read_signed_register (reg);
1183 /* This is an instruction extension. Fetch the real instruction
1184 (which follows the extension) and decode things based on
1188 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1201 mips16_next_pc (CORE_ADDR pc)
1203 unsigned int insn = fetch_mips_16 (pc);
1204 return extended_mips16_next_pc (pc, 0, insn);
1207 /* The mips_next_pc function supports single_step when the remote
1208 target monitor or stub is not developed enough to do a single_step.
1209 It works by decoding the current instruction and predicting where a
1210 branch will go. This isnt hard because all the data is available.
1211 The MIPS32 and MIPS16 variants are quite different */
1213 mips_next_pc (CORE_ADDR pc)
1216 return mips16_next_pc (pc);
1218 return mips32_next_pc (pc);
1221 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1225 mips_find_saved_regs (struct frame_info *fci)
1228 CORE_ADDR reg_position;
1229 /* r0 bit means kernel trap */
1231 /* What registers have been saved? Bitmasks. */
1232 unsigned long gen_mask, float_mask;
1233 mips_extra_func_info_t proc_desc;
1236 frame_saved_regs_zalloc (fci);
1238 /* If it is the frame for sigtramp, the saved registers are located
1239 in a sigcontext structure somewhere on the stack.
1240 If the stack layout for sigtramp changes we might have to change these
1241 constants and the companion fixup_sigtramp in mdebugread.c */
1242 #ifndef SIGFRAME_BASE
1243 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1244 above the sigtramp frame. */
1245 #define SIGFRAME_BASE MIPS_REGSIZE
1246 /* FIXME! Are these correct?? */
1247 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1248 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1249 #define SIGFRAME_FPREGSAVE_OFF \
1250 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1252 #ifndef SIGFRAME_REG_SIZE
1253 /* FIXME! Is this correct?? */
1254 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1256 if (fci->signal_handler_caller)
1258 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1260 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
1261 + ireg * SIGFRAME_REG_SIZE;
1262 fci->saved_regs[ireg] = reg_position;
1264 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1266 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
1267 + ireg * SIGFRAME_REG_SIZE;
1268 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1270 fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
1274 proc_desc = fci->extra_info->proc_desc;
1275 if (proc_desc == NULL)
1276 /* I'm not sure how/whether this can happen. Normally when we can't
1277 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1278 and set the saved_regs right away. */
1281 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1282 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1283 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1285 if ( /* In any frame other than the innermost or a frame interrupted by
1286 a signal, we assume that all registers have been saved.
1287 This assumes that all register saves in a function happen before
1288 the first function call. */
1289 (fci->next == NULL || fci->next->signal_handler_caller)
1291 /* In a dummy frame we know exactly where things are saved. */
1292 && !PROC_DESC_IS_DUMMY (proc_desc)
1294 /* Don't bother unless we are inside a function prologue. Outside the
1295 prologue, we know where everything is. */
1297 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
1299 /* Not sure exactly what kernel_trap means, but if it means
1300 the kernel saves the registers without a prologue doing it,
1301 we better not examine the prologue to see whether registers
1302 have been saved yet. */
1305 /* We need to figure out whether the registers that the proc_desc
1306 claims are saved have been saved yet. */
1310 /* Bitmasks; set if we have found a save for the register. */
1311 unsigned long gen_save_found = 0;
1312 unsigned long float_save_found = 0;
1315 /* If the address is odd, assume this is MIPS16 code. */
1316 addr = PROC_LOW_ADDR (proc_desc);
1317 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1319 /* Scan through this function's instructions preceding the current
1320 PC, and look for those that save registers. */
1321 while (addr < fci->pc)
1323 inst = mips_fetch_instruction (addr);
1324 if (pc_is_mips16 (addr))
1325 mips16_decode_reg_save (inst, &gen_save_found);
1327 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1330 gen_mask = gen_save_found;
1331 float_mask = float_save_found;
1334 /* Fill in the offsets for the registers which gen_mask says
1336 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1337 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1338 if (gen_mask & 0x80000000)
1340 fci->saved_regs[ireg] = reg_position;
1341 reg_position -= MIPS_SAVED_REGSIZE;
1344 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1345 of that normally used by gcc. Therefore, we have to fetch the first
1346 instruction of the function, and if it's an entry instruction that
1347 saves $s0 or $s1, correct their saved addresses. */
1348 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1350 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1351 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1354 int sreg_count = (inst >> 6) & 3;
1356 /* Check if the ra register was pushed on the stack. */
1357 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1359 reg_position -= MIPS_SAVED_REGSIZE;
1361 /* Check if the s0 and s1 registers were pushed on the stack. */
1362 for (reg = 16; reg < sreg_count + 16; reg++)
1364 fci->saved_regs[reg] = reg_position;
1365 reg_position -= MIPS_SAVED_REGSIZE;
1370 /* Fill in the offsets for the registers which float_mask says
1372 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
1374 /* Apparently, the freg_offset gives the offset to the first 64 bit
1377 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1378 designates the first saved 64 bit register.
1380 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1381 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1382 FREG_OFFSET, designates the address of the lower register of the
1383 register pair. Adjust the offset so that it designates the upper
1384 register of the pair -- i.e., the address of the first saved 32
1387 if (MIPS_SAVED_REGSIZE == 4)
1388 reg_position += MIPS_SAVED_REGSIZE;
1390 /* Fill in the offsets for the float registers which float_mask says
1392 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1393 if (float_mask & 0x80000000)
1395 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1396 reg_position -= MIPS_SAVED_REGSIZE;
1399 fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM];
1403 read_next_frame_reg (struct frame_info *fi, int regno)
1405 for (; fi; fi = fi->next)
1407 /* We have to get the saved sp from the sigcontext
1408 if it is a signal handler frame. */
1409 if (regno == SP_REGNUM && !fi->signal_handler_caller)
1413 if (fi->saved_regs == NULL)
1414 mips_find_saved_regs (fi);
1415 if (fi->saved_regs[regno])
1416 return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE);
1419 return read_signed_register (regno);
1422 /* mips_addr_bits_remove - remove useless address bits */
1425 mips_addr_bits_remove (CORE_ADDR addr)
1427 if (GDB_TARGET_IS_MIPS64)
1429 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1431 /* This hack is a work-around for existing boards using
1432 PMON, the simulator, and any other 64-bit targets that
1433 doesn't have true 64-bit addressing. On these targets,
1434 the upper 32 bits of addresses are ignored by the
1435 hardware. Thus, the PC or SP are likely to have been
1436 sign extended to all 1s by instruction sequences that
1437 load 32-bit addresses. For example, a typical piece of
1438 code that loads an address is this:
1439 lui $r2, <upper 16 bits>
1440 ori $r2, <lower 16 bits>
1441 But the lui sign-extends the value such that the upper 32
1442 bits may be all 1s. The workaround is simply to mask off
1443 these bits. In the future, gcc may be changed to support
1444 true 64-bit addressing, and this masking will have to be
1446 addr &= (CORE_ADDR) 0xffffffff;
1449 else if (mips_mask_address_p ())
1451 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1452 masking off bits, instead, the actual target should be asking
1453 for the address to be converted to a valid pointer. */
1454 /* Even when GDB is configured for some 32-bit targets
1455 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1456 so CORE_ADDR is 64 bits. So we still have to mask off
1457 useless bits from addresses. */
1458 addr &= (CORE_ADDR) 0xffffffff;
1463 /* mips_software_single_step() is called just before we want to resume
1464 the inferior, if we want to single-step it but there is no hardware
1465 or kernel single-step support (MIPS on GNU/Linux for example). We find
1466 the target of the coming instruction and breakpoint it.
1468 single_step is also called just after the inferior stops. If we had
1469 set up a simulated single-step, we undo our damage. */
1472 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1474 static CORE_ADDR next_pc;
1475 typedef char binsn_quantum[BREAKPOINT_MAX];
1476 static binsn_quantum break_mem;
1479 if (insert_breakpoints_p)
1481 pc = read_register (PC_REGNUM);
1482 next_pc = mips_next_pc (pc);
1484 target_insert_breakpoint (next_pc, break_mem);
1487 target_remove_breakpoint (next_pc, break_mem);
1491 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1495 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
1496 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
1497 tmp = mips_skip_stub (pc);
1498 prev->pc = tmp ? tmp : pc;
1503 mips_frame_saved_pc (struct frame_info *frame)
1506 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
1507 /* We have to get the saved pc from the sigcontext
1508 if it is a signal handler frame. */
1509 int pcreg = frame->signal_handler_caller ? PC_REGNUM
1510 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1512 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1513 saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1515 saved_pc = read_next_frame_reg (frame, pcreg);
1517 return ADDR_BITS_REMOVE (saved_pc);
1520 static struct mips_extra_func_info temp_proc_desc;
1521 static CORE_ADDR temp_saved_regs[NUM_REGS];
1523 /* Set a register's saved stack address in temp_saved_regs. If an address
1524 has already been set for this register, do nothing; this way we will
1525 only recognize the first save of a given register in a function prologue.
1526 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1529 set_reg_offset (int regno, CORE_ADDR offset)
1531 if (temp_saved_regs[regno] == 0)
1532 temp_saved_regs[regno] = offset;
1536 /* Test whether the PC points to the return instruction at the
1537 end of a function. */
1540 mips_about_to_return (CORE_ADDR pc)
1542 if (pc_is_mips16 (pc))
1543 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1544 generates a "jr $ra"; other times it generates code to load
1545 the return address from the stack to an accessible register (such
1546 as $a3), then a "jr" using that register. This second case
1547 is almost impossible to distinguish from an indirect jump
1548 used for switch statements, so we don't even try. */
1549 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1551 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1555 /* This fencepost looks highly suspicious to me. Removing it also
1556 seems suspicious as it could affect remote debugging across serial
1560 heuristic_proc_start (CORE_ADDR pc)
1567 pc = ADDR_BITS_REMOVE (pc);
1569 fence = start_pc - heuristic_fence_post;
1573 if (heuristic_fence_post == UINT_MAX
1574 || fence < VM_MIN_ADDRESS)
1575 fence = VM_MIN_ADDRESS;
1577 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1579 /* search back for previous return */
1580 for (start_pc -= instlen;; start_pc -= instlen)
1581 if (start_pc < fence)
1583 /* It's not clear to me why we reach this point when
1584 stop_soon_quietly, but with this test, at least we
1585 don't print out warnings for every child forked (eg, on
1586 decstation). 22apr93 rich@cygnus.com. */
1587 if (!stop_soon_quietly)
1589 static int blurb_printed = 0;
1591 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1596 /* This actually happens frequently in embedded
1597 development, when you first connect to a board
1598 and your stack pointer and pc are nowhere in
1599 particular. This message needs to give people
1600 in that situation enough information to
1601 determine that it's no big deal. */
1602 printf_filtered ("\n\
1603 GDB is unable to find the start of the function at 0x%s\n\
1604 and thus can't determine the size of that function's stack frame.\n\
1605 This means that GDB may be unable to access that stack frame, or\n\
1606 the frames below it.\n\
1607 This problem is most likely caused by an invalid program counter or\n\
1609 However, if you think GDB should simply search farther back\n\
1610 from 0x%s for code which looks like the beginning of a\n\
1611 function, you can increase the range of the search using the `set\n\
1612 heuristic-fence-post' command.\n",
1613 paddr_nz (pc), paddr_nz (pc));
1620 else if (pc_is_mips16 (start_pc))
1622 unsigned short inst;
1624 /* On MIPS16, any one of the following is likely to be the
1625 start of a function:
1629 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1630 inst = mips_fetch_instruction (start_pc);
1631 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1632 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1633 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1634 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1636 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1637 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1642 else if (mips_about_to_return (start_pc))
1644 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1651 /* Fetch the immediate value from a MIPS16 instruction.
1652 If the previous instruction was an EXTEND, use it to extend
1653 the upper bits of the immediate value. This is a helper function
1654 for mips16_heuristic_proc_desc. */
1657 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1658 unsigned short inst, /* current instruction */
1659 int nbits, /* number of bits in imm field */
1660 int scale, /* scale factor to be applied to imm */
1661 int is_signed) /* is the imm field signed? */
1665 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1667 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1668 if (offset & 0x8000) /* check for negative extend */
1669 offset = 0 - (0x10000 - (offset & 0xffff));
1670 return offset | (inst & 0x1f);
1674 int max_imm = 1 << nbits;
1675 int mask = max_imm - 1;
1676 int sign_bit = max_imm >> 1;
1678 offset = inst & mask;
1679 if (is_signed && (offset & sign_bit))
1680 offset = 0 - (max_imm - offset);
1681 return offset * scale;
1686 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1687 stream from start_pc to limit_pc. */
1690 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1691 struct frame_info *next_frame, CORE_ADDR sp)
1694 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1695 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1696 unsigned inst = 0; /* current instruction */
1697 unsigned entry_inst = 0; /* the entry instruction */
1700 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1701 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1703 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1705 /* Save the previous instruction. If it's an EXTEND, we'll extract
1706 the immediate offset extension from it in mips16_get_imm. */
1709 /* Fetch and decode the instruction. */
1710 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1711 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1712 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1714 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1715 if (offset < 0) /* negative stack adjustment? */
1716 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
1718 /* Exit loop if a positive stack adjustment is found, which
1719 usually means that the stack cleanup code in the function
1720 epilogue is reached. */
1723 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1725 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1726 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1727 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1728 set_reg_offset (reg, sp + offset);
1730 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1732 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1733 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1734 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1735 set_reg_offset (reg, sp + offset);
1737 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1739 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1740 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1741 set_reg_offset (RA_REGNUM, sp + offset);
1743 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1745 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1746 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1747 set_reg_offset (RA_REGNUM, sp + offset);
1749 else if (inst == 0x673d) /* move $s1, $sp */
1752 PROC_FRAME_REG (&temp_proc_desc) = 17;
1754 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1756 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1757 frame_addr = sp + offset;
1758 PROC_FRAME_REG (&temp_proc_desc) = 17;
1759 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1761 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1763 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1764 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1765 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1766 set_reg_offset (reg, frame_addr + offset);
1768 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1770 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1771 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1772 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1773 set_reg_offset (reg, frame_addr + offset);
1775 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1776 entry_inst = inst; /* save for later processing */
1777 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1778 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
1781 /* The entry instruction is typically the first instruction in a function,
1782 and it stores registers at offsets relative to the value of the old SP
1783 (before the prologue). But the value of the sp parameter to this
1784 function is the new SP (after the prologue has been executed). So we
1785 can't calculate those offsets until we've seen the entire prologue,
1786 and can calculate what the old SP must have been. */
1787 if (entry_inst != 0)
1789 int areg_count = (entry_inst >> 8) & 7;
1790 int sreg_count = (entry_inst >> 6) & 3;
1792 /* The entry instruction always subtracts 32 from the SP. */
1793 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
1795 /* Now we can calculate what the SP must have been at the
1796 start of the function prologue. */
1797 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
1799 /* Check if a0-a3 were saved in the caller's argument save area. */
1800 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1802 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1803 set_reg_offset (reg, sp + offset);
1804 offset += MIPS_SAVED_REGSIZE;
1807 /* Check if the ra register was pushed on the stack. */
1809 if (entry_inst & 0x20)
1811 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
1812 set_reg_offset (RA_REGNUM, sp + offset);
1813 offset -= MIPS_SAVED_REGSIZE;
1816 /* Check if the s0 and s1 registers were pushed on the stack. */
1817 for (reg = 16; reg < sreg_count + 16; reg++)
1819 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1820 set_reg_offset (reg, sp + offset);
1821 offset -= MIPS_SAVED_REGSIZE;
1827 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1828 struct frame_info *next_frame, CORE_ADDR sp)
1831 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1833 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
1834 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
1835 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1836 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
1838 unsigned long inst, high_word, low_word;
1841 /* Fetch the instruction. */
1842 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1844 /* Save some code by pre-extracting some useful fields. */
1845 high_word = (inst >> 16) & 0xffff;
1846 low_word = inst & 0xffff;
1847 reg = high_word & 0x1f;
1849 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1850 || high_word == 0x23bd /* addi $sp,$sp,-i */
1851 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1853 if (low_word & 0x8000) /* negative stack adjustment? */
1854 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
1856 /* Exit loop if a positive stack adjustment is found, which
1857 usually means that the stack cleanup code in the function
1858 epilogue is reached. */
1861 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1863 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1864 set_reg_offset (reg, sp + low_word);
1866 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1868 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1869 but the register size used is only 32 bits. Make the address
1870 for the saved register point to the lower 32 bits. */
1871 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1872 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
1874 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1876 /* Old gcc frame, r30 is virtual frame pointer. */
1877 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
1878 frame_addr = sp + low_word;
1879 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1881 unsigned alloca_adjust;
1882 PROC_FRAME_REG (&temp_proc_desc) = 30;
1883 frame_addr = read_next_frame_reg (next_frame, 30);
1884 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1885 if (alloca_adjust > 0)
1887 /* FP > SP + frame_size. This may be because
1888 * of an alloca or somethings similar.
1889 * Fix sp to "pre-alloca" value, and try again.
1891 sp += alloca_adjust;
1896 /* move $30,$sp. With different versions of gas this will be either
1897 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1898 Accept any one of these. */
1899 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1901 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1902 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1904 unsigned alloca_adjust;
1905 PROC_FRAME_REG (&temp_proc_desc) = 30;
1906 frame_addr = read_next_frame_reg (next_frame, 30);
1907 alloca_adjust = (unsigned) (frame_addr - sp);
1908 if (alloca_adjust > 0)
1910 /* FP > SP + frame_size. This may be because
1911 * of an alloca or somethings similar.
1912 * Fix sp to "pre-alloca" value, and try again.
1914 sp += alloca_adjust;
1919 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1921 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1922 set_reg_offset (reg, frame_addr + low_word);
1927 static mips_extra_func_info_t
1928 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1929 struct frame_info *next_frame, int cur_frame)
1934 sp = read_next_frame_reg (next_frame, SP_REGNUM);
1940 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
1941 memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
1942 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
1943 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
1944 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
1946 if (start_pc + 200 < limit_pc)
1947 limit_pc = start_pc + 200;
1948 if (pc_is_mips16 (start_pc))
1949 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
1951 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
1952 return &temp_proc_desc;
1955 struct mips_objfile_private
1961 /* Global used to communicate between non_heuristic_proc_desc and
1962 compare_pdr_entries within qsort (). */
1963 static bfd *the_bfd;
1966 compare_pdr_entries (const void *a, const void *b)
1968 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
1969 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
1973 else if (lhs == rhs)
1979 static mips_extra_func_info_t
1980 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
1982 CORE_ADDR startaddr;
1983 mips_extra_func_info_t proc_desc;
1984 struct block *b = block_for_pc (pc);
1986 struct obj_section *sec;
1987 struct mips_objfile_private *priv;
1989 if (PC_IN_CALL_DUMMY (pc, 0, 0))
1992 find_pc_partial_function (pc, NULL, &startaddr, NULL);
1994 *addrptr = startaddr;
1998 sec = find_pc_section (pc);
2001 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2003 /* Search the ".pdr" section generated by GAS. This includes most of
2004 the information normally found in ECOFF PDRs. */
2006 the_bfd = sec->objfile->obfd;
2008 && (the_bfd->format == bfd_object
2009 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2010 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2012 /* Right now GAS only outputs the address as a four-byte sequence.
2013 This means that we should not bother with this method on 64-bit
2014 targets (until that is fixed). */
2016 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2017 sizeof (struct mips_objfile_private));
2019 sec->objfile->obj_private = priv;
2021 else if (priv == NULL)
2025 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2026 sizeof (struct mips_objfile_private));
2028 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2031 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2032 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2034 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2035 priv->contents, 0, priv->size);
2037 /* In general, the .pdr section is sorted. However, in the
2038 presence of multiple code sections (and other corner cases)
2039 it can become unsorted. Sort it so that we can use a faster
2041 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2046 sec->objfile->obj_private = priv;
2050 if (priv->size != 0)
2056 high = priv->size / 32;
2062 mid = (low + high) / 2;
2064 ptr = priv->contents + mid * 32;
2065 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2066 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2067 SECT_OFF_TEXT (sec->objfile));
2068 if (pdr_pc == startaddr)
2070 if (pdr_pc > startaddr)
2075 while (low != high);
2079 struct symbol *sym = find_pc_function (pc);
2081 /* Fill in what we need of the proc_desc. */
2082 proc_desc = (mips_extra_func_info_t)
2083 obstack_alloc (&sec->objfile->psymbol_obstack,
2084 sizeof (struct mips_extra_func_info));
2085 PROC_LOW_ADDR (proc_desc) = startaddr;
2087 /* Only used for dummy frames. */
2088 PROC_HIGH_ADDR (proc_desc) = 0;
2090 PROC_FRAME_OFFSET (proc_desc)
2091 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2092 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2094 PROC_FRAME_ADJUST (proc_desc) = 0;
2095 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2097 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2099 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2101 PROC_FREG_OFFSET (proc_desc)
2102 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2103 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2105 proc_desc->pdr.isym = (long) sym;
2115 if (startaddr > BLOCK_START (b))
2117 /* This is the "pathological" case referred to in a comment in
2118 print_frame_info. It might be better to move this check into
2123 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
2125 /* If we never found a PDR for this function in symbol reading, then
2126 examine prologues to find the information. */
2129 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2130 if (PROC_FRAME_REG (proc_desc) == -1)
2140 static mips_extra_func_info_t
2141 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2143 mips_extra_func_info_t proc_desc;
2144 CORE_ADDR startaddr;
2146 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2150 /* IF this is the topmost frame AND
2151 * (this proc does not have debugging information OR
2152 * the PC is in the procedure prologue)
2153 * THEN create a "heuristic" proc_desc (by analyzing
2154 * the actual code) to replace the "official" proc_desc.
2156 if (next_frame == NULL)
2158 struct symtab_and_line val;
2159 struct symbol *proc_symbol =
2160 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2164 val = find_pc_line (BLOCK_START
2165 (SYMBOL_BLOCK_VALUE (proc_symbol)),
2167 val.pc = val.end ? val.end : pc;
2169 if (!proc_symbol || pc < val.pc)
2171 mips_extra_func_info_t found_heuristic =
2172 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2173 pc, next_frame, cur_frame);
2174 if (found_heuristic)
2175 proc_desc = found_heuristic;
2181 /* Is linked_proc_desc_table really necessary? It only seems to be used
2182 by procedure call dummys. However, the procedures being called ought
2183 to have their own proc_descs, and even if they don't,
2184 heuristic_proc_desc knows how to create them! */
2186 register struct linked_proc_info *link;
2188 for (link = linked_proc_desc_table; link; link = link->next)
2189 if (PROC_LOW_ADDR (&link->info) <= pc
2190 && PROC_HIGH_ADDR (&link->info) > pc)
2194 startaddr = heuristic_proc_start (pc);
2197 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2203 get_frame_pointer (struct frame_info *frame,
2204 mips_extra_func_info_t proc_desc)
2206 return ADDR_BITS_REMOVE (
2207 read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) +
2208 PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
2211 mips_extra_func_info_t cached_proc_desc;
2214 mips_frame_chain (struct frame_info *frame)
2216 mips_extra_func_info_t proc_desc;
2218 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
2220 if (saved_pc == 0 || inside_entry_file (saved_pc))
2223 /* Check if the PC is inside a call stub. If it is, fetch the
2224 PC of the caller of that stub. */
2225 if ((tmp = mips_skip_stub (saved_pc)) != 0)
2228 /* Look up the procedure descriptor for this PC. */
2229 proc_desc = find_proc_desc (saved_pc, frame, 1);
2233 cached_proc_desc = proc_desc;
2235 /* If no frame pointer and frame size is zero, we must be at end
2236 of stack (or otherwise hosed). If we don't check frame size,
2237 we loop forever if we see a zero size frame. */
2238 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2239 && PROC_FRAME_OFFSET (proc_desc) == 0
2240 /* The previous frame from a sigtramp frame might be frameless
2241 and have frame size zero. */
2242 && !frame->signal_handler_caller)
2245 return get_frame_pointer (frame, proc_desc);
2249 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2253 /* Use proc_desc calculated in frame_chain */
2254 mips_extra_func_info_t proc_desc =
2255 fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1);
2257 fci->extra_info = (struct frame_extra_info *)
2258 frame_obstack_alloc (sizeof (struct frame_extra_info));
2260 fci->saved_regs = NULL;
2261 fci->extra_info->proc_desc =
2262 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2265 /* Fixup frame-pointer - only needed for top frame */
2266 /* This may not be quite right, if proc has a real frame register.
2267 Get the value of the frame relative sp, procedure might have been
2268 interrupted by a signal at it's very start. */
2269 if (fci->pc == PROC_LOW_ADDR (proc_desc)
2270 && !PROC_DESC_IS_DUMMY (proc_desc))
2271 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
2273 fci->frame = get_frame_pointer (fci->next, proc_desc);
2275 if (proc_desc == &temp_proc_desc)
2279 /* Do not set the saved registers for a sigtramp frame,
2280 mips_find_saved_registers will do that for us.
2281 We can't use fci->signal_handler_caller, it is not yet set. */
2282 find_pc_partial_function (fci->pc, &name,
2283 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2284 if (!PC_IN_SIGTRAMP (fci->pc, name))
2286 frame_saved_regs_zalloc (fci);
2287 memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2288 fci->saved_regs[PC_REGNUM]
2289 = fci->saved_regs[RA_REGNUM];
2293 /* hack: if argument regs are saved, guess these contain args */
2294 /* assume we can't tell how many args for now */
2295 fci->extra_info->num_args = -1;
2296 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2298 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2300 fci->extra_info->num_args = regnum - A0_REGNUM + 1;
2307 /* MIPS stack frames are almost impenetrable. When execution stops,
2308 we basically have to look at symbol information for the function
2309 that we stopped in, which tells us *which* register (if any) is
2310 the base of the frame pointer, and what offset from that register
2311 the frame itself is at.
2313 This presents a problem when trying to examine a stack in memory
2314 (that isn't executing at the moment), using the "frame" command. We
2315 don't have a PC, nor do we have any registers except SP.
2317 This routine takes two arguments, SP and PC, and tries to make the
2318 cached frames look as if these two arguments defined a frame on the
2319 cache. This allows the rest of info frame to extract the important
2320 arguments without difficulty. */
2323 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2326 error ("MIPS frame specifications require two arguments: sp and pc");
2328 return create_new_frame (argv[0], argv[1]);
2331 /* According to the current ABI, should the type be passed in a
2332 floating-point register (assuming that there is space)? When there
2333 is no FPU, FP are not even considered as possibile candidates for
2334 FP registers and, consequently this returns false - forces FP
2335 arguments into integer registers. */
2338 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2340 return ((typecode == TYPE_CODE_FLT
2342 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2343 && TYPE_NFIELDS (arg_type) == 1
2344 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2345 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2348 /* On o32, argument passing in GPRs depends on the alignment of the type being
2349 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2352 mips_type_needs_double_align (struct type *type)
2354 enum type_code typecode = TYPE_CODE (type);
2356 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2358 else if (typecode == TYPE_CODE_STRUCT)
2360 if (TYPE_NFIELDS (type) < 1)
2362 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2364 else if (typecode == TYPE_CODE_UNION)
2368 n = TYPE_NFIELDS (type);
2369 for (i = 0; i < n; i++)
2370 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2378 mips_push_arguments (int nargs,
2379 struct value **args,
2382 CORE_ADDR struct_addr)
2388 int stack_offset = 0;
2389 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2391 /* Macros to round N up or down to the next A boundary; A must be
2393 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2394 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2396 /* First ensure that the stack and structure return address (if any)
2397 are properly aligned. The stack has to be at least 64-bit aligned
2398 even on 32-bit machines, because doubles must be 64-bit aligned.
2399 On at least one MIPS variant, stack frames need to be 128-bit
2400 aligned, so we round to this widest known alignment. */
2401 sp = ROUND_DOWN (sp, 16);
2402 struct_addr = ROUND_DOWN (struct_addr, 16);
2404 /* Now make space on the stack for the args. We allocate more
2405 than necessary for EABI, because the first few arguments are
2406 passed in registers, but that's OK. */
2407 for (argnum = 0; argnum < nargs; argnum++)
2408 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_STACK_ARGSIZE);
2409 sp -= ROUND_UP (len, 16);
2412 fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n",
2413 (long) sp, ROUND_UP (len, 16));
2415 /* Initialize the integer and float register pointers. */
2417 float_argreg = FPA0_REGNUM;
2419 /* the struct_return pointer occupies the first parameter-passing reg */
2423 fprintf_unfiltered (gdb_stdlog,
2424 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2425 argreg, (long) struct_addr);
2426 write_register (argreg++, struct_addr);
2427 if (MIPS_REGS_HAVE_HOME_P)
2428 stack_offset += MIPS_STACK_ARGSIZE;
2431 /* Now load as many as possible of the first arguments into
2432 registers, and push the rest onto the stack. Loop thru args
2433 from first to last. */
2434 for (argnum = 0; argnum < nargs; argnum++)
2437 char valbuf[MAX_REGISTER_RAW_SIZE];
2438 struct value *arg = args[argnum];
2439 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2440 int len = TYPE_LENGTH (arg_type);
2441 enum type_code typecode = TYPE_CODE (arg_type);
2444 fprintf_unfiltered (gdb_stdlog,
2445 "mips_push_arguments: %d len=%d type=%d",
2446 argnum + 1, len, (int) typecode);
2448 /* The EABI passes structures that do not fit in a register by
2449 reference. In all other cases, pass the structure by value. */
2451 && len > MIPS_SAVED_REGSIZE
2452 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2454 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2455 typecode = TYPE_CODE_PTR;
2456 len = MIPS_SAVED_REGSIZE;
2459 fprintf_unfiltered (gdb_stdlog, " push");
2462 val = (char *) VALUE_CONTENTS (arg);
2464 /* 32-bit ABIs always start floating point arguments in an
2465 even-numbered floating point register. Round the FP register
2466 up before the check to see if there are any FP registers
2467 left. Non MIPS_EABI targets also pass the FP in the integer
2468 registers so also round up normal registers. */
2469 if (!FP_REGISTER_DOUBLE
2470 && fp_register_arg_p (typecode, arg_type))
2472 if ((float_argreg & 1))
2476 /* Floating point arguments passed in registers have to be
2477 treated specially. On 32-bit architectures, doubles
2478 are passed in register pairs; the even register gets
2479 the low word, and the odd register gets the high word.
2480 On non-EABI processors, the first two floating point arguments are
2481 also copied to general registers, because MIPS16 functions
2482 don't use float registers for arguments. This duplication of
2483 arguments in general registers can't hurt non-MIPS16 functions
2484 because those registers are normally skipped. */
2485 /* MIPS_EABI squeezes a struct that contains a single floating
2486 point value into an FP register instead of pushing it onto the
2488 if (fp_register_arg_p (typecode, arg_type)
2489 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2491 if (!FP_REGISTER_DOUBLE && len == 8)
2493 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2494 unsigned long regval;
2496 /* Write the low word of the double to the even register(s). */
2497 regval = extract_unsigned_integer (val + low_offset, 4);
2499 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2500 float_argreg, phex (regval, 4));
2501 write_register (float_argreg++, regval);
2505 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2506 argreg, phex (regval, 4));
2507 write_register (argreg++, regval);
2510 /* Write the high word of the double to the odd register(s). */
2511 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2513 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2514 float_argreg, phex (regval, 4));
2515 write_register (float_argreg++, regval);
2519 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2520 argreg, phex (regval, 4));
2521 write_register (argreg++, regval);
2527 /* This is a floating point value that fits entirely
2528 in a single register. */
2529 /* On 32 bit ABI's the float_argreg is further adjusted
2530 above to ensure that it is even register aligned. */
2531 LONGEST regval = extract_unsigned_integer (val, len);
2533 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2534 float_argreg, phex (regval, len));
2535 write_register (float_argreg++, regval);
2538 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2539 registers for each argument. The below is (my
2540 guess) to ensure that the corresponding integer
2541 register has reserved the same space. */
2543 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2544 argreg, phex (regval, len));
2545 write_register (argreg, regval);
2546 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
2549 /* Reserve space for the FP register. */
2550 if (MIPS_REGS_HAVE_HOME_P)
2551 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
2555 /* Copy the argument to general registers or the stack in
2556 register-sized pieces. Large arguments are split between
2557 registers and stack. */
2558 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2559 are treated specially: Irix cc passes them in registers
2560 where gcc sometimes puts them on the stack. For maximum
2561 compatibility, we will put them in both places. */
2562 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2563 (len % MIPS_SAVED_REGSIZE != 0));
2564 /* Structures should be aligned to eight bytes (even arg registers)
2565 on MIPS_ABI_O32 if their first member has double precision. */
2566 if (tdep->mips_abi == MIPS_ABI_O32
2567 && mips_type_needs_double_align (arg_type))
2572 /* Note: Floating-point values that didn't fit into an FP
2573 register are only written to memory. */
2576 /* Rememer if the argument was written to the stack. */
2577 int stack_used_p = 0;
2578 int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2581 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2584 /* Write this portion of the argument to the stack. */
2585 if (argreg > MIPS_LAST_ARG_REGNUM
2587 || fp_register_arg_p (typecode, arg_type))
2589 /* Should shorter than int integer values be
2590 promoted to int before being stored? */
2591 int longword_offset = 0;
2594 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2596 if (MIPS_STACK_ARGSIZE == 8 &&
2597 (typecode == TYPE_CODE_INT ||
2598 typecode == TYPE_CODE_PTR ||
2599 typecode == TYPE_CODE_FLT) && len <= 4)
2600 longword_offset = MIPS_STACK_ARGSIZE - len;
2601 else if ((typecode == TYPE_CODE_STRUCT ||
2602 typecode == TYPE_CODE_UNION) &&
2603 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2604 longword_offset = MIPS_STACK_ARGSIZE - len;
2609 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%lx",
2610 (long) stack_offset);
2611 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx",
2612 (long) longword_offset);
2615 addr = sp + stack_offset + longword_offset;
2620 fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr);
2621 for (i = 0; i < partial_len; i++)
2623 fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff);
2626 write_memory (addr, val, partial_len);
2629 /* Note!!! This is NOT an else clause. Odd sized
2630 structs may go thru BOTH paths. Floating point
2631 arguments will not. */
2632 /* Write this portion of the argument to a general
2633 purpose register. */
2634 if (argreg <= MIPS_LAST_ARG_REGNUM
2635 && !fp_register_arg_p (typecode, arg_type))
2637 LONGEST regval = extract_unsigned_integer (val, partial_len);
2639 /* A non-floating-point argument being passed in a
2640 general register. If a struct or union, and if
2641 the remaining length is smaller than the register
2642 size, we have to adjust the register value on
2645 It does not seem to be necessary to do the
2646 same for integral types.
2648 Also don't do this adjustment on EABI and O64
2651 cagney/2001-07-23: gdb/179: Also, GCC, when
2652 outputting LE O32 with sizeof (struct) <
2653 MIPS_SAVED_REGSIZE, generates a left shift as
2654 part of storing the argument in a register a
2655 register (the left shift isn't generated when
2656 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2657 is quite possible that this is GCC contradicting
2658 the LE/O32 ABI, GDB has not been adjusted to
2659 accommodate this. Either someone needs to
2660 demonstrate that the LE/O32 ABI specifies such a
2661 left shift OR this new ABI gets identified as
2662 such and GDB gets tweaked accordingly. */
2665 && MIPS_SAVED_REGSIZE < 8
2666 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2667 && partial_len < MIPS_SAVED_REGSIZE
2668 && (typecode == TYPE_CODE_STRUCT ||
2669 typecode == TYPE_CODE_UNION))
2670 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
2674 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2676 phex (regval, MIPS_SAVED_REGSIZE));
2677 write_register (argreg, regval);
2680 /* If this is the old ABI, prevent subsequent floating
2681 point arguments from being passed in floating point
2684 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
2690 /* Compute the the offset into the stack at which we
2691 will copy the next parameter.
2693 In older ABIs, the caller reserved space for
2694 registers that contained arguments. This was loosely
2695 refered to as their "home". Consequently, space is
2698 In the new EABI (and the NABI32), the stack_offset
2699 only needs to be adjusted when it has been used.. */
2701 if (MIPS_REGS_HAVE_HOME_P || stack_used_p)
2702 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2706 fprintf_unfiltered (gdb_stdlog, "\n");
2709 /* Return adjusted stack pointer. */
2714 mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2716 /* Set the return address register to point to the entry
2717 point of the program, where a breakpoint lies in wait. */
2718 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
2723 mips_push_register (CORE_ADDR * sp, int regno)
2725 char buffer[MAX_REGISTER_RAW_SIZE];
2728 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
2730 regsize = MIPS_SAVED_REGSIZE;
2731 offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2732 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
2737 regsize = REGISTER_RAW_SIZE (regno);
2741 read_register_gen (regno, buffer);
2742 write_memory (*sp, buffer + offset, regsize);
2745 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2746 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2749 mips_push_dummy_frame (void)
2752 struct linked_proc_info *link = (struct linked_proc_info *)
2753 xmalloc (sizeof (struct linked_proc_info));
2754 mips_extra_func_info_t proc_desc = &link->info;
2755 CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
2756 CORE_ADDR old_sp = sp;
2757 link->next = linked_proc_desc_table;
2758 linked_proc_desc_table = link;
2760 /* FIXME! are these correct ? */
2761 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2762 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2763 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2764 #define FLOAT_SINGLE_REG_SAVE_MASK \
2765 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2767 * The registers we must save are all those not preserved across
2768 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2769 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2770 * and FP Control/Status registers.
2773 * Dummy frame layout:
2776 * Saved MMHI, MMLO, FPC_CSR
2781 * Saved D18 (i.e. F19, F18)
2783 * Saved D0 (i.e. F1, F0)
2784 * Argument build area and stack arguments written via mips_push_arguments
2788 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2789 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
2790 PROC_FRAME_OFFSET (proc_desc) = 0;
2791 PROC_FRAME_ADJUST (proc_desc) = 0;
2792 mips_push_register (&sp, PC_REGNUM);
2793 mips_push_register (&sp, HI_REGNUM);
2794 mips_push_register (&sp, LO_REGNUM);
2795 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
2797 /* Save general CPU registers */
2798 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
2799 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2800 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
2801 for (ireg = 32; --ireg >= 0;)
2802 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
2803 mips_push_register (&sp, ireg);
2805 /* Save floating point registers starting with high order word */
2806 PROC_FREG_MASK (proc_desc) =
2807 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
2808 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
2809 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2811 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
2812 for (ireg = 32; --ireg >= 0;)
2813 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
2814 mips_push_register (&sp, ireg + FP0_REGNUM);
2816 /* Update the frame pointer for the call dummy and the stack pointer.
2817 Set the procedure's starting and ending addresses to point to the
2818 call dummy address at the entry point. */
2819 write_register (PUSH_FP_REGNUM, old_sp);
2820 write_register (SP_REGNUM, sp);
2821 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
2822 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
2823 SET_PROC_DESC_IS_DUMMY (proc_desc);
2824 PROC_PC_REG (proc_desc) = RA_REGNUM;
2828 mips_pop_frame (void)
2830 register int regnum;
2831 struct frame_info *frame = get_current_frame ();
2832 CORE_ADDR new_sp = FRAME_FP (frame);
2834 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
2836 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
2837 if (frame->saved_regs == NULL)
2838 mips_find_saved_regs (frame);
2839 for (regnum = 0; regnum < NUM_REGS; regnum++)
2841 if (regnum != SP_REGNUM && regnum != PC_REGNUM
2842 && frame->saved_regs[regnum])
2843 write_register (regnum,
2844 read_memory_integer (frame->saved_regs[regnum],
2845 MIPS_SAVED_REGSIZE));
2847 write_register (SP_REGNUM, new_sp);
2848 flush_cached_frames ();
2850 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
2852 struct linked_proc_info *pi_ptr, *prev_ptr;
2854 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
2856 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
2858 if (&pi_ptr->info == proc_desc)
2863 error ("Can't locate dummy extra frame info\n");
2865 if (prev_ptr != NULL)
2866 prev_ptr->next = pi_ptr->next;
2868 linked_proc_desc_table = pi_ptr->next;
2872 write_register (HI_REGNUM,
2873 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
2874 MIPS_SAVED_REGSIZE));
2875 write_register (LO_REGNUM,
2876 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
2877 MIPS_SAVED_REGSIZE));
2878 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
2879 write_register (FCRCS_REGNUM,
2880 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
2881 MIPS_SAVED_REGSIZE));
2885 /* Floating point register management.
2887 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2888 64bit operations, these early MIPS cpus treat fp register pairs
2889 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2890 registers and offer a compatibility mode that emulates the MIPS2 fp
2891 model. When operating in MIPS2 fp compat mode, later cpu's split
2892 double precision floats into two 32-bit chunks and store them in
2893 consecutive fp regs. To display 64-bit floats stored in this
2894 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2895 Throw in user-configurable endianness and you have a real mess.
2897 The way this works is:
2898 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2899 double-precision value will be split across two logical registers.
2900 The lower-numbered logical register will hold the low-order bits,
2901 regardless of the processor's endianness.
2902 - If we are on a 64-bit processor, and we are looking for a
2903 single-precision value, it will be in the low ordered bits
2904 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2905 save slot in memory.
2906 - If we are in 64-bit mode, everything is straightforward.
2908 Note that this code only deals with "live" registers at the top of the
2909 stack. We will attempt to deal with saved registers later, when
2910 the raw/cooked register interface is in place. (We need a general
2911 interface that can deal with dynamic saved register sizes -- fp
2912 regs could be 32 bits wide in one frame and 64 on the frame above
2915 static struct type *
2916 mips_float_register_type (void)
2918 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2919 return builtin_type_ieee_single_big;
2921 return builtin_type_ieee_single_little;
2924 static struct type *
2925 mips_double_register_type (void)
2927 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2928 return builtin_type_ieee_double_big;
2930 return builtin_type_ieee_double_little;
2933 /* Copy a 32-bit single-precision value from the current frame
2934 into rare_buffer. */
2937 mips_read_fp_register_single (int regno, char *rare_buffer)
2939 int raw_size = REGISTER_RAW_SIZE (regno);
2940 char *raw_buffer = alloca (raw_size);
2942 if (!frame_register_read (selected_frame, regno, raw_buffer))
2943 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
2946 /* We have a 64-bit value for this register. Find the low-order
2950 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2955 memcpy (rare_buffer, raw_buffer + offset, 4);
2959 memcpy (rare_buffer, raw_buffer, 4);
2963 /* Copy a 64-bit double-precision value from the current frame into
2964 rare_buffer. This may include getting half of it from the next
2968 mips_read_fp_register_double (int regno, char *rare_buffer)
2970 int raw_size = REGISTER_RAW_SIZE (regno);
2972 if (raw_size == 8 && !mips2_fp_compat ())
2974 /* We have a 64-bit value for this register, and we should use
2976 if (!frame_register_read (selected_frame, regno, rare_buffer))
2977 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
2981 if ((regno - FP0_REGNUM) & 1)
2982 internal_error (__FILE__, __LINE__,
2983 "mips_read_fp_register_double: bad access to "
2984 "odd-numbered FP register");
2986 /* mips_read_fp_register_single will find the correct 32 bits from
2988 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2990 mips_read_fp_register_single (regno, rare_buffer + 4);
2991 mips_read_fp_register_single (regno + 1, rare_buffer);
2995 mips_read_fp_register_single (regno, rare_buffer);
2996 mips_read_fp_register_single (regno + 1, rare_buffer + 4);
3002 mips_print_register (int regnum, int all)
3004 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3006 /* Get the data in raw format. */
3007 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3009 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
3013 /* If we have a actual 32-bit floating point register (or we are in
3014 32-bit compatibility mode), and the register is even-numbered,
3015 also print it as a double (spanning two registers). */
3016 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
3017 && (REGISTER_RAW_SIZE (regnum) == 4
3018 || mips2_fp_compat ())
3019 && !((regnum - FP0_REGNUM) & 1))
3021 char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
3023 mips_read_fp_register_double (regnum, dbuffer);
3025 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
3026 val_print (mips_double_register_type (), dbuffer, 0, 0,
3027 gdb_stdout, 0, 1, 0, Val_pretty_default);
3028 printf_filtered ("); ");
3030 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3032 /* The problem with printing numeric register names (r26, etc.) is that
3033 the user can't use them on input. Probably the best solution is to
3034 fix it so that either the numeric or the funky (a2, etc.) names
3035 are accepted on input. */
3036 if (regnum < MIPS_NUMREGS)
3037 printf_filtered ("(r%d): ", regnum);
3039 printf_filtered (": ");
3041 /* If virtual format is floating, print it that way. */
3042 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3043 if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
3045 /* We have a meaningful 64-bit value in this register. Show
3046 it as a 32-bit float and a 64-bit double. */
3047 int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
3049 printf_filtered (" (float) ");
3050 val_print (mips_float_register_type (), raw_buffer + offset, 0, 0,
3051 gdb_stdout, 0, 1, 0, Val_pretty_default);
3052 printf_filtered (", (double) ");
3053 val_print (mips_double_register_type (), raw_buffer, 0, 0,
3054 gdb_stdout, 0, 1, 0, Val_pretty_default);
3057 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
3058 gdb_stdout, 0, 1, 0, Val_pretty_default);
3059 /* Else print as integer in hex. */
3064 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3065 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
3069 print_scalar_formatted (raw_buffer + offset,
3070 REGISTER_VIRTUAL_TYPE (regnum),
3071 'x', 0, gdb_stdout);
3075 /* Replacement for generic do_registers_info.
3076 Print regs in pretty columns. */
3079 do_fp_register_row (int regnum)
3080 { /* do values for FP (float) regs */
3082 double doub, flt1, flt2; /* doubles extracted from raw hex data */
3083 int inv1, inv2, inv3;
3085 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
3087 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
3089 /* 4-byte registers: we can fit two registers per row. */
3090 /* Also print every pair of 4-byte regs as an 8-byte double. */
3091 mips_read_fp_register_single (regnum, raw_buffer);
3092 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
3094 mips_read_fp_register_single (regnum + 1, raw_buffer);
3095 flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2);
3097 mips_read_fp_register_double (regnum, raw_buffer);
3098 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
3100 printf_filtered (" %-5s", REGISTER_NAME (regnum));
3102 printf_filtered (": <invalid float>");
3104 printf_filtered ("%-17.9g", flt1);
3106 printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
3108 printf_filtered (": <invalid float>");
3110 printf_filtered ("%-17.9g", flt2);
3112 printf_filtered (" dbl: ");
3114 printf_filtered ("<invalid double>");
3116 printf_filtered ("%-24.17g", doub);
3117 printf_filtered ("\n");
3119 /* may want to do hex display here (future enhancement) */
3124 /* Eight byte registers: print each one as float AND as double. */
3125 mips_read_fp_register_single (regnum, raw_buffer);
3126 flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1);
3128 mips_read_fp_register_double (regnum, raw_buffer);
3129 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
3131 printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
3133 printf_filtered ("<invalid float>");
3135 printf_filtered ("flt: %-17.9g", flt1);
3137 printf_filtered (" dbl: ");
3139 printf_filtered ("<invalid double>");
3141 printf_filtered ("%-24.17g", doub);
3143 printf_filtered ("\n");
3144 /* may want to do hex display here (future enhancement) */
3150 /* Print a row's worth of GP (int) registers, with name labels above */
3153 do_gp_register_row (int regnum)
3155 /* do values for GP (int) regs */
3156 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3157 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
3159 int start_regnum = regnum;
3160 int numregs = NUM_REGS;
3163 /* For GP registers, we print a separate row of names above the vals */
3164 printf_filtered (" ");
3165 for (col = 0; col < ncols && regnum < numregs; regnum++)
3167 if (*REGISTER_NAME (regnum) == '\0')
3168 continue; /* unused register */
3169 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3170 break; /* end the row: reached FP register */
3171 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
3172 REGISTER_NAME (regnum));
3175 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
3176 start_regnum); /* print the R0 to R31 names */
3178 regnum = start_regnum; /* go back to start of row */
3179 /* now print the values in hex, 4 or 8 to the row */
3180 for (col = 0; col < ncols && regnum < numregs; regnum++)
3182 if (*REGISTER_NAME (regnum) == '\0')
3183 continue; /* unused register */
3184 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3185 break; /* end row: reached FP register */
3186 /* OK: get the data in raw format. */
3187 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3188 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3189 /* pad small registers */
3190 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
3191 printf_filtered (" ");
3192 /* Now print the register value in hex, endian order. */
3193 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3194 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
3195 byte < REGISTER_RAW_SIZE (regnum);
3197 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
3199 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
3202 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
3203 printf_filtered (" ");
3206 if (col > 0) /* ie. if we actually printed anything... */
3207 printf_filtered ("\n");
3212 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3215 mips_do_registers_info (int regnum, int fpregs)
3217 if (regnum != -1) /* do one specified register */
3219 if (*(REGISTER_NAME (regnum)) == '\0')
3220 error ("Not a valid register for the current processor type");
3222 mips_print_register (regnum, 0);
3223 printf_filtered ("\n");
3226 /* do all (or most) registers */
3229 while (regnum < NUM_REGS)
3231 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3232 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
3233 regnum = do_fp_register_row (regnum); /* FP regs */
3235 regnum += MIPS_NUMREGS; /* skip floating point regs */
3237 regnum = do_gp_register_row (regnum); /* GP (int) regs */
3242 /* Return number of args passed to a frame. described by FIP.
3243 Can return -1, meaning no way to tell. */
3246 mips_frame_num_args (struct frame_info *frame)
3251 /* Is this a branch with a delay slot? */
3253 static int is_delayed (unsigned long);
3256 is_delayed (unsigned long insn)
3259 for (i = 0; i < NUMOPCODES; ++i)
3260 if (mips_opcodes[i].pinfo != INSN_MACRO
3261 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
3263 return (i < NUMOPCODES
3264 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
3265 | INSN_COND_BRANCH_DELAY
3266 | INSN_COND_BRANCH_LIKELY)));
3270 mips_step_skips_delay (CORE_ADDR pc)
3272 char buf[MIPS_INSTLEN];
3274 /* There is no branch delay slot on MIPS16. */
3275 if (pc_is_mips16 (pc))
3278 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
3279 /* If error reading memory, guess that it is not a delayed branch. */
3281 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
3285 /* Skip the PC past function prologue instructions (32-bit version).
3286 This is a helper function for mips_skip_prologue. */
3289 mips32_skip_prologue (CORE_ADDR pc)
3293 int seen_sp_adjust = 0;
3294 int load_immediate_bytes = 0;
3296 /* Skip the typical prologue instructions. These are the stack adjustment
3297 instruction and the instructions that save registers on the stack
3298 or in the gcc frame. */
3299 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
3301 unsigned long high_word;
3303 inst = mips_fetch_instruction (pc);
3304 high_word = (inst >> 16) & 0xffff;
3306 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
3307 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
3309 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
3310 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
3312 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3313 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3314 && (inst & 0x001F0000)) /* reg != $zero */
3317 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3319 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
3321 continue; /* reg != $zero */
3323 /* move $s8,$sp. With different versions of gas this will be either
3324 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3325 Accept any one of these. */
3326 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3329 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3331 else if (high_word == 0x3c1c) /* lui $gp,n */
3333 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
3335 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3336 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
3338 /* The following instructions load $at or $t0 with an immediate
3339 value in preparation for a stack adjustment via
3340 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3341 a local variable, so we accept them only before a stack adjustment
3342 instruction was seen. */
3343 else if (!seen_sp_adjust)
3345 if (high_word == 0x3c01 || /* lui $at,n */
3346 high_word == 0x3c08) /* lui $t0,n */
3348 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
3351 else if (high_word == 0x3421 || /* ori $at,$at,n */
3352 high_word == 0x3508 || /* ori $t0,$t0,n */
3353 high_word == 0x3401 || /* ori $at,$zero,n */
3354 high_word == 0x3408) /* ori $t0,$zero,n */
3356 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
3366 /* In a frameless function, we might have incorrectly
3367 skipped some load immediate instructions. Undo the skipping
3368 if the load immediate was not followed by a stack adjustment. */
3369 if (load_immediate_bytes && !seen_sp_adjust)
3370 pc -= load_immediate_bytes;
3374 /* Skip the PC past function prologue instructions (16-bit version).
3375 This is a helper function for mips_skip_prologue. */
3378 mips16_skip_prologue (CORE_ADDR pc)
3381 int extend_bytes = 0;
3382 int prev_extend_bytes;
3384 /* Table of instructions likely to be found in a function prologue. */
3387 unsigned short inst;
3388 unsigned short mask;
3395 , /* addiu $sp,offset */
3399 , /* daddiu $sp,offset */
3403 , /* sw reg,n($sp) */
3407 , /* sd reg,n($sp) */
3411 , /* sw $ra,n($sp) */
3415 , /* sd $ra,n($sp) */
3423 , /* sw $a0-$a3,n($s1) */
3427 , /* move reg,$a0-$a3 */
3431 , /* entry pseudo-op */
3435 , /* addiu $s1,$sp,n */
3438 } /* end of table marker */
3441 /* Skip the typical prologue instructions. These are the stack adjustment
3442 instruction and the instructions that save registers on the stack
3443 or in the gcc frame. */
3444 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
3446 unsigned short inst;
3449 inst = mips_fetch_instruction (pc);
3451 /* Normally we ignore an extend instruction. However, if it is
3452 not followed by a valid prologue instruction, we must adjust
3453 the pc back over the extend so that it won't be considered
3454 part of the prologue. */
3455 if ((inst & 0xf800) == 0xf000) /* extend */
3457 extend_bytes = MIPS16_INSTLEN;
3460 prev_extend_bytes = extend_bytes;
3463 /* Check for other valid prologue instructions besides extend. */
3464 for (i = 0; table[i].mask != 0; i++)
3465 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
3467 if (table[i].mask != 0) /* it was in table? */
3468 continue; /* ignore it */
3472 /* Return the current pc, adjusted backwards by 2 if
3473 the previous instruction was an extend. */
3474 return pc - prev_extend_bytes;
3480 /* To skip prologues, I use this predicate. Returns either PC itself
3481 if the code at PC does not look like a function prologue; otherwise
3482 returns an address that (if we're lucky) follows the prologue. If
3483 LENIENT, then we must skip everything which is involved in setting
3484 up the frame (it's OK to skip more, just so long as we don't skip
3485 anything which might clobber the registers which are being saved.
3486 We must skip more in the case where part of the prologue is in the
3487 delay slot of a non-prologue instruction). */
3490 mips_skip_prologue (CORE_ADDR pc)
3492 /* See if we can determine the end of the prologue via the symbol table.
3493 If so, then return either PC, or the PC after the prologue, whichever
3496 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
3498 if (post_prologue_pc != 0)
3499 return max (pc, post_prologue_pc);
3501 /* Can't determine prologue from the symbol table, need to examine
3504 if (pc_is_mips16 (pc))
3505 return mips16_skip_prologue (pc);
3507 return mips32_skip_prologue (pc);
3510 /* Determine how a return value is stored within the MIPS register
3511 file, given the return type `valtype'. */
3513 struct return_value_word
3522 return_value_location (struct type *valtype,
3523 struct return_value_word *hi,
3524 struct return_value_word *lo)
3526 int len = TYPE_LENGTH (valtype);
3528 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
3529 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
3530 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
3532 if (!FP_REGISTER_DOUBLE && len == 8)
3534 /* We need to break a 64bit float in two 32 bit halves and
3535 spread them across a floating-point register pair. */
3536 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3537 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
3538 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3539 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
3541 hi->reg_offset = lo->reg_offset;
3542 lo->reg = FP0_REGNUM + 0;
3543 hi->reg = FP0_REGNUM + 1;
3549 /* The floating point value fits in a single floating-point
3551 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3552 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
3555 lo->reg = FP0_REGNUM;
3566 /* Locate a result possibly spread across two registers. */
3568 lo->reg = regnum + 0;
3569 hi->reg = regnum + 1;
3570 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3571 && len < MIPS_SAVED_REGSIZE)
3573 /* "un-left-justify" the value in the low register */
3574 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
3579 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3580 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
3581 && len < MIPS_SAVED_REGSIZE * 2
3582 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
3583 TYPE_CODE (valtype) == TYPE_CODE_UNION))
3585 /* "un-left-justify" the value spread across two registers. */
3586 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
3587 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
3589 hi->len = len - lo->len;
3593 /* Only perform a partial copy of the second register. */
3596 if (len > MIPS_SAVED_REGSIZE)
3598 lo->len = MIPS_SAVED_REGSIZE;
3599 hi->len = len - MIPS_SAVED_REGSIZE;
3607 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3608 && REGISTER_RAW_SIZE (regnum) == 8
3609 && MIPS_SAVED_REGSIZE == 4)
3611 /* Account for the fact that only the least-signficant part
3612 of the register is being used */
3613 lo->reg_offset += 4;
3614 hi->reg_offset += 4;
3617 hi->buf_offset = lo->len;
3621 /* Given a return value in `regbuf' with a type `valtype', extract and
3622 copy its value into `valbuf'. */
3625 mips_extract_return_value (struct type *valtype,
3626 char regbuf[REGISTER_BYTES],
3629 struct return_value_word lo;
3630 struct return_value_word hi;
3631 return_value_location (valtype, &hi, &lo);
3633 memcpy (valbuf + lo.buf_offset,
3634 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
3638 memcpy (valbuf + hi.buf_offset,
3639 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
3643 /* Given a return value in `valbuf' with a type `valtype', write it's
3644 value into the appropriate register. */
3647 mips_store_return_value (struct type *valtype, char *valbuf)
3649 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3650 struct return_value_word lo;
3651 struct return_value_word hi;
3652 return_value_location (valtype, &hi, &lo);
3654 memset (raw_buffer, 0, sizeof (raw_buffer));
3655 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
3656 write_register_bytes (REGISTER_BYTE (lo.reg),
3658 REGISTER_RAW_SIZE (lo.reg));
3662 memset (raw_buffer, 0, sizeof (raw_buffer));
3663 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
3664 write_register_bytes (REGISTER_BYTE (hi.reg),
3666 REGISTER_RAW_SIZE (hi.reg));
3670 /* Exported procedure: Is PC in the signal trampoline code */
3673 in_sigtramp (CORE_ADDR pc, char *ignore)
3675 if (sigtramp_address == 0)
3677 return (pc >= sigtramp_address && pc < sigtramp_end);
3680 /* Root of all "set mips "/"show mips " commands. This will eventually be
3681 used for all MIPS-specific commands. */
3684 show_mips_command (char *args, int from_tty)
3686 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
3690 set_mips_command (char *args, int from_tty)
3692 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3693 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
3696 /* Commands to show/set the MIPS FPU type. */
3699 show_mipsfpu_command (char *args, int from_tty)
3702 switch (MIPS_FPU_TYPE)
3704 case MIPS_FPU_SINGLE:
3705 fpu = "single-precision";
3707 case MIPS_FPU_DOUBLE:
3708 fpu = "double-precision";
3711 fpu = "absent (none)";
3714 internal_error (__FILE__, __LINE__, "bad switch");
3716 if (mips_fpu_type_auto)
3717 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3720 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3726 set_mipsfpu_command (char *args, int from_tty)
3728 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3729 show_mipsfpu_command (args, from_tty);
3733 set_mipsfpu_single_command (char *args, int from_tty)
3735 mips_fpu_type = MIPS_FPU_SINGLE;
3736 mips_fpu_type_auto = 0;
3737 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
3741 set_mipsfpu_double_command (char *args, int from_tty)
3743 mips_fpu_type = MIPS_FPU_DOUBLE;
3744 mips_fpu_type_auto = 0;
3745 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
3749 set_mipsfpu_none_command (char *args, int from_tty)
3751 mips_fpu_type = MIPS_FPU_NONE;
3752 mips_fpu_type_auto = 0;
3753 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
3757 set_mipsfpu_auto_command (char *args, int from_tty)
3759 mips_fpu_type_auto = 1;
3762 /* Command to set the processor type. */
3765 mips_set_processor_type_command (char *args, int from_tty)
3769 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
3771 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3772 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3773 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
3775 /* Restore the value. */
3776 tmp_mips_processor_type = xstrdup (mips_processor_type);
3781 if (!mips_set_processor_type (tmp_mips_processor_type))
3783 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
3784 /* Restore its value. */
3785 tmp_mips_processor_type = xstrdup (mips_processor_type);
3790 mips_show_processor_type_command (char *args, int from_tty)
3794 /* Modify the actual processor type. */
3797 mips_set_processor_type (char *str)
3804 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3806 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
3808 mips_processor_type = str;
3809 mips_processor_reg_names = mips_processor_type_table[i].regnames;
3811 /* FIXME tweak fpu flag too */
3818 /* Attempt to identify the particular processor model by reading the
3822 mips_read_processor_type (void)
3826 prid = read_register (PRID_REGNUM);
3828 if ((prid & ~0xf) == 0x700)
3829 return savestring ("r3041", strlen ("r3041"));
3834 /* Just like reinit_frame_cache, but with the right arguments to be
3835 callable as an sfunc. */
3838 reinit_frame_cache_sfunc (char *args, int from_tty,
3839 struct cmd_list_element *c)
3841 reinit_frame_cache ();
3845 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
3847 mips_extra_func_info_t proc_desc;
3849 /* Search for the function containing this address. Set the low bit
3850 of the address when searching, in case we were given an even address
3851 that is the start of a 16-bit function. If we didn't do this,
3852 the search would fail because the symbol table says the function
3853 starts at an odd address, i.e. 1 byte past the given address. */
3854 memaddr = ADDR_BITS_REMOVE (memaddr);
3855 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
3857 /* Make an attempt to determine if this is a 16-bit function. If
3858 the procedure descriptor exists and the address therein is odd,
3859 it's definitely a 16-bit function. Otherwise, we have to just
3860 guess that if the address passed in is odd, it's 16-bits. */
3862 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
3863 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
3865 info->mach = pc_is_mips16 (memaddr) ?
3866 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
3868 /* Round down the instruction address to the appropriate boundary. */
3869 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
3871 /* Call the appropriate disassembler based on the target endian-ness. */
3872 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3873 return print_insn_big_mips (memaddr, info);
3875 return print_insn_little_mips (memaddr, info);
3878 /* Old-style breakpoint macros.
3879 The IDT board uses an unusual breakpoint value, and sometimes gets
3880 confused when it sees the usual MIPS breakpoint instruction. */
3882 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3883 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3884 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3885 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3886 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3887 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3888 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3889 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3891 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3892 counter value to determine whether a 16- or 32-bit breakpoint should be
3893 used. It returns a pointer to a string of bytes that encode a breakpoint
3894 instruction, stores the length of the string to *lenptr, and adjusts pc
3895 (if necessary) to point to the actual memory location where the
3896 breakpoint should be inserted. */
3898 const unsigned char *
3899 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
3901 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3903 if (pc_is_mips16 (*pcptr))
3905 static unsigned char mips16_big_breakpoint[] =
3906 MIPS16_BIG_BREAKPOINT;
3907 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
3908 *lenptr = sizeof (mips16_big_breakpoint);
3909 return mips16_big_breakpoint;
3913 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
3914 static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
3915 static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
3917 *lenptr = sizeof (big_breakpoint);
3919 if (strcmp (target_shortname, "mips") == 0)
3920 return idt_big_breakpoint;
3921 else if (strcmp (target_shortname, "ddb") == 0
3922 || strcmp (target_shortname, "pmon") == 0
3923 || strcmp (target_shortname, "lsi") == 0)
3924 return pmon_big_breakpoint;
3926 return big_breakpoint;
3931 if (pc_is_mips16 (*pcptr))
3933 static unsigned char mips16_little_breakpoint[] =
3934 MIPS16_LITTLE_BREAKPOINT;
3935 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
3936 *lenptr = sizeof (mips16_little_breakpoint);
3937 return mips16_little_breakpoint;
3941 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
3942 static unsigned char pmon_little_breakpoint[] =
3943 PMON_LITTLE_BREAKPOINT;
3944 static unsigned char idt_little_breakpoint[] =
3945 IDT_LITTLE_BREAKPOINT;
3947 *lenptr = sizeof (little_breakpoint);
3949 if (strcmp (target_shortname, "mips") == 0)
3950 return idt_little_breakpoint;
3951 else if (strcmp (target_shortname, "ddb") == 0
3952 || strcmp (target_shortname, "pmon") == 0
3953 || strcmp (target_shortname, "lsi") == 0)
3954 return pmon_little_breakpoint;
3956 return little_breakpoint;
3961 /* If PC is in a mips16 call or return stub, return the address of the target
3962 PC, which is either the callee or the caller. There are several
3963 cases which must be handled:
3965 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3966 target PC is in $31 ($ra).
3967 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3968 and the target PC is in $2.
3969 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3970 before the jal instruction, this is effectively a call stub
3971 and the the target PC is in $2. Otherwise this is effectively
3972 a return stub and the target PC is in $18.
3974 See the source code for the stubs in gcc/config/mips/mips16.S for
3977 This function implements the SKIP_TRAMPOLINE_CODE macro.
3981 mips_skip_stub (CORE_ADDR pc)
3984 CORE_ADDR start_addr;
3986 /* Find the starting address and name of the function containing the PC. */
3987 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
3990 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3991 target PC is in $31 ($ra). */
3992 if (strcmp (name, "__mips16_ret_sf") == 0
3993 || strcmp (name, "__mips16_ret_df") == 0)
3994 return read_signed_register (RA_REGNUM);
3996 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
3998 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3999 and the target PC is in $2. */
4000 if (name[19] >= '0' && name[19] <= '9')
4001 return read_signed_register (2);
4003 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4004 before the jal instruction, this is effectively a call stub
4005 and the the target PC is in $2. Otherwise this is effectively
4006 a return stub and the target PC is in $18. */
4007 else if (name[19] == 's' || name[19] == 'd')
4009 if (pc == start_addr)
4011 /* Check if the target of the stub is a compiler-generated
4012 stub. Such a stub for a function bar might have a name
4013 like __fn_stub_bar, and might look like this:
4018 la $1,bar (becomes a lui/addiu pair)
4020 So scan down to the lui/addi and extract the target
4021 address from those two instructions. */
4023 CORE_ADDR target_pc = read_signed_register (2);
4027 /* See if the name of the target function is __fn_stub_*. */
4028 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
4030 if (strncmp (name, "__fn_stub_", 10) != 0
4031 && strcmp (name, "etext") != 0
4032 && strcmp (name, "_etext") != 0)
4035 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4036 The limit on the search is arbitrarily set to 20
4037 instructions. FIXME. */
4038 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
4040 inst = mips_fetch_instruction (target_pc);
4041 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
4042 pc = (inst << 16) & 0xffff0000; /* high word */
4043 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
4044 return pc | (inst & 0xffff); /* low word */
4047 /* Couldn't find the lui/addui pair, so return stub address. */
4051 /* This is the 'return' part of a call stub. The return
4052 address is in $r18. */
4053 return read_signed_register (18);
4056 return 0; /* not a stub */
4060 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4061 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4064 mips_in_call_stub (CORE_ADDR pc, char *name)
4066 CORE_ADDR start_addr;
4068 /* Find the starting address of the function containing the PC. If the
4069 caller didn't give us a name, look it up at the same time. */
4070 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
4073 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
4075 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4076 if (name[19] >= '0' && name[19] <= '9')
4078 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4079 before the jal instruction, this is effectively a call stub. */
4080 else if (name[19] == 's' || name[19] == 'd')
4081 return pc == start_addr;
4084 return 0; /* not a stub */
4088 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4089 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4092 mips_in_return_stub (CORE_ADDR pc, char *name)
4094 CORE_ADDR start_addr;
4096 /* Find the starting address of the function containing the PC. */
4097 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
4100 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4101 if (strcmp (name, "__mips16_ret_sf") == 0
4102 || strcmp (name, "__mips16_ret_df") == 0)
4105 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4106 i.e. after the jal instruction, this is effectively a return stub. */
4107 if (strncmp (name, "__mips16_call_stub_", 19) == 0
4108 && (name[19] == 's' || name[19] == 'd')
4109 && pc != start_addr)
4112 return 0; /* not a stub */
4116 /* Return non-zero if the PC is in a library helper function that should
4117 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4120 mips_ignore_helper (CORE_ADDR pc)
4124 /* Find the starting address and name of the function containing the PC. */
4125 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
4128 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4129 that we want to ignore. */
4130 return (strcmp (name, "__mips16_ret_sf") == 0
4131 || strcmp (name, "__mips16_ret_df") == 0);
4135 /* Return a location where we can set a breakpoint that will be hit
4136 when an inferior function call returns. This is normally the
4137 program's entry point. Executables that don't have an entry
4138 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4139 whose address is the location where the breakpoint should be placed. */
4142 mips_call_dummy_address (void)
4144 struct minimal_symbol *sym;
4146 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
4148 return SYMBOL_VALUE_ADDRESS (sym);
4150 return entry_point_address ();
4154 /* If the current gcc for this target does not produce correct debugging
4155 information for float parameters, both prototyped and unprototyped, then
4156 define this macro. This forces gdb to always assume that floats are
4157 passed as doubles and then converted in the callee.
4159 For the mips chip, it appears that the debug info marks the parameters as
4160 floats regardless of whether the function is prototyped, but the actual
4161 values are passed as doubles for the non-prototyped case and floats for
4162 the prototyped case. Thus we choose to make the non-prototyped case work
4163 for C and break the prototyped case, since the non-prototyped case is
4164 probably much more common. (FIXME). */
4167 mips_coerce_float_to_double (struct type *formal, struct type *actual)
4169 return current_language->la_language == language_c;
4172 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4173 the register stored on the stack (32) is different to its real raw
4174 size (64). The below ensures that registers are fetched from the
4175 stack using their ABI size and then stored into the RAW_BUFFER
4176 using their raw size.
4178 The alternative to adding this function would be to add an ABI
4179 macro - REGISTER_STACK_SIZE(). */
4182 mips_get_saved_register (char *raw_buffer,
4185 struct frame_info *frame,
4187 enum lval_type *lval)
4191 if (!target_has_registers)
4192 error ("No registers.");
4194 /* Normal systems don't optimize out things with register numbers. */
4195 if (optimized != NULL)
4197 addr = find_saved_register (frame, regnum);
4201 *lval = lval_memory;
4202 if (regnum == SP_REGNUM)
4204 if (raw_buffer != NULL)
4206 /* Put it back in target format. */
4207 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
4214 if (raw_buffer != NULL)
4218 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4220 val = read_memory_integer (addr, MIPS_SAVED_REGSIZE);
4222 val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum));
4223 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
4229 *lval = lval_register;
4230 addr = REGISTER_BYTE (regnum);
4231 if (raw_buffer != NULL)
4232 read_register_gen (regnum, raw_buffer);
4238 /* Immediately after a function call, return the saved pc.
4239 Can't always go through the frames for this because on some machines
4240 the new frame is not set up until the new function executes
4241 some instructions. */
4244 mips_saved_pc_after_call (struct frame_info *frame)
4246 return read_signed_register (RA_REGNUM);
4250 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4254 mips_stab_reg_to_regnum (int num)
4259 return num + FP0_REGNUM - 38;
4262 /* Convert a ecoff register number to a gdb REGNUM */
4265 mips_ecoff_reg_to_regnum (int num)
4270 return num + FP0_REGNUM - 32;
4273 /* Convert an integer into an address. By first converting the value
4274 into a pointer and then extracting it signed, the address is
4275 guarenteed to be correctly sign extended. */
4278 mips_integer_to_address (struct type *type, void *buf)
4280 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
4281 LONGEST val = unpack_long (type, buf);
4282 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
4283 return extract_signed_integer (tmp,
4284 TYPE_LENGTH (builtin_type_void_data_ptr));
4288 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
4290 enum mips_abi *abip = (enum mips_abi *) obj;
4291 const char *name = bfd_get_section_name (abfd, sect);
4293 if (*abip != MIPS_ABI_UNKNOWN)
4296 if (strncmp (name, ".mdebug.", 8) != 0)
4299 if (strcmp (name, ".mdebug.abi32") == 0)
4300 *abip = MIPS_ABI_O32;
4301 else if (strcmp (name, ".mdebug.abiN32") == 0)
4302 *abip = MIPS_ABI_N32;
4303 else if (strcmp (name, ".mdebug.abiN64") == 0)
4304 *abip = MIPS_ABI_N64;
4305 else if (strcmp (name, ".mdebug.abiO64") == 0)
4306 *abip = MIPS_ABI_O64;
4307 else if (strcmp (name, ".mdebug.eabi32") == 0)
4308 *abip = MIPS_ABI_EABI32;
4309 else if (strcmp (name, ".mdebug.eabi64") == 0)
4310 *abip = MIPS_ABI_EABI64;
4312 warning ("unsupported ABI %s.", name + 8);
4315 static enum mips_abi
4316 global_mips_abi (void)
4320 for (i = 0; mips_abi_strings[i] != NULL; i++)
4321 if (mips_abi_strings[i] == mips_abi_string)
4322 return (enum mips_abi) i;
4324 internal_error (__FILE__, __LINE__,
4325 "unknown ABI string");
4328 static struct gdbarch *
4329 mips_gdbarch_init (struct gdbarch_info info,
4330 struct gdbarch_list *arches)
4332 static LONGEST mips_call_dummy_words[] =
4334 struct gdbarch *gdbarch;
4335 struct gdbarch_tdep *tdep;
4337 enum mips_abi mips_abi, found_abi, wanted_abi;
4338 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
4340 /* Reset the disassembly info, in case it was set to something
4342 tm_print_insn_info.flavour = bfd_target_unknown_flavour;
4343 tm_print_insn_info.arch = bfd_arch_unknown;
4344 tm_print_insn_info.mach = 0;
4350 /* First of all, extract the elf_flags, if available. */
4351 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
4352 elf_flags = elf_elfheader (info.abfd)->e_flags;
4354 /* Try to determine the OS ABI of the object we are loading. If
4355 we end up with `unknown', just leave it that way. */
4356 osabi = gdbarch_lookup_osabi (info.abfd);
4359 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4360 switch ((elf_flags & EF_MIPS_ABI))
4362 case E_MIPS_ABI_O32:
4363 mips_abi = MIPS_ABI_O32;
4365 case E_MIPS_ABI_O64:
4366 mips_abi = MIPS_ABI_O64;
4368 case E_MIPS_ABI_EABI32:
4369 mips_abi = MIPS_ABI_EABI32;
4371 case E_MIPS_ABI_EABI64:
4372 mips_abi = MIPS_ABI_EABI64;
4375 if ((elf_flags & EF_MIPS_ABI2))
4376 mips_abi = MIPS_ABI_N32;
4378 mips_abi = MIPS_ABI_UNKNOWN;
4382 /* GCC creates a pseudo-section whose name describes the ABI. */
4383 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
4384 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
4386 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
4387 Use the ABI from the last architecture if there is one. */
4388 if (info.abfd == NULL && arches != NULL)
4389 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
4391 /* Try the architecture for any hint of the correct ABI. */
4392 if (mips_abi == MIPS_ABI_UNKNOWN
4393 && info.bfd_arch_info != NULL
4394 && info.bfd_arch_info->arch == bfd_arch_mips)
4396 switch (info.bfd_arch_info->mach)
4398 case bfd_mach_mips3900:
4399 mips_abi = MIPS_ABI_EABI32;
4401 case bfd_mach_mips4100:
4402 case bfd_mach_mips5000:
4403 mips_abi = MIPS_ABI_EABI64;
4405 case bfd_mach_mips8000:
4406 case bfd_mach_mips10000:
4407 /* On Irix, ELF64 executables use the N64 ABI. The
4408 pseudo-sections which describe the ABI aren't present
4409 on IRIX. (Even for executables created by gcc.) */
4410 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
4411 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
4412 mips_abi = MIPS_ABI_N64;
4414 mips_abi = MIPS_ABI_N32;
4419 #ifdef MIPS_DEFAULT_ABI
4420 if (mips_abi == MIPS_ABI_UNKNOWN)
4421 mips_abi = MIPS_DEFAULT_ABI;
4424 if (mips_abi == MIPS_ABI_UNKNOWN)
4425 mips_abi = MIPS_ABI_O32;
4427 /* Now that we have found what the ABI for this binary would be,
4428 check whether the user is overriding it. */
4429 found_abi = mips_abi;
4430 wanted_abi = global_mips_abi ();
4431 if (wanted_abi != MIPS_ABI_UNKNOWN)
4432 mips_abi = wanted_abi;
4436 fprintf_unfiltered (gdb_stdlog,
4437 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4439 fprintf_unfiltered (gdb_stdlog,
4440 "mips_gdbarch_init: mips_abi = %d\n",
4442 fprintf_unfiltered (gdb_stdlog,
4443 "mips_gdbarch_init: found_mips_abi = %d\n",
4447 /* try to find a pre-existing architecture */
4448 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4450 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4452 /* MIPS needs to be pedantic about which ABI the object is
4454 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
4456 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
4458 if (gdbarch_tdep (arches->gdbarch)->osabi == osabi)
4459 return arches->gdbarch;
4462 /* Need a new architecture. Fill in a target specific vector. */
4463 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4464 gdbarch = gdbarch_alloc (&info, tdep);
4465 tdep->elf_flags = elf_flags;
4466 tdep->osabi = osabi;
4468 /* Initially set everything according to the default ABI/ISA. */
4469 set_gdbarch_short_bit (gdbarch, 16);
4470 set_gdbarch_int_bit (gdbarch, 32);
4471 set_gdbarch_float_bit (gdbarch, 32);
4472 set_gdbarch_double_bit (gdbarch, 64);
4473 set_gdbarch_long_double_bit (gdbarch, 64);
4474 set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size);
4475 tdep->found_abi = found_abi;
4476 tdep->mips_abi = mips_abi;
4481 tdep->mips_default_saved_regsize = 4;
4482 tdep->mips_default_stack_argsize = 4;
4483 tdep->mips_fp_register_double = 0;
4484 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
4485 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
4486 tdep->mips_regs_have_home_p = 1;
4487 tdep->gdb_target_is_mips64 = 0;
4488 tdep->default_mask_address_p = 0;
4489 set_gdbarch_long_bit (gdbarch, 32);
4490 set_gdbarch_ptr_bit (gdbarch, 32);
4491 set_gdbarch_long_long_bit (gdbarch, 64);
4494 tdep->mips_default_saved_regsize = 8;
4495 tdep->mips_default_stack_argsize = 8;
4496 tdep->mips_fp_register_double = 1;
4497 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
4498 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
4499 tdep->mips_regs_have_home_p = 1;
4500 tdep->gdb_target_is_mips64 = 1;
4501 tdep->default_mask_address_p = 0;
4502 set_gdbarch_long_bit (gdbarch, 32);
4503 set_gdbarch_ptr_bit (gdbarch, 32);
4504 set_gdbarch_long_long_bit (gdbarch, 64);
4506 case MIPS_ABI_EABI32:
4507 tdep->mips_default_saved_regsize = 4;
4508 tdep->mips_default_stack_argsize = 4;
4509 tdep->mips_fp_register_double = 0;
4510 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4511 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4512 tdep->mips_regs_have_home_p = 0;
4513 tdep->gdb_target_is_mips64 = 0;
4514 tdep->default_mask_address_p = 0;
4515 set_gdbarch_long_bit (gdbarch, 32);
4516 set_gdbarch_ptr_bit (gdbarch, 32);
4517 set_gdbarch_long_long_bit (gdbarch, 64);
4519 case MIPS_ABI_EABI64:
4520 tdep->mips_default_saved_regsize = 8;
4521 tdep->mips_default_stack_argsize = 8;
4522 tdep->mips_fp_register_double = 1;
4523 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4524 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4525 tdep->mips_regs_have_home_p = 0;
4526 tdep->gdb_target_is_mips64 = 1;
4527 tdep->default_mask_address_p = 0;
4528 set_gdbarch_long_bit (gdbarch, 64);
4529 set_gdbarch_ptr_bit (gdbarch, 64);
4530 set_gdbarch_long_long_bit (gdbarch, 64);
4533 tdep->mips_default_saved_regsize = 8;
4534 tdep->mips_default_stack_argsize = 8;
4535 tdep->mips_fp_register_double = 1;
4536 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4537 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4538 tdep->mips_regs_have_home_p = 0;
4539 tdep->gdb_target_is_mips64 = 1;
4540 tdep->default_mask_address_p = 0;
4541 set_gdbarch_long_bit (gdbarch, 32);
4542 set_gdbarch_ptr_bit (gdbarch, 32);
4543 set_gdbarch_long_long_bit (gdbarch, 64);
4545 /* Set up the disassembler info, so that we get the right
4546 register names from libopcodes. */
4547 tm_print_insn_info.flavour = bfd_target_elf_flavour;
4548 tm_print_insn_info.arch = bfd_arch_mips;
4549 if (info.bfd_arch_info != NULL
4550 && info.bfd_arch_info->arch == bfd_arch_mips
4551 && info.bfd_arch_info->mach)
4552 tm_print_insn_info.mach = info.bfd_arch_info->mach;
4554 tm_print_insn_info.mach = bfd_mach_mips8000;
4557 tdep->mips_default_saved_regsize = 8;
4558 tdep->mips_default_stack_argsize = 8;
4559 tdep->mips_fp_register_double = 1;
4560 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4561 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4562 tdep->mips_regs_have_home_p = 0;
4563 tdep->gdb_target_is_mips64 = 1;
4564 tdep->default_mask_address_p = 0;
4565 set_gdbarch_long_bit (gdbarch, 64);
4566 set_gdbarch_ptr_bit (gdbarch, 64);
4567 set_gdbarch_long_long_bit (gdbarch, 64);
4569 /* Set up the disassembler info, so that we get the right
4570 register names from libopcodes. */
4571 tm_print_insn_info.flavour = bfd_target_elf_flavour;
4572 tm_print_insn_info.arch = bfd_arch_mips;
4573 if (info.bfd_arch_info != NULL
4574 && info.bfd_arch_info->arch == bfd_arch_mips
4575 && info.bfd_arch_info->mach)
4576 tm_print_insn_info.mach = info.bfd_arch_info->mach;
4578 tm_print_insn_info.mach = bfd_mach_mips8000;
4581 internal_error (__FILE__, __LINE__,
4582 "unknown ABI in switch");
4585 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4586 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4589 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4590 flag in object files because to do so would make it impossible to
4591 link with libraries compiled without "-gp32". This is
4592 unnecessarily restrictive.
4594 We could solve this problem by adding "-gp32" multilibs to gcc,
4595 but to set this flag before gcc is built with such multilibs will
4596 break too many systems.''
4598 But even more unhelpfully, the default linker output target for
4599 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4600 for 64-bit programs - you need to change the ABI to change this,
4601 and not all gcc targets support that currently. Therefore using
4602 this flag to detect 32-bit mode would do the wrong thing given
4603 the current gcc - it would make GDB treat these 64-bit programs
4604 as 32-bit programs by default. */
4606 /* enable/disable the MIPS FPU */
4607 if (!mips_fpu_type_auto)
4608 tdep->mips_fpu_type = mips_fpu_type;
4609 else if (info.bfd_arch_info != NULL
4610 && info.bfd_arch_info->arch == bfd_arch_mips)
4611 switch (info.bfd_arch_info->mach)
4613 case bfd_mach_mips3900:
4614 case bfd_mach_mips4100:
4615 case bfd_mach_mips4111:
4616 tdep->mips_fpu_type = MIPS_FPU_NONE;
4618 case bfd_mach_mips4650:
4619 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
4622 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
4626 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
4628 /* MIPS version of register names. NOTE: At present the MIPS
4629 register name management is part way between the old -
4630 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4631 Further work on it is required. */
4632 set_gdbarch_register_name (gdbarch, mips_register_name);
4633 set_gdbarch_read_pc (gdbarch, mips_read_pc);
4634 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4635 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
4636 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4637 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4639 /* Add/remove bits from an address. The MIPS needs be careful to
4640 ensure that all 32 bit addresses are sign extended to 64 bits. */
4641 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
4643 /* There's a mess in stack frame creation. See comments in
4644 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4645 set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
4646 set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop);
4648 /* Map debug register numbers onto internal register numbers. */
4649 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
4650 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum);
4652 /* Initialize a frame */
4653 set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
4655 /* MIPS version of CALL_DUMMY */
4657 set_gdbarch_call_dummy_p (gdbarch, 1);
4658 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
4659 set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
4660 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
4661 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
4662 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
4663 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
4664 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4665 set_gdbarch_call_dummy_length (gdbarch, 0);
4666 set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
4667 set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
4668 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
4669 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
4670 set_gdbarch_push_arguments (gdbarch, mips_push_arguments);
4671 set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not);
4672 set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double);
4674 set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
4675 set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
4677 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4678 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
4679 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4681 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
4682 set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
4684 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
4685 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
4686 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
4688 /* There are MIPS targets which do not yet use this since they still
4689 define REGISTER_VIRTUAL_TYPE. */
4690 set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type);
4692 /* Hook in OS ABI-specific overrides, if they have been registered. */
4693 gdbarch_init_osabi (info, gdbarch, osabi);
4699 mips_abi_update (char *ignore_args, int from_tty,
4700 struct cmd_list_element *c)
4702 struct gdbarch_info info;
4704 /* Force the architecture to update, and (if it's a MIPS architecture)
4705 mips_gdbarch_init will take care of the rest. */
4706 gdbarch_info_init (&info);
4707 gdbarch_update_p (info);
4711 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4713 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4717 int ef_mips_32bitmode;
4718 /* determine the ISA */
4719 switch (tdep->elf_flags & EF_MIPS_ARCH)
4737 /* determine the size of a pointer */
4738 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
4739 fprintf_unfiltered (file,
4740 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4742 fprintf_unfiltered (file,
4743 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4745 fprintf_unfiltered (file,
4746 "mips_dump_tdep: ef_mips_arch = %d\n",
4748 fprintf_unfiltered (file,
4749 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4751 mips_abi_strings[tdep->mips_abi]);
4752 fprintf_unfiltered (file,
4753 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4754 mips_mask_address_p (),
4755 tdep->default_mask_address_p);
4757 fprintf_unfiltered (file,
4758 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4759 FP_REGISTER_DOUBLE);
4760 fprintf_unfiltered (file,
4761 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4762 MIPS_DEFAULT_FPU_TYPE,
4763 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
4764 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
4765 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
4767 fprintf_unfiltered (file,
4768 "mips_dump_tdep: MIPS_EABI = %d\n",
4770 fprintf_unfiltered (file,
4771 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4772 MIPS_LAST_FP_ARG_REGNUM,
4773 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
4774 fprintf_unfiltered (file,
4775 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4777 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
4778 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
4779 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
4781 fprintf_unfiltered (file,
4782 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4783 MIPS_DEFAULT_SAVED_REGSIZE);
4784 fprintf_unfiltered (file,
4785 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4786 FP_REGISTER_DOUBLE);
4787 fprintf_unfiltered (file,
4788 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4789 MIPS_REGS_HAVE_HOME_P);
4790 fprintf_unfiltered (file,
4791 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4792 MIPS_DEFAULT_STACK_ARGSIZE);
4793 fprintf_unfiltered (file,
4794 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4795 MIPS_STACK_ARGSIZE);
4796 fprintf_unfiltered (file,
4797 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4799 fprintf_unfiltered (file,
4800 "mips_dump_tdep: A0_REGNUM = %d\n",
4802 fprintf_unfiltered (file,
4803 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4804 XSTRING (ADDR_BITS_REMOVE(ADDR)));
4805 fprintf_unfiltered (file,
4806 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4807 XSTRING (ATTACH_DETACH));
4808 fprintf_unfiltered (file,
4809 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4811 fprintf_unfiltered (file,
4812 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4813 fprintf_unfiltered (file,
4814 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4816 fprintf_unfiltered (file,
4817 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4819 fprintf_unfiltered (file,
4820 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4822 fprintf_unfiltered (file,
4823 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4824 XSTRING (DO_REGISTERS_INFO));
4825 fprintf_unfiltered (file,
4826 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4827 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
4828 fprintf_unfiltered (file,
4829 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4830 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
4831 fprintf_unfiltered (file,
4832 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4833 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM)));
4834 fprintf_unfiltered (file,
4835 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4837 fprintf_unfiltered (file,
4838 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4840 fprintf_unfiltered (file,
4841 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4842 FIRST_EMBED_REGNUM);
4843 fprintf_unfiltered (file,
4844 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4846 fprintf_unfiltered (file,
4847 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4848 GDB_TARGET_IS_MIPS64);
4849 fprintf_unfiltered (file,
4850 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4851 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC)));
4852 fprintf_unfiltered (file,
4853 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4854 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC)));
4855 fprintf_unfiltered (file,
4856 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4858 fprintf_unfiltered (file,
4859 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4860 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
4861 fprintf_unfiltered (file,
4862 "mips_dump_tdep: HI_REGNUM = %d\n",
4864 fprintf_unfiltered (file,
4865 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4866 fprintf_unfiltered (file,
4867 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4868 fprintf_unfiltered (file,
4869 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4870 XSTRING (IGNORE_HELPER_CALL (PC)));
4871 fprintf_unfiltered (file,
4872 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4873 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
4874 fprintf_unfiltered (file,
4875 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4876 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
4877 fprintf_unfiltered (file,
4878 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4879 fprintf_unfiltered (file,
4880 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4882 fprintf_unfiltered (file,
4883 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4884 fprintf_unfiltered (file,
4885 "mips_dump_tdep: LO_REGNUM = %d\n",
4887 #ifdef MACHINE_CPROC_FP_OFFSET
4888 fprintf_unfiltered (file,
4889 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4890 MACHINE_CPROC_FP_OFFSET);
4892 #ifdef MACHINE_CPROC_PC_OFFSET
4893 fprintf_unfiltered (file,
4894 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4895 MACHINE_CPROC_PC_OFFSET);
4897 #ifdef MACHINE_CPROC_SP_OFFSET
4898 fprintf_unfiltered (file,
4899 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4900 MACHINE_CPROC_SP_OFFSET);
4902 fprintf_unfiltered (file,
4903 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4904 fprintf_unfiltered (file,
4905 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4906 fprintf_unfiltered (file,
4907 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4909 fprintf_unfiltered (file,
4910 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4911 fprintf_unfiltered (file,
4912 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4913 fprintf_unfiltered (file,
4914 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4915 fprintf_unfiltered (file,
4916 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4918 fprintf_unfiltered (file,
4919 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4920 MIPS_LAST_ARG_REGNUM,
4921 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
4922 fprintf_unfiltered (file,
4923 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4925 fprintf_unfiltered (file,
4926 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4927 fprintf_unfiltered (file,
4928 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4929 MIPS_SAVED_REGSIZE);
4930 fprintf_unfiltered (file,
4931 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4932 fprintf_unfiltered (file,
4933 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4934 XSTRING (MSYMBOL_SIZE (MSYM)));
4935 fprintf_unfiltered (file,
4936 "mips_dump_tdep: OP_LDFPR = used?\n");
4937 fprintf_unfiltered (file,
4938 "mips_dump_tdep: OP_LDGPR = used?\n");
4939 fprintf_unfiltered (file,
4940 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4941 fprintf_unfiltered (file,
4942 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4943 fprintf_unfiltered (file,
4944 "mips_dump_tdep: PRID_REGNUM = %d\n",
4946 fprintf_unfiltered (file,
4947 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4948 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
4949 fprintf_unfiltered (file,
4950 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4951 fprintf_unfiltered (file,
4952 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4953 fprintf_unfiltered (file,
4954 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4955 fprintf_unfiltered (file,
4956 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4957 fprintf_unfiltered (file,
4958 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4959 fprintf_unfiltered (file,
4960 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4961 fprintf_unfiltered (file,
4962 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4963 fprintf_unfiltered (file,
4964 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4965 fprintf_unfiltered (file,
4966 "mips_dump_tdep: PROC_PC_REG = function?\n");
4967 fprintf_unfiltered (file,
4968 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4969 fprintf_unfiltered (file,
4970 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4971 fprintf_unfiltered (file,
4972 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4973 fprintf_unfiltered (file,
4974 "mips_dump_tdep: PS_REGNUM = %d\n",
4976 fprintf_unfiltered (file,
4977 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4979 fprintf_unfiltered (file,
4980 "mips_dump_tdep: RA_REGNUM = %d\n",
4982 fprintf_unfiltered (file,
4983 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4984 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
4985 fprintf_unfiltered (file,
4986 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4987 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
4988 fprintf_unfiltered (file,
4989 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4990 fprintf_unfiltered (file,
4991 "mips_dump_tdep: ROUND_DOWN = function?\n");
4992 fprintf_unfiltered (file,
4993 "mips_dump_tdep: ROUND_UP = function?\n");
4995 fprintf_unfiltered (file,
4996 "mips_dump_tdep: SAVED_BYTES = %d\n",
5000 fprintf_unfiltered (file,
5001 "mips_dump_tdep: SAVED_FP = %d\n",
5005 fprintf_unfiltered (file,
5006 "mips_dump_tdep: SAVED_PC = %d\n",
5009 fprintf_unfiltered (file,
5010 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5011 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
5012 fprintf_unfiltered (file,
5013 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
5014 fprintf_unfiltered (file,
5015 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
5017 fprintf_unfiltered (file,
5018 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
5019 SIGFRAME_FPREGSAVE_OFF);
5020 fprintf_unfiltered (file,
5021 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
5023 fprintf_unfiltered (file,
5024 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
5025 SIGFRAME_REGSAVE_OFF);
5026 fprintf_unfiltered (file,
5027 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
5029 fprintf_unfiltered (file,
5030 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
5031 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
5032 fprintf_unfiltered (file,
5033 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5034 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
5035 fprintf_unfiltered (file,
5036 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5037 SOFTWARE_SINGLE_STEP_P ());
5038 fprintf_unfiltered (file,
5039 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5040 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
5041 #ifdef STACK_END_ADDR
5042 fprintf_unfiltered (file,
5043 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5046 fprintf_unfiltered (file,
5047 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5048 XSTRING (STEP_SKIPS_DELAY (PC)));
5049 fprintf_unfiltered (file,
5050 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5051 STEP_SKIPS_DELAY_P);
5052 fprintf_unfiltered (file,
5053 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5054 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
5055 fprintf_unfiltered (file,
5056 "mips_dump_tdep: T9_REGNUM = %d\n",
5058 fprintf_unfiltered (file,
5059 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5060 fprintf_unfiltered (file,
5061 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5062 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
5063 fprintf_unfiltered (file,
5064 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
5065 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
5066 fprintf_unfiltered (file,
5067 "mips_dump_tdep: TARGET_MIPS = used?\n");
5068 fprintf_unfiltered (file,
5069 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
5070 XSTRING (TM_PRINT_INSN_MACH));
5072 fprintf_unfiltered (file,
5073 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5074 XSTRING (TRACE_CLEAR (THREAD, STATE)));
5077 fprintf_unfiltered (file,
5078 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
5081 #ifdef TRACE_FLAVOR_SIZE
5082 fprintf_unfiltered (file,
5083 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5087 fprintf_unfiltered (file,
5088 "mips_dump_tdep: TRACE_SET # %s\n",
5089 XSTRING (TRACE_SET (X,STATE)));
5091 fprintf_unfiltered (file,
5092 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
5093 #ifdef UNUSED_REGNUM
5094 fprintf_unfiltered (file,
5095 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
5098 fprintf_unfiltered (file,
5099 "mips_dump_tdep: V0_REGNUM = %d\n",
5101 fprintf_unfiltered (file,
5102 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5103 (long) VM_MIN_ADDRESS);
5105 fprintf_unfiltered (file,
5106 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
5109 fprintf_unfiltered (file,
5110 "mips_dump_tdep: ZERO_REGNUM = %d\n",
5112 fprintf_unfiltered (file,
5113 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
5116 fprintf_unfiltered (file,
5117 "mips_dump_tdep: OS ABI = %s\n",
5118 gdbarch_osabi_name (tdep->osabi));
5122 _initialize_mips_tdep (void)
5124 static struct cmd_list_element *mipsfpulist = NULL;
5125 struct cmd_list_element *c;
5127 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
5128 if (MIPS_ABI_LAST + 1
5129 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
5130 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
5132 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
5133 if (!tm_print_insn) /* Someone may have already set it */
5134 tm_print_insn = gdb_print_insn_mips;
5136 /* Add root prefix command for all "set mips"/"show mips" commands */
5137 add_prefix_cmd ("mips", no_class, set_mips_command,
5138 "Various MIPS specific commands.",
5139 &setmipscmdlist, "set mips ", 0, &setlist);
5141 add_prefix_cmd ("mips", no_class, show_mips_command,
5142 "Various MIPS specific commands.",
5143 &showmipscmdlist, "show mips ", 0, &showlist);
5145 /* Allow the user to override the saved register size. */
5146 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5149 &mips_saved_regsize_string, "\
5150 Set size of general purpose registers saved on the stack.\n\
5151 This option can be set to one of:\n\
5152 32 - Force GDB to treat saved GP registers as 32-bit\n\
5153 64 - Force GDB to treat saved GP registers as 64-bit\n\
5154 auto - Allow GDB to use the target's default setting or autodetect the\n\
5155 saved GP register size from information contained in the executable.\n\
5160 /* Allow the user to override the argument stack size. */
5161 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5164 &mips_stack_argsize_string, "\
5165 Set the amount of stack space reserved for each argument.\n\
5166 This option can be set to one of:\n\
5167 32 - Force GDB to allocate 32-bit chunks per argument\n\
5168 64 - Force GDB to allocate 64-bit chunks per argument\n\
5169 auto - Allow GDB to determine the correct setting from the current\n\
5170 target and executable (default)",
5174 /* Allow the user to override the ABI. */
5175 c = add_set_enum_cmd
5176 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
5177 "Set the ABI used by this program.\n"
5178 "This option can be set to one of:\n"
5179 " auto - the default ABI associated with the current binary\n"
5187 add_show_from_set (c, &showmipscmdlist);
5188 set_cmd_sfunc (c, mips_abi_update);
5190 /* Let the user turn off floating point and set the fence post for
5191 heuristic_proc_start. */
5193 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
5194 "Set use of MIPS floating-point coprocessor.",
5195 &mipsfpulist, "set mipsfpu ", 0, &setlist);
5196 add_cmd ("single", class_support, set_mipsfpu_single_command,
5197 "Select single-precision MIPS floating-point coprocessor.",
5199 add_cmd ("double", class_support, set_mipsfpu_double_command,
5200 "Select double-precision MIPS floating-point coprocessor.",
5202 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
5203 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
5204 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
5205 add_cmd ("none", class_support, set_mipsfpu_none_command,
5206 "Select no MIPS floating-point coprocessor.",
5208 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
5209 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
5210 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
5211 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
5212 "Select MIPS floating-point coprocessor automatically.",
5214 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
5215 "Show current use of MIPS floating-point coprocessor target.",
5218 /* We really would like to have both "0" and "unlimited" work, but
5219 command.c doesn't deal with that. So make it a var_zinteger
5220 because the user can always use "999999" or some such for unlimited. */
5221 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
5222 (char *) &heuristic_fence_post,
5224 Set the distance searched for the start of a function.\n\
5225 If you are debugging a stripped executable, GDB needs to search through the\n\
5226 program for the start of a function. This command sets the distance of the\n\
5227 search. The only need to set it is when debugging a stripped executable.",
5229 /* We need to throw away the frame cache when we set this, since it
5230 might change our ability to get backtraces. */
5231 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
5232 add_show_from_set (c, &showlist);
5234 /* Allow the user to control whether the upper bits of 64-bit
5235 addresses should be zeroed. */
5236 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
5237 Set zeroing of upper 32 bits of 64-bit addresses.\n\
5238 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5239 allow GDB to determine the correct value.\n", "\
5240 Show zeroing of upper 32 bits of 64-bit addresses.",
5241 NULL, show_mask_address,
5242 &setmipscmdlist, &showmipscmdlist);
5244 /* Allow the user to control the size of 32 bit registers within the
5245 raw remote packet. */
5246 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5249 (char *)&mips64_transfers_32bit_regs_p, "\
5250 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5251 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5252 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5253 64 bits for others. Use \"off\" to disable compatibility mode",
5257 /* Debug this files internals. */
5258 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
5259 &mips_debug, "Set mips debugging.\n\
5260 When non-zero, mips specific debugging is enabled.", &setdebuglist),