1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data *mips_pdr_data;
63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE = 4,
74 MIPS_FPU_DOUBLE_REGSIZE = 8
83 static const char *mips_abi_string;
85 static const char *mips_abi_strings[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM },
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE /* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto = 1;
159 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
161 static int mips_debug = 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc *mips_tdesc_gp32;
169 struct target_desc *mips_tdesc_gp64;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi;
179 enum mips_abi found_abi;
180 enum mips_fpu_type mips_fpu_type;
181 int mips_last_arg_regnum;
182 int mips_last_fp_arg_regnum;
183 int default_mask_address_p;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum *regnum;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p;
202 const struct mips_regnum *
203 mips_regnum (struct gdbarch *gdbarch)
205 return gdbarch_tdep (gdbarch)->regnum;
209 mips_fpa0_regnum (struct gdbarch *gdbarch)
211 return mips_regnum (gdbarch)->fp0 + 12;
214 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
215 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
217 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
219 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
221 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
223 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
224 functions to test, set, or clear bit 0 of addresses. */
227 is_mips16_addr (CORE_ADDR addr)
233 unmake_mips16_addr (CORE_ADDR addr)
235 return ((addr) & ~(CORE_ADDR) 1);
238 /* Return the MIPS ABI associated with GDBARCH. */
240 mips_abi (struct gdbarch *gdbarch)
242 return gdbarch_tdep (gdbarch)->mips_abi;
246 mips_isa_regsize (struct gdbarch *gdbarch)
248 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
250 /* If we know how big the registers are, use that size. */
251 if (tdep->register_size_valid_p)
252 return tdep->register_size;
254 /* Fall back to the previous behavior. */
255 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
256 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
259 /* Return the currently configured (or set) saved register size. */
262 mips_abi_regsize (struct gdbarch *gdbarch)
264 switch (mips_abi (gdbarch))
266 case MIPS_ABI_EABI32:
272 case MIPS_ABI_EABI64:
274 case MIPS_ABI_UNKNOWN:
277 internal_error (__FILE__, __LINE__, _("bad switch"));
281 /* Functions for setting and testing a bit in a minimal symbol that
282 marks it as 16-bit function. The MSB of the minimal symbol's
283 "info" field is used for this purpose.
285 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
286 i.e. refers to a 16-bit function, and sets a "special" bit in a
287 minimal symbol to mark it as a 16-bit function
289 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
292 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
294 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
296 MSYMBOL_INFO (msym) = (char *)
297 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
298 SYMBOL_VALUE_ADDRESS (msym) |= 1;
303 msymbol_is_special (struct minimal_symbol *msym)
305 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
308 /* XFER a value from the big/little/left end of the register.
309 Depending on the size of the value it might occupy the entire
310 register or just part of it. Make an allowance for this, aligning
311 things accordingly. */
314 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
315 int reg_num, int length,
316 enum bfd_endian endian, gdb_byte *in,
317 const gdb_byte *out, int buf_offset)
321 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
322 /* Need to transfer the left or right part of the register, based on
323 the targets byte order. */
327 reg_offset = register_size (gdbarch, reg_num) - length;
329 case BFD_ENDIAN_LITTLE:
332 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
336 internal_error (__FILE__, __LINE__, _("bad switch"));
339 fprintf_unfiltered (gdb_stderr,
340 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
341 reg_num, reg_offset, buf_offset, length);
342 if (mips_debug && out != NULL)
345 fprintf_unfiltered (gdb_stdlog, "out ");
346 for (i = 0; i < length; i++)
347 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
350 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
353 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
355 if (mips_debug && in != NULL)
358 fprintf_unfiltered (gdb_stdlog, "in ");
359 for (i = 0; i < length; i++)
360 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
363 fprintf_unfiltered (gdb_stdlog, "\n");
366 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
367 compatiblity mode. A return value of 1 means that we have
368 physical 64-bit registers, but should treat them as 32-bit registers. */
371 mips2_fp_compat (struct frame_info *frame)
373 struct gdbarch *gdbarch = get_frame_arch (frame);
374 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
376 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
380 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
381 in all the places we deal with FP registers. PR gdb/413. */
382 /* Otherwise check the FR bit in the status register - it controls
383 the FP compatiblity mode. If it is clear we are in compatibility
385 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
392 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
394 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
396 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
398 static struct type *mips_float_register_type (void);
399 static struct type *mips_double_register_type (void);
401 /* The list of available "set mips " and "show mips " commands */
403 static struct cmd_list_element *setmipscmdlist = NULL;
404 static struct cmd_list_element *showmipscmdlist = NULL;
406 /* Integer registers 0 thru 31 are handled explicitly by
407 mips_register_name(). Processor specific registers 32 and above
408 are listed in the following tables. */
411 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
415 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
418 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
419 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
420 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
421 "fsr", "fir", "" /*"fp" */ , "",
422 "", "", "", "", "", "", "", "",
423 "", "", "", "", "", "", "", "",
426 /* Names of IDT R3041 registers. */
428 static const char *mips_r3041_reg_names[] = {
429 "sr", "lo", "hi", "bad", "cause", "pc",
430 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
431 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
432 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
433 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
434 "fsr", "fir", "", /*"fp" */ "",
435 "", "", "bus", "ccfg", "", "", "", "",
436 "", "", "port", "cmp", "", "", "epc", "prid",
439 /* Names of tx39 registers. */
441 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
442 "sr", "lo", "hi", "bad", "cause", "pc",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
448 "", "", "", "", "", "", "", "",
449 "", "", "config", "cache", "debug", "depc", "epc", ""
452 /* Names of IRIX registers. */
453 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
454 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
455 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
456 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
457 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
458 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
462 /* Return the name of the register corresponding to REGNO. */
464 mips_register_name (struct gdbarch *gdbarch, int regno)
466 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
467 /* GPR names for all ABIs other than n32/n64. */
468 static char *mips_gpr_names[] = {
469 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
470 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
472 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
475 /* GPR names for n32 and n64 ABIs. */
476 static char *mips_n32_n64_gpr_names[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
483 enum mips_abi abi = mips_abi (gdbarch);
485 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
486 but then don't make the raw register names visible. */
487 int rawnum = regno % gdbarch_num_regs (gdbarch);
488 if (regno < gdbarch_num_regs (gdbarch))
491 /* The MIPS integer registers are always mapped from 0 to 31. The
492 names of the registers (which reflects the conventions regarding
493 register use) vary depending on the ABI. */
494 if (0 <= rawnum && rawnum < 32)
496 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
497 return mips_n32_n64_gpr_names[rawnum];
499 return mips_gpr_names[rawnum];
501 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
502 return tdesc_register_name (gdbarch, rawnum);
503 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
505 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
506 return tdep->mips_processor_reg_names[rawnum - 32];
509 internal_error (__FILE__, __LINE__,
510 _("mips_register_name: bad register number %d"), rawnum);
513 /* Return the groups that a MIPS register can be categorised into. */
516 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
517 struct reggroup *reggroup)
522 int rawnum = regnum % gdbarch_num_regs (gdbarch);
523 int pseudo = regnum / gdbarch_num_regs (gdbarch);
524 if (reggroup == all_reggroup)
526 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
527 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
528 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
529 (gdbarch), as not all architectures are multi-arch. */
530 raw_p = rawnum < gdbarch_num_regs (gdbarch);
531 if (gdbarch_register_name (gdbarch, regnum) == NULL
532 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
534 if (reggroup == float_reggroup)
535 return float_p && pseudo;
536 if (reggroup == vector_reggroup)
537 return vector_p && pseudo;
538 if (reggroup == general_reggroup)
539 return (!vector_p && !float_p) && pseudo;
540 /* Save the pseudo registers. Need to make certain that any code
541 extracting register values from a saved register cache also uses
543 if (reggroup == save_reggroup)
544 return raw_p && pseudo;
545 /* Restore the same pseudo register. */
546 if (reggroup == restore_reggroup)
547 return raw_p && pseudo;
551 /* Return the groups that a MIPS register can be categorised into.
552 This version is only used if we have a target description which
553 describes real registers (and their groups). */
556 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
557 struct reggroup *reggroup)
559 int rawnum = regnum % gdbarch_num_regs (gdbarch);
560 int pseudo = regnum / gdbarch_num_regs (gdbarch);
563 /* Only save, restore, and display the pseudo registers. Need to
564 make certain that any code extracting register values from a
565 saved register cache also uses pseudo registers.
567 Note: saving and restoring the pseudo registers is slightly
568 strange; if we have 64 bits, we should save and restore all
569 64 bits. But this is hard and has little benefit. */
573 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
577 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
580 /* Map the symbol table registers which live in the range [1 *
581 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
582 registers. Take care of alignment and size problems. */
585 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
586 int cookednum, gdb_byte *buf)
588 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
589 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
590 && cookednum < 2 * gdbarch_num_regs (gdbarch));
591 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
592 regcache_raw_read (regcache, rawnum, buf);
593 else if (register_size (gdbarch, rawnum) >
594 register_size (gdbarch, cookednum))
596 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
597 || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
598 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
600 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
603 internal_error (__FILE__, __LINE__, _("bad register size"));
607 mips_pseudo_register_write (struct gdbarch *gdbarch,
608 struct regcache *regcache, int cookednum,
611 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
612 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
613 && cookednum < 2 * gdbarch_num_regs (gdbarch));
614 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
615 regcache_raw_write (regcache, rawnum, buf);
616 else if (register_size (gdbarch, rawnum) >
617 register_size (gdbarch, cookednum))
619 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
620 || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
621 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
623 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
626 internal_error (__FILE__, __LINE__, _("bad register size"));
629 /* Table to translate MIPS16 register field to actual register number. */
630 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
632 /* Heuristic_proc_start may hunt through the text section for a long
633 time across a 2400 baud serial line. Allows the user to limit this
636 static unsigned int heuristic_fence_post = 0;
638 /* Number of bytes of storage in the actual machine representation for
639 register N. NOTE: This defines the pseudo register type so need to
640 rebuild the architecture vector. */
642 static int mips64_transfers_32bit_regs_p = 0;
645 set_mips64_transfers_32bit_regs (char *args, int from_tty,
646 struct cmd_list_element *c)
648 struct gdbarch_info info;
649 gdbarch_info_init (&info);
650 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
651 instead of relying on globals. Doing that would let generic code
652 handle the search for this specific architecture. */
653 if (!gdbarch_update_p (info))
655 mips64_transfers_32bit_regs_p = 0;
656 error (_("32-bit compatibility mode not supported"));
660 /* Convert to/from a register and the corresponding memory value. */
663 mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
665 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
666 && register_size (gdbarch, regnum) == 4
667 && (regnum % gdbarch_num_regs (gdbarch))
668 >= mips_regnum (gdbarch)->fp0
669 && (regnum % gdbarch_num_regs (gdbarch))
670 < mips_regnum (gdbarch)->fp0 + 32
671 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
675 mips_register_to_value (struct frame_info *frame, int regnum,
676 struct type *type, gdb_byte *to)
678 get_frame_register (frame, regnum + 0, to + 4);
679 get_frame_register (frame, regnum + 1, to + 0);
683 mips_value_to_register (struct frame_info *frame, int regnum,
684 struct type *type, const gdb_byte *from)
686 put_frame_register (frame, regnum + 0, from + 4);
687 put_frame_register (frame, regnum + 1, from + 0);
690 /* Return the GDB type object for the "standard" data type of data in
694 mips_register_type (struct gdbarch *gdbarch, int regnum)
696 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
697 if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0
698 && (regnum % gdbarch_num_regs (gdbarch))
699 < mips_regnum (gdbarch)->fp0 + 32)
701 /* The floating-point registers raw, or cooked, always match
702 mips_isa_regsize(), and also map 1:1, byte for byte. */
703 if (mips_isa_regsize (gdbarch) == 4)
704 return builtin_type_ieee_single;
706 return builtin_type_ieee_double;
708 else if (regnum < gdbarch_num_regs (gdbarch))
710 /* The raw or ISA registers. These are all sized according to
712 if (mips_isa_regsize (gdbarch) == 4)
713 return builtin_type_int32;
715 return builtin_type_int64;
719 /* The cooked or ABI registers. These are sized according to
720 the ABI (with a few complications). */
721 if (regnum >= (gdbarch_num_regs (gdbarch)
722 + mips_regnum (gdbarch)->fp_control_status)
723 && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM)
724 /* The pseudo/cooked view of the embedded registers is always
725 32-bit. The raw view is handled below. */
726 return builtin_type_int32;
727 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
728 /* The target, while possibly using a 64-bit register buffer,
729 is only transfering 32-bits of each integer register.
730 Reflect this in the cooked/pseudo (ABI) register value. */
731 return builtin_type_int32;
732 else if (mips_abi_regsize (gdbarch) == 4)
733 /* The ABI is restricted to 32-bit registers (the ISA could be
735 return builtin_type_int32;
738 return builtin_type_int64;
742 /* Return the GDB type for the pseudo register REGNUM, which is the
743 ABI-level view. This function is only called if there is a target
744 description which includes registers, so we know precisely the
745 types of hardware registers. */
748 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
750 const int num_regs = gdbarch_num_regs (gdbarch);
751 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
752 int rawnum = regnum % num_regs;
753 struct type *rawtype;
755 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
757 /* Absent registers are still absent. */
758 rawtype = gdbarch_register_type (gdbarch, rawnum);
759 if (TYPE_LENGTH (rawtype) == 0)
762 if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32)
763 /* Present the floating point registers however the hardware did;
764 do not try to convert between FPU layouts. */
767 if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM)
769 /* The pseudo/cooked view of embedded registers is always
770 32-bit, even if the target transfers 64-bit values for them.
771 New targets relying on XML descriptions should only transfer
772 the necessary 32 bits, but older versions of GDB expected 64,
773 so allow the target to provide 64 bits without interfering
774 with the displayed type. */
775 return builtin_type_int32;
778 /* Use pointer types for registers if we can. For n32 we can not,
779 since we do not have a 64-bit pointer type. */
780 if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr))
782 if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM)
783 return builtin_type_void_data_ptr;
784 else if (rawnum == MIPS_EMBED_PC_REGNUM)
785 return builtin_type_void_func_ptr;
788 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
789 && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM)
790 return builtin_type_int32;
792 /* For all other registers, pass through the hardware type. */
796 /* Should the upper word of 64-bit addresses be zeroed? */
797 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
800 mips_mask_address_p (struct gdbarch_tdep *tdep)
802 switch (mask_address_var)
804 case AUTO_BOOLEAN_TRUE:
806 case AUTO_BOOLEAN_FALSE:
809 case AUTO_BOOLEAN_AUTO:
810 return tdep->default_mask_address_p;
812 internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch"));
818 show_mask_address (struct ui_file *file, int from_tty,
819 struct cmd_list_element *c, const char *value)
821 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
823 deprecated_show_value_hack (file, from_tty, c, value);
824 switch (mask_address_var)
826 case AUTO_BOOLEAN_TRUE:
827 printf_filtered ("The 32 bit mips address mask is enabled\n");
829 case AUTO_BOOLEAN_FALSE:
830 printf_filtered ("The 32 bit mips address mask is disabled\n");
832 case AUTO_BOOLEAN_AUTO:
834 ("The 32 bit address mask is set automatically. Currently %s\n",
835 mips_mask_address_p (tdep) ? "enabled" : "disabled");
838 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
843 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
846 mips_pc_is_mips16 (CORE_ADDR memaddr)
848 struct minimal_symbol *sym;
850 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
851 if (is_mips16_addr (memaddr))
854 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
855 the high bit of the info field. Use this to decide if the function is
856 MIPS16 or normal MIPS. */
857 sym = lookup_minimal_symbol_by_pc (memaddr);
859 return msymbol_is_special (sym);
864 /* MIPS believes that the PC has a sign extended value. Perhaps the
865 all registers should be sign extended for simplicity? */
868 mips_read_pc (struct regcache *regcache)
871 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
872 regcache_cooked_read_signed (regcache, regnum, &pc);
877 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
879 return frame_unwind_register_signed
880 (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc);
884 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
886 return frame_unwind_register_signed
887 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
890 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
891 dummy frame. The frame ID's base needs to match the TOS value
892 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
895 static struct frame_id
896 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
898 return frame_id_build
899 (get_frame_register_signed (this_frame,
900 gdbarch_num_regs (gdbarch)
902 get_frame_pc (this_frame));
906 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
908 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
909 regcache_cooked_write_unsigned (regcache, regnum, pc);
912 /* Fetch and return instruction from the specified location. If the PC
913 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
916 mips_fetch_instruction (CORE_ADDR addr)
918 gdb_byte buf[MIPS_INSN32_SIZE];
922 if (mips_pc_is_mips16 (addr))
924 instlen = MIPS_INSN16_SIZE;
925 addr = unmake_mips16_addr (addr);
928 instlen = MIPS_INSN32_SIZE;
929 status = target_read_memory (addr, buf, instlen);
931 memory_error (status, addr);
932 return extract_unsigned_integer (buf, instlen);
935 /* These the fields of 32 bit mips instructions */
936 #define mips32_op(x) (x >> 26)
937 #define itype_op(x) (x >> 26)
938 #define itype_rs(x) ((x >> 21) & 0x1f)
939 #define itype_rt(x) ((x >> 16) & 0x1f)
940 #define itype_immediate(x) (x & 0xffff)
942 #define jtype_op(x) (x >> 26)
943 #define jtype_target(x) (x & 0x03ffffff)
945 #define rtype_op(x) (x >> 26)
946 #define rtype_rs(x) ((x >> 21) & 0x1f)
947 #define rtype_rt(x) ((x >> 16) & 0x1f)
948 #define rtype_rd(x) ((x >> 11) & 0x1f)
949 #define rtype_shamt(x) ((x >> 6) & 0x1f)
950 #define rtype_funct(x) (x & 0x3f)
953 mips32_relative_offset (ULONGEST inst)
955 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
958 /* Determine where to set a single step breakpoint while considering
959 branch prediction. */
961 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
965 inst = mips_fetch_instruction (pc);
966 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
968 if (itype_op (inst) >> 2 == 5)
969 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
971 op = (itype_op (inst) & 0x03);
986 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
987 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
989 int tf = itype_rt (inst) & 0x01;
990 int cnum = itype_rt (inst) >> 2;
992 get_frame_register_signed (frame,
993 mips_regnum (get_frame_arch (frame))->
995 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
997 if (((cond >> cnum) & 0x01) == tf)
998 pc += mips32_relative_offset (inst) + 4;
1003 pc += 4; /* Not a branch, next instruction is easy */
1006 { /* This gets way messy */
1008 /* Further subdivide into SPECIAL, REGIMM and other */
1009 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
1011 case 0: /* SPECIAL */
1012 op = rtype_funct (inst);
1017 /* Set PC to that address */
1018 pc = get_frame_register_signed (frame, rtype_rs (inst));
1024 break; /* end SPECIAL */
1025 case 1: /* REGIMM */
1027 op = itype_rt (inst); /* branch condition */
1032 case 16: /* BLTZAL */
1033 case 18: /* BLTZALL */
1035 if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1036 pc += mips32_relative_offset (inst) + 4;
1038 pc += 8; /* after the delay slot */
1042 case 17: /* BGEZAL */
1043 case 19: /* BGEZALL */
1044 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1045 pc += mips32_relative_offset (inst) + 4;
1047 pc += 8; /* after the delay slot */
1049 /* All of the other instructions in the REGIMM category */
1054 break; /* end REGIMM */
1059 reg = jtype_target (inst) << 2;
1060 /* Upper four bits get never changed... */
1061 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1064 /* FIXME case JALX : */
1067 reg = jtype_target (inst) << 2;
1068 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */
1069 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1071 break; /* The new PC will be alternate mode */
1072 case 4: /* BEQ, BEQL */
1074 if (get_frame_register_signed (frame, itype_rs (inst)) ==
1075 get_frame_register_signed (frame, itype_rt (inst)))
1076 pc += mips32_relative_offset (inst) + 4;
1080 case 5: /* BNE, BNEL */
1082 if (get_frame_register_signed (frame, itype_rs (inst)) !=
1083 get_frame_register_signed (frame, itype_rt (inst)))
1084 pc += mips32_relative_offset (inst) + 4;
1088 case 6: /* BLEZ, BLEZL */
1089 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1090 pc += mips32_relative_offset (inst) + 4;
1096 greater_branch: /* BGTZ, BGTZL */
1097 if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1098 pc += mips32_relative_offset (inst) + 4;
1105 } /* mips32_next_pc */
1107 /* Decoding the next place to set a breakpoint is irregular for the
1108 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1109 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1110 We dont want to set a single step instruction on the extend instruction
1114 /* Lots of mips16 instruction formats */
1115 /* Predicting jumps requires itype,ritype,i8type
1116 and their extensions extItype,extritype,extI8type
1118 enum mips16_inst_fmts
1120 itype, /* 0 immediate 5,10 */
1121 ritype, /* 1 5,3,8 */
1122 rrtype, /* 2 5,3,3,5 */
1123 rritype, /* 3 5,3,3,5 */
1124 rrrtype, /* 4 5,3,3,3,2 */
1125 rriatype, /* 5 5,3,3,1,4 */
1126 shifttype, /* 6 5,3,3,3,2 */
1127 i8type, /* 7 5,3,8 */
1128 i8movtype, /* 8 5,3,3,5 */
1129 i8mov32rtype, /* 9 5,3,5,3 */
1130 i64type, /* 10 5,3,8 */
1131 ri64type, /* 11 5,3,3,5 */
1132 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1133 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1134 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1135 extRRItype, /* 15 5,5,5,5,3,3,5 */
1136 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1137 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1138 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1139 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1140 extRi64type, /* 20 5,6,5,5,3,3,5 */
1141 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1143 /* I am heaping all the fields of the formats into one structure and
1144 then, only the fields which are involved in instruction extension */
1148 unsigned int regx; /* Function in i8 type */
1153 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1154 for the bits which make up the immediate extension. */
1157 extended_offset (unsigned int extension)
1160 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1162 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1164 value |= extension & 0x01f; /* extract 4:0 */
1168 /* Only call this function if you know that this is an extendable
1169 instruction. It won't malfunction, but why make excess remote memory
1170 references? If the immediate operands get sign extended or something,
1171 do it after the extension is performed. */
1172 /* FIXME: Every one of these cases needs to worry about sign extension
1173 when the offset is to be used in relative addressing. */
1176 fetch_mips_16 (CORE_ADDR pc)
1179 pc &= 0xfffffffe; /* clear the low order bit */
1180 target_read_memory (pc, buf, 2);
1181 return extract_unsigned_integer (buf, 2);
1185 unpack_mips16 (CORE_ADDR pc,
1186 unsigned int extension,
1188 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1193 switch (insn_format)
1200 value = extended_offset (extension);
1201 value = value << 11; /* rom for the original value */
1202 value |= inst & 0x7ff; /* eleven bits from instruction */
1206 value = inst & 0x7ff;
1207 /* FIXME : Consider sign extension */
1216 { /* A register identifier and an offset */
1217 /* Most of the fields are the same as I type but the
1218 immediate value is of a different length */
1222 value = extended_offset (extension);
1223 value = value << 8; /* from the original instruction */
1224 value |= inst & 0xff; /* eleven bits from instruction */
1225 regx = (extension >> 8) & 0x07; /* or i8 funct */
1226 if (value & 0x4000) /* test the sign bit , bit 26 */
1228 value &= ~0x3fff; /* remove the sign bit */
1234 value = inst & 0xff; /* 8 bits */
1235 regx = (inst >> 8) & 0x07; /* or i8 funct */
1236 /* FIXME: Do sign extension , this format needs it */
1237 if (value & 0x80) /* THIS CONFUSES ME */
1239 value &= 0xef; /* remove the sign bit */
1249 unsigned long value;
1250 unsigned int nexthalf;
1251 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1252 value = value << 16;
1253 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1261 internal_error (__FILE__, __LINE__, _("bad switch"));
1263 upk->offset = offset;
1270 add_offset_16 (CORE_ADDR pc, int offset)
1272 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
1276 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
1277 unsigned int extension, unsigned int insn)
1279 int op = (insn >> 11);
1282 case 2: /* Branch */
1285 struct upk_mips16 upk;
1286 unpack_mips16 (pc, extension, insn, itype, &upk);
1287 offset = upk.offset;
1293 pc += (offset << 1) + 2;
1296 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1298 struct upk_mips16 upk;
1299 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1300 pc = add_offset_16 (pc, upk.offset);
1301 if ((insn >> 10) & 0x01) /* Exchange mode */
1302 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1309 struct upk_mips16 upk;
1311 unpack_mips16 (pc, extension, insn, ritype, &upk);
1312 reg = get_frame_register_signed (frame, upk.regx);
1314 pc += (upk.offset << 1) + 2;
1321 struct upk_mips16 upk;
1323 unpack_mips16 (pc, extension, insn, ritype, &upk);
1324 reg = get_frame_register_signed (frame, upk.regx);
1326 pc += (upk.offset << 1) + 2;
1331 case 12: /* I8 Formats btez btnez */
1333 struct upk_mips16 upk;
1335 unpack_mips16 (pc, extension, insn, i8type, &upk);
1336 /* upk.regx contains the opcode */
1337 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
1338 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1339 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1340 /* pc = add_offset_16(pc,upk.offset) ; */
1341 pc += (upk.offset << 1) + 2;
1346 case 29: /* RR Formats JR, JALR, JALR-RA */
1348 struct upk_mips16 upk;
1349 /* upk.fmt = rrtype; */
1354 upk.regx = (insn >> 8) & 0x07;
1355 upk.regy = (insn >> 5) & 0x07;
1363 break; /* Function return instruction */
1369 break; /* BOGUS Guess */
1371 pc = get_frame_register_signed (frame, reg);
1378 /* This is an instruction extension. Fetch the real instruction
1379 (which follows the extension) and decode things based on
1383 pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc));
1396 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
1398 unsigned int insn = fetch_mips_16 (pc);
1399 return extended_mips16_next_pc (frame, pc, 0, insn);
1402 /* The mips_next_pc function supports single_step when the remote
1403 target monitor or stub is not developed enough to do a single_step.
1404 It works by decoding the current instruction and predicting where a
1405 branch will go. This isnt hard because all the data is available.
1406 The MIPS32 and MIPS16 variants are quite different. */
1408 mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1410 if (is_mips16_addr (pc))
1411 return mips16_next_pc (frame, pc);
1413 return mips32_next_pc (frame, pc);
1416 struct mips_frame_cache
1419 struct trad_frame_saved_reg *saved_regs;
1422 /* Set a register's saved stack address in temp_saved_regs. If an
1423 address has already been set for this register, do nothing; this
1424 way we will only recognize the first save of a given register in a
1427 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1428 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1429 Strictly speaking, only the second range is used as it is only second
1430 range (the ABI instead of ISA registers) that comes into play when finding
1431 saved registers in a frame. */
1434 set_reg_offset (struct mips_frame_cache *this_cache, int regnum,
1437 if (this_cache != NULL
1438 && this_cache->saved_regs[regnum].addr == -1)
1440 this_cache->saved_regs[regnum
1441 + 0 * gdbarch_num_regs (current_gdbarch)].addr
1443 this_cache->saved_regs[regnum
1444 + 1 * gdbarch_num_regs (current_gdbarch)].addr
1450 /* Fetch the immediate value from a MIPS16 instruction.
1451 If the previous instruction was an EXTEND, use it to extend
1452 the upper bits of the immediate value. This is a helper function
1453 for mips16_scan_prologue. */
1456 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1457 unsigned short inst, /* current instruction */
1458 int nbits, /* number of bits in imm field */
1459 int scale, /* scale factor to be applied to imm */
1460 int is_signed) /* is the imm field signed? */
1464 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1466 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1467 if (offset & 0x8000) /* check for negative extend */
1468 offset = 0 - (0x10000 - (offset & 0xffff));
1469 return offset | (inst & 0x1f);
1473 int max_imm = 1 << nbits;
1474 int mask = max_imm - 1;
1475 int sign_bit = max_imm >> 1;
1477 offset = inst & mask;
1478 if (is_signed && (offset & sign_bit))
1479 offset = 0 - (max_imm - offset);
1480 return offset * scale;
1485 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1486 the associated FRAME_CACHE if not null.
1487 Return the address of the first instruction past the prologue. */
1490 mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1491 struct frame_info *this_frame,
1492 struct mips_frame_cache *this_cache)
1495 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1497 long frame_offset = 0; /* Size of stack frame. */
1498 long frame_adjust = 0; /* Offset of FP from SP. */
1499 int frame_reg = MIPS_SP_REGNUM;
1500 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1501 unsigned inst = 0; /* current instruction */
1502 unsigned entry_inst = 0; /* the entry instruction */
1503 unsigned save_inst = 0; /* the save instruction */
1506 int extend_bytes = 0;
1507 int prev_extend_bytes;
1508 CORE_ADDR end_prologue_addr = 0;
1509 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1511 /* Can be called when there's no process, and hence when there's no
1513 if (this_frame != NULL)
1514 sp = get_frame_register_signed (this_frame,
1515 gdbarch_num_regs (gdbarch)
1520 if (limit_pc > start_pc + 200)
1521 limit_pc = start_pc + 200;
1523 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
1525 /* Save the previous instruction. If it's an EXTEND, we'll extract
1526 the immediate offset extension from it in mips16_get_imm. */
1529 /* Fetch and decode the instruction. */
1530 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1532 /* Normally we ignore extend instructions. However, if it is
1533 not followed by a valid prologue instruction, then this
1534 instruction is not part of the prologue either. We must
1535 remember in this case to adjust the end_prologue_addr back
1537 if ((inst & 0xf800) == 0xf000) /* extend */
1539 extend_bytes = MIPS_INSN16_SIZE;
1543 prev_extend_bytes = extend_bytes;
1546 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1547 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1549 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1550 if (offset < 0) /* negative stack adjustment? */
1551 frame_offset -= offset;
1553 /* Exit loop if a positive stack adjustment is found, which
1554 usually means that the stack cleanup code in the function
1555 epilogue is reached. */
1558 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1560 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1561 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1562 set_reg_offset (this_cache, reg, sp + offset);
1564 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1566 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1567 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1568 set_reg_offset (this_cache, reg, sp + offset);
1570 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1572 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1573 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1575 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1577 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1578 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1580 else if (inst == 0x673d) /* move $s1, $sp */
1585 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1587 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1588 frame_addr = sp + offset;
1590 frame_adjust = offset;
1592 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1594 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1595 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1596 set_reg_offset (this_cache, reg, frame_addr + offset);
1598 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1600 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1601 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1602 set_reg_offset (this_cache, reg, frame_addr + offset);
1604 else if ((inst & 0xf81f) == 0xe809
1605 && (inst & 0x700) != 0x700) /* entry */
1606 entry_inst = inst; /* save for later processing */
1607 else if ((inst & 0xff80) == 0x6480) /* save */
1609 save_inst = inst; /* save for later processing */
1610 if (prev_extend_bytes) /* extend */
1611 save_inst |= prev_inst << 16;
1613 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1614 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
1615 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1617 /* This instruction is part of the prologue, but we don't
1618 need to do anything special to handle it. */
1622 /* This instruction is not an instruction typically found
1623 in a prologue, so we must have reached the end of the
1625 if (end_prologue_addr == 0)
1626 end_prologue_addr = cur_pc - prev_extend_bytes;
1630 /* The entry instruction is typically the first instruction in a function,
1631 and it stores registers at offsets relative to the value of the old SP
1632 (before the prologue). But the value of the sp parameter to this
1633 function is the new SP (after the prologue has been executed). So we
1634 can't calculate those offsets until we've seen the entire prologue,
1635 and can calculate what the old SP must have been. */
1636 if (entry_inst != 0)
1638 int areg_count = (entry_inst >> 8) & 7;
1639 int sreg_count = (entry_inst >> 6) & 3;
1641 /* The entry instruction always subtracts 32 from the SP. */
1644 /* Now we can calculate what the SP must have been at the
1645 start of the function prologue. */
1648 /* Check if a0-a3 were saved in the caller's argument save area. */
1649 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1651 set_reg_offset (this_cache, reg, sp + offset);
1652 offset += mips_abi_regsize (gdbarch);
1655 /* Check if the ra register was pushed on the stack. */
1657 if (entry_inst & 0x20)
1659 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1660 offset -= mips_abi_regsize (gdbarch);
1663 /* Check if the s0 and s1 registers were pushed on the stack. */
1664 for (reg = 16; reg < sreg_count + 16; reg++)
1666 set_reg_offset (this_cache, reg, sp + offset);
1667 offset -= mips_abi_regsize (gdbarch);
1671 /* The SAVE instruction is similar to ENTRY, except that defined by the
1672 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1673 size of the frame is specified as an immediate field of instruction
1674 and an extended variation exists which lets additional registers and
1675 frame space to be specified. The instruction always treats registers
1676 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1677 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
1679 static int args_table[16] = {
1680 0, 0, 0, 0, 1, 1, 1, 1,
1681 2, 2, 2, 0, 3, 3, 4, -1,
1683 static int astatic_table[16] = {
1684 0, 1, 2, 3, 0, 1, 2, 3,
1685 0, 1, 2, 4, 0, 1, 0, -1,
1687 int aregs = (save_inst >> 16) & 0xf;
1688 int xsregs = (save_inst >> 24) & 0x7;
1689 int args = args_table[aregs];
1690 int astatic = astatic_table[aregs];
1695 warning (_("Invalid number of argument registers encoded in SAVE."));
1700 warning (_("Invalid number of static registers encoded in SAVE."));
1704 /* For standard SAVE the frame size of 0 means 128. */
1705 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
1706 if (frame_size == 0 && (save_inst >> 16) == 0)
1709 frame_offset += frame_size;
1711 /* Now we can calculate what the SP must have been at the
1712 start of the function prologue. */
1715 /* Check if A0-A3 were saved in the caller's argument save area. */
1716 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
1718 set_reg_offset (this_cache, reg, sp + offset);
1719 offset += mips_abi_regsize (gdbarch);
1724 /* Check if the RA register was pushed on the stack. */
1725 if (save_inst & 0x40)
1727 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1728 offset -= mips_abi_regsize (gdbarch);
1731 /* Check if the S8 register was pushed on the stack. */
1734 set_reg_offset (this_cache, 30, sp + offset);
1735 offset -= mips_abi_regsize (gdbarch);
1738 /* Check if S2-S7 were pushed on the stack. */
1739 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
1741 set_reg_offset (this_cache, reg, sp + offset);
1742 offset -= mips_abi_regsize (gdbarch);
1745 /* Check if the S1 register was pushed on the stack. */
1746 if (save_inst & 0x10)
1748 set_reg_offset (this_cache, 17, sp + offset);
1749 offset -= mips_abi_regsize (gdbarch);
1751 /* Check if the S0 register was pushed on the stack. */
1752 if (save_inst & 0x20)
1754 set_reg_offset (this_cache, 16, sp + offset);
1755 offset -= mips_abi_regsize (gdbarch);
1758 /* Check if A0-A3 were pushed on the stack. */
1759 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
1761 set_reg_offset (this_cache, reg, sp + offset);
1762 offset -= mips_abi_regsize (gdbarch);
1766 if (this_cache != NULL)
1769 (get_frame_register_signed (this_frame,
1770 gdbarch_num_regs (gdbarch) + frame_reg)
1771 + frame_offset - frame_adjust);
1772 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1773 be able to get rid of the assignment below, evetually. But it's
1774 still needed for now. */
1775 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
1776 + mips_regnum (gdbarch)->pc]
1777 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
1780 /* If we didn't reach the end of the prologue when scanning the function
1781 instructions, then set end_prologue_addr to the address of the
1782 instruction immediately after the last one we scanned. */
1783 if (end_prologue_addr == 0)
1784 end_prologue_addr = cur_pc;
1786 return end_prologue_addr;
1789 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1790 Procedures that use the 32-bit instruction set are handled by the
1791 mips_insn32 unwinder. */
1793 static struct mips_frame_cache *
1794 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
1796 struct mips_frame_cache *cache;
1798 if ((*this_cache) != NULL)
1799 return (*this_cache);
1800 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1801 (*this_cache) = cache;
1802 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1804 /* Analyze the function prologue. */
1806 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
1807 CORE_ADDR start_addr;
1809 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1810 if (start_addr == 0)
1811 start_addr = heuristic_proc_start (pc);
1812 /* We can't analyze the prologue if we couldn't find the begining
1814 if (start_addr == 0)
1817 mips16_scan_prologue (start_addr, pc, this_frame, *this_cache);
1820 /* gdbarch_sp_regnum contains the value and not the address. */
1821 trad_frame_set_value (cache->saved_regs,
1822 gdbarch_num_regs (get_frame_arch (this_frame))
1826 return (*this_cache);
1830 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
1831 struct frame_id *this_id)
1833 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1835 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
1838 static struct value *
1839 mips_insn16_frame_prev_register (struct frame_info *this_frame,
1840 void **this_cache, int regnum)
1842 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1844 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1848 mips_insn16_frame_sniffer (const struct frame_unwind *self,
1849 struct frame_info *this_frame, void **this_cache)
1851 CORE_ADDR pc = get_frame_pc (this_frame);
1852 if (mips_pc_is_mips16 (pc))
1857 static const struct frame_unwind mips_insn16_frame_unwind =
1860 mips_insn16_frame_this_id,
1861 mips_insn16_frame_prev_register,
1863 mips_insn16_frame_sniffer
1867 mips_insn16_frame_base_address (struct frame_info *this_frame,
1870 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1875 static const struct frame_base mips_insn16_frame_base =
1877 &mips_insn16_frame_unwind,
1878 mips_insn16_frame_base_address,
1879 mips_insn16_frame_base_address,
1880 mips_insn16_frame_base_address
1883 static const struct frame_base *
1884 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
1886 CORE_ADDR pc = get_frame_pc (this_frame);
1887 if (mips_pc_is_mips16 (pc))
1888 return &mips_insn16_frame_base;
1893 /* Mark all the registers as unset in the saved_regs array
1894 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1897 reset_saved_regs (struct mips_frame_cache *this_cache)
1899 if (this_cache == NULL || this_cache->saved_regs == NULL)
1903 const int num_regs = gdbarch_num_regs (current_gdbarch);
1906 for (i = 0; i < num_regs; i++)
1908 this_cache->saved_regs[i].addr = -1;
1913 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1914 the associated FRAME_CACHE if not null.
1915 Return the address of the first instruction past the prologue. */
1918 mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1919 struct frame_info *this_frame,
1920 struct mips_frame_cache *this_cache)
1923 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1926 int frame_reg = MIPS_SP_REGNUM;
1928 CORE_ADDR end_prologue_addr = 0;
1929 int seen_sp_adjust = 0;
1930 int load_immediate_bytes = 0;
1931 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1932 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
1934 /* Can be called when there's no process, and hence when there's no
1936 if (this_frame != NULL)
1937 sp = get_frame_register_signed (this_frame,
1938 gdbarch_num_regs (gdbarch)
1943 if (limit_pc > start_pc + 200)
1944 limit_pc = start_pc + 200;
1949 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
1951 unsigned long inst, high_word, low_word;
1954 /* Fetch the instruction. */
1955 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1957 /* Save some code by pre-extracting some useful fields. */
1958 high_word = (inst >> 16) & 0xffff;
1959 low_word = inst & 0xffff;
1960 reg = high_word & 0x1f;
1962 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1963 || high_word == 0x23bd /* addi $sp,$sp,-i */
1964 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1966 if (low_word & 0x8000) /* negative stack adjustment? */
1967 frame_offset += 0x10000 - low_word;
1969 /* Exit loop if a positive stack adjustment is found, which
1970 usually means that the stack cleanup code in the function
1971 epilogue is reached. */
1975 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1976 && !regsize_is_64_bits)
1978 set_reg_offset (this_cache, reg, sp + low_word);
1980 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1981 && regsize_is_64_bits)
1983 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1984 set_reg_offset (this_cache, reg, sp + low_word);
1986 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1988 /* Old gcc frame, r30 is virtual frame pointer. */
1989 if ((long) low_word != frame_offset)
1990 frame_addr = sp + low_word;
1991 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
1993 unsigned alloca_adjust;
1996 frame_addr = get_frame_register_signed
1997 (this_frame, gdbarch_num_regs (gdbarch) + 30);
1999 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2000 if (alloca_adjust > 0)
2002 /* FP > SP + frame_size. This may be because of
2003 an alloca or somethings similar. Fix sp to
2004 "pre-alloca" value, and try again. */
2005 sp += alloca_adjust;
2006 /* Need to reset the status of all registers. Otherwise,
2007 we will hit a guard that prevents the new address
2008 for each register to be recomputed during the second
2010 reset_saved_regs (this_cache);
2015 /* move $30,$sp. With different versions of gas this will be either
2016 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2017 Accept any one of these. */
2018 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2020 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2021 if (this_frame && frame_reg == MIPS_SP_REGNUM)
2023 unsigned alloca_adjust;
2026 frame_addr = get_frame_register_signed
2027 (this_frame, gdbarch_num_regs (gdbarch) + 30);
2029 alloca_adjust = (unsigned) (frame_addr - sp);
2030 if (alloca_adjust > 0)
2032 /* FP > SP + frame_size. This may be because of
2033 an alloca or somethings similar. Fix sp to
2034 "pre-alloca" value, and try again. */
2036 /* Need to reset the status of all registers. Otherwise,
2037 we will hit a guard that prevents the new address
2038 for each register to be recomputed during the second
2040 reset_saved_regs (this_cache);
2045 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2046 && !regsize_is_64_bits)
2048 set_reg_offset (this_cache, reg, frame_addr + low_word);
2050 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2051 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2052 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2053 || high_word == 0x3c1c /* lui $gp,n */
2054 || high_word == 0x279c /* addiu $gp,$gp,n */
2055 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
2056 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
2059 /* These instructions are part of the prologue, but we don't
2060 need to do anything special to handle them. */
2062 /* The instructions below load $at or $t0 with an immediate
2063 value in preparation for a stack adjustment via
2064 subu $sp,$sp,[$at,$t0]. These instructions could also
2065 initialize a local variable, so we accept them only before
2066 a stack adjustment instruction was seen. */
2067 else if (!seen_sp_adjust
2068 && (high_word == 0x3c01 /* lui $at,n */
2069 || high_word == 0x3c08 /* lui $t0,n */
2070 || high_word == 0x3421 /* ori $at,$at,n */
2071 || high_word == 0x3508 /* ori $t0,$t0,n */
2072 || high_word == 0x3401 /* ori $at,$zero,n */
2073 || high_word == 0x3408 /* ori $t0,$zero,n */
2076 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
2080 /* This instruction is not an instruction typically found
2081 in a prologue, so we must have reached the end of the
2083 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2084 loop now? Why would we need to continue scanning the function
2086 if (end_prologue_addr == 0)
2087 end_prologue_addr = cur_pc;
2091 if (this_cache != NULL)
2094 (get_frame_register_signed (this_frame,
2095 gdbarch_num_regs (gdbarch) + frame_reg)
2097 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2098 this assignment below, eventually. But it's still needed
2100 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2101 + mips_regnum (gdbarch)->pc]
2102 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2106 /* If we didn't reach the end of the prologue when scanning the function
2107 instructions, then set end_prologue_addr to the address of the
2108 instruction immediately after the last one we scanned. */
2109 /* brobecker/2004-10-10: I don't think this would ever happen, but
2110 we may as well be careful and do our best if we have a null
2111 end_prologue_addr. */
2112 if (end_prologue_addr == 0)
2113 end_prologue_addr = cur_pc;
2115 /* In a frameless function, we might have incorrectly
2116 skipped some load immediate instructions. Undo the skipping
2117 if the load immediate was not followed by a stack adjustment. */
2118 if (load_immediate_bytes && !seen_sp_adjust)
2119 end_prologue_addr -= load_immediate_bytes;
2121 return end_prologue_addr;
2124 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2125 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2126 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2129 static struct mips_frame_cache *
2130 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
2132 struct mips_frame_cache *cache;
2134 if ((*this_cache) != NULL)
2135 return (*this_cache);
2137 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2138 (*this_cache) = cache;
2139 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2141 /* Analyze the function prologue. */
2143 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2144 CORE_ADDR start_addr;
2146 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2147 if (start_addr == 0)
2148 start_addr = heuristic_proc_start (pc);
2149 /* We can't analyze the prologue if we couldn't find the begining
2151 if (start_addr == 0)
2154 mips32_scan_prologue (start_addr, pc, this_frame, *this_cache);
2157 /* gdbarch_sp_regnum contains the value and not the address. */
2158 trad_frame_set_value (cache->saved_regs,
2159 gdbarch_num_regs (get_frame_arch (this_frame))
2163 return (*this_cache);
2167 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
2168 struct frame_id *this_id)
2170 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2172 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2175 static struct value *
2176 mips_insn32_frame_prev_register (struct frame_info *this_frame,
2177 void **this_cache, int regnum)
2179 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2181 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2185 mips_insn32_frame_sniffer (const struct frame_unwind *self,
2186 struct frame_info *this_frame, void **this_cache)
2188 CORE_ADDR pc = get_frame_pc (this_frame);
2189 if (! mips_pc_is_mips16 (pc))
2194 static const struct frame_unwind mips_insn32_frame_unwind =
2197 mips_insn32_frame_this_id,
2198 mips_insn32_frame_prev_register,
2200 mips_insn32_frame_sniffer
2204 mips_insn32_frame_base_address (struct frame_info *this_frame,
2207 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2212 static const struct frame_base mips_insn32_frame_base =
2214 &mips_insn32_frame_unwind,
2215 mips_insn32_frame_base_address,
2216 mips_insn32_frame_base_address,
2217 mips_insn32_frame_base_address
2220 static const struct frame_base *
2221 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
2223 CORE_ADDR pc = get_frame_pc (this_frame);
2224 if (! mips_pc_is_mips16 (pc))
2225 return &mips_insn32_frame_base;
2230 static struct trad_frame_cache *
2231 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
2234 CORE_ADDR start_addr;
2235 CORE_ADDR stack_addr;
2236 struct trad_frame_cache *this_trad_cache;
2237 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2238 int num_regs = gdbarch_num_regs (gdbarch);
2240 if ((*this_cache) != NULL)
2241 return (*this_cache);
2242 this_trad_cache = trad_frame_cache_zalloc (this_frame);
2243 (*this_cache) = this_trad_cache;
2245 /* The return address is in the link register. */
2246 trad_frame_set_reg_realreg (this_trad_cache,
2247 gdbarch_pc_regnum (gdbarch),
2248 num_regs + MIPS_RA_REGNUM);
2250 /* Frame ID, since it's a frameless / stackless function, no stack
2251 space is allocated and SP on entry is the current SP. */
2252 pc = get_frame_pc (this_frame);
2253 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2254 stack_addr = get_frame_register_signed (this_frame,
2255 num_regs + MIPS_SP_REGNUM);
2256 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
2258 /* Assume that the frame's base is the same as the
2260 trad_frame_set_this_base (this_trad_cache, stack_addr);
2262 return this_trad_cache;
2266 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
2267 struct frame_id *this_id)
2269 struct trad_frame_cache *this_trad_cache
2270 = mips_stub_frame_cache (this_frame, this_cache);
2271 trad_frame_get_id (this_trad_cache, this_id);
2274 static struct value *
2275 mips_stub_frame_prev_register (struct frame_info *this_frame,
2276 void **this_cache, int regnum)
2278 struct trad_frame_cache *this_trad_cache
2279 = mips_stub_frame_cache (this_frame, this_cache);
2280 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
2284 mips_stub_frame_sniffer (const struct frame_unwind *self,
2285 struct frame_info *this_frame, void **this_cache)
2288 struct obj_section *s;
2289 CORE_ADDR pc = get_frame_address_in_block (this_frame);
2291 /* Use the stub unwinder for unreadable code. */
2292 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2295 if (in_plt_section (pc, NULL))
2298 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2299 s = find_pc_section (pc);
2302 && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
2303 ".MIPS.stubs") == 0)
2309 static const struct frame_unwind mips_stub_frame_unwind =
2312 mips_stub_frame_this_id,
2313 mips_stub_frame_prev_register,
2315 mips_stub_frame_sniffer
2319 mips_stub_frame_base_address (struct frame_info *this_frame,
2322 struct trad_frame_cache *this_trad_cache
2323 = mips_stub_frame_cache (this_frame, this_cache);
2324 return trad_frame_get_this_base (this_trad_cache);
2327 static const struct frame_base mips_stub_frame_base =
2329 &mips_stub_frame_unwind,
2330 mips_stub_frame_base_address,
2331 mips_stub_frame_base_address,
2332 mips_stub_frame_base_address
2335 static const struct frame_base *
2336 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
2338 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
2339 return &mips_stub_frame_base;
2344 /* mips_addr_bits_remove - remove useless address bits */
2347 mips_addr_bits_remove (CORE_ADDR addr)
2349 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2350 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
2351 /* This hack is a work-around for existing boards using PMON, the
2352 simulator, and any other 64-bit targets that doesn't have true
2353 64-bit addressing. On these targets, the upper 32 bits of
2354 addresses are ignored by the hardware. Thus, the PC or SP are
2355 likely to have been sign extended to all 1s by instruction
2356 sequences that load 32-bit addresses. For example, a typical
2357 piece of code that loads an address is this:
2359 lui $r2, <upper 16 bits>
2360 ori $r2, <lower 16 bits>
2362 But the lui sign-extends the value such that the upper 32 bits
2363 may be all 1s. The workaround is simply to mask off these
2364 bits. In the future, gcc may be changed to support true 64-bit
2365 addressing, and this masking will have to be disabled. */
2366 return addr &= 0xffffffffUL;
2371 /* Instructions used during single-stepping of atomic sequences. */
2372 #define LL_OPCODE 0x30
2373 #define LLD_OPCODE 0x34
2374 #define SC_OPCODE 0x38
2375 #define SCD_OPCODE 0x3c
2377 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2378 instruction and ending with a SC/SCD instruction. If such a sequence
2379 is found, attempt to step through it. A breakpoint is placed at the end of
2383 deal_with_atomic_sequence (CORE_ADDR pc)
2385 CORE_ADDR breaks[2] = {-1, -1};
2387 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
2391 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2392 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2397 insn = mips_fetch_instruction (loc);
2398 /* Assume all atomic sequences start with a ll/lld instruction. */
2399 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
2402 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2404 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2407 loc += MIPS_INSN32_SIZE;
2408 insn = mips_fetch_instruction (loc);
2410 /* Assume that there is at most one branch in the atomic
2411 sequence. If a branch is found, put a breakpoint in its
2412 destination address. */
2413 switch (itype_op (insn))
2415 case 0: /* SPECIAL */
2416 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
2417 return 0; /* fallback to the standard single-step code. */
2419 case 1: /* REGIMM */
2420 is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */
2424 return 0; /* fallback to the standard single-step code. */
2431 case 22: /* BLEZL */
2432 case 23: /* BGTTL */
2438 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2443 branch_bp = loc + mips32_relative_offset (insn) + 4;
2444 if (last_breakpoint >= 1)
2445 return 0; /* More than one branch found, fallback to the
2446 standard single-step code. */
2447 breaks[1] = branch_bp;
2451 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
2455 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2456 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
2459 loc += MIPS_INSN32_SIZE;
2461 /* Insert a breakpoint right after the end of the atomic sequence. */
2464 /* Check for duplicated breakpoints. Check also for a breakpoint
2465 placed (branch instruction's destination) in the atomic sequence */
2466 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
2467 last_breakpoint = 0;
2469 /* Effectively inserts the breakpoints. */
2470 for (index = 0; index <= last_breakpoint; index++)
2471 insert_single_step_breakpoint (breaks[index]);
2476 /* mips_software_single_step() is called just before we want to resume
2477 the inferior, if we want to single-step it but there is no hardware
2478 or kernel single-step support (MIPS on GNU/Linux for example). We find
2479 the target of the coming instruction and breakpoint it. */
2482 mips_software_single_step (struct frame_info *frame)
2484 CORE_ADDR pc, next_pc;
2486 pc = get_frame_pc (frame);
2487 if (deal_with_atomic_sequence (pc))
2490 next_pc = mips_next_pc (frame, pc);
2492 insert_single_step_breakpoint (next_pc);
2496 /* Test whether the PC points to the return instruction at the
2497 end of a function. */
2500 mips_about_to_return (CORE_ADDR pc)
2502 if (mips_pc_is_mips16 (pc))
2503 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2504 generates a "jr $ra"; other times it generates code to load
2505 the return address from the stack to an accessible register (such
2506 as $a3), then a "jr" using that register. This second case
2507 is almost impossible to distinguish from an indirect jump
2508 used for switch statements, so we don't even try. */
2509 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
2511 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
2515 /* This fencepost looks highly suspicious to me. Removing it also
2516 seems suspicious as it could affect remote debugging across serial
2520 heuristic_proc_start (CORE_ADDR pc)
2527 pc = gdbarch_addr_bits_remove (current_gdbarch, pc);
2529 fence = start_pc - heuristic_fence_post;
2533 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
2534 fence = VM_MIN_ADDRESS;
2536 instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE;
2538 /* search back for previous return */
2539 for (start_pc -= instlen;; start_pc -= instlen)
2540 if (start_pc < fence)
2542 /* It's not clear to me why we reach this point when
2543 stop_soon, but with this test, at least we
2544 don't print out warnings for every child forked (eg, on
2545 decstation). 22apr93 rich@cygnus.com. */
2546 if (stop_soon == NO_STOP_QUIETLY)
2548 static int blurb_printed = 0;
2550 warning (_("GDB can't find the start of the function at 0x%s."),
2555 /* This actually happens frequently in embedded
2556 development, when you first connect to a board
2557 and your stack pointer and pc are nowhere in
2558 particular. This message needs to give people
2559 in that situation enough information to
2560 determine that it's no big deal. */
2561 printf_filtered ("\n\
2562 GDB is unable to find the start of the function at 0x%s\n\
2563 and thus can't determine the size of that function's stack frame.\n\
2564 This means that GDB may be unable to access that stack frame, or\n\
2565 the frames below it.\n\
2566 This problem is most likely caused by an invalid program counter or\n\
2568 However, if you think GDB should simply search farther back\n\
2569 from 0x%s for code which looks like the beginning of a\n\
2570 function, you can increase the range of the search using the `set\n\
2571 heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
2578 else if (mips_pc_is_mips16 (start_pc))
2580 unsigned short inst;
2582 /* On MIPS16, any one of the following is likely to be the
2583 start of a function:
2589 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2590 inst = mips_fetch_instruction (start_pc);
2591 if ((inst & 0xff80) == 0x6480) /* save */
2593 if (start_pc - instlen >= fence)
2595 inst = mips_fetch_instruction (start_pc - instlen);
2596 if ((inst & 0xf800) == 0xf000) /* extend */
2597 start_pc -= instlen;
2601 else if (((inst & 0xf81f) == 0xe809
2602 && (inst & 0x700) != 0x700) /* entry */
2603 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
2604 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
2605 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
2607 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
2608 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2613 else if (mips_about_to_return (start_pc))
2615 /* Skip return and its delay slot. */
2616 start_pc += 2 * MIPS_INSN32_SIZE;
2623 struct mips_objfile_private
2629 /* According to the current ABI, should the type be passed in a
2630 floating-point register (assuming that there is space)? When there
2631 is no FPU, FP are not even considered as possible candidates for
2632 FP registers and, consequently this returns false - forces FP
2633 arguments into integer registers. */
2636 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2638 return ((typecode == TYPE_CODE_FLT
2640 && (typecode == TYPE_CODE_STRUCT
2641 || typecode == TYPE_CODE_UNION)
2642 && TYPE_NFIELDS (arg_type) == 1
2643 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
2645 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2648 /* On o32, argument passing in GPRs depends on the alignment of the type being
2649 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2652 mips_type_needs_double_align (struct type *type)
2654 enum type_code typecode = TYPE_CODE (type);
2656 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2658 else if (typecode == TYPE_CODE_STRUCT)
2660 if (TYPE_NFIELDS (type) < 1)
2662 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2664 else if (typecode == TYPE_CODE_UNION)
2668 n = TYPE_NFIELDS (type);
2669 for (i = 0; i < n; i++)
2670 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2677 /* Adjust the address downward (direction of stack growth) so that it
2678 is correctly aligned for a new stack frame. */
2680 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2682 return align_down (addr, 16);
2686 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2687 struct regcache *regcache, CORE_ADDR bp_addr,
2688 int nargs, struct value **args, CORE_ADDR sp,
2689 int struct_return, CORE_ADDR struct_addr)
2695 int stack_offset = 0;
2696 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2697 CORE_ADDR func_addr = find_function_addr (function, NULL);
2698 int regsize = mips_abi_regsize (gdbarch);
2700 /* For shared libraries, "t9" needs to point at the function
2702 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2704 /* Set the return address register to point to the entry point of
2705 the program, where a breakpoint lies in wait. */
2706 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2708 /* First ensure that the stack and structure return address (if any)
2709 are properly aligned. The stack has to be at least 64-bit
2710 aligned even on 32-bit machines, because doubles must be 64-bit
2711 aligned. For n32 and n64, stack frames need to be 128-bit
2712 aligned, so we round to this widest known alignment. */
2714 sp = align_down (sp, 16);
2715 struct_addr = align_down (struct_addr, 16);
2717 /* Now make space on the stack for the args. We allocate more
2718 than necessary for EABI, because the first few arguments are
2719 passed in registers, but that's OK. */
2720 for (argnum = 0; argnum < nargs; argnum++)
2721 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
2722 sp -= align_up (len, 16);
2725 fprintf_unfiltered (gdb_stdlog,
2726 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2727 paddr_nz (sp), (long) align_up (len, 16));
2729 /* Initialize the integer and float register pointers. */
2730 argreg = MIPS_A0_REGNUM;
2731 float_argreg = mips_fpa0_regnum (gdbarch);
2733 /* The struct_return pointer occupies the first parameter-passing reg. */
2737 fprintf_unfiltered (gdb_stdlog,
2738 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2739 argreg, paddr_nz (struct_addr));
2740 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
2743 /* Now load as many as possible of the first arguments into
2744 registers, and push the rest onto the stack. Loop thru args
2745 from first to last. */
2746 for (argnum = 0; argnum < nargs; argnum++)
2748 const gdb_byte *val;
2749 gdb_byte valbuf[MAX_REGISTER_SIZE];
2750 struct value *arg = args[argnum];
2751 struct type *arg_type = check_typedef (value_type (arg));
2752 int len = TYPE_LENGTH (arg_type);
2753 enum type_code typecode = TYPE_CODE (arg_type);
2756 fprintf_unfiltered (gdb_stdlog,
2757 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2758 argnum + 1, len, (int) typecode);
2760 /* The EABI passes structures that do not fit in a register by
2763 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2765 store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg));
2766 typecode = TYPE_CODE_PTR;
2770 fprintf_unfiltered (gdb_stdlog, " push");
2773 val = value_contents (arg);
2775 /* 32-bit ABIs always start floating point arguments in an
2776 even-numbered floating point register. Round the FP register
2777 up before the check to see if there are any FP registers
2778 left. Non MIPS_EABI targets also pass the FP in the integer
2779 registers so also round up normal registers. */
2780 if (regsize < 8 && fp_register_arg_p (typecode, arg_type))
2782 if ((float_argreg & 1))
2786 /* Floating point arguments passed in registers have to be
2787 treated specially. On 32-bit architectures, doubles
2788 are passed in register pairs; the even register gets
2789 the low word, and the odd register gets the high word.
2790 On non-EABI processors, the first two floating point arguments are
2791 also copied to general registers, because MIPS16 functions
2792 don't use float registers for arguments. This duplication of
2793 arguments in general registers can't hurt non-MIPS16 functions
2794 because those registers are normally skipped. */
2795 /* MIPS_EABI squeezes a struct that contains a single floating
2796 point value into an FP register instead of pushing it onto the
2798 if (fp_register_arg_p (typecode, arg_type)
2799 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2801 /* EABI32 will pass doubles in consecutive registers, even on
2802 64-bit cores. At one time, we used to check the size of
2803 `float_argreg' to determine whether or not to pass doubles
2804 in consecutive registers, but this is not sufficient for
2805 making the ABI determination. */
2806 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
2808 int low_offset = gdbarch_byte_order (gdbarch)
2809 == BFD_ENDIAN_BIG ? 4 : 0;
2810 unsigned long regval;
2812 /* Write the low word of the double to the even register(s). */
2813 regval = extract_unsigned_integer (val + low_offset, 4);
2815 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2816 float_argreg, phex (regval, 4));
2817 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2819 /* Write the high word of the double to the odd register(s). */
2820 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2822 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2823 float_argreg, phex (regval, 4));
2824 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2828 /* This is a floating point value that fits entirely
2829 in a single register. */
2830 /* On 32 bit ABI's the float_argreg is further adjusted
2831 above to ensure that it is even register aligned. */
2832 LONGEST regval = extract_unsigned_integer (val, len);
2834 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2835 float_argreg, phex (regval, len));
2836 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2841 /* Copy the argument to general registers or the stack in
2842 register-sized pieces. Large arguments are split between
2843 registers and stack. */
2844 /* Note: structs whose size is not a multiple of regsize
2845 are treated specially: Irix cc passes
2846 them in registers where gcc sometimes puts them on the
2847 stack. For maximum compatibility, we will put them in
2849 int odd_sized_struct = (len > regsize && len % regsize != 0);
2851 /* Note: Floating-point values that didn't fit into an FP
2852 register are only written to memory. */
2855 /* Remember if the argument was written to the stack. */
2856 int stack_used_p = 0;
2857 int partial_len = (len < regsize ? len : regsize);
2860 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2863 /* Write this portion of the argument to the stack. */
2864 if (argreg > MIPS_LAST_ARG_REGNUM
2866 || fp_register_arg_p (typecode, arg_type))
2868 /* Should shorter than int integer values be
2869 promoted to int before being stored? */
2870 int longword_offset = 0;
2873 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2876 && (typecode == TYPE_CODE_INT
2877 || typecode == TYPE_CODE_PTR
2878 || typecode == TYPE_CODE_FLT) && len <= 4)
2879 longword_offset = regsize - len;
2880 else if ((typecode == TYPE_CODE_STRUCT
2881 || typecode == TYPE_CODE_UNION)
2882 && TYPE_LENGTH (arg_type) < regsize)
2883 longword_offset = regsize - len;
2888 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2889 paddr_nz (stack_offset));
2890 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2891 paddr_nz (longword_offset));
2894 addr = sp + stack_offset + longword_offset;
2899 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2901 for (i = 0; i < partial_len; i++)
2903 fprintf_unfiltered (gdb_stdlog, "%02x",
2907 write_memory (addr, val, partial_len);
2910 /* Note!!! This is NOT an else clause. Odd sized
2911 structs may go thru BOTH paths. Floating point
2912 arguments will not. */
2913 /* Write this portion of the argument to a general
2914 purpose register. */
2915 if (argreg <= MIPS_LAST_ARG_REGNUM
2916 && !fp_register_arg_p (typecode, arg_type))
2919 extract_unsigned_integer (val, partial_len);
2922 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2924 phex (regval, regsize));
2925 regcache_cooked_write_unsigned (regcache, argreg, regval);
2932 /* Compute the the offset into the stack at which we
2933 will copy the next parameter.
2935 In the new EABI (and the NABI32), the stack_offset
2936 only needs to be adjusted when it has been used. */
2939 stack_offset += align_up (partial_len, regsize);
2943 fprintf_unfiltered (gdb_stdlog, "\n");
2946 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2948 /* Return adjusted stack pointer. */
2952 /* Determine the return value convention being used. */
2954 static enum return_value_convention
2955 mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type,
2956 struct type *type, struct regcache *regcache,
2957 gdb_byte *readbuf, const gdb_byte *writebuf)
2959 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2960 int fp_return_type = 0;
2961 int offset, regnum, xfer;
2963 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2964 return RETURN_VALUE_STRUCT_CONVENTION;
2966 /* Floating point type? */
2967 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
2969 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2971 /* Structs with a single field of float type
2972 are returned in a floating point register. */
2973 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
2974 || TYPE_CODE (type) == TYPE_CODE_UNION)
2975 && TYPE_NFIELDS (type) == 1)
2977 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
2979 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
2986 /* A floating-point value belongs in the least significant part
2989 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
2990 regnum = mips_regnum (gdbarch)->fp0;
2994 /* An integer value goes in V0/V1. */
2996 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
2997 regnum = MIPS_V0_REGNUM;
3000 offset < TYPE_LENGTH (type);
3001 offset += mips_abi_regsize (gdbarch), regnum++)
3003 xfer = mips_abi_regsize (gdbarch);
3004 if (offset + xfer > TYPE_LENGTH (type))
3005 xfer = TYPE_LENGTH (type) - offset;
3006 mips_xfer_register (gdbarch, regcache,
3007 gdbarch_num_regs (gdbarch) + regnum, xfer,
3008 gdbarch_byte_order (gdbarch), readbuf, writebuf,
3012 return RETURN_VALUE_REGISTER_CONVENTION;
3016 /* N32/N64 ABI stuff. */
3018 /* Search for a naturally aligned double at OFFSET inside a struct
3019 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3023 mips_n32n64_fp_arg_chunk_p (struct type *arg_type, int offset)
3027 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
3030 if (MIPS_FPU_TYPE != MIPS_FPU_DOUBLE)
3033 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
3036 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
3039 struct type *field_type;
3041 /* We're only looking at normal fields. */
3042 if (TYPE_FIELD_STATIC (arg_type, i)
3043 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
3046 /* If we have gone past the offset, there is no double to pass. */
3047 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
3051 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
3053 /* If this field is entirely before the requested offset, go
3054 on to the next one. */
3055 if (pos + TYPE_LENGTH (field_type) <= offset)
3058 /* If this is our special aligned double, we can stop. */
3059 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
3060 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
3063 /* This field starts at or before the requested offset, and
3064 overlaps it. If it is a structure, recurse inwards. */
3065 return mips_n32n64_fp_arg_chunk_p (field_type, offset - pos);
3072 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3073 struct regcache *regcache, CORE_ADDR bp_addr,
3074 int nargs, struct value **args, CORE_ADDR sp,
3075 int struct_return, CORE_ADDR struct_addr)
3081 int stack_offset = 0;
3082 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3083 CORE_ADDR func_addr = find_function_addr (function, NULL);
3085 /* For shared libraries, "t9" needs to point at the function
3087 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3089 /* Set the return address register to point to the entry point of
3090 the program, where a breakpoint lies in wait. */
3091 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3093 /* First ensure that the stack and structure return address (if any)
3094 are properly aligned. The stack has to be at least 64-bit
3095 aligned even on 32-bit machines, because doubles must be 64-bit
3096 aligned. For n32 and n64, stack frames need to be 128-bit
3097 aligned, so we round to this widest known alignment. */
3099 sp = align_down (sp, 16);
3100 struct_addr = align_down (struct_addr, 16);
3102 /* Now make space on the stack for the args. */
3103 for (argnum = 0; argnum < nargs; argnum++)
3104 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
3105 sp -= align_up (len, 16);
3108 fprintf_unfiltered (gdb_stdlog,
3109 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3110 paddr_nz (sp), (long) align_up (len, 16));
3112 /* Initialize the integer and float register pointers. */
3113 argreg = MIPS_A0_REGNUM;
3114 float_argreg = mips_fpa0_regnum (gdbarch);
3116 /* The struct_return pointer occupies the first parameter-passing reg. */
3120 fprintf_unfiltered (gdb_stdlog,
3121 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3122 argreg, paddr_nz (struct_addr));
3123 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3126 /* Now load as many as possible of the first arguments into
3127 registers, and push the rest onto the stack. Loop thru args
3128 from first to last. */
3129 for (argnum = 0; argnum < nargs; argnum++)
3131 const gdb_byte *val;
3132 struct value *arg = args[argnum];
3133 struct type *arg_type = check_typedef (value_type (arg));
3134 int len = TYPE_LENGTH (arg_type);
3135 enum type_code typecode = TYPE_CODE (arg_type);
3138 fprintf_unfiltered (gdb_stdlog,
3139 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3140 argnum + 1, len, (int) typecode);
3142 val = value_contents (arg);
3144 if (fp_register_arg_p (typecode, arg_type)
3145 && argreg <= MIPS_LAST_ARG_REGNUM)
3147 /* This is a floating point value that fits entirely
3148 in a single register. */
3149 LONGEST regval = extract_unsigned_integer (val, len);
3151 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3152 float_argreg, phex (regval, len));
3153 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3156 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3157 argreg, phex (regval, len));
3158 regcache_cooked_write_unsigned (regcache, argreg, regval);
3164 /* Copy the argument to general registers or the stack in
3165 register-sized pieces. Large arguments are split between
3166 registers and stack. */
3167 /* For N32/N64, structs, unions, or other composite types are
3168 treated as a sequence of doublewords, and are passed in integer
3169 or floating point registers as though they were simple scalar
3170 parameters to the extent that they fit, with any excess on the
3171 stack packed according to the normal memory layout of the
3173 The caller does not reserve space for the register arguments;
3174 the callee is responsible for reserving it if required. */
3175 /* Note: Floating-point values that didn't fit into an FP
3176 register are only written to memory. */
3179 /* Remember if the argument was written to the stack. */
3180 int stack_used_p = 0;
3181 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3184 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3187 if (fp_register_arg_p (typecode, arg_type))
3188 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM);
3190 /* Write this portion of the argument to the stack. */
3191 if (argreg > MIPS_LAST_ARG_REGNUM)
3193 /* Should shorter than int integer values be
3194 promoted to int before being stored? */
3195 int longword_offset = 0;
3198 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
3200 if ((typecode == TYPE_CODE_INT
3201 || typecode == TYPE_CODE_PTR
3202 || typecode == TYPE_CODE_FLT)
3204 longword_offset = MIPS64_REGSIZE - len;
3209 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3210 paddr_nz (stack_offset));
3211 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3212 paddr_nz (longword_offset));
3215 addr = sp + stack_offset + longword_offset;
3220 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3222 for (i = 0; i < partial_len; i++)
3224 fprintf_unfiltered (gdb_stdlog, "%02x",
3228 write_memory (addr, val, partial_len);
3231 /* Note!!! This is NOT an else clause. Odd sized
3232 structs may go thru BOTH paths. */
3233 /* Write this portion of the argument to a general
3234 purpose register. */
3235 if (argreg <= MIPS_LAST_ARG_REGNUM)
3239 /* Sign extend pointers, 32-bit integers and signed
3240 16-bit and 8-bit integers; everything else is taken
3243 if ((partial_len == 4
3244 && (typecode == TYPE_CODE_PTR
3245 || typecode == TYPE_CODE_INT))
3247 && typecode == TYPE_CODE_INT
3248 && !TYPE_UNSIGNED (arg_type)))
3249 regval = extract_signed_integer (val, partial_len);
3251 regval = extract_unsigned_integer (val, partial_len);
3253 /* A non-floating-point argument being passed in a
3254 general register. If a struct or union, and if
3255 the remaining length is smaller than the register
3256 size, we have to adjust the register value on
3259 It does not seem to be necessary to do the
3260 same for integral types. */
3262 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3263 && partial_len < MIPS64_REGSIZE
3264 && (typecode == TYPE_CODE_STRUCT
3265 || typecode == TYPE_CODE_UNION))
3266 regval <<= ((MIPS64_REGSIZE - partial_len)
3270 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3272 phex (regval, MIPS64_REGSIZE));
3273 regcache_cooked_write_unsigned (regcache, argreg, regval);
3275 if (mips_n32n64_fp_arg_chunk_p (arg_type,
3276 TYPE_LENGTH (arg_type) - len))
3279 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
3281 phex (regval, MIPS64_REGSIZE));
3282 regcache_cooked_write_unsigned (regcache, float_argreg,
3293 /* Compute the the offset into the stack at which we
3294 will copy the next parameter.
3296 In N32 (N64?), the stack_offset only needs to be
3297 adjusted when it has been used. */
3300 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
3304 fprintf_unfiltered (gdb_stdlog, "\n");
3307 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3309 /* Return adjusted stack pointer. */
3313 static enum return_value_convention
3314 mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type,
3315 struct type *type, struct regcache *regcache,
3316 gdb_byte *readbuf, const gdb_byte *writebuf)
3318 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3320 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3322 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3323 if needed), as appropriate for the type. Composite results (struct,
3324 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3327 * A struct with only one or two floating point fields is returned in $f0
3328 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3331 * Any other struct or union results of at most 128 bits are returned in
3332 $2 (first 64 bits) and $3 (remainder, if necessary).
3334 * Larger composite results are handled by converting the function to a
3335 procedure with an implicit first parameter, which is a pointer to an area
3336 reserved by the caller to receive the result. [The o32-bit ABI requires
3337 that all composite results be handled by conversion to implicit first
3338 parameters. The MIPS/SGI Fortran implementation has always made a
3339 specific exception to return COMPLEX results in the floating point
3342 if (TYPE_CODE (type) == TYPE_CODE_ARRAY
3343 || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
3344 return RETURN_VALUE_STRUCT_CONVENTION;
3345 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3346 && TYPE_LENGTH (type) == 16
3347 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3349 /* A 128-bit floating-point value fills both $f0 and $f2. The
3350 two registers are used in the same as memory order, so the
3351 eight bytes with the lower memory address are in $f0. */
3353 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
3354 mips_xfer_register (gdbarch, regcache,
3355 gdbarch_num_regs (gdbarch)
3356 + mips_regnum (gdbarch)->fp0,
3357 8, gdbarch_byte_order (gdbarch),
3358 readbuf, writebuf, 0);
3359 mips_xfer_register (gdbarch, regcache,
3360 gdbarch_num_regs (gdbarch)
3361 + mips_regnum (gdbarch)->fp0 + 2,
3362 8, gdbarch_byte_order (gdbarch),
3363 readbuf ? readbuf + 8 : readbuf,
3364 writebuf ? writebuf + 8 : writebuf, 0);
3365 return RETURN_VALUE_REGISTER_CONVENTION;
3367 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3368 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3370 /* A single or double floating-point value that fits in FP0. */
3372 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3373 mips_xfer_register (gdbarch, regcache,
3374 gdbarch_num_regs (gdbarch)
3375 + mips_regnum (gdbarch)->fp0,
3377 gdbarch_byte_order (gdbarch),
3378 readbuf, writebuf, 0);
3379 return RETURN_VALUE_REGISTER_CONVENTION;
3381 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3382 && TYPE_NFIELDS (type) <= 2
3383 && TYPE_NFIELDS (type) >= 1
3384 && ((TYPE_NFIELDS (type) == 1
3385 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3387 || (TYPE_NFIELDS (type) == 2
3388 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3390 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
3392 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3394 /* A struct that contains one or two floats. Each value is part
3395 in the least significant part of their floating point
3399 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
3400 field < TYPE_NFIELDS (type); field++, regnum += 2)
3402 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3405 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3407 mips_xfer_register (gdbarch, regcache,
3408 gdbarch_num_regs (gdbarch) + regnum,
3409 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3410 gdbarch_byte_order (gdbarch),
3411 readbuf, writebuf, offset);
3413 return RETURN_VALUE_REGISTER_CONVENTION;
3415 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3416 || TYPE_CODE (type) == TYPE_CODE_UNION)
3418 /* A structure or union. Extract the left justified value,
3419 regardless of the byte order. I.e. DO NOT USE
3423 for (offset = 0, regnum = MIPS_V0_REGNUM;
3424 offset < TYPE_LENGTH (type);
3425 offset += register_size (gdbarch, regnum), regnum++)
3427 int xfer = register_size (gdbarch, regnum);
3428 if (offset + xfer > TYPE_LENGTH (type))
3429 xfer = TYPE_LENGTH (type) - offset;
3431 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3432 offset, xfer, regnum);
3433 mips_xfer_register (gdbarch, regcache,
3434 gdbarch_num_regs (gdbarch) + regnum,
3435 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
3438 return RETURN_VALUE_REGISTER_CONVENTION;
3442 /* A scalar extract each part but least-significant-byte
3446 for (offset = 0, regnum = MIPS_V0_REGNUM;
3447 offset < TYPE_LENGTH (type);
3448 offset += register_size (gdbarch, regnum), regnum++)
3450 int xfer = register_size (gdbarch, regnum);
3451 if (offset + xfer > TYPE_LENGTH (type))
3452 xfer = TYPE_LENGTH (type) - offset;
3454 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3455 offset, xfer, regnum);
3456 mips_xfer_register (gdbarch, regcache,
3457 gdbarch_num_regs (gdbarch) + regnum,
3458 xfer, gdbarch_byte_order (gdbarch),
3459 readbuf, writebuf, offset);
3461 return RETURN_VALUE_REGISTER_CONVENTION;
3465 /* O32 ABI stuff. */
3468 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3469 struct regcache *regcache, CORE_ADDR bp_addr,
3470 int nargs, struct value **args, CORE_ADDR sp,
3471 int struct_return, CORE_ADDR struct_addr)
3477 int stack_offset = 0;
3478 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3479 CORE_ADDR func_addr = find_function_addr (function, NULL);
3481 /* For shared libraries, "t9" needs to point at the function
3483 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3485 /* Set the return address register to point to the entry point of
3486 the program, where a breakpoint lies in wait. */
3487 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3489 /* First ensure that the stack and structure return address (if any)
3490 are properly aligned. The stack has to be at least 64-bit
3491 aligned even on 32-bit machines, because doubles must be 64-bit
3492 aligned. For n32 and n64, stack frames need to be 128-bit
3493 aligned, so we round to this widest known alignment. */
3495 sp = align_down (sp, 16);
3496 struct_addr = align_down (struct_addr, 16);
3498 /* Now make space on the stack for the args. */
3499 for (argnum = 0; argnum < nargs; argnum++)
3501 struct type *arg_type = check_typedef (value_type (args[argnum]));
3502 int arglen = TYPE_LENGTH (arg_type);
3504 /* Align to double-word if necessary. */
3505 if (mips_type_needs_double_align (arg_type))
3506 len = align_up (len, MIPS32_REGSIZE * 2);
3507 /* Allocate space on the stack. */
3508 len += align_up (arglen, MIPS32_REGSIZE);
3510 sp -= align_up (len, 16);
3513 fprintf_unfiltered (gdb_stdlog,
3514 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3515 paddr_nz (sp), (long) align_up (len, 16));
3517 /* Initialize the integer and float register pointers. */
3518 argreg = MIPS_A0_REGNUM;
3519 float_argreg = mips_fpa0_regnum (gdbarch);
3521 /* The struct_return pointer occupies the first parameter-passing reg. */
3525 fprintf_unfiltered (gdb_stdlog,
3526 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3527 argreg, paddr_nz (struct_addr));
3528 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3529 stack_offset += MIPS32_REGSIZE;
3532 /* Now load as many as possible of the first arguments into
3533 registers, and push the rest onto the stack. Loop thru args
3534 from first to last. */
3535 for (argnum = 0; argnum < nargs; argnum++)
3537 const gdb_byte *val;
3538 struct value *arg = args[argnum];
3539 struct type *arg_type = check_typedef (value_type (arg));
3540 int len = TYPE_LENGTH (arg_type);
3541 enum type_code typecode = TYPE_CODE (arg_type);
3544 fprintf_unfiltered (gdb_stdlog,
3545 "mips_o32_push_dummy_call: %d len=%d type=%d",
3546 argnum + 1, len, (int) typecode);
3548 val = value_contents (arg);
3550 /* 32-bit ABIs always start floating point arguments in an
3551 even-numbered floating point register. Round the FP register
3552 up before the check to see if there are any FP registers
3553 left. O32/O64 targets also pass the FP in the integer
3554 registers so also round up normal registers. */
3555 if (fp_register_arg_p (typecode, arg_type))
3557 if ((float_argreg & 1))
3561 /* Floating point arguments passed in registers have to be
3562 treated specially. On 32-bit architectures, doubles
3563 are passed in register pairs; the even register gets
3564 the low word, and the odd register gets the high word.
3565 On O32/O64, the first two floating point arguments are
3566 also copied to general registers, because MIPS16 functions
3567 don't use float registers for arguments. This duplication of
3568 arguments in general registers can't hurt non-MIPS16 functions
3569 because those registers are normally skipped. */
3571 if (fp_register_arg_p (typecode, arg_type)
3572 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3574 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
3576 int low_offset = gdbarch_byte_order (gdbarch)
3577 == BFD_ENDIAN_BIG ? 4 : 0;
3578 unsigned long regval;
3580 /* Write the low word of the double to the even register(s). */
3581 regval = extract_unsigned_integer (val + low_offset, 4);
3583 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3584 float_argreg, phex (regval, 4));
3585 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3587 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3588 argreg, phex (regval, 4));
3589 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3591 /* Write the high word of the double to the odd register(s). */
3592 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3594 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3595 float_argreg, phex (regval, 4));
3596 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3599 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3600 argreg, phex (regval, 4));
3601 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3605 /* This is a floating point value that fits entirely
3606 in a single register. */
3607 /* On 32 bit ABI's the float_argreg is further adjusted
3608 above to ensure that it is even register aligned. */
3609 LONGEST regval = extract_unsigned_integer (val, len);
3611 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3612 float_argreg, phex (regval, len));
3613 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3614 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3615 registers for each argument. The below is (my
3616 guess) to ensure that the corresponding integer
3617 register has reserved the same space. */
3619 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3620 argreg, phex (regval, len));
3621 regcache_cooked_write_unsigned (regcache, argreg, regval);
3624 /* Reserve space for the FP register. */
3625 stack_offset += align_up (len, MIPS32_REGSIZE);
3629 /* Copy the argument to general registers or the stack in
3630 register-sized pieces. Large arguments are split between
3631 registers and stack. */
3632 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3633 are treated specially: Irix cc passes
3634 them in registers where gcc sometimes puts them on the
3635 stack. For maximum compatibility, we will put them in
3637 int odd_sized_struct = (len > MIPS32_REGSIZE
3638 && len % MIPS32_REGSIZE != 0);
3639 /* Structures should be aligned to eight bytes (even arg registers)
3640 on MIPS_ABI_O32, if their first member has double precision. */
3641 if (mips_type_needs_double_align (arg_type))
3646 stack_offset += MIPS32_REGSIZE;
3651 /* Remember if the argument was written to the stack. */
3652 int stack_used_p = 0;
3653 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
3656 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3659 /* Write this portion of the argument to the stack. */
3660 if (argreg > MIPS_LAST_ARG_REGNUM
3661 || odd_sized_struct)
3663 /* Should shorter than int integer values be
3664 promoted to int before being stored? */
3665 int longword_offset = 0;
3671 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3672 paddr_nz (stack_offset));
3673 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3674 paddr_nz (longword_offset));
3677 addr = sp + stack_offset + longword_offset;
3682 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3684 for (i = 0; i < partial_len; i++)
3686 fprintf_unfiltered (gdb_stdlog, "%02x",
3690 write_memory (addr, val, partial_len);
3693 /* Note!!! This is NOT an else clause. Odd sized
3694 structs may go thru BOTH paths. */
3695 /* Write this portion of the argument to a general
3696 purpose register. */
3697 if (argreg <= MIPS_LAST_ARG_REGNUM)
3699 LONGEST regval = extract_signed_integer (val, partial_len);
3700 /* Value may need to be sign extended, because
3701 mips_isa_regsize() != mips_abi_regsize(). */
3703 /* A non-floating-point argument being passed in a
3704 general register. If a struct or union, and if
3705 the remaining length is smaller than the register
3706 size, we have to adjust the register value on
3709 It does not seem to be necessary to do the
3710 same for integral types.
3712 Also don't do this adjustment on O64 binaries.
3714 cagney/2001-07-23: gdb/179: Also, GCC, when
3715 outputting LE O32 with sizeof (struct) <
3716 mips_abi_regsize(), generates a left shift
3717 as part of storing the argument in a register
3718 (the left shift isn't generated when
3719 sizeof (struct) >= mips_abi_regsize()). Since
3720 it is quite possible that this is GCC
3721 contradicting the LE/O32 ABI, GDB has not been
3722 adjusted to accommodate this. Either someone
3723 needs to demonstrate that the LE/O32 ABI
3724 specifies such a left shift OR this new ABI gets
3725 identified as such and GDB gets tweaked
3728 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3729 && partial_len < MIPS32_REGSIZE
3730 && (typecode == TYPE_CODE_STRUCT
3731 || typecode == TYPE_CODE_UNION))
3732 regval <<= ((MIPS32_REGSIZE - partial_len)
3736 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3738 phex (regval, MIPS32_REGSIZE));
3739 regcache_cooked_write_unsigned (regcache, argreg, regval);
3742 /* Prevent subsequent floating point arguments from
3743 being passed in floating point registers. */
3744 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3750 /* Compute the the offset into the stack at which we
3751 will copy the next parameter.
3753 In older ABIs, the caller reserved space for
3754 registers that contained arguments. This was loosely
3755 refered to as their "home". Consequently, space is
3756 always allocated. */
3758 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
3762 fprintf_unfiltered (gdb_stdlog, "\n");
3765 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3767 /* Return adjusted stack pointer. */
3771 static enum return_value_convention
3772 mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type,
3773 struct type *type, struct regcache *regcache,
3774 gdb_byte *readbuf, const gdb_byte *writebuf)
3776 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3778 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3779 || TYPE_CODE (type) == TYPE_CODE_UNION
3780 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3781 return RETURN_VALUE_STRUCT_CONVENTION;
3782 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3783 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3785 /* A single-precision floating-point value. It fits in the
3786 least significant part of FP0. */
3788 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3789 mips_xfer_register (gdbarch, regcache,
3790 gdbarch_num_regs (gdbarch)
3791 + mips_regnum (gdbarch)->fp0,
3793 gdbarch_byte_order (gdbarch),
3794 readbuf, writebuf, 0);
3795 return RETURN_VALUE_REGISTER_CONVENTION;
3797 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3798 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3800 /* A double-precision floating-point value. The most
3801 significant part goes in FP1, and the least significant in
3804 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3805 switch (gdbarch_byte_order (gdbarch))
3807 case BFD_ENDIAN_LITTLE:
3808 mips_xfer_register (gdbarch, regcache,
3809 gdbarch_num_regs (gdbarch)
3810 + mips_regnum (gdbarch)->fp0 +
3811 0, 4, gdbarch_byte_order (gdbarch),
3812 readbuf, writebuf, 0);
3813 mips_xfer_register (gdbarch, regcache,
3814 gdbarch_num_regs (gdbarch)
3815 + mips_regnum (gdbarch)->fp0 + 1,
3816 4, gdbarch_byte_order (gdbarch),
3817 readbuf, writebuf, 4);
3819 case BFD_ENDIAN_BIG:
3820 mips_xfer_register (gdbarch, regcache,
3821 gdbarch_num_regs (gdbarch)
3822 + mips_regnum (gdbarch)->fp0 + 1,
3823 4, gdbarch_byte_order (gdbarch),
3824 readbuf, writebuf, 0);
3825 mips_xfer_register (gdbarch, regcache,
3826 gdbarch_num_regs (gdbarch)
3827 + mips_regnum (gdbarch)->fp0 + 0,
3828 4, gdbarch_byte_order (gdbarch),
3829 readbuf, writebuf, 4);
3832 internal_error (__FILE__, __LINE__, _("bad switch"));
3834 return RETURN_VALUE_REGISTER_CONVENTION;
3837 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3838 && TYPE_NFIELDS (type) <= 2
3839 && TYPE_NFIELDS (type) >= 1
3840 && ((TYPE_NFIELDS (type) == 1
3841 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3843 || (TYPE_NFIELDS (type) == 2
3844 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3846 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3848 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3850 /* A struct that contains one or two floats. Each value is part
3851 in the least significant part of their floating point
3853 gdb_byte reg[MAX_REGISTER_SIZE];
3856 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
3857 field < TYPE_NFIELDS (type); field++, regnum += 2)
3859 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3862 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3864 mips_xfer_register (gdbarch, regcache,
3865 gdbarch_num_regs (gdbarch) + regnum,
3866 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3867 gdbarch_byte_order (gdbarch),
3868 readbuf, writebuf, offset);
3870 return RETURN_VALUE_REGISTER_CONVENTION;
3874 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3875 || TYPE_CODE (type) == TYPE_CODE_UNION)
3877 /* A structure or union. Extract the left justified value,
3878 regardless of the byte order. I.e. DO NOT USE
3882 for (offset = 0, regnum = MIPS_V0_REGNUM;
3883 offset < TYPE_LENGTH (type);
3884 offset += register_size (gdbarch, regnum), regnum++)
3886 int xfer = register_size (gdbarch, regnum);
3887 if (offset + xfer > TYPE_LENGTH (type))
3888 xfer = TYPE_LENGTH (type) - offset;
3890 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3891 offset, xfer, regnum);
3892 mips_xfer_register (gdbarch, regcache,
3893 gdbarch_num_regs (gdbarch) + regnum, xfer,
3894 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3896 return RETURN_VALUE_REGISTER_CONVENTION;
3901 /* A scalar extract each part but least-significant-byte
3902 justified. o32 thinks registers are 4 byte, regardless of
3906 for (offset = 0, regnum = MIPS_V0_REGNUM;
3907 offset < TYPE_LENGTH (type);
3908 offset += MIPS32_REGSIZE, regnum++)
3910 int xfer = MIPS32_REGSIZE;
3911 if (offset + xfer > TYPE_LENGTH (type))
3912 xfer = TYPE_LENGTH (type) - offset;
3914 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3915 offset, xfer, regnum);
3916 mips_xfer_register (gdbarch, regcache,
3917 gdbarch_num_regs (gdbarch) + regnum, xfer,
3918 gdbarch_byte_order (gdbarch),
3919 readbuf, writebuf, offset);
3921 return RETURN_VALUE_REGISTER_CONVENTION;
3925 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3929 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3930 struct regcache *regcache, CORE_ADDR bp_addr,
3932 struct value **args, CORE_ADDR sp,
3933 int struct_return, CORE_ADDR struct_addr)
3939 int stack_offset = 0;
3940 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3941 CORE_ADDR func_addr = find_function_addr (function, NULL);
3943 /* For shared libraries, "t9" needs to point at the function
3945 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3947 /* Set the return address register to point to the entry point of
3948 the program, where a breakpoint lies in wait. */
3949 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3951 /* First ensure that the stack and structure return address (if any)
3952 are properly aligned. The stack has to be at least 64-bit
3953 aligned even on 32-bit machines, because doubles must be 64-bit
3954 aligned. For n32 and n64, stack frames need to be 128-bit
3955 aligned, so we round to this widest known alignment. */
3957 sp = align_down (sp, 16);
3958 struct_addr = align_down (struct_addr, 16);
3960 /* Now make space on the stack for the args. */
3961 for (argnum = 0; argnum < nargs; argnum++)
3963 struct type *arg_type = check_typedef (value_type (args[argnum]));
3964 int arglen = TYPE_LENGTH (arg_type);
3966 /* Allocate space on the stack. */
3967 len += align_up (arglen, MIPS64_REGSIZE);
3969 sp -= align_up (len, 16);
3972 fprintf_unfiltered (gdb_stdlog,
3973 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3974 paddr_nz (sp), (long) align_up (len, 16));
3976 /* Initialize the integer and float register pointers. */
3977 argreg = MIPS_A0_REGNUM;
3978 float_argreg = mips_fpa0_regnum (gdbarch);
3980 /* The struct_return pointer occupies the first parameter-passing reg. */
3984 fprintf_unfiltered (gdb_stdlog,
3985 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3986 argreg, paddr_nz (struct_addr));
3987 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3988 stack_offset += MIPS64_REGSIZE;
3991 /* Now load as many as possible of the first arguments into
3992 registers, and push the rest onto the stack. Loop thru args
3993 from first to last. */
3994 for (argnum = 0; argnum < nargs; argnum++)
3996 const gdb_byte *val;
3997 struct value *arg = args[argnum];
3998 struct type *arg_type = check_typedef (value_type (arg));
3999 int len = TYPE_LENGTH (arg_type);
4000 enum type_code typecode = TYPE_CODE (arg_type);
4003 fprintf_unfiltered (gdb_stdlog,
4004 "mips_o64_push_dummy_call: %d len=%d type=%d",
4005 argnum + 1, len, (int) typecode);
4007 val = value_contents (arg);
4009 /* Floating point arguments passed in registers have to be
4010 treated specially. On 32-bit architectures, doubles
4011 are passed in register pairs; the even register gets
4012 the low word, and the odd register gets the high word.
4013 On O32/O64, the first two floating point arguments are
4014 also copied to general registers, because MIPS16 functions
4015 don't use float registers for arguments. This duplication of
4016 arguments in general registers can't hurt non-MIPS16 functions
4017 because those registers are normally skipped. */
4019 if (fp_register_arg_p (typecode, arg_type)
4020 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
4022 LONGEST regval = extract_unsigned_integer (val, len);
4024 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4025 float_argreg, phex (regval, len));
4026 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
4028 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4029 argreg, phex (regval, len));
4030 regcache_cooked_write_unsigned (regcache, argreg, regval);
4032 /* Reserve space for the FP register. */
4033 stack_offset += align_up (len, MIPS64_REGSIZE);
4037 /* Copy the argument to general registers or the stack in
4038 register-sized pieces. Large arguments are split between
4039 registers and stack. */
4040 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4041 are treated specially: Irix cc passes them in registers
4042 where gcc sometimes puts them on the stack. For maximum
4043 compatibility, we will put them in both places. */
4044 int odd_sized_struct = (len > MIPS64_REGSIZE
4045 && len % MIPS64_REGSIZE != 0);
4048 /* Remember if the argument was written to the stack. */
4049 int stack_used_p = 0;
4050 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4053 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4056 /* Write this portion of the argument to the stack. */
4057 if (argreg > MIPS_LAST_ARG_REGNUM
4058 || odd_sized_struct)
4060 /* Should shorter than int integer values be
4061 promoted to int before being stored? */
4062 int longword_offset = 0;
4065 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4067 if ((typecode == TYPE_CODE_INT
4068 || typecode == TYPE_CODE_PTR
4069 || typecode == TYPE_CODE_FLT)
4071 longword_offset = MIPS64_REGSIZE - len;
4076 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
4077 paddr_nz (stack_offset));
4078 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
4079 paddr_nz (longword_offset));
4082 addr = sp + stack_offset + longword_offset;
4087 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
4089 for (i = 0; i < partial_len; i++)
4091 fprintf_unfiltered (gdb_stdlog, "%02x",
4095 write_memory (addr, val, partial_len);
4098 /* Note!!! This is NOT an else clause. Odd sized
4099 structs may go thru BOTH paths. */
4100 /* Write this portion of the argument to a general
4101 purpose register. */
4102 if (argreg <= MIPS_LAST_ARG_REGNUM)
4104 LONGEST regval = extract_signed_integer (val, partial_len);
4105 /* Value may need to be sign extended, because
4106 mips_isa_regsize() != mips_abi_regsize(). */
4108 /* A non-floating-point argument being passed in a
4109 general register. If a struct or union, and if
4110 the remaining length is smaller than the register
4111 size, we have to adjust the register value on
4114 It does not seem to be necessary to do the
4115 same for integral types. */
4117 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
4118 && partial_len < MIPS64_REGSIZE
4119 && (typecode == TYPE_CODE_STRUCT
4120 || typecode == TYPE_CODE_UNION))
4121 regval <<= ((MIPS64_REGSIZE - partial_len)
4125 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4127 phex (regval, MIPS64_REGSIZE));
4128 regcache_cooked_write_unsigned (regcache, argreg, regval);
4131 /* Prevent subsequent floating point arguments from
4132 being passed in floating point registers. */
4133 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
4139 /* Compute the the offset into the stack at which we
4140 will copy the next parameter.
4142 In older ABIs, the caller reserved space for
4143 registers that contained arguments. This was loosely
4144 refered to as their "home". Consequently, space is
4145 always allocated. */
4147 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
4151 fprintf_unfiltered (gdb_stdlog, "\n");
4154 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4156 /* Return adjusted stack pointer. */
4160 static enum return_value_convention
4161 mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type,
4162 struct type *type, struct regcache *regcache,
4163 gdb_byte *readbuf, const gdb_byte *writebuf)
4165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4167 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4168 || TYPE_CODE (type) == TYPE_CODE_UNION
4169 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
4170 return RETURN_VALUE_STRUCT_CONVENTION;
4171 else if (fp_register_arg_p (TYPE_CODE (type), type))
4173 /* A floating-point value. It fits in the least significant
4176 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4177 mips_xfer_register (gdbarch, regcache,
4178 gdbarch_num_regs (gdbarch)
4179 + mips_regnum (gdbarch)->fp0,
4181 gdbarch_byte_order (gdbarch),
4182 readbuf, writebuf, 0);
4183 return RETURN_VALUE_REGISTER_CONVENTION;
4187 /* A scalar extract each part but least-significant-byte
4191 for (offset = 0, regnum = MIPS_V0_REGNUM;
4192 offset < TYPE_LENGTH (type);
4193 offset += MIPS64_REGSIZE, regnum++)
4195 int xfer = MIPS64_REGSIZE;
4196 if (offset + xfer > TYPE_LENGTH (type))
4197 xfer = TYPE_LENGTH (type) - offset;
4199 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4200 offset, xfer, regnum);
4201 mips_xfer_register (gdbarch, regcache,
4202 gdbarch_num_regs (gdbarch) + regnum,
4203 xfer, gdbarch_byte_order (gdbarch),
4204 readbuf, writebuf, offset);
4206 return RETURN_VALUE_REGISTER_CONVENTION;
4210 /* Floating point register management.
4212 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4213 64bit operations, these early MIPS cpus treat fp register pairs
4214 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4215 registers and offer a compatibility mode that emulates the MIPS2 fp
4216 model. When operating in MIPS2 fp compat mode, later cpu's split
4217 double precision floats into two 32-bit chunks and store them in
4218 consecutive fp regs. To display 64-bit floats stored in this
4219 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4220 Throw in user-configurable endianness and you have a real mess.
4222 The way this works is:
4223 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4224 double-precision value will be split across two logical registers.
4225 The lower-numbered logical register will hold the low-order bits,
4226 regardless of the processor's endianness.
4227 - If we are on a 64-bit processor, and we are looking for a
4228 single-precision value, it will be in the low ordered bits
4229 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4230 save slot in memory.
4231 - If we are in 64-bit mode, everything is straightforward.
4233 Note that this code only deals with "live" registers at the top of the
4234 stack. We will attempt to deal with saved registers later, when
4235 the raw/cooked register interface is in place. (We need a general
4236 interface that can deal with dynamic saved register sizes -- fp
4237 regs could be 32 bits wide in one frame and 64 on the frame above
4240 static struct type *
4241 mips_float_register_type (void)
4243 return builtin_type_ieee_single;
4246 static struct type *
4247 mips_double_register_type (void)
4249 return builtin_type_ieee_double;
4252 /* Copy a 32-bit single-precision value from the current frame
4253 into rare_buffer. */
4256 mips_read_fp_register_single (struct frame_info *frame, int regno,
4257 gdb_byte *rare_buffer)
4259 struct gdbarch *gdbarch = get_frame_arch (frame);
4260 int raw_size = register_size (gdbarch, regno);
4261 gdb_byte *raw_buffer = alloca (raw_size);
4263 if (!frame_register_read (frame, regno, raw_buffer))
4264 error (_("can't read register %d (%s)"),
4265 regno, gdbarch_register_name (gdbarch, regno));
4268 /* We have a 64-bit value for this register. Find the low-order
4272 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4277 memcpy (rare_buffer, raw_buffer + offset, 4);
4281 memcpy (rare_buffer, raw_buffer, 4);
4285 /* Copy a 64-bit double-precision value from the current frame into
4286 rare_buffer. This may include getting half of it from the next
4290 mips_read_fp_register_double (struct frame_info *frame, int regno,
4291 gdb_byte *rare_buffer)
4293 struct gdbarch *gdbarch = get_frame_arch (frame);
4294 int raw_size = register_size (gdbarch, regno);
4296 if (raw_size == 8 && !mips2_fp_compat (frame))
4298 /* We have a 64-bit value for this register, and we should use
4300 if (!frame_register_read (frame, regno, rare_buffer))
4301 error (_("can't read register %d (%s)"),
4302 regno, gdbarch_register_name (gdbarch, regno));
4306 int rawnum = regno % gdbarch_num_regs (gdbarch);
4308 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
4309 internal_error (__FILE__, __LINE__,
4310 _("mips_read_fp_register_double: bad access to "
4311 "odd-numbered FP register"));
4313 /* mips_read_fp_register_single will find the correct 32 bits from
4315 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4317 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4318 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4322 mips_read_fp_register_single (frame, regno, rare_buffer);
4323 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4329 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4331 { /* do values for FP (float) regs */
4332 struct gdbarch *gdbarch = get_frame_arch (frame);
4333 gdb_byte *raw_buffer;
4334 double doub, flt1; /* doubles extracted from raw hex data */
4337 raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0));
4339 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
4340 fprintf_filtered (file, "%*s",
4341 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
4344 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
4346 /* 4-byte registers: Print hex and floating. Also print even
4347 numbered registers as doubles. */
4348 mips_read_fp_register_single (frame, regnum, raw_buffer);
4349 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4351 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
4354 fprintf_filtered (file, " flt: ");
4356 fprintf_filtered (file, " <invalid float> ");
4358 fprintf_filtered (file, "%-17.9g", flt1);
4360 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
4362 mips_read_fp_register_double (frame, regnum, raw_buffer);
4363 doub = unpack_double (mips_double_register_type (), raw_buffer,
4366 fprintf_filtered (file, " dbl: ");
4368 fprintf_filtered (file, "<invalid double>");
4370 fprintf_filtered (file, "%-24.17g", doub);
4375 /* Eight byte registers: print each one as hex, float and double. */
4376 mips_read_fp_register_single (frame, regnum, raw_buffer);
4377 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4379 mips_read_fp_register_double (frame, regnum, raw_buffer);
4380 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4383 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
4386 fprintf_filtered (file, " flt: ");
4388 fprintf_filtered (file, "<invalid float>");
4390 fprintf_filtered (file, "%-17.9g", flt1);
4392 fprintf_filtered (file, " dbl: ");
4394 fprintf_filtered (file, "<invalid double>");
4396 fprintf_filtered (file, "%-24.17g", doub);
4401 mips_print_register (struct ui_file *file, struct frame_info *frame,
4404 struct gdbarch *gdbarch = get_frame_arch (frame);
4405 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4408 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4410 mips_print_fp_register (file, frame, regnum);
4414 /* Get the data in raw format. */
4415 if (!frame_register_read (frame, regnum, raw_buffer))
4417 fprintf_filtered (file, "%s: [Invalid]",
4418 gdbarch_register_name (gdbarch, regnum));
4422 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
4424 /* The problem with printing numeric register names (r26, etc.) is that
4425 the user can't use them on input. Probably the best solution is to
4426 fix it so that either the numeric or the funky (a2, etc.) names
4427 are accepted on input. */
4428 if (regnum < MIPS_NUMREGS)
4429 fprintf_filtered (file, "(r%d): ", regnum);
4431 fprintf_filtered (file, ": ");
4433 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4435 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4439 print_scalar_formatted (raw_buffer + offset,
4440 register_type (gdbarch, regnum), 'x', 0,
4444 /* Replacement for generic do_registers_info.
4445 Print regs in pretty columns. */
4448 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4451 fprintf_filtered (file, " ");
4452 mips_print_fp_register (file, frame, regnum);
4453 fprintf_filtered (file, "\n");
4458 /* Print a row's worth of GP (int) registers, with name labels above */
4461 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4464 struct gdbarch *gdbarch = get_frame_arch (frame);
4465 /* do values for GP (int) regs */
4466 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4467 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4471 /* For GP registers, we print a separate row of names above the vals */
4472 for (col = 0, regnum = start_regnum;
4473 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4474 + gdbarch_num_pseudo_regs (gdbarch);
4477 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4478 continue; /* unused register */
4479 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4481 break; /* end the row: reached FP register */
4482 /* Large registers are handled separately. */
4483 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4486 break; /* End the row before this register. */
4488 /* Print this register on a row by itself. */
4489 mips_print_register (file, frame, regnum);
4490 fprintf_filtered (file, "\n");
4494 fprintf_filtered (file, " ");
4495 fprintf_filtered (file,
4496 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
4497 gdbarch_register_name (gdbarch, regnum));
4504 /* print the R0 to R31 names */
4505 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
4506 fprintf_filtered (file, "\n R%-4d",
4507 start_regnum % gdbarch_num_regs (gdbarch));
4509 fprintf_filtered (file, "\n ");
4511 /* now print the values in hex, 4 or 8 to the row */
4512 for (col = 0, regnum = start_regnum;
4513 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4514 + gdbarch_num_pseudo_regs (gdbarch);
4517 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4518 continue; /* unused register */
4519 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4521 break; /* end row: reached FP register */
4522 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4523 break; /* End row: large register. */
4525 /* OK: get the data in raw format. */
4526 if (!frame_register_read (frame, regnum, raw_buffer))
4527 error (_("can't read register %d (%s)"),
4528 regnum, gdbarch_register_name (gdbarch, regnum));
4529 /* pad small registers */
4531 byte < (mips_abi_regsize (gdbarch)
4532 - register_size (gdbarch, regnum)); byte++)
4533 printf_filtered (" ");
4534 /* Now print the register value in hex, endian order. */
4535 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4537 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4538 byte < register_size (gdbarch, regnum); byte++)
4539 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4541 for (byte = register_size (gdbarch, regnum) - 1;
4543 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4544 fprintf_filtered (file, " ");
4547 if (col > 0) /* ie. if we actually printed anything... */
4548 fprintf_filtered (file, "\n");
4553 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4556 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4557 struct frame_info *frame, int regnum, int all)
4559 if (regnum != -1) /* do one specified register */
4561 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
4562 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
4563 error (_("Not a valid register for the current processor type"));
4565 mips_print_register (file, frame, regnum);
4566 fprintf_filtered (file, "\n");
4569 /* do all (or most) registers */
4571 regnum = gdbarch_num_regs (gdbarch);
4572 while (regnum < gdbarch_num_regs (gdbarch)
4573 + gdbarch_num_pseudo_regs (gdbarch))
4575 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4578 if (all) /* true for "INFO ALL-REGISTERS" command */
4579 regnum = print_fp_register_row (file, frame, regnum);
4581 regnum += MIPS_NUMREGS; /* skip floating point regs */
4584 regnum = print_gp_register_row (file, frame, regnum);
4589 /* Is this a branch with a delay slot? */
4592 is_delayed (unsigned long insn)
4595 for (i = 0; i < NUMOPCODES; ++i)
4596 if (mips_opcodes[i].pinfo != INSN_MACRO
4597 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4599 return (i < NUMOPCODES
4600 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4601 | INSN_COND_BRANCH_DELAY
4602 | INSN_COND_BRANCH_LIKELY)));
4606 mips_single_step_through_delay (struct gdbarch *gdbarch,
4607 struct frame_info *frame)
4609 CORE_ADDR pc = get_frame_pc (frame);
4610 gdb_byte buf[MIPS_INSN32_SIZE];
4612 /* There is no branch delay slot on MIPS16. */
4613 if (mips_pc_is_mips16 (pc))
4616 if (!breakpoint_here_p (pc + 4))
4619 if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf))
4620 /* If error reading memory, guess that it is not a delayed
4623 return is_delayed (extract_unsigned_integer (buf, sizeof buf));
4626 /* To skip prologues, I use this predicate. Returns either PC itself
4627 if the code at PC does not look like a function prologue; otherwise
4628 returns an address that (if we're lucky) follows the prologue. If
4629 LENIENT, then we must skip everything which is involved in setting
4630 up the frame (it's OK to skip more, just so long as we don't skip
4631 anything which might clobber the registers which are being saved.
4632 We must skip more in the case where part of the prologue is in the
4633 delay slot of a non-prologue instruction). */
4636 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
4639 CORE_ADDR func_addr;
4641 /* See if we can determine the end of the prologue via the symbol table.
4642 If so, then return either PC, or the PC after the prologue, whichever
4644 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
4646 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
4647 if (post_prologue_pc != 0)
4648 return max (pc, post_prologue_pc);
4651 /* Can't determine prologue from the symbol table, need to examine
4654 /* Find an upper limit on the function prologue using the debug
4655 information. If the debug information could not be used to provide
4656 that bound, then use an arbitrary large number as the upper bound. */
4657 limit_pc = skip_prologue_using_sal (pc);
4659 limit_pc = pc + 100; /* Magic. */
4661 if (mips_pc_is_mips16 (pc))
4662 return mips16_scan_prologue (pc, limit_pc, NULL, NULL);
4664 return mips32_scan_prologue (pc, limit_pc, NULL, NULL);
4667 /* Check whether the PC is in a function epilogue (32-bit version).
4668 This is a helper function for mips_in_function_epilogue_p. */
4670 mips32_in_function_epilogue_p (CORE_ADDR pc)
4672 CORE_ADDR func_addr = 0, func_end = 0;
4674 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4676 /* The MIPS epilogue is max. 12 bytes long. */
4677 CORE_ADDR addr = func_end - 12;
4679 if (addr < func_addr + 4)
4680 addr = func_addr + 4;
4684 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
4686 unsigned long high_word;
4689 inst = mips_fetch_instruction (pc);
4690 high_word = (inst >> 16) & 0xffff;
4692 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
4693 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
4694 && inst != 0x03e00008 /* jr $ra */
4695 && inst != 0x00000000) /* nop */
4705 /* Check whether the PC is in a function epilogue (16-bit version).
4706 This is a helper function for mips_in_function_epilogue_p. */
4708 mips16_in_function_epilogue_p (CORE_ADDR pc)
4710 CORE_ADDR func_addr = 0, func_end = 0;
4712 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4714 /* The MIPS epilogue is max. 12 bytes long. */
4715 CORE_ADDR addr = func_end - 12;
4717 if (addr < func_addr + 4)
4718 addr = func_addr + 4;
4722 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
4724 unsigned short inst;
4726 inst = mips_fetch_instruction (pc);
4728 if ((inst & 0xf800) == 0xf000) /* extend */
4731 if (inst != 0x6300 /* addiu $sp,offset */
4732 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
4733 && inst != 0xe820 /* jr $ra */
4734 && inst != 0xe8a0 /* jrc $ra */
4735 && inst != 0x6500) /* nop */
4745 /* The epilogue is defined here as the area at the end of a function,
4746 after an instruction which destroys the function's stack frame. */
4748 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4750 if (mips_pc_is_mips16 (pc))
4751 return mips16_in_function_epilogue_p (pc);
4753 return mips32_in_function_epilogue_p (pc);
4756 /* Root of all "set mips "/"show mips " commands. This will eventually be
4757 used for all MIPS-specific commands. */
4760 show_mips_command (char *args, int from_tty)
4762 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4766 set_mips_command (char *args, int from_tty)
4769 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4770 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4773 /* Commands to show/set the MIPS FPU type. */
4776 show_mipsfpu_command (char *args, int from_tty)
4780 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
4783 ("The MIPS floating-point coprocessor is unknown "
4784 "because the current architecture is not MIPS.\n");
4788 switch (MIPS_FPU_TYPE)
4790 case MIPS_FPU_SINGLE:
4791 fpu = "single-precision";
4793 case MIPS_FPU_DOUBLE:
4794 fpu = "double-precision";
4797 fpu = "absent (none)";
4800 internal_error (__FILE__, __LINE__, _("bad switch"));
4802 if (mips_fpu_type_auto)
4804 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4808 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4813 set_mipsfpu_command (char *args, int from_tty)
4816 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4817 show_mipsfpu_command (args, from_tty);
4821 set_mipsfpu_single_command (char *args, int from_tty)
4823 struct gdbarch_info info;
4824 gdbarch_info_init (&info);
4825 mips_fpu_type = MIPS_FPU_SINGLE;
4826 mips_fpu_type_auto = 0;
4827 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4828 instead of relying on globals. Doing that would let generic code
4829 handle the search for this specific architecture. */
4830 if (!gdbarch_update_p (info))
4831 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4835 set_mipsfpu_double_command (char *args, int from_tty)
4837 struct gdbarch_info info;
4838 gdbarch_info_init (&info);
4839 mips_fpu_type = MIPS_FPU_DOUBLE;
4840 mips_fpu_type_auto = 0;
4841 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4842 instead of relying on globals. Doing that would let generic code
4843 handle the search for this specific architecture. */
4844 if (!gdbarch_update_p (info))
4845 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4849 set_mipsfpu_none_command (char *args, int from_tty)
4851 struct gdbarch_info info;
4852 gdbarch_info_init (&info);
4853 mips_fpu_type = MIPS_FPU_NONE;
4854 mips_fpu_type_auto = 0;
4855 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4856 instead of relying on globals. Doing that would let generic code
4857 handle the search for this specific architecture. */
4858 if (!gdbarch_update_p (info))
4859 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4863 set_mipsfpu_auto_command (char *args, int from_tty)
4865 mips_fpu_type_auto = 1;
4868 /* Attempt to identify the particular processor model by reading the
4869 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4870 the relevant processor still exists (it dates back to '94) and
4871 secondly this is not the way to do this. The processor type should
4872 be set by forcing an architecture change. */
4875 deprecated_mips_set_processor_regs_hack (void)
4877 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4880 regcache_cooked_read_unsigned (get_current_regcache (),
4881 MIPS_PRID_REGNUM, &prid);
4882 if ((prid & ~0xf) == 0x700)
4883 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4886 /* Just like reinit_frame_cache, but with the right arguments to be
4887 callable as an sfunc. */
4890 reinit_frame_cache_sfunc (char *args, int from_tty,
4891 struct cmd_list_element *c)
4893 reinit_frame_cache ();
4897 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4899 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4901 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4902 disassembler needs to be able to locally determine the ISA, and
4903 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4905 if (mips_pc_is_mips16 (memaddr))
4906 info->mach = bfd_mach_mips16;
4908 /* Round down the instruction address to the appropriate boundary. */
4909 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4911 /* Set the disassembler options. */
4912 if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64)
4914 /* Set up the disassembler info, so that we get the right
4915 register names from libopcodes. */
4916 if (tdep->mips_abi == MIPS_ABI_N32)
4917 info->disassembler_options = "gpr-names=n32";
4919 info->disassembler_options = "gpr-names=64";
4920 info->flavour = bfd_target_elf_flavour;
4923 /* This string is not recognized explicitly by the disassembler,
4924 but it tells the disassembler to not try to guess the ABI from
4925 the bfd elf headers, such that, if the user overrides the ABI
4926 of a program linked as NewABI, the disassembly will follow the
4927 register naming conventions specified by the user. */
4928 info->disassembler_options = "gpr-names=32";
4930 /* Call the appropriate disassembler based on the target endian-ness. */
4931 if (info->endian == BFD_ENDIAN_BIG)
4932 return print_insn_big_mips (memaddr, info);
4934 return print_insn_little_mips (memaddr, info);
4937 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4938 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4939 It returns a pointer to a string of bytes that encode a breakpoint
4940 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4941 necessary) to point to the actual memory location where the breakpoint
4942 should be inserted. */
4944 static const gdb_byte *
4945 mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
4947 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4949 if (mips_pc_is_mips16 (*pcptr))
4951 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
4952 *pcptr = unmake_mips16_addr (*pcptr);
4953 *lenptr = sizeof (mips16_big_breakpoint);
4954 return mips16_big_breakpoint;
4958 /* The IDT board uses an unusual breakpoint value, and
4959 sometimes gets confused when it sees the usual MIPS
4960 breakpoint instruction. */
4961 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
4962 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
4963 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
4965 *lenptr = sizeof (big_breakpoint);
4967 if (strcmp (target_shortname, "mips") == 0)
4968 return idt_big_breakpoint;
4969 else if (strcmp (target_shortname, "ddb") == 0
4970 || strcmp (target_shortname, "pmon") == 0
4971 || strcmp (target_shortname, "lsi") == 0)
4972 return pmon_big_breakpoint;
4974 return big_breakpoint;
4979 if (mips_pc_is_mips16 (*pcptr))
4981 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
4982 *pcptr = unmake_mips16_addr (*pcptr);
4983 *lenptr = sizeof (mips16_little_breakpoint);
4984 return mips16_little_breakpoint;
4988 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
4989 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
4990 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
4992 *lenptr = sizeof (little_breakpoint);
4994 if (strcmp (target_shortname, "mips") == 0)
4995 return idt_little_breakpoint;
4996 else if (strcmp (target_shortname, "ddb") == 0
4997 || strcmp (target_shortname, "pmon") == 0
4998 || strcmp (target_shortname, "lsi") == 0)
4999 return pmon_little_breakpoint;
5001 return little_breakpoint;
5006 /* If PC is in a mips16 call or return stub, return the address of the target
5007 PC, which is either the callee or the caller. There are several
5008 cases which must be handled:
5010 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5011 target PC is in $31 ($ra).
5012 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5013 and the target PC is in $2.
5014 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5015 before the jal instruction, this is effectively a call stub
5016 and the the target PC is in $2. Otherwise this is effectively
5017 a return stub and the target PC is in $18.
5019 See the source code for the stubs in gcc/config/mips/mips16.S for
5023 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5026 CORE_ADDR start_addr;
5028 /* Find the starting address and name of the function containing the PC. */
5029 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5032 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5033 target PC is in $31 ($ra). */
5034 if (strcmp (name, "__mips16_ret_sf") == 0
5035 || strcmp (name, "__mips16_ret_df") == 0)
5036 return get_frame_register_signed (frame, MIPS_RA_REGNUM);
5038 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5040 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5041 and the target PC is in $2. */
5042 if (name[19] >= '0' && name[19] <= '9')
5043 return get_frame_register_signed (frame, 2);
5045 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5046 before the jal instruction, this is effectively a call stub
5047 and the the target PC is in $2. Otherwise this is effectively
5048 a return stub and the target PC is in $18. */
5049 else if (name[19] == 's' || name[19] == 'd')
5051 if (pc == start_addr)
5053 /* Check if the target of the stub is a compiler-generated
5054 stub. Such a stub for a function bar might have a name
5055 like __fn_stub_bar, and might look like this:
5060 la $1,bar (becomes a lui/addiu pair)
5062 So scan down to the lui/addi and extract the target
5063 address from those two instructions. */
5065 CORE_ADDR target_pc = get_frame_register_signed (frame, 2);
5069 /* See if the name of the target function is __fn_stub_*. */
5070 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
5073 if (strncmp (name, "__fn_stub_", 10) != 0
5074 && strcmp (name, "etext") != 0
5075 && strcmp (name, "_etext") != 0)
5078 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5079 The limit on the search is arbitrarily set to 20
5080 instructions. FIXME. */
5081 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE)
5083 inst = mips_fetch_instruction (target_pc);
5084 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5085 pc = (inst << 16) & 0xffff0000; /* high word */
5086 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5087 return pc | (inst & 0xffff); /* low word */
5090 /* Couldn't find the lui/addui pair, so return stub address. */
5094 /* This is the 'return' part of a call stub. The return
5095 address is in $r18. */
5096 return get_frame_register_signed (frame, 18);
5099 return 0; /* not a stub */
5102 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5103 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5106 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
5109 if (num >= 0 && num < 32)
5111 else if (num >= 38 && num < 70)
5112 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
5114 regnum = mips_regnum (gdbarch)->hi;
5116 regnum = mips_regnum (gdbarch)->lo;
5118 /* This will hopefully (eventually) provoke a warning. Should
5119 we be calling complaint() here? */
5120 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5121 return gdbarch_num_regs (gdbarch) + regnum;
5125 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5126 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5129 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
5132 if (num >= 0 && num < 32)
5134 else if (num >= 32 && num < 64)
5135 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
5137 regnum = mips_regnum (gdbarch)->hi;
5139 regnum = mips_regnum (gdbarch)->lo;
5141 /* This will hopefully (eventually) provoke a warning. Should we
5142 be calling complaint() here? */
5143 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5144 return gdbarch_num_regs (gdbarch) + regnum;
5148 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
5150 /* Only makes sense to supply raw registers. */
5151 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
5152 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5153 decide if it is valid. Should instead define a standard sim/gdb
5154 register numbering scheme. */
5155 if (gdbarch_register_name (gdbarch,
5156 gdbarch_num_regs (gdbarch) + regnum) != NULL
5157 && gdbarch_register_name (gdbarch,
5158 gdbarch_num_regs (gdbarch) + regnum)[0] != '\0')
5161 return LEGACY_SIM_REGNO_IGNORE;
5165 /* Convert an integer into an address. Extracting the value signed
5166 guarantees a correctly sign extended address. */
5169 mips_integer_to_address (struct gdbarch *gdbarch,
5170 struct type *type, const gdb_byte *buf)
5172 return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type));
5175 /* Dummy virtual frame pointer method. This is no more or less accurate
5176 than most other architectures; we just need to be explicit about it,
5177 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5178 an assertion failure. */
5181 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
5182 CORE_ADDR pc, int *reg, LONGEST *offset)
5184 *reg = MIPS_SP_REGNUM;
5189 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5191 enum mips_abi *abip = (enum mips_abi *) obj;
5192 const char *name = bfd_get_section_name (abfd, sect);
5194 if (*abip != MIPS_ABI_UNKNOWN)
5197 if (strncmp (name, ".mdebug.", 8) != 0)
5200 if (strcmp (name, ".mdebug.abi32") == 0)
5201 *abip = MIPS_ABI_O32;
5202 else if (strcmp (name, ".mdebug.abiN32") == 0)
5203 *abip = MIPS_ABI_N32;
5204 else if (strcmp (name, ".mdebug.abi64") == 0)
5205 *abip = MIPS_ABI_N64;
5206 else if (strcmp (name, ".mdebug.abiO64") == 0)
5207 *abip = MIPS_ABI_O64;
5208 else if (strcmp (name, ".mdebug.eabi32") == 0)
5209 *abip = MIPS_ABI_EABI32;
5210 else if (strcmp (name, ".mdebug.eabi64") == 0)
5211 *abip = MIPS_ABI_EABI64;
5213 warning (_("unsupported ABI %s."), name + 8);
5217 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
5219 int *lbp = (int *) obj;
5220 const char *name = bfd_get_section_name (abfd, sect);
5222 if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
5224 else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
5226 else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
5227 warning (_("unrecognized .gcc_compiled_longXX"));
5230 static enum mips_abi
5231 global_mips_abi (void)
5235 for (i = 0; mips_abi_strings[i] != NULL; i++)
5236 if (mips_abi_strings[i] == mips_abi_string)
5237 return (enum mips_abi) i;
5239 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
5243 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
5245 /* If the size matches the set of 32-bit or 64-bit integer registers,
5246 assume that's what we've got. */
5247 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
5248 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
5250 /* If the size matches the full set of registers GDB traditionally
5251 knows about, including floating point, for either 32-bit or
5252 64-bit, assume that's what we've got. */
5253 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
5254 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
5256 /* Otherwise we don't have a useful guess. */
5259 static struct value *
5260 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
5262 const int *reg_p = baton;
5263 return value_of_register (*reg_p, frame);
5266 static struct gdbarch *
5267 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5269 struct gdbarch *gdbarch;
5270 struct gdbarch_tdep *tdep;
5272 enum mips_abi mips_abi, found_abi, wanted_abi;
5274 enum mips_fpu_type fpu_type;
5275 struct tdesc_arch_data *tdesc_data = NULL;
5276 int elf_fpu_type = 0;
5278 /* Check any target description for validity. */
5279 if (tdesc_has_registers (info.target_desc))
5281 static const char *const mips_gprs[] = {
5282 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5283 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5284 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5285 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5287 static const char *const mips_fprs[] = {
5288 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5289 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5290 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5291 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5294 const struct tdesc_feature *feature;
5297 feature = tdesc_find_feature (info.target_desc,
5298 "org.gnu.gdb.mips.cpu");
5299 if (feature == NULL)
5302 tdesc_data = tdesc_data_alloc ();
5305 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
5306 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
5310 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5311 MIPS_EMBED_LO_REGNUM, "lo");
5312 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5313 MIPS_EMBED_HI_REGNUM, "hi");
5314 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5315 MIPS_EMBED_PC_REGNUM, "pc");
5319 tdesc_data_cleanup (tdesc_data);
5323 feature = tdesc_find_feature (info.target_desc,
5324 "org.gnu.gdb.mips.cp0");
5325 if (feature == NULL)
5327 tdesc_data_cleanup (tdesc_data);
5332 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5333 MIPS_EMBED_BADVADDR_REGNUM,
5335 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5336 MIPS_PS_REGNUM, "status");
5337 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5338 MIPS_EMBED_CAUSE_REGNUM, "cause");
5342 tdesc_data_cleanup (tdesc_data);
5346 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5347 backend is not prepared for that, though. */
5348 feature = tdesc_find_feature (info.target_desc,
5349 "org.gnu.gdb.mips.fpu");
5350 if (feature == NULL)
5352 tdesc_data_cleanup (tdesc_data);
5357 for (i = 0; i < 32; i++)
5358 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5359 i + MIPS_EMBED_FP0_REGNUM,
5362 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5363 MIPS_EMBED_FP0_REGNUM + 32, "fcsr");
5364 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5365 MIPS_EMBED_FP0_REGNUM + 33, "fir");
5369 tdesc_data_cleanup (tdesc_data);
5373 /* It would be nice to detect an attempt to use a 64-bit ABI
5374 when only 32-bit registers are provided. */
5377 /* First of all, extract the elf_flags, if available. */
5378 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5379 elf_flags = elf_elfheader (info.abfd)->e_flags;
5380 else if (arches != NULL)
5381 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5385 fprintf_unfiltered (gdb_stdlog,
5386 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5388 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5389 switch ((elf_flags & EF_MIPS_ABI))
5391 case E_MIPS_ABI_O32:
5392 found_abi = MIPS_ABI_O32;
5394 case E_MIPS_ABI_O64:
5395 found_abi = MIPS_ABI_O64;
5397 case E_MIPS_ABI_EABI32:
5398 found_abi = MIPS_ABI_EABI32;
5400 case E_MIPS_ABI_EABI64:
5401 found_abi = MIPS_ABI_EABI64;
5404 if ((elf_flags & EF_MIPS_ABI2))
5405 found_abi = MIPS_ABI_N32;
5407 found_abi = MIPS_ABI_UNKNOWN;
5411 /* GCC creates a pseudo-section whose name describes the ABI. */
5412 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5413 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5415 /* If we have no useful BFD information, use the ABI from the last
5416 MIPS architecture (if there is one). */
5417 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5418 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5420 /* Try the architecture for any hint of the correct ABI. */
5421 if (found_abi == MIPS_ABI_UNKNOWN
5422 && info.bfd_arch_info != NULL
5423 && info.bfd_arch_info->arch == bfd_arch_mips)
5425 switch (info.bfd_arch_info->mach)
5427 case bfd_mach_mips3900:
5428 found_abi = MIPS_ABI_EABI32;
5430 case bfd_mach_mips4100:
5431 case bfd_mach_mips5000:
5432 found_abi = MIPS_ABI_EABI64;
5434 case bfd_mach_mips8000:
5435 case bfd_mach_mips10000:
5436 /* On Irix, ELF64 executables use the N64 ABI. The
5437 pseudo-sections which describe the ABI aren't present
5438 on IRIX. (Even for executables created by gcc.) */
5439 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5440 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5441 found_abi = MIPS_ABI_N64;
5443 found_abi = MIPS_ABI_N32;
5448 /* Default 64-bit objects to N64 instead of O32. */
5449 if (found_abi == MIPS_ABI_UNKNOWN
5450 && info.abfd != NULL
5451 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5452 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5453 found_abi = MIPS_ABI_N64;
5456 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5459 /* What has the user specified from the command line? */
5460 wanted_abi = global_mips_abi ();
5462 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5465 /* Now that we have found what the ABI for this binary would be,
5466 check whether the user is overriding it. */
5467 if (wanted_abi != MIPS_ABI_UNKNOWN)
5468 mips_abi = wanted_abi;
5469 else if (found_abi != MIPS_ABI_UNKNOWN)
5470 mips_abi = found_abi;
5472 mips_abi = MIPS_ABI_O32;
5474 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5477 /* Also used when doing an architecture lookup. */
5479 fprintf_unfiltered (gdb_stdlog,
5480 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5481 mips64_transfers_32bit_regs_p);
5483 /* Determine the MIPS FPU type. */
5486 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5487 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5488 Tag_GNU_MIPS_ABI_FP);
5489 #endif /* HAVE_ELF */
5491 if (!mips_fpu_type_auto)
5492 fpu_type = mips_fpu_type;
5493 else if (elf_fpu_type != 0)
5495 switch (elf_fpu_type)
5498 fpu_type = MIPS_FPU_DOUBLE;
5501 fpu_type = MIPS_FPU_SINGLE;
5505 /* Soft float or unknown. */
5506 fpu_type = MIPS_FPU_NONE;
5510 else if (info.bfd_arch_info != NULL
5511 && info.bfd_arch_info->arch == bfd_arch_mips)
5512 switch (info.bfd_arch_info->mach)
5514 case bfd_mach_mips3900:
5515 case bfd_mach_mips4100:
5516 case bfd_mach_mips4111:
5517 case bfd_mach_mips4120:
5518 fpu_type = MIPS_FPU_NONE;
5520 case bfd_mach_mips4650:
5521 fpu_type = MIPS_FPU_SINGLE;
5524 fpu_type = MIPS_FPU_DOUBLE;
5527 else if (arches != NULL)
5528 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5530 fpu_type = MIPS_FPU_DOUBLE;
5532 fprintf_unfiltered (gdb_stdlog,
5533 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5535 /* Check for blatant incompatibilities. */
5537 /* If we have only 32-bit registers, then we can't debug a 64-bit
5539 if (info.target_desc
5540 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
5541 && mips_abi != MIPS_ABI_EABI32
5542 && mips_abi != MIPS_ABI_O32)
5544 if (tdesc_data != NULL)
5545 tdesc_data_cleanup (tdesc_data);
5549 /* try to find a pre-existing architecture */
5550 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5552 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5554 /* MIPS needs to be pedantic about which ABI the object is
5556 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5558 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5560 /* Need to be pedantic about which register virtual size is
5562 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5563 != mips64_transfers_32bit_regs_p)
5565 /* Be pedantic about which FPU is selected. */
5566 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5569 if (tdesc_data != NULL)
5570 tdesc_data_cleanup (tdesc_data);
5571 return arches->gdbarch;
5574 /* Need a new architecture. Fill in a target specific vector. */
5575 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5576 gdbarch = gdbarch_alloc (&info, tdep);
5577 tdep->elf_flags = elf_flags;
5578 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5579 tdep->found_abi = found_abi;
5580 tdep->mips_abi = mips_abi;
5581 tdep->mips_fpu_type = fpu_type;
5582 tdep->register_size_valid_p = 0;
5583 tdep->register_size = 0;
5585 if (info.target_desc)
5587 /* Some useful properties can be inferred from the target. */
5588 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
5590 tdep->register_size_valid_p = 1;
5591 tdep->register_size = 4;
5593 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
5595 tdep->register_size_valid_p = 1;
5596 tdep->register_size = 8;
5600 /* Initially set everything according to the default ABI/ISA. */
5601 set_gdbarch_short_bit (gdbarch, 16);
5602 set_gdbarch_int_bit (gdbarch, 32);
5603 set_gdbarch_float_bit (gdbarch, 32);
5604 set_gdbarch_double_bit (gdbarch, 64);
5605 set_gdbarch_long_double_bit (gdbarch, 64);
5606 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5607 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5608 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5610 set_gdbarch_elf_make_msymbol_special (gdbarch,
5611 mips_elf_make_msymbol_special);
5613 /* Fill in the OS dependant register numbers and names. */
5615 const char **reg_names;
5616 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
5617 struct mips_regnum);
5618 if (tdesc_has_registers (info.target_desc))
5620 regnum->lo = MIPS_EMBED_LO_REGNUM;
5621 regnum->hi = MIPS_EMBED_HI_REGNUM;
5622 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5623 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5624 regnum->pc = MIPS_EMBED_PC_REGNUM;
5625 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5626 regnum->fp_control_status = 70;
5627 regnum->fp_implementation_revision = 71;
5628 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
5631 else if (info.osabi == GDB_OSABI_IRIX)
5636 regnum->badvaddr = 66;
5639 regnum->fp_control_status = 69;
5640 regnum->fp_implementation_revision = 70;
5642 reg_names = mips_irix_reg_names;
5646 regnum->lo = MIPS_EMBED_LO_REGNUM;
5647 regnum->hi = MIPS_EMBED_HI_REGNUM;
5648 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5649 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5650 regnum->pc = MIPS_EMBED_PC_REGNUM;
5651 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5652 regnum->fp_control_status = 70;
5653 regnum->fp_implementation_revision = 71;
5655 if (info.bfd_arch_info != NULL
5656 && info.bfd_arch_info->mach == bfd_mach_mips3900)
5657 reg_names = mips_tx39_reg_names;
5659 reg_names = mips_generic_reg_names;
5661 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5662 replaced by read_pc? */
5663 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
5664 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
5665 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
5666 set_gdbarch_num_regs (gdbarch, num_regs);
5667 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5668 set_gdbarch_register_name (gdbarch, mips_register_name);
5669 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
5670 tdep->mips_processor_reg_names = reg_names;
5671 tdep->regnum = regnum;
5677 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5678 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
5679 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5680 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5681 tdep->default_mask_address_p = 0;
5682 set_gdbarch_long_bit (gdbarch, 32);
5683 set_gdbarch_ptr_bit (gdbarch, 32);
5684 set_gdbarch_long_long_bit (gdbarch, 64);
5687 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5688 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
5689 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5690 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5691 tdep->default_mask_address_p = 0;
5692 set_gdbarch_long_bit (gdbarch, 32);
5693 set_gdbarch_ptr_bit (gdbarch, 32);
5694 set_gdbarch_long_long_bit (gdbarch, 64);
5696 case MIPS_ABI_EABI32:
5697 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5698 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5699 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5700 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5701 tdep->default_mask_address_p = 0;
5702 set_gdbarch_long_bit (gdbarch, 32);
5703 set_gdbarch_ptr_bit (gdbarch, 32);
5704 set_gdbarch_long_long_bit (gdbarch, 64);
5706 case MIPS_ABI_EABI64:
5707 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5708 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5709 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5710 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5711 tdep->default_mask_address_p = 0;
5712 set_gdbarch_long_bit (gdbarch, 64);
5713 set_gdbarch_ptr_bit (gdbarch, 64);
5714 set_gdbarch_long_long_bit (gdbarch, 64);
5717 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5718 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5719 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5720 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5721 tdep->default_mask_address_p = 0;
5722 set_gdbarch_long_bit (gdbarch, 32);
5723 set_gdbarch_ptr_bit (gdbarch, 32);
5724 set_gdbarch_long_long_bit (gdbarch, 64);
5725 set_gdbarch_long_double_bit (gdbarch, 128);
5726 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
5729 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5730 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5731 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5732 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5733 tdep->default_mask_address_p = 0;
5734 set_gdbarch_long_bit (gdbarch, 64);
5735 set_gdbarch_ptr_bit (gdbarch, 64);
5736 set_gdbarch_long_long_bit (gdbarch, 64);
5737 set_gdbarch_long_double_bit (gdbarch, 128);
5738 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
5741 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5744 /* GCC creates a pseudo-section whose name specifies the size of
5745 longs, since -mlong32 or -mlong64 may be used independent of
5746 other options. How those options affect pointer sizes is ABI and
5747 architecture dependent, so use them to override the default sizes
5748 set by the ABI. This table shows the relationship between ABI,
5749 -mlongXX, and size of pointers:
5751 ABI -mlongXX ptr bits
5752 --- -------- --------
5766 Note that for o32 and eabi32, pointers are always 32 bits
5767 regardless of any -mlongXX option. For all others, pointers and
5768 longs are the same, as set by -mlongXX or set by defaults.
5771 if (info.abfd != NULL)
5775 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
5778 set_gdbarch_long_bit (gdbarch, long_bit);
5782 case MIPS_ABI_EABI32:
5787 case MIPS_ABI_EABI64:
5788 set_gdbarch_ptr_bit (gdbarch, long_bit);
5791 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5796 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5797 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5800 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5801 flag in object files because to do so would make it impossible to
5802 link with libraries compiled without "-gp32". This is
5803 unnecessarily restrictive.
5805 We could solve this problem by adding "-gp32" multilibs to gcc,
5806 but to set this flag before gcc is built with such multilibs will
5807 break too many systems.''
5809 But even more unhelpfully, the default linker output target for
5810 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5811 for 64-bit programs - you need to change the ABI to change this,
5812 and not all gcc targets support that currently. Therefore using
5813 this flag to detect 32-bit mode would do the wrong thing given
5814 the current gcc - it would make GDB treat these 64-bit programs
5815 as 32-bit programs by default. */
5817 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5818 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5820 /* Add/remove bits from an address. The MIPS needs be careful to
5821 ensure that all 32 bit addresses are sign extended to 64 bits. */
5822 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5824 /* Unwind the frame. */
5825 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5826 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
5827 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
5829 /* Map debug register numbers onto internal register numbers. */
5830 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5831 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5832 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5833 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5834 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5835 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5837 /* MIPS version of CALL_DUMMY */
5839 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5840 replaced by a command, and all targets will default to on stack
5841 (regardless of the stack's execute status). */
5842 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5843 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5845 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
5846 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
5847 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
5849 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5850 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5852 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5854 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
5856 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5857 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5858 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5860 set_gdbarch_register_type (gdbarch, mips_register_type);
5862 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5864 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
5866 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5867 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5868 need to all be folded into the target vector. Since they are
5869 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5870 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5872 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
5874 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
5876 set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay);
5878 /* Virtual tables. */
5879 set_gdbarch_vbit_in_delta (gdbarch, 1);
5881 mips_register_g_packet_guesses (gdbarch);
5883 /* Hook in OS ABI-specific overrides, if they have been registered. */
5884 info.tdep_info = (void *) tdesc_data;
5885 gdbarch_init_osabi (info, gdbarch);
5887 /* Unwind the frame. */
5888 dwarf2_append_unwinders (gdbarch);
5889 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
5890 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
5891 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
5892 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
5893 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
5894 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
5895 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
5899 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
5900 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
5902 /* Override the normal target description methods to handle our
5903 dual real and pseudo registers. */
5904 set_gdbarch_register_name (gdbarch, mips_register_name);
5905 set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p);
5907 num_regs = gdbarch_num_regs (gdbarch);
5908 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5909 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
5910 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
5913 /* Add ABI-specific aliases for the registers. */
5914 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
5915 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
5916 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
5917 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
5919 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
5920 user_reg_add (gdbarch, mips_o32_aliases[i].name,
5921 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
5923 /* Add some other standard aliases. */
5924 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
5925 user_reg_add (gdbarch, mips_register_aliases[i].name,
5926 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
5932 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
5934 struct gdbarch_info info;
5936 /* Force the architecture to update, and (if it's a MIPS architecture)
5937 mips_gdbarch_init will take care of the rest. */
5938 gdbarch_info_init (&info);
5939 gdbarch_update_p (info);
5942 /* Print out which MIPS ABI is in use. */
5945 show_mips_abi (struct ui_file *file,
5947 struct cmd_list_element *ignored_cmd,
5948 const char *ignored_value)
5950 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
5953 "The MIPS ABI is unknown because the current architecture "
5957 enum mips_abi global_abi = global_mips_abi ();
5958 enum mips_abi actual_abi = mips_abi (current_gdbarch);
5959 const char *actual_abi_str = mips_abi_strings[actual_abi];
5961 if (global_abi == MIPS_ABI_UNKNOWN)
5964 "The MIPS ABI is set automatically (currently \"%s\").\n",
5966 else if (global_abi == actual_abi)
5969 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5973 /* Probably shouldn't happen... */
5976 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5977 actual_abi_str, mips_abi_strings[global_abi]);
5983 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
5985 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5989 int ef_mips_32bitmode;
5990 /* Determine the ISA. */
5991 switch (tdep->elf_flags & EF_MIPS_ARCH)
6009 /* Determine the size of a pointer. */
6010 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6011 fprintf_unfiltered (file,
6012 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6014 fprintf_unfiltered (file,
6015 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6017 fprintf_unfiltered (file,
6018 "mips_dump_tdep: ef_mips_arch = %d\n",
6020 fprintf_unfiltered (file,
6021 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6022 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
6023 fprintf_unfiltered (file,
6024 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6025 mips_mask_address_p (tdep),
6026 tdep->default_mask_address_p);
6028 fprintf_unfiltered (file,
6029 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6030 MIPS_DEFAULT_FPU_TYPE,
6031 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6032 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6033 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6035 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI);
6036 fprintf_unfiltered (file,
6037 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6039 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
6040 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6041 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6045 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6048 _initialize_mips_tdep (void)
6050 static struct cmd_list_element *mipsfpulist = NULL;
6051 struct cmd_list_element *c;
6053 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
6054 if (MIPS_ABI_LAST + 1
6055 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6056 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
6058 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6060 mips_pdr_data = register_objfile_data ();
6062 /* Create feature sets with the appropriate properties. The values
6063 are not important. */
6064 mips_tdesc_gp32 = allocate_target_description ();
6065 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
6067 mips_tdesc_gp64 = allocate_target_description ();
6068 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
6070 /* Add root prefix command for all "set mips"/"show mips" commands */
6071 add_prefix_cmd ("mips", no_class, set_mips_command,
6072 _("Various MIPS specific commands."),
6073 &setmipscmdlist, "set mips ", 0, &setlist);
6075 add_prefix_cmd ("mips", no_class, show_mips_command,
6076 _("Various MIPS specific commands."),
6077 &showmipscmdlist, "show mips ", 0, &showlist);
6079 /* Allow the user to override the ABI. */
6080 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
6081 &mips_abi_string, _("\
6082 Set the MIPS ABI used by this program."), _("\
6083 Show the MIPS ABI used by this program."), _("\
6084 This option can be set to one of:\n\
6085 auto - the default ABI associated with the current binary\n\
6094 &setmipscmdlist, &showmipscmdlist);
6096 /* Let the user turn off floating point and set the fence post for
6097 heuristic_proc_start. */
6099 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6100 _("Set use of MIPS floating-point coprocessor."),
6101 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6102 add_cmd ("single", class_support, set_mipsfpu_single_command,
6103 _("Select single-precision MIPS floating-point coprocessor."),
6105 add_cmd ("double", class_support, set_mipsfpu_double_command,
6106 _("Select double-precision MIPS floating-point coprocessor."),
6108 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6109 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6110 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6111 add_cmd ("none", class_support, set_mipsfpu_none_command,
6112 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
6113 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6114 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6115 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6116 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6117 _("Select MIPS floating-point coprocessor automatically."),
6119 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6120 _("Show current use of MIPS floating-point coprocessor target."),
6123 /* We really would like to have both "0" and "unlimited" work, but
6124 command.c doesn't deal with that. So make it a var_zinteger
6125 because the user can always use "999999" or some such for unlimited. */
6126 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
6127 &heuristic_fence_post, _("\
6128 Set the distance searched for the start of a function."), _("\
6129 Show the distance searched for the start of a function."), _("\
6130 If you are debugging a stripped executable, GDB needs to search through the\n\
6131 program for the start of a function. This command sets the distance of the\n\
6132 search. The only need to set it is when debugging a stripped executable."),
6133 reinit_frame_cache_sfunc,
6134 NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6135 &setlist, &showlist);
6137 /* Allow the user to control whether the upper bits of 64-bit
6138 addresses should be zeroed. */
6139 add_setshow_auto_boolean_cmd ("mask-address", no_class,
6140 &mask_address_var, _("\
6141 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6142 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6143 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6144 allow GDB to determine the correct value."),
6145 NULL, show_mask_address,
6146 &setmipscmdlist, &showmipscmdlist);
6148 /* Allow the user to control the size of 32 bit registers within the
6149 raw remote packet. */
6150 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6151 &mips64_transfers_32bit_regs_p, _("\
6152 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6154 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6156 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6157 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6158 64 bits for others. Use \"off\" to disable compatibility mode"),
6159 set_mips64_transfers_32bit_regs,
6160 NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6161 &setlist, &showlist);
6163 /* Debug this files internals. */
6164 add_setshow_zinteger_cmd ("mips", class_maintenance,
6166 Set mips debugging."), _("\
6167 Show mips debugging."), _("\
6168 When non-zero, mips specific debugging is enabled."),
6170 NULL, /* FIXME: i18n: Mips debugging is currently %s. */
6171 &setdebuglist, &showdebuglist);