1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "opcode/mips.h"
49 /* A useful bit in the CP0 status register (PS_REGNUM). */
50 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
51 #define ST0_FR (1 << 26)
53 /* The sizes of floating point registers. */
57 MIPS_FPU_SINGLE_REGSIZE = 4,
58 MIPS_FPU_DOUBLE_REGSIZE = 8
62 static const char *mips_abi_string;
64 static const char *mips_abi_strings[] = {
75 struct frame_extra_info
77 mips_extra_func_info_t proc_desc;
81 /* Various MIPS ISA options (related to stack analysis) can be
82 overridden dynamically. Establish an enum/array for managing
85 static const char size_auto[] = "auto";
86 static const char size_32[] = "32";
87 static const char size_64[] = "64";
89 static const char *size_enums[] = {
96 /* Some MIPS boards don't support floating point while others only
97 support single-precision floating-point operations. See also
98 FP_REGISTER_DOUBLE. */
102 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
103 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
104 MIPS_FPU_NONE /* No floating point. */
107 #ifndef MIPS_DEFAULT_FPU_TYPE
108 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
110 static int mips_fpu_type_auto = 1;
111 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
113 static int mips_debug = 0;
115 /* MIPS specific per-architecture information */
118 /* from the elf header */
122 enum mips_abi mips_abi;
123 enum mips_abi found_abi;
124 enum mips_fpu_type mips_fpu_type;
125 int mips_last_arg_regnum;
126 int mips_last_fp_arg_regnum;
127 int mips_default_saved_regsize;
128 int mips_fp_register_double;
129 int mips_default_stack_argsize;
130 int gdb_target_is_mips64;
131 int default_mask_address_p;
134 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
135 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
137 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
139 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
141 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
143 /* Return the currently configured (or set) saved register size. */
145 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
147 static const char *mips_saved_regsize_string = size_auto;
149 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
151 /* Return the MIPS ABI associated with GDBARCH. */
153 mips_abi (struct gdbarch *gdbarch)
155 return gdbarch_tdep (gdbarch)->mips_abi;
159 mips_saved_regsize (void)
161 if (mips_saved_regsize_string == size_auto)
162 return MIPS_DEFAULT_SAVED_REGSIZE;
163 else if (mips_saved_regsize_string == size_64)
165 else /* if (mips_saved_regsize_string == size_32) */
169 /* Functions for setting and testing a bit in a minimal symbol that
170 marks it as 16-bit function. The MSB of the minimal symbol's
171 "info" field is used for this purpose. This field is already
172 being used to store the symbol size, so the assumption is
173 that the symbol size cannot exceed 2^31.
175 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
176 i.e. refers to a 16-bit function, and sets a "special" bit in a
177 minimal symbol to mark it as a 16-bit function
179 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
180 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
181 the "info" field with the "special" bit masked out */
184 mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
186 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16)
188 MSYMBOL_INFO (msym) = (char *)
189 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
190 SYMBOL_VALUE_ADDRESS (msym) |= 1;
195 msymbol_is_special (struct minimal_symbol *msym)
197 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
201 msymbol_size (struct minimal_symbol *msym)
203 return ((long) MSYMBOL_INFO (msym) & 0x7fffffff);
206 /* XFER a value from the big/little/left end of the register.
207 Depending on the size of the value it might occupy the entire
208 register or just part of it. Make an allowance for this, aligning
209 things accordingly. */
212 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
213 enum bfd_endian endian, bfd_byte *in, const bfd_byte *out,
216 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
218 /* Need to transfer the left or right part of the register, based on
219 the targets byte order. */
223 reg_offset = REGISTER_RAW_SIZE (reg_num) - length;
225 case BFD_ENDIAN_LITTLE:
228 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
232 internal_error (__FILE__, __LINE__, "bad switch");
235 fprintf_unfiltered (gdb_stderr,
236 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
237 reg_num, reg_offset, buf_offset, length);
238 if (mips_debug && out != NULL)
241 fprintf_unfiltered (gdb_stdlog, "out ");
242 for (i = 0; i < length; i++)
243 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
246 regcache_raw_read_part (regcache, reg_num, reg_offset, length, in + buf_offset);
248 regcache_raw_write_part (regcache, reg_num, reg_offset, length, out + buf_offset);
249 if (mips_debug && in != NULL)
252 fprintf_unfiltered (gdb_stdlog, "in ");
253 for (i = 0; i < length; i++)
254 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
257 fprintf_unfiltered (gdb_stdlog, "\n");
260 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
261 compatiblity mode. A return value of 1 means that we have
262 physical 64-bit registers, but should treat them as 32-bit registers. */
265 mips2_fp_compat (void)
267 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
269 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
273 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
274 in all the places we deal with FP registers. PR gdb/413. */
275 /* Otherwise check the FR bit in the status register - it controls
276 the FP compatiblity mode. If it is clear we are in compatibility
278 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
285 /* Indicate that the ABI makes use of double-precision registers
286 provided by the FPU (rather than combining pairs of registers to
287 form double-precision values). Do not use "TARGET_IS_MIPS64" to
288 determine if the ABI is using double-precision registers. See also
290 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
292 /* The amount of space reserved on the stack for registers. This is
293 different to MIPS_SAVED_REGSIZE as it determines the alignment of
294 data allocated after the registers have run out. */
296 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
298 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
300 static const char *mips_stack_argsize_string = size_auto;
303 mips_stack_argsize (void)
305 if (mips_stack_argsize_string == size_auto)
306 return MIPS_DEFAULT_STACK_ARGSIZE;
307 else if (mips_stack_argsize_string == size_64)
309 else /* if (mips_stack_argsize_string == size_32) */
313 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
315 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
317 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
319 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
321 static void mips_print_register (int, int);
323 static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR,
324 struct frame_info *, int);
326 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
328 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
330 static int mips_set_processor_type (char *);
332 static void mips_show_processor_type_command (char *, int);
334 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
336 static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc,
337 struct frame_info *next_frame,
340 static CORE_ADDR after_prologue (CORE_ADDR pc,
341 mips_extra_func_info_t proc_desc);
343 static void mips_read_fp_register_single (int regno, char *rare_buffer);
344 static void mips_read_fp_register_double (int regno, char *rare_buffer);
346 static struct type *mips_float_register_type (void);
347 static struct type *mips_double_register_type (void);
349 /* This value is the model of MIPS in use. It is derived from the value
350 of the PrID register. */
352 char *mips_processor_type;
354 char *tmp_mips_processor_type;
356 /* The list of available "set mips " and "show mips " commands */
358 static struct cmd_list_element *setmipscmdlist = NULL;
359 static struct cmd_list_element *showmipscmdlist = NULL;
361 /* A set of original names, to be used when restoring back to generic
362 registers from a specific set. */
364 char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
365 char **mips_processor_reg_names = mips_generic_reg_names;
368 mips_register_name (int i)
370 return mips_processor_reg_names[i];
373 /* Names of IDT R3041 registers. */
375 char *mips_r3041_reg_names[] = {
376 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
377 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
378 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
379 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
380 "sr", "lo", "hi", "bad", "cause","pc",
381 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
382 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
383 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
384 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
385 "fsr", "fir", "",/*"fp"*/ "",
386 "", "", "bus", "ccfg", "", "", "", "",
387 "", "", "port", "cmp", "", "", "epc", "prid",
390 /* Names of IDT R3051 registers. */
392 char *mips_r3051_reg_names[] = {
393 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
394 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
395 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
396 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
397 "sr", "lo", "hi", "bad", "cause","pc",
398 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
399 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
400 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
401 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
402 "fsr", "fir", ""/*"fp"*/, "",
403 "inx", "rand", "elo", "", "ctxt", "", "", "",
404 "", "", "ehi", "", "", "", "epc", "prid",
407 /* Names of IDT R3081 registers. */
409 char *mips_r3081_reg_names[] = {
410 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
411 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
412 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
413 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
414 "sr", "lo", "hi", "bad", "cause","pc",
415 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
416 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
417 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
418 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
419 "fsr", "fir", ""/*"fp"*/, "",
420 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
421 "", "", "ehi", "", "", "", "epc", "prid",
424 /* Names of LSI 33k registers. */
426 char *mips_lsi33k_reg_names[] = {
427 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
428 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
429 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
430 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
431 "epc", "hi", "lo", "sr", "cause","badvaddr",
432 "dcic", "bpc", "bda", "", "", "", "", "",
433 "", "", "", "", "", "", "", "",
434 "", "", "", "", "", "", "", "",
435 "", "", "", "", "", "", "", "",
437 "", "", "", "", "", "", "", "",
438 "", "", "", "", "", "", "", "",
444 } mips_processor_type_table[] = {
445 { "generic", mips_generic_reg_names },
446 { "r3041", mips_r3041_reg_names },
447 { "r3051", mips_r3051_reg_names },
448 { "r3071", mips_r3081_reg_names },
449 { "r3081", mips_r3081_reg_names },
450 { "lsi33k", mips_lsi33k_reg_names },
458 /* Table to translate MIPS16 register field to actual register number. */
459 static int mips16_to_32_reg[8] =
460 {16, 17, 2, 3, 4, 5, 6, 7};
462 /* Heuristic_proc_start may hunt through the text section for a long
463 time across a 2400 baud serial line. Allows the user to limit this
466 static unsigned int heuristic_fence_post = 0;
468 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
469 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
470 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
471 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
472 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
473 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
474 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
475 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
476 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
477 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
478 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
479 this will corrupt pdr.iline. Fortunately we don't use it. */
480 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
481 #define _PROC_MAGIC_ 0x0F0F0F0F
482 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
483 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
485 struct linked_proc_info
487 struct mips_extra_func_info info;
488 struct linked_proc_info *next;
490 *linked_proc_desc_table = NULL;
493 mips_print_extra_frame_info (struct frame_info *fi)
496 && get_frame_extra_info (fi)
497 && get_frame_extra_info (fi)->proc_desc
498 && get_frame_extra_info (fi)->proc_desc->pdr.framereg < NUM_REGS)
499 printf_filtered (" frame pointer is at %s+%s\n",
500 REGISTER_NAME (get_frame_extra_info (fi)->proc_desc->pdr.framereg),
501 paddr_d (get_frame_extra_info (fi)->proc_desc->pdr.frameoffset));
504 /* Number of bytes of storage in the actual machine representation for
505 register N. NOTE: This indirectly defines the register size
506 transfered by the GDB protocol. */
508 static int mips64_transfers_32bit_regs_p = 0;
511 mips_register_raw_size (int reg_nr)
513 if (mips64_transfers_32bit_regs_p)
514 return REGISTER_VIRTUAL_SIZE (reg_nr);
515 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
516 && FP_REGISTER_DOUBLE)
517 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
524 /* Convert between RAW and VIRTUAL registers. The RAW register size
525 defines the remote-gdb packet. */
528 mips_register_convertible (int reg_nr)
530 if (mips64_transfers_32bit_regs_p)
533 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
537 mips_register_convert_to_virtual (int n, struct type *virtual_type,
538 char *raw_buf, char *virt_buf)
540 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
542 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
543 TYPE_LENGTH (virtual_type));
547 TYPE_LENGTH (virtual_type));
551 mips_register_convert_to_raw (struct type *virtual_type, int n,
552 char *virt_buf, char *raw_buf)
554 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
555 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
556 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
558 TYPE_LENGTH (virtual_type));
562 TYPE_LENGTH (virtual_type));
566 mips_register_convert_to_type (int regnum, struct type *type, char *buffer)
568 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
569 && REGISTER_RAW_SIZE (regnum) == 4
570 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
571 && TYPE_CODE(type) == TYPE_CODE_FLT
572 && TYPE_LENGTH(type) == 8)
575 memcpy (temp, ((char *)(buffer))+4, 4);
576 memcpy (((char *)(buffer))+4, (buffer), 4);
577 memcpy (((char *)(buffer)), temp, 4);
582 mips_register_convert_from_type (int regnum, struct type *type, char *buffer)
584 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
585 && REGISTER_RAW_SIZE (regnum) == 4
586 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
587 && TYPE_CODE(type) == TYPE_CODE_FLT
588 && TYPE_LENGTH(type) == 8)
591 memcpy (temp, ((char *)(buffer))+4, 4);
592 memcpy (((char *)(buffer))+4, (buffer), 4);
593 memcpy (((char *)(buffer)), temp, 4);
597 /* Return the GDB type object for the "standard" data type
598 of data in register REG.
600 Note: kevinb/2002-08-01: The definition below should faithfully
601 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
602 definitions found in config/mips/tm-*.h. I'm concerned about
603 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
604 though. In some cases FP_REGNUM is in this range, and I doubt
605 that this code is correct for the 64-bit case. */
608 mips_register_virtual_type (int reg)
610 if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32)
612 /* Floating point registers... */
613 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
614 return builtin_type_ieee_double_big;
616 return builtin_type_ieee_double_little;
618 else if (reg == PS_REGNUM /* CR */)
619 return builtin_type_uint32;
620 else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM)
621 return builtin_type_uint32;
624 /* Everything else...
625 Return type appropriate for width of register. */
626 if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64))
627 return builtin_type_uint64;
629 return builtin_type_uint32;
633 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
638 return ADDR_BITS_REMOVE (read_register (SP_REGNUM));
641 /* Should the upper word of 64-bit addresses be zeroed? */
642 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
645 mips_mask_address_p (void)
647 switch (mask_address_var)
649 case AUTO_BOOLEAN_TRUE:
651 case AUTO_BOOLEAN_FALSE:
654 case AUTO_BOOLEAN_AUTO:
655 return MIPS_DEFAULT_MASK_ADDRESS_P;
657 internal_error (__FILE__, __LINE__,
658 "mips_mask_address_p: bad switch");
664 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
666 switch (mask_address_var)
668 case AUTO_BOOLEAN_TRUE:
669 printf_filtered ("The 32 bit mips address mask is enabled\n");
671 case AUTO_BOOLEAN_FALSE:
672 printf_filtered ("The 32 bit mips address mask is disabled\n");
674 case AUTO_BOOLEAN_AUTO:
675 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
676 mips_mask_address_p () ? "enabled" : "disabled");
679 internal_error (__FILE__, __LINE__,
680 "show_mask_address: bad switch");
685 /* Should call_function allocate stack space for a struct return? */
688 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
690 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
694 mips_n32n64_use_struct_convention (int gcc_p, struct type *type)
696 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
700 mips_o32_use_struct_convention (int gcc_p, struct type *type)
702 return 1; /* Structures are returned by ref in extra arg0. */
705 /* Should call_function pass struct by reference?
706 For each architecture, structs are passed either by
707 value or by reference, depending on their size. */
710 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
712 enum type_code typecode = TYPE_CODE (check_typedef (type));
713 int len = TYPE_LENGTH (check_typedef (type));
715 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
716 return (len > MIPS_SAVED_REGSIZE);
722 mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type)
724 return 0; /* Assumption: N32/N64 never passes struct by ref. */
728 mips_o32_reg_struct_has_addr (int gcc_p, struct type *type)
730 return 0; /* Assumption: O32/O64 never passes struct by ref. */
733 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
736 pc_is_mips16 (bfd_vma memaddr)
738 struct minimal_symbol *sym;
740 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
741 if (IS_MIPS16_ADDR (memaddr))
744 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
745 the high bit of the info field. Use this to decide if the function is
746 MIPS16 or normal MIPS. */
747 sym = lookup_minimal_symbol_by_pc (memaddr);
749 return msymbol_is_special (sym);
754 /* MIPS believes that the PC has a sign extended value. Perhaphs the
755 all registers should be sign extended for simplicity? */
758 mips_read_pc (ptid_t ptid)
760 return read_signed_register_pid (PC_REGNUM, ptid);
763 /* This returns the PC of the first inst after the prologue. If we can't
764 find the prologue, then return 0. */
767 after_prologue (CORE_ADDR pc,
768 mips_extra_func_info_t proc_desc)
770 struct symtab_and_line sal;
771 CORE_ADDR func_addr, func_end;
773 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
774 to read the stack pointer from the current machine state, because
775 the current machine state has nothing to do with the information
776 we need from the proc_desc; and the process may or may not exist
779 proc_desc = find_proc_desc (pc, NULL, 0);
783 /* If function is frameless, then we need to do it the hard way. I
784 strongly suspect that frameless always means prologueless... */
785 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
786 && PROC_FRAME_OFFSET (proc_desc) == 0)
790 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
791 return 0; /* Unknown */
793 sal = find_pc_line (func_addr, 0);
795 if (sal.end < func_end)
798 /* The line after the prologue is after the end of the function. In this
799 case, tell the caller to find the prologue the hard way. */
804 /* Decode a MIPS32 instruction that saves a register in the stack, and
805 set the appropriate bit in the general register mask or float register mask
806 to indicate which register is saved. This is a helper function
807 for mips_find_saved_regs. */
810 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
811 unsigned long *float_mask)
815 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
816 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
817 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
819 /* It might be possible to use the instruction to
820 find the offset, rather than the code below which
821 is based on things being in a certain order in the
822 frame, but figuring out what the instruction's offset
823 is relative to might be a little tricky. */
824 reg = (inst & 0x001f0000) >> 16;
825 *gen_mask |= (1 << reg);
827 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
828 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
829 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
832 reg = ((inst & 0x001f0000) >> 16);
833 *float_mask |= (1 << reg);
837 /* Decode a MIPS16 instruction that saves a register in the stack, and
838 set the appropriate bit in the general register or float register mask
839 to indicate which register is saved. This is a helper function
840 for mips_find_saved_regs. */
843 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
845 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
847 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
848 *gen_mask |= (1 << reg);
850 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
852 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
853 *gen_mask |= (1 << reg);
855 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
856 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
857 *gen_mask |= (1 << RA_REGNUM);
861 /* Fetch and return instruction from the specified location. If the PC
862 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
865 mips_fetch_instruction (CORE_ADDR addr)
867 char buf[MIPS_INSTLEN];
871 if (pc_is_mips16 (addr))
873 instlen = MIPS16_INSTLEN;
874 addr = UNMAKE_MIPS16_ADDR (addr);
877 instlen = MIPS_INSTLEN;
878 status = read_memory_nobpt (addr, buf, instlen);
880 memory_error (status, addr);
881 return extract_unsigned_integer (buf, instlen);
885 /* These the fields of 32 bit mips instructions */
886 #define mips32_op(x) (x >> 26)
887 #define itype_op(x) (x >> 26)
888 #define itype_rs(x) ((x >> 21) & 0x1f)
889 #define itype_rt(x) ((x >> 16) & 0x1f)
890 #define itype_immediate(x) (x & 0xffff)
892 #define jtype_op(x) (x >> 26)
893 #define jtype_target(x) (x & 0x03ffffff)
895 #define rtype_op(x) (x >> 26)
896 #define rtype_rs(x) ((x >> 21) & 0x1f)
897 #define rtype_rt(x) ((x >> 16) & 0x1f)
898 #define rtype_rd(x) ((x >> 11) & 0x1f)
899 #define rtype_shamt(x) ((x >> 6) & 0x1f)
900 #define rtype_funct(x) (x & 0x3f)
903 mips32_relative_offset (unsigned long inst)
906 x = itype_immediate (inst);
907 if (x & 0x8000) /* sign bit set */
909 x |= 0xffff0000; /* sign extension */
915 /* Determine whate to set a single step breakpoint while considering
918 mips32_next_pc (CORE_ADDR pc)
922 inst = mips_fetch_instruction (pc);
923 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
925 if (itype_op (inst) >> 2 == 5)
926 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
928 op = (itype_op (inst) & 0x03);
943 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
944 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
946 int tf = itype_rt (inst) & 0x01;
947 int cnum = itype_rt (inst) >> 2;
948 int fcrcs = read_signed_register (FCRCS_REGNUM);
949 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
951 if (((cond >> cnum) & 0x01) == tf)
952 pc += mips32_relative_offset (inst) + 4;
957 pc += 4; /* Not a branch, next instruction is easy */
960 { /* This gets way messy */
962 /* Further subdivide into SPECIAL, REGIMM and other */
963 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
965 case 0: /* SPECIAL */
966 op = rtype_funct (inst);
971 /* Set PC to that address */
972 pc = read_signed_register (rtype_rs (inst));
978 break; /* end SPECIAL */
981 op = itype_rt (inst); /* branch condition */
986 case 16: /* BLTZAL */
987 case 18: /* BLTZALL */
989 if (read_signed_register (itype_rs (inst)) < 0)
990 pc += mips32_relative_offset (inst) + 4;
992 pc += 8; /* after the delay slot */
996 case 17: /* BGEZAL */
997 case 19: /* BGEZALL */
998 greater_equal_branch:
999 if (read_signed_register (itype_rs (inst)) >= 0)
1000 pc += mips32_relative_offset (inst) + 4;
1002 pc += 8; /* after the delay slot */
1004 /* All of the other instructions in the REGIMM category */
1009 break; /* end REGIMM */
1014 reg = jtype_target (inst) << 2;
1015 /* Upper four bits get never changed... */
1016 pc = reg + ((pc + 4) & 0xf0000000);
1019 /* FIXME case JALX : */
1022 reg = jtype_target (inst) << 2;
1023 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
1024 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1026 break; /* The new PC will be alternate mode */
1027 case 4: /* BEQ, BEQL */
1029 if (read_signed_register (itype_rs (inst)) ==
1030 read_signed_register (itype_rt (inst)))
1031 pc += mips32_relative_offset (inst) + 4;
1035 case 5: /* BNE, BNEL */
1037 if (read_signed_register (itype_rs (inst)) !=
1038 read_signed_register (itype_rt (inst)))
1039 pc += mips32_relative_offset (inst) + 4;
1043 case 6: /* BLEZ, BLEZL */
1045 if (read_signed_register (itype_rs (inst) <= 0))
1046 pc += mips32_relative_offset (inst) + 4;
1052 greater_branch: /* BGTZ, BGTZL */
1053 if (read_signed_register (itype_rs (inst) > 0))
1054 pc += mips32_relative_offset (inst) + 4;
1061 } /* mips32_next_pc */
1063 /* Decoding the next place to set a breakpoint is irregular for the
1064 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1065 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1066 We dont want to set a single step instruction on the extend instruction
1070 /* Lots of mips16 instruction formats */
1071 /* Predicting jumps requires itype,ritype,i8type
1072 and their extensions extItype,extritype,extI8type
1074 enum mips16_inst_fmts
1076 itype, /* 0 immediate 5,10 */
1077 ritype, /* 1 5,3,8 */
1078 rrtype, /* 2 5,3,3,5 */
1079 rritype, /* 3 5,3,3,5 */
1080 rrrtype, /* 4 5,3,3,3,2 */
1081 rriatype, /* 5 5,3,3,1,4 */
1082 shifttype, /* 6 5,3,3,3,2 */
1083 i8type, /* 7 5,3,8 */
1084 i8movtype, /* 8 5,3,3,5 */
1085 i8mov32rtype, /* 9 5,3,5,3 */
1086 i64type, /* 10 5,3,8 */
1087 ri64type, /* 11 5,3,3,5 */
1088 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1089 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1090 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1091 extRRItype, /* 15 5,5,5,5,3,3,5 */
1092 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1093 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1094 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1095 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1096 extRi64type, /* 20 5,6,5,5,3,3,5 */
1097 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1099 /* I am heaping all the fields of the formats into one structure and
1100 then, only the fields which are involved in instruction extension */
1104 unsigned int regx; /* Function in i8 type */
1109 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1110 for the bits which make up the immediatate extension. */
1113 extended_offset (unsigned int extension)
1116 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1118 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1120 value |= extension & 0x01f; /* extract 4:0 */
1124 /* Only call this function if you know that this is an extendable
1125 instruction, It wont malfunction, but why make excess remote memory references?
1126 If the immediate operands get sign extended or somthing, do it after
1127 the extension is performed.
1129 /* FIXME: Every one of these cases needs to worry about sign extension
1130 when the offset is to be used in relative addressing */
1134 fetch_mips_16 (CORE_ADDR pc)
1137 pc &= 0xfffffffe; /* clear the low order bit */
1138 target_read_memory (pc, buf, 2);
1139 return extract_unsigned_integer (buf, 2);
1143 unpack_mips16 (CORE_ADDR pc,
1144 unsigned int extension,
1146 enum mips16_inst_fmts insn_format,
1147 struct upk_mips16 *upk)
1152 switch (insn_format)
1159 value = extended_offset (extension);
1160 value = value << 11; /* rom for the original value */
1161 value |= inst & 0x7ff; /* eleven bits from instruction */
1165 value = inst & 0x7ff;
1166 /* FIXME : Consider sign extension */
1175 { /* A register identifier and an offset */
1176 /* Most of the fields are the same as I type but the
1177 immediate value is of a different length */
1181 value = extended_offset (extension);
1182 value = value << 8; /* from the original instruction */
1183 value |= inst & 0xff; /* eleven bits from instruction */
1184 regx = (extension >> 8) & 0x07; /* or i8 funct */
1185 if (value & 0x4000) /* test the sign bit , bit 26 */
1187 value &= ~0x3fff; /* remove the sign bit */
1193 value = inst & 0xff; /* 8 bits */
1194 regx = (inst >> 8) & 0x07; /* or i8 funct */
1195 /* FIXME: Do sign extension , this format needs it */
1196 if (value & 0x80) /* THIS CONFUSES ME */
1198 value &= 0xef; /* remove the sign bit */
1208 unsigned long value;
1209 unsigned int nexthalf;
1210 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1211 value = value << 16;
1212 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1220 internal_error (__FILE__, __LINE__,
1223 upk->offset = offset;
1230 add_offset_16 (CORE_ADDR pc, int offset)
1232 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1236 extended_mips16_next_pc (CORE_ADDR pc,
1237 unsigned int extension,
1240 int op = (insn >> 11);
1243 case 2: /* Branch */
1246 struct upk_mips16 upk;
1247 unpack_mips16 (pc, extension, insn, itype, &upk);
1248 offset = upk.offset;
1254 pc += (offset << 1) + 2;
1257 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1259 struct upk_mips16 upk;
1260 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1261 pc = add_offset_16 (pc, upk.offset);
1262 if ((insn >> 10) & 0x01) /* Exchange mode */
1263 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1270 struct upk_mips16 upk;
1272 unpack_mips16 (pc, extension, insn, ritype, &upk);
1273 reg = read_signed_register (upk.regx);
1275 pc += (upk.offset << 1) + 2;
1282 struct upk_mips16 upk;
1284 unpack_mips16 (pc, extension, insn, ritype, &upk);
1285 reg = read_signed_register (upk.regx);
1287 pc += (upk.offset << 1) + 2;
1292 case 12: /* I8 Formats btez btnez */
1294 struct upk_mips16 upk;
1296 unpack_mips16 (pc, extension, insn, i8type, &upk);
1297 /* upk.regx contains the opcode */
1298 reg = read_signed_register (24); /* Test register is 24 */
1299 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1300 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1301 /* pc = add_offset_16(pc,upk.offset) ; */
1302 pc += (upk.offset << 1) + 2;
1307 case 29: /* RR Formats JR, JALR, JALR-RA */
1309 struct upk_mips16 upk;
1310 /* upk.fmt = rrtype; */
1315 upk.regx = (insn >> 8) & 0x07;
1316 upk.regy = (insn >> 5) & 0x07;
1324 break; /* Function return instruction */
1330 break; /* BOGUS Guess */
1332 pc = read_signed_register (reg);
1339 /* This is an instruction extension. Fetch the real instruction
1340 (which follows the extension) and decode things based on
1344 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1357 mips16_next_pc (CORE_ADDR pc)
1359 unsigned int insn = fetch_mips_16 (pc);
1360 return extended_mips16_next_pc (pc, 0, insn);
1363 /* The mips_next_pc function supports single_step when the remote
1364 target monitor or stub is not developed enough to do a single_step.
1365 It works by decoding the current instruction and predicting where a
1366 branch will go. This isnt hard because all the data is available.
1367 The MIPS32 and MIPS16 variants are quite different */
1369 mips_next_pc (CORE_ADDR pc)
1372 return mips16_next_pc (pc);
1374 return mips32_next_pc (pc);
1377 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1380 Note: kevinb/2002-08-09: The only caller of this function is (and
1381 should remain) mips_frame_init_saved_regs(). In fact,
1382 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1383 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1384 functions should really be combined and now that there is only one
1385 caller, it should be straightforward. (Watch out for multiple returns
1389 mips_find_saved_regs (struct frame_info *fci)
1392 CORE_ADDR reg_position;
1393 /* r0 bit means kernel trap */
1395 /* What registers have been saved? Bitmasks. */
1396 unsigned long gen_mask, float_mask;
1397 mips_extra_func_info_t proc_desc;
1400 frame_saved_regs_zalloc (fci);
1402 /* If it is the frame for sigtramp, the saved registers are located
1403 in a sigcontext structure somewhere on the stack.
1404 If the stack layout for sigtramp changes we might have to change these
1405 constants and the companion fixup_sigtramp in mdebugread.c */
1406 #ifndef SIGFRAME_BASE
1407 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1408 above the sigtramp frame. */
1409 #define SIGFRAME_BASE MIPS_REGSIZE
1410 /* FIXME! Are these correct?? */
1411 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1412 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1413 #define SIGFRAME_FPREGSAVE_OFF \
1414 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1416 #ifndef SIGFRAME_REG_SIZE
1417 /* FIXME! Is this correct?? */
1418 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1420 if ((get_frame_type (fci) == SIGTRAMP_FRAME))
1422 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1424 reg_position = get_frame_base (fci) + SIGFRAME_REGSAVE_OFF
1425 + ireg * SIGFRAME_REG_SIZE;
1426 get_frame_saved_regs (fci)[ireg] = reg_position;
1428 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1430 reg_position = get_frame_base (fci) + SIGFRAME_FPREGSAVE_OFF
1431 + ireg * SIGFRAME_REG_SIZE;
1432 get_frame_saved_regs (fci)[FP0_REGNUM + ireg] = reg_position;
1434 get_frame_saved_regs (fci)[PC_REGNUM] = get_frame_base (fci) + SIGFRAME_PC_OFF;
1438 proc_desc = get_frame_extra_info (fci)->proc_desc;
1439 if (proc_desc == NULL)
1440 /* I'm not sure how/whether this can happen. Normally when we can't
1441 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1442 and set the saved_regs right away. */
1445 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1446 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1447 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1449 if ( /* In any frame other than the innermost or a frame interrupted by
1450 a signal, we assume that all registers have been saved.
1451 This assumes that all register saves in a function happen before
1452 the first function call. */
1453 (get_next_frame (fci) == NULL
1454 || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME))
1456 /* In a dummy frame we know exactly where things are saved. */
1457 && !PROC_DESC_IS_DUMMY (proc_desc)
1459 /* Don't bother unless we are inside a function prologue. Outside the
1460 prologue, we know where everything is. */
1462 && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc))
1464 /* Not sure exactly what kernel_trap means, but if it means
1465 the kernel saves the registers without a prologue doing it,
1466 we better not examine the prologue to see whether registers
1467 have been saved yet. */
1470 /* We need to figure out whether the registers that the proc_desc
1471 claims are saved have been saved yet. */
1475 /* Bitmasks; set if we have found a save for the register. */
1476 unsigned long gen_save_found = 0;
1477 unsigned long float_save_found = 0;
1480 /* If the address is odd, assume this is MIPS16 code. */
1481 addr = PROC_LOW_ADDR (proc_desc);
1482 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1484 /* Scan through this function's instructions preceding the current
1485 PC, and look for those that save registers. */
1486 while (addr < get_frame_pc (fci))
1488 inst = mips_fetch_instruction (addr);
1489 if (pc_is_mips16 (addr))
1490 mips16_decode_reg_save (inst, &gen_save_found);
1492 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1495 gen_mask = gen_save_found;
1496 float_mask = float_save_found;
1499 /* Fill in the offsets for the registers which gen_mask says
1501 reg_position = get_frame_base (fci) + PROC_REG_OFFSET (proc_desc);
1502 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1503 if (gen_mask & 0x80000000)
1505 get_frame_saved_regs (fci)[ireg] = reg_position;
1506 reg_position -= MIPS_SAVED_REGSIZE;
1509 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1510 of that normally used by gcc. Therefore, we have to fetch the first
1511 instruction of the function, and if it's an entry instruction that
1512 saves $s0 or $s1, correct their saved addresses. */
1513 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1515 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1516 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1519 int sreg_count = (inst >> 6) & 3;
1521 /* Check if the ra register was pushed on the stack. */
1522 reg_position = get_frame_base (fci) + PROC_REG_OFFSET (proc_desc);
1524 reg_position -= MIPS_SAVED_REGSIZE;
1526 /* Check if the s0 and s1 registers were pushed on the stack. */
1527 for (reg = 16; reg < sreg_count + 16; reg++)
1529 get_frame_saved_regs (fci)[reg] = reg_position;
1530 reg_position -= MIPS_SAVED_REGSIZE;
1535 /* Fill in the offsets for the registers which float_mask says
1537 reg_position = get_frame_base (fci) + PROC_FREG_OFFSET (proc_desc);
1539 /* Apparently, the freg_offset gives the offset to the first 64 bit
1542 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1543 designates the first saved 64 bit register.
1545 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1546 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1547 FREG_OFFSET, designates the address of the lower register of the
1548 register pair. Adjust the offset so that it designates the upper
1549 register of the pair -- i.e., the address of the first saved 32
1552 if (MIPS_SAVED_REGSIZE == 4)
1553 reg_position += MIPS_SAVED_REGSIZE;
1555 /* Fill in the offsets for the float registers which float_mask says
1557 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1558 if (float_mask & 0x80000000)
1560 get_frame_saved_regs (fci)[FP0_REGNUM + ireg] = reg_position;
1561 reg_position -= MIPS_SAVED_REGSIZE;
1564 get_frame_saved_regs (fci)[PC_REGNUM] = get_frame_saved_regs (fci)[RA_REGNUM];
1567 /* Set up the 'saved_regs' array. This is a data structure containing
1568 the addresses on the stack where each register has been saved, for
1569 each stack frame. Registers that have not been saved will have
1570 zero here. The stack pointer register is special: rather than the
1571 address where the stack register has been saved, saved_regs[SP_REGNUM]
1572 will have the actual value of the previous frame's stack register. */
1575 mips_frame_init_saved_regs (struct frame_info *frame)
1577 if (get_frame_saved_regs (frame) == NULL)
1579 mips_find_saved_regs (frame);
1581 get_frame_saved_regs (frame)[SP_REGNUM] = get_frame_base (frame);
1585 read_next_frame_reg (struct frame_info *fi, int regno)
1590 enum lval_type lval;
1591 void *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
1592 frame_register_unwind (fi, regno, &optimized, &lval, &addr, &realnum,
1594 /* FIXME: cagney/2002-09-13: This is just soooo bad. The MIPS
1595 should have a pseudo register range that correspons to the ABI's,
1596 rather than the ISA's, view of registers. These registers would
1597 then implicitly describe their size and hence could be used
1598 without the below munging. */
1599 if (lval == lval_memory)
1603 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
1605 return read_memory_integer (addr, MIPS_SAVED_REGSIZE);
1609 return extract_signed_integer (raw_buffer, REGISTER_VIRTUAL_SIZE (regno));
1612 /* mips_addr_bits_remove - remove useless address bits */
1615 mips_addr_bits_remove (CORE_ADDR addr)
1617 if (GDB_TARGET_IS_MIPS64)
1619 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1621 /* This hack is a work-around for existing boards using
1622 PMON, the simulator, and any other 64-bit targets that
1623 doesn't have true 64-bit addressing. On these targets,
1624 the upper 32 bits of addresses are ignored by the
1625 hardware. Thus, the PC or SP are likely to have been
1626 sign extended to all 1s by instruction sequences that
1627 load 32-bit addresses. For example, a typical piece of
1628 code that loads an address is this:
1629 lui $r2, <upper 16 bits>
1630 ori $r2, <lower 16 bits>
1631 But the lui sign-extends the value such that the upper 32
1632 bits may be all 1s. The workaround is simply to mask off
1633 these bits. In the future, gcc may be changed to support
1634 true 64-bit addressing, and this masking will have to be
1636 addr &= (CORE_ADDR) 0xffffffff;
1639 else if (mips_mask_address_p ())
1641 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1642 masking off bits, instead, the actual target should be asking
1643 for the address to be converted to a valid pointer. */
1644 /* Even when GDB is configured for some 32-bit targets
1645 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1646 so CORE_ADDR is 64 bits. So we still have to mask off
1647 useless bits from addresses. */
1648 addr &= (CORE_ADDR) 0xffffffff;
1653 /* mips_software_single_step() is called just before we want to resume
1654 the inferior, if we want to single-step it but there is no hardware
1655 or kernel single-step support (MIPS on GNU/Linux for example). We find
1656 the target of the coming instruction and breakpoint it.
1658 single_step is also called just after the inferior stops. If we had
1659 set up a simulated single-step, we undo our damage. */
1662 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1664 static CORE_ADDR next_pc;
1665 typedef char binsn_quantum[BREAKPOINT_MAX];
1666 static binsn_quantum break_mem;
1669 if (insert_breakpoints_p)
1671 pc = read_register (PC_REGNUM);
1672 next_pc = mips_next_pc (pc);
1674 target_insert_breakpoint (next_pc, break_mem);
1677 target_remove_breakpoint (next_pc, break_mem);
1681 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1686 ? SAVED_PC_AFTER_CALL (get_next_frame (prev))
1687 : get_next_frame (prev)
1688 ? FRAME_SAVED_PC (get_next_frame (prev))
1690 tmp = SKIP_TRAMPOLINE_CODE (pc);
1691 return tmp ? tmp : pc;
1696 mips_frame_saved_pc (struct frame_info *frame)
1699 mips_extra_func_info_t proc_desc = get_frame_extra_info (frame)->proc_desc;
1700 /* We have to get the saved pc from the sigcontext
1701 if it is a signal handler frame. */
1702 int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME) ? PC_REGNUM
1703 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1705 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
1708 frame_unwind_signed_register (frame, PC_REGNUM, &tmp);
1711 else if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1712 saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1714 saved_pc = read_next_frame_reg (frame, pcreg);
1716 return ADDR_BITS_REMOVE (saved_pc);
1719 static struct mips_extra_func_info temp_proc_desc;
1721 /* This hack will go away once the get_prev_frame() code has been
1722 modified to set the frame's type first. That is BEFORE init extra
1723 frame info et.al. is called. This is because it will become
1724 possible to skip the init extra info call for sigtramp and dummy
1726 static CORE_ADDR *temp_saved_regs;
1728 /* Set a register's saved stack address in temp_saved_regs. If an address
1729 has already been set for this register, do nothing; this way we will
1730 only recognize the first save of a given register in a function prologue.
1731 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1734 set_reg_offset (int regno, CORE_ADDR offset)
1736 if (temp_saved_regs[regno] == 0)
1737 temp_saved_regs[regno] = offset;
1741 /* Test whether the PC points to the return instruction at the
1742 end of a function. */
1745 mips_about_to_return (CORE_ADDR pc)
1747 if (pc_is_mips16 (pc))
1748 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1749 generates a "jr $ra"; other times it generates code to load
1750 the return address from the stack to an accessible register (such
1751 as $a3), then a "jr" using that register. This second case
1752 is almost impossible to distinguish from an indirect jump
1753 used for switch statements, so we don't even try. */
1754 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1756 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1760 /* This fencepost looks highly suspicious to me. Removing it also
1761 seems suspicious as it could affect remote debugging across serial
1765 heuristic_proc_start (CORE_ADDR pc)
1772 pc = ADDR_BITS_REMOVE (pc);
1774 fence = start_pc - heuristic_fence_post;
1778 if (heuristic_fence_post == UINT_MAX
1779 || fence < VM_MIN_ADDRESS)
1780 fence = VM_MIN_ADDRESS;
1782 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1784 /* search back for previous return */
1785 for (start_pc -= instlen;; start_pc -= instlen)
1786 if (start_pc < fence)
1788 /* It's not clear to me why we reach this point when
1789 stop_soon_quietly, but with this test, at least we
1790 don't print out warnings for every child forked (eg, on
1791 decstation). 22apr93 rich@cygnus.com. */
1792 if (!stop_soon_quietly)
1794 static int blurb_printed = 0;
1796 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1801 /* This actually happens frequently in embedded
1802 development, when you first connect to a board
1803 and your stack pointer and pc are nowhere in
1804 particular. This message needs to give people
1805 in that situation enough information to
1806 determine that it's no big deal. */
1807 printf_filtered ("\n\
1808 GDB is unable to find the start of the function at 0x%s\n\
1809 and thus can't determine the size of that function's stack frame.\n\
1810 This means that GDB may be unable to access that stack frame, or\n\
1811 the frames below it.\n\
1812 This problem is most likely caused by an invalid program counter or\n\
1814 However, if you think GDB should simply search farther back\n\
1815 from 0x%s for code which looks like the beginning of a\n\
1816 function, you can increase the range of the search using the `set\n\
1817 heuristic-fence-post' command.\n",
1818 paddr_nz (pc), paddr_nz (pc));
1825 else if (pc_is_mips16 (start_pc))
1827 unsigned short inst;
1829 /* On MIPS16, any one of the following is likely to be the
1830 start of a function:
1834 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1835 inst = mips_fetch_instruction (start_pc);
1836 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1837 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1838 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1839 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1841 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1842 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1847 else if (mips_about_to_return (start_pc))
1849 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1856 /* Fetch the immediate value from a MIPS16 instruction.
1857 If the previous instruction was an EXTEND, use it to extend
1858 the upper bits of the immediate value. This is a helper function
1859 for mips16_heuristic_proc_desc. */
1862 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1863 unsigned short inst, /* current instruction */
1864 int nbits, /* number of bits in imm field */
1865 int scale, /* scale factor to be applied to imm */
1866 int is_signed) /* is the imm field signed? */
1870 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1872 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1873 if (offset & 0x8000) /* check for negative extend */
1874 offset = 0 - (0x10000 - (offset & 0xffff));
1875 return offset | (inst & 0x1f);
1879 int max_imm = 1 << nbits;
1880 int mask = max_imm - 1;
1881 int sign_bit = max_imm >> 1;
1883 offset = inst & mask;
1884 if (is_signed && (offset & sign_bit))
1885 offset = 0 - (max_imm - offset);
1886 return offset * scale;
1891 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1892 stream from start_pc to limit_pc. */
1895 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1896 struct frame_info *next_frame, CORE_ADDR sp)
1899 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1900 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1901 unsigned inst = 0; /* current instruction */
1902 unsigned entry_inst = 0; /* the entry instruction */
1905 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1906 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1908 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1910 /* Save the previous instruction. If it's an EXTEND, we'll extract
1911 the immediate offset extension from it in mips16_get_imm. */
1914 /* Fetch and decode the instruction. */
1915 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1916 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1917 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1919 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1920 if (offset < 0) /* negative stack adjustment? */
1921 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
1923 /* Exit loop if a positive stack adjustment is found, which
1924 usually means that the stack cleanup code in the function
1925 epilogue is reached. */
1928 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1930 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1931 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1932 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1933 set_reg_offset (reg, sp + offset);
1935 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1937 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1938 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1939 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1940 set_reg_offset (reg, sp + offset);
1942 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1944 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1945 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1946 set_reg_offset (RA_REGNUM, sp + offset);
1948 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1950 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1951 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1952 set_reg_offset (RA_REGNUM, sp + offset);
1954 else if (inst == 0x673d) /* move $s1, $sp */
1957 PROC_FRAME_REG (&temp_proc_desc) = 17;
1959 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1961 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1962 frame_addr = sp + offset;
1963 PROC_FRAME_REG (&temp_proc_desc) = 17;
1964 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1966 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1968 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1969 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1970 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1971 set_reg_offset (reg, frame_addr + offset);
1973 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1975 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1976 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1977 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1978 set_reg_offset (reg, frame_addr + offset);
1980 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1981 entry_inst = inst; /* save for later processing */
1982 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1983 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
1986 /* The entry instruction is typically the first instruction in a function,
1987 and it stores registers at offsets relative to the value of the old SP
1988 (before the prologue). But the value of the sp parameter to this
1989 function is the new SP (after the prologue has been executed). So we
1990 can't calculate those offsets until we've seen the entire prologue,
1991 and can calculate what the old SP must have been. */
1992 if (entry_inst != 0)
1994 int areg_count = (entry_inst >> 8) & 7;
1995 int sreg_count = (entry_inst >> 6) & 3;
1997 /* The entry instruction always subtracts 32 from the SP. */
1998 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
2000 /* Now we can calculate what the SP must have been at the
2001 start of the function prologue. */
2002 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
2004 /* Check if a0-a3 were saved in the caller's argument save area. */
2005 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2007 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2008 set_reg_offset (reg, sp + offset);
2009 offset += MIPS_SAVED_REGSIZE;
2012 /* Check if the ra register was pushed on the stack. */
2014 if (entry_inst & 0x20)
2016 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
2017 set_reg_offset (RA_REGNUM, sp + offset);
2018 offset -= MIPS_SAVED_REGSIZE;
2021 /* Check if the s0 and s1 registers were pushed on the stack. */
2022 for (reg = 16; reg < sreg_count + 16; reg++)
2024 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2025 set_reg_offset (reg, sp + offset);
2026 offset -= MIPS_SAVED_REGSIZE;
2032 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2033 struct frame_info *next_frame, CORE_ADDR sp)
2036 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
2038 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2039 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2040 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
2041 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2042 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2044 unsigned long inst, high_word, low_word;
2047 /* Fetch the instruction. */
2048 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2050 /* Save some code by pre-extracting some useful fields. */
2051 high_word = (inst >> 16) & 0xffff;
2052 low_word = inst & 0xffff;
2053 reg = high_word & 0x1f;
2055 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2056 || high_word == 0x23bd /* addi $sp,$sp,-i */
2057 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2059 if (low_word & 0x8000) /* negative stack adjustment? */
2060 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
2062 /* Exit loop if a positive stack adjustment is found, which
2063 usually means that the stack cleanup code in the function
2064 epilogue is reached. */
2067 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2069 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2070 set_reg_offset (reg, sp + low_word);
2072 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2074 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2075 but the register size used is only 32 bits. Make the address
2076 for the saved register point to the lower 32 bits. */
2077 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2078 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
2080 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2082 /* Old gcc frame, r30 is virtual frame pointer. */
2083 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2084 frame_addr = sp + low_word;
2085 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2087 unsigned alloca_adjust;
2088 PROC_FRAME_REG (&temp_proc_desc) = 30;
2089 frame_addr = read_next_frame_reg (next_frame, 30);
2090 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2091 if (alloca_adjust > 0)
2093 /* FP > SP + frame_size. This may be because
2094 * of an alloca or somethings similar.
2095 * Fix sp to "pre-alloca" value, and try again.
2097 sp += alloca_adjust;
2102 /* move $30,$sp. With different versions of gas this will be either
2103 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2104 Accept any one of these. */
2105 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2107 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2108 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2110 unsigned alloca_adjust;
2111 PROC_FRAME_REG (&temp_proc_desc) = 30;
2112 frame_addr = read_next_frame_reg (next_frame, 30);
2113 alloca_adjust = (unsigned) (frame_addr - sp);
2114 if (alloca_adjust > 0)
2116 /* FP > SP + frame_size. This may be because
2117 * of an alloca or somethings similar.
2118 * Fix sp to "pre-alloca" value, and try again.
2120 sp += alloca_adjust;
2125 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2127 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2128 set_reg_offset (reg, frame_addr + low_word);
2133 static mips_extra_func_info_t
2134 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2135 struct frame_info *next_frame, int cur_frame)
2140 sp = read_next_frame_reg (next_frame, SP_REGNUM);
2146 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2147 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2148 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2149 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2150 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2151 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2153 if (start_pc + 200 < limit_pc)
2154 limit_pc = start_pc + 200;
2155 if (pc_is_mips16 (start_pc))
2156 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2158 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2159 return &temp_proc_desc;
2162 struct mips_objfile_private
2168 /* Global used to communicate between non_heuristic_proc_desc and
2169 compare_pdr_entries within qsort (). */
2170 static bfd *the_bfd;
2173 compare_pdr_entries (const void *a, const void *b)
2175 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2176 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2180 else if (lhs == rhs)
2186 static mips_extra_func_info_t
2187 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2189 CORE_ADDR startaddr;
2190 mips_extra_func_info_t proc_desc;
2191 struct block *b = block_for_pc (pc);
2193 struct obj_section *sec;
2194 struct mips_objfile_private *priv;
2196 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
2199 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2201 *addrptr = startaddr;
2205 sec = find_pc_section (pc);
2208 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2210 /* Search the ".pdr" section generated by GAS. This includes most of
2211 the information normally found in ECOFF PDRs. */
2213 the_bfd = sec->objfile->obfd;
2215 && (the_bfd->format == bfd_object
2216 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2217 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2219 /* Right now GAS only outputs the address as a four-byte sequence.
2220 This means that we should not bother with this method on 64-bit
2221 targets (until that is fixed). */
2223 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2224 sizeof (struct mips_objfile_private));
2226 sec->objfile->obj_private = priv;
2228 else if (priv == NULL)
2232 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2233 sizeof (struct mips_objfile_private));
2235 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2238 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2239 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2241 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2242 priv->contents, 0, priv->size);
2244 /* In general, the .pdr section is sorted. However, in the
2245 presence of multiple code sections (and other corner cases)
2246 it can become unsorted. Sort it so that we can use a faster
2248 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2253 sec->objfile->obj_private = priv;
2257 if (priv->size != 0)
2263 high = priv->size / 32;
2269 mid = (low + high) / 2;
2271 ptr = priv->contents + mid * 32;
2272 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2273 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2274 SECT_OFF_TEXT (sec->objfile));
2275 if (pdr_pc == startaddr)
2277 if (pdr_pc > startaddr)
2282 while (low != high);
2286 struct symbol *sym = find_pc_function (pc);
2288 /* Fill in what we need of the proc_desc. */
2289 proc_desc = (mips_extra_func_info_t)
2290 obstack_alloc (&sec->objfile->psymbol_obstack,
2291 sizeof (struct mips_extra_func_info));
2292 PROC_LOW_ADDR (proc_desc) = startaddr;
2294 /* Only used for dummy frames. */
2295 PROC_HIGH_ADDR (proc_desc) = 0;
2297 PROC_FRAME_OFFSET (proc_desc)
2298 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2299 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2301 PROC_FRAME_ADJUST (proc_desc) = 0;
2302 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2304 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2306 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2308 PROC_FREG_OFFSET (proc_desc)
2309 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2310 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2312 proc_desc->pdr.isym = (long) sym;
2322 if (startaddr > BLOCK_START (b))
2324 /* This is the "pathological" case referred to in a comment in
2325 print_frame_info. It might be better to move this check into
2330 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
2332 /* If we never found a PDR for this function in symbol reading, then
2333 examine prologues to find the information. */
2336 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2337 if (PROC_FRAME_REG (proc_desc) == -1)
2347 static mips_extra_func_info_t
2348 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2350 mips_extra_func_info_t proc_desc;
2351 CORE_ADDR startaddr = 0;
2353 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2357 /* IF this is the topmost frame AND
2358 * (this proc does not have debugging information OR
2359 * the PC is in the procedure prologue)
2360 * THEN create a "heuristic" proc_desc (by analyzing
2361 * the actual code) to replace the "official" proc_desc.
2363 if (next_frame == NULL)
2365 struct symtab_and_line val;
2366 struct symbol *proc_symbol =
2367 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2371 val = find_pc_line (BLOCK_START
2372 (SYMBOL_BLOCK_VALUE (proc_symbol)),
2374 val.pc = val.end ? val.end : pc;
2376 if (!proc_symbol || pc < val.pc)
2378 mips_extra_func_info_t found_heuristic =
2379 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2380 pc, next_frame, cur_frame);
2381 if (found_heuristic)
2382 proc_desc = found_heuristic;
2388 /* Is linked_proc_desc_table really necessary? It only seems to be used
2389 by procedure call dummys. However, the procedures being called ought
2390 to have their own proc_descs, and even if they don't,
2391 heuristic_proc_desc knows how to create them! */
2393 register struct linked_proc_info *link;
2395 for (link = linked_proc_desc_table; link; link = link->next)
2396 if (PROC_LOW_ADDR (&link->info) <= pc
2397 && PROC_HIGH_ADDR (&link->info) > pc)
2401 startaddr = heuristic_proc_start (pc);
2404 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2410 get_frame_pointer (struct frame_info *frame,
2411 mips_extra_func_info_t proc_desc)
2413 return ADDR_BITS_REMOVE (read_next_frame_reg (frame,
2414 PROC_FRAME_REG (proc_desc)) +
2415 PROC_FRAME_OFFSET (proc_desc) -
2416 PROC_FRAME_ADJUST (proc_desc));
2419 static mips_extra_func_info_t cached_proc_desc;
2422 mips_frame_chain (struct frame_info *frame)
2424 mips_extra_func_info_t proc_desc;
2426 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
2428 if (saved_pc == 0 || inside_entry_file (saved_pc))
2431 /* Check if the PC is inside a call stub. If it is, fetch the
2432 PC of the caller of that stub. */
2433 if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0)
2436 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0))
2438 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2439 is well, frame->frame the bottom of the current frame will
2440 contain that value. */
2441 return get_frame_base (frame);
2444 /* Look up the procedure descriptor for this PC. */
2445 proc_desc = find_proc_desc (saved_pc, frame, 1);
2449 cached_proc_desc = proc_desc;
2451 /* If no frame pointer and frame size is zero, we must be at end
2452 of stack (or otherwise hosed). If we don't check frame size,
2453 we loop forever if we see a zero size frame. */
2454 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2455 && PROC_FRAME_OFFSET (proc_desc) == 0
2456 /* The previous frame from a sigtramp frame might be frameless
2457 and have frame size zero. */
2458 && !(get_frame_type (frame) == SIGTRAMP_FRAME)
2459 /* For a generic dummy frame, let get_frame_pointer() unwind a
2460 register value saved as part of the dummy frame call. */
2461 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)))
2464 return get_frame_pointer (frame, proc_desc);
2468 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2472 /* Use proc_desc calculated in frame_chain */
2473 mips_extra_func_info_t proc_desc =
2474 get_next_frame (fci)
2476 : find_proc_desc (get_frame_pc (fci), get_next_frame (fci), 1);
2478 frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info));
2480 deprecated_set_frame_saved_regs_hack (fci, NULL);
2481 get_frame_extra_info (fci)->proc_desc =
2482 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2485 /* Fixup frame-pointer - only needed for top frame */
2486 /* This may not be quite right, if proc has a real frame register.
2487 Get the value of the frame relative sp, procedure might have been
2488 interrupted by a signal at it's very start. */
2489 if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc)
2490 && !PROC_DESC_IS_DUMMY (proc_desc))
2491 deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), SP_REGNUM));
2492 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0))
2493 /* Do not ``fix'' fci->frame. It will have the value of the
2494 generic dummy frame's top-of-stack (since the draft
2495 fci->frame is obtained by returning the unwound stack
2496 pointer) and that is what we want. That way the fci->frame
2497 value will match the top-of-stack value that was saved as
2498 part of the dummy frames data. */
2501 deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc));
2503 if (proc_desc == &temp_proc_desc)
2507 /* Do not set the saved registers for a sigtramp frame,
2508 mips_find_saved_registers will do that for us. We can't
2509 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2511 /* FIXME: cagney/2002-11-18: This problem will go away once
2512 frame.c:get_prev_frame() is modified to set the frame's
2513 type before calling functions like this. */
2514 find_pc_partial_function (get_frame_pc (fci), &name,
2515 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2516 if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name))
2518 frame_saved_regs_zalloc (fci);
2519 memcpy (get_frame_saved_regs (fci), temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2520 get_frame_saved_regs (fci)[PC_REGNUM]
2521 = get_frame_saved_regs (fci)[RA_REGNUM];
2522 /* Set value of previous frame's stack pointer. Remember that
2523 saved_regs[SP_REGNUM] is special in that it contains the
2524 value of the stack pointer register. The other saved_regs
2525 values are addresses (in the inferior) at which a given
2526 register's value may be found. */
2527 get_frame_saved_regs (fci)[SP_REGNUM] = get_frame_base (fci);
2531 /* hack: if argument regs are saved, guess these contain args */
2532 /* assume we can't tell how many args for now */
2533 get_frame_extra_info (fci)->num_args = -1;
2534 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2536 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2538 get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1;
2545 /* MIPS stack frames are almost impenetrable. When execution stops,
2546 we basically have to look at symbol information for the function
2547 that we stopped in, which tells us *which* register (if any) is
2548 the base of the frame pointer, and what offset from that register
2549 the frame itself is at.
2551 This presents a problem when trying to examine a stack in memory
2552 (that isn't executing at the moment), using the "frame" command. We
2553 don't have a PC, nor do we have any registers except SP.
2555 This routine takes two arguments, SP and PC, and tries to make the
2556 cached frames look as if these two arguments defined a frame on the
2557 cache. This allows the rest of info frame to extract the important
2558 arguments without difficulty. */
2561 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2564 error ("MIPS frame specifications require two arguments: sp and pc");
2566 return create_new_frame (argv[0], argv[1]);
2569 /* According to the current ABI, should the type be passed in a
2570 floating-point register (assuming that there is space)? When there
2571 is no FPU, FP are not even considered as possibile candidates for
2572 FP registers and, consequently this returns false - forces FP
2573 arguments into integer registers. */
2576 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2578 return ((typecode == TYPE_CODE_FLT
2580 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2581 && TYPE_NFIELDS (arg_type) == 1
2582 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2583 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2586 /* On o32, argument passing in GPRs depends on the alignment of the type being
2587 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2590 mips_type_needs_double_align (struct type *type)
2592 enum type_code typecode = TYPE_CODE (type);
2594 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2596 else if (typecode == TYPE_CODE_STRUCT)
2598 if (TYPE_NFIELDS (type) < 1)
2600 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2602 else if (typecode == TYPE_CODE_UNION)
2606 n = TYPE_NFIELDS (type);
2607 for (i = 0; i < n; i++)
2608 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2615 /* Macros to round N up or down to the next A boundary;
2616 A must be a power of two. */
2618 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2619 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2621 /* Adjust the address downward (direction of stack growth) so that it
2622 is correctly aligned for a new stack frame. */
2624 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2626 return ROUND_DOWN (addr, 16);
2630 mips_eabi_push_arguments (int nargs,
2631 struct value **args,
2634 CORE_ADDR struct_addr)
2640 int stack_offset = 0;
2642 /* First ensure that the stack and structure return address (if any)
2643 are properly aligned. The stack has to be at least 64-bit
2644 aligned even on 32-bit machines, because doubles must be 64-bit
2645 aligned. For n32 and n64, stack frames need to be 128-bit
2646 aligned, so we round to this widest known alignment. */
2648 sp = ROUND_DOWN (sp, 16);
2649 struct_addr = ROUND_DOWN (struct_addr, 16);
2651 /* Now make space on the stack for the args. We allocate more
2652 than necessary for EABI, because the first few arguments are
2653 passed in registers, but that's OK. */
2654 for (argnum = 0; argnum < nargs; argnum++)
2655 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2656 MIPS_STACK_ARGSIZE);
2657 sp -= ROUND_UP (len, 16);
2660 fprintf_unfiltered (gdb_stdlog,
2661 "mips_eabi_push_arguments: sp=0x%s allocated %d\n",
2662 paddr_nz (sp), ROUND_UP (len, 16));
2664 /* Initialize the integer and float register pointers. */
2666 float_argreg = FPA0_REGNUM;
2668 /* The struct_return pointer occupies the first parameter-passing reg. */
2672 fprintf_unfiltered (gdb_stdlog,
2673 "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n",
2674 argreg, paddr_nz (struct_addr));
2675 write_register (argreg++, struct_addr);
2678 /* Now load as many as possible of the first arguments into
2679 registers, and push the rest onto the stack. Loop thru args
2680 from first to last. */
2681 for (argnum = 0; argnum < nargs; argnum++)
2684 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2685 struct value *arg = args[argnum];
2686 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2687 int len = TYPE_LENGTH (arg_type);
2688 enum type_code typecode = TYPE_CODE (arg_type);
2691 fprintf_unfiltered (gdb_stdlog,
2692 "mips_eabi_push_arguments: %d len=%d type=%d",
2693 argnum + 1, len, (int) typecode);
2695 /* The EABI passes structures that do not fit in a register by
2697 if (len > MIPS_SAVED_REGSIZE
2698 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2700 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2701 typecode = TYPE_CODE_PTR;
2702 len = MIPS_SAVED_REGSIZE;
2705 fprintf_unfiltered (gdb_stdlog, " push");
2708 val = (char *) VALUE_CONTENTS (arg);
2710 /* 32-bit ABIs always start floating point arguments in an
2711 even-numbered floating point register. Round the FP register
2712 up before the check to see if there are any FP registers
2713 left. Non MIPS_EABI targets also pass the FP in the integer
2714 registers so also round up normal registers. */
2715 if (!FP_REGISTER_DOUBLE
2716 && fp_register_arg_p (typecode, arg_type))
2718 if ((float_argreg & 1))
2722 /* Floating point arguments passed in registers have to be
2723 treated specially. On 32-bit architectures, doubles
2724 are passed in register pairs; the even register gets
2725 the low word, and the odd register gets the high word.
2726 On non-EABI processors, the first two floating point arguments are
2727 also copied to general registers, because MIPS16 functions
2728 don't use float registers for arguments. This duplication of
2729 arguments in general registers can't hurt non-MIPS16 functions
2730 because those registers are normally skipped. */
2731 /* MIPS_EABI squeezes a struct that contains a single floating
2732 point value into an FP register instead of pushing it onto the
2734 if (fp_register_arg_p (typecode, arg_type)
2735 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2737 if (!FP_REGISTER_DOUBLE && len == 8)
2739 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2740 unsigned long regval;
2742 /* Write the low word of the double to the even register(s). */
2743 regval = extract_unsigned_integer (val + low_offset, 4);
2745 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2746 float_argreg, phex (regval, 4));
2747 write_register (float_argreg++, regval);
2749 /* Write the high word of the double to the odd register(s). */
2750 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2752 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2753 float_argreg, phex (regval, 4));
2754 write_register (float_argreg++, regval);
2758 /* This is a floating point value that fits entirely
2759 in a single register. */
2760 /* On 32 bit ABI's the float_argreg is further adjusted
2761 above to ensure that it is even register aligned. */
2762 LONGEST regval = extract_unsigned_integer (val, len);
2764 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2765 float_argreg, phex (regval, len));
2766 write_register (float_argreg++, regval);
2771 /* Copy the argument to general registers or the stack in
2772 register-sized pieces. Large arguments are split between
2773 registers and stack. */
2774 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2775 are treated specially: Irix cc passes them in registers
2776 where gcc sometimes puts them on the stack. For maximum
2777 compatibility, we will put them in both places. */
2778 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2779 (len % MIPS_SAVED_REGSIZE != 0));
2781 /* Note: Floating-point values that didn't fit into an FP
2782 register are only written to memory. */
2785 /* Remember if the argument was written to the stack. */
2786 int stack_used_p = 0;
2788 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2791 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2794 /* Write this portion of the argument to the stack. */
2795 if (argreg > MIPS_LAST_ARG_REGNUM
2797 || fp_register_arg_p (typecode, arg_type))
2799 /* Should shorter than int integer values be
2800 promoted to int before being stored? */
2801 int longword_offset = 0;
2804 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2806 if (MIPS_STACK_ARGSIZE == 8 &&
2807 (typecode == TYPE_CODE_INT ||
2808 typecode == TYPE_CODE_PTR ||
2809 typecode == TYPE_CODE_FLT) && len <= 4)
2810 longword_offset = MIPS_STACK_ARGSIZE - len;
2811 else if ((typecode == TYPE_CODE_STRUCT ||
2812 typecode == TYPE_CODE_UNION) &&
2813 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2814 longword_offset = MIPS_STACK_ARGSIZE - len;
2819 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2820 paddr_nz (stack_offset));
2821 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2822 paddr_nz (longword_offset));
2825 addr = sp + stack_offset + longword_offset;
2830 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2832 for (i = 0; i < partial_len; i++)
2834 fprintf_unfiltered (gdb_stdlog, "%02x",
2838 write_memory (addr, val, partial_len);
2841 /* Note!!! This is NOT an else clause. Odd sized
2842 structs may go thru BOTH paths. Floating point
2843 arguments will not. */
2844 /* Write this portion of the argument to a general
2845 purpose register. */
2846 if (argreg <= MIPS_LAST_ARG_REGNUM
2847 && !fp_register_arg_p (typecode, arg_type))
2849 LONGEST regval = extract_unsigned_integer (val, partial_len);
2852 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2854 phex (regval, MIPS_SAVED_REGSIZE));
2855 write_register (argreg, regval);
2862 /* Compute the the offset into the stack at which we
2863 will copy the next parameter.
2865 In the new EABI (and the NABI32), the stack_offset
2866 only needs to be adjusted when it has been used. */
2869 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2873 fprintf_unfiltered (gdb_stdlog, "\n");
2876 /* Return adjusted stack pointer. */
2880 /* N32/N64 version of push_arguments. */
2883 mips_n32n64_push_arguments (int nargs,
2884 struct value **args,
2887 CORE_ADDR struct_addr)
2893 int stack_offset = 0;
2895 /* First ensure that the stack and structure return address (if any)
2896 are properly aligned. The stack has to be at least 64-bit
2897 aligned even on 32-bit machines, because doubles must be 64-bit
2898 aligned. For n32 and n64, stack frames need to be 128-bit
2899 aligned, so we round to this widest known alignment. */
2901 sp = ROUND_DOWN (sp, 16);
2902 struct_addr = ROUND_DOWN (struct_addr, 16);
2904 /* Now make space on the stack for the args. */
2905 for (argnum = 0; argnum < nargs; argnum++)
2906 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2907 MIPS_STACK_ARGSIZE);
2908 sp -= ROUND_UP (len, 16);
2911 fprintf_unfiltered (gdb_stdlog,
2912 "mips_n32n64_push_arguments: sp=0x%s allocated %d\n",
2913 paddr_nz (sp), ROUND_UP (len, 16));
2915 /* Initialize the integer and float register pointers. */
2917 float_argreg = FPA0_REGNUM;
2919 /* The struct_return pointer occupies the first parameter-passing reg. */
2923 fprintf_unfiltered (gdb_stdlog,
2924 "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n",
2925 argreg, paddr_nz (struct_addr));
2926 write_register (argreg++, struct_addr);
2929 /* Now load as many as possible of the first arguments into
2930 registers, and push the rest onto the stack. Loop thru args
2931 from first to last. */
2932 for (argnum = 0; argnum < nargs; argnum++)
2935 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2936 struct value *arg = args[argnum];
2937 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2938 int len = TYPE_LENGTH (arg_type);
2939 enum type_code typecode = TYPE_CODE (arg_type);
2942 fprintf_unfiltered (gdb_stdlog,
2943 "mips_n32n64_push_arguments: %d len=%d type=%d",
2944 argnum + 1, len, (int) typecode);
2946 val = (char *) VALUE_CONTENTS (arg);
2948 if (fp_register_arg_p (typecode, arg_type)
2949 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2951 /* This is a floating point value that fits entirely
2952 in a single register. */
2953 /* On 32 bit ABI's the float_argreg is further adjusted
2954 above to ensure that it is even register aligned. */
2955 LONGEST regval = extract_unsigned_integer (val, len);
2957 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2958 float_argreg, phex (regval, len));
2959 write_register (float_argreg++, regval);
2962 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2963 argreg, phex (regval, len));
2964 write_register (argreg, regval);
2969 /* Copy the argument to general registers or the stack in
2970 register-sized pieces. Large arguments are split between
2971 registers and stack. */
2972 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2973 are treated specially: Irix cc passes them in registers
2974 where gcc sometimes puts them on the stack. For maximum
2975 compatibility, we will put them in both places. */
2976 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2977 (len % MIPS_SAVED_REGSIZE != 0));
2978 /* Note: Floating-point values that didn't fit into an FP
2979 register are only written to memory. */
2982 /* Rememer if the argument was written to the stack. */
2983 int stack_used_p = 0;
2984 int partial_len = len < MIPS_SAVED_REGSIZE ?
2985 len : MIPS_SAVED_REGSIZE;
2988 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2991 /* Write this portion of the argument to the stack. */
2992 if (argreg > MIPS_LAST_ARG_REGNUM
2994 || fp_register_arg_p (typecode, arg_type))
2996 /* Should shorter than int integer values be
2997 promoted to int before being stored? */
2998 int longword_offset = 0;
3001 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3003 if (MIPS_STACK_ARGSIZE == 8 &&
3004 (typecode == TYPE_CODE_INT ||
3005 typecode == TYPE_CODE_PTR ||
3006 typecode == TYPE_CODE_FLT) && len <= 4)
3007 longword_offset = MIPS_STACK_ARGSIZE - len;
3012 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3013 paddr_nz (stack_offset));
3014 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3015 paddr_nz (longword_offset));
3018 addr = sp + stack_offset + longword_offset;
3023 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3025 for (i = 0; i < partial_len; i++)
3027 fprintf_unfiltered (gdb_stdlog, "%02x",
3031 write_memory (addr, val, partial_len);
3034 /* Note!!! This is NOT an else clause. Odd sized
3035 structs may go thru BOTH paths. Floating point
3036 arguments will not. */
3037 /* Write this portion of the argument to a general
3038 purpose register. */
3039 if (argreg <= MIPS_LAST_ARG_REGNUM
3040 && !fp_register_arg_p (typecode, arg_type))
3042 LONGEST regval = extract_unsigned_integer (val, partial_len);
3044 /* A non-floating-point argument being passed in a
3045 general register. If a struct or union, and if
3046 the remaining length is smaller than the register
3047 size, we have to adjust the register value on
3050 It does not seem to be necessary to do the
3051 same for integral types.
3053 cagney/2001-07-23: gdb/179: Also, GCC, when
3054 outputting LE O32 with sizeof (struct) <
3055 MIPS_SAVED_REGSIZE, generates a left shift as
3056 part of storing the argument in a register a
3057 register (the left shift isn't generated when
3058 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3059 is quite possible that this is GCC contradicting
3060 the LE/O32 ABI, GDB has not been adjusted to
3061 accommodate this. Either someone needs to
3062 demonstrate that the LE/O32 ABI specifies such a
3063 left shift OR this new ABI gets identified as
3064 such and GDB gets tweaked accordingly. */
3066 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3067 && partial_len < MIPS_SAVED_REGSIZE
3068 && (typecode == TYPE_CODE_STRUCT ||
3069 typecode == TYPE_CODE_UNION))
3070 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3074 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3076 phex (regval, MIPS_SAVED_REGSIZE));
3077 write_register (argreg, regval);
3084 /* Compute the the offset into the stack at which we
3085 will copy the next parameter.
3087 In N32 (N64?), the stack_offset only needs to be
3088 adjusted when it has been used. */
3091 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3095 fprintf_unfiltered (gdb_stdlog, "\n");
3098 /* Return adjusted stack pointer. */
3102 /* O32 version of push_arguments. */
3105 mips_o32_push_arguments (int nargs,
3106 struct value **args,
3109 CORE_ADDR struct_addr)
3115 int stack_offset = 0;
3117 /* First ensure that the stack and structure return address (if any)
3118 are properly aligned. The stack has to be at least 64-bit
3119 aligned even on 32-bit machines, because doubles must be 64-bit
3120 aligned. For n32 and n64, stack frames need to be 128-bit
3121 aligned, so we round to this widest known alignment. */
3123 sp = ROUND_DOWN (sp, 16);
3124 struct_addr = ROUND_DOWN (struct_addr, 16);
3126 /* Now make space on the stack for the args. */
3127 for (argnum = 0; argnum < nargs; argnum++)
3128 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3129 MIPS_STACK_ARGSIZE);
3130 sp -= ROUND_UP (len, 16);
3133 fprintf_unfiltered (gdb_stdlog,
3134 "mips_o32_push_arguments: sp=0x%s allocated %d\n",
3135 paddr_nz (sp), ROUND_UP (len, 16));
3137 /* Initialize the integer and float register pointers. */
3139 float_argreg = FPA0_REGNUM;
3141 /* The struct_return pointer occupies the first parameter-passing reg. */
3145 fprintf_unfiltered (gdb_stdlog,
3146 "mips_o32_push_arguments: struct_return reg=%d 0x%s\n",
3147 argreg, paddr_nz (struct_addr));
3148 write_register (argreg++, struct_addr);
3149 stack_offset += MIPS_STACK_ARGSIZE;
3152 /* Now load as many as possible of the first arguments into
3153 registers, and push the rest onto the stack. Loop thru args
3154 from first to last. */
3155 for (argnum = 0; argnum < nargs; argnum++)
3158 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
3159 struct value *arg = args[argnum];
3160 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3161 int len = TYPE_LENGTH (arg_type);
3162 enum type_code typecode = TYPE_CODE (arg_type);
3165 fprintf_unfiltered (gdb_stdlog,
3166 "mips_o32_push_arguments: %d len=%d type=%d",
3167 argnum + 1, len, (int) typecode);
3169 val = (char *) VALUE_CONTENTS (arg);
3171 /* 32-bit ABIs always start floating point arguments in an
3172 even-numbered floating point register. Round the FP register
3173 up before the check to see if there are any FP registers
3174 left. O32/O64 targets also pass the FP in the integer
3175 registers so also round up normal registers. */
3176 if (!FP_REGISTER_DOUBLE
3177 && fp_register_arg_p (typecode, arg_type))
3179 if ((float_argreg & 1))
3183 /* Floating point arguments passed in registers have to be
3184 treated specially. On 32-bit architectures, doubles
3185 are passed in register pairs; the even register gets
3186 the low word, and the odd register gets the high word.
3187 On O32/O64, the first two floating point arguments are
3188 also copied to general registers, because MIPS16 functions
3189 don't use float registers for arguments. This duplication of
3190 arguments in general registers can't hurt non-MIPS16 functions
3191 because those registers are normally skipped. */
3193 if (fp_register_arg_p (typecode, arg_type)
3194 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3196 if (!FP_REGISTER_DOUBLE && len == 8)
3198 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3199 unsigned long regval;
3201 /* Write the low word of the double to the even register(s). */
3202 regval = extract_unsigned_integer (val + low_offset, 4);
3204 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3205 float_argreg, phex (regval, 4));
3206 write_register (float_argreg++, regval);
3208 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3209 argreg, phex (regval, 4));
3210 write_register (argreg++, regval);
3212 /* Write the high word of the double to the odd register(s). */
3213 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3215 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3216 float_argreg, phex (regval, 4));
3217 write_register (float_argreg++, regval);
3220 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3221 argreg, phex (regval, 4));
3222 write_register (argreg++, regval);
3226 /* This is a floating point value that fits entirely
3227 in a single register. */
3228 /* On 32 bit ABI's the float_argreg is further adjusted
3229 above to ensure that it is even register aligned. */
3230 LONGEST regval = extract_unsigned_integer (val, len);
3232 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3233 float_argreg, phex (regval, len));
3234 write_register (float_argreg++, regval);
3235 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3236 registers for each argument. The below is (my
3237 guess) to ensure that the corresponding integer
3238 register has reserved the same space. */
3240 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3241 argreg, phex (regval, len));
3242 write_register (argreg, regval);
3243 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3245 /* Reserve space for the FP register. */
3246 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3250 /* Copy the argument to general registers or the stack in
3251 register-sized pieces. Large arguments are split between
3252 registers and stack. */
3253 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3254 are treated specially: Irix cc passes them in registers
3255 where gcc sometimes puts them on the stack. For maximum
3256 compatibility, we will put them in both places. */
3257 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3258 (len % MIPS_SAVED_REGSIZE != 0));
3259 /* Structures should be aligned to eight bytes (even arg registers)
3260 on MIPS_ABI_O32, if their first member has double precision. */
3261 if (MIPS_SAVED_REGSIZE < 8
3262 && mips_type_needs_double_align (arg_type))
3267 /* Note: Floating-point values that didn't fit into an FP
3268 register are only written to memory. */
3271 /* Remember if the argument was written to the stack. */
3272 int stack_used_p = 0;
3274 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3277 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3280 /* Write this portion of the argument to the stack. */
3281 if (argreg > MIPS_LAST_ARG_REGNUM
3283 || fp_register_arg_p (typecode, arg_type))
3285 /* Should shorter than int integer values be
3286 promoted to int before being stored? */
3287 int longword_offset = 0;
3290 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3292 if (MIPS_STACK_ARGSIZE == 8 &&
3293 (typecode == TYPE_CODE_INT ||
3294 typecode == TYPE_CODE_PTR ||
3295 typecode == TYPE_CODE_FLT) && len <= 4)
3296 longword_offset = MIPS_STACK_ARGSIZE - len;
3301 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3302 paddr_nz (stack_offset));
3303 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3304 paddr_nz (longword_offset));
3307 addr = sp + stack_offset + longword_offset;
3312 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3314 for (i = 0; i < partial_len; i++)
3316 fprintf_unfiltered (gdb_stdlog, "%02x",
3320 write_memory (addr, val, partial_len);
3323 /* Note!!! This is NOT an else clause. Odd sized
3324 structs may go thru BOTH paths. Floating point
3325 arguments will not. */
3326 /* Write this portion of the argument to a general
3327 purpose register. */
3328 if (argreg <= MIPS_LAST_ARG_REGNUM
3329 && !fp_register_arg_p (typecode, arg_type))
3331 LONGEST regval = extract_signed_integer (val, partial_len);
3332 /* Value may need to be sign extended, because
3333 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3335 /* A non-floating-point argument being passed in a
3336 general register. If a struct or union, and if
3337 the remaining length is smaller than the register
3338 size, we have to adjust the register value on
3341 It does not seem to be necessary to do the
3342 same for integral types.
3344 Also don't do this adjustment on O64 binaries.
3346 cagney/2001-07-23: gdb/179: Also, GCC, when
3347 outputting LE O32 with sizeof (struct) <
3348 MIPS_SAVED_REGSIZE, generates a left shift as
3349 part of storing the argument in a register a
3350 register (the left shift isn't generated when
3351 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3352 is quite possible that this is GCC contradicting
3353 the LE/O32 ABI, GDB has not been adjusted to
3354 accommodate this. Either someone needs to
3355 demonstrate that the LE/O32 ABI specifies such a
3356 left shift OR this new ABI gets identified as
3357 such and GDB gets tweaked accordingly. */
3359 if (MIPS_SAVED_REGSIZE < 8
3360 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3361 && partial_len < MIPS_SAVED_REGSIZE
3362 && (typecode == TYPE_CODE_STRUCT ||
3363 typecode == TYPE_CODE_UNION))
3364 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3368 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3370 phex (regval, MIPS_SAVED_REGSIZE));
3371 write_register (argreg, regval);
3374 /* Prevent subsequent floating point arguments from
3375 being passed in floating point registers. */
3376 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3382 /* Compute the the offset into the stack at which we
3383 will copy the next parameter.
3385 In older ABIs, the caller reserved space for
3386 registers that contained arguments. This was loosely
3387 refered to as their "home". Consequently, space is
3388 always allocated. */
3390 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3394 fprintf_unfiltered (gdb_stdlog, "\n");
3397 /* Return adjusted stack pointer. */
3401 /* O64 version of push_arguments. */
3404 mips_o64_push_arguments (int nargs,
3405 struct value **args,
3408 CORE_ADDR struct_addr)
3414 int stack_offset = 0;
3416 /* First ensure that the stack and structure return address (if any)
3417 are properly aligned. The stack has to be at least 64-bit
3418 aligned even on 32-bit machines, because doubles must be 64-bit
3419 aligned. For n32 and n64, stack frames need to be 128-bit
3420 aligned, so we round to this widest known alignment. */
3422 sp = ROUND_DOWN (sp, 16);
3423 struct_addr = ROUND_DOWN (struct_addr, 16);
3425 /* Now make space on the stack for the args. */
3426 for (argnum = 0; argnum < nargs; argnum++)
3427 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3428 MIPS_STACK_ARGSIZE);
3429 sp -= ROUND_UP (len, 16);
3432 fprintf_unfiltered (gdb_stdlog,
3433 "mips_o64_push_arguments: sp=0x%s allocated %d\n",
3434 paddr_nz (sp), ROUND_UP (len, 16));
3436 /* Initialize the integer and float register pointers. */
3438 float_argreg = FPA0_REGNUM;
3440 /* The struct_return pointer occupies the first parameter-passing reg. */
3444 fprintf_unfiltered (gdb_stdlog,
3445 "mips_o64_push_arguments: struct_return reg=%d 0x%s\n",
3446 argreg, paddr_nz (struct_addr));
3447 write_register (argreg++, struct_addr);
3448 stack_offset += MIPS_STACK_ARGSIZE;
3451 /* Now load as many as possible of the first arguments into
3452 registers, and push the rest onto the stack. Loop thru args
3453 from first to last. */
3454 for (argnum = 0; argnum < nargs; argnum++)
3457 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
3458 struct value *arg = args[argnum];
3459 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3460 int len = TYPE_LENGTH (arg_type);
3461 enum type_code typecode = TYPE_CODE (arg_type);
3464 fprintf_unfiltered (gdb_stdlog,
3465 "mips_o64_push_arguments: %d len=%d type=%d",
3466 argnum + 1, len, (int) typecode);
3468 val = (char *) VALUE_CONTENTS (arg);
3470 /* 32-bit ABIs always start floating point arguments in an
3471 even-numbered floating point register. Round the FP register
3472 up before the check to see if there are any FP registers
3473 left. O32/O64 targets also pass the FP in the integer
3474 registers so also round up normal registers. */
3475 if (!FP_REGISTER_DOUBLE
3476 && fp_register_arg_p (typecode, arg_type))
3478 if ((float_argreg & 1))
3482 /* Floating point arguments passed in registers have to be
3483 treated specially. On 32-bit architectures, doubles
3484 are passed in register pairs; the even register gets
3485 the low word, and the odd register gets the high word.
3486 On O32/O64, the first two floating point arguments are
3487 also copied to general registers, because MIPS16 functions
3488 don't use float registers for arguments. This duplication of
3489 arguments in general registers can't hurt non-MIPS16 functions
3490 because those registers are normally skipped. */
3492 if (fp_register_arg_p (typecode, arg_type)
3493 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3495 if (!FP_REGISTER_DOUBLE && len == 8)
3497 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3498 unsigned long regval;
3500 /* Write the low word of the double to the even register(s). */
3501 regval = extract_unsigned_integer (val + low_offset, 4);
3503 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3504 float_argreg, phex (regval, 4));
3505 write_register (float_argreg++, regval);
3507 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3508 argreg, phex (regval, 4));
3509 write_register (argreg++, regval);
3511 /* Write the high word of the double to the odd register(s). */
3512 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3514 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3515 float_argreg, phex (regval, 4));
3516 write_register (float_argreg++, regval);
3519 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3520 argreg, phex (regval, 4));
3521 write_register (argreg++, regval);
3525 /* This is a floating point value that fits entirely
3526 in a single register. */
3527 /* On 32 bit ABI's the float_argreg is further adjusted
3528 above to ensure that it is even register aligned. */
3529 LONGEST regval = extract_unsigned_integer (val, len);
3531 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3532 float_argreg, phex (regval, len));
3533 write_register (float_argreg++, regval);
3534 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3535 registers for each argument. The below is (my
3536 guess) to ensure that the corresponding integer
3537 register has reserved the same space. */
3539 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3540 argreg, phex (regval, len));
3541 write_register (argreg, regval);
3542 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3544 /* Reserve space for the FP register. */
3545 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3549 /* Copy the argument to general registers or the stack in
3550 register-sized pieces. Large arguments are split between
3551 registers and stack. */
3552 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3553 are treated specially: Irix cc passes them in registers
3554 where gcc sometimes puts them on the stack. For maximum
3555 compatibility, we will put them in both places. */
3556 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3557 (len % MIPS_SAVED_REGSIZE != 0));
3558 /* Structures should be aligned to eight bytes (even arg registers)
3559 on MIPS_ABI_O32, if their first member has double precision. */
3560 if (MIPS_SAVED_REGSIZE < 8
3561 && mips_type_needs_double_align (arg_type))
3566 /* Note: Floating-point values that didn't fit into an FP
3567 register are only written to memory. */
3570 /* Remember if the argument was written to the stack. */
3571 int stack_used_p = 0;
3573 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3576 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3579 /* Write this portion of the argument to the stack. */
3580 if (argreg > MIPS_LAST_ARG_REGNUM
3582 || fp_register_arg_p (typecode, arg_type))
3584 /* Should shorter than int integer values be
3585 promoted to int before being stored? */
3586 int longword_offset = 0;
3589 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3591 if (MIPS_STACK_ARGSIZE == 8 &&
3592 (typecode == TYPE_CODE_INT ||
3593 typecode == TYPE_CODE_PTR ||
3594 typecode == TYPE_CODE_FLT) && len <= 4)
3595 longword_offset = MIPS_STACK_ARGSIZE - len;
3600 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3601 paddr_nz (stack_offset));
3602 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3603 paddr_nz (longword_offset));
3606 addr = sp + stack_offset + longword_offset;
3611 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3613 for (i = 0; i < partial_len; i++)
3615 fprintf_unfiltered (gdb_stdlog, "%02x",
3619 write_memory (addr, val, partial_len);
3622 /* Note!!! This is NOT an else clause. Odd sized
3623 structs may go thru BOTH paths. Floating point
3624 arguments will not. */
3625 /* Write this portion of the argument to a general
3626 purpose register. */
3627 if (argreg <= MIPS_LAST_ARG_REGNUM
3628 && !fp_register_arg_p (typecode, arg_type))
3630 LONGEST regval = extract_signed_integer (val, partial_len);
3631 /* Value may need to be sign extended, because
3632 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3634 /* A non-floating-point argument being passed in a
3635 general register. If a struct or union, and if
3636 the remaining length is smaller than the register
3637 size, we have to adjust the register value on
3640 It does not seem to be necessary to do the
3641 same for integral types.
3643 Also don't do this adjustment on O64 binaries.
3645 cagney/2001-07-23: gdb/179: Also, GCC, when
3646 outputting LE O32 with sizeof (struct) <
3647 MIPS_SAVED_REGSIZE, generates a left shift as
3648 part of storing the argument in a register a
3649 register (the left shift isn't generated when
3650 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3651 is quite possible that this is GCC contradicting
3652 the LE/O32 ABI, GDB has not been adjusted to
3653 accommodate this. Either someone needs to
3654 demonstrate that the LE/O32 ABI specifies such a
3655 left shift OR this new ABI gets identified as
3656 such and GDB gets tweaked accordingly. */
3658 if (MIPS_SAVED_REGSIZE < 8
3659 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3660 && partial_len < MIPS_SAVED_REGSIZE
3661 && (typecode == TYPE_CODE_STRUCT ||
3662 typecode == TYPE_CODE_UNION))
3663 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3667 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3669 phex (regval, MIPS_SAVED_REGSIZE));
3670 write_register (argreg, regval);
3673 /* Prevent subsequent floating point arguments from
3674 being passed in floating point registers. */
3675 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3681 /* Compute the the offset into the stack at which we
3682 will copy the next parameter.
3684 In older ABIs, the caller reserved space for
3685 registers that contained arguments. This was loosely
3686 refered to as their "home". Consequently, space is
3687 always allocated. */
3689 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3693 fprintf_unfiltered (gdb_stdlog, "\n");
3696 /* Return adjusted stack pointer. */
3701 mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
3703 /* Set the return address register to point to the entry
3704 point of the program, where a breakpoint lies in wait. */
3705 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
3710 mips_push_register (CORE_ADDR * sp, int regno)
3712 char *buffer = alloca (MAX_REGISTER_RAW_SIZE);
3715 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
3717 regsize = MIPS_SAVED_REGSIZE;
3718 offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3719 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
3724 regsize = REGISTER_RAW_SIZE (regno);
3728 deprecated_read_register_gen (regno, buffer);
3729 write_memory (*sp, buffer + offset, regsize);
3732 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
3733 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
3736 mips_push_dummy_frame (void)
3739 struct linked_proc_info *link = (struct linked_proc_info *)
3740 xmalloc (sizeof (struct linked_proc_info));
3741 mips_extra_func_info_t proc_desc = &link->info;
3742 CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
3743 CORE_ADDR old_sp = sp;
3744 link->next = linked_proc_desc_table;
3745 linked_proc_desc_table = link;
3747 /* FIXME! are these correct ? */
3748 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
3749 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
3750 #define FLOAT_REG_SAVE_MASK MASK(0,19)
3751 #define FLOAT_SINGLE_REG_SAVE_MASK \
3752 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
3754 * The registers we must save are all those not preserved across
3755 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
3756 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
3757 * and FP Control/Status registers.
3760 * Dummy frame layout:
3763 * Saved MMHI, MMLO, FPC_CSR
3768 * Saved D18 (i.e. F19, F18)
3770 * Saved D0 (i.e. F1, F0)
3771 * Argument build area and stack arguments written via mips_push_arguments
3775 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
3776 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
3777 PROC_FRAME_OFFSET (proc_desc) = 0;
3778 PROC_FRAME_ADJUST (proc_desc) = 0;
3779 mips_push_register (&sp, PC_REGNUM);
3780 mips_push_register (&sp, HI_REGNUM);
3781 mips_push_register (&sp, LO_REGNUM);
3782 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
3784 /* Save general CPU registers */
3785 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
3786 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
3787 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
3788 for (ireg = 32; --ireg >= 0;)
3789 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
3790 mips_push_register (&sp, ireg);
3792 /* Save floating point registers starting with high order word */
3793 PROC_FREG_MASK (proc_desc) =
3794 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
3795 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
3796 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
3798 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
3799 for (ireg = 32; --ireg >= 0;)
3800 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
3801 mips_push_register (&sp, ireg + FP0_REGNUM);
3803 /* Update the frame pointer for the call dummy and the stack pointer.
3804 Set the procedure's starting and ending addresses to point to the
3805 call dummy address at the entry point. */
3806 write_register (PUSH_FP_REGNUM, old_sp);
3807 write_register (SP_REGNUM, sp);
3808 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
3809 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
3810 SET_PROC_DESC_IS_DUMMY (proc_desc);
3811 PROC_PC_REG (proc_desc) = RA_REGNUM;
3815 mips_pop_frame (void)
3817 register int regnum;
3818 struct frame_info *frame = get_current_frame ();
3819 CORE_ADDR new_sp = get_frame_base (frame);
3820 mips_extra_func_info_t proc_desc = get_frame_extra_info (frame)->proc_desc;
3822 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
3824 generic_pop_dummy_frame ();
3825 flush_cached_frames ();
3829 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
3830 if (get_frame_saved_regs (frame) == NULL)
3831 FRAME_INIT_SAVED_REGS (frame);
3832 for (regnum = 0; regnum < NUM_REGS; regnum++)
3833 if (regnum != SP_REGNUM && regnum != PC_REGNUM
3834 && get_frame_saved_regs (frame)[regnum])
3836 /* Floating point registers must not be sign extended,
3837 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3839 if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32)
3840 write_register (regnum,
3841 read_memory_unsigned_integer (get_frame_saved_regs (frame)[regnum],
3842 MIPS_SAVED_REGSIZE));
3844 write_register (regnum,
3845 read_memory_integer (get_frame_saved_regs (frame)[regnum],
3846 MIPS_SAVED_REGSIZE));
3849 write_register (SP_REGNUM, new_sp);
3850 flush_cached_frames ();
3852 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
3854 struct linked_proc_info *pi_ptr, *prev_ptr;
3856 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
3858 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
3860 if (&pi_ptr->info == proc_desc)
3865 error ("Can't locate dummy extra frame info\n");
3867 if (prev_ptr != NULL)
3868 prev_ptr->next = pi_ptr->next;
3870 linked_proc_desc_table = pi_ptr->next;
3874 write_register (HI_REGNUM,
3875 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
3876 MIPS_SAVED_REGSIZE));
3877 write_register (LO_REGNUM,
3878 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
3879 MIPS_SAVED_REGSIZE));
3880 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
3881 write_register (FCRCS_REGNUM,
3882 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
3883 MIPS_SAVED_REGSIZE));
3888 mips_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
3889 struct value **args, struct type *type, int gcc_p)
3891 write_register(T9_REGNUM, fun);
3894 /* Floating point register management.
3896 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3897 64bit operations, these early MIPS cpus treat fp register pairs
3898 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3899 registers and offer a compatibility mode that emulates the MIPS2 fp
3900 model. When operating in MIPS2 fp compat mode, later cpu's split
3901 double precision floats into two 32-bit chunks and store them in
3902 consecutive fp regs. To display 64-bit floats stored in this
3903 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3904 Throw in user-configurable endianness and you have a real mess.
3906 The way this works is:
3907 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3908 double-precision value will be split across two logical registers.
3909 The lower-numbered logical register will hold the low-order bits,
3910 regardless of the processor's endianness.
3911 - If we are on a 64-bit processor, and we are looking for a
3912 single-precision value, it will be in the low ordered bits
3913 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3914 save slot in memory.
3915 - If we are in 64-bit mode, everything is straightforward.
3917 Note that this code only deals with "live" registers at the top of the
3918 stack. We will attempt to deal with saved registers later, when
3919 the raw/cooked register interface is in place. (We need a general
3920 interface that can deal with dynamic saved register sizes -- fp
3921 regs could be 32 bits wide in one frame and 64 on the frame above
3924 static struct type *
3925 mips_float_register_type (void)
3927 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3928 return builtin_type_ieee_single_big;
3930 return builtin_type_ieee_single_little;
3933 static struct type *
3934 mips_double_register_type (void)
3936 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3937 return builtin_type_ieee_double_big;
3939 return builtin_type_ieee_double_little;
3942 /* Copy a 32-bit single-precision value from the current frame
3943 into rare_buffer. */
3946 mips_read_fp_register_single (int regno, char *rare_buffer)
3948 int raw_size = REGISTER_RAW_SIZE (regno);
3949 char *raw_buffer = alloca (raw_size);
3951 if (!frame_register_read (deprecated_selected_frame, regno, raw_buffer))
3952 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3955 /* We have a 64-bit value for this register. Find the low-order
3959 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3964 memcpy (rare_buffer, raw_buffer + offset, 4);
3968 memcpy (rare_buffer, raw_buffer, 4);
3972 /* Copy a 64-bit double-precision value from the current frame into
3973 rare_buffer. This may include getting half of it from the next
3977 mips_read_fp_register_double (int regno, char *rare_buffer)
3979 int raw_size = REGISTER_RAW_SIZE (regno);
3981 if (raw_size == 8 && !mips2_fp_compat ())
3983 /* We have a 64-bit value for this register, and we should use
3985 if (!frame_register_read (deprecated_selected_frame, regno, rare_buffer))
3986 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3990 if ((regno - FP0_REGNUM) & 1)
3991 internal_error (__FILE__, __LINE__,
3992 "mips_read_fp_register_double: bad access to "
3993 "odd-numbered FP register");
3995 /* mips_read_fp_register_single will find the correct 32 bits from
3997 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3999 mips_read_fp_register_single (regno, rare_buffer + 4);
4000 mips_read_fp_register_single (regno + 1, rare_buffer);
4004 mips_read_fp_register_single (regno, rare_buffer);
4005 mips_read_fp_register_single (regno + 1, rare_buffer + 4);
4011 mips_print_register (int regnum, int all)
4013 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4015 /* Get the data in raw format. */
4016 if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
4018 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
4022 /* If we have a actual 32-bit floating point register (or we are in
4023 32-bit compatibility mode), and the register is even-numbered,
4024 also print it as a double (spanning two registers). */
4025 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
4026 && (REGISTER_RAW_SIZE (regnum) == 4
4027 || mips2_fp_compat ())
4028 && !((regnum - FP0_REGNUM) & 1))
4030 char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE);
4032 mips_read_fp_register_double (regnum, dbuffer);
4034 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
4035 val_print (mips_double_register_type (), dbuffer, 0, 0,
4036 gdb_stdout, 0, 1, 0, Val_pretty_default);
4037 printf_filtered ("); ");
4039 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
4041 /* The problem with printing numeric register names (r26, etc.) is that
4042 the user can't use them on input. Probably the best solution is to
4043 fix it so that either the numeric or the funky (a2, etc.) names
4044 are accepted on input. */
4045 if (regnum < MIPS_NUMREGS)
4046 printf_filtered ("(r%d): ", regnum);
4048 printf_filtered (": ");
4050 /* If virtual format is floating, print it that way. */
4051 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4052 if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
4054 /* We have a meaningful 64-bit value in this register. Show
4055 it as a 32-bit float and a 64-bit double. */
4056 int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
4058 printf_filtered (" (float) ");
4059 val_print (mips_float_register_type (), raw_buffer + offset, 0, 0,
4060 gdb_stdout, 0, 1, 0, Val_pretty_default);
4061 printf_filtered (", (double) ");
4062 val_print (mips_double_register_type (), raw_buffer, 0, 0,
4063 gdb_stdout, 0, 1, 0, Val_pretty_default);
4066 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4067 gdb_stdout, 0, 1, 0, Val_pretty_default);
4068 /* Else print as integer in hex. */
4073 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4074 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4078 print_scalar_formatted (raw_buffer + offset,
4079 REGISTER_VIRTUAL_TYPE (regnum),
4080 'x', 0, gdb_stdout);
4084 /* Replacement for generic do_registers_info.
4085 Print regs in pretty columns. */
4088 do_fp_register_row (int regnum)
4089 { /* do values for FP (float) regs */
4091 double doub, flt1, flt2; /* doubles extracted from raw hex data */
4092 int inv1, inv2, inv3;
4094 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
4096 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
4098 /* 4-byte registers: we can fit two registers per row. */
4099 /* Also print every pair of 4-byte regs as an 8-byte double. */
4100 mips_read_fp_register_single (regnum, raw_buffer);
4101 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4103 mips_read_fp_register_single (regnum + 1, raw_buffer);
4104 flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2);
4106 mips_read_fp_register_double (regnum, raw_buffer);
4107 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
4109 printf_filtered (" %-5s", REGISTER_NAME (regnum));
4111 printf_filtered (": <invalid float>");
4113 printf_filtered ("%-17.9g", flt1);
4115 printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
4117 printf_filtered (": <invalid float>");
4119 printf_filtered ("%-17.9g", flt2);
4121 printf_filtered (" dbl: ");
4123 printf_filtered ("<invalid double>");
4125 printf_filtered ("%-24.17g", doub);
4126 printf_filtered ("\n");
4128 /* may want to do hex display here (future enhancement) */
4133 /* Eight byte registers: print each one as float AND as double. */
4134 mips_read_fp_register_single (regnum, raw_buffer);
4135 flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1);
4137 mips_read_fp_register_double (regnum, raw_buffer);
4138 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
4140 printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
4142 printf_filtered ("<invalid float>");
4144 printf_filtered ("flt: %-17.9g", flt1);
4146 printf_filtered (" dbl: ");
4148 printf_filtered ("<invalid double>");
4150 printf_filtered ("%-24.17g", doub);
4152 printf_filtered ("\n");
4153 /* may want to do hex display here (future enhancement) */
4159 /* Print a row's worth of GP (int) registers, with name labels above */
4162 do_gp_register_row (int regnum)
4164 /* do values for GP (int) regs */
4165 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4166 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
4168 int start_regnum = regnum;
4169 int numregs = NUM_REGS;
4172 /* For GP registers, we print a separate row of names above the vals */
4173 printf_filtered (" ");
4174 for (col = 0; col < ncols && regnum < numregs; regnum++)
4176 if (*REGISTER_NAME (regnum) == '\0')
4177 continue; /* unused register */
4178 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4179 break; /* end the row: reached FP register */
4180 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
4181 REGISTER_NAME (regnum));
4184 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
4185 start_regnum); /* print the R0 to R31 names */
4187 regnum = start_regnum; /* go back to start of row */
4188 /* now print the values in hex, 4 or 8 to the row */
4189 for (col = 0; col < ncols && regnum < numregs; regnum++)
4191 if (*REGISTER_NAME (regnum) == '\0')
4192 continue; /* unused register */
4193 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4194 break; /* end row: reached FP register */
4195 /* OK: get the data in raw format. */
4196 if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
4197 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4198 /* pad small registers */
4199 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
4200 printf_filtered (" ");
4201 /* Now print the register value in hex, endian order. */
4202 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4203 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4204 byte < REGISTER_RAW_SIZE (regnum);
4206 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
4208 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
4211 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
4212 printf_filtered (" ");
4215 if (col > 0) /* ie. if we actually printed anything... */
4216 printf_filtered ("\n");
4221 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4224 mips_do_registers_info (int regnum, int fpregs)
4226 if (regnum != -1) /* do one specified register */
4228 if (*(REGISTER_NAME (regnum)) == '\0')
4229 error ("Not a valid register for the current processor type");
4231 mips_print_register (regnum, 0);
4232 printf_filtered ("\n");
4235 /* do all (or most) registers */
4238 while (regnum < NUM_REGS)
4240 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4241 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
4242 regnum = do_fp_register_row (regnum); /* FP regs */
4244 regnum += MIPS_NUMREGS; /* skip floating point regs */
4246 regnum = do_gp_register_row (regnum); /* GP (int) regs */
4251 /* Is this a branch with a delay slot? */
4253 static int is_delayed (unsigned long);
4256 is_delayed (unsigned long insn)
4259 for (i = 0; i < NUMOPCODES; ++i)
4260 if (mips_opcodes[i].pinfo != INSN_MACRO
4261 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4263 return (i < NUMOPCODES
4264 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4265 | INSN_COND_BRANCH_DELAY
4266 | INSN_COND_BRANCH_LIKELY)));
4270 mips_step_skips_delay (CORE_ADDR pc)
4272 char buf[MIPS_INSTLEN];
4274 /* There is no branch delay slot on MIPS16. */
4275 if (pc_is_mips16 (pc))
4278 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4279 /* If error reading memory, guess that it is not a delayed branch. */
4281 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
4285 /* Skip the PC past function prologue instructions (32-bit version).
4286 This is a helper function for mips_skip_prologue. */
4289 mips32_skip_prologue (CORE_ADDR pc)
4293 int seen_sp_adjust = 0;
4294 int load_immediate_bytes = 0;
4296 /* Skip the typical prologue instructions. These are the stack adjustment
4297 instruction and the instructions that save registers on the stack
4298 or in the gcc frame. */
4299 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
4301 unsigned long high_word;
4303 inst = mips_fetch_instruction (pc);
4304 high_word = (inst >> 16) & 0xffff;
4306 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4307 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4309 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4310 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4312 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4313 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4314 && (inst & 0x001F0000)) /* reg != $zero */
4317 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4319 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4321 continue; /* reg != $zero */
4323 /* move $s8,$sp. With different versions of gas this will be either
4324 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4325 Accept any one of these. */
4326 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4329 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4331 else if (high_word == 0x3c1c) /* lui $gp,n */
4333 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4335 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4336 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4338 /* The following instructions load $at or $t0 with an immediate
4339 value in preparation for a stack adjustment via
4340 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4341 a local variable, so we accept them only before a stack adjustment
4342 instruction was seen. */
4343 else if (!seen_sp_adjust)
4345 if (high_word == 0x3c01 || /* lui $at,n */
4346 high_word == 0x3c08) /* lui $t0,n */
4348 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4351 else if (high_word == 0x3421 || /* ori $at,$at,n */
4352 high_word == 0x3508 || /* ori $t0,$t0,n */
4353 high_word == 0x3401 || /* ori $at,$zero,n */
4354 high_word == 0x3408) /* ori $t0,$zero,n */
4356 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4366 /* In a frameless function, we might have incorrectly
4367 skipped some load immediate instructions. Undo the skipping
4368 if the load immediate was not followed by a stack adjustment. */
4369 if (load_immediate_bytes && !seen_sp_adjust)
4370 pc -= load_immediate_bytes;
4374 /* Skip the PC past function prologue instructions (16-bit version).
4375 This is a helper function for mips_skip_prologue. */
4378 mips16_skip_prologue (CORE_ADDR pc)
4381 int extend_bytes = 0;
4382 int prev_extend_bytes;
4384 /* Table of instructions likely to be found in a function prologue. */
4387 unsigned short inst;
4388 unsigned short mask;
4395 , /* addiu $sp,offset */
4399 , /* daddiu $sp,offset */
4403 , /* sw reg,n($sp) */
4407 , /* sd reg,n($sp) */
4411 , /* sw $ra,n($sp) */
4415 , /* sd $ra,n($sp) */
4423 , /* sw $a0-$a3,n($s1) */
4427 , /* move reg,$a0-$a3 */
4431 , /* entry pseudo-op */
4435 , /* addiu $s1,$sp,n */
4438 } /* end of table marker */
4441 /* Skip the typical prologue instructions. These are the stack adjustment
4442 instruction and the instructions that save registers on the stack
4443 or in the gcc frame. */
4444 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
4446 unsigned short inst;
4449 inst = mips_fetch_instruction (pc);
4451 /* Normally we ignore an extend instruction. However, if it is
4452 not followed by a valid prologue instruction, we must adjust
4453 the pc back over the extend so that it won't be considered
4454 part of the prologue. */
4455 if ((inst & 0xf800) == 0xf000) /* extend */
4457 extend_bytes = MIPS16_INSTLEN;
4460 prev_extend_bytes = extend_bytes;
4463 /* Check for other valid prologue instructions besides extend. */
4464 for (i = 0; table[i].mask != 0; i++)
4465 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4467 if (table[i].mask != 0) /* it was in table? */
4468 continue; /* ignore it */
4472 /* Return the current pc, adjusted backwards by 2 if
4473 the previous instruction was an extend. */
4474 return pc - prev_extend_bytes;
4480 /* To skip prologues, I use this predicate. Returns either PC itself
4481 if the code at PC does not look like a function prologue; otherwise
4482 returns an address that (if we're lucky) follows the prologue. If
4483 LENIENT, then we must skip everything which is involved in setting
4484 up the frame (it's OK to skip more, just so long as we don't skip
4485 anything which might clobber the registers which are being saved.
4486 We must skip more in the case where part of the prologue is in the
4487 delay slot of a non-prologue instruction). */
4490 mips_skip_prologue (CORE_ADDR pc)
4492 /* See if we can determine the end of the prologue via the symbol table.
4493 If so, then return either PC, or the PC after the prologue, whichever
4496 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4498 if (post_prologue_pc != 0)
4499 return max (pc, post_prologue_pc);
4501 /* Can't determine prologue from the symbol table, need to examine
4504 if (pc_is_mips16 (pc))
4505 return mips16_skip_prologue (pc);
4507 return mips32_skip_prologue (pc);
4510 /* Determine how a return value is stored within the MIPS register
4511 file, given the return type `valtype'. */
4513 struct return_value_word
4522 return_value_location (struct type *valtype,
4523 struct return_value_word *hi,
4524 struct return_value_word *lo)
4526 int len = TYPE_LENGTH (valtype);
4528 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
4529 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
4530 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
4532 if (!FP_REGISTER_DOUBLE && len == 8)
4534 /* We need to break a 64bit float in two 32 bit halves and
4535 spread them across a floating-point register pair. */
4536 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
4537 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
4538 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4539 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
4541 hi->reg_offset = lo->reg_offset;
4542 lo->reg = FP0_REGNUM + 0;
4543 hi->reg = FP0_REGNUM + 1;
4549 /* The floating point value fits in a single floating-point
4551 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4552 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
4555 lo->reg = FP0_REGNUM;
4566 /* Locate a result possibly spread across two registers. */
4568 lo->reg = regnum + 0;
4569 hi->reg = regnum + 1;
4570 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4571 && len < MIPS_SAVED_REGSIZE)
4573 /* "un-left-justify" the value in the low register */
4574 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
4579 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4580 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
4581 && len < MIPS_SAVED_REGSIZE * 2
4582 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
4583 TYPE_CODE (valtype) == TYPE_CODE_UNION))
4585 /* "un-left-justify" the value spread across two registers. */
4586 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
4587 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
4589 hi->len = len - lo->len;
4593 /* Only perform a partial copy of the second register. */
4596 if (len > MIPS_SAVED_REGSIZE)
4598 lo->len = MIPS_SAVED_REGSIZE;
4599 hi->len = len - MIPS_SAVED_REGSIZE;
4607 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4608 && REGISTER_RAW_SIZE (regnum) == 8
4609 && MIPS_SAVED_REGSIZE == 4)
4611 /* Account for the fact that only the least-signficant part
4612 of the register is being used */
4613 lo->reg_offset += 4;
4614 hi->reg_offset += 4;
4617 hi->buf_offset = lo->len;
4621 /* Given a return value in `regbuf' with a type `valtype', extract and
4622 copy its value into `valbuf'. */
4625 mips_eabi_extract_return_value (struct type *valtype,
4626 char regbuf[REGISTER_BYTES],
4629 struct return_value_word lo;
4630 struct return_value_word hi;
4631 return_value_location (valtype, &hi, &lo);
4633 memcpy (valbuf + lo.buf_offset,
4634 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4638 memcpy (valbuf + hi.buf_offset,
4639 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4644 mips_o64_extract_return_value (struct type *valtype,
4645 char regbuf[REGISTER_BYTES],
4648 struct return_value_word lo;
4649 struct return_value_word hi;
4650 return_value_location (valtype, &hi, &lo);
4652 memcpy (valbuf + lo.buf_offset,
4653 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4657 memcpy (valbuf + hi.buf_offset,
4658 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4662 /* Given a return value in `valbuf' with a type `valtype', write it's
4663 value into the appropriate register. */
4666 mips_eabi_store_return_value (struct type *valtype, char *valbuf)
4668 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4669 struct return_value_word lo;
4670 struct return_value_word hi;
4671 return_value_location (valtype, &hi, &lo);
4673 memset (raw_buffer, 0, sizeof (raw_buffer));
4674 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4675 deprecated_write_register_bytes (REGISTER_BYTE (lo.reg), raw_buffer,
4676 REGISTER_RAW_SIZE (lo.reg));
4680 memset (raw_buffer, 0, sizeof (raw_buffer));
4681 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4682 deprecated_write_register_bytes (REGISTER_BYTE (hi.reg), raw_buffer,
4683 REGISTER_RAW_SIZE (hi.reg));
4688 mips_o64_store_return_value (struct type *valtype, char *valbuf)
4690 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4691 struct return_value_word lo;
4692 struct return_value_word hi;
4693 return_value_location (valtype, &hi, &lo);
4695 memset (raw_buffer, 0, sizeof (raw_buffer));
4696 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4697 deprecated_write_register_bytes (REGISTER_BYTE (lo.reg), raw_buffer,
4698 REGISTER_RAW_SIZE (lo.reg));
4702 memset (raw_buffer, 0, sizeof (raw_buffer));
4703 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4704 deprecated_write_register_bytes (REGISTER_BYTE (hi.reg), raw_buffer,
4705 REGISTER_RAW_SIZE (hi.reg));
4709 /* O32 ABI stuff. */
4712 mips_o32_xfer_return_value (struct type *type,
4713 struct regcache *regcache,
4714 bfd_byte *in, const bfd_byte *out)
4716 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4717 if (TYPE_CODE (type) == TYPE_CODE_FLT
4718 && TYPE_LENGTH (type) == 4
4719 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4721 /* A single-precision floating-point value. It fits in the
4722 least significant part of FP0. */
4724 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4725 mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type),
4726 TARGET_BYTE_ORDER, in, out, 0);
4728 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4729 && TYPE_LENGTH (type) == 8
4730 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4732 /* A double-precision floating-point value. It fits in the
4733 least significant part of FP0/FP1 but with byte ordering
4734 based on the target (???). */
4736 fprintf_unfiltered (gdb_stderr, "Return float in $fp0/$fp1\n");
4737 switch (TARGET_BYTE_ORDER)
4739 case BFD_ENDIAN_LITTLE:
4740 mips_xfer_register (regcache, FP0_REGNUM + 0, 4,
4741 TARGET_BYTE_ORDER, in, out, 0);
4742 mips_xfer_register (regcache, FP0_REGNUM + 1, 4,
4743 TARGET_BYTE_ORDER, in, out, 4);
4745 case BFD_ENDIAN_BIG:
4746 mips_xfer_register (regcache, FP0_REGNUM + 1, 4,
4747 TARGET_BYTE_ORDER, in, out, 0);
4748 mips_xfer_register (regcache, FP0_REGNUM + 0, 4,
4749 TARGET_BYTE_ORDER, in, out, 4);
4752 internal_error (__FILE__, __LINE__, "bad switch");
4756 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4757 && TYPE_NFIELDS (type) <= 2
4758 && TYPE_NFIELDS (type) >= 1
4759 && ((TYPE_NFIELDS (type) == 1
4760 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4762 || (TYPE_NFIELDS (type) == 2
4763 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4765 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4767 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4769 /* A struct that contains one or two floats. Each value is part
4770 in the least significant part of their floating point
4772 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
4775 for (field = 0, regnum = FP0_REGNUM;
4776 field < TYPE_NFIELDS (type);
4777 field++, regnum += 2)
4779 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4782 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4783 mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4784 TARGET_BYTE_ORDER, in, out, offset);
4789 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4790 || TYPE_CODE (type) == TYPE_CODE_UNION)
4792 /* A structure or union. Extract the left justified value,
4793 regardless of the byte order. I.e. DO NOT USE
4797 for (offset = 0, regnum = V0_REGNUM;
4798 offset < TYPE_LENGTH (type);
4799 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4801 int xfer = REGISTER_RAW_SIZE (regnum);
4802 if (offset + xfer > TYPE_LENGTH (type))
4803 xfer = TYPE_LENGTH (type) - offset;
4805 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4806 offset, xfer, regnum);
4807 mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN,
4814 /* A scalar extract each part but least-significant-byte
4815 justified. o32 thinks registers are 4 byte, regardless of
4816 the ISA. mips_stack_argsize controls this. */
4819 for (offset = 0, regnum = V0_REGNUM;
4820 offset < TYPE_LENGTH (type);
4821 offset += mips_stack_argsize (), regnum++)
4823 int xfer = mips_stack_argsize ();
4825 if (offset + xfer > TYPE_LENGTH (type))
4826 xfer = TYPE_LENGTH (type) - offset;
4828 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4829 offset, xfer, regnum);
4830 mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER,
4837 mips_o32_extract_return_value (struct type *type,
4838 struct regcache *regcache,
4841 mips_o32_xfer_return_value (type, regcache, valbuf, NULL);
4845 mips_o32_store_return_value (struct type *type, char *valbuf)
4847 mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf);
4850 /* N32/N44 ABI stuff. */
4853 mips_n32n64_xfer_return_value (struct type *type,
4854 struct regcache *regcache,
4855 bfd_byte *in, const bfd_byte *out)
4857 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4858 if (TYPE_CODE (type) == TYPE_CODE_FLT
4859 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4861 /* A floating-point value belongs in the least significant part
4864 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4865 mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type),
4866 TARGET_BYTE_ORDER, in, out, 0);
4868 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4869 && TYPE_NFIELDS (type) <= 2
4870 && TYPE_NFIELDS (type) >= 1
4871 && ((TYPE_NFIELDS (type) == 1
4872 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4874 || (TYPE_NFIELDS (type) == 2
4875 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4877 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4879 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4881 /* A struct that contains one or two floats. Each value is part
4882 in the least significant part of their floating point
4884 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
4887 for (field = 0, regnum = FP0_REGNUM;
4888 field < TYPE_NFIELDS (type);
4889 field++, regnum += 2)
4891 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4894 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4895 mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4896 TARGET_BYTE_ORDER, in, out, offset);
4899 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4900 || TYPE_CODE (type) == TYPE_CODE_UNION)
4902 /* A structure or union. Extract the left justified value,
4903 regardless of the byte order. I.e. DO NOT USE
4907 for (offset = 0, regnum = V0_REGNUM;
4908 offset < TYPE_LENGTH (type);
4909 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4911 int xfer = REGISTER_RAW_SIZE (regnum);
4912 if (offset + xfer > TYPE_LENGTH (type))
4913 xfer = TYPE_LENGTH (type) - offset;
4915 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4916 offset, xfer, regnum);
4917 mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN,
4923 /* A scalar extract each part but least-significant-byte
4927 for (offset = 0, regnum = V0_REGNUM;
4928 offset < TYPE_LENGTH (type);
4929 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4931 int xfer = REGISTER_RAW_SIZE (regnum);
4933 if (offset + xfer > TYPE_LENGTH (type))
4934 xfer = TYPE_LENGTH (type) - offset;
4936 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4937 offset, xfer, regnum);
4938 mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER,
4945 mips_n32n64_extract_return_value (struct type *type,
4946 struct regcache *regcache,
4949 mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL);
4953 mips_n32n64_store_return_value (struct type *type, char *valbuf)
4955 mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf);
4959 mips_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
4961 /* Nothing to do -- push_arguments does all the work. */
4965 mips_extract_struct_value_address (struct regcache *regcache)
4967 /* FIXME: This will only work at random. The caller passes the
4968 struct_return address in V0, but it is not preserved. It may
4969 still be there, or this may be a random value. */
4972 regcache_cooked_read_signed (regcache, V0_REGNUM, &val);
4976 /* Exported procedure: Is PC in the signal trampoline code */
4979 mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore)
4981 if (sigtramp_address == 0)
4983 return (pc >= sigtramp_address && pc < sigtramp_end);
4986 /* Root of all "set mips "/"show mips " commands. This will eventually be
4987 used for all MIPS-specific commands. */
4990 show_mips_command (char *args, int from_tty)
4992 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4996 set_mips_command (char *args, int from_tty)
4998 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4999 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
5002 /* Commands to show/set the MIPS FPU type. */
5005 show_mipsfpu_command (char *args, int from_tty)
5008 switch (MIPS_FPU_TYPE)
5010 case MIPS_FPU_SINGLE:
5011 fpu = "single-precision";
5013 case MIPS_FPU_DOUBLE:
5014 fpu = "double-precision";
5017 fpu = "absent (none)";
5020 internal_error (__FILE__, __LINE__, "bad switch");
5022 if (mips_fpu_type_auto)
5023 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5026 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5032 set_mipsfpu_command (char *args, int from_tty)
5034 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5035 show_mipsfpu_command (args, from_tty);
5039 set_mipsfpu_single_command (char *args, int from_tty)
5041 mips_fpu_type = MIPS_FPU_SINGLE;
5042 mips_fpu_type_auto = 0;
5043 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
5047 set_mipsfpu_double_command (char *args, int from_tty)
5049 mips_fpu_type = MIPS_FPU_DOUBLE;
5050 mips_fpu_type_auto = 0;
5051 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
5055 set_mipsfpu_none_command (char *args, int from_tty)
5057 mips_fpu_type = MIPS_FPU_NONE;
5058 mips_fpu_type_auto = 0;
5059 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
5063 set_mipsfpu_auto_command (char *args, int from_tty)
5065 mips_fpu_type_auto = 1;
5068 /* Command to set the processor type. */
5071 mips_set_processor_type_command (char *args, int from_tty)
5075 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
5077 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5078 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5079 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
5081 /* Restore the value. */
5082 tmp_mips_processor_type = xstrdup (mips_processor_type);
5087 if (!mips_set_processor_type (tmp_mips_processor_type))
5089 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
5090 /* Restore its value. */
5091 tmp_mips_processor_type = xstrdup (mips_processor_type);
5096 mips_show_processor_type_command (char *args, int from_tty)
5100 /* Modify the actual processor type. */
5103 mips_set_processor_type (char *str)
5110 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5112 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
5114 mips_processor_type = str;
5115 mips_processor_reg_names = mips_processor_type_table[i].regnames;
5117 /* FIXME tweak fpu flag too */
5124 /* Attempt to identify the particular processor model by reading the
5128 mips_read_processor_type (void)
5132 prid = read_register (PRID_REGNUM);
5134 if ((prid & ~0xf) == 0x700)
5135 return savestring ("r3041", strlen ("r3041"));
5140 /* Just like reinit_frame_cache, but with the right arguments to be
5141 callable as an sfunc. */
5144 reinit_frame_cache_sfunc (char *args, int from_tty,
5145 struct cmd_list_element *c)
5147 reinit_frame_cache ();
5151 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
5153 mips_extra_func_info_t proc_desc;
5155 /* Search for the function containing this address. Set the low bit
5156 of the address when searching, in case we were given an even address
5157 that is the start of a 16-bit function. If we didn't do this,
5158 the search would fail because the symbol table says the function
5159 starts at an odd address, i.e. 1 byte past the given address. */
5160 memaddr = ADDR_BITS_REMOVE (memaddr);
5161 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
5163 /* Make an attempt to determine if this is a 16-bit function. If
5164 the procedure descriptor exists and the address therein is odd,
5165 it's definitely a 16-bit function. Otherwise, we have to just
5166 guess that if the address passed in is odd, it's 16-bits. */
5168 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
5169 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
5171 info->mach = pc_is_mips16 (memaddr) ?
5172 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
5174 /* Round down the instruction address to the appropriate boundary. */
5175 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
5177 /* Call the appropriate disassembler based on the target endian-ness. */
5178 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5179 return print_insn_big_mips (memaddr, info);
5181 return print_insn_little_mips (memaddr, info);
5184 /* Old-style breakpoint macros.
5185 The IDT board uses an unusual breakpoint value, and sometimes gets
5186 confused when it sees the usual MIPS breakpoint instruction. */
5188 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
5189 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
5190 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
5191 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
5192 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
5193 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
5194 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
5195 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
5197 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5198 counter value to determine whether a 16- or 32-bit breakpoint should be
5199 used. It returns a pointer to a string of bytes that encode a breakpoint
5200 instruction, stores the length of the string to *lenptr, and adjusts pc
5201 (if necessary) to point to the actual memory location where the
5202 breakpoint should be inserted. */
5204 static const unsigned char *
5205 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
5207 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5209 if (pc_is_mips16 (*pcptr))
5211 static unsigned char mips16_big_breakpoint[] =
5212 MIPS16_BIG_BREAKPOINT;
5213 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
5214 *lenptr = sizeof (mips16_big_breakpoint);
5215 return mips16_big_breakpoint;
5219 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
5220 static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
5221 static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
5223 *lenptr = sizeof (big_breakpoint);
5225 if (strcmp (target_shortname, "mips") == 0)
5226 return idt_big_breakpoint;
5227 else if (strcmp (target_shortname, "ddb") == 0
5228 || strcmp (target_shortname, "pmon") == 0
5229 || strcmp (target_shortname, "lsi") == 0)
5230 return pmon_big_breakpoint;
5232 return big_breakpoint;
5237 if (pc_is_mips16 (*pcptr))
5239 static unsigned char mips16_little_breakpoint[] =
5240 MIPS16_LITTLE_BREAKPOINT;
5241 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
5242 *lenptr = sizeof (mips16_little_breakpoint);
5243 return mips16_little_breakpoint;
5247 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
5248 static unsigned char pmon_little_breakpoint[] =
5249 PMON_LITTLE_BREAKPOINT;
5250 static unsigned char idt_little_breakpoint[] =
5251 IDT_LITTLE_BREAKPOINT;
5253 *lenptr = sizeof (little_breakpoint);
5255 if (strcmp (target_shortname, "mips") == 0)
5256 return idt_little_breakpoint;
5257 else if (strcmp (target_shortname, "ddb") == 0
5258 || strcmp (target_shortname, "pmon") == 0
5259 || strcmp (target_shortname, "lsi") == 0)
5260 return pmon_little_breakpoint;
5262 return little_breakpoint;
5267 /* If PC is in a mips16 call or return stub, return the address of the target
5268 PC, which is either the callee or the caller. There are several
5269 cases which must be handled:
5271 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5272 target PC is in $31 ($ra).
5273 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5274 and the target PC is in $2.
5275 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5276 before the jal instruction, this is effectively a call stub
5277 and the the target PC is in $2. Otherwise this is effectively
5278 a return stub and the target PC is in $18.
5280 See the source code for the stubs in gcc/config/mips/mips16.S for
5283 This function implements the SKIP_TRAMPOLINE_CODE macro.
5287 mips_skip_stub (CORE_ADDR pc)
5290 CORE_ADDR start_addr;
5292 /* Find the starting address and name of the function containing the PC. */
5293 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5296 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5297 target PC is in $31 ($ra). */
5298 if (strcmp (name, "__mips16_ret_sf") == 0
5299 || strcmp (name, "__mips16_ret_df") == 0)
5300 return read_signed_register (RA_REGNUM);
5302 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5304 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5305 and the target PC is in $2. */
5306 if (name[19] >= '0' && name[19] <= '9')
5307 return read_signed_register (2);
5309 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5310 before the jal instruction, this is effectively a call stub
5311 and the the target PC is in $2. Otherwise this is effectively
5312 a return stub and the target PC is in $18. */
5313 else if (name[19] == 's' || name[19] == 'd')
5315 if (pc == start_addr)
5317 /* Check if the target of the stub is a compiler-generated
5318 stub. Such a stub for a function bar might have a name
5319 like __fn_stub_bar, and might look like this:
5324 la $1,bar (becomes a lui/addiu pair)
5326 So scan down to the lui/addi and extract the target
5327 address from those two instructions. */
5329 CORE_ADDR target_pc = read_signed_register (2);
5333 /* See if the name of the target function is __fn_stub_*. */
5334 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
5336 if (strncmp (name, "__fn_stub_", 10) != 0
5337 && strcmp (name, "etext") != 0
5338 && strcmp (name, "_etext") != 0)
5341 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5342 The limit on the search is arbitrarily set to 20
5343 instructions. FIXME. */
5344 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5346 inst = mips_fetch_instruction (target_pc);
5347 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5348 pc = (inst << 16) & 0xffff0000; /* high word */
5349 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5350 return pc | (inst & 0xffff); /* low word */
5353 /* Couldn't find the lui/addui pair, so return stub address. */
5357 /* This is the 'return' part of a call stub. The return
5358 address is in $r18. */
5359 return read_signed_register (18);
5362 return 0; /* not a stub */
5366 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5367 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5370 mips_in_call_stub (CORE_ADDR pc, char *name)
5372 CORE_ADDR start_addr;
5374 /* Find the starting address of the function containing the PC. If the
5375 caller didn't give us a name, look it up at the same time. */
5376 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
5379 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5381 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5382 if (name[19] >= '0' && name[19] <= '9')
5384 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5385 before the jal instruction, this is effectively a call stub. */
5386 else if (name[19] == 's' || name[19] == 'd')
5387 return pc == start_addr;
5390 return 0; /* not a stub */
5394 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5395 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5398 mips_in_return_stub (CORE_ADDR pc, char *name)
5400 CORE_ADDR start_addr;
5402 /* Find the starting address of the function containing the PC. */
5403 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5406 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5407 if (strcmp (name, "__mips16_ret_sf") == 0
5408 || strcmp (name, "__mips16_ret_df") == 0)
5411 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5412 i.e. after the jal instruction, this is effectively a return stub. */
5413 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5414 && (name[19] == 's' || name[19] == 'd')
5415 && pc != start_addr)
5418 return 0; /* not a stub */
5422 /* Return non-zero if the PC is in a library helper function that should
5423 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5426 mips_ignore_helper (CORE_ADDR pc)
5430 /* Find the starting address and name of the function containing the PC. */
5431 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5434 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5435 that we want to ignore. */
5436 return (strcmp (name, "__mips16_ret_sf") == 0
5437 || strcmp (name, "__mips16_ret_df") == 0);
5441 /* Return a location where we can set a breakpoint that will be hit
5442 when an inferior function call returns. This is normally the
5443 program's entry point. Executables that don't have an entry
5444 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
5445 whose address is the location where the breakpoint should be placed. */
5448 mips_call_dummy_address (void)
5450 struct minimal_symbol *sym;
5452 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
5454 return SYMBOL_VALUE_ADDRESS (sym);
5456 return entry_point_address ();
5460 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5461 the register stored on the stack (32) is different to its real raw
5462 size (64). The below ensures that registers are fetched from the
5463 stack using their ABI size and then stored into the RAW_BUFFER
5464 using their raw size.
5466 The alternative to adding this function would be to add an ABI
5467 macro - REGISTER_STACK_SIZE(). */
5470 mips_get_saved_register (char *raw_buffer,
5473 struct frame_info *frame,
5475 enum lval_type *lvalp)
5478 enum lval_type lvalx;
5482 if (!target_has_registers)
5483 error ("No registers.");
5485 /* Make certain that all needed parameters are present. */
5490 if (optimizedp == NULL)
5491 optimizedp = &optimizedx;
5492 frame_register_unwind (get_next_frame (frame), regnum, optimizedp, lvalp,
5493 addrp, &realnum, raw_buffer);
5494 /* FIXME: cagney/2002-09-13: This is just so bad. The MIPS should
5495 have a pseudo register range that correspons to the ABI's, rather
5496 than the ISA's, view of registers. These registers would then
5497 implicitly describe their size and hence could be used without
5498 the below munging. */
5499 if ((*lvalp) == lval_memory)
5501 if (raw_buffer != NULL)
5505 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
5507 LONGEST val = read_memory_integer ((*addrp), MIPS_SAVED_REGSIZE);
5508 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
5514 /* Immediately after a function call, return the saved pc.
5515 Can't always go through the frames for this because on some machines
5516 the new frame is not set up until the new function executes
5517 some instructions. */
5520 mips_saved_pc_after_call (struct frame_info *frame)
5522 return read_signed_register (RA_REGNUM);
5526 /* Convert a dbx stab register number (from `r' declaration) to a gdb
5530 mips_stab_reg_to_regnum (int num)
5535 return num + FP0_REGNUM - 38;
5538 /* Convert a ecoff register number to a gdb REGNUM */
5541 mips_ecoff_reg_to_regnum (int num)
5546 return num + FP0_REGNUM - 32;
5549 /* Convert an integer into an address. By first converting the value
5550 into a pointer and then extracting it signed, the address is
5551 guarenteed to be correctly sign extended. */
5554 mips_integer_to_address (struct type *type, void *buf)
5556 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5557 LONGEST val = unpack_long (type, buf);
5558 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5559 return extract_signed_integer (tmp,
5560 TYPE_LENGTH (builtin_type_void_data_ptr));
5564 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5566 enum mips_abi *abip = (enum mips_abi *) obj;
5567 const char *name = bfd_get_section_name (abfd, sect);
5569 if (*abip != MIPS_ABI_UNKNOWN)
5572 if (strncmp (name, ".mdebug.", 8) != 0)
5575 if (strcmp (name, ".mdebug.abi32") == 0)
5576 *abip = MIPS_ABI_O32;
5577 else if (strcmp (name, ".mdebug.abiN32") == 0)
5578 *abip = MIPS_ABI_N32;
5579 else if (strcmp (name, ".mdebug.abi64") == 0)
5580 *abip = MIPS_ABI_N64;
5581 else if (strcmp (name, ".mdebug.abiO64") == 0)
5582 *abip = MIPS_ABI_O64;
5583 else if (strcmp (name, ".mdebug.eabi32") == 0)
5584 *abip = MIPS_ABI_EABI32;
5585 else if (strcmp (name, ".mdebug.eabi64") == 0)
5586 *abip = MIPS_ABI_EABI64;
5588 warning ("unsupported ABI %s.", name + 8);
5591 static enum mips_abi
5592 global_mips_abi (void)
5596 for (i = 0; mips_abi_strings[i] != NULL; i++)
5597 if (mips_abi_strings[i] == mips_abi_string)
5598 return (enum mips_abi) i;
5600 internal_error (__FILE__, __LINE__,
5601 "unknown ABI string");
5604 static struct gdbarch *
5605 mips_gdbarch_init (struct gdbarch_info info,
5606 struct gdbarch_list *arches)
5608 static LONGEST mips_call_dummy_words[] =
5610 struct gdbarch *gdbarch;
5611 struct gdbarch_tdep *tdep;
5613 enum mips_abi mips_abi, found_abi, wanted_abi;
5615 /* Reset the disassembly info, in case it was set to something
5617 tm_print_insn_info.flavour = bfd_target_unknown_flavour;
5618 tm_print_insn_info.arch = bfd_arch_unknown;
5619 tm_print_insn_info.mach = 0;
5625 /* First of all, extract the elf_flags, if available. */
5626 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5627 elf_flags = elf_elfheader (info.abfd)->e_flags;
5630 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5631 switch ((elf_flags & EF_MIPS_ABI))
5633 case E_MIPS_ABI_O32:
5634 mips_abi = MIPS_ABI_O32;
5636 case E_MIPS_ABI_O64:
5637 mips_abi = MIPS_ABI_O64;
5639 case E_MIPS_ABI_EABI32:
5640 mips_abi = MIPS_ABI_EABI32;
5642 case E_MIPS_ABI_EABI64:
5643 mips_abi = MIPS_ABI_EABI64;
5646 if ((elf_flags & EF_MIPS_ABI2))
5647 mips_abi = MIPS_ABI_N32;
5649 mips_abi = MIPS_ABI_UNKNOWN;
5653 /* GCC creates a pseudo-section whose name describes the ABI. */
5654 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5655 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
5657 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5658 Use the ABI from the last architecture if there is one. */
5659 if (info.abfd == NULL && arches != NULL)
5660 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5662 /* Try the architecture for any hint of the correct ABI. */
5663 if (mips_abi == MIPS_ABI_UNKNOWN
5664 && info.bfd_arch_info != NULL
5665 && info.bfd_arch_info->arch == bfd_arch_mips)
5667 switch (info.bfd_arch_info->mach)
5669 case bfd_mach_mips3900:
5670 mips_abi = MIPS_ABI_EABI32;
5672 case bfd_mach_mips4100:
5673 case bfd_mach_mips5000:
5674 mips_abi = MIPS_ABI_EABI64;
5676 case bfd_mach_mips8000:
5677 case bfd_mach_mips10000:
5678 /* On Irix, ELF64 executables use the N64 ABI. The
5679 pseudo-sections which describe the ABI aren't present
5680 on IRIX. (Even for executables created by gcc.) */
5681 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5682 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5683 mips_abi = MIPS_ABI_N64;
5685 mips_abi = MIPS_ABI_N32;
5690 if (mips_abi == MIPS_ABI_UNKNOWN)
5691 mips_abi = MIPS_ABI_O32;
5693 /* Now that we have found what the ABI for this binary would be,
5694 check whether the user is overriding it. */
5695 found_abi = mips_abi;
5696 wanted_abi = global_mips_abi ();
5697 if (wanted_abi != MIPS_ABI_UNKNOWN)
5698 mips_abi = wanted_abi;
5702 fprintf_unfiltered (gdb_stdlog,
5703 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5705 fprintf_unfiltered (gdb_stdlog,
5706 "mips_gdbarch_init: mips_abi = %d\n",
5708 fprintf_unfiltered (gdb_stdlog,
5709 "mips_gdbarch_init: found_mips_abi = %d\n",
5713 /* try to find a pre-existing architecture */
5714 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5716 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5718 /* MIPS needs to be pedantic about which ABI the object is
5720 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5722 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5724 return arches->gdbarch;
5727 /* Need a new architecture. Fill in a target specific vector. */
5728 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5729 gdbarch = gdbarch_alloc (&info, tdep);
5730 tdep->elf_flags = elf_flags;
5732 /* Initially set everything according to the default ABI/ISA. */
5733 set_gdbarch_short_bit (gdbarch, 16);
5734 set_gdbarch_int_bit (gdbarch, 32);
5735 set_gdbarch_float_bit (gdbarch, 32);
5736 set_gdbarch_double_bit (gdbarch, 64);
5737 set_gdbarch_long_double_bit (gdbarch, 64);
5738 set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size);
5739 set_gdbarch_max_register_raw_size (gdbarch, 8);
5740 set_gdbarch_max_register_virtual_size (gdbarch, 8);
5741 tdep->found_abi = found_abi;
5742 tdep->mips_abi = mips_abi;
5744 set_gdbarch_elf_make_msymbol_special (gdbarch,
5745 mips_elf_make_msymbol_special);
5747 if (info.osabi == GDB_OSABI_IRIX)
5748 set_gdbarch_num_regs (gdbarch, 71);
5750 set_gdbarch_num_regs (gdbarch, 90);
5755 set_gdbarch_push_arguments (gdbarch, mips_o32_push_arguments);
5756 set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value);
5757 set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value);
5758 tdep->mips_default_saved_regsize = 4;
5759 tdep->mips_default_stack_argsize = 4;
5760 tdep->mips_fp_register_double = 0;
5761 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5762 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5763 tdep->gdb_target_is_mips64 = 0;
5764 tdep->default_mask_address_p = 0;
5765 set_gdbarch_long_bit (gdbarch, 32);
5766 set_gdbarch_ptr_bit (gdbarch, 32);
5767 set_gdbarch_long_long_bit (gdbarch, 64);
5768 set_gdbarch_reg_struct_has_addr (gdbarch,
5769 mips_o32_reg_struct_has_addr);
5770 set_gdbarch_use_struct_convention (gdbarch,
5771 mips_o32_use_struct_convention);
5774 set_gdbarch_push_arguments (gdbarch, mips_o64_push_arguments);
5775 set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value);
5776 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value);
5777 tdep->mips_default_saved_regsize = 8;
5778 tdep->mips_default_stack_argsize = 8;
5779 tdep->mips_fp_register_double = 1;
5780 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5781 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5782 tdep->gdb_target_is_mips64 = 1;
5783 tdep->default_mask_address_p = 0;
5784 set_gdbarch_long_bit (gdbarch, 32);
5785 set_gdbarch_ptr_bit (gdbarch, 32);
5786 set_gdbarch_long_long_bit (gdbarch, 64);
5787 set_gdbarch_reg_struct_has_addr (gdbarch,
5788 mips_o32_reg_struct_has_addr);
5789 set_gdbarch_use_struct_convention (gdbarch,
5790 mips_o32_use_struct_convention);
5792 case MIPS_ABI_EABI32:
5793 set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments);
5794 set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
5795 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5796 tdep->mips_default_saved_regsize = 4;
5797 tdep->mips_default_stack_argsize = 4;
5798 tdep->mips_fp_register_double = 0;
5799 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5800 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5801 tdep->gdb_target_is_mips64 = 0;
5802 tdep->default_mask_address_p = 0;
5803 set_gdbarch_long_bit (gdbarch, 32);
5804 set_gdbarch_ptr_bit (gdbarch, 32);
5805 set_gdbarch_long_long_bit (gdbarch, 64);
5806 set_gdbarch_reg_struct_has_addr (gdbarch,
5807 mips_eabi_reg_struct_has_addr);
5808 set_gdbarch_use_struct_convention (gdbarch,
5809 mips_eabi_use_struct_convention);
5811 case MIPS_ABI_EABI64:
5812 set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments);
5813 set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
5814 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5815 tdep->mips_default_saved_regsize = 8;
5816 tdep->mips_default_stack_argsize = 8;
5817 tdep->mips_fp_register_double = 1;
5818 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5819 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5820 tdep->gdb_target_is_mips64 = 1;
5821 tdep->default_mask_address_p = 0;
5822 set_gdbarch_long_bit (gdbarch, 64);
5823 set_gdbarch_ptr_bit (gdbarch, 64);
5824 set_gdbarch_long_long_bit (gdbarch, 64);
5825 set_gdbarch_reg_struct_has_addr (gdbarch,
5826 mips_eabi_reg_struct_has_addr);
5827 set_gdbarch_use_struct_convention (gdbarch,
5828 mips_eabi_use_struct_convention);
5831 set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments);
5832 set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value);
5833 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5834 tdep->mips_default_saved_regsize = 8;
5835 tdep->mips_default_stack_argsize = 8;
5836 tdep->mips_fp_register_double = 1;
5837 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5838 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5839 tdep->gdb_target_is_mips64 = 1;
5840 tdep->default_mask_address_p = 0;
5841 set_gdbarch_long_bit (gdbarch, 32);
5842 set_gdbarch_ptr_bit (gdbarch, 32);
5843 set_gdbarch_long_long_bit (gdbarch, 64);
5845 /* Set up the disassembler info, so that we get the right
5846 register names from libopcodes. */
5847 tm_print_insn_info.flavour = bfd_target_elf_flavour;
5848 tm_print_insn_info.arch = bfd_arch_mips;
5849 if (info.bfd_arch_info != NULL
5850 && info.bfd_arch_info->arch == bfd_arch_mips
5851 && info.bfd_arch_info->mach)
5852 tm_print_insn_info.mach = info.bfd_arch_info->mach;
5854 tm_print_insn_info.mach = bfd_mach_mips8000;
5856 set_gdbarch_use_struct_convention (gdbarch,
5857 mips_n32n64_use_struct_convention);
5858 set_gdbarch_reg_struct_has_addr (gdbarch,
5859 mips_n32n64_reg_struct_has_addr);
5862 set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments);
5863 set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value);
5864 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5865 tdep->mips_default_saved_regsize = 8;
5866 tdep->mips_default_stack_argsize = 8;
5867 tdep->mips_fp_register_double = 1;
5868 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5869 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5870 tdep->gdb_target_is_mips64 = 1;
5871 tdep->default_mask_address_p = 0;
5872 set_gdbarch_long_bit (gdbarch, 64);
5873 set_gdbarch_ptr_bit (gdbarch, 64);
5874 set_gdbarch_long_long_bit (gdbarch, 64);
5876 /* Set up the disassembler info, so that we get the right
5877 register names from libopcodes. */
5878 tm_print_insn_info.flavour = bfd_target_elf_flavour;
5879 tm_print_insn_info.arch = bfd_arch_mips;
5880 if (info.bfd_arch_info != NULL
5881 && info.bfd_arch_info->arch == bfd_arch_mips
5882 && info.bfd_arch_info->mach)
5883 tm_print_insn_info.mach = info.bfd_arch_info->mach;
5885 tm_print_insn_info.mach = bfd_mach_mips8000;
5887 set_gdbarch_use_struct_convention (gdbarch,
5888 mips_n32n64_use_struct_convention);
5889 set_gdbarch_reg_struct_has_addr (gdbarch,
5890 mips_n32n64_reg_struct_has_addr);
5893 internal_error (__FILE__, __LINE__,
5894 "unknown ABI in switch");
5897 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5898 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5901 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5902 flag in object files because to do so would make it impossible to
5903 link with libraries compiled without "-gp32". This is
5904 unnecessarily restrictive.
5906 We could solve this problem by adding "-gp32" multilibs to gcc,
5907 but to set this flag before gcc is built with such multilibs will
5908 break too many systems.''
5910 But even more unhelpfully, the default linker output target for
5911 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5912 for 64-bit programs - you need to change the ABI to change this,
5913 and not all gcc targets support that currently. Therefore using
5914 this flag to detect 32-bit mode would do the wrong thing given
5915 the current gcc - it would make GDB treat these 64-bit programs
5916 as 32-bit programs by default. */
5918 /* enable/disable the MIPS FPU */
5919 if (!mips_fpu_type_auto)
5920 tdep->mips_fpu_type = mips_fpu_type;
5921 else if (info.bfd_arch_info != NULL
5922 && info.bfd_arch_info->arch == bfd_arch_mips)
5923 switch (info.bfd_arch_info->mach)
5925 case bfd_mach_mips3900:
5926 case bfd_mach_mips4100:
5927 case bfd_mach_mips4111:
5928 tdep->mips_fpu_type = MIPS_FPU_NONE;
5930 case bfd_mach_mips4650:
5931 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
5934 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5938 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5940 /* MIPS version of register names. NOTE: At present the MIPS
5941 register name management is part way between the old -
5942 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5943 Further work on it is required. */
5944 /* NOTE: many targets (esp. embedded) do not go thru the
5945 gdbarch_register_name vector at all, instead bypassing it
5946 by defining REGISTER_NAMES. */
5947 set_gdbarch_register_name (gdbarch, mips_register_name);
5948 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5949 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
5950 set_gdbarch_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */
5951 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5952 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
5954 /* Add/remove bits from an address. The MIPS needs be careful to
5955 ensure that all 32 bit addresses are sign extended to 64 bits. */
5956 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5958 /* There's a mess in stack frame creation. See comments in
5959 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
5960 set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
5961 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_noop);
5963 /* Map debug register numbers onto internal register numbers. */
5964 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5965 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum);
5967 /* Initialize a frame */
5968 set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
5969 set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs);
5971 /* MIPS version of CALL_DUMMY */
5973 set_gdbarch_call_dummy_p (gdbarch, 1);
5974 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
5975 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
5976 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
5977 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
5978 set_gdbarch_pop_frame (gdbarch, mips_pop_frame);
5979 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
5980 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
5981 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
5982 set_gdbarch_call_dummy_length (gdbarch, 0);
5983 set_gdbarch_fix_call_dummy (gdbarch, mips_fix_call_dummy);
5984 set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
5985 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
5986 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
5987 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5988 set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
5989 set_gdbarch_register_convertible (gdbarch, mips_register_convertible);
5990 set_gdbarch_register_convert_to_virtual (gdbarch,
5991 mips_register_convert_to_virtual);
5992 set_gdbarch_register_convert_to_raw (gdbarch,
5993 mips_register_convert_to_raw);
5995 set_gdbarch_frame_chain (gdbarch, mips_frame_chain);
5996 set_gdbarch_frameless_function_invocation (gdbarch,
5997 generic_frameless_function_invocation_not);
5998 set_gdbarch_frame_saved_pc (gdbarch, mips_frame_saved_pc);
5999 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
6000 set_gdbarch_frame_args_skip (gdbarch, 0);
6002 set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
6004 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6005 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
6006 set_gdbarch_decr_pc_after_break (gdbarch, 0);
6008 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
6009 set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
6011 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
6012 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
6013 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
6015 set_gdbarch_function_start_offset (gdbarch, 0);
6017 /* There are MIPS targets which do not yet use this since they still
6018 define REGISTER_VIRTUAL_TYPE. */
6019 set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type);
6020 set_gdbarch_register_virtual_size (gdbarch, generic_register_size);
6022 set_gdbarch_deprecated_do_registers_info (gdbarch, mips_do_registers_info);
6023 set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp);
6025 /* Hook in OS ABI-specific overrides, if they have been registered. */
6026 gdbarch_init_osabi (info, gdbarch);
6028 set_gdbarch_store_struct_return (gdbarch, mips_store_struct_return);
6029 set_gdbarch_extract_struct_value_address (gdbarch,
6030 mips_extract_struct_value_address);
6032 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
6034 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
6035 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
6041 mips_abi_update (char *ignore_args, int from_tty,
6042 struct cmd_list_element *c)
6044 struct gdbarch_info info;
6046 /* Force the architecture to update, and (if it's a MIPS architecture)
6047 mips_gdbarch_init will take care of the rest. */
6048 gdbarch_info_init (&info);
6049 gdbarch_update_p (info);
6053 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
6055 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
6059 int ef_mips_32bitmode;
6060 /* determine the ISA */
6061 switch (tdep->elf_flags & EF_MIPS_ARCH)
6079 /* determine the size of a pointer */
6080 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6081 fprintf_unfiltered (file,
6082 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6084 fprintf_unfiltered (file,
6085 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6087 fprintf_unfiltered (file,
6088 "mips_dump_tdep: ef_mips_arch = %d\n",
6090 fprintf_unfiltered (file,
6091 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6093 mips_abi_strings[tdep->mips_abi]);
6094 fprintf_unfiltered (file,
6095 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6096 mips_mask_address_p (),
6097 tdep->default_mask_address_p);
6099 fprintf_unfiltered (file,
6100 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6101 FP_REGISTER_DOUBLE);
6102 fprintf_unfiltered (file,
6103 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6104 MIPS_DEFAULT_FPU_TYPE,
6105 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6106 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6107 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6109 fprintf_unfiltered (file,
6110 "mips_dump_tdep: MIPS_EABI = %d\n",
6112 fprintf_unfiltered (file,
6113 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6114 MIPS_LAST_FP_ARG_REGNUM,
6115 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
6116 fprintf_unfiltered (file,
6117 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6119 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
6120 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6121 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6123 fprintf_unfiltered (file,
6124 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6125 MIPS_DEFAULT_SAVED_REGSIZE);
6126 fprintf_unfiltered (file,
6127 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6128 FP_REGISTER_DOUBLE);
6129 fprintf_unfiltered (file,
6130 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6131 MIPS_DEFAULT_STACK_ARGSIZE);
6132 fprintf_unfiltered (file,
6133 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6134 MIPS_STACK_ARGSIZE);
6135 fprintf_unfiltered (file,
6136 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
6138 fprintf_unfiltered (file,
6139 "mips_dump_tdep: A0_REGNUM = %d\n",
6141 fprintf_unfiltered (file,
6142 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6143 XSTRING (ADDR_BITS_REMOVE(ADDR)));
6144 fprintf_unfiltered (file,
6145 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6146 XSTRING (ATTACH_DETACH));
6147 fprintf_unfiltered (file,
6148 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6150 fprintf_unfiltered (file,
6151 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
6152 fprintf_unfiltered (file,
6153 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6155 fprintf_unfiltered (file,
6156 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6157 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
6158 fprintf_unfiltered (file,
6159 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6160 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
6161 fprintf_unfiltered (file,
6162 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6164 fprintf_unfiltered (file,
6165 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6167 fprintf_unfiltered (file,
6168 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6169 FIRST_EMBED_REGNUM);
6170 fprintf_unfiltered (file,
6171 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6173 fprintf_unfiltered (file,
6174 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6175 GDB_TARGET_IS_MIPS64);
6176 fprintf_unfiltered (file,
6177 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
6179 fprintf_unfiltered (file,
6180 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
6181 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
6182 fprintf_unfiltered (file,
6183 "mips_dump_tdep: HI_REGNUM = %d\n",
6185 fprintf_unfiltered (file,
6186 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
6187 fprintf_unfiltered (file,
6188 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
6189 fprintf_unfiltered (file,
6190 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6191 XSTRING (IGNORE_HELPER_CALL (PC)));
6192 fprintf_unfiltered (file,
6193 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6194 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
6195 fprintf_unfiltered (file,
6196 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6197 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
6198 fprintf_unfiltered (file,
6199 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
6200 fprintf_unfiltered (file,
6201 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6203 fprintf_unfiltered (file,
6204 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
6205 fprintf_unfiltered (file,
6206 "mips_dump_tdep: LO_REGNUM = %d\n",
6208 #ifdef MACHINE_CPROC_FP_OFFSET
6209 fprintf_unfiltered (file,
6210 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6211 MACHINE_CPROC_FP_OFFSET);
6213 #ifdef MACHINE_CPROC_PC_OFFSET
6214 fprintf_unfiltered (file,
6215 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6216 MACHINE_CPROC_PC_OFFSET);
6218 #ifdef MACHINE_CPROC_SP_OFFSET
6219 fprintf_unfiltered (file,
6220 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6221 MACHINE_CPROC_SP_OFFSET);
6223 fprintf_unfiltered (file,
6224 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
6225 fprintf_unfiltered (file,
6226 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
6227 fprintf_unfiltered (file,
6228 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6230 fprintf_unfiltered (file,
6231 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
6232 fprintf_unfiltered (file,
6233 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6234 fprintf_unfiltered (file,
6235 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6236 fprintf_unfiltered (file,
6237 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6239 fprintf_unfiltered (file,
6240 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6241 MIPS_LAST_ARG_REGNUM,
6242 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
6243 fprintf_unfiltered (file,
6244 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6246 fprintf_unfiltered (file,
6247 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6248 fprintf_unfiltered (file,
6249 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6250 MIPS_SAVED_REGSIZE);
6251 fprintf_unfiltered (file,
6252 "mips_dump_tdep: OP_LDFPR = used?\n");
6253 fprintf_unfiltered (file,
6254 "mips_dump_tdep: OP_LDGPR = used?\n");
6255 fprintf_unfiltered (file,
6256 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
6257 fprintf_unfiltered (file,
6258 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
6259 fprintf_unfiltered (file,
6260 "mips_dump_tdep: PRID_REGNUM = %d\n",
6262 fprintf_unfiltered (file,
6263 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
6264 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
6265 fprintf_unfiltered (file,
6266 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6267 fprintf_unfiltered (file,
6268 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6269 fprintf_unfiltered (file,
6270 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6271 fprintf_unfiltered (file,
6272 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6273 fprintf_unfiltered (file,
6274 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6275 fprintf_unfiltered (file,
6276 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6277 fprintf_unfiltered (file,
6278 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6279 fprintf_unfiltered (file,
6280 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6281 fprintf_unfiltered (file,
6282 "mips_dump_tdep: PROC_PC_REG = function?\n");
6283 fprintf_unfiltered (file,
6284 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6285 fprintf_unfiltered (file,
6286 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6287 fprintf_unfiltered (file,
6288 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6289 fprintf_unfiltered (file,
6290 "mips_dump_tdep: PS_REGNUM = %d\n",
6292 fprintf_unfiltered (file,
6293 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
6295 fprintf_unfiltered (file,
6296 "mips_dump_tdep: RA_REGNUM = %d\n",
6298 fprintf_unfiltered (file,
6299 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
6300 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
6301 fprintf_unfiltered (file,
6302 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
6303 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
6304 fprintf_unfiltered (file,
6305 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
6306 fprintf_unfiltered (file,
6307 "mips_dump_tdep: ROUND_DOWN = function?\n");
6308 fprintf_unfiltered (file,
6309 "mips_dump_tdep: ROUND_UP = function?\n");
6311 fprintf_unfiltered (file,
6312 "mips_dump_tdep: SAVED_BYTES = %d\n",
6316 fprintf_unfiltered (file,
6317 "mips_dump_tdep: SAVED_FP = %d\n",
6321 fprintf_unfiltered (file,
6322 "mips_dump_tdep: SAVED_PC = %d\n",
6325 fprintf_unfiltered (file,
6326 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6327 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
6328 fprintf_unfiltered (file,
6329 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6330 fprintf_unfiltered (file,
6331 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6333 fprintf_unfiltered (file,
6334 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6335 SIGFRAME_FPREGSAVE_OFF);
6336 fprintf_unfiltered (file,
6337 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6339 fprintf_unfiltered (file,
6340 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6341 SIGFRAME_REGSAVE_OFF);
6342 fprintf_unfiltered (file,
6343 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6345 fprintf_unfiltered (file,
6346 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6347 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
6348 fprintf_unfiltered (file,
6349 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6350 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
6351 fprintf_unfiltered (file,
6352 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6353 SOFTWARE_SINGLE_STEP_P ());
6354 fprintf_unfiltered (file,
6355 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6356 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6357 #ifdef STACK_END_ADDR
6358 fprintf_unfiltered (file,
6359 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6362 fprintf_unfiltered (file,
6363 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6364 XSTRING (STEP_SKIPS_DELAY (PC)));
6365 fprintf_unfiltered (file,
6366 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6367 STEP_SKIPS_DELAY_P);
6368 fprintf_unfiltered (file,
6369 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6370 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6371 fprintf_unfiltered (file,
6372 "mips_dump_tdep: T9_REGNUM = %d\n",
6374 fprintf_unfiltered (file,
6375 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6376 fprintf_unfiltered (file,
6377 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6378 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
6379 fprintf_unfiltered (file,
6380 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6381 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
6382 fprintf_unfiltered (file,
6383 "mips_dump_tdep: TARGET_MIPS = used?\n");
6384 fprintf_unfiltered (file,
6385 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
6386 XSTRING (TM_PRINT_INSN_MACH));
6388 fprintf_unfiltered (file,
6389 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6390 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6393 fprintf_unfiltered (file,
6394 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6397 #ifdef TRACE_FLAVOR_SIZE
6398 fprintf_unfiltered (file,
6399 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6403 fprintf_unfiltered (file,
6404 "mips_dump_tdep: TRACE_SET # %s\n",
6405 XSTRING (TRACE_SET (X,STATE)));
6407 fprintf_unfiltered (file,
6408 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
6409 #ifdef UNUSED_REGNUM
6410 fprintf_unfiltered (file,
6411 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6414 fprintf_unfiltered (file,
6415 "mips_dump_tdep: V0_REGNUM = %d\n",
6417 fprintf_unfiltered (file,
6418 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6419 (long) VM_MIN_ADDRESS);
6421 fprintf_unfiltered (file,
6422 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
6425 fprintf_unfiltered (file,
6426 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6428 fprintf_unfiltered (file,
6429 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6434 _initialize_mips_tdep (void)
6436 static struct cmd_list_element *mipsfpulist = NULL;
6437 struct cmd_list_element *c;
6439 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
6440 if (MIPS_ABI_LAST + 1
6441 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6442 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6444 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6445 if (!tm_print_insn) /* Someone may have already set it */
6446 tm_print_insn = gdb_print_insn_mips;
6448 /* Add root prefix command for all "set mips"/"show mips" commands */
6449 add_prefix_cmd ("mips", no_class, set_mips_command,
6450 "Various MIPS specific commands.",
6451 &setmipscmdlist, "set mips ", 0, &setlist);
6453 add_prefix_cmd ("mips", no_class, show_mips_command,
6454 "Various MIPS specific commands.",
6455 &showmipscmdlist, "show mips ", 0, &showlist);
6457 /* Allow the user to override the saved register size. */
6458 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6461 &mips_saved_regsize_string, "\
6462 Set size of general purpose registers saved on the stack.\n\
6463 This option can be set to one of:\n\
6464 32 - Force GDB to treat saved GP registers as 32-bit\n\
6465 64 - Force GDB to treat saved GP registers as 64-bit\n\
6466 auto - Allow GDB to use the target's default setting or autodetect the\n\
6467 saved GP register size from information contained in the executable.\n\
6472 /* Allow the user to override the argument stack size. */
6473 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6476 &mips_stack_argsize_string, "\
6477 Set the amount of stack space reserved for each argument.\n\
6478 This option can be set to one of:\n\
6479 32 - Force GDB to allocate 32-bit chunks per argument\n\
6480 64 - Force GDB to allocate 64-bit chunks per argument\n\
6481 auto - Allow GDB to determine the correct setting from the current\n\
6482 target and executable (default)",
6486 /* Allow the user to override the ABI. */
6487 c = add_set_enum_cmd
6488 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6489 "Set the ABI used by this program.\n"
6490 "This option can be set to one of:\n"
6491 " auto - the default ABI associated with the current binary\n"
6499 add_show_from_set (c, &showmipscmdlist);
6500 set_cmd_sfunc (c, mips_abi_update);
6502 /* Let the user turn off floating point and set the fence post for
6503 heuristic_proc_start. */
6505 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6506 "Set use of MIPS floating-point coprocessor.",
6507 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6508 add_cmd ("single", class_support, set_mipsfpu_single_command,
6509 "Select single-precision MIPS floating-point coprocessor.",
6511 add_cmd ("double", class_support, set_mipsfpu_double_command,
6512 "Select double-precision MIPS floating-point coprocessor.",
6514 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6515 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6516 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6517 add_cmd ("none", class_support, set_mipsfpu_none_command,
6518 "Select no MIPS floating-point coprocessor.",
6520 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6521 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6522 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6523 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6524 "Select MIPS floating-point coprocessor automatically.",
6526 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6527 "Show current use of MIPS floating-point coprocessor target.",
6530 /* We really would like to have both "0" and "unlimited" work, but
6531 command.c doesn't deal with that. So make it a var_zinteger
6532 because the user can always use "999999" or some such for unlimited. */
6533 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6534 (char *) &heuristic_fence_post,
6536 Set the distance searched for the start of a function.\n\
6537 If you are debugging a stripped executable, GDB needs to search through the\n\
6538 program for the start of a function. This command sets the distance of the\n\
6539 search. The only need to set it is when debugging a stripped executable.",
6541 /* We need to throw away the frame cache when we set this, since it
6542 might change our ability to get backtraces. */
6543 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
6544 add_show_from_set (c, &showlist);
6546 /* Allow the user to control whether the upper bits of 64-bit
6547 addresses should be zeroed. */
6548 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6549 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6550 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6551 allow GDB to determine the correct value.\n", "\
6552 Show zeroing of upper 32 bits of 64-bit addresses.",
6553 NULL, show_mask_address,
6554 &setmipscmdlist, &showmipscmdlist);
6556 /* Allow the user to control the size of 32 bit registers within the
6557 raw remote packet. */
6558 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6561 (char *)&mips64_transfers_32bit_regs_p, "\
6562 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6563 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6564 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6565 64 bits for others. Use \"off\" to disable compatibility mode",
6569 /* Debug this files internals. */
6570 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6571 &mips_debug, "Set mips debugging.\n\
6572 When non-zero, mips specific debugging is enabled.", &setdebuglist),