1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
58 static const struct objfile_data *mips_pdr_data;
60 static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off);
61 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE = 4,
72 MIPS_FPU_DOUBLE_REGSIZE = 8
76 static const char *mips_abi_string;
78 static const char *mips_abi_strings[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto[] = "auto";
100 static const char size_32[] = "32";
101 static const char size_64[] = "64";
103 static const char *size_enums[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE /* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto = 1;
124 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
126 static int mips_debug = 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi;
136 enum mips_abi found_abi;
137 enum mips_fpu_type mips_fpu_type;
138 int mips_last_arg_regnum;
139 int mips_last_fp_arg_regnum;
140 int default_mask_address_p;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum *regnum;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names;
152 const struct mips_regnum *
153 mips_regnum (struct gdbarch *gdbarch)
155 return gdbarch_tdep (gdbarch)->regnum;
159 mips_fpa0_regnum (struct gdbarch *gdbarch)
161 return mips_regnum (gdbarch)->fp0 + 12;
164 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
165 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
167 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
169 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
171 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
173 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
174 functions to test, set, or clear bit 0 of addresses. */
177 is_mips16_addr (CORE_ADDR addr)
183 make_mips16_addr (CORE_ADDR addr)
189 unmake_mips16_addr (CORE_ADDR addr)
191 return ((addr) & ~1);
194 /* Return the contents of register REGNUM as a signed integer. */
197 read_signed_register (int regnum)
199 void *buf = alloca (register_size (current_gdbarch, regnum));
200 deprecated_read_register_gen (regnum, buf);
201 return (extract_signed_integer
202 (buf, register_size (current_gdbarch, regnum)));
206 read_signed_register_pid (int regnum, ptid_t ptid)
211 if (ptid_equal (ptid, inferior_ptid))
212 return read_signed_register (regnum);
214 save_ptid = inferior_ptid;
216 inferior_ptid = ptid;
218 retval = read_signed_register (regnum);
220 inferior_ptid = save_ptid;
225 /* Return the MIPS ABI associated with GDBARCH. */
227 mips_abi (struct gdbarch *gdbarch)
229 return gdbarch_tdep (gdbarch)->mips_abi;
233 mips_isa_regsize (struct gdbarch *gdbarch)
235 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
236 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
239 /* Return the currently configured (or set) saved register size. */
241 static const char *mips_abi_regsize_string = size_auto;
244 mips_abi_regsize (struct gdbarch *gdbarch)
246 if (mips_abi_regsize_string == size_auto)
247 switch (mips_abi (gdbarch))
249 case MIPS_ABI_EABI32:
255 case MIPS_ABI_EABI64:
257 case MIPS_ABI_UNKNOWN:
260 internal_error (__FILE__, __LINE__, "bad switch");
262 else if (mips_abi_regsize_string == size_64)
264 else /* if (mips_abi_regsize_string == size_32) */
268 /* Functions for setting and testing a bit in a minimal symbol that
269 marks it as 16-bit function. The MSB of the minimal symbol's
270 "info" field is used for this purpose.
272 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
273 i.e. refers to a 16-bit function, and sets a "special" bit in a
274 minimal symbol to mark it as a 16-bit function
276 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
279 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
281 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
283 MSYMBOL_INFO (msym) = (char *)
284 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
285 SYMBOL_VALUE_ADDRESS (msym) |= 1;
290 msymbol_is_special (struct minimal_symbol *msym)
292 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
295 /* XFER a value from the big/little/left end of the register.
296 Depending on the size of the value it might occupy the entire
297 register or just part of it. Make an allowance for this, aligning
298 things accordingly. */
301 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
302 enum bfd_endian endian, bfd_byte * in,
303 const bfd_byte * out, int buf_offset)
306 gdb_assert (reg_num >= NUM_REGS);
307 /* Need to transfer the left or right part of the register, based on
308 the targets byte order. */
312 reg_offset = register_size (current_gdbarch, reg_num) - length;
314 case BFD_ENDIAN_LITTLE:
317 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
321 internal_error (__FILE__, __LINE__, "bad switch");
324 fprintf_unfiltered (gdb_stderr,
325 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
326 reg_num, reg_offset, buf_offset, length);
327 if (mips_debug && out != NULL)
330 fprintf_unfiltered (gdb_stdlog, "out ");
331 for (i = 0; i < length; i++)
332 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
335 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
338 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
340 if (mips_debug && in != NULL)
343 fprintf_unfiltered (gdb_stdlog, "in ");
344 for (i = 0; i < length; i++)
345 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
348 fprintf_unfiltered (gdb_stdlog, "\n");
351 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
352 compatiblity mode. A return value of 1 means that we have
353 physical 64-bit registers, but should treat them as 32-bit registers. */
356 mips2_fp_compat (void)
358 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
360 if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) ==
365 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
366 in all the places we deal with FP registers. PR gdb/413. */
367 /* Otherwise check the FR bit in the status register - it controls
368 the FP compatiblity mode. If it is clear we are in compatibility
370 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
377 /* The amount of space reserved on the stack for registers. This is
378 different to MIPS_ABI_REGSIZE as it determines the alignment of
379 data allocated after the registers have run out. */
381 static const char *mips_stack_argsize_string = size_auto;
384 mips_stack_argsize (struct gdbarch *gdbarch)
386 if (mips_stack_argsize_string == size_auto)
387 return mips_abi_regsize (gdbarch);
388 else if (mips_stack_argsize_string == size_64)
390 else /* if (mips_stack_argsize_string == size_32) */
394 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
396 static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR,
397 struct frame_info *, int);
399 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
401 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
403 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
405 static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc,
406 struct frame_info *next_frame,
409 static CORE_ADDR after_prologue (CORE_ADDR pc,
410 mips_extra_func_info_t proc_desc);
412 static struct type *mips_float_register_type (void);
413 static struct type *mips_double_register_type (void);
415 /* The list of available "set mips " and "show mips " commands */
417 static struct cmd_list_element *setmipscmdlist = NULL;
418 static struct cmd_list_element *showmipscmdlist = NULL;
420 /* Integer registers 0 thru 31 are handled explicitly by
421 mips_register_name(). Processor specific registers 32 and above
422 are listed in the followign tables. */
425 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
429 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
430 "sr", "lo", "hi", "bad", "cause", "pc",
431 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
432 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
433 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
434 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
435 "fsr", "fir", "" /*"fp" */ , "",
436 "", "", "", "", "", "", "", "",
437 "", "", "", "", "", "", "", "",
440 /* Names of IDT R3041 registers. */
442 static const char *mips_r3041_reg_names[] = {
443 "sr", "lo", "hi", "bad", "cause", "pc",
444 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
445 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
446 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
447 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
448 "fsr", "fir", "", /*"fp" */ "",
449 "", "", "bus", "ccfg", "", "", "", "",
450 "", "", "port", "cmp", "", "", "epc", "prid",
453 /* Names of tx39 registers. */
455 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
456 "sr", "lo", "hi", "bad", "cause", "pc",
457 "", "", "", "", "", "", "", "",
458 "", "", "", "", "", "", "", "",
459 "", "", "", "", "", "", "", "",
460 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
463 "", "", "config", "cache", "debug", "depc", "epc", ""
466 /* Names of IRIX registers. */
467 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
468 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
469 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
470 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
471 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
472 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
476 /* Return the name of the register corresponding to REGNO. */
478 mips_register_name (int regno)
480 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
481 /* GPR names for all ABIs other than n32/n64. */
482 static char *mips_gpr_names[] = {
483 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
484 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
485 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
486 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
489 /* GPR names for n32 and n64 ABIs. */
490 static char *mips_n32_n64_gpr_names[] = {
491 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
492 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
493 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
494 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
497 enum mips_abi abi = mips_abi (current_gdbarch);
499 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
500 don't make the raw register names visible. */
501 int rawnum = regno % NUM_REGS;
502 if (regno < NUM_REGS)
505 /* The MIPS integer registers are always mapped from 0 to 31. The
506 names of the registers (which reflects the conventions regarding
507 register use) vary depending on the ABI. */
508 if (0 <= rawnum && rawnum < 32)
510 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
511 return mips_n32_n64_gpr_names[rawnum];
513 return mips_gpr_names[rawnum];
515 else if (32 <= rawnum && rawnum < NUM_REGS)
517 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
518 return tdep->mips_processor_reg_names[rawnum - 32];
521 internal_error (__FILE__, __LINE__,
522 "mips_register_name: bad register number %d", rawnum);
525 /* Return the groups that a MIPS register can be categorised into. */
528 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
529 struct reggroup *reggroup)
534 int rawnum = regnum % NUM_REGS;
535 int pseudo = regnum / NUM_REGS;
536 if (reggroup == all_reggroup)
538 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
539 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
540 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
541 (gdbarch), as not all architectures are multi-arch. */
542 raw_p = rawnum < NUM_REGS;
543 if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0')
545 if (reggroup == float_reggroup)
546 return float_p && pseudo;
547 if (reggroup == vector_reggroup)
548 return vector_p && pseudo;
549 if (reggroup == general_reggroup)
550 return (!vector_p && !float_p) && pseudo;
551 /* Save the pseudo registers. Need to make certain that any code
552 extracting register values from a saved register cache also uses
554 if (reggroup == save_reggroup)
555 return raw_p && pseudo;
556 /* Restore the same pseudo register. */
557 if (reggroup == restore_reggroup)
558 return raw_p && pseudo;
562 /* Map the symbol table registers which live in the range [1 *
563 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
564 registers. Take care of alignment and size problems. */
567 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
568 int cookednum, void *buf)
570 int rawnum = cookednum % NUM_REGS;
571 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
572 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
573 regcache_raw_read (regcache, rawnum, buf);
574 else if (register_size (gdbarch, rawnum) >
575 register_size (gdbarch, cookednum))
577 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
578 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
579 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
581 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
584 internal_error (__FILE__, __LINE__, "bad register size");
588 mips_pseudo_register_write (struct gdbarch *gdbarch,
589 struct regcache *regcache, int cookednum,
592 int rawnum = cookednum % NUM_REGS;
593 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
594 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
595 regcache_raw_write (regcache, rawnum, buf);
596 else if (register_size (gdbarch, rawnum) >
597 register_size (gdbarch, cookednum))
599 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
600 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
601 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
603 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
606 internal_error (__FILE__, __LINE__, "bad register size");
609 /* Table to translate MIPS16 register field to actual register number. */
610 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
612 /* Heuristic_proc_start may hunt through the text section for a long
613 time across a 2400 baud serial line. Allows the user to limit this
616 static unsigned int heuristic_fence_post = 0;
618 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
619 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
620 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
621 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
622 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
623 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
624 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
625 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
626 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
627 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
628 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
629 this will corrupt pdr.iline. Fortunately we don't use it. */
630 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
631 #define _PROC_MAGIC_ 0x0F0F0F0F
632 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
633 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
635 struct linked_proc_info
637 struct mips_extra_func_info info;
638 struct linked_proc_info *next;
640 *linked_proc_desc_table = NULL;
642 /* Number of bytes of storage in the actual machine representation for
643 register N. NOTE: This defines the pseudo register type so need to
644 rebuild the architecture vector. */
646 static int mips64_transfers_32bit_regs_p = 0;
649 set_mips64_transfers_32bit_regs (char *args, int from_tty,
650 struct cmd_list_element *c)
652 struct gdbarch_info info;
653 gdbarch_info_init (&info);
654 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
655 instead of relying on globals. Doing that would let generic code
656 handle the search for this specific architecture. */
657 if (!gdbarch_update_p (info))
659 mips64_transfers_32bit_regs_p = 0;
660 error ("32-bit compatibility mode not supported");
664 /* Convert to/from a register and the corresponding memory value. */
667 mips_convert_register_p (int regnum, struct type *type)
669 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
670 && register_size (current_gdbarch, regnum) == 4
671 && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
672 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32
673 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
677 mips_register_to_value (struct frame_info *frame, int regnum,
678 struct type *type, void *to)
680 get_frame_register (frame, regnum + 0, (char *) to + 4);
681 get_frame_register (frame, regnum + 1, (char *) to + 0);
685 mips_value_to_register (struct frame_info *frame, int regnum,
686 struct type *type, const void *from)
688 put_frame_register (frame, regnum + 0, (const char *) from + 4);
689 put_frame_register (frame, regnum + 1, (const char *) from + 0);
692 /* Return the GDB type object for the "standard" data type of data in
696 mips_register_type (struct gdbarch *gdbarch, int regnum)
698 gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS);
699 if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
700 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32)
702 /* The floating-point registers raw, or cooked, always match
703 mips_isa_regsize(), and also map 1:1, byte for byte. */
704 switch (gdbarch_byte_order (gdbarch))
707 if (mips_isa_regsize (gdbarch) == 4)
708 return builtin_type_ieee_single_big;
710 return builtin_type_ieee_double_big;
711 case BFD_ENDIAN_LITTLE:
712 if (mips_isa_regsize (gdbarch) == 4)
713 return builtin_type_ieee_single_little;
715 return builtin_type_ieee_double_little;
716 case BFD_ENDIAN_UNKNOWN:
718 internal_error (__FILE__, __LINE__, "bad switch");
721 else if (regnum < NUM_REGS)
723 /* The raw or ISA registers. These are all sized according to
725 if (mips_isa_regsize (gdbarch) == 4)
726 return builtin_type_int32;
728 return builtin_type_int64;
732 /* The cooked or ABI registers. These are sized according to
733 the ABI (with a few complications). */
734 if (regnum >= (NUM_REGS
735 + mips_regnum (current_gdbarch)->fp_control_status)
736 && regnum <= NUM_REGS + LAST_EMBED_REGNUM)
737 /* The pseudo/cooked view of the embedded registers is always
738 32-bit. The raw view is handled below. */
739 return builtin_type_int32;
740 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
741 /* The target, while possibly using a 64-bit register buffer,
742 is only transfering 32-bits of each integer register.
743 Reflect this in the cooked/pseudo (ABI) register value. */
744 return builtin_type_int32;
745 else if (mips_abi_regsize (gdbarch) == 4)
746 /* The ABI is restricted to 32-bit registers (the ISA could be
748 return builtin_type_int32;
751 return builtin_type_int64;
755 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
760 return read_signed_register (MIPS_SP_REGNUM);
763 /* Should the upper word of 64-bit addresses be zeroed? */
764 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
767 mips_mask_address_p (struct gdbarch_tdep *tdep)
769 switch (mask_address_var)
771 case AUTO_BOOLEAN_TRUE:
773 case AUTO_BOOLEAN_FALSE:
776 case AUTO_BOOLEAN_AUTO:
777 return tdep->default_mask_address_p;
779 internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch");
785 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
787 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
788 switch (mask_address_var)
790 case AUTO_BOOLEAN_TRUE:
791 printf_filtered ("The 32 bit mips address mask is enabled\n");
793 case AUTO_BOOLEAN_FALSE:
794 printf_filtered ("The 32 bit mips address mask is disabled\n");
796 case AUTO_BOOLEAN_AUTO:
798 ("The 32 bit address mask is set automatically. Currently %s\n",
799 mips_mask_address_p (tdep) ? "enabled" : "disabled");
802 internal_error (__FILE__, __LINE__, "show_mask_address: bad switch");
807 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
810 pc_is_mips16 (bfd_vma memaddr)
812 struct minimal_symbol *sym;
814 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
815 if (is_mips16_addr (memaddr))
818 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
819 the high bit of the info field. Use this to decide if the function is
820 MIPS16 or normal MIPS. */
821 sym = lookup_minimal_symbol_by_pc (memaddr);
823 return msymbol_is_special (sym);
828 /* MIPS believes that the PC has a sign extended value. Perhaps the
829 all registers should be sign extended for simplicity? */
832 mips_read_pc (ptid_t ptid)
834 return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid);
838 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
840 return frame_unwind_register_signed (next_frame,
841 NUM_REGS + mips_regnum (gdbarch)->pc);
844 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
845 dummy frame. The frame ID's base needs to match the TOS value
846 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
849 static struct frame_id
850 mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
852 return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM),
853 frame_pc_unwind (next_frame));
857 mips_write_pc (CORE_ADDR pc, ptid_t ptid)
859 write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid);
862 /* This returns the PC of the first inst after the prologue. If we can't
863 find the prologue, then return 0. */
866 after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc)
868 struct symtab_and_line sal;
869 CORE_ADDR func_addr, func_end;
871 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
872 to read the stack pointer from the current machine state, because
873 the current machine state has nothing to do with the information
874 we need from the proc_desc; and the process may or may not exist
877 proc_desc = find_proc_desc (pc, NULL, 0);
881 /* If function is frameless, then we need to do it the hard way. I
882 strongly suspect that frameless always means prologueless... */
883 if (PROC_FRAME_REG (proc_desc) == MIPS_SP_REGNUM
884 && PROC_FRAME_OFFSET (proc_desc) == 0)
888 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
889 return 0; /* Unknown */
891 sal = find_pc_line (func_addr, 0);
893 if (sal.end < func_end)
896 /* The line after the prologue is after the end of the function. In this
897 case, tell the caller to find the prologue the hard way. */
902 /* Decode a MIPS32 instruction that saves a register in the stack, and
903 set the appropriate bit in the general register mask or float register mask
904 to indicate which register is saved. This is a helper function
905 for mips_find_saved_regs. */
908 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
909 unsigned long *float_mask)
913 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
914 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
915 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
917 /* It might be possible to use the instruction to
918 find the offset, rather than the code below which
919 is based on things being in a certain order in the
920 frame, but figuring out what the instruction's offset
921 is relative to might be a little tricky. */
922 reg = (inst & 0x001f0000) >> 16;
923 *gen_mask |= (1 << reg);
925 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
926 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
927 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
930 reg = ((inst & 0x001f0000) >> 16);
931 *float_mask |= (1 << reg);
935 /* Decode a MIPS16 instruction that saves a register in the stack, and
936 set the appropriate bit in the general register or float register mask
937 to indicate which register is saved. This is a helper function
938 for mips_find_saved_regs. */
941 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
943 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
945 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
946 *gen_mask |= (1 << reg);
948 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
950 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
951 *gen_mask |= (1 << reg);
953 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
954 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
955 *gen_mask |= (1 << RA_REGNUM);
959 /* Fetch and return instruction from the specified location. If the PC
960 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
963 mips_fetch_instruction (CORE_ADDR addr)
965 char buf[MIPS_INSTLEN];
969 if (pc_is_mips16 (addr))
971 instlen = MIPS16_INSTLEN;
972 addr = unmake_mips16_addr (addr);
975 instlen = MIPS_INSTLEN;
976 status = deprecated_read_memory_nobpt (addr, buf, instlen);
978 memory_error (status, addr);
979 return extract_unsigned_integer (buf, instlen);
983 mips16_fetch_instruction (CORE_ADDR addr)
985 char buf[MIPS_INSTLEN];
989 instlen = MIPS16_INSTLEN;
990 addr = unmake_mips16_addr (addr);
991 status = deprecated_read_memory_nobpt (addr, buf, instlen);
993 memory_error (status, addr);
994 return extract_unsigned_integer (buf, instlen);
998 mips32_fetch_instruction (CORE_ADDR addr)
1000 char buf[MIPS_INSTLEN];
1003 instlen = MIPS_INSTLEN;
1004 status = deprecated_read_memory_nobpt (addr, buf, instlen);
1006 memory_error (status, addr);
1007 return extract_unsigned_integer (buf, instlen);
1011 /* These the fields of 32 bit mips instructions */
1012 #define mips32_op(x) (x >> 26)
1013 #define itype_op(x) (x >> 26)
1014 #define itype_rs(x) ((x >> 21) & 0x1f)
1015 #define itype_rt(x) ((x >> 16) & 0x1f)
1016 #define itype_immediate(x) (x & 0xffff)
1018 #define jtype_op(x) (x >> 26)
1019 #define jtype_target(x) (x & 0x03ffffff)
1021 #define rtype_op(x) (x >> 26)
1022 #define rtype_rs(x) ((x >> 21) & 0x1f)
1023 #define rtype_rt(x) ((x >> 16) & 0x1f)
1024 #define rtype_rd(x) ((x >> 11) & 0x1f)
1025 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1026 #define rtype_funct(x) (x & 0x3f)
1029 mips32_relative_offset (unsigned long inst)
1032 x = itype_immediate (inst);
1033 if (x & 0x8000) /* sign bit set */
1035 x |= 0xffff0000; /* sign extension */
1041 /* Determine whate to set a single step breakpoint while considering
1042 branch prediction */
1044 mips32_next_pc (CORE_ADDR pc)
1048 inst = mips_fetch_instruction (pc);
1049 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1051 if (itype_op (inst) >> 2 == 5)
1052 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1054 op = (itype_op (inst) & 0x03);
1064 goto greater_branch;
1069 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
1070 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1072 int tf = itype_rt (inst) & 0x01;
1073 int cnum = itype_rt (inst) >> 2;
1075 read_signed_register (mips_regnum (current_gdbarch)->
1077 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
1079 if (((cond >> cnum) & 0x01) == tf)
1080 pc += mips32_relative_offset (inst) + 4;
1085 pc += 4; /* Not a branch, next instruction is easy */
1088 { /* This gets way messy */
1090 /* Further subdivide into SPECIAL, REGIMM and other */
1091 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
1093 case 0: /* SPECIAL */
1094 op = rtype_funct (inst);
1099 /* Set PC to that address */
1100 pc = read_signed_register (rtype_rs (inst));
1106 break; /* end SPECIAL */
1107 case 1: /* REGIMM */
1109 op = itype_rt (inst); /* branch condition */
1114 case 16: /* BLTZAL */
1115 case 18: /* BLTZALL */
1117 if (read_signed_register (itype_rs (inst)) < 0)
1118 pc += mips32_relative_offset (inst) + 4;
1120 pc += 8; /* after the delay slot */
1124 case 17: /* BGEZAL */
1125 case 19: /* BGEZALL */
1126 if (read_signed_register (itype_rs (inst)) >= 0)
1127 pc += mips32_relative_offset (inst) + 4;
1129 pc += 8; /* after the delay slot */
1131 /* All of the other instructions in the REGIMM category */
1136 break; /* end REGIMM */
1141 reg = jtype_target (inst) << 2;
1142 /* Upper four bits get never changed... */
1143 pc = reg + ((pc + 4) & 0xf0000000);
1146 /* FIXME case JALX : */
1149 reg = jtype_target (inst) << 2;
1150 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
1151 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1153 break; /* The new PC will be alternate mode */
1154 case 4: /* BEQ, BEQL */
1156 if (read_signed_register (itype_rs (inst)) ==
1157 read_signed_register (itype_rt (inst)))
1158 pc += mips32_relative_offset (inst) + 4;
1162 case 5: /* BNE, BNEL */
1164 if (read_signed_register (itype_rs (inst)) !=
1165 read_signed_register (itype_rt (inst)))
1166 pc += mips32_relative_offset (inst) + 4;
1170 case 6: /* BLEZ, BLEZL */
1171 if (read_signed_register (itype_rs (inst) <= 0))
1172 pc += mips32_relative_offset (inst) + 4;
1178 greater_branch: /* BGTZ, BGTZL */
1179 if (read_signed_register (itype_rs (inst) > 0))
1180 pc += mips32_relative_offset (inst) + 4;
1187 } /* mips32_next_pc */
1189 /* Decoding the next place to set a breakpoint is irregular for the
1190 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1191 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1192 We dont want to set a single step instruction on the extend instruction
1196 /* Lots of mips16 instruction formats */
1197 /* Predicting jumps requires itype,ritype,i8type
1198 and their extensions extItype,extritype,extI8type
1200 enum mips16_inst_fmts
1202 itype, /* 0 immediate 5,10 */
1203 ritype, /* 1 5,3,8 */
1204 rrtype, /* 2 5,3,3,5 */
1205 rritype, /* 3 5,3,3,5 */
1206 rrrtype, /* 4 5,3,3,3,2 */
1207 rriatype, /* 5 5,3,3,1,4 */
1208 shifttype, /* 6 5,3,3,3,2 */
1209 i8type, /* 7 5,3,8 */
1210 i8movtype, /* 8 5,3,3,5 */
1211 i8mov32rtype, /* 9 5,3,5,3 */
1212 i64type, /* 10 5,3,8 */
1213 ri64type, /* 11 5,3,3,5 */
1214 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1215 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1216 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1217 extRRItype, /* 15 5,5,5,5,3,3,5 */
1218 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1219 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1220 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1221 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1222 extRi64type, /* 20 5,6,5,5,3,3,5 */
1223 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1225 /* I am heaping all the fields of the formats into one structure and
1226 then, only the fields which are involved in instruction extension */
1230 unsigned int regx; /* Function in i8 type */
1235 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1236 for the bits which make up the immediatate extension. */
1239 extended_offset (unsigned int extension)
1242 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1244 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1246 value |= extension & 0x01f; /* extract 4:0 */
1250 /* Only call this function if you know that this is an extendable
1251 instruction, It wont malfunction, but why make excess remote memory references?
1252 If the immediate operands get sign extended or somthing, do it after
1253 the extension is performed.
1255 /* FIXME: Every one of these cases needs to worry about sign extension
1256 when the offset is to be used in relative addressing */
1260 fetch_mips_16 (CORE_ADDR pc)
1263 pc &= 0xfffffffe; /* clear the low order bit */
1264 target_read_memory (pc, buf, 2);
1265 return extract_unsigned_integer (buf, 2);
1269 unpack_mips16 (CORE_ADDR pc,
1270 unsigned int extension,
1272 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1277 switch (insn_format)
1284 value = extended_offset (extension);
1285 value = value << 11; /* rom for the original value */
1286 value |= inst & 0x7ff; /* eleven bits from instruction */
1290 value = inst & 0x7ff;
1291 /* FIXME : Consider sign extension */
1300 { /* A register identifier and an offset */
1301 /* Most of the fields are the same as I type but the
1302 immediate value is of a different length */
1306 value = extended_offset (extension);
1307 value = value << 8; /* from the original instruction */
1308 value |= inst & 0xff; /* eleven bits from instruction */
1309 regx = (extension >> 8) & 0x07; /* or i8 funct */
1310 if (value & 0x4000) /* test the sign bit , bit 26 */
1312 value &= ~0x3fff; /* remove the sign bit */
1318 value = inst & 0xff; /* 8 bits */
1319 regx = (inst >> 8) & 0x07; /* or i8 funct */
1320 /* FIXME: Do sign extension , this format needs it */
1321 if (value & 0x80) /* THIS CONFUSES ME */
1323 value &= 0xef; /* remove the sign bit */
1333 unsigned long value;
1334 unsigned int nexthalf;
1335 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1336 value = value << 16;
1337 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1345 internal_error (__FILE__, __LINE__, "bad switch");
1347 upk->offset = offset;
1354 add_offset_16 (CORE_ADDR pc, int offset)
1356 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1360 extended_mips16_next_pc (CORE_ADDR pc,
1361 unsigned int extension, unsigned int insn)
1363 int op = (insn >> 11);
1366 case 2: /* Branch */
1369 struct upk_mips16 upk;
1370 unpack_mips16 (pc, extension, insn, itype, &upk);
1371 offset = upk.offset;
1377 pc += (offset << 1) + 2;
1380 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1382 struct upk_mips16 upk;
1383 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1384 pc = add_offset_16 (pc, upk.offset);
1385 if ((insn >> 10) & 0x01) /* Exchange mode */
1386 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1393 struct upk_mips16 upk;
1395 unpack_mips16 (pc, extension, insn, ritype, &upk);
1396 reg = read_signed_register (upk.regx);
1398 pc += (upk.offset << 1) + 2;
1405 struct upk_mips16 upk;
1407 unpack_mips16 (pc, extension, insn, ritype, &upk);
1408 reg = read_signed_register (upk.regx);
1410 pc += (upk.offset << 1) + 2;
1415 case 12: /* I8 Formats btez btnez */
1417 struct upk_mips16 upk;
1419 unpack_mips16 (pc, extension, insn, i8type, &upk);
1420 /* upk.regx contains the opcode */
1421 reg = read_signed_register (24); /* Test register is 24 */
1422 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1423 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1424 /* pc = add_offset_16(pc,upk.offset) ; */
1425 pc += (upk.offset << 1) + 2;
1430 case 29: /* RR Formats JR, JALR, JALR-RA */
1432 struct upk_mips16 upk;
1433 /* upk.fmt = rrtype; */
1438 upk.regx = (insn >> 8) & 0x07;
1439 upk.regy = (insn >> 5) & 0x07;
1447 break; /* Function return instruction */
1453 break; /* BOGUS Guess */
1455 pc = read_signed_register (reg);
1462 /* This is an instruction extension. Fetch the real instruction
1463 (which follows the extension) and decode things based on
1467 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1480 mips16_next_pc (CORE_ADDR pc)
1482 unsigned int insn = fetch_mips_16 (pc);
1483 return extended_mips16_next_pc (pc, 0, insn);
1486 /* The mips_next_pc function supports single_step when the remote
1487 target monitor or stub is not developed enough to do a single_step.
1488 It works by decoding the current instruction and predicting where a
1489 branch will go. This isnt hard because all the data is available.
1490 The MIPS32 and MIPS16 variants are quite different */
1492 mips_next_pc (CORE_ADDR pc)
1495 return mips16_next_pc (pc);
1497 return mips32_next_pc (pc);
1500 struct mips_frame_cache
1503 struct trad_frame_saved_reg *saved_regs;
1507 static struct mips_frame_cache *
1508 mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache)
1510 mips_extra_func_info_t proc_desc;
1511 struct mips_frame_cache *cache;
1512 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1513 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1514 /* r0 bit means kernel trap */
1516 /* What registers have been saved? Bitmasks. */
1517 unsigned long gen_mask, float_mask;
1519 if ((*this_cache) != NULL)
1520 return (*this_cache);
1521 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1522 (*this_cache) = cache;
1523 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1525 /* Get the mdebug proc descriptor. */
1526 proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1);
1527 if (proc_desc == NULL)
1528 /* I'm not sure how/whether this can happen. Normally when we
1529 can't find a proc_desc, we "synthesize" one using
1530 heuristic_proc_desc and set the saved_regs right away. */
1533 /* Extract the frame's base. */
1534 cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
1535 + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
1537 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1538 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1539 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1541 /* In any frame other than the innermost or a frame interrupted by a
1542 signal, we assume that all registers have been saved. This
1543 assumes that all register saves in a function happen before the
1544 first function call. */
1545 if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc))
1546 /* Not sure exactly what kernel_trap means, but if it means the
1547 kernel saves the registers without a prologue doing it, we
1548 better not examine the prologue to see whether registers
1549 have been saved yet. */
1552 /* We need to figure out whether the registers that the
1553 proc_desc claims are saved have been saved yet. */
1557 /* Bitmasks; set if we have found a save for the register. */
1558 unsigned long gen_save_found = 0;
1559 unsigned long float_save_found = 0;
1562 /* If the address is odd, assume this is MIPS16 code. */
1563 addr = PROC_LOW_ADDR (proc_desc);
1564 mips16 = pc_is_mips16 (addr);
1566 /* Scan through this function's instructions preceding the
1567 current PC, and look for those that save registers. */
1568 while (addr < frame_pc_unwind (next_frame))
1572 mips16_decode_reg_save (mips16_fetch_instruction (addr),
1574 addr += MIPS16_INSTLEN;
1578 mips32_decode_reg_save (mips32_fetch_instruction (addr),
1579 &gen_save_found, &float_save_found);
1580 addr += MIPS_INSTLEN;
1583 gen_mask = gen_save_found;
1584 float_mask = float_save_found;
1587 /* Fill in the offsets for the registers which gen_mask says were
1590 CORE_ADDR reg_position = (cache->base
1591 + PROC_REG_OFFSET (proc_desc));
1593 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1594 if (gen_mask & 0x80000000)
1596 cache->saved_regs[NUM_REGS + ireg].addr = reg_position;
1597 reg_position -= mips_abi_regsize (gdbarch);
1601 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1602 order of that normally used by gcc. Therefore, we have to fetch
1603 the first instruction of the function, and if it's an entry
1604 instruction that saves $s0 or $s1, correct their saved addresses. */
1605 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1607 ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1608 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
1612 int sreg_count = (inst >> 6) & 3;
1614 /* Check if the ra register was pushed on the stack. */
1615 CORE_ADDR reg_position = (cache->base
1616 + PROC_REG_OFFSET (proc_desc));
1618 reg_position -= mips_abi_regsize (gdbarch);
1620 /* Check if the s0 and s1 registers were pushed on the
1622 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1624 for (reg = 16; reg < sreg_count + 16; reg++)
1626 cache->saved_regs[NUM_REGS + reg].addr = reg_position;
1627 reg_position -= mips_abi_regsize (gdbarch);
1632 /* Fill in the offsets for the registers which float_mask says were
1635 CORE_ADDR reg_position = (cache->base
1636 + PROC_FREG_OFFSET (proc_desc));
1638 /* Fill in the offsets for the float registers which float_mask
1640 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1641 if (float_mask & 0x80000000)
1643 if (mips_abi_regsize (gdbarch) == 4
1644 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1646 /* On a big endian 32 bit ABI, floating point registers
1647 are paired to form doubles such that the most
1648 significant part is in $f[N+1] and the least
1649 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1650 registers are also spilled as a pair and stored as a
1653 When little-endian the least significant part is
1654 stored first leading to the memory order $f[N] and
1657 Unfortunately, when big-endian the most significant
1658 part of the double is stored first, and the least
1659 significant is stored second. This leads to the
1660 registers being ordered in memory as firt $f[N+1] and
1663 For the big-endian case make certain that the
1664 addresses point at the correct (swapped) locations
1665 $f[N] and $f[N+1] pair (keep in mind that
1666 reg_position is decremented each time through the
1669 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1670 .addr = reg_position - mips_abi_regsize (gdbarch);
1672 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1673 .addr = reg_position + mips_abi_regsize (gdbarch);
1676 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1677 .addr = reg_position;
1678 reg_position -= mips_abi_regsize (gdbarch);
1681 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
1682 = cache->saved_regs[NUM_REGS + RA_REGNUM];
1685 /* SP_REGNUM, contains the value and not the address. */
1686 trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
1688 return (*this_cache);
1692 mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache,
1693 struct frame_id *this_id)
1695 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1697 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
1701 mips_mdebug_frame_prev_register (struct frame_info *next_frame,
1703 int regnum, int *optimizedp,
1704 enum lval_type *lvalp, CORE_ADDR *addrp,
1705 int *realnump, void *valuep)
1707 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1709 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
1710 optimizedp, lvalp, addrp, realnump, valuep);
1713 static const struct frame_unwind mips_mdebug_frame_unwind =
1716 mips_mdebug_frame_this_id,
1717 mips_mdebug_frame_prev_register
1720 static const struct frame_unwind *
1721 mips_mdebug_frame_sniffer (struct frame_info *next_frame)
1723 return &mips_mdebug_frame_unwind;
1727 mips_mdebug_frame_base_address (struct frame_info *next_frame,
1730 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1735 static const struct frame_base mips_mdebug_frame_base = {
1736 &mips_mdebug_frame_unwind,
1737 mips_mdebug_frame_base_address,
1738 mips_mdebug_frame_base_address,
1739 mips_mdebug_frame_base_address
1742 static const struct frame_base *
1743 mips_mdebug_frame_base_sniffer (struct frame_info *next_frame)
1745 return &mips_mdebug_frame_base;
1749 read_next_frame_reg (struct frame_info *fi, int regno)
1751 /* Always a pseudo. */
1752 gdb_assert (regno >= NUM_REGS);
1756 regcache_cooked_read_signed (current_regcache, regno, &val);
1759 else if ((regno % NUM_REGS) == MIPS_SP_REGNUM)
1760 /* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
1761 In fact, it is so special that it can even only be fetched
1762 using a raw register number! Once this code as been converted
1763 to frame-unwind the problem goes away. */
1764 return frame_unwind_register_signed (fi, regno % NUM_REGS);
1766 return frame_unwind_register_signed (fi, regno);
1770 /* mips_addr_bits_remove - remove useless address bits */
1773 mips_addr_bits_remove (CORE_ADDR addr)
1775 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1776 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
1777 /* This hack is a work-around for existing boards using PMON, the
1778 simulator, and any other 64-bit targets that doesn't have true
1779 64-bit addressing. On these targets, the upper 32 bits of
1780 addresses are ignored by the hardware. Thus, the PC or SP are
1781 likely to have been sign extended to all 1s by instruction
1782 sequences that load 32-bit addresses. For example, a typical
1783 piece of code that loads an address is this:
1785 lui $r2, <upper 16 bits>
1786 ori $r2, <lower 16 bits>
1788 But the lui sign-extends the value such that the upper 32 bits
1789 may be all 1s. The workaround is simply to mask off these
1790 bits. In the future, gcc may be changed to support true 64-bit
1791 addressing, and this masking will have to be disabled. */
1792 return addr &= 0xffffffffUL;
1797 /* mips_software_single_step() is called just before we want to resume
1798 the inferior, if we want to single-step it but there is no hardware
1799 or kernel single-step support (MIPS on GNU/Linux for example). We find
1800 the target of the coming instruction and breakpoint it.
1802 single_step is also called just after the inferior stops. If we had
1803 set up a simulated single-step, we undo our damage. */
1806 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1808 static CORE_ADDR next_pc;
1809 typedef char binsn_quantum[BREAKPOINT_MAX];
1810 static binsn_quantum break_mem;
1813 if (insert_breakpoints_p)
1815 pc = read_register (mips_regnum (current_gdbarch)->pc);
1816 next_pc = mips_next_pc (pc);
1818 target_insert_breakpoint (next_pc, break_mem);
1821 target_remove_breakpoint (next_pc, break_mem);
1824 static struct mips_extra_func_info temp_proc_desc;
1826 /* This hack will go away once the get_prev_frame() code has been
1827 modified to set the frame's type first. That is BEFORE init extra
1828 frame info et.al. is called. This is because it will become
1829 possible to skip the init extra info call for sigtramp and dummy
1831 static CORE_ADDR *temp_saved_regs;
1833 /* Set a register's saved stack address in temp_saved_regs. If an
1834 address has already been set for this register, do nothing; this
1835 way we will only recognize the first save of a given register in a
1838 For simplicity, save the address in both [0 .. NUM_REGS) and
1839 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1840 is used as it is only second range (the ABI instead of ISA
1841 registers) that comes into play when finding saved registers in a
1845 set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset)
1847 if (saved_regs[regno] == 0)
1849 saved_regs[regno + 0 * NUM_REGS] = offset;
1850 saved_regs[regno + 1 * NUM_REGS] = offset;
1855 /* Test whether the PC points to the return instruction at the
1856 end of a function. */
1859 mips_about_to_return (CORE_ADDR pc)
1861 if (pc_is_mips16 (pc))
1862 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1863 generates a "jr $ra"; other times it generates code to load
1864 the return address from the stack to an accessible register (such
1865 as $a3), then a "jr" using that register. This second case
1866 is almost impossible to distinguish from an indirect jump
1867 used for switch statements, so we don't even try. */
1868 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1870 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1874 /* This fencepost looks highly suspicious to me. Removing it also
1875 seems suspicious as it could affect remote debugging across serial
1879 heuristic_proc_start (CORE_ADDR pc)
1886 pc = ADDR_BITS_REMOVE (pc);
1888 fence = start_pc - heuristic_fence_post;
1892 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
1893 fence = VM_MIN_ADDRESS;
1895 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1897 /* search back for previous return */
1898 for (start_pc -= instlen;; start_pc -= instlen)
1899 if (start_pc < fence)
1901 /* It's not clear to me why we reach this point when
1902 stop_soon, but with this test, at least we
1903 don't print out warnings for every child forked (eg, on
1904 decstation). 22apr93 rich@cygnus.com. */
1905 if (stop_soon == NO_STOP_QUIETLY)
1907 static int blurb_printed = 0;
1909 warning ("GDB can't find the start of the function at 0x%s.",
1914 /* This actually happens frequently in embedded
1915 development, when you first connect to a board
1916 and your stack pointer and pc are nowhere in
1917 particular. This message needs to give people
1918 in that situation enough information to
1919 determine that it's no big deal. */
1920 printf_filtered ("\n\
1921 GDB is unable to find the start of the function at 0x%s\n\
1922 and thus can't determine the size of that function's stack frame.\n\
1923 This means that GDB may be unable to access that stack frame, or\n\
1924 the frames below it.\n\
1925 This problem is most likely caused by an invalid program counter or\n\
1927 However, if you think GDB should simply search farther back\n\
1928 from 0x%s for code which looks like the beginning of a\n\
1929 function, you can increase the range of the search using the `set\n\
1930 heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
1937 else if (pc_is_mips16 (start_pc))
1939 unsigned short inst;
1941 /* On MIPS16, any one of the following is likely to be the
1942 start of a function:
1946 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1947 inst = mips_fetch_instruction (start_pc);
1948 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1949 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1950 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1951 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1953 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1954 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1959 else if (mips_about_to_return (start_pc))
1961 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1968 /* Fetch the immediate value from a MIPS16 instruction.
1969 If the previous instruction was an EXTEND, use it to extend
1970 the upper bits of the immediate value. This is a helper function
1971 for mips16_heuristic_proc_desc. */
1974 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1975 unsigned short inst, /* current instruction */
1976 int nbits, /* number of bits in imm field */
1977 int scale, /* scale factor to be applied to imm */
1978 int is_signed) /* is the imm field signed? */
1982 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1984 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1985 if (offset & 0x8000) /* check for negative extend */
1986 offset = 0 - (0x10000 - (offset & 0xffff));
1987 return offset | (inst & 0x1f);
1991 int max_imm = 1 << nbits;
1992 int mask = max_imm - 1;
1993 int sign_bit = max_imm >> 1;
1995 offset = inst & mask;
1996 if (is_signed && (offset & sign_bit))
1997 offset = 0 - (max_imm - offset);
1998 return offset * scale;
2003 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2004 stream from start_pc to limit_pc. */
2007 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2008 struct frame_info *next_frame, CORE_ADDR sp)
2011 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
2012 unsigned short prev_inst = 0; /* saved copy of previous instruction */
2013 unsigned inst = 0; /* current instruction */
2014 unsigned entry_inst = 0; /* the entry instruction */
2016 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2018 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
2019 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2021 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
2023 /* Save the previous instruction. If it's an EXTEND, we'll extract
2024 the immediate offset extension from it in mips16_get_imm. */
2027 /* Fetch and decode the instruction. */
2028 inst = (unsigned short) mips_fetch_instruction (cur_pc);
2029 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2030 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2032 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2033 if (offset < 0) /* negative stack adjustment? */
2034 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
2036 /* Exit loop if a positive stack adjustment is found, which
2037 usually means that the stack cleanup code in the function
2038 epilogue is reached. */
2041 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2043 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2044 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
2045 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2046 set_reg_offset (temp_saved_regs, reg, sp + offset);
2048 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2050 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2051 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2052 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2053 set_reg_offset (temp_saved_regs, reg, sp + offset);
2055 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2057 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2058 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2059 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2061 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2063 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2064 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2065 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2067 else if (inst == 0x673d) /* move $s1, $sp */
2070 PROC_FRAME_REG (&temp_proc_desc) = 17;
2072 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2074 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2075 frame_addr = sp + offset;
2076 PROC_FRAME_REG (&temp_proc_desc) = 17;
2077 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
2079 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2081 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2082 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2083 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2084 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2086 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2088 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2089 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2090 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2091 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2093 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2094 entry_inst = inst; /* save for later processing */
2095 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
2096 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
2099 /* The entry instruction is typically the first instruction in a function,
2100 and it stores registers at offsets relative to the value of the old SP
2101 (before the prologue). But the value of the sp parameter to this
2102 function is the new SP (after the prologue has been executed). So we
2103 can't calculate those offsets until we've seen the entire prologue,
2104 and can calculate what the old SP must have been. */
2105 if (entry_inst != 0)
2107 int areg_count = (entry_inst >> 8) & 7;
2108 int sreg_count = (entry_inst >> 6) & 3;
2110 /* The entry instruction always subtracts 32 from the SP. */
2111 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
2113 /* Now we can calculate what the SP must have been at the
2114 start of the function prologue. */
2115 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
2117 /* Check if a0-a3 were saved in the caller's argument save area. */
2118 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2120 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2121 set_reg_offset (temp_saved_regs, reg, sp + offset);
2122 offset += mips_abi_regsize (current_gdbarch);
2125 /* Check if the ra register was pushed on the stack. */
2127 if (entry_inst & 0x20)
2129 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
2130 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2131 offset -= mips_abi_regsize (current_gdbarch);
2134 /* Check if the s0 and s1 registers were pushed on the stack. */
2135 for (reg = 16; reg < sreg_count + 16; reg++)
2137 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2138 set_reg_offset (temp_saved_regs, reg, sp + offset);
2139 offset -= mips_abi_regsize (current_gdbarch);
2145 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2146 struct frame_info *next_frame, CORE_ADDR sp)
2149 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
2151 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2152 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2153 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
2154 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2155 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2157 unsigned long inst, high_word, low_word;
2160 /* Fetch the instruction. */
2161 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2163 /* Save some code by pre-extracting some useful fields. */
2164 high_word = (inst >> 16) & 0xffff;
2165 low_word = inst & 0xffff;
2166 reg = high_word & 0x1f;
2168 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2169 || high_word == 0x23bd /* addi $sp,$sp,-i */
2170 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2172 if (low_word & 0x8000) /* negative stack adjustment? */
2173 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
2175 /* Exit loop if a positive stack adjustment is found, which
2176 usually means that the stack cleanup code in the function
2177 epilogue is reached. */
2180 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2182 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2183 set_reg_offset (temp_saved_regs, reg, sp + low_word);
2185 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2187 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2189 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2190 set_reg_offset (temp_saved_regs, reg, sp + low_word);
2192 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2194 /* Old gcc frame, r30 is virtual frame pointer. */
2195 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2196 frame_addr = sp + low_word;
2197 else if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM)
2199 unsigned alloca_adjust;
2200 PROC_FRAME_REG (&temp_proc_desc) = 30;
2201 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
2202 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2203 if (alloca_adjust > 0)
2205 /* FP > SP + frame_size. This may be because
2206 * of an alloca or somethings similar.
2207 * Fix sp to "pre-alloca" value, and try again.
2209 sp += alloca_adjust;
2214 /* move $30,$sp. With different versions of gas this will be either
2215 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2216 Accept any one of these. */
2217 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2219 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2220 if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM)
2222 unsigned alloca_adjust;
2223 PROC_FRAME_REG (&temp_proc_desc) = 30;
2224 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
2225 alloca_adjust = (unsigned) (frame_addr - sp);
2226 if (alloca_adjust > 0)
2228 /* FP > SP + frame_size. This may be because
2229 * of an alloca or somethings similar.
2230 * Fix sp to "pre-alloca" value, and try again.
2232 sp += alloca_adjust;
2237 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2239 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2240 set_reg_offset (temp_saved_regs, reg, frame_addr + low_word);
2245 static mips_extra_func_info_t
2246 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2247 struct frame_info *next_frame, int cur_frame)
2252 sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM);
2258 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2259 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2260 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2261 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2262 PROC_FRAME_REG (&temp_proc_desc) = MIPS_SP_REGNUM;
2263 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2265 if (start_pc + 200 < limit_pc)
2266 limit_pc = start_pc + 200;
2267 if (pc_is_mips16 (start_pc))
2268 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2270 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2271 return &temp_proc_desc;
2274 struct mips_objfile_private
2280 /* Global used to communicate between non_heuristic_proc_desc and
2281 compare_pdr_entries within qsort (). */
2282 static bfd *the_bfd;
2285 compare_pdr_entries (const void *a, const void *b)
2287 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2288 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2292 else if (lhs == rhs)
2298 static mips_extra_func_info_t
2299 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2301 CORE_ADDR startaddr;
2302 mips_extra_func_info_t proc_desc;
2303 struct block *b = block_for_pc (pc);
2305 struct obj_section *sec;
2306 struct mips_objfile_private *priv;
2308 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2310 *addrptr = startaddr;
2314 sec = find_pc_section (pc);
2317 priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data);
2319 /* Search the ".pdr" section generated by GAS. This includes most of
2320 the information normally found in ECOFF PDRs. */
2322 the_bfd = sec->objfile->obfd;
2324 && (the_bfd->format == bfd_object
2325 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2326 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2328 /* Right now GAS only outputs the address as a four-byte sequence.
2329 This means that we should not bother with this method on 64-bit
2330 targets (until that is fixed). */
2332 priv = obstack_alloc (&sec->objfile->objfile_obstack,
2333 sizeof (struct mips_objfile_private));
2335 set_objfile_data (sec->objfile, mips_pdr_data, priv);
2337 else if (priv == NULL)
2341 priv = obstack_alloc (&sec->objfile->objfile_obstack,
2342 sizeof (struct mips_objfile_private));
2344 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2347 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2348 priv->contents = obstack_alloc (&sec->objfile->objfile_obstack,
2350 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2351 priv->contents, 0, priv->size);
2353 /* In general, the .pdr section is sorted. However, in the
2354 presence of multiple code sections (and other corner cases)
2355 it can become unsorted. Sort it so that we can use a faster
2357 qsort (priv->contents, priv->size / 32, 32,
2358 compare_pdr_entries);
2363 set_objfile_data (sec->objfile, mips_pdr_data, priv);
2367 if (priv->size != 0)
2374 high = priv->size / 32;
2376 /* We've found a .pdr section describing this objfile. We want to
2377 find the entry which describes this code address. The .pdr
2378 information is not very descriptive; we have only a function
2379 start address. We have to look for the closest entry, because
2380 the local symbol at the beginning of this function may have
2381 been stripped - so if we ask the symbol table for the start
2382 address we may get a preceding global function. */
2384 /* First, find the last .pdr entry starting at or before PC. */
2387 mid = (low + high) / 2;
2389 ptr = priv->contents + mid * 32;
2390 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2391 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2392 SECT_OFF_TEXT (sec->objfile));
2399 while (low != high);
2401 /* Both low and high point one past the PDR of interest. If
2402 both are zero, that means this PC is before any region
2403 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2407 ptr = priv->contents + (low - 1) * 32;
2408 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2409 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2410 SECT_OFF_TEXT (sec->objfile));
2413 /* We don't have a range, so we have no way to know for sure
2414 whether we're in the correct PDR or a PDR for a preceding
2415 function and the current function was a stripped local
2416 symbol. But if the PDR's PC is at least as great as the
2417 best guess from the symbol table, assume that it does cover
2418 the right area; if a .pdr section is present at all then
2419 nearly every function will have an entry. The biggest exception
2420 will be the dynamic linker stubs; conveniently these are
2421 placed before .text instead of after. */
2423 if (pc >= pdr_pc && pdr_pc >= startaddr)
2425 struct symbol *sym = find_pc_function (pc);
2430 /* Fill in what we need of the proc_desc. */
2431 proc_desc = (mips_extra_func_info_t)
2432 obstack_alloc (&sec->objfile->objfile_obstack,
2433 sizeof (struct mips_extra_func_info));
2434 PROC_LOW_ADDR (proc_desc) = pdr_pc;
2436 /* Only used for dummy frames. */
2437 PROC_HIGH_ADDR (proc_desc) = 0;
2439 PROC_FRAME_OFFSET (proc_desc)
2440 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2441 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2443 PROC_FRAME_ADJUST (proc_desc) = 0;
2444 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2446 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2448 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2450 PROC_FREG_OFFSET (proc_desc)
2451 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2452 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2454 proc_desc->pdr.isym = (long) sym;
2464 if (startaddr > BLOCK_START (b))
2466 /* This is the "pathological" case referred to in a comment in
2467 print_frame_info. It might be better to move this check into
2472 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL);
2474 /* If we never found a PDR for this function in symbol reading, then
2475 examine prologues to find the information. */
2478 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2479 if (PROC_FRAME_REG (proc_desc) == -1)
2489 static mips_extra_func_info_t
2490 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2492 mips_extra_func_info_t proc_desc;
2493 CORE_ADDR startaddr = 0;
2495 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2499 /* IF this is the topmost frame AND
2500 * (this proc does not have debugging information OR
2501 * the PC is in the procedure prologue)
2502 * THEN create a "heuristic" proc_desc (by analyzing
2503 * the actual code) to replace the "official" proc_desc.
2505 if (next_frame == NULL)
2507 struct symtab_and_line val;
2508 struct symbol *proc_symbol =
2509 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2513 val = find_pc_line (BLOCK_START
2514 (SYMBOL_BLOCK_VALUE (proc_symbol)), 0);
2515 val.pc = val.end ? val.end : pc;
2517 if (!proc_symbol || pc < val.pc)
2519 mips_extra_func_info_t found_heuristic =
2520 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2521 pc, next_frame, cur_frame);
2522 if (found_heuristic)
2523 proc_desc = found_heuristic;
2529 /* Is linked_proc_desc_table really necessary? It only seems to be used
2530 by procedure call dummys. However, the procedures being called ought
2531 to have their own proc_descs, and even if they don't,
2532 heuristic_proc_desc knows how to create them! */
2534 struct linked_proc_info *link;
2536 for (link = linked_proc_desc_table; link; link = link->next)
2537 if (PROC_LOW_ADDR (&link->info) <= pc
2538 && PROC_HIGH_ADDR (&link->info) > pc)
2542 startaddr = heuristic_proc_start (pc);
2544 proc_desc = heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2549 /* MIPS stack frames are almost impenetrable. When execution stops,
2550 we basically have to look at symbol information for the function
2551 that we stopped in, which tells us *which* register (if any) is
2552 the base of the frame pointer, and what offset from that register
2553 the frame itself is at.
2555 This presents a problem when trying to examine a stack in memory
2556 (that isn't executing at the moment), using the "frame" command. We
2557 don't have a PC, nor do we have any registers except SP.
2559 This routine takes two arguments, SP and PC, and tries to make the
2560 cached frames look as if these two arguments defined a frame on the
2561 cache. This allows the rest of info frame to extract the important
2562 arguments without difficulty. */
2565 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2568 error ("MIPS frame specifications require two arguments: sp and pc");
2570 return create_new_frame (argv[0], argv[1]);
2573 /* According to the current ABI, should the type be passed in a
2574 floating-point register (assuming that there is space)? When there
2575 is no FPU, FP are not even considered as possibile candidates for
2576 FP registers and, consequently this returns false - forces FP
2577 arguments into integer registers. */
2580 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2582 return ((typecode == TYPE_CODE_FLT
2584 && (typecode == TYPE_CODE_STRUCT
2585 || typecode == TYPE_CODE_UNION)
2586 && TYPE_NFIELDS (arg_type) == 1
2587 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2588 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2591 /* On o32, argument passing in GPRs depends on the alignment of the type being
2592 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2595 mips_type_needs_double_align (struct type *type)
2597 enum type_code typecode = TYPE_CODE (type);
2599 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2601 else if (typecode == TYPE_CODE_STRUCT)
2603 if (TYPE_NFIELDS (type) < 1)
2605 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2607 else if (typecode == TYPE_CODE_UNION)
2611 n = TYPE_NFIELDS (type);
2612 for (i = 0; i < n; i++)
2613 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2620 /* Adjust the address downward (direction of stack growth) so that it
2621 is correctly aligned for a new stack frame. */
2623 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2625 return align_down (addr, 16);
2628 /* Determine how a return value is stored within the MIPS register
2629 file, given the return type `valtype'. */
2631 struct return_value_word
2640 return_value_location (struct type *valtype,
2641 struct return_value_word *hi,
2642 struct return_value_word *lo)
2644 int len = TYPE_LENGTH (valtype);
2645 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2647 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
2648 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
2649 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
2651 if (mips_abi_regsize (current_gdbarch) < 8 && len == 8)
2653 /* We need to break a 64bit float in two 32 bit halves and
2654 spread them across a floating-point register pair. */
2655 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2656 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
2657 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2658 && register_size (current_gdbarch,
2659 mips_regnum (current_gdbarch)->
2660 fp0) == 8) ? 4 : 0);
2661 hi->reg_offset = lo->reg_offset;
2662 lo->reg = mips_regnum (current_gdbarch)->fp0 + 0;
2663 hi->reg = mips_regnum (current_gdbarch)->fp0 + 1;
2669 /* The floating point value fits in a single floating-point
2671 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2672 && register_size (current_gdbarch,
2673 mips_regnum (current_gdbarch)->
2675 && len == 4) ? 4 : 0);
2676 lo->reg = mips_regnum (current_gdbarch)->fp0;
2687 /* Locate a result possibly spread across two registers. */
2689 lo->reg = regnum + 0;
2690 hi->reg = regnum + 1;
2691 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2692 && len < mips_abi_regsize (current_gdbarch))
2694 /* "un-left-justify" the value in the low register */
2695 lo->reg_offset = mips_abi_regsize (current_gdbarch) - len;
2700 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_abi_regsize (current_gdbarch) /* odd-size structs */
2701 && len < mips_abi_regsize (current_gdbarch) * 2
2702 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
2703 TYPE_CODE (valtype) == TYPE_CODE_UNION))
2705 /* "un-left-justify" the value spread across two registers. */
2706 lo->reg_offset = 2 * mips_abi_regsize (current_gdbarch) - len;
2707 lo->len = mips_abi_regsize (current_gdbarch) - lo->reg_offset;
2709 hi->len = len - lo->len;
2713 /* Only perform a partial copy of the second register. */
2716 if (len > mips_abi_regsize (current_gdbarch))
2718 lo->len = mips_abi_regsize (current_gdbarch);
2719 hi->len = len - mips_abi_regsize (current_gdbarch);
2727 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2728 && register_size (current_gdbarch, regnum) == 8
2729 && mips_abi_regsize (current_gdbarch) == 4)
2731 /* Account for the fact that only the least-signficant part
2732 of the register is being used */
2733 lo->reg_offset += 4;
2734 hi->reg_offset += 4;
2737 hi->buf_offset = lo->len;
2741 /* Should call_function allocate stack space for a struct return? */
2744 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
2746 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2747 return (TYPE_LENGTH (type) > 2 * mips_abi_regsize (current_gdbarch));
2750 /* Should call_function pass struct by reference?
2751 For each architecture, structs are passed either by
2752 value or by reference, depending on their size. */
2755 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
2757 enum type_code typecode = TYPE_CODE (check_typedef (type));
2758 int len = TYPE_LENGTH (check_typedef (type));
2759 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2761 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2762 return (len > mips_abi_regsize (current_gdbarch));
2768 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2769 struct regcache *regcache, CORE_ADDR bp_addr,
2770 int nargs, struct value **args, CORE_ADDR sp,
2771 int struct_return, CORE_ADDR struct_addr)
2777 int stack_offset = 0;
2778 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2779 CORE_ADDR func_addr = find_function_addr (function, NULL);
2781 /* For shared libraries, "t9" needs to point at the function
2783 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
2785 /* Set the return address register to point to the entry point of
2786 the program, where a breakpoint lies in wait. */
2787 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
2789 /* First ensure that the stack and structure return address (if any)
2790 are properly aligned. The stack has to be at least 64-bit
2791 aligned even on 32-bit machines, because doubles must be 64-bit
2792 aligned. For n32 and n64, stack frames need to be 128-bit
2793 aligned, so we round to this widest known alignment. */
2795 sp = align_down (sp, 16);
2796 struct_addr = align_down (struct_addr, 16);
2798 /* Now make space on the stack for the args. We allocate more
2799 than necessary for EABI, because the first few arguments are
2800 passed in registers, but that's OK. */
2801 for (argnum = 0; argnum < nargs; argnum++)
2802 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2803 mips_stack_argsize (gdbarch));
2804 sp -= align_up (len, 16);
2807 fprintf_unfiltered (gdb_stdlog,
2808 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2809 paddr_nz (sp), (long) align_up (len, 16));
2811 /* Initialize the integer and float register pointers. */
2813 float_argreg = mips_fpa0_regnum (current_gdbarch);
2815 /* The struct_return pointer occupies the first parameter-passing reg. */
2819 fprintf_unfiltered (gdb_stdlog,
2820 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2821 argreg, paddr_nz (struct_addr));
2822 write_register (argreg++, struct_addr);
2825 /* Now load as many as possible of the first arguments into
2826 registers, and push the rest onto the stack. Loop thru args
2827 from first to last. */
2828 for (argnum = 0; argnum < nargs; argnum++)
2831 char valbuf[MAX_REGISTER_SIZE];
2832 struct value *arg = args[argnum];
2833 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2834 int len = TYPE_LENGTH (arg_type);
2835 enum type_code typecode = TYPE_CODE (arg_type);
2838 fprintf_unfiltered (gdb_stdlog,
2839 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2840 argnum + 1, len, (int) typecode);
2842 /* The EABI passes structures that do not fit in a register by
2844 if (len > mips_abi_regsize (gdbarch)
2845 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2847 store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch),
2848 VALUE_ADDRESS (arg));
2849 typecode = TYPE_CODE_PTR;
2850 len = mips_abi_regsize (gdbarch);
2853 fprintf_unfiltered (gdb_stdlog, " push");
2856 val = (char *) VALUE_CONTENTS (arg);
2858 /* 32-bit ABIs always start floating point arguments in an
2859 even-numbered floating point register. Round the FP register
2860 up before the check to see if there are any FP registers
2861 left. Non MIPS_EABI targets also pass the FP in the integer
2862 registers so also round up normal registers. */
2863 if (mips_abi_regsize (gdbarch) < 8
2864 && fp_register_arg_p (typecode, arg_type))
2866 if ((float_argreg & 1))
2870 /* Floating point arguments passed in registers have to be
2871 treated specially. On 32-bit architectures, doubles
2872 are passed in register pairs; the even register gets
2873 the low word, and the odd register gets the high word.
2874 On non-EABI processors, the first two floating point arguments are
2875 also copied to general registers, because MIPS16 functions
2876 don't use float registers for arguments. This duplication of
2877 arguments in general registers can't hurt non-MIPS16 functions
2878 because those registers are normally skipped. */
2879 /* MIPS_EABI squeezes a struct that contains a single floating
2880 point value into an FP register instead of pushing it onto the
2882 if (fp_register_arg_p (typecode, arg_type)
2883 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2885 if (mips_abi_regsize (gdbarch) < 8 && len == 8)
2887 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2888 unsigned long regval;
2890 /* Write the low word of the double to the even register(s). */
2891 regval = extract_unsigned_integer (val + low_offset, 4);
2893 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2894 float_argreg, phex (regval, 4));
2895 write_register (float_argreg++, regval);
2897 /* Write the high word of the double to the odd register(s). */
2898 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2900 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2901 float_argreg, phex (regval, 4));
2902 write_register (float_argreg++, regval);
2906 /* This is a floating point value that fits entirely
2907 in a single register. */
2908 /* On 32 bit ABI's the float_argreg is further adjusted
2909 above to ensure that it is even register aligned. */
2910 LONGEST regval = extract_unsigned_integer (val, len);
2912 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2913 float_argreg, phex (regval, len));
2914 write_register (float_argreg++, regval);
2919 /* Copy the argument to general registers or the stack in
2920 register-sized pieces. Large arguments are split between
2921 registers and stack. */
2922 /* Note: structs whose size is not a multiple of
2923 mips_abi_regsize() are treated specially: Irix cc passes
2924 them in registers where gcc sometimes puts them on the
2925 stack. For maximum compatibility, we will put them in
2927 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
2928 && (len % mips_abi_regsize (gdbarch) != 0));
2930 /* Note: Floating-point values that didn't fit into an FP
2931 register are only written to memory. */
2934 /* Remember if the argument was written to the stack. */
2935 int stack_used_p = 0;
2936 int partial_len = (len < mips_abi_regsize (gdbarch)
2937 ? len : mips_abi_regsize (gdbarch));
2940 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2943 /* Write this portion of the argument to the stack. */
2944 if (argreg > MIPS_LAST_ARG_REGNUM
2946 || fp_register_arg_p (typecode, arg_type))
2948 /* Should shorter than int integer values be
2949 promoted to int before being stored? */
2950 int longword_offset = 0;
2953 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2955 if (mips_stack_argsize (gdbarch) == 8
2956 && (typecode == TYPE_CODE_INT
2957 || typecode == TYPE_CODE_PTR
2958 || typecode == TYPE_CODE_FLT) && len <= 4)
2959 longword_offset = mips_stack_argsize (gdbarch) - len;
2960 else if ((typecode == TYPE_CODE_STRUCT
2961 || typecode == TYPE_CODE_UNION)
2962 && (TYPE_LENGTH (arg_type)
2963 < mips_stack_argsize (gdbarch)))
2964 longword_offset = mips_stack_argsize (gdbarch) - len;
2969 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2970 paddr_nz (stack_offset));
2971 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2972 paddr_nz (longword_offset));
2975 addr = sp + stack_offset + longword_offset;
2980 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2982 for (i = 0; i < partial_len; i++)
2984 fprintf_unfiltered (gdb_stdlog, "%02x",
2988 write_memory (addr, val, partial_len);
2991 /* Note!!! This is NOT an else clause. Odd sized
2992 structs may go thru BOTH paths. Floating point
2993 arguments will not. */
2994 /* Write this portion of the argument to a general
2995 purpose register. */
2996 if (argreg <= MIPS_LAST_ARG_REGNUM
2997 && !fp_register_arg_p (typecode, arg_type))
3000 extract_unsigned_integer (val, partial_len);
3003 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3006 mips_abi_regsize (gdbarch)));
3007 write_register (argreg, regval);
3014 /* Compute the the offset into the stack at which we
3015 will copy the next parameter.
3017 In the new EABI (and the NABI32), the stack_offset
3018 only needs to be adjusted when it has been used. */
3021 stack_offset += align_up (partial_len,
3022 mips_stack_argsize (gdbarch));
3026 fprintf_unfiltered (gdb_stdlog, "\n");
3029 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3031 /* Return adjusted stack pointer. */
3035 /* Given a return value in `regbuf' with a type `valtype', extract and
3036 copy its value into `valbuf'. */
3039 mips_eabi_extract_return_value (struct type *valtype,
3040 char regbuf[], char *valbuf)
3042 struct return_value_word lo;
3043 struct return_value_word hi;
3044 return_value_location (valtype, &hi, &lo);
3046 memcpy (valbuf + lo.buf_offset,
3047 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) +
3048 lo.reg_offset, lo.len);
3051 memcpy (valbuf + hi.buf_offset,
3052 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) +
3053 hi.reg_offset, hi.len);
3056 /* Given a return value in `valbuf' with a type `valtype', write it's
3057 value into the appropriate register. */
3060 mips_eabi_store_return_value (struct type *valtype, char *valbuf)
3062 char raw_buffer[MAX_REGISTER_SIZE];
3063 struct return_value_word lo;
3064 struct return_value_word hi;
3065 return_value_location (valtype, &hi, &lo);
3067 memset (raw_buffer, 0, sizeof (raw_buffer));
3068 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
3069 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg),
3070 raw_buffer, register_size (current_gdbarch,
3075 memset (raw_buffer, 0, sizeof (raw_buffer));
3076 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
3077 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg),
3079 register_size (current_gdbarch,
3084 /* N32/N64 ABI stuff. */
3087 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3088 struct regcache *regcache, CORE_ADDR bp_addr,
3089 int nargs, struct value **args, CORE_ADDR sp,
3090 int struct_return, CORE_ADDR struct_addr)
3096 int stack_offset = 0;
3097 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3098 CORE_ADDR func_addr = find_function_addr (function, NULL);
3100 /* For shared libraries, "t9" needs to point at the function
3102 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3104 /* Set the return address register to point to the entry point of
3105 the program, where a breakpoint lies in wait. */
3106 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3108 /* First ensure that the stack and structure return address (if any)
3109 are properly aligned. The stack has to be at least 64-bit
3110 aligned even on 32-bit machines, because doubles must be 64-bit
3111 aligned. For n32 and n64, stack frames need to be 128-bit
3112 aligned, so we round to this widest known alignment. */
3114 sp = align_down (sp, 16);
3115 struct_addr = align_down (struct_addr, 16);
3117 /* Now make space on the stack for the args. */
3118 for (argnum = 0; argnum < nargs; argnum++)
3119 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3120 mips_stack_argsize (gdbarch));
3121 sp -= align_up (len, 16);
3124 fprintf_unfiltered (gdb_stdlog,
3125 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3126 paddr_nz (sp), (long) align_up (len, 16));
3128 /* Initialize the integer and float register pointers. */
3130 float_argreg = mips_fpa0_regnum (current_gdbarch);
3132 /* The struct_return pointer occupies the first parameter-passing reg. */
3136 fprintf_unfiltered (gdb_stdlog,
3137 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3138 argreg, paddr_nz (struct_addr));
3139 write_register (argreg++, struct_addr);
3142 /* Now load as many as possible of the first arguments into
3143 registers, and push the rest onto the stack. Loop thru args
3144 from first to last. */
3145 for (argnum = 0; argnum < nargs; argnum++)
3148 struct value *arg = args[argnum];
3149 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3150 int len = TYPE_LENGTH (arg_type);
3151 enum type_code typecode = TYPE_CODE (arg_type);
3154 fprintf_unfiltered (gdb_stdlog,
3155 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3156 argnum + 1, len, (int) typecode);
3158 val = (char *) VALUE_CONTENTS (arg);
3160 if (fp_register_arg_p (typecode, arg_type)
3161 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3163 /* This is a floating point value that fits entirely
3164 in a single register. */
3165 /* On 32 bit ABI's the float_argreg is further adjusted
3166 above to ensure that it is even register aligned. */
3167 LONGEST regval = extract_unsigned_integer (val, len);
3169 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3170 float_argreg, phex (regval, len));
3171 write_register (float_argreg++, regval);
3174 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3175 argreg, phex (regval, len));
3176 write_register (argreg, regval);
3181 /* Copy the argument to general registers or the stack in
3182 register-sized pieces. Large arguments are split between
3183 registers and stack. */
3184 /* Note: structs whose size is not a multiple of
3185 mips_abi_regsize() are treated specially: Irix cc passes
3186 them in registers where gcc sometimes puts them on the
3187 stack. For maximum compatibility, we will put them in
3189 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
3190 && (len % mips_abi_regsize (gdbarch) != 0));
3191 /* Note: Floating-point values that didn't fit into an FP
3192 register are only written to memory. */
3195 /* Rememer if the argument was written to the stack. */
3196 int stack_used_p = 0;
3197 int partial_len = (len < mips_abi_regsize (gdbarch)
3198 ? len : mips_abi_regsize (gdbarch));
3201 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3204 /* Write this portion of the argument to the stack. */
3205 if (argreg > MIPS_LAST_ARG_REGNUM
3207 || fp_register_arg_p (typecode, arg_type))
3209 /* Should shorter than int integer values be
3210 promoted to int before being stored? */
3211 int longword_offset = 0;
3214 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3216 if (mips_stack_argsize (gdbarch) == 8
3217 && (typecode == TYPE_CODE_INT
3218 || typecode == TYPE_CODE_PTR
3219 || typecode == TYPE_CODE_FLT) && len <= 4)
3220 longword_offset = mips_stack_argsize (gdbarch) - len;
3225 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3226 paddr_nz (stack_offset));
3227 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3228 paddr_nz (longword_offset));
3231 addr = sp + stack_offset + longword_offset;
3236 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3238 for (i = 0; i < partial_len; i++)
3240 fprintf_unfiltered (gdb_stdlog, "%02x",
3244 write_memory (addr, val, partial_len);
3247 /* Note!!! This is NOT an else clause. Odd sized
3248 structs may go thru BOTH paths. Floating point
3249 arguments will not. */
3250 /* Write this portion of the argument to a general
3251 purpose register. */
3252 if (argreg <= MIPS_LAST_ARG_REGNUM
3253 && !fp_register_arg_p (typecode, arg_type))
3256 extract_unsigned_integer (val, partial_len);
3258 /* A non-floating-point argument being passed in a
3259 general register. If a struct or union, and if
3260 the remaining length is smaller than the register
3261 size, we have to adjust the register value on
3264 It does not seem to be necessary to do the
3265 same for integral types.
3267 cagney/2001-07-23: gdb/179: Also, GCC, when
3268 outputting LE O32 with sizeof (struct) <
3269 mips_abi_regsize(), generates a left shift as
3270 part of storing the argument in a register a
3271 register (the left shift isn't generated when
3272 sizeof (struct) >= mips_abi_regsize()). Since
3273 it is quite possible that this is GCC
3274 contradicting the LE/O32 ABI, GDB has not been
3275 adjusted to accommodate this. Either someone
3276 needs to demonstrate that the LE/O32 ABI
3277 specifies such a left shift OR this new ABI gets
3278 identified as such and GDB gets tweaked
3281 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3282 && partial_len < mips_abi_regsize (gdbarch)
3283 && (typecode == TYPE_CODE_STRUCT ||
3284 typecode == TYPE_CODE_UNION))
3285 regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
3289 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3292 mips_abi_regsize (gdbarch)));
3293 write_register (argreg, regval);
3300 /* Compute the the offset into the stack at which we
3301 will copy the next parameter.
3303 In N32 (N64?), the stack_offset only needs to be
3304 adjusted when it has been used. */
3307 stack_offset += align_up (partial_len,
3308 mips_stack_argsize (gdbarch));
3312 fprintf_unfiltered (gdb_stdlog, "\n");
3315 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3317 /* Return adjusted stack pointer. */
3321 static enum return_value_convention
3322 mips_n32n64_return_value (struct gdbarch *gdbarch,
3323 struct type *type, struct regcache *regcache,
3324 void *readbuf, const void *writebuf)
3326 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3327 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3328 || TYPE_CODE (type) == TYPE_CODE_UNION
3329 || TYPE_CODE (type) == TYPE_CODE_ARRAY
3330 || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
3331 return RETURN_VALUE_STRUCT_CONVENTION;
3332 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3333 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3335 /* A floating-point value belongs in the least significant part
3338 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3339 mips_xfer_register (regcache,
3340 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3342 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3343 return RETURN_VALUE_REGISTER_CONVENTION;
3345 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3346 && TYPE_NFIELDS (type) <= 2
3347 && TYPE_NFIELDS (type) >= 1
3348 && ((TYPE_NFIELDS (type) == 1
3349 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3351 || (TYPE_NFIELDS (type) == 2
3352 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3354 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3356 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3358 /* A struct that contains one or two floats. Each value is part
3359 in the least significant part of their floating point
3363 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
3364 field < TYPE_NFIELDS (type); field++, regnum += 2)
3366 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3369 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3371 mips_xfer_register (regcache, NUM_REGS + regnum,
3372 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3373 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3375 return RETURN_VALUE_REGISTER_CONVENTION;
3377 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3378 || TYPE_CODE (type) == TYPE_CODE_UNION)
3380 /* A structure or union. Extract the left justified value,
3381 regardless of the byte order. I.e. DO NOT USE
3385 for (offset = 0, regnum = V0_REGNUM;
3386 offset < TYPE_LENGTH (type);
3387 offset += register_size (current_gdbarch, regnum), regnum++)
3389 int xfer = register_size (current_gdbarch, regnum);
3390 if (offset + xfer > TYPE_LENGTH (type))
3391 xfer = TYPE_LENGTH (type) - offset;
3393 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3394 offset, xfer, regnum);
3395 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3396 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3398 return RETURN_VALUE_REGISTER_CONVENTION;
3402 /* A scalar extract each part but least-significant-byte
3406 for (offset = 0, regnum = V0_REGNUM;
3407 offset < TYPE_LENGTH (type);
3408 offset += register_size (current_gdbarch, regnum), regnum++)
3410 int xfer = register_size (current_gdbarch, regnum);
3411 if (offset + xfer > TYPE_LENGTH (type))
3412 xfer = TYPE_LENGTH (type) - offset;
3414 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3415 offset, xfer, regnum);
3416 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3417 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3419 return RETURN_VALUE_REGISTER_CONVENTION;
3423 /* O32 ABI stuff. */
3426 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3427 struct regcache *regcache, CORE_ADDR bp_addr,
3428 int nargs, struct value **args, CORE_ADDR sp,
3429 int struct_return, CORE_ADDR struct_addr)
3435 int stack_offset = 0;
3436 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3437 CORE_ADDR func_addr = find_function_addr (function, NULL);
3439 /* For shared libraries, "t9" needs to point at the function
3441 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3443 /* Set the return address register to point to the entry point of
3444 the program, where a breakpoint lies in wait. */
3445 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3447 /* First ensure that the stack and structure return address (if any)
3448 are properly aligned. The stack has to be at least 64-bit
3449 aligned even on 32-bit machines, because doubles must be 64-bit
3450 aligned. For n32 and n64, stack frames need to be 128-bit
3451 aligned, so we round to this widest known alignment. */
3453 sp = align_down (sp, 16);
3454 struct_addr = align_down (struct_addr, 16);
3456 /* Now make space on the stack for the args. */
3457 for (argnum = 0; argnum < nargs; argnum++)
3458 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3459 mips_stack_argsize (gdbarch));
3460 sp -= align_up (len, 16);
3463 fprintf_unfiltered (gdb_stdlog,
3464 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3465 paddr_nz (sp), (long) align_up (len, 16));
3467 /* Initialize the integer and float register pointers. */
3469 float_argreg = mips_fpa0_regnum (current_gdbarch);
3471 /* The struct_return pointer occupies the first parameter-passing reg. */
3475 fprintf_unfiltered (gdb_stdlog,
3476 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3477 argreg, paddr_nz (struct_addr));
3478 write_register (argreg++, struct_addr);
3479 stack_offset += mips_stack_argsize (gdbarch);
3482 /* Now load as many as possible of the first arguments into
3483 registers, and push the rest onto the stack. Loop thru args
3484 from first to last. */
3485 for (argnum = 0; argnum < nargs; argnum++)
3488 struct value *arg = args[argnum];
3489 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3490 int len = TYPE_LENGTH (arg_type);
3491 enum type_code typecode = TYPE_CODE (arg_type);
3494 fprintf_unfiltered (gdb_stdlog,
3495 "mips_o32_push_dummy_call: %d len=%d type=%d",
3496 argnum + 1, len, (int) typecode);
3498 val = (char *) VALUE_CONTENTS (arg);
3500 /* 32-bit ABIs always start floating point arguments in an
3501 even-numbered floating point register. Round the FP register
3502 up before the check to see if there are any FP registers
3503 left. O32/O64 targets also pass the FP in the integer
3504 registers so also round up normal registers. */
3505 if (mips_abi_regsize (gdbarch) < 8
3506 && fp_register_arg_p (typecode, arg_type))
3508 if ((float_argreg & 1))
3512 /* Floating point arguments passed in registers have to be
3513 treated specially. On 32-bit architectures, doubles
3514 are passed in register pairs; the even register gets
3515 the low word, and the odd register gets the high word.
3516 On O32/O64, the first two floating point arguments are
3517 also copied to general registers, because MIPS16 functions
3518 don't use float registers for arguments. This duplication of
3519 arguments in general registers can't hurt non-MIPS16 functions
3520 because those registers are normally skipped. */
3522 if (fp_register_arg_p (typecode, arg_type)
3523 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3525 if (mips_abi_regsize (gdbarch) < 8 && len == 8)
3527 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3528 unsigned long regval;
3530 /* Write the low word of the double to the even register(s). */
3531 regval = extract_unsigned_integer (val + low_offset, 4);
3533 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3534 float_argreg, phex (regval, 4));
3535 write_register (float_argreg++, regval);
3537 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3538 argreg, phex (regval, 4));
3539 write_register (argreg++, regval);
3541 /* Write the high word of the double to the odd register(s). */
3542 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3544 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3545 float_argreg, phex (regval, 4));
3546 write_register (float_argreg++, regval);
3549 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3550 argreg, phex (regval, 4));
3551 write_register (argreg++, regval);
3555 /* This is a floating point value that fits entirely
3556 in a single register. */
3557 /* On 32 bit ABI's the float_argreg is further adjusted
3558 above to ensure that it is even register aligned. */
3559 LONGEST regval = extract_unsigned_integer (val, len);
3561 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3562 float_argreg, phex (regval, len));
3563 write_register (float_argreg++, regval);
3564 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3565 registers for each argument. The below is (my
3566 guess) to ensure that the corresponding integer
3567 register has reserved the same space. */
3569 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3570 argreg, phex (regval, len));
3571 write_register (argreg, regval);
3572 argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2;
3574 /* Reserve space for the FP register. */
3575 stack_offset += align_up (len, mips_stack_argsize (gdbarch));
3579 /* Copy the argument to general registers or the stack in
3580 register-sized pieces. Large arguments are split between
3581 registers and stack. */
3582 /* Note: structs whose size is not a multiple of
3583 mips_abi_regsize() are treated specially: Irix cc passes
3584 them in registers where gcc sometimes puts them on the
3585 stack. For maximum compatibility, we will put them in
3587 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
3588 && (len % mips_abi_regsize (gdbarch) != 0));
3589 /* Structures should be aligned to eight bytes (even arg registers)
3590 on MIPS_ABI_O32, if their first member has double precision. */
3591 if (mips_abi_regsize (gdbarch) < 8
3592 && mips_type_needs_double_align (arg_type))
3597 /* Note: Floating-point values that didn't fit into an FP
3598 register are only written to memory. */
3601 /* Remember if the argument was written to the stack. */
3602 int stack_used_p = 0;
3603 int partial_len = (len < mips_abi_regsize (gdbarch)
3604 ? len : mips_abi_regsize (gdbarch));
3607 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3610 /* Write this portion of the argument to the stack. */
3611 if (argreg > MIPS_LAST_ARG_REGNUM
3613 || fp_register_arg_p (typecode, arg_type))
3615 /* Should shorter than int integer values be
3616 promoted to int before being stored? */
3617 int longword_offset = 0;
3620 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3622 if (mips_stack_argsize (gdbarch) == 8
3623 && (typecode == TYPE_CODE_INT
3624 || typecode == TYPE_CODE_PTR
3625 || typecode == TYPE_CODE_FLT) && len <= 4)
3626 longword_offset = mips_stack_argsize (gdbarch) - len;
3631 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3632 paddr_nz (stack_offset));
3633 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3634 paddr_nz (longword_offset));
3637 addr = sp + stack_offset + longword_offset;
3642 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3644 for (i = 0; i < partial_len; i++)
3646 fprintf_unfiltered (gdb_stdlog, "%02x",
3650 write_memory (addr, val, partial_len);
3653 /* Note!!! This is NOT an else clause. Odd sized
3654 structs may go thru BOTH paths. Floating point
3655 arguments will not. */
3656 /* Write this portion of the argument to a general
3657 purpose register. */
3658 if (argreg <= MIPS_LAST_ARG_REGNUM
3659 && !fp_register_arg_p (typecode, arg_type))
3661 LONGEST regval = extract_signed_integer (val, partial_len);
3662 /* Value may need to be sign extended, because
3663 mips_isa_regsize() != mips_abi_regsize(). */
3665 /* A non-floating-point argument being passed in a
3666 general register. If a struct or union, and if
3667 the remaining length is smaller than the register
3668 size, we have to adjust the register value on
3671 It does not seem to be necessary to do the
3672 same for integral types.
3674 Also don't do this adjustment on O64 binaries.
3676 cagney/2001-07-23: gdb/179: Also, GCC, when
3677 outputting LE O32 with sizeof (struct) <
3678 mips_abi_regsize(), generates a left shift as
3679 part of storing the argument in a register a
3680 register (the left shift isn't generated when
3681 sizeof (struct) >= mips_abi_regsize()). Since
3682 it is quite possible that this is GCC
3683 contradicting the LE/O32 ABI, GDB has not been
3684 adjusted to accommodate this. Either someone
3685 needs to demonstrate that the LE/O32 ABI
3686 specifies such a left shift OR this new ABI gets
3687 identified as such and GDB gets tweaked
3690 if (mips_abi_regsize (gdbarch) < 8
3691 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3692 && partial_len < mips_abi_regsize (gdbarch)
3693 && (typecode == TYPE_CODE_STRUCT ||
3694 typecode == TYPE_CODE_UNION))
3695 regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
3699 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3702 mips_abi_regsize (gdbarch)));
3703 write_register (argreg, regval);
3706 /* Prevent subsequent floating point arguments from
3707 being passed in floating point registers. */
3708 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3714 /* Compute the the offset into the stack at which we
3715 will copy the next parameter.
3717 In older ABIs, the caller reserved space for
3718 registers that contained arguments. This was loosely
3719 refered to as their "home". Consequently, space is
3720 always allocated. */
3722 stack_offset += align_up (partial_len,
3723 mips_stack_argsize (gdbarch));
3727 fprintf_unfiltered (gdb_stdlog, "\n");
3730 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3732 /* Return adjusted stack pointer. */
3736 static enum return_value_convention
3737 mips_o32_return_value (struct gdbarch *gdbarch, struct type *type,
3738 struct regcache *regcache,
3739 void *readbuf, const void *writebuf)
3741 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3743 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3744 || TYPE_CODE (type) == TYPE_CODE_UNION
3745 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3746 return RETURN_VALUE_STRUCT_CONVENTION;
3747 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3748 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3750 /* A single-precision floating-point value. It fits in the
3751 least significant part of FP0. */
3753 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3754 mips_xfer_register (regcache,
3755 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3757 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3758 return RETURN_VALUE_REGISTER_CONVENTION;
3760 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3761 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3763 /* A double-precision floating-point value. The most
3764 significant part goes in FP1, and the least significant in
3767 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3768 switch (TARGET_BYTE_ORDER)
3770 case BFD_ENDIAN_LITTLE:
3771 mips_xfer_register (regcache,
3772 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3773 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3774 mips_xfer_register (regcache,
3775 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3776 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3778 case BFD_ENDIAN_BIG:
3779 mips_xfer_register (regcache,
3780 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3781 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3782 mips_xfer_register (regcache,
3783 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3784 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3787 internal_error (__FILE__, __LINE__, "bad switch");
3789 return RETURN_VALUE_REGISTER_CONVENTION;
3792 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3793 && TYPE_NFIELDS (type) <= 2
3794 && TYPE_NFIELDS (type) >= 1
3795 && ((TYPE_NFIELDS (type) == 1
3796 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3798 || (TYPE_NFIELDS (type) == 2
3799 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3801 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3803 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3805 /* A struct that contains one or two floats. Each value is part
3806 in the least significant part of their floating point
3808 bfd_byte reg[MAX_REGISTER_SIZE];
3811 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
3812 field < TYPE_NFIELDS (type); field++, regnum += 2)
3814 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3817 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3819 mips_xfer_register (regcache, NUM_REGS + regnum,
3820 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3821 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3823 return RETURN_VALUE_REGISTER_CONVENTION;
3827 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3828 || TYPE_CODE (type) == TYPE_CODE_UNION)
3830 /* A structure or union. Extract the left justified value,
3831 regardless of the byte order. I.e. DO NOT USE
3835 for (offset = 0, regnum = V0_REGNUM;
3836 offset < TYPE_LENGTH (type);
3837 offset += register_size (current_gdbarch, regnum), regnum++)
3839 int xfer = register_size (current_gdbarch, regnum);
3840 if (offset + xfer > TYPE_LENGTH (type))
3841 xfer = TYPE_LENGTH (type) - offset;
3843 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3844 offset, xfer, regnum);
3845 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3846 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3848 return RETURN_VALUE_REGISTER_CONVENTION;
3853 /* A scalar extract each part but least-significant-byte
3854 justified. o32 thinks registers are 4 byte, regardless of
3855 the ISA. mips_stack_argsize controls this. */
3858 for (offset = 0, regnum = V0_REGNUM;
3859 offset < TYPE_LENGTH (type);
3860 offset += mips_stack_argsize (gdbarch), regnum++)
3862 int xfer = mips_stack_argsize (gdbarch);
3863 if (offset + xfer > TYPE_LENGTH (type))
3864 xfer = TYPE_LENGTH (type) - offset;
3866 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3867 offset, xfer, regnum);
3868 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3869 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3871 return RETURN_VALUE_REGISTER_CONVENTION;
3875 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3879 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3880 struct regcache *regcache, CORE_ADDR bp_addr,
3882 struct value **args, CORE_ADDR sp,
3883 int struct_return, CORE_ADDR struct_addr)
3889 int stack_offset = 0;
3890 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3891 CORE_ADDR func_addr = find_function_addr (function, NULL);
3893 /* For shared libraries, "t9" needs to point at the function
3895 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3897 /* Set the return address register to point to the entry point of
3898 the program, where a breakpoint lies in wait. */
3899 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3901 /* First ensure that the stack and structure return address (if any)
3902 are properly aligned. The stack has to be at least 64-bit
3903 aligned even on 32-bit machines, because doubles must be 64-bit
3904 aligned. For n32 and n64, stack frames need to be 128-bit
3905 aligned, so we round to this widest known alignment. */
3907 sp = align_down (sp, 16);
3908 struct_addr = align_down (struct_addr, 16);
3910 /* Now make space on the stack for the args. */
3911 for (argnum = 0; argnum < nargs; argnum++)
3912 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3913 mips_stack_argsize (gdbarch));
3914 sp -= align_up (len, 16);
3917 fprintf_unfiltered (gdb_stdlog,
3918 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3919 paddr_nz (sp), (long) align_up (len, 16));
3921 /* Initialize the integer and float register pointers. */
3923 float_argreg = mips_fpa0_regnum (current_gdbarch);
3925 /* The struct_return pointer occupies the first parameter-passing reg. */
3929 fprintf_unfiltered (gdb_stdlog,
3930 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3931 argreg, paddr_nz (struct_addr));
3932 write_register (argreg++, struct_addr);
3933 stack_offset += mips_stack_argsize (gdbarch);
3936 /* Now load as many as possible of the first arguments into
3937 registers, and push the rest onto the stack. Loop thru args
3938 from first to last. */
3939 for (argnum = 0; argnum < nargs; argnum++)
3942 struct value *arg = args[argnum];
3943 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3944 int len = TYPE_LENGTH (arg_type);
3945 enum type_code typecode = TYPE_CODE (arg_type);
3948 fprintf_unfiltered (gdb_stdlog,
3949 "mips_o64_push_dummy_call: %d len=%d type=%d",
3950 argnum + 1, len, (int) typecode);
3952 val = (char *) VALUE_CONTENTS (arg);
3954 /* 32-bit ABIs always start floating point arguments in an
3955 even-numbered floating point register. Round the FP register
3956 up before the check to see if there are any FP registers
3957 left. O32/O64 targets also pass the FP in the integer
3958 registers so also round up normal registers. */
3959 if (mips_abi_regsize (gdbarch) < 8
3960 && fp_register_arg_p (typecode, arg_type))
3962 if ((float_argreg & 1))
3966 /* Floating point arguments passed in registers have to be
3967 treated specially. On 32-bit architectures, doubles
3968 are passed in register pairs; the even register gets
3969 the low word, and the odd register gets the high word.
3970 On O32/O64, the first two floating point arguments are
3971 also copied to general registers, because MIPS16 functions
3972 don't use float registers for arguments. This duplication of
3973 arguments in general registers can't hurt non-MIPS16 functions
3974 because those registers are normally skipped. */
3976 if (fp_register_arg_p (typecode, arg_type)
3977 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3979 if (mips_abi_regsize (gdbarch) < 8 && len == 8)
3981 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3982 unsigned long regval;
3984 /* Write the low word of the double to the even register(s). */
3985 regval = extract_unsigned_integer (val + low_offset, 4);
3987 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3988 float_argreg, phex (regval, 4));
3989 write_register (float_argreg++, regval);
3991 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3992 argreg, phex (regval, 4));
3993 write_register (argreg++, regval);
3995 /* Write the high word of the double to the odd register(s). */
3996 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3998 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3999 float_argreg, phex (regval, 4));
4000 write_register (float_argreg++, regval);
4003 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4004 argreg, phex (regval, 4));
4005 write_register (argreg++, regval);
4009 /* This is a floating point value that fits entirely
4010 in a single register. */
4011 /* On 32 bit ABI's the float_argreg is further adjusted
4012 above to ensure that it is even register aligned. */
4013 LONGEST regval = extract_unsigned_integer (val, len);
4015 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4016 float_argreg, phex (regval, len));
4017 write_register (float_argreg++, regval);
4018 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4019 registers for each argument. The below is (my
4020 guess) to ensure that the corresponding integer
4021 register has reserved the same space. */
4023 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4024 argreg, phex (regval, len));
4025 write_register (argreg, regval);
4026 argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2;
4028 /* Reserve space for the FP register. */
4029 stack_offset += align_up (len, mips_stack_argsize (gdbarch));
4033 /* Copy the argument to general registers or the stack in
4034 register-sized pieces. Large arguments are split between
4035 registers and stack. */
4036 /* Note: structs whose size is not a multiple of
4037 mips_abi_regsize() are treated specially: Irix cc passes
4038 them in registers where gcc sometimes puts them on the
4039 stack. For maximum compatibility, we will put them in
4041 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
4042 && (len % mips_abi_regsize (gdbarch) != 0));
4043 /* Structures should be aligned to eight bytes (even arg registers)
4044 on MIPS_ABI_O32, if their first member has double precision. */
4045 if (mips_abi_regsize (gdbarch) < 8
4046 && mips_type_needs_double_align (arg_type))
4051 /* Note: Floating-point values that didn't fit into an FP
4052 register are only written to memory. */
4055 /* Remember if the argument was written to the stack. */
4056 int stack_used_p = 0;
4057 int partial_len = (len < mips_abi_regsize (gdbarch)
4058 ? len : mips_abi_regsize (gdbarch));
4061 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4064 /* Write this portion of the argument to the stack. */
4065 if (argreg > MIPS_LAST_ARG_REGNUM
4067 || fp_register_arg_p (typecode, arg_type))
4069 /* Should shorter than int integer values be
4070 promoted to int before being stored? */
4071 int longword_offset = 0;
4074 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4076 if (mips_stack_argsize (gdbarch) == 8
4077 && (typecode == TYPE_CODE_INT
4078 || typecode == TYPE_CODE_PTR
4079 || typecode == TYPE_CODE_FLT) && len <= 4)
4080 longword_offset = mips_stack_argsize (gdbarch) - len;
4085 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
4086 paddr_nz (stack_offset));
4087 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
4088 paddr_nz (longword_offset));
4091 addr = sp + stack_offset + longword_offset;
4096 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
4098 for (i = 0; i < partial_len; i++)
4100 fprintf_unfiltered (gdb_stdlog, "%02x",
4104 write_memory (addr, val, partial_len);
4107 /* Note!!! This is NOT an else clause. Odd sized
4108 structs may go thru BOTH paths. Floating point
4109 arguments will not. */
4110 /* Write this portion of the argument to a general
4111 purpose register. */
4112 if (argreg <= MIPS_LAST_ARG_REGNUM
4113 && !fp_register_arg_p (typecode, arg_type))
4115 LONGEST regval = extract_signed_integer (val, partial_len);
4116 /* Value may need to be sign extended, because
4117 mips_isa_regsize() != mips_abi_regsize(). */
4119 /* A non-floating-point argument being passed in a
4120 general register. If a struct or union, and if
4121 the remaining length is smaller than the register
4122 size, we have to adjust the register value on
4125 It does not seem to be necessary to do the
4126 same for integral types.
4128 Also don't do this adjustment on O64 binaries.
4130 cagney/2001-07-23: gdb/179: Also, GCC, when
4131 outputting LE O32 with sizeof (struct) <
4132 mips_abi_regsize(), generates a left shift as
4133 part of storing the argument in a register a
4134 register (the left shift isn't generated when
4135 sizeof (struct) >= mips_abi_regsize()). Since
4136 it is quite possible that this is GCC
4137 contradicting the LE/O32 ABI, GDB has not been
4138 adjusted to accommodate this. Either someone
4139 needs to demonstrate that the LE/O32 ABI
4140 specifies such a left shift OR this new ABI gets
4141 identified as such and GDB gets tweaked
4144 if (mips_abi_regsize (gdbarch) < 8
4145 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4146 && partial_len < mips_abi_regsize (gdbarch)
4147 && (typecode == TYPE_CODE_STRUCT ||
4148 typecode == TYPE_CODE_UNION))
4149 regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
4153 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4156 mips_abi_regsize (gdbarch)));
4157 write_register (argreg, regval);
4160 /* Prevent subsequent floating point arguments from
4161 being passed in floating point registers. */
4162 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
4168 /* Compute the the offset into the stack at which we
4169 will copy the next parameter.
4171 In older ABIs, the caller reserved space for
4172 registers that contained arguments. This was loosely
4173 refered to as their "home". Consequently, space is
4174 always allocated. */
4176 stack_offset += align_up (partial_len,
4177 mips_stack_argsize (gdbarch));
4181 fprintf_unfiltered (gdb_stdlog, "\n");
4184 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4186 /* Return adjusted stack pointer. */
4191 mips_o64_extract_return_value (struct type *valtype,
4192 char regbuf[], char *valbuf)
4194 struct return_value_word lo;
4195 struct return_value_word hi;
4196 return_value_location (valtype, &hi, &lo);
4198 memcpy (valbuf + lo.buf_offset,
4199 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) +
4200 lo.reg_offset, lo.len);
4203 memcpy (valbuf + hi.buf_offset,
4204 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) +
4205 hi.reg_offset, hi.len);
4209 mips_o64_store_return_value (struct type *valtype, char *valbuf)
4211 char raw_buffer[MAX_REGISTER_SIZE];
4212 struct return_value_word lo;
4213 struct return_value_word hi;
4214 return_value_location (valtype, &hi, &lo);
4216 memset (raw_buffer, 0, sizeof (raw_buffer));
4217 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4218 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg),
4219 raw_buffer, register_size (current_gdbarch,
4224 memset (raw_buffer, 0, sizeof (raw_buffer));
4225 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4226 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg),
4228 register_size (current_gdbarch,
4233 /* Floating point register management.
4235 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4236 64bit operations, these early MIPS cpus treat fp register pairs
4237 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4238 registers and offer a compatibility mode that emulates the MIPS2 fp
4239 model. When operating in MIPS2 fp compat mode, later cpu's split
4240 double precision floats into two 32-bit chunks and store them in
4241 consecutive fp regs. To display 64-bit floats stored in this
4242 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4243 Throw in user-configurable endianness and you have a real mess.
4245 The way this works is:
4246 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4247 double-precision value will be split across two logical registers.
4248 The lower-numbered logical register will hold the low-order bits,
4249 regardless of the processor's endianness.
4250 - If we are on a 64-bit processor, and we are looking for a
4251 single-precision value, it will be in the low ordered bits
4252 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4253 save slot in memory.
4254 - If we are in 64-bit mode, everything is straightforward.
4256 Note that this code only deals with "live" registers at the top of the
4257 stack. We will attempt to deal with saved registers later, when
4258 the raw/cooked register interface is in place. (We need a general
4259 interface that can deal with dynamic saved register sizes -- fp
4260 regs could be 32 bits wide in one frame and 64 on the frame above
4263 static struct type *
4264 mips_float_register_type (void)
4266 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4267 return builtin_type_ieee_single_big;
4269 return builtin_type_ieee_single_little;
4272 static struct type *
4273 mips_double_register_type (void)
4275 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4276 return builtin_type_ieee_double_big;
4278 return builtin_type_ieee_double_little;
4281 /* Copy a 32-bit single-precision value from the current frame
4282 into rare_buffer. */
4285 mips_read_fp_register_single (struct frame_info *frame, int regno,
4288 int raw_size = register_size (current_gdbarch, regno);
4289 char *raw_buffer = alloca (raw_size);
4291 if (!frame_register_read (frame, regno, raw_buffer))
4292 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4295 /* We have a 64-bit value for this register. Find the low-order
4299 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4304 memcpy (rare_buffer, raw_buffer + offset, 4);
4308 memcpy (rare_buffer, raw_buffer, 4);
4312 /* Copy a 64-bit double-precision value from the current frame into
4313 rare_buffer. This may include getting half of it from the next
4317 mips_read_fp_register_double (struct frame_info *frame, int regno,
4320 int raw_size = register_size (current_gdbarch, regno);
4322 if (raw_size == 8 && !mips2_fp_compat ())
4324 /* We have a 64-bit value for this register, and we should use
4326 if (!frame_register_read (frame, regno, rare_buffer))
4327 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4331 if ((regno - mips_regnum (current_gdbarch)->fp0) & 1)
4332 internal_error (__FILE__, __LINE__,
4333 "mips_read_fp_register_double: bad access to "
4334 "odd-numbered FP register");
4336 /* mips_read_fp_register_single will find the correct 32 bits from
4338 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4340 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4341 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4345 mips_read_fp_register_single (frame, regno, rare_buffer);
4346 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4352 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4354 { /* do values for FP (float) regs */
4356 double doub, flt1; /* doubles extracted from raw hex data */
4360 (char *) alloca (2 *
4361 register_size (current_gdbarch,
4362 mips_regnum (current_gdbarch)->fp0));
4364 fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
4365 fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
4368 if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ())
4370 /* 4-byte registers: Print hex and floating. Also print even
4371 numbered registers as doubles. */
4372 mips_read_fp_register_single (frame, regnum, raw_buffer);
4373 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4375 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
4378 fprintf_filtered (file, " flt: ");
4380 fprintf_filtered (file, " <invalid float> ");
4382 fprintf_filtered (file, "%-17.9g", flt1);
4384 if (regnum % 2 == 0)
4386 mips_read_fp_register_double (frame, regnum, raw_buffer);
4387 doub = unpack_double (mips_double_register_type (), raw_buffer,
4390 fprintf_filtered (file, " dbl: ");
4392 fprintf_filtered (file, "<invalid double>");
4394 fprintf_filtered (file, "%-24.17g", doub);
4399 /* Eight byte registers: print each one as hex, float and double. */
4400 mips_read_fp_register_single (frame, regnum, raw_buffer);
4401 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4403 mips_read_fp_register_double (frame, regnum, raw_buffer);
4404 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4407 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
4410 fprintf_filtered (file, " flt: ");
4412 fprintf_filtered (file, "<invalid float>");
4414 fprintf_filtered (file, "%-17.9g", flt1);
4416 fprintf_filtered (file, " dbl: ");
4418 fprintf_filtered (file, "<invalid double>");
4420 fprintf_filtered (file, "%-24.17g", doub);
4425 mips_print_register (struct ui_file *file, struct frame_info *frame,
4426 int regnum, int all)
4428 struct gdbarch *gdbarch = get_frame_arch (frame);
4429 char raw_buffer[MAX_REGISTER_SIZE];
4432 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4434 mips_print_fp_register (file, frame, regnum);
4438 /* Get the data in raw format. */
4439 if (!frame_register_read (frame, regnum, raw_buffer))
4441 fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum));
4445 fputs_filtered (REGISTER_NAME (regnum), file);
4447 /* The problem with printing numeric register names (r26, etc.) is that
4448 the user can't use them on input. Probably the best solution is to
4449 fix it so that either the numeric or the funky (a2, etc.) names
4450 are accepted on input. */
4451 if (regnum < MIPS_NUMREGS)
4452 fprintf_filtered (file, "(r%d): ", regnum);
4454 fprintf_filtered (file, ": ");
4456 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4458 register_size (current_gdbarch,
4459 regnum) - register_size (current_gdbarch, regnum);
4463 print_scalar_formatted (raw_buffer + offset,
4464 gdbarch_register_type (gdbarch, regnum), 'x', 0,
4468 /* Replacement for generic do_registers_info.
4469 Print regs in pretty columns. */
4472 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4475 fprintf_filtered (file, " ");
4476 mips_print_fp_register (file, frame, regnum);
4477 fprintf_filtered (file, "\n");
4482 /* Print a row's worth of GP (int) registers, with name labels above */
4485 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4488 struct gdbarch *gdbarch = get_frame_arch (frame);
4489 /* do values for GP (int) regs */
4490 char raw_buffer[MAX_REGISTER_SIZE];
4491 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4495 /* For GP registers, we print a separate row of names above the vals */
4496 fprintf_filtered (file, " ");
4497 for (col = 0, regnum = start_regnum;
4498 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4500 if (*REGISTER_NAME (regnum) == '\0')
4501 continue; /* unused register */
4502 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4504 break; /* end the row: reached FP register */
4505 fprintf_filtered (file,
4506 mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
4507 REGISTER_NAME (regnum));
4510 /* print the R0 to R31 names */
4511 if ((start_regnum % NUM_REGS) < MIPS_NUMREGS)
4512 fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS);
4514 fprintf_filtered (file, "\n ");
4516 /* now print the values in hex, 4 or 8 to the row */
4517 for (col = 0, regnum = start_regnum;
4518 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4520 if (*REGISTER_NAME (regnum) == '\0')
4521 continue; /* unused register */
4522 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4524 break; /* end row: reached FP register */
4525 /* OK: get the data in raw format. */
4526 if (!frame_register_read (frame, regnum, raw_buffer))
4527 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4528 /* pad small registers */
4530 byte < (mips_abi_regsize (current_gdbarch)
4531 - register_size (current_gdbarch, regnum)); byte++)
4532 printf_filtered (" ");
4533 /* Now print the register value in hex, endian order. */
4534 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4536 register_size (current_gdbarch,
4537 regnum) - register_size (current_gdbarch, regnum);
4538 byte < register_size (current_gdbarch, regnum); byte++)
4539 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4541 for (byte = register_size (current_gdbarch, regnum) - 1;
4543 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4544 fprintf_filtered (file, " ");
4547 if (col > 0) /* ie. if we actually printed anything... */
4548 fprintf_filtered (file, "\n");
4553 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4556 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4557 struct frame_info *frame, int regnum, int all)
4559 if (regnum != -1) /* do one specified register */
4561 gdb_assert (regnum >= NUM_REGS);
4562 if (*(REGISTER_NAME (regnum)) == '\0')
4563 error ("Not a valid register for the current processor type");
4565 mips_print_register (file, frame, regnum, 0);
4566 fprintf_filtered (file, "\n");
4569 /* do all (or most) registers */
4572 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4574 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4577 if (all) /* true for "INFO ALL-REGISTERS" command */
4578 regnum = print_fp_register_row (file, frame, regnum);
4580 regnum += MIPS_NUMREGS; /* skip floating point regs */
4583 regnum = print_gp_register_row (file, frame, regnum);
4588 /* Is this a branch with a delay slot? */
4590 static int is_delayed (unsigned long);
4593 is_delayed (unsigned long insn)
4596 for (i = 0; i < NUMOPCODES; ++i)
4597 if (mips_opcodes[i].pinfo != INSN_MACRO
4598 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4600 return (i < NUMOPCODES
4601 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4602 | INSN_COND_BRANCH_DELAY
4603 | INSN_COND_BRANCH_LIKELY)));
4607 mips_step_skips_delay (CORE_ADDR pc)
4609 char buf[MIPS_INSTLEN];
4611 /* There is no branch delay slot on MIPS16. */
4612 if (pc_is_mips16 (pc))
4615 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4616 /* If error reading memory, guess that it is not a delayed branch. */
4618 return is_delayed ((unsigned long)
4619 extract_unsigned_integer (buf, MIPS_INSTLEN));
4622 /* Skip the PC past function prologue instructions (32-bit version).
4623 This is a helper function for mips_skip_prologue. */
4626 mips32_skip_prologue (CORE_ADDR pc)
4630 int seen_sp_adjust = 0;
4631 int load_immediate_bytes = 0;
4633 /* Find an upper bound on the prologue. */
4634 end_pc = skip_prologue_using_sal (pc);
4636 end_pc = pc + 100; /* Magic. */
4638 /* Skip the typical prologue instructions. These are the stack adjustment
4639 instruction and the instructions that save registers on the stack
4640 or in the gcc frame. */
4641 for (; pc < end_pc; pc += MIPS_INSTLEN)
4643 unsigned long high_word;
4645 inst = mips_fetch_instruction (pc);
4646 high_word = (inst >> 16) & 0xffff;
4648 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4649 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4651 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4652 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4654 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4655 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4656 && (inst & 0x001F0000)) /* reg != $zero */
4659 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4661 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4663 continue; /* reg != $zero */
4665 /* move $s8,$sp. With different versions of gas this will be either
4666 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4667 Accept any one of these. */
4668 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4671 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4673 else if (high_word == 0x3c1c) /* lui $gp,n */
4675 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4677 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4678 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4680 /* The following instructions load $at or $t0 with an immediate
4681 value in preparation for a stack adjustment via
4682 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4683 a local variable, so we accept them only before a stack adjustment
4684 instruction was seen. */
4685 else if (!seen_sp_adjust)
4687 if (high_word == 0x3c01 || /* lui $at,n */
4688 high_word == 0x3c08) /* lui $t0,n */
4690 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4693 else if (high_word == 0x3421 || /* ori $at,$at,n */
4694 high_word == 0x3508 || /* ori $t0,$t0,n */
4695 high_word == 0x3401 || /* ori $at,$zero,n */
4696 high_word == 0x3408) /* ori $t0,$zero,n */
4698 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4708 /* In a frameless function, we might have incorrectly
4709 skipped some load immediate instructions. Undo the skipping
4710 if the load immediate was not followed by a stack adjustment. */
4711 if (load_immediate_bytes && !seen_sp_adjust)
4712 pc -= load_immediate_bytes;
4716 /* Skip the PC past function prologue instructions (16-bit version).
4717 This is a helper function for mips_skip_prologue. */
4720 mips16_skip_prologue (CORE_ADDR pc)
4723 int extend_bytes = 0;
4724 int prev_extend_bytes;
4726 /* Table of instructions likely to be found in a function prologue. */
4729 unsigned short inst;
4730 unsigned short mask;
4736 , /* addiu $sp,offset */
4739 , /* daddiu $sp,offset */
4742 , /* sw reg,n($sp) */
4745 , /* sd reg,n($sp) */
4748 , /* sw $ra,n($sp) */
4751 , /* sd $ra,n($sp) */
4757 , /* sw $a0-$a3,n($s1) */
4760 , /* move reg,$a0-$a3 */
4763 , /* entry pseudo-op */
4766 , /* addiu $s1,$sp,n */
4768 0, 0} /* end of table marker */
4771 /* Find an upper bound on the prologue. */
4772 end_pc = skip_prologue_using_sal (pc);
4774 end_pc = pc + 100; /* Magic. */
4776 /* Skip the typical prologue instructions. These are the stack adjustment
4777 instruction and the instructions that save registers on the stack
4778 or in the gcc frame. */
4779 for (; pc < end_pc; pc += MIPS16_INSTLEN)
4781 unsigned short inst;
4784 inst = mips_fetch_instruction (pc);
4786 /* Normally we ignore an extend instruction. However, if it is
4787 not followed by a valid prologue instruction, we must adjust
4788 the pc back over the extend so that it won't be considered
4789 part of the prologue. */
4790 if ((inst & 0xf800) == 0xf000) /* extend */
4792 extend_bytes = MIPS16_INSTLEN;
4795 prev_extend_bytes = extend_bytes;
4798 /* Check for other valid prologue instructions besides extend. */
4799 for (i = 0; table[i].mask != 0; i++)
4800 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4802 if (table[i].mask != 0) /* it was in table? */
4803 continue; /* ignore it */
4807 /* Return the current pc, adjusted backwards by 2 if
4808 the previous instruction was an extend. */
4809 return pc - prev_extend_bytes;
4815 /* To skip prologues, I use this predicate. Returns either PC itself
4816 if the code at PC does not look like a function prologue; otherwise
4817 returns an address that (if we're lucky) follows the prologue. If
4818 LENIENT, then we must skip everything which is involved in setting
4819 up the frame (it's OK to skip more, just so long as we don't skip
4820 anything which might clobber the registers which are being saved.
4821 We must skip more in the case where part of the prologue is in the
4822 delay slot of a non-prologue instruction). */
4825 mips_skip_prologue (CORE_ADDR pc)
4827 /* See if we can determine the end of the prologue via the symbol table.
4828 If so, then return either PC, or the PC after the prologue, whichever
4831 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4833 if (post_prologue_pc != 0)
4834 return max (pc, post_prologue_pc);
4836 /* Can't determine prologue from the symbol table, need to examine
4839 if (pc_is_mips16 (pc))
4840 return mips16_skip_prologue (pc);
4842 return mips32_skip_prologue (pc);
4845 /* Root of all "set mips "/"show mips " commands. This will eventually be
4846 used for all MIPS-specific commands. */
4849 show_mips_command (char *args, int from_tty)
4851 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4855 set_mips_command (char *args, int from_tty)
4858 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4859 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4862 /* Commands to show/set the MIPS FPU type. */
4865 show_mipsfpu_command (char *args, int from_tty)
4868 switch (MIPS_FPU_TYPE)
4870 case MIPS_FPU_SINGLE:
4871 fpu = "single-precision";
4873 case MIPS_FPU_DOUBLE:
4874 fpu = "double-precision";
4877 fpu = "absent (none)";
4880 internal_error (__FILE__, __LINE__, "bad switch");
4882 if (mips_fpu_type_auto)
4884 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4888 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4893 set_mipsfpu_command (char *args, int from_tty)
4896 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4897 show_mipsfpu_command (args, from_tty);
4901 set_mipsfpu_single_command (char *args, int from_tty)
4903 struct gdbarch_info info;
4904 gdbarch_info_init (&info);
4905 mips_fpu_type = MIPS_FPU_SINGLE;
4906 mips_fpu_type_auto = 0;
4907 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4908 instead of relying on globals. Doing that would let generic code
4909 handle the search for this specific architecture. */
4910 if (!gdbarch_update_p (info))
4911 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4915 set_mipsfpu_double_command (char *args, int from_tty)
4917 struct gdbarch_info info;
4918 gdbarch_info_init (&info);
4919 mips_fpu_type = MIPS_FPU_DOUBLE;
4920 mips_fpu_type_auto = 0;
4921 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4922 instead of relying on globals. Doing that would let generic code
4923 handle the search for this specific architecture. */
4924 if (!gdbarch_update_p (info))
4925 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4929 set_mipsfpu_none_command (char *args, int from_tty)
4931 struct gdbarch_info info;
4932 gdbarch_info_init (&info);
4933 mips_fpu_type = MIPS_FPU_NONE;
4934 mips_fpu_type_auto = 0;
4935 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4936 instead of relying on globals. Doing that would let generic code
4937 handle the search for this specific architecture. */
4938 if (!gdbarch_update_p (info))
4939 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4943 set_mipsfpu_auto_command (char *args, int from_tty)
4945 mips_fpu_type_auto = 1;
4948 /* Attempt to identify the particular processor model by reading the
4949 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4950 the relevant processor still exists (it dates back to '94) and
4951 secondly this is not the way to do this. The processor type should
4952 be set by forcing an architecture change. */
4955 deprecated_mips_set_processor_regs_hack (void)
4957 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4960 prid = read_register (PRID_REGNUM);
4962 if ((prid & ~0xf) == 0x700)
4963 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4966 /* Just like reinit_frame_cache, but with the right arguments to be
4967 callable as an sfunc. */
4970 reinit_frame_cache_sfunc (char *args, int from_tty,
4971 struct cmd_list_element *c)
4973 reinit_frame_cache ();
4977 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4979 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4980 mips_extra_func_info_t proc_desc;
4982 /* Search for the function containing this address. Set the low bit
4983 of the address when searching, in case we were given an even address
4984 that is the start of a 16-bit function. If we didn't do this,
4985 the search would fail because the symbol table says the function
4986 starts at an odd address, i.e. 1 byte past the given address. */
4987 memaddr = ADDR_BITS_REMOVE (memaddr);
4988 proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL);
4990 /* Make an attempt to determine if this is a 16-bit function. If
4991 the procedure descriptor exists and the address therein is odd,
4992 it's definitely a 16-bit function. Otherwise, we have to just
4993 guess that if the address passed in is odd, it's 16-bits. */
4994 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4995 disassembler needs to be able to locally determine the ISA, and
4996 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5000 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
5001 info->mach = bfd_mach_mips16;
5005 if (pc_is_mips16 (memaddr))
5006 info->mach = bfd_mach_mips16;
5009 /* Round down the instruction address to the appropriate boundary. */
5010 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
5012 /* Set the disassembler options. */
5013 if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64)
5015 /* Set up the disassembler info, so that we get the right
5016 register names from libopcodes. */
5017 if (tdep->mips_abi == MIPS_ABI_N32)
5018 info->disassembler_options = "gpr-names=n32";
5020 info->disassembler_options = "gpr-names=64";
5021 info->flavour = bfd_target_elf_flavour;
5024 /* This string is not recognized explicitly by the disassembler,
5025 but it tells the disassembler to not try to guess the ABI from
5026 the bfd elf headers, such that, if the user overrides the ABI
5027 of a program linked as NewABI, the disassembly will follow the
5028 register naming conventions specified by the user. */
5029 info->disassembler_options = "gpr-names=32";
5031 /* Call the appropriate disassembler based on the target endian-ness. */
5032 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5033 return print_insn_big_mips (memaddr, info);
5035 return print_insn_little_mips (memaddr, info);
5038 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5039 counter value to determine whether a 16- or 32-bit breakpoint should be
5040 used. It returns a pointer to a string of bytes that encode a breakpoint
5041 instruction, stores the length of the string to *lenptr, and adjusts pc
5042 (if necessary) to point to the actual memory location where the
5043 breakpoint should be inserted. */
5045 static const unsigned char *
5046 mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
5048 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5050 if (pc_is_mips16 (*pcptr))
5052 static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 };
5053 *pcptr = unmake_mips16_addr (*pcptr);
5054 *lenptr = sizeof (mips16_big_breakpoint);
5055 return mips16_big_breakpoint;
5059 /* The IDT board uses an unusual breakpoint value, and
5060 sometimes gets confused when it sees the usual MIPS
5061 breakpoint instruction. */
5062 static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd };
5063 static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
5064 static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
5066 *lenptr = sizeof (big_breakpoint);
5068 if (strcmp (target_shortname, "mips") == 0)
5069 return idt_big_breakpoint;
5070 else if (strcmp (target_shortname, "ddb") == 0
5071 || strcmp (target_shortname, "pmon") == 0
5072 || strcmp (target_shortname, "lsi") == 0)
5073 return pmon_big_breakpoint;
5075 return big_breakpoint;
5080 if (pc_is_mips16 (*pcptr))
5082 static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 };
5083 *pcptr = unmake_mips16_addr (*pcptr);
5084 *lenptr = sizeof (mips16_little_breakpoint);
5085 return mips16_little_breakpoint;
5089 static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 };
5090 static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
5091 static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
5093 *lenptr = sizeof (little_breakpoint);
5095 if (strcmp (target_shortname, "mips") == 0)
5096 return idt_little_breakpoint;
5097 else if (strcmp (target_shortname, "ddb") == 0
5098 || strcmp (target_shortname, "pmon") == 0
5099 || strcmp (target_shortname, "lsi") == 0)
5100 return pmon_little_breakpoint;
5102 return little_breakpoint;
5107 /* If PC is in a mips16 call or return stub, return the address of the target
5108 PC, which is either the callee or the caller. There are several
5109 cases which must be handled:
5111 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5112 target PC is in $31 ($ra).
5113 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5114 and the target PC is in $2.
5115 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5116 before the jal instruction, this is effectively a call stub
5117 and the the target PC is in $2. Otherwise this is effectively
5118 a return stub and the target PC is in $18.
5120 See the source code for the stubs in gcc/config/mips/mips16.S for
5123 This function implements the SKIP_TRAMPOLINE_CODE macro.
5127 mips_skip_stub (CORE_ADDR pc)
5130 CORE_ADDR start_addr;
5132 /* Find the starting address and name of the function containing the PC. */
5133 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5136 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5137 target PC is in $31 ($ra). */
5138 if (strcmp (name, "__mips16_ret_sf") == 0
5139 || strcmp (name, "__mips16_ret_df") == 0)
5140 return read_signed_register (RA_REGNUM);
5142 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5144 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5145 and the target PC is in $2. */
5146 if (name[19] >= '0' && name[19] <= '9')
5147 return read_signed_register (2);
5149 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5150 before the jal instruction, this is effectively a call stub
5151 and the the target PC is in $2. Otherwise this is effectively
5152 a return stub and the target PC is in $18. */
5153 else if (name[19] == 's' || name[19] == 'd')
5155 if (pc == start_addr)
5157 /* Check if the target of the stub is a compiler-generated
5158 stub. Such a stub for a function bar might have a name
5159 like __fn_stub_bar, and might look like this:
5164 la $1,bar (becomes a lui/addiu pair)
5166 So scan down to the lui/addi and extract the target
5167 address from those two instructions. */
5169 CORE_ADDR target_pc = read_signed_register (2);
5173 /* See if the name of the target function is __fn_stub_*. */
5174 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
5177 if (strncmp (name, "__fn_stub_", 10) != 0
5178 && strcmp (name, "etext") != 0
5179 && strcmp (name, "_etext") != 0)
5182 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5183 The limit on the search is arbitrarily set to 20
5184 instructions. FIXME. */
5185 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5187 inst = mips_fetch_instruction (target_pc);
5188 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5189 pc = (inst << 16) & 0xffff0000; /* high word */
5190 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5191 return pc | (inst & 0xffff); /* low word */
5194 /* Couldn't find the lui/addui pair, so return stub address. */
5198 /* This is the 'return' part of a call stub. The return
5199 address is in $r18. */
5200 return read_signed_register (18);
5203 return 0; /* not a stub */
5207 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5208 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5211 mips_in_call_stub (CORE_ADDR pc, char *name)
5213 CORE_ADDR start_addr;
5215 /* Find the starting address of the function containing the PC. If the
5216 caller didn't give us a name, look it up at the same time. */
5217 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) ==
5221 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5223 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5224 if (name[19] >= '0' && name[19] <= '9')
5226 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5227 before the jal instruction, this is effectively a call stub. */
5228 else if (name[19] == 's' || name[19] == 'd')
5229 return pc == start_addr;
5232 return 0; /* not a stub */
5236 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5237 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5240 mips_in_return_stub (CORE_ADDR pc, char *name)
5242 CORE_ADDR start_addr;
5244 /* Find the starting address of the function containing the PC. */
5245 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5248 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5249 if (strcmp (name, "__mips16_ret_sf") == 0
5250 || strcmp (name, "__mips16_ret_df") == 0)
5253 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5254 i.e. after the jal instruction, this is effectively a return stub. */
5255 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5256 && (name[19] == 's' || name[19] == 'd') && pc != start_addr)
5259 return 0; /* not a stub */
5263 /* Return non-zero if the PC is in a library helper function that should
5264 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5267 mips_ignore_helper (CORE_ADDR pc)
5271 /* Find the starting address and name of the function containing the PC. */
5272 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5275 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5276 that we want to ignore. */
5277 return (strcmp (name, "__mips16_ret_sf") == 0
5278 || strcmp (name, "__mips16_ret_df") == 0);
5282 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5283 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5286 mips_stab_reg_to_regnum (int num)
5289 if (num >= 0 && num < 32)
5291 else if (num >= 38 && num < 70)
5292 regnum = num + mips_regnum (current_gdbarch)->fp0 - 38;
5294 regnum = mips_regnum (current_gdbarch)->hi;
5296 regnum = mips_regnum (current_gdbarch)->lo;
5298 /* This will hopefully (eventually) provoke a warning. Should
5299 we be calling complaint() here? */
5300 return NUM_REGS + NUM_PSEUDO_REGS;
5301 return NUM_REGS + regnum;
5305 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5306 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5309 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
5312 if (num >= 0 && num < 32)
5314 else if (num >= 32 && num < 64)
5315 regnum = num + mips_regnum (current_gdbarch)->fp0 - 32;
5317 regnum = mips_regnum (current_gdbarch)->hi;
5319 regnum = mips_regnum (current_gdbarch)->lo;
5321 /* This will hopefully (eventually) provoke a warning. Should we
5322 be calling complaint() here? */
5323 return NUM_REGS + NUM_PSEUDO_REGS;
5324 return NUM_REGS + regnum;
5328 mips_register_sim_regno (int regnum)
5330 /* Only makes sense to supply raw registers. */
5331 gdb_assert (regnum >= 0 && regnum < NUM_REGS);
5332 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5333 decide if it is valid. Should instead define a standard sim/gdb
5334 register numbering scheme. */
5335 if (REGISTER_NAME (NUM_REGS + regnum) != NULL
5336 && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0')
5339 return LEGACY_SIM_REGNO_IGNORE;
5343 /* Convert an integer into an address. By first converting the value
5344 into a pointer and then extracting it signed, the address is
5345 guarenteed to be correctly sign extended. */
5348 mips_integer_to_address (struct type *type, void *buf)
5350 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5351 LONGEST val = unpack_long (type, buf);
5352 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5353 return extract_signed_integer (tmp,
5354 TYPE_LENGTH (builtin_type_void_data_ptr));
5358 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5360 enum mips_abi *abip = (enum mips_abi *) obj;
5361 const char *name = bfd_get_section_name (abfd, sect);
5363 if (*abip != MIPS_ABI_UNKNOWN)
5366 if (strncmp (name, ".mdebug.", 8) != 0)
5369 if (strcmp (name, ".mdebug.abi32") == 0)
5370 *abip = MIPS_ABI_O32;
5371 else if (strcmp (name, ".mdebug.abiN32") == 0)
5372 *abip = MIPS_ABI_N32;
5373 else if (strcmp (name, ".mdebug.abi64") == 0)
5374 *abip = MIPS_ABI_N64;
5375 else if (strcmp (name, ".mdebug.abiO64") == 0)
5376 *abip = MIPS_ABI_O64;
5377 else if (strcmp (name, ".mdebug.eabi32") == 0)
5378 *abip = MIPS_ABI_EABI32;
5379 else if (strcmp (name, ".mdebug.eabi64") == 0)
5380 *abip = MIPS_ABI_EABI64;
5382 warning ("unsupported ABI %s.", name + 8);
5385 static enum mips_abi
5386 global_mips_abi (void)
5390 for (i = 0; mips_abi_strings[i] != NULL; i++)
5391 if (mips_abi_strings[i] == mips_abi_string)
5392 return (enum mips_abi) i;
5394 internal_error (__FILE__, __LINE__, "unknown ABI string");
5397 static struct gdbarch *
5398 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5400 struct gdbarch *gdbarch;
5401 struct gdbarch_tdep *tdep;
5403 enum mips_abi mips_abi, found_abi, wanted_abi;
5405 enum mips_fpu_type fpu_type;
5407 /* First of all, extract the elf_flags, if available. */
5408 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5409 elf_flags = elf_elfheader (info.abfd)->e_flags;
5410 else if (arches != NULL)
5411 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5415 fprintf_unfiltered (gdb_stdlog,
5416 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5418 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5419 switch ((elf_flags & EF_MIPS_ABI))
5421 case E_MIPS_ABI_O32:
5422 found_abi = MIPS_ABI_O32;
5424 case E_MIPS_ABI_O64:
5425 found_abi = MIPS_ABI_O64;
5427 case E_MIPS_ABI_EABI32:
5428 found_abi = MIPS_ABI_EABI32;
5430 case E_MIPS_ABI_EABI64:
5431 found_abi = MIPS_ABI_EABI64;
5434 if ((elf_flags & EF_MIPS_ABI2))
5435 found_abi = MIPS_ABI_N32;
5437 found_abi = MIPS_ABI_UNKNOWN;
5441 /* GCC creates a pseudo-section whose name describes the ABI. */
5442 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5443 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5445 /* If we have no useful BFD information, use the ABI from the last
5446 MIPS architecture (if there is one). */
5447 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5448 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5450 /* Try the architecture for any hint of the correct ABI. */
5451 if (found_abi == MIPS_ABI_UNKNOWN
5452 && info.bfd_arch_info != NULL
5453 && info.bfd_arch_info->arch == bfd_arch_mips)
5455 switch (info.bfd_arch_info->mach)
5457 case bfd_mach_mips3900:
5458 found_abi = MIPS_ABI_EABI32;
5460 case bfd_mach_mips4100:
5461 case bfd_mach_mips5000:
5462 found_abi = MIPS_ABI_EABI64;
5464 case bfd_mach_mips8000:
5465 case bfd_mach_mips10000:
5466 /* On Irix, ELF64 executables use the N64 ABI. The
5467 pseudo-sections which describe the ABI aren't present
5468 on IRIX. (Even for executables created by gcc.) */
5469 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5470 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5471 found_abi = MIPS_ABI_N64;
5473 found_abi = MIPS_ABI_N32;
5479 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5482 /* What has the user specified from the command line? */
5483 wanted_abi = global_mips_abi ();
5485 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5488 /* Now that we have found what the ABI for this binary would be,
5489 check whether the user is overriding it. */
5490 if (wanted_abi != MIPS_ABI_UNKNOWN)
5491 mips_abi = wanted_abi;
5492 else if (found_abi != MIPS_ABI_UNKNOWN)
5493 mips_abi = found_abi;
5495 mips_abi = MIPS_ABI_O32;
5497 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5500 /* Also used when doing an architecture lookup. */
5502 fprintf_unfiltered (gdb_stdlog,
5503 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5504 mips64_transfers_32bit_regs_p);
5506 /* Determine the MIPS FPU type. */
5507 if (!mips_fpu_type_auto)
5508 fpu_type = mips_fpu_type;
5509 else if (info.bfd_arch_info != NULL
5510 && info.bfd_arch_info->arch == bfd_arch_mips)
5511 switch (info.bfd_arch_info->mach)
5513 case bfd_mach_mips3900:
5514 case bfd_mach_mips4100:
5515 case bfd_mach_mips4111:
5516 case bfd_mach_mips4120:
5517 fpu_type = MIPS_FPU_NONE;
5519 case bfd_mach_mips4650:
5520 fpu_type = MIPS_FPU_SINGLE;
5523 fpu_type = MIPS_FPU_DOUBLE;
5526 else if (arches != NULL)
5527 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5529 fpu_type = MIPS_FPU_DOUBLE;
5531 fprintf_unfiltered (gdb_stdlog,
5532 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5534 /* try to find a pre-existing architecture */
5535 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5537 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5539 /* MIPS needs to be pedantic about which ABI the object is
5541 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5543 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5545 /* Need to be pedantic about which register virtual size is
5547 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5548 != mips64_transfers_32bit_regs_p)
5550 /* Be pedantic about which FPU is selected. */
5551 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5553 return arches->gdbarch;
5556 /* Need a new architecture. Fill in a target specific vector. */
5557 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5558 gdbarch = gdbarch_alloc (&info, tdep);
5559 tdep->elf_flags = elf_flags;
5560 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5561 tdep->found_abi = found_abi;
5562 tdep->mips_abi = mips_abi;
5563 tdep->mips_fpu_type = fpu_type;
5565 /* Initially set everything according to the default ABI/ISA. */
5566 set_gdbarch_short_bit (gdbarch, 16);
5567 set_gdbarch_int_bit (gdbarch, 32);
5568 set_gdbarch_float_bit (gdbarch, 32);
5569 set_gdbarch_double_bit (gdbarch, 64);
5570 set_gdbarch_long_double_bit (gdbarch, 64);
5571 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5572 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5573 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5575 set_gdbarch_elf_make_msymbol_special (gdbarch,
5576 mips_elf_make_msymbol_special);
5578 /* Fill in the OS dependant register numbers and names. */
5580 const char **reg_names;
5581 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
5582 struct mips_regnum);
5583 if (info.osabi == GDB_OSABI_IRIX)
5588 regnum->badvaddr = 66;
5591 regnum->fp_control_status = 69;
5592 regnum->fp_implementation_revision = 70;
5594 reg_names = mips_irix_reg_names;
5598 regnum->lo = MIPS_EMBED_LO_REGNUM;
5599 regnum->hi = MIPS_EMBED_HI_REGNUM;
5600 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5601 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5602 regnum->pc = MIPS_EMBED_PC_REGNUM;
5603 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5604 regnum->fp_control_status = 70;
5605 regnum->fp_implementation_revision = 71;
5607 if (info.bfd_arch_info != NULL
5608 && info.bfd_arch_info->mach == bfd_mach_mips3900)
5609 reg_names = mips_tx39_reg_names;
5611 reg_names = mips_generic_reg_names;
5613 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5614 replaced by read_pc? */
5615 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
5616 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
5617 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
5618 set_gdbarch_num_regs (gdbarch, num_regs);
5619 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5620 set_gdbarch_register_name (gdbarch, mips_register_name);
5621 tdep->mips_processor_reg_names = reg_names;
5622 tdep->regnum = regnum;
5628 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5629 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
5630 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5631 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5632 tdep->default_mask_address_p = 0;
5633 set_gdbarch_long_bit (gdbarch, 32);
5634 set_gdbarch_ptr_bit (gdbarch, 32);
5635 set_gdbarch_long_long_bit (gdbarch, 64);
5638 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5639 set_gdbarch_deprecated_store_return_value (gdbarch,
5640 mips_o64_store_return_value);
5641 set_gdbarch_deprecated_extract_return_value (gdbarch,
5642 mips_o64_extract_return_value);
5643 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5644 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5645 tdep->default_mask_address_p = 0;
5646 set_gdbarch_long_bit (gdbarch, 32);
5647 set_gdbarch_ptr_bit (gdbarch, 32);
5648 set_gdbarch_long_long_bit (gdbarch, 64);
5649 set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention);
5651 case MIPS_ABI_EABI32:
5652 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5653 set_gdbarch_deprecated_store_return_value (gdbarch,
5654 mips_eabi_store_return_value);
5655 set_gdbarch_deprecated_extract_return_value (gdbarch,
5656 mips_eabi_extract_return_value);
5657 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5658 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5659 tdep->default_mask_address_p = 0;
5660 set_gdbarch_long_bit (gdbarch, 32);
5661 set_gdbarch_ptr_bit (gdbarch, 32);
5662 set_gdbarch_long_long_bit (gdbarch, 64);
5663 set_gdbarch_deprecated_reg_struct_has_addr
5664 (gdbarch, mips_eabi_reg_struct_has_addr);
5665 set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention);
5667 case MIPS_ABI_EABI64:
5668 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5669 set_gdbarch_deprecated_store_return_value (gdbarch,
5670 mips_eabi_store_return_value);
5671 set_gdbarch_deprecated_extract_return_value (gdbarch,
5672 mips_eabi_extract_return_value);
5673 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5674 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5675 tdep->default_mask_address_p = 0;
5676 set_gdbarch_long_bit (gdbarch, 64);
5677 set_gdbarch_ptr_bit (gdbarch, 64);
5678 set_gdbarch_long_long_bit (gdbarch, 64);
5679 set_gdbarch_deprecated_reg_struct_has_addr
5680 (gdbarch, mips_eabi_reg_struct_has_addr);
5681 set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention);
5684 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5685 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5686 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5687 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5688 tdep->default_mask_address_p = 0;
5689 set_gdbarch_long_bit (gdbarch, 32);
5690 set_gdbarch_ptr_bit (gdbarch, 32);
5691 set_gdbarch_long_long_bit (gdbarch, 64);
5694 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5695 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5696 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5697 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5698 tdep->default_mask_address_p = 0;
5699 set_gdbarch_long_bit (gdbarch, 64);
5700 set_gdbarch_ptr_bit (gdbarch, 64);
5701 set_gdbarch_long_long_bit (gdbarch, 64);
5704 internal_error (__FILE__, __LINE__, "unknown ABI in switch");
5707 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5708 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5711 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5712 flag in object files because to do so would make it impossible to
5713 link with libraries compiled without "-gp32". This is
5714 unnecessarily restrictive.
5716 We could solve this problem by adding "-gp32" multilibs to gcc,
5717 but to set this flag before gcc is built with such multilibs will
5718 break too many systems.''
5720 But even more unhelpfully, the default linker output target for
5721 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5722 for 64-bit programs - you need to change the ABI to change this,
5723 and not all gcc targets support that currently. Therefore using
5724 this flag to detect 32-bit mode would do the wrong thing given
5725 the current gcc - it would make GDB treat these 64-bit programs
5726 as 32-bit programs by default. */
5728 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5729 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5730 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5732 /* Add/remove bits from an address. The MIPS needs be careful to
5733 ensure that all 32 bit addresses are sign extended to 64 bits. */
5734 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5736 /* Unwind the frame. */
5737 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5738 set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id);
5740 /* Map debug register numbers onto internal register numbers. */
5741 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5742 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5743 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5744 set_gdbarch_dwarf_reg_to_regnum (gdbarch,
5745 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5746 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5747 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5748 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5750 /* MIPS version of CALL_DUMMY */
5752 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5753 replaced by a command, and all targets will default to on stack
5754 (regardless of the stack's execute status). */
5755 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5756 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5758 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
5759 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
5760 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
5762 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5763 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5765 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5767 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5768 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5769 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5771 set_gdbarch_register_type (gdbarch, mips_register_type);
5773 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5775 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
5777 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5778 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5779 need to all be folded into the target vector. Since they are
5780 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5781 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5783 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
5785 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
5787 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5788 to support MIPS16. This is a bad thing. Make sure not to do it
5789 if we have an OS ABI that actually supports shared libraries, since
5790 shared library support is more important. If we have an OS someday
5791 that supports both shared libraries and MIPS16, we'll have to find
5792 a better place for these. */
5793 if (info.osabi == GDB_OSABI_UNKNOWN)
5795 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
5796 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
5799 /* Hook in OS ABI-specific overrides, if they have been registered. */
5800 gdbarch_init_osabi (info, gdbarch);
5802 /* Unwind the frame. */
5803 frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer);
5804 frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer);
5810 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
5812 struct gdbarch_info info;
5814 /* Force the architecture to update, and (if it's a MIPS architecture)
5815 mips_gdbarch_init will take care of the rest. */
5816 gdbarch_info_init (&info);
5817 gdbarch_update_p (info);
5820 /* Print out which MIPS ABI is in use. */
5823 show_mips_abi (char *ignore_args, int from_tty)
5825 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
5827 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5830 enum mips_abi global_abi = global_mips_abi ();
5831 enum mips_abi actual_abi = mips_abi (current_gdbarch);
5832 const char *actual_abi_str = mips_abi_strings[actual_abi];
5834 if (global_abi == MIPS_ABI_UNKNOWN)
5836 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5838 else if (global_abi == actual_abi)
5840 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5844 /* Probably shouldn't happen... */
5846 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5847 actual_abi_str, mips_abi_strings[global_abi]);
5853 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
5855 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
5859 int ef_mips_32bitmode;
5860 /* determine the ISA */
5861 switch (tdep->elf_flags & EF_MIPS_ARCH)
5879 /* determine the size of a pointer */
5880 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
5881 fprintf_unfiltered (file,
5882 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5884 fprintf_unfiltered (file,
5885 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5887 fprintf_unfiltered (file,
5888 "mips_dump_tdep: ef_mips_arch = %d\n",
5890 fprintf_unfiltered (file,
5891 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5892 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
5893 fprintf_unfiltered (file,
5894 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5895 mips_mask_address_p (tdep),
5896 tdep->default_mask_address_p);
5898 fprintf_unfiltered (file,
5899 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5900 MIPS_DEFAULT_FPU_TYPE,
5901 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
5902 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5903 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5905 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI);
5906 fprintf_unfiltered (file,
5907 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5909 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
5910 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5911 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5913 fprintf_unfiltered (file,
5914 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5915 mips_stack_argsize (current_gdbarch));
5916 fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM);
5917 fprintf_unfiltered (file,
5918 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5919 XSTRING (ADDR_BITS_REMOVE (ADDR)));
5920 fprintf_unfiltered (file,
5921 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5922 XSTRING (ATTACH_DETACH));
5923 fprintf_unfiltered (file,
5924 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5925 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
5926 fprintf_unfiltered (file,
5927 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5928 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
5929 fprintf_unfiltered (file,
5930 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5931 FIRST_EMBED_REGNUM);
5932 fprintf_unfiltered (file,
5933 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5934 XSTRING (IGNORE_HELPER_CALL (PC)));
5935 fprintf_unfiltered (file,
5936 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5937 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
5938 fprintf_unfiltered (file,
5939 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5940 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
5941 fprintf_unfiltered (file,
5942 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5944 #ifdef MACHINE_CPROC_FP_OFFSET
5945 fprintf_unfiltered (file,
5946 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5947 MACHINE_CPROC_FP_OFFSET);
5949 #ifdef MACHINE_CPROC_PC_OFFSET
5950 fprintf_unfiltered (file,
5951 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5952 MACHINE_CPROC_PC_OFFSET);
5954 #ifdef MACHINE_CPROC_SP_OFFSET
5955 fprintf_unfiltered (file,
5956 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5957 MACHINE_CPROC_SP_OFFSET);
5959 fprintf_unfiltered (file,
5960 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5962 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5963 fprintf_unfiltered (file,
5964 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5965 fprintf_unfiltered (file,
5966 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN);
5967 fprintf_unfiltered (file,
5968 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5969 MIPS_LAST_ARG_REGNUM,
5970 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
5971 fprintf_unfiltered (file,
5972 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS);
5973 fprintf_unfiltered (file,
5974 "mips_dump_tdep: mips_abi_regsize() = %d\n",
5975 mips_abi_regsize (current_gdbarch));
5976 fprintf_unfiltered (file,
5977 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM);
5978 fprintf_unfiltered (file,
5979 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5980 fprintf_unfiltered (file,
5981 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5982 fprintf_unfiltered (file,
5983 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5984 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5985 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5986 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5987 fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5988 fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5989 fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n");
5990 fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n");
5991 fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5992 fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n");
5993 fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM);
5994 fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM);
5996 fprintf_unfiltered (file,
5997 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES);
6000 fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP);
6003 fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC);
6005 fprintf_unfiltered (file,
6006 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6007 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
6008 fprintf_unfiltered (file,
6009 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6010 fprintf_unfiltered (file,
6011 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6012 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
6013 fprintf_unfiltered (file,
6014 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6015 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
6016 fprintf_unfiltered (file,
6017 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6018 SOFTWARE_SINGLE_STEP_P ());
6019 fprintf_unfiltered (file,
6020 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6021 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6022 #ifdef STACK_END_ADDR
6023 fprintf_unfiltered (file,
6024 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6027 fprintf_unfiltered (file,
6028 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6029 XSTRING (STEP_SKIPS_DELAY (PC)));
6030 fprintf_unfiltered (file,
6031 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6032 STEP_SKIPS_DELAY_P);
6033 fprintf_unfiltered (file,
6034 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6035 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6036 fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM);
6037 fprintf_unfiltered (file,
6038 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6039 fprintf_unfiltered (file,
6040 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6041 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6042 (TYPE, CNT, OTHERTYPE)));
6043 fprintf_unfiltered (file,
6044 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6045 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
6047 fprintf_unfiltered (file,
6048 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6049 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6052 fprintf_unfiltered (file,
6053 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR);
6055 #ifdef TRACE_FLAVOR_SIZE
6056 fprintf_unfiltered (file,
6057 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6061 fprintf_unfiltered (file,
6062 "mips_dump_tdep: TRACE_SET # %s\n",
6063 XSTRING (TRACE_SET (X, STATE)));
6065 #ifdef UNUSED_REGNUM
6066 fprintf_unfiltered (file,
6067 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM);
6069 fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM);
6070 fprintf_unfiltered (file,
6071 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6072 (long) VM_MIN_ADDRESS);
6073 fprintf_unfiltered (file,
6074 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM);
6075 fprintf_unfiltered (file,
6076 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_);
6079 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6082 _initialize_mips_tdep (void)
6084 static struct cmd_list_element *mipsfpulist = NULL;
6085 struct cmd_list_element *c;
6087 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
6088 if (MIPS_ABI_LAST + 1
6089 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6090 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6092 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6094 mips_pdr_data = register_objfile_data ();
6096 /* Add root prefix command for all "set mips"/"show mips" commands */
6097 add_prefix_cmd ("mips", no_class, set_mips_command,
6098 "Various MIPS specific commands.",
6099 &setmipscmdlist, "set mips ", 0, &setlist);
6101 add_prefix_cmd ("mips", no_class, show_mips_command,
6102 "Various MIPS specific commands.",
6103 &showmipscmdlist, "show mips ", 0, &showlist);
6105 /* Allow the user to override the saved register size. */
6106 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6109 &mips_abi_regsize_string, "\
6110 Set size of general purpose registers saved on the stack.\n\
6111 This option can be set to one of:\n\
6112 32 - Force GDB to treat saved GP registers as 32-bit\n\
6113 64 - Force GDB to treat saved GP registers as 64-bit\n\
6114 auto - Allow GDB to use the target's default setting or autodetect the\n\
6115 saved GP register size from information contained in the executable.\n\
6116 (default: auto)", &setmipscmdlist), &showmipscmdlist);
6118 /* Allow the user to override the argument stack size. */
6119 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6122 &mips_stack_argsize_string, "\
6123 Set the amount of stack space reserved for each argument.\n\
6124 This option can be set to one of:\n\
6125 32 - Force GDB to allocate 32-bit chunks per argument\n\
6126 64 - Force GDB to allocate 64-bit chunks per argument\n\
6127 auto - Allow GDB to determine the correct setting from the current\n\
6128 target and executable (default)", &setmipscmdlist), &showmipscmdlist);
6130 /* Allow the user to override the ABI. */
6131 c = add_set_enum_cmd
6132 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6133 "Set the ABI used by this program.\n"
6134 "This option can be set to one of:\n"
6135 " auto - the default ABI associated with the current binary\n"
6137 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist);
6138 set_cmd_sfunc (c, mips_abi_update);
6139 add_cmd ("abi", class_obscure, show_mips_abi,
6140 "Show ABI in use by MIPS target", &showmipscmdlist);
6142 /* Let the user turn off floating point and set the fence post for
6143 heuristic_proc_start. */
6145 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6146 "Set use of MIPS floating-point coprocessor.",
6147 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6148 add_cmd ("single", class_support, set_mipsfpu_single_command,
6149 "Select single-precision MIPS floating-point coprocessor.",
6151 add_cmd ("double", class_support, set_mipsfpu_double_command,
6152 "Select double-precision MIPS floating-point coprocessor.",
6154 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6155 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6156 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6157 add_cmd ("none", class_support, set_mipsfpu_none_command,
6158 "Select no MIPS floating-point coprocessor.", &mipsfpulist);
6159 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6160 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6161 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6162 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6163 "Select MIPS floating-point coprocessor automatically.",
6165 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6166 "Show current use of MIPS floating-point coprocessor target.",
6169 /* We really would like to have both "0" and "unlimited" work, but
6170 command.c doesn't deal with that. So make it a var_zinteger
6171 because the user can always use "999999" or some such for unlimited. */
6172 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6173 (char *) &heuristic_fence_post, "\
6174 Set the distance searched for the start of a function.\n\
6175 If you are debugging a stripped executable, GDB needs to search through the\n\
6176 program for the start of a function. This command sets the distance of the\n\
6177 search. The only need to set it is when debugging a stripped executable.", &setlist);
6178 /* We need to throw away the frame cache when we set this, since it
6179 might change our ability to get backtraces. */
6180 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
6181 add_show_from_set (c, &showlist);
6183 /* Allow the user to control whether the upper bits of 64-bit
6184 addresses should be zeroed. */
6185 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6186 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6187 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6188 allow GDB to determine the correct value.\n", "\
6189 Show zeroing of upper 32 bits of 64-bit addresses.",
6190 NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist);
6192 /* Allow the user to control the size of 32 bit registers within the
6193 raw remote packet. */
6194 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6195 var_boolean, &mips64_transfers_32bit_regs_p, "\
6196 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6197 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6198 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6199 64 bits for others. Use \"off\" to disable compatibility mode", "\
6200 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6201 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6202 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6203 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist);
6205 /* Debug this files internals. */
6206 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6207 &mips_debug, "Set mips debugging.\n\
6208 When non-zero, mips specific debugging is enabled.", &setdebuglist), &showdebuglist);