1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack;
45 static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR));
48 static int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *));
50 static void mips_print_register PARAMS ((int, int));
52 static mips_extra_func_info_t
53 heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *));
55 static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR));
57 static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int));
59 static void mips_set_fpu_command PARAMS ((char *, int,
60 struct cmd_list_element *));
62 static void mips_show_fpu_command PARAMS ((char *, int,
63 struct cmd_list_element *));
65 void mips_set_processor_type_command PARAMS ((char *, int));
67 int mips_set_processor_type PARAMS ((char *));
69 static void mips_show_processor_type_command PARAMS ((char *, int));
71 static void reinit_frame_cache_sfunc PARAMS ((char *, int,
72 struct cmd_list_element *));
74 static mips_extra_func_info_t
75 find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame));
77 static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc,
78 mips_extra_func_info_t proc_desc));
80 /* This value is the model of MIPS in use. It is derived from the value
81 of the PrID register. */
83 char *mips_processor_type;
85 char *tmp_mips_processor_type;
87 /* Some MIPS boards don't support floating point, so we permit the
88 user to turn it off. */
90 enum mips_fpu_type mips_fpu;
92 static char *mips_fpu_string;
94 /* A set of original names, to be used when restoring back to generic
95 registers from a specific set. */
97 char *mips_generic_reg_names[] = REGISTER_NAMES;
99 /* Names of IDT R3041 registers. */
101 char *mips_r3041_reg_names[] = {
102 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
103 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
104 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
105 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
106 "sr", "lo", "hi", "bad", "cause","pc",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
111 "fsr", "fir", "fp", "",
112 "", "", "bus", "ccfg", "", "", "", "",
113 "", "", "port", "cmp", "", "", "epc", "prid",
116 /* Names of IDT R3051 registers. */
118 char *mips_r3051_reg_names[] = {
119 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
120 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
121 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
122 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
123 "sr", "lo", "hi", "bad", "cause","pc",
124 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
125 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
126 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
127 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
128 "fsr", "fir", "fp", "",
129 "inx", "rand", "elo", "", "ctxt", "", "", "",
130 "", "", "ehi", "", "", "", "epc", "prid",
133 /* Names of IDT R3081 registers. */
135 char *mips_r3081_reg_names[] = {
136 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
137 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
138 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
139 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
140 "sr", "lo", "hi", "bad", "cause","pc",
141 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
142 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
143 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
144 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
145 "fsr", "fir", "fp", "",
146 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
147 "", "", "ehi", "", "", "", "epc", "prid",
150 /* Names of LSI 33k registers. */
152 char *mips_lsi33k_reg_names[] = {
153 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
154 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
155 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
156 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
157 "epc", "hi", "lo", "sr", "cause","badvaddr",
158 "dcic", "bpc", "bda", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
170 } mips_processor_type_table[] = {
171 { "generic", mips_generic_reg_names },
172 { "r3041", mips_r3041_reg_names },
173 { "r3051", mips_r3051_reg_names },
174 { "r3071", mips_r3081_reg_names },
175 { "r3081", mips_r3081_reg_names },
176 { "lsi33k", mips_lsi33k_reg_names },
180 /* Table to translate MIPS16 register field to actual register number. */
181 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
183 /* Heuristic_proc_start may hunt through the text section for a long
184 time across a 2400 baud serial line. Allows the user to limit this
187 static unsigned int heuristic_fence_post = 0;
189 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
190 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
191 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
192 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
193 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
194 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
195 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
196 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
197 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
198 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
199 #define _PROC_MAGIC_ 0x0F0F0F0F
200 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
201 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
203 struct linked_proc_info
205 struct mips_extra_func_info info;
206 struct linked_proc_info *next;
207 } *linked_proc_desc_table = NULL;
210 /* This returns the PC of the first inst after the prologue. If we can't
211 find the prologue, then return 0. */
214 after_prologue (pc, proc_desc)
216 mips_extra_func_info_t proc_desc;
218 struct symtab_and_line sal;
219 CORE_ADDR func_addr, func_end;
222 proc_desc = find_proc_desc (pc, NULL);
226 /* If function is frameless, then we need to do it the hard way. I
227 strongly suspect that frameless always means prologueless... */
228 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
229 && PROC_FRAME_OFFSET (proc_desc) == 0)
233 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
234 return 0; /* Unknown */
236 sal = find_pc_line (func_addr, 0);
238 if (sal.end < func_end)
241 /* The line after the prologue is after the end of the function. In this
242 case, tell the caller to find the prologue the hard way. */
247 /* Decode a MIPS32 instruction that saves a register in the stack, and
248 set the appropriate bit in the general register mask or float register mask
249 to indicate which register is saved. This is a helper function
250 for mips_find_saved_regs. */
253 mips32_decode_reg_save (inst, gen_mask, float_mask)
255 unsigned long *gen_mask;
256 unsigned long *float_mask;
260 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
261 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
262 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
264 /* It might be possible to use the instruction to
265 find the offset, rather than the code below which
266 is based on things being in a certain order in the
267 frame, but figuring out what the instruction's offset
268 is relative to might be a little tricky. */
269 reg = (inst & 0x001f0000) >> 16;
270 *gen_mask |= (1 << reg);
272 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
273 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
274 || (inst & 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
277 reg = ((inst & 0x001f0000) >> 16);
278 *float_mask |= (1 << reg);
282 /* Decode a MIPS16 instruction that saves a register in the stack, and
283 set the appropriate bit in the general register or float register mask
284 to indicate which register is saved. This is a helper function
285 for mips_find_saved_regs. */
288 mips16_decode_reg_save (inst, gen_mask)
290 unsigned long *gen_mask;
292 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
294 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
295 *gen_mask |= (1 << reg);
297 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
299 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
300 *gen_mask |= (1 << reg);
302 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
303 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
304 *gen_mask |= (1 << 31);
308 /* Fetch and return instruction from the specified location. If the PC
309 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
312 mips_fetch_instruction (addr)
315 char buf[MIPS_INSTLEN];
319 if (IS_MIPS16_ADDR (addr))
321 instlen = MIPS16_INSTLEN;
322 addr = UNMAKE_MIPS16_ADDR (addr);
325 instlen = MIPS_INSTLEN;
326 status = read_memory_nobpt (addr, buf, instlen);
328 memory_error (status, addr);
329 return extract_unsigned_integer (buf, instlen);
333 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
337 mips_find_saved_regs (fci)
338 struct frame_info *fci;
341 CORE_ADDR reg_position;
342 /* r0 bit means kernel trap */
344 /* What registers have been saved? Bitmasks. */
345 unsigned long gen_mask, float_mask;
346 mips_extra_func_info_t proc_desc;
349 fci->saved_regs = (struct frame_saved_regs *)
350 obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs));
351 memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs));
353 /* If it is the frame for sigtramp, the saved registers are located
354 in a sigcontext structure somewhere on the stack.
355 If the stack layout for sigtramp changes we might have to change these
356 constants and the companion fixup_sigtramp in mdebugread.c */
357 #ifndef SIGFRAME_BASE
358 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
359 above the sigtramp frame. */
360 #define SIGFRAME_BASE MIPS_REGSIZE
361 /* FIXME! Are these correct?? */
362 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
363 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
364 #define SIGFRAME_FPREGSAVE_OFF \
365 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
367 #ifndef SIGFRAME_REG_SIZE
368 /* FIXME! Is this correct?? */
369 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
371 if (fci->signal_handler_caller)
373 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
375 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
376 + ireg * SIGFRAME_REG_SIZE;
377 fci->saved_regs->regs[ireg] = reg_position;
379 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
381 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
382 + ireg * SIGFRAME_REG_SIZE;
383 fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position;
385 fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
389 proc_desc = fci->proc_desc;
390 if (proc_desc == NULL)
391 /* I'm not sure how/whether this can happen. Normally when we can't
392 find a proc_desc, we "synthesize" one using heuristic_proc_desc
393 and set the saved_regs right away. */
396 kernel_trap = PROC_REG_MASK(proc_desc) & 1;
397 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc);
398 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc);
400 if (/* In any frame other than the innermost or a frame interrupted by
401 a signal, we assume that all registers have been saved.
402 This assumes that all register saves in a function happen before
403 the first function call. */
404 (fci->next == NULL || fci->next->signal_handler_caller)
406 /* In a dummy frame we know exactly where things are saved. */
407 && !PROC_DESC_IS_DUMMY (proc_desc)
409 /* Don't bother unless we are inside a function prologue. Outside the
410 prologue, we know where everything is. */
412 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
414 /* Not sure exactly what kernel_trap means, but if it means
415 the kernel saves the registers without a prologue doing it,
416 we better not examine the prologue to see whether registers
417 have been saved yet. */
420 /* We need to figure out whether the registers that the proc_desc
421 claims are saved have been saved yet. */
425 /* Bitmasks; set if we have found a save for the register. */
426 unsigned long gen_save_found = 0;
427 unsigned long float_save_found = 0;
430 /* If the address is odd, assume this is MIPS16 code. */
431 addr = PROC_LOW_ADDR (proc_desc);
432 instlen = IS_MIPS16_ADDR (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
434 /* Scan through this function's instructions preceding the current
435 PC, and look for those that save registers. */
436 while (addr < fci->pc)
438 inst = mips_fetch_instruction (addr);
439 if (IS_MIPS16_ADDR (addr))
440 mips16_decode_reg_save (inst, &gen_save_found);
442 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
445 gen_mask = gen_save_found;
446 float_mask = float_save_found;
449 /* Fill in the offsets for the registers which gen_mask says
451 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
452 for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1)
453 if (gen_mask & 0x80000000)
455 fci->saved_regs->regs[ireg] = reg_position;
456 reg_position -= MIPS_REGSIZE;
459 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
460 of that normally used by gcc. Therefore, we have to fetch the first
461 instruction of the function, and if it's an entry instruction that
462 saves $s0 or $s1, correct their saved addresses. */
463 if (IS_MIPS16_ADDR (PROC_LOW_ADDR (proc_desc)))
465 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
466 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
469 int sreg_count = (inst >> 6) & 3;
471 /* Check if the ra register was pushed on the stack. */
472 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
474 reg_position -= MIPS_REGSIZE;
476 /* Check if the s0 and s1 registers were pushed on the stack. */
477 for (reg = 16; reg < sreg_count+16; reg++)
479 fci->saved_regs->regs[reg] = reg_position;
480 reg_position -= MIPS_REGSIZE;
485 /* Fill in the offsets for the registers which float_mask says
487 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
489 /* The freg_offset points to where the first *double* register
490 is saved. So skip to the high-order word. */
491 if (! GDB_TARGET_IS_MIPS64)
492 reg_position += MIPS_REGSIZE;
494 /* Fill in the offsets for the float registers which float_mask says
496 for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1)
497 if (float_mask & 0x80000000)
499 fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position;
500 reg_position -= MIPS_REGSIZE;
503 fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM];
507 read_next_frame_reg(fi, regno)
508 struct frame_info *fi;
511 for (; fi; fi = fi->next)
513 /* We have to get the saved sp from the sigcontext
514 if it is a signal handler frame. */
515 if (regno == SP_REGNUM && !fi->signal_handler_caller)
519 if (fi->saved_regs == NULL)
520 mips_find_saved_regs (fi);
521 if (fi->saved_regs->regs[regno])
522 return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE);
525 return read_register (regno);
528 /* mips_addr_bits_remove - remove useless address bits */
531 mips_addr_bits_remove (addr)
534 #if GDB_TARGET_IS_MIPS64
535 if ((addr >> 32 == (CORE_ADDR)0xffffffff)
536 && (strcmp (target_shortname,"pmon")==0
537 || strcmp (target_shortname,"ddb")==0
538 || strcmp (target_shortname,"sim")==0))
540 /* This hack is a work-around for existing boards using PMON,
541 the simulator, and any other 64-bit targets that doesn't have
542 true 64-bit addressing. On these targets, the upper 32 bits
543 of addresses are ignored by the hardware. Thus, the PC or SP
544 are likely to have been sign extended to all 1s by instruction
545 sequences that load 32-bit addresses. For example, a typical
546 piece of code that loads an address is this:
547 lui $r2, <upper 16 bits>
548 ori $r2, <lower 16 bits>
549 But the lui sign-extends the value such that the upper 32 bits
550 may be all 1s. The workaround is simply to mask off these bits.
551 In the future, gcc may be changed to support true 64-bit
552 addressing, and this masking will have to be disabled. */
553 addr &= (CORE_ADDR)0xffffffff;
556 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
557 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
558 So we still have to mask off useless bits from addresses. */
559 addr &= (CORE_ADDR)0xffffffff;
566 mips_init_frame_pc_first (fromleaf, prev)
568 struct frame_info *prev;
572 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
573 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
574 tmp = mips_skip_stub (pc);
575 prev->pc = tmp ? tmp : pc;
580 mips_frame_saved_pc(frame)
581 struct frame_info *frame;
584 mips_extra_func_info_t proc_desc = frame->proc_desc;
585 /* We have to get the saved pc from the sigcontext
586 if it is a signal handler frame. */
587 int pcreg = frame->signal_handler_caller ? PC_REGNUM
588 : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM);
590 if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc))
591 saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE);
593 saved_pc = read_next_frame_reg(frame, pcreg);
595 return ADDR_BITS_REMOVE (saved_pc);
598 static struct mips_extra_func_info temp_proc_desc;
599 static struct frame_saved_regs temp_saved_regs;
601 /* This fencepost looks highly suspicious to me. Removing it also
602 seems suspicious as it could affect remote debugging across serial
606 heuristic_proc_start(pc)
614 pc = ADDR_BITS_REMOVE (pc);
616 fence = start_pc - heuristic_fence_post;
617 if (start_pc == 0) return 0;
619 if (heuristic_fence_post == UINT_MAX
620 || fence < VM_MIN_ADDRESS)
621 fence = VM_MIN_ADDRESS;
623 instlen = IS_MIPS16_ADDR (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
625 /* search back for previous return */
626 for (start_pc -= instlen; ; start_pc -= instlen)
627 if (start_pc < fence)
629 /* It's not clear to me why we reach this point when
630 stop_soon_quietly, but with this test, at least we
631 don't print out warnings for every child forked (eg, on
632 decstation). 22apr93 rich@cygnus.com. */
633 if (!stop_soon_quietly)
635 static int blurb_printed = 0;
637 if (fence == VM_MIN_ADDRESS)
638 warning("Hit beginning of text section without finding");
640 warning("Hit heuristic-fence-post without finding");
642 warning("enclosing function for address 0x%s", paddr_nz (pc));
646 This warning occurs if you are debugging a function without any symbols\n\
647 (for example, in a stripped executable). In that case, you may wish to\n\
648 increase the size of the search with the `set heuristic-fence-post' command.\n\
650 Otherwise, you told GDB there was a function where there isn't one, or\n\
651 (more likely) you have encountered a bug in GDB.\n");
658 else if (IS_MIPS16_ADDR (start_pc))
662 /* On MIPS16, any one of the following is likely to be the
667 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
668 inst = mips_fetch_instruction (start_pc);
669 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
670 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
671 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
672 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
674 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
675 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
680 else if (ABOUT_TO_RETURN(start_pc))
682 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
687 /* skip nops (usually 1) 0 - is this */
688 while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0)
689 start_pc += MIPS_INSTLEN;
694 /* Fetch the immediate value from a MIPS16 instruction.
695 If the previous instruction was an EXTEND, use it to extend
696 the upper bits of the immediate value. This is a helper function
697 for mips16_heuristic_proc_desc. */
700 mips16_get_imm (prev_inst, inst, nbits, scale, is_signed)
701 unsigned short prev_inst; /* previous instruction */
702 unsigned short inst; /* current current instruction */
703 int nbits; /* number of bits in imm field */
704 int scale; /* scale factor to be applied to imm */
705 int is_signed; /* is the imm field signed? */
709 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
711 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
712 if (offset & 0x8000) /* check for negative extend */
713 offset = 0 - (0x10000 - (offset & 0xffff));
714 return offset | (inst & 0x1f);
718 int max_imm = 1 << nbits;
719 int mask = max_imm - 1;
720 int sign_bit = max_imm >> 1;
722 offset = inst & mask;
723 if (is_signed && (offset & sign_bit))
724 offset = 0 - (max_imm - offset);
725 return offset * scale;
730 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
731 stream from start_pc to limit_pc. */
734 mips16_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp)
735 CORE_ADDR start_pc, limit_pc;
736 struct frame_info *next_frame;
740 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
741 unsigned short prev_inst = 0; /* saved copy of previous instruction */
742 unsigned inst = 0; /* current instruction */
744 PROC_FRAME_OFFSET(&temp_proc_desc) = 0;
746 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
750 /* Save the previous instruction. If it's an EXTEND, we'll extract
751 the immediate offset extension from it in mips16_get_imm. */
754 /* Fetch and decode the instruction. */
755 inst = (unsigned short) mips_fetch_instruction (cur_pc);
756 if ((inst & 0xff00) == 0x6300 /* addiu sp */
757 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
759 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
760 if (offset < 0) /* negative stack adjustment? */
761 PROC_FRAME_OFFSET(&temp_proc_desc) -= offset;
763 /* Exit loop if a positive stack adjustment is found, which
764 usually means that the stack cleanup code in the function
765 epilogue is reached. */
768 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
770 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
771 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
772 PROC_REG_MASK(&temp_proc_desc) |= (1 << reg);
773 temp_saved_regs.regs[reg] = sp + offset;
775 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
777 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
778 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
779 PROC_REG_MASK(&temp_proc_desc) |= (1 << reg);
780 temp_saved_regs.regs[reg] = sp + offset;
782 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
784 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
785 PROC_REG_MASK(&temp_proc_desc) |= (1 << 31);
786 temp_saved_regs.regs[31] = sp + offset;
788 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
790 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
791 PROC_REG_MASK(&temp_proc_desc) |= (1 << 31);
792 temp_saved_regs.regs[31] = sp + offset;
794 else if (inst == 0x673d) /* move $s1, $sp */
796 frame_addr = read_next_frame_reg(next_frame, 30);
797 PROC_FRAME_REG (&temp_proc_desc) = 17;
799 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
801 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
802 frame_addr = sp + offset;
803 PROC_FRAME_REG (&temp_proc_desc) = 17;
805 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
807 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
808 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
809 PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
810 temp_saved_regs.regs[reg] = frame_addr + offset;
812 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
814 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
815 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
816 PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
817 temp_saved_regs.regs[reg] = frame_addr + offset;
819 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
821 int areg_count = (inst >> 8) & 7;
822 int sreg_count = (inst >> 6) & 3;
824 /* The entry instruction always subtracts 32 from the SP. */
825 PROC_FRAME_OFFSET(&temp_proc_desc) += 32;
827 /* Check if a0-a3 were saved in the caller's argument save area. */
828 for (reg = 4, offset = 32; reg < areg_count+4; reg++)
830 PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
831 temp_saved_regs.regs[reg] = sp + offset;
832 offset -= MIPS_REGSIZE;
835 /* Check if the ra register was pushed on the stack. */
839 PROC_REG_MASK(&temp_proc_desc) |= 1 << 31;
840 temp_saved_regs.regs[31] = sp + offset;
841 offset -= MIPS_REGSIZE;
844 /* Check if the s0 and s1 registers were pushed on the stack. */
845 for (reg = 16; reg < sreg_count+16; reg++)
847 PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
848 temp_saved_regs.regs[reg] = sp + offset;
849 offset -= MIPS_REGSIZE;
852 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
853 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
858 mips32_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp)
859 CORE_ADDR start_pc, limit_pc;
860 struct frame_info *next_frame;
864 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
866 PROC_FRAME_OFFSET(&temp_proc_desc) = 0;
867 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
869 unsigned long inst, high_word, low_word;
872 /* Fetch the instruction. */
873 inst = (unsigned long) mips_fetch_instruction (cur_pc);
875 /* Save some code by pre-extracting some useful fields. */
876 high_word = (inst >> 16) & 0xffff;
877 low_word = inst & 0xffff;
878 reg = high_word & 0x1f;
880 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
881 || high_word == 0x23bd /* addi $sp,$sp,-i */
882 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
884 if (low_word & 0x8000) /* negative stack adjustment? */
885 PROC_FRAME_OFFSET(&temp_proc_desc) += 0x10000 - low_word;
887 /* Exit loop if a positive stack adjustment is found, which
888 usually means that the stack cleanup code in the function
889 epilogue is reached. */
892 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
894 PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
895 temp_saved_regs.regs[reg] = sp + low_word;
897 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
899 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
900 but the register size used is only 32 bits. Make the address
901 for the saved register point to the lower 32 bits. */
902 PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
903 temp_saved_regs.regs[reg] = sp + low_word + 8 - MIPS_REGSIZE;
905 else if (high_word == 0x27be) /* addiu $30,$sp,size */
907 /* Old gcc frame, r30 is virtual frame pointer. */
908 if ((long)low_word != PROC_FRAME_OFFSET(&temp_proc_desc))
909 frame_addr = sp + low_word;
910 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
912 unsigned alloca_adjust;
913 PROC_FRAME_REG (&temp_proc_desc) = 30;
914 frame_addr = read_next_frame_reg(next_frame, 30);
915 alloca_adjust = (unsigned)(frame_addr - (sp + low_word));
916 if (alloca_adjust > 0)
918 /* FP > SP + frame_size. This may be because
919 * of an alloca or somethings similar.
920 * Fix sp to "pre-alloca" value, and try again.
927 /* move $30,$sp. With different versions of gas this will be either
928 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
929 Accept any one of these. */
930 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
932 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
933 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
935 unsigned alloca_adjust;
936 PROC_FRAME_REG (&temp_proc_desc) = 30;
937 frame_addr = read_next_frame_reg(next_frame, 30);
938 alloca_adjust = (unsigned)(frame_addr - sp);
939 if (alloca_adjust > 0)
941 /* FP > SP + frame_size. This may be because
942 * of an alloca or somethings similar.
943 * Fix sp to "pre-alloca" value, and try again.
950 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
952 PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
953 temp_saved_regs.regs[reg] = frame_addr + low_word;
958 static mips_extra_func_info_t
959 heuristic_proc_desc(start_pc, limit_pc, next_frame)
960 CORE_ADDR start_pc, limit_pc;
961 struct frame_info *next_frame;
963 CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM);
965 if (start_pc == 0) return NULL;
966 memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc));
967 memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs));
968 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
969 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
970 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
972 if (start_pc + 200 < limit_pc)
973 limit_pc = start_pc + 200;
974 if (IS_MIPS16_ADDR (start_pc))
975 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
977 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
978 return &temp_proc_desc;
981 static mips_extra_func_info_t
982 non_heuristic_proc_desc (pc, addrptr)
987 mips_extra_func_info_t proc_desc;
988 struct block *b = block_for_pc(pc);
991 find_pc_partial_function (pc, NULL, &startaddr, NULL);
993 *addrptr = startaddr;
994 if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0))
998 if (startaddr > BLOCK_START (b))
999 /* This is the "pathological" case referred to in a comment in
1000 print_frame_info. It might be better to move this check into
1004 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
1007 /* If we never found a PDR for this function in symbol reading, then
1008 examine prologues to find the information. */
1011 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
1012 if (PROC_FRAME_REG (proc_desc) == -1)
1022 static mips_extra_func_info_t
1023 find_proc_desc (pc, next_frame)
1025 struct frame_info *next_frame;
1027 mips_extra_func_info_t proc_desc;
1028 CORE_ADDR startaddr;
1030 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
1034 /* IF this is the topmost frame AND
1035 * (this proc does not have debugging information OR
1036 * the PC is in the procedure prologue)
1037 * THEN create a "heuristic" proc_desc (by analyzing
1038 * the actual code) to replace the "official" proc_desc.
1040 if (next_frame == NULL)
1042 struct symtab_and_line val;
1043 struct symbol *proc_symbol =
1044 PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc);
1048 val = find_pc_line (BLOCK_START
1049 (SYMBOL_BLOCK_VALUE(proc_symbol)),
1051 val.pc = val.end ? val.end : pc;
1053 if (!proc_symbol || pc < val.pc)
1055 mips_extra_func_info_t found_heuristic =
1056 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
1058 if (found_heuristic)
1059 proc_desc = found_heuristic;
1065 /* Is linked_proc_desc_table really necessary? It only seems to be used
1066 by procedure call dummys. However, the procedures being called ought
1067 to have their own proc_descs, and even if they don't,
1068 heuristic_proc_desc knows how to create them! */
1070 register struct linked_proc_info *link;
1072 for (link = linked_proc_desc_table; link; link = link->next)
1073 if (PROC_LOW_ADDR(&link->info) <= pc
1074 && PROC_HIGH_ADDR(&link->info) > pc)
1078 startaddr = heuristic_proc_start (pc);
1081 heuristic_proc_desc (startaddr, pc, next_frame);
1087 get_frame_pointer(frame, proc_desc)
1088 struct frame_info *frame;
1089 mips_extra_func_info_t proc_desc;
1091 return ADDR_BITS_REMOVE (read_next_frame_reg (frame,
1092 PROC_FRAME_REG(proc_desc)) + PROC_FRAME_OFFSET(proc_desc));
1095 mips_extra_func_info_t cached_proc_desc;
1098 mips_frame_chain(frame)
1099 struct frame_info *frame;
1101 mips_extra_func_info_t proc_desc;
1103 CORE_ADDR saved_pc = FRAME_SAVED_PC(frame);
1105 if (saved_pc == 0 || inside_entry_file (saved_pc))
1108 /* Check if the PC is inside a call stub. If it is, fetch the
1109 PC of the caller of that stub. */
1110 if ((tmp = mips_skip_stub (saved_pc)) != 0)
1113 /* Look up the procedure descriptor for this PC. */
1114 proc_desc = find_proc_desc(saved_pc, frame);
1118 cached_proc_desc = proc_desc;
1120 /* If no frame pointer and frame size is zero, we must be at end
1121 of stack (or otherwise hosed). If we don't check frame size,
1122 we loop forever if we see a zero size frame. */
1123 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
1124 && PROC_FRAME_OFFSET (proc_desc) == 0
1125 /* The previous frame from a sigtramp frame might be frameless
1126 and have frame size zero. */
1127 && !frame->signal_handler_caller)
1130 return get_frame_pointer (frame, proc_desc);
1134 init_extra_frame_info(fci)
1135 struct frame_info *fci;
1139 /* Use proc_desc calculated in frame_chain */
1140 mips_extra_func_info_t proc_desc =
1141 fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next);
1143 fci->saved_regs = NULL;
1145 proc_desc == &temp_proc_desc ? 0 : proc_desc;
1148 /* Fixup frame-pointer - only needed for top frame */
1149 /* This may not be quite right, if proc has a real frame register.
1150 Get the value of the frame relative sp, procedure might have been
1151 interrupted by a signal at it's very start. */
1152 if (fci->pc == PROC_LOW_ADDR (proc_desc)
1153 && !PROC_DESC_IS_DUMMY (proc_desc))
1154 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
1156 fci->frame = get_frame_pointer (fci->next, proc_desc);
1158 if (proc_desc == &temp_proc_desc)
1162 /* Do not set the saved registers for a sigtramp frame,
1163 mips_find_saved_registers will do that for us.
1164 We can't use fci->signal_handler_caller, it is not yet set. */
1165 find_pc_partial_function (fci->pc, &name,
1166 (CORE_ADDR *)NULL,(CORE_ADDR *)NULL);
1167 if (!IN_SIGTRAMP (fci->pc, name))
1169 fci->saved_regs = (struct frame_saved_regs*)
1170 obstack_alloc (&frame_cache_obstack,
1171 sizeof (struct frame_saved_regs));
1172 *fci->saved_regs = temp_saved_regs;
1173 fci->saved_regs->regs[PC_REGNUM]
1174 = fci->saved_regs->regs[RA_REGNUM];
1178 /* hack: if argument regs are saved, guess these contain args */
1179 fci->num_args = -1; /* assume we can't tell how many args for now */
1180 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
1182 if (PROC_REG_MASK(proc_desc) & (1 << regnum))
1184 fci->num_args = regnum - A0_REGNUM + 1;
1191 /* MIPS stack frames are almost impenetrable. When execution stops,
1192 we basically have to look at symbol information for the function
1193 that we stopped in, which tells us *which* register (if any) is
1194 the base of the frame pointer, and what offset from that register
1195 the frame itself is at.
1197 This presents a problem when trying to examine a stack in memory
1198 (that isn't executing at the moment), using the "frame" command. We
1199 don't have a PC, nor do we have any registers except SP.
1201 This routine takes two arguments, SP and PC, and tries to make the
1202 cached frames look as if these two arguments defined a frame on the
1203 cache. This allows the rest of info frame to extract the important
1204 arguments without difficulty. */
1207 setup_arbitrary_frame (argc, argv)
1212 error ("MIPS frame specifications require two arguments: sp and pc");
1214 return create_new_frame (argv[0], argv[1]);
1218 mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
1223 CORE_ADDR struct_addr;
1231 /* Macros to round N up or down to the next A boundary; A must be
1233 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1234 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1236 /* First ensure that the stack and structure return address (if any)
1237 are properly aligned. The stack has to be 64-bit aligned even
1238 on 32-bit machines, because doubles must be 64-bit aligned. */
1239 sp = ROUND_DOWN (sp, 8);
1240 struct_addr = ROUND_DOWN (struct_addr, MIPS_REGSIZE);
1242 /* Now make space on the stack for the args. We allocate more
1243 than necessary for EABI, because the first few arguments are
1244 passed in registers, but that's OK. */
1245 for (argnum = 0; argnum < nargs; argnum++)
1246 len += ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args[argnum])), MIPS_REGSIZE);
1247 sp -= ROUND_UP (len, 8);
1249 /* Initialize the integer and float register pointers. */
1251 float_argreg = FPA0_REGNUM;
1253 /* the struct_return pointer occupies the first parameter-passing reg */
1255 write_register (argreg++, struct_addr);
1257 /* The offset onto the stack at which we will start copying parameters
1258 (after the registers are used up) begins at 16 in the old ABI.
1259 This leaves room for the "home" area for register parameters. */
1260 stack_offset = MIPS_EABI ? 0 : MIPS_REGSIZE * 4;
1262 /* Now load as many as possible of the first arguments into
1263 registers, and push the rest onto the stack. Loop thru args
1264 from first to last. */
1265 for (argnum = 0; argnum < nargs; argnum++)
1268 char valbuf[REGISTER_RAW_SIZE(A0_REGNUM)];
1269 value_ptr arg = args[argnum];
1270 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
1271 int len = TYPE_LENGTH (arg_type);
1272 enum type_code typecode = TYPE_CODE (arg_type);
1274 /* The EABI passes structures that do not fit in a register by
1275 reference. In all other cases, pass the structure by value. */
1276 if (typecode == TYPE_CODE_STRUCT && MIPS_EABI && len > MIPS_REGSIZE)
1278 store_address (valbuf, MIPS_REGSIZE, VALUE_ADDRESS (arg));
1279 typecode = TYPE_CODE_PTR;
1284 val = (char *)VALUE_CONTENTS (arg);
1286 /* 32-bit ABIs always start floating point arguments in an
1287 even-numbered floating point register. */
1288 if (!GDB_TARGET_IS_MIPS64 && typecode == TYPE_CODE_FLT
1289 && (float_argreg & 1))
1292 /* Floating point arguments passed in registers have to be
1293 treated specially. On 32-bit architectures, doubles
1294 are passed in register pairs; the even register gets
1295 the low word, and the odd register gets the high word.
1296 On non-EABI processors, the first two floating point arguments are
1297 also copied to general registers, because MIPS16 functions
1298 don't use float registers for arguments. This duplication of
1299 arguments in general registers can't hurt non-MIPS16 functions
1300 because those registers are normally skipped. */
1301 if (typecode == TYPE_CODE_FLT
1302 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM
1303 && mips_fpu != MIPS_FPU_NONE)
1305 if (!GDB_TARGET_IS_MIPS64 && len == 8)
1307 int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0;
1308 unsigned long regval;
1310 /* Write the low word of the double to the even register(s). */
1311 regval = extract_unsigned_integer (val+low_offset, 4);
1312 write_register (float_argreg++, regval);
1314 write_register (argreg+1, regval);
1316 /* Write the high word of the double to the odd register(s). */
1317 regval = extract_unsigned_integer (val+4-low_offset, 4);
1318 write_register (float_argreg++, regval);
1321 write_register (argreg, regval);
1328 /* This is a floating point value that fits entirely
1329 in a single register. */
1330 CORE_ADDR regval = extract_address (val, len);
1331 write_register (float_argreg++, regval);
1334 write_register (argreg, regval);
1335 argreg += GDB_TARGET_IS_MIPS64 ? 1 : 2;
1341 /* Copy the argument to general registers or the stack in
1342 register-sized pieces. Large arguments are split between
1343 registers and stack. */
1346 int partial_len = len < MIPS_REGSIZE ? len : MIPS_REGSIZE;
1348 if (argreg <= MIPS_LAST_ARG_REGNUM)
1350 CORE_ADDR regval = extract_address (val, partial_len);
1352 /* It's a simple argument being passed in a general
1354 If the argument length is smaller than the register size,
1355 we have to adjust the argument on big endian targets.
1356 But don't do this adjustment on EABI targets. */
1357 if (TARGET_BYTE_ORDER == BIG_ENDIAN
1358 && partial_len < MIPS_REGSIZE
1360 regval <<= ((MIPS_REGSIZE - partial_len) * TARGET_CHAR_BIT);
1361 write_register (argreg, regval);
1364 /* If this is the old ABI, prevent subsequent floating
1365 point arguments from being passed in floating point
1368 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
1372 /* Write this portion of the argument to the stack. */
1373 int longword_offset;
1376 longword_offset = 0;
1377 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1378 if (MIPS_REGSIZE == 8 &&
1379 (typecode == TYPE_CODE_INT ||
1380 typecode == TYPE_CODE_PTR ||
1381 typecode == TYPE_CODE_FLT) && len <= 4)
1382 longword_offset = 4;
1383 else if ((typecode == TYPE_CODE_STRUCT ||
1384 typecode == TYPE_CODE_UNION) &&
1386 longword_offset = MIPS_REGSIZE - len;
1388 write_memory (sp + stack_offset + longword_offset,
1390 stack_offset += ROUND_UP (partial_len, MIPS_REGSIZE);
1399 /* Set the return address register to point to the entry
1400 point of the program, where a breakpoint lies in wait. */
1401 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS());
1403 /* Return adjusted stack pointer. */
1408 mips_push_register(CORE_ADDR *sp, int regno)
1410 char buffer[MAX_REGISTER_RAW_SIZE];
1411 int regsize = REGISTER_RAW_SIZE (regno);
1414 read_register_gen (regno, buffer);
1415 write_memory (*sp, buffer, regsize);
1418 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1419 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1422 mips_push_dummy_frame()
1425 struct linked_proc_info *link = (struct linked_proc_info*)
1426 xmalloc(sizeof(struct linked_proc_info));
1427 mips_extra_func_info_t proc_desc = &link->info;
1428 CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM));
1429 CORE_ADDR old_sp = sp;
1430 link->next = linked_proc_desc_table;
1431 linked_proc_desc_table = link;
1433 /* FIXME! are these correct ? */
1434 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1435 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1436 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1437 #define FLOAT_SINGLE_REG_SAVE_MASK \
1438 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1440 * The registers we must save are all those not preserved across
1441 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1442 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1443 * and FP Control/Status registers.
1446 * Dummy frame layout:
1449 * Saved MMHI, MMLO, FPC_CSR
1454 * Saved D18 (i.e. F19, F18)
1456 * Saved D0 (i.e. F1, F0)
1457 * Argument build area and stack arguments written via mips_push_arguments
1461 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1462 PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM;
1463 PROC_FRAME_OFFSET(proc_desc) = 0;
1464 mips_push_register (&sp, PC_REGNUM);
1465 mips_push_register (&sp, HI_REGNUM);
1466 mips_push_register (&sp, LO_REGNUM);
1467 mips_push_register (&sp, mips_fpu == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
1469 /* Save general CPU registers */
1470 PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK;
1471 PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */
1472 for (ireg = 32; --ireg >= 0; )
1473 if (PROC_REG_MASK(proc_desc) & (1 << ireg))
1474 mips_push_register (&sp, ireg);
1476 /* Save floating point registers starting with high order word */
1477 PROC_FREG_MASK(proc_desc) =
1478 mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
1479 : mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
1480 PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */
1481 for (ireg = 32; --ireg >= 0; )
1482 if (PROC_FREG_MASK(proc_desc) & (1 << ireg))
1483 mips_push_register (&sp, ireg + FP0_REGNUM);
1485 /* Update the frame pointer for the call dummy and the stack pointer.
1486 Set the procedure's starting and ending addresses to point to the
1487 call dummy address at the entry point. */
1488 write_register (PUSH_FP_REGNUM, old_sp);
1489 write_register (SP_REGNUM, sp);
1490 PROC_LOW_ADDR(proc_desc) = CALL_DUMMY_ADDRESS();
1491 PROC_HIGH_ADDR(proc_desc) = CALL_DUMMY_ADDRESS() + 4;
1492 SET_PROC_DESC_IS_DUMMY(proc_desc);
1493 PROC_PC_REG(proc_desc) = RA_REGNUM;
1499 register int regnum;
1500 struct frame_info *frame = get_current_frame ();
1501 CORE_ADDR new_sp = FRAME_FP (frame);
1503 mips_extra_func_info_t proc_desc = frame->proc_desc;
1505 write_register (PC_REGNUM, FRAME_SAVED_PC(frame));
1506 if (frame->saved_regs == NULL)
1507 mips_find_saved_regs (frame);
1508 for (regnum = 0; regnum < NUM_REGS; regnum++)
1510 if (regnum != SP_REGNUM && regnum != PC_REGNUM
1511 && frame->saved_regs->regs[regnum])
1512 write_register (regnum,
1513 read_memory_integer (frame->saved_regs->regs[regnum],
1516 write_register (SP_REGNUM, new_sp);
1517 flush_cached_frames ();
1519 if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc))
1521 struct linked_proc_info *pi_ptr, *prev_ptr;
1523 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
1525 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
1527 if (&pi_ptr->info == proc_desc)
1532 error ("Can't locate dummy extra frame info\n");
1534 if (prev_ptr != NULL)
1535 prev_ptr->next = pi_ptr->next;
1537 linked_proc_desc_table = pi_ptr->next;
1541 write_register (HI_REGNUM,
1542 read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE));
1543 write_register (LO_REGNUM,
1544 read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE));
1545 if (mips_fpu != MIPS_FPU_NONE)
1546 write_register (FCRCS_REGNUM,
1547 read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE));
1552 mips_print_register (regnum, all)
1555 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1557 /* Get the data in raw format. */
1558 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1560 printf_filtered ("%s: [Invalid]", reg_names[regnum]);
1564 /* If an even floating pointer register, also print as double. */
1565 if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+MIPS_NUMREGS
1566 && !((regnum-FP0_REGNUM) & 1))
1568 char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
1570 read_relative_register_raw_bytes (regnum, dbuffer);
1571 read_relative_register_raw_bytes (regnum+1, dbuffer+MIPS_REGSIZE);
1572 REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer);
1574 printf_filtered ("(d%d: ", regnum-FP0_REGNUM);
1575 val_print (builtin_type_double, dbuffer, 0,
1576 gdb_stdout, 0, 1, 0, Val_pretty_default);
1577 printf_filtered ("); ");
1579 fputs_filtered (reg_names[regnum], gdb_stdout);
1581 /* The problem with printing numeric register names (r26, etc.) is that
1582 the user can't use them on input. Probably the best solution is to
1583 fix it so that either the numeric or the funky (a2, etc.) names
1584 are accepted on input. */
1585 if (regnum < MIPS_NUMREGS)
1586 printf_filtered ("(r%d): ", regnum);
1588 printf_filtered (": ");
1590 /* If virtual format is floating, print it that way. */
1591 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1592 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0,
1593 gdb_stdout, 0, 1, 0, Val_pretty_default);
1594 /* Else print as integer in hex. */
1596 print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum),
1597 'x', 0, gdb_stdout);
1600 /* Replacement for generic do_registers_info. */
1603 mips_do_registers_info (regnum, fpregs)
1609 if (*(reg_names[regnum]) == '\0')
1610 error ("Not a valid register for the current processor type");
1612 mips_print_register (regnum, 0);
1613 printf_filtered ("\n");
1617 int did_newline = 0;
1619 for (regnum = 0; regnum < NUM_REGS; )
1621 if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM)
1622 || *(reg_names[regnum]) == '\0')
1627 mips_print_register (regnum, 1);
1629 printf_filtered ("; ");
1631 if ((regnum & 3) == 0)
1633 printf_filtered ("\n");
1638 printf_filtered ("\n");
1642 /* Return number of args passed to a frame. described by FIP.
1643 Can return -1, meaning no way to tell. */
1646 mips_frame_num_args (frame)
1647 struct frame_info *frame;
1649 #if 0 /* FIXME Use or lose this! */
1650 struct chain_info_t *p;
1652 p = mips_find_cached_frame (FRAME_FP (frame));
1654 return p->the_info.numargs;
1659 /* Is this a branch with a delay slot? */
1661 static int is_delayed PARAMS ((unsigned long));
1668 for (i = 0; i < NUMOPCODES; ++i)
1669 if (mips_opcodes[i].pinfo != INSN_MACRO
1670 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
1672 return (i < NUMOPCODES
1673 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
1674 | INSN_COND_BRANCH_DELAY
1675 | INSN_COND_BRANCH_LIKELY)));
1679 mips_step_skips_delay (pc)
1682 char buf[MIPS_INSTLEN];
1684 /* There is no branch delay slot on MIPS16. */
1685 if (IS_MIPS16_ADDR (pc))
1688 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
1689 /* If error reading memory, guess that it is not a delayed branch. */
1691 return is_delayed ((unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN));
1695 /* Skip the PC past function prologue instructions (32-bit version).
1696 This is a helper function for mips_skip_prologue. */
1699 mips32_skip_prologue (pc, lenient)
1700 CORE_ADDR pc; /* starting PC to search from */
1705 int seen_sp_adjust = 0;
1706 int load_immediate_bytes = 0;
1708 /* Skip the typical prologue instructions. These are the stack adjustment
1709 instruction and the instructions that save registers on the stack
1710 or in the gcc frame. */
1711 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
1713 unsigned long high_word;
1715 inst = mips_fetch_instruction (pc);
1716 high_word = (inst >> 16) & 0xffff;
1719 if (lenient && is_delayed (inst))
1723 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
1724 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
1726 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
1727 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
1729 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
1730 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
1731 && (inst & 0x001F0000)) /* reg != $zero */
1734 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1736 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
1738 continue; /* reg != $zero */
1740 /* move $s8,$sp. With different versions of gas this will be either
1741 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
1742 Accept any one of these. */
1743 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1746 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1748 else if (high_word == 0x3c1c) /* lui $gp,n */
1750 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
1752 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
1753 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
1755 /* The following instructions load $at or $t0 with an immediate
1756 value in preparation for a stack adjustment via
1757 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1758 a local variable, so we accept them only before a stack adjustment
1759 instruction was seen. */
1760 else if (!seen_sp_adjust)
1762 if (high_word == 0x3c01 || /* lui $at,n */
1763 high_word == 0x3c08) /* lui $t0,n */
1765 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
1768 else if (high_word == 0x3421 || /* ori $at,$at,n */
1769 high_word == 0x3508 || /* ori $t0,$t0,n */
1770 high_word == 0x3401 || /* ori $at,$zero,n */
1771 high_word == 0x3408) /* ori $t0,$zero,n */
1773 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
1783 /* In a frameless function, we might have incorrectly
1784 skipped some load immediate instructions. Undo the skipping
1785 if the load immediate was not followed by a stack adjustment. */
1786 if (load_immediate_bytes && !seen_sp_adjust)
1787 pc -= load_immediate_bytes;
1791 /* Skip the PC past function prologue instructions (16-bit version).
1792 This is a helper function for mips_skip_prologue. */
1795 mips16_skip_prologue (pc, lenient)
1796 CORE_ADDR pc; /* starting PC to search from */
1800 int extend_bytes = 0;
1801 int prev_extend_bytes;
1803 /* Table of instructions likely to be found in a function prologue. */
1806 unsigned short inst;
1807 unsigned short mask;
1810 { 0x6300, 0xff00 }, /* addiu $sp,offset */
1811 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
1812 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
1813 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
1814 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
1815 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
1816 { 0x673d, 0xffff }, /* move $s1,sp */
1817 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
1818 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
1819 { 0xe809, 0xf81f }, /* entry pseudo-op */
1820 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
1821 { 0, 0 } /* end of table marker */
1824 /* Skip the typical prologue instructions. These are the stack adjustment
1825 instruction and the instructions that save registers on the stack
1826 or in the gcc frame. */
1827 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
1829 unsigned short inst;
1832 inst = mips_fetch_instruction (pc);
1834 /* Normally we ignore an extend instruction. However, if it is
1835 not followed by a valid prologue instruction, we must adjust
1836 the pc back over the extend so that it won't be considered
1837 part of the prologue. */
1838 if ((inst & 0xf800) == 0xf000) /* extend */
1840 extend_bytes = MIPS16_INSTLEN;
1843 prev_extend_bytes = extend_bytes;
1846 /* Check for other valid prologue instructions besides extend. */
1847 for (i = 0; table[i].mask != 0; i++)
1848 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
1850 if (table[i].mask != 0) /* it was in table? */
1851 continue; /* ignore it */
1852 else /* non-prologue */
1854 /* Return the current pc, adjusted backwards by 2 if
1855 the previous instruction was an extend. */
1856 return pc - prev_extend_bytes;
1862 /* To skip prologues, I use this predicate. Returns either PC itself
1863 if the code at PC does not look like a function prologue; otherwise
1864 returns an address that (if we're lucky) follows the prologue. If
1865 LENIENT, then we must skip everything which is involved in setting
1866 up the frame (it's OK to skip more, just so long as we don't skip
1867 anything which might clobber the registers which are being saved.
1868 We must skip more in the case where part of the prologue is in the
1869 delay slot of a non-prologue instruction). */
1872 mips_skip_prologue (pc, lenient)
1876 /* See if we can determine the end of the prologue via the symbol table.
1877 If so, then return either PC, or the PC after the prologue, whichever
1880 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
1882 if (post_prologue_pc != 0)
1883 return max (pc, post_prologue_pc);
1885 /* Can't determine prologue from the symbol table, need to examine
1888 if (IS_MIPS16_ADDR (pc))
1889 return mips16_skip_prologue (pc, lenient);
1891 return mips32_skip_prologue (pc, lenient);
1895 /* The lenient prologue stuff should be superseded by the code in
1896 init_extra_frame_info which looks to see whether the stores mentioned
1897 in the proc_desc have actually taken place. */
1899 /* Is address PC in the prologue (loosely defined) for function at
1903 mips_in_lenient_prologue (startaddr, pc)
1904 CORE_ADDR startaddr;
1907 CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1);
1908 return pc >= startaddr && pc < end_prologue;
1912 /* Given a return value in `regbuf' with a type `valtype',
1913 extract and copy its value into `valbuf'. */
1915 mips_extract_return_value (valtype, regbuf, valbuf)
1916 struct type *valtype;
1917 char regbuf[REGISTER_BYTES];
1922 int len = TYPE_LENGTH (valtype);
1925 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1926 && (mips_fpu == MIPS_FPU_DOUBLE
1927 || (mips_fpu == MIPS_FPU_SINGLE && len <= MIPS_REGSIZE)))
1928 regnum = FP0_REGNUM;
1930 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1931 { /* "un-left-justify" the value from the register */
1932 if (len < REGISTER_RAW_SIZE (regnum) &&
1933 TYPE_CODE (valtype) != TYPE_CODE_FLT)
1934 offset = REGISTER_RAW_SIZE (regnum) - len;
1935 if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */
1936 len < REGISTER_RAW_SIZE (regnum) * 2 &&
1937 (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
1938 TYPE_CODE (valtype) == TYPE_CODE_UNION))
1939 offset = 2 * REGISTER_RAW_SIZE (regnum) - len;
1941 memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len);
1942 REGISTER_CONVERT_TO_TYPE (regnum, valtype, valbuf);
1945 /* Given a return value in `regbuf' with a type `valtype',
1946 write it's value into the appropriate register. */
1948 mips_store_return_value (valtype, valbuf)
1949 struct type *valtype;
1954 int len = TYPE_LENGTH (valtype);
1955 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1958 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1959 && (mips_fpu == MIPS_FPU_DOUBLE
1960 || (mips_fpu == MIPS_FPU_SINGLE && len <= MIPS_REGSIZE)))
1961 regnum = FP0_REGNUM;
1963 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1964 { /* "left-justify" the value in the register */
1965 if (len < REGISTER_RAW_SIZE (regnum))
1966 offset = REGISTER_RAW_SIZE (regnum) - len;
1967 if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */
1968 len < REGISTER_RAW_SIZE (regnum) * 2 &&
1969 (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
1970 TYPE_CODE (valtype) == TYPE_CODE_UNION))
1971 offset = 2 * REGISTER_RAW_SIZE (regnum) - len;
1973 memcpy(raw_buffer + offset, valbuf, len);
1974 REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer);
1975 write_register_bytes(REGISTER_BYTE (regnum), raw_buffer,
1976 len > REGISTER_RAW_SIZE (regnum) ?
1977 len : REGISTER_RAW_SIZE (regnum));
1980 /* Exported procedure: Is PC in the signal trampoline code */
1983 in_sigtramp (pc, ignore)
1985 char *ignore; /* function name */
1987 if (sigtramp_address == 0)
1989 return (pc >= sigtramp_address && pc < sigtramp_end);
1992 /* Command to set FPU type. mips_fpu_string will have been set to the
1993 user's argument. Set mips_fpu based on mips_fpu_string, and then
1994 canonicalize mips_fpu_string. */
1998 mips_set_fpu_command (args, from_tty, c)
2001 struct cmd_list_element *c;
2005 if (mips_fpu_string == NULL || *mips_fpu_string == '\0')
2006 mips_fpu = MIPS_FPU_DOUBLE;
2007 else if (strcasecmp (mips_fpu_string, "double") == 0
2008 || strcasecmp (mips_fpu_string, "on") == 0
2009 || strcasecmp (mips_fpu_string, "1") == 0
2010 || strcasecmp (mips_fpu_string, "yes") == 0)
2011 mips_fpu = MIPS_FPU_DOUBLE;
2012 else if (strcasecmp (mips_fpu_string, "none") == 0
2013 || strcasecmp (mips_fpu_string, "off") == 0
2014 || strcasecmp (mips_fpu_string, "0") == 0
2015 || strcasecmp (mips_fpu_string, "no") == 0)
2016 mips_fpu = MIPS_FPU_NONE;
2017 else if (strcasecmp (mips_fpu_string, "single") == 0)
2018 mips_fpu = MIPS_FPU_SINGLE;
2020 err = strsave (mips_fpu_string);
2022 if (mips_fpu_string != NULL)
2023 free (mips_fpu_string);
2027 case MIPS_FPU_DOUBLE:
2028 mips_fpu_string = strsave ("double");
2030 case MIPS_FPU_SINGLE:
2031 mips_fpu_string = strsave ("single");
2034 mips_fpu_string = strsave ("none");
2040 struct cleanup *cleanups = make_cleanup (free, err);
2041 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2043 do_cleanups (cleanups);
2048 mips_show_fpu_command (args, from_tty, c)
2051 struct cmd_list_element *c;
2055 /* Command to set the processor type. */
2058 mips_set_processor_type_command (args, from_tty)
2064 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
2066 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2067 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
2068 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
2070 /* Restore the value. */
2071 tmp_mips_processor_type = strsave (mips_processor_type);
2076 if (!mips_set_processor_type (tmp_mips_processor_type))
2078 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
2079 /* Restore its value. */
2080 tmp_mips_processor_type = strsave (mips_processor_type);
2085 mips_show_processor_type_command (args, from_tty)
2091 /* Modify the actual processor type. */
2094 mips_set_processor_type (str)
2102 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
2104 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
2106 mips_processor_type = str;
2108 for (j = 0; j < NUM_REGS; ++j)
2109 reg_names[j] = mips_processor_type_table[i].regnames[j];
2113 /* FIXME tweak fpu flag too */
2120 /* Attempt to identify the particular processor model by reading the
2124 mips_read_processor_type ()
2128 prid = read_register (PRID_REGNUM);
2130 if ((prid & ~0xf) == 0x700)
2131 return savestring ("r3041", strlen("r3041"));
2136 /* Just like reinit_frame_cache, but with the right arguments to be
2137 callable as an sfunc. */
2140 reinit_frame_cache_sfunc (args, from_tty, c)
2143 struct cmd_list_element *c;
2145 reinit_frame_cache ();
2149 gdb_print_insn_mips (memaddr, info)
2151 disassemble_info *info;
2153 mips_extra_func_info_t proc_desc;
2155 /* Search for the function containing this address. Set the low bit
2156 of the address when searching, in case we were given an even address
2157 that is the start of a 16-bit function. If we didn't do this,
2158 the search would fail because the symbol table says the function
2159 starts at an odd address, i.e. 1 byte past the given address. */
2160 memaddr = ADDR_BITS_REMOVE (memaddr);
2161 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
2163 /* Make an attempt to determine if this is a 16-bit function. If
2164 the procedure descriptor exists and the address therein is odd,
2165 it's definitely a 16-bit function. Otherwise, we have to just
2166 guess that if the address passed in is odd, it's 16-bits. */
2168 info->mach = IS_MIPS16_ADDR (PROC_LOW_ADDR (proc_desc)) ? 16 : 0;
2170 info->mach = IS_MIPS16_ADDR (memaddr) ? 16 : 0;
2172 /* Round down the instruction address to the appropriate boundary. */
2173 memaddr &= (info->mach == 16 ? ~1 : ~3);
2175 /* Call the appropriate disassembler based on the target endian-ness. */
2176 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
2177 return print_insn_big_mips (memaddr, info);
2179 return print_insn_little_mips (memaddr, info);
2182 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2183 counter value to determine whether a 16- or 32-bit breakpoint should be
2184 used. It returns a pointer to a string of bytes that encode a breakpoint
2185 instruction, stores the length of the string to *lenptr, and adjusts pc
2186 (if necessary) to point to the actual memory location where the
2187 breakpoint should be inserted. */
2189 unsigned char *mips_breakpoint_from_pc (pcptr, lenptr)
2193 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
2195 if (IS_MIPS16_ADDR (*pcptr))
2197 static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT;
2198 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
2199 *lenptr = sizeof(mips16_big_breakpoint);
2200 return mips16_big_breakpoint;
2204 static char big_breakpoint[] = BIG_BREAKPOINT;
2205 static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
2206 static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
2208 *lenptr = sizeof(big_breakpoint);
2210 if (strcmp (target_shortname, "mips") == 0)
2211 return idt_big_breakpoint;
2212 else if (strcmp (target_shortname, "ddb") == 0
2213 || strcmp (target_shortname, "pmon") == 0
2214 || strcmp (target_shortname, "lsi") == 0)
2215 return pmon_big_breakpoint;
2217 return big_breakpoint;
2222 if (IS_MIPS16_ADDR (*pcptr))
2224 static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT;
2225 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
2226 *lenptr = sizeof(mips16_little_breakpoint);
2227 return mips16_little_breakpoint;
2231 static char little_breakpoint[] = LITTLE_BREAKPOINT;
2232 static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT;
2233 static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT;
2235 *lenptr = sizeof(little_breakpoint);
2237 if (strcmp (target_shortname, "mips") == 0)
2238 return idt_little_breakpoint;
2239 else if (strcmp (target_shortname, "ddb") == 0
2240 || strcmp (target_shortname, "pmon") == 0
2241 || strcmp (target_shortname, "lsi") == 0)
2242 return pmon_little_breakpoint;
2244 return little_breakpoint;
2249 /* Test whether the PC points to the return instruction at the
2250 end of a function. This implements the ABOUT_TO_RETURN macro. */
2253 mips_about_to_return (pc)
2256 if (IS_MIPS16_ADDR (pc))
2257 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2258 generates a "jr $ra"; other times it generates code to load
2259 the return address from the stack to an accessible register (such
2260 as $a3), then a "jr" using that register. This second case
2261 is almost impossible to distinguish from an indirect jump
2262 used for switch statements, so we don't even try. */
2263 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
2265 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
2269 /* If PC is in a mips16 call or return stub, return the address of the target
2270 PC, which is either the callee or the caller. There are several
2271 cases which must be handled:
2273 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2274 target PC is in $31 ($ra).
2275 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2276 and the target PC is in $2.
2277 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2278 before the jal instruction, this is effectively a call stub
2279 and the the target PC is in $2. Otherwise this is effectively
2280 a return stub and the target PC is in $18.
2282 See the source code for the stubs in gcc/config/mips/mips16.S for
2285 This function implements the SKIP_TRAMPOLINE_CODE macro.
2293 CORE_ADDR start_addr;
2295 /* Find the starting address and name of the function containing the PC. */
2296 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2299 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2300 target PC is in $31 ($ra). */
2301 if (strcmp (name, "__mips16_ret_sf") == 0
2302 || strcmp (name, "__mips16_ret_df") == 0)
2303 return read_register (RA_REGNUM);
2305 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
2307 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2308 and the target PC is in $2. */
2309 if (name[19] >= '0' && name[19] <= '9')
2310 return read_register (2);
2312 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2313 before the jal instruction, this is effectively a call stub
2314 and the the target PC is in $2. Otherwise this is effectively
2315 a return stub and the target PC is in $18. */
2316 else if (name[19] == 's' || name[19] == 'd')
2318 if (pc == start_addr)
2320 /* Check if the target of the stub is a compiler-generated
2321 stub. Such a stub for a function bar might have a name
2322 like __fn_stub_bar, and might look like this:
2327 la $1,bar (becomes a lui/addiu pair)
2329 So scan down to the lui/addi and extract the target
2330 address from those two instructions. */
2332 CORE_ADDR target_pc = read_register (2);
2336 /* See if the name of the target function is __fn_stub_*. */
2337 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
2339 if (strncmp (name, "__fn_stub_", 10) != 0
2340 && strcmp (name, "etext") != 0
2341 && strcmp (name, "_etext") != 0)
2344 /* Scan through this _fn_stub_ code for the lui/addiu pair.
2345 The limit on the search is arbitrarily set to 20
2346 instructions. FIXME. */
2347 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
2349 inst = mips_fetch_instruction (target_pc);
2350 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
2351 pc = (inst << 16) & 0xffff0000; /* high word */
2352 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
2353 return pc | (inst & 0xffff); /* low word */
2356 /* Couldn't find the lui/addui pair, so return stub address. */
2360 /* This is the 'return' part of a call stub. The return
2361 address is in $r18. */
2362 return read_register (18);
2365 return 0; /* not a stub */
2369 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
2370 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
2373 mips_in_call_stub (pc, name)
2377 CORE_ADDR start_addr;
2379 /* Find the starting address of the function containing the PC. If the
2380 caller didn't give us a name, look it up at the same time. */
2381 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
2384 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
2386 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
2387 if (name[19] >= '0' && name[19] <= '9')
2389 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2390 before the jal instruction, this is effectively a call stub. */
2391 else if (name[19] == 's' || name[19] == 'd')
2392 return pc == start_addr;
2395 return 0; /* not a stub */
2399 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
2400 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
2403 mips_in_return_stub (pc, name)
2407 CORE_ADDR start_addr;
2409 /* Find the starting address of the function containing the PC. */
2410 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
2413 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
2414 if (strcmp (name, "__mips16_ret_sf") == 0
2415 || strcmp (name, "__mips16_ret_df") == 0)
2418 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
2419 i.e. after the jal instruction, this is effectively a return stub. */
2420 if (strncmp (name, "__mips16_call_stub_", 19) == 0
2421 && (name[19] == 's' || name[19] == 'd')
2422 && pc != start_addr)
2425 return 0; /* not a stub */
2429 /* Return non-zero if the PC is in a library helper function that should
2430 be ignored. This implements the IGNORE_HELPER_CALL macro. */
2433 mips_ignore_helper (pc)
2438 /* Find the starting address and name of the function containing the PC. */
2439 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
2442 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
2443 that we want to ignore. */
2444 return (strcmp (name, "__mips16_ret_sf") == 0
2445 || strcmp (name, "__mips16_ret_df") == 0);
2450 _initialize_mips_tdep ()
2452 struct cmd_list_element *c;
2454 tm_print_insn = gdb_print_insn_mips;
2456 /* Let the user turn off floating point and set the fence post for
2457 heuristic_proc_start. */
2459 c = add_set_cmd ("mipsfpu", class_support, var_string_noescape,
2460 (char *) &mips_fpu_string,
2461 "Set use of floating point coprocessor.\n\
2462 Set to `none' to avoid using floating point instructions when calling\n\
2463 functions or dealing with return values. Set to `single' to use only\n\
2464 single precision floating point as on the R4650. Set to `double' for\n\
2465 normal floating point support.",
2467 c->function.sfunc = mips_set_fpu_command;
2468 c = add_show_from_set (c, &showlist);
2469 c->function.sfunc = mips_show_fpu_command;
2471 mips_fpu = MIPS_FPU_DOUBLE;
2472 mips_fpu_string = strsave ("double");
2474 c = add_set_cmd ("processor", class_support, var_string_noescape,
2475 (char *) &tmp_mips_processor_type,
2476 "Set the type of MIPS processor in use.\n\
2477 Set this to be able to access processor-type-specific registers.\n\
2480 c->function.cfunc = mips_set_processor_type_command;
2481 c = add_show_from_set (c, &showlist);
2482 c->function.cfunc = mips_show_processor_type_command;
2484 tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE);
2485 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0);
2487 /* We really would like to have both "0" and "unlimited" work, but
2488 command.c doesn't deal with that. So make it a var_zinteger
2489 because the user can always use "999999" or some such for unlimited. */
2490 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
2491 (char *) &heuristic_fence_post,
2493 Set the distance searched for the start of a function.\n\
2494 If you are debugging a stripped executable, GDB needs to search through the\n\
2495 program for the start of a function. This command sets the distance of the\n\
2496 search. The only need to set it is when debugging a stripped executable.",
2498 /* We need to throw away the frame cache when we set this, since it
2499 might change our ability to get backtraces. */
2500 c->function.sfunc = reinit_frame_cache_sfunc;
2501 add_show_from_set (c, &showlist);