1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
62 static const struct objfile_data *mips_pdr_data;
64 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE = 4,
75 MIPS_FPU_DOUBLE_REGSIZE = 8
84 static const char *mips_abi_string;
86 static const char *mips_abi_strings[] = {
97 /* The standard register names, and all the valid aliases for them. */
104 /* Aliases for o32 and most other ABIs. */
105 const struct register_alias mips_o32_aliases[] = {
112 /* Aliases for n32 and n64. */
113 const struct register_alias mips_n32_n64_aliases[] = {
120 /* Aliases for ABI-independent registers. */
121 const struct register_alias mips_register_aliases[] = {
122 /* The architecture manuals specify these ABI-independent names for
124 #define R(n) { "r" #n, n }
125 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
131 /* k0 and k1 are sometimes called these instead (for "kernel
136 /* This is the traditional GDB name for the CP0 status register. */
137 { "sr", MIPS_PS_REGNUM },
139 /* This is the traditional GDB name for the CP0 BadVAddr register. */
140 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
142 /* This is the traditional GDB name for the FCSR. */
143 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
146 #ifndef MIPS_DEFAULT_FPU_TYPE
147 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
149 static int mips_fpu_type_auto = 1;
150 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
152 static int mips_debug = 0;
154 /* Properties (for struct target_desc) describing the g/G packet
156 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
157 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
159 struct target_desc *mips_tdesc_gp32;
160 struct target_desc *mips_tdesc_gp64;
162 const struct mips_regnum *
163 mips_regnum (struct gdbarch *gdbarch)
165 return gdbarch_tdep (gdbarch)->regnum;
169 mips_fpa0_regnum (struct gdbarch *gdbarch)
171 return mips_regnum (gdbarch)->fp0 + 12;
174 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
176 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
178 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
180 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
182 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
184 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
185 functions to test, set, or clear bit 0 of addresses. */
188 is_mips16_addr (CORE_ADDR addr)
194 unmake_mips16_addr (CORE_ADDR addr)
196 return ((addr) & ~(CORE_ADDR) 1);
199 /* Return the MIPS ABI associated with GDBARCH. */
201 mips_abi (struct gdbarch *gdbarch)
203 return gdbarch_tdep (gdbarch)->mips_abi;
207 mips_isa_regsize (struct gdbarch *gdbarch)
209 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
211 /* If we know how big the registers are, use that size. */
212 if (tdep->register_size_valid_p)
213 return tdep->register_size;
215 /* Fall back to the previous behavior. */
216 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
217 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
220 /* Return the currently configured (or set) saved register size. */
223 mips_abi_regsize (struct gdbarch *gdbarch)
225 switch (mips_abi (gdbarch))
227 case MIPS_ABI_EABI32:
233 case MIPS_ABI_EABI64:
235 case MIPS_ABI_UNKNOWN:
238 internal_error (__FILE__, __LINE__, _("bad switch"));
242 /* Functions for setting and testing a bit in a minimal symbol that
243 marks it as 16-bit function. The MSB of the minimal symbol's
244 "info" field is used for this purpose.
246 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
247 i.e. refers to a 16-bit function, and sets a "special" bit in a
248 minimal symbol to mark it as a 16-bit function
250 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
253 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
255 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
257 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
258 SYMBOL_VALUE_ADDRESS (msym) |= 1;
263 msymbol_is_special (struct minimal_symbol *msym)
265 return MSYMBOL_TARGET_FLAG_1 (msym);
268 /* XFER a value from the big/little/left end of the register.
269 Depending on the size of the value it might occupy the entire
270 register or just part of it. Make an allowance for this, aligning
271 things accordingly. */
274 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
275 int reg_num, int length,
276 enum bfd_endian endian, gdb_byte *in,
277 const gdb_byte *out, int buf_offset)
281 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
282 /* Need to transfer the left or right part of the register, based on
283 the targets byte order. */
287 reg_offset = register_size (gdbarch, reg_num) - length;
289 case BFD_ENDIAN_LITTLE:
292 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
296 internal_error (__FILE__, __LINE__, _("bad switch"));
299 fprintf_unfiltered (gdb_stderr,
300 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
301 reg_num, reg_offset, buf_offset, length);
302 if (mips_debug && out != NULL)
305 fprintf_unfiltered (gdb_stdlog, "out ");
306 for (i = 0; i < length; i++)
307 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
310 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
313 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
315 if (mips_debug && in != NULL)
318 fprintf_unfiltered (gdb_stdlog, "in ");
319 for (i = 0; i < length; i++)
320 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
323 fprintf_unfiltered (gdb_stdlog, "\n");
326 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
327 compatiblity mode. A return value of 1 means that we have
328 physical 64-bit registers, but should treat them as 32-bit registers. */
331 mips2_fp_compat (struct frame_info *frame)
333 struct gdbarch *gdbarch = get_frame_arch (frame);
334 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
336 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
340 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
341 in all the places we deal with FP registers. PR gdb/413. */
342 /* Otherwise check the FR bit in the status register - it controls
343 the FP compatiblity mode. If it is clear we are in compatibility
345 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
352 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
354 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
356 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
358 static struct type *mips_float_register_type (void);
359 static struct type *mips_double_register_type (void);
361 /* The list of available "set mips " and "show mips " commands */
363 static struct cmd_list_element *setmipscmdlist = NULL;
364 static struct cmd_list_element *showmipscmdlist = NULL;
366 /* Integer registers 0 thru 31 are handled explicitly by
367 mips_register_name(). Processor specific registers 32 and above
368 are listed in the following tables. */
371 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
375 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
376 "sr", "lo", "hi", "bad", "cause", "pc",
377 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
378 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
379 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
380 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
381 "fsr", "fir", "" /*"fp" */ , "",
382 "", "", "", "", "", "", "", "",
383 "", "", "", "", "", "", "", "",
386 /* Names of IDT R3041 registers. */
388 static const char *mips_r3041_reg_names[] = {
389 "sr", "lo", "hi", "bad", "cause", "pc",
390 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
391 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
392 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
393 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
394 "fsr", "fir", "", /*"fp" */ "",
395 "", "", "bus", "ccfg", "", "", "", "",
396 "", "", "port", "cmp", "", "", "epc", "prid",
399 /* Names of tx39 registers. */
401 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
402 "sr", "lo", "hi", "bad", "cause", "pc",
403 "", "", "", "", "", "", "", "",
404 "", "", "", "", "", "", "", "",
405 "", "", "", "", "", "", "", "",
406 "", "", "", "", "", "", "", "",
408 "", "", "", "", "", "", "", "",
409 "", "", "config", "cache", "debug", "depc", "epc", ""
412 /* Names of IRIX registers. */
413 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
414 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
415 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
416 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
417 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
418 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
422 /* Return the name of the register corresponding to REGNO. */
424 mips_register_name (struct gdbarch *gdbarch, int regno)
426 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
427 /* GPR names for all ABIs other than n32/n64. */
428 static char *mips_gpr_names[] = {
429 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
430 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
431 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
432 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
435 /* GPR names for n32 and n64 ABIs. */
436 static char *mips_n32_n64_gpr_names[] = {
437 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
438 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
439 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
440 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
443 enum mips_abi abi = mips_abi (gdbarch);
445 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
446 but then don't make the raw register names visible. */
447 int rawnum = regno % gdbarch_num_regs (gdbarch);
448 if (regno < gdbarch_num_regs (gdbarch))
451 /* The MIPS integer registers are always mapped from 0 to 31. The
452 names of the registers (which reflects the conventions regarding
453 register use) vary depending on the ABI. */
454 if (0 <= rawnum && rawnum < 32)
456 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
457 return mips_n32_n64_gpr_names[rawnum];
459 return mips_gpr_names[rawnum];
461 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
462 return tdesc_register_name (gdbarch, rawnum);
463 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
465 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
466 return tdep->mips_processor_reg_names[rawnum - 32];
469 internal_error (__FILE__, __LINE__,
470 _("mips_register_name: bad register number %d"), rawnum);
473 /* Return the groups that a MIPS register can be categorised into. */
476 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
477 struct reggroup *reggroup)
482 int rawnum = regnum % gdbarch_num_regs (gdbarch);
483 int pseudo = regnum / gdbarch_num_regs (gdbarch);
484 if (reggroup == all_reggroup)
486 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
487 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
488 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
489 (gdbarch), as not all architectures are multi-arch. */
490 raw_p = rawnum < gdbarch_num_regs (gdbarch);
491 if (gdbarch_register_name (gdbarch, regnum) == NULL
492 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
494 if (reggroup == float_reggroup)
495 return float_p && pseudo;
496 if (reggroup == vector_reggroup)
497 return vector_p && pseudo;
498 if (reggroup == general_reggroup)
499 return (!vector_p && !float_p) && pseudo;
500 /* Save the pseudo registers. Need to make certain that any code
501 extracting register values from a saved register cache also uses
503 if (reggroup == save_reggroup)
504 return raw_p && pseudo;
505 /* Restore the same pseudo register. */
506 if (reggroup == restore_reggroup)
507 return raw_p && pseudo;
511 /* Return the groups that a MIPS register can be categorised into.
512 This version is only used if we have a target description which
513 describes real registers (and their groups). */
516 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
517 struct reggroup *reggroup)
519 int rawnum = regnum % gdbarch_num_regs (gdbarch);
520 int pseudo = regnum / gdbarch_num_regs (gdbarch);
523 /* Only save, restore, and display the pseudo registers. Need to
524 make certain that any code extracting register values from a
525 saved register cache also uses pseudo registers.
527 Note: saving and restoring the pseudo registers is slightly
528 strange; if we have 64 bits, we should save and restore all
529 64 bits. But this is hard and has little benefit. */
533 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
537 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
540 /* Map the symbol table registers which live in the range [1 *
541 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
542 registers. Take care of alignment and size problems. */
545 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
546 int cookednum, gdb_byte *buf)
548 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
549 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
550 && cookednum < 2 * gdbarch_num_regs (gdbarch));
551 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
552 regcache_raw_read (regcache, rawnum, buf);
553 else if (register_size (gdbarch, rawnum) >
554 register_size (gdbarch, cookednum))
556 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
557 || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
558 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
560 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
563 internal_error (__FILE__, __LINE__, _("bad register size"));
567 mips_pseudo_register_write (struct gdbarch *gdbarch,
568 struct regcache *regcache, int cookednum,
571 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
572 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
573 && cookednum < 2 * gdbarch_num_regs (gdbarch));
574 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
575 regcache_raw_write (regcache, rawnum, buf);
576 else if (register_size (gdbarch, rawnum) >
577 register_size (gdbarch, cookednum))
579 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
580 || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
581 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
583 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
586 internal_error (__FILE__, __LINE__, _("bad register size"));
589 /* Table to translate MIPS16 register field to actual register number. */
590 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
592 /* Heuristic_proc_start may hunt through the text section for a long
593 time across a 2400 baud serial line. Allows the user to limit this
596 static unsigned int heuristic_fence_post = 0;
598 /* Number of bytes of storage in the actual machine representation for
599 register N. NOTE: This defines the pseudo register type so need to
600 rebuild the architecture vector. */
602 static int mips64_transfers_32bit_regs_p = 0;
605 set_mips64_transfers_32bit_regs (char *args, int from_tty,
606 struct cmd_list_element *c)
608 struct gdbarch_info info;
609 gdbarch_info_init (&info);
610 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
611 instead of relying on globals. Doing that would let generic code
612 handle the search for this specific architecture. */
613 if (!gdbarch_update_p (info))
615 mips64_transfers_32bit_regs_p = 0;
616 error (_("32-bit compatibility mode not supported"));
620 /* Convert to/from a register and the corresponding memory value. */
623 mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
625 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
626 && register_size (gdbarch, regnum) == 4
627 && (regnum % gdbarch_num_regs (gdbarch))
628 >= mips_regnum (gdbarch)->fp0
629 && (regnum % gdbarch_num_regs (gdbarch))
630 < mips_regnum (gdbarch)->fp0 + 32
631 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
635 mips_register_to_value (struct frame_info *frame, int regnum,
636 struct type *type, gdb_byte *to)
638 get_frame_register (frame, regnum + 0, to + 4);
639 get_frame_register (frame, regnum + 1, to + 0);
643 mips_value_to_register (struct frame_info *frame, int regnum,
644 struct type *type, const gdb_byte *from)
646 put_frame_register (frame, regnum + 0, from + 4);
647 put_frame_register (frame, regnum + 1, from + 0);
650 /* Return the GDB type object for the "standard" data type of data in
654 mips_register_type (struct gdbarch *gdbarch, int regnum)
656 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
657 if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0
658 && (regnum % gdbarch_num_regs (gdbarch))
659 < mips_regnum (gdbarch)->fp0 + 32)
661 /* The floating-point registers raw, or cooked, always match
662 mips_isa_regsize(), and also map 1:1, byte for byte. */
663 if (mips_isa_regsize (gdbarch) == 4)
664 return builtin_type_ieee_single;
666 return builtin_type_ieee_double;
668 else if (regnum < gdbarch_num_regs (gdbarch))
670 /* The raw or ISA registers. These are all sized according to
672 if (mips_isa_regsize (gdbarch) == 4)
673 return builtin_type_int32;
675 return builtin_type_int64;
679 /* The cooked or ABI registers. These are sized according to
680 the ABI (with a few complications). */
681 if (regnum >= (gdbarch_num_regs (gdbarch)
682 + mips_regnum (gdbarch)->fp_control_status)
683 && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM)
684 /* The pseudo/cooked view of the embedded registers is always
685 32-bit. The raw view is handled below. */
686 return builtin_type_int32;
687 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
688 /* The target, while possibly using a 64-bit register buffer,
689 is only transfering 32-bits of each integer register.
690 Reflect this in the cooked/pseudo (ABI) register value. */
691 return builtin_type_int32;
692 else if (mips_abi_regsize (gdbarch) == 4)
693 /* The ABI is restricted to 32-bit registers (the ISA could be
695 return builtin_type_int32;
698 return builtin_type_int64;
702 /* Return the GDB type for the pseudo register REGNUM, which is the
703 ABI-level view. This function is only called if there is a target
704 description which includes registers, so we know precisely the
705 types of hardware registers. */
708 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
710 const int num_regs = gdbarch_num_regs (gdbarch);
711 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
712 int rawnum = regnum % num_regs;
713 struct type *rawtype;
715 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
717 /* Absent registers are still absent. */
718 rawtype = gdbarch_register_type (gdbarch, rawnum);
719 if (TYPE_LENGTH (rawtype) == 0)
722 if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32)
723 /* Present the floating point registers however the hardware did;
724 do not try to convert between FPU layouts. */
727 if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM)
729 /* The pseudo/cooked view of embedded registers is always
730 32-bit, even if the target transfers 64-bit values for them.
731 New targets relying on XML descriptions should only transfer
732 the necessary 32 bits, but older versions of GDB expected 64,
733 so allow the target to provide 64 bits without interfering
734 with the displayed type. */
735 return builtin_type_int32;
738 /* Use pointer types for registers if we can. For n32 we can not,
739 since we do not have a 64-bit pointer type. */
740 if (mips_abi_regsize (gdbarch)
741 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
743 if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM)
744 return builtin_type (gdbarch)->builtin_data_ptr;
745 else if (rawnum == MIPS_EMBED_PC_REGNUM)
746 return builtin_type (gdbarch)->builtin_func_ptr;
749 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
750 && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM)
751 return builtin_type_int32;
753 /* For all other registers, pass through the hardware type. */
757 /* Should the upper word of 64-bit addresses be zeroed? */
758 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
761 mips_mask_address_p (struct gdbarch_tdep *tdep)
763 switch (mask_address_var)
765 case AUTO_BOOLEAN_TRUE:
767 case AUTO_BOOLEAN_FALSE:
770 case AUTO_BOOLEAN_AUTO:
771 return tdep->default_mask_address_p;
773 internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch"));
779 show_mask_address (struct ui_file *file, int from_tty,
780 struct cmd_list_element *c, const char *value)
782 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
784 deprecated_show_value_hack (file, from_tty, c, value);
785 switch (mask_address_var)
787 case AUTO_BOOLEAN_TRUE:
788 printf_filtered ("The 32 bit mips address mask is enabled\n");
790 case AUTO_BOOLEAN_FALSE:
791 printf_filtered ("The 32 bit mips address mask is disabled\n");
793 case AUTO_BOOLEAN_AUTO:
795 ("The 32 bit address mask is set automatically. Currently %s\n",
796 mips_mask_address_p (tdep) ? "enabled" : "disabled");
799 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
804 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
807 mips_pc_is_mips16 (CORE_ADDR memaddr)
809 struct minimal_symbol *sym;
811 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
812 if (is_mips16_addr (memaddr))
815 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
816 the high bit of the info field. Use this to decide if the function is
817 MIPS16 or normal MIPS. */
818 sym = lookup_minimal_symbol_by_pc (memaddr);
820 return msymbol_is_special (sym);
825 /* MIPS believes that the PC has a sign extended value. Perhaps the
826 all registers should be sign extended for simplicity? */
829 mips_read_pc (struct regcache *regcache)
832 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
833 regcache_cooked_read_signed (regcache, regnum, &pc);
838 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
840 return frame_unwind_register_signed
841 (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc);
845 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
847 return frame_unwind_register_signed
848 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
851 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
852 dummy frame. The frame ID's base needs to match the TOS value
853 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
856 static struct frame_id
857 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
859 return frame_id_build
860 (get_frame_register_signed (this_frame,
861 gdbarch_num_regs (gdbarch)
863 get_frame_pc (this_frame));
867 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
869 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
870 regcache_cooked_write_unsigned (regcache, regnum, pc);
873 /* Fetch and return instruction from the specified location. If the PC
874 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
877 mips_fetch_instruction (CORE_ADDR addr)
879 gdb_byte buf[MIPS_INSN32_SIZE];
883 if (mips_pc_is_mips16 (addr))
885 instlen = MIPS_INSN16_SIZE;
886 addr = unmake_mips16_addr (addr);
889 instlen = MIPS_INSN32_SIZE;
890 status = target_read_memory (addr, buf, instlen);
892 memory_error (status, addr);
893 return extract_unsigned_integer (buf, instlen);
896 /* These the fields of 32 bit mips instructions */
897 #define mips32_op(x) (x >> 26)
898 #define itype_op(x) (x >> 26)
899 #define itype_rs(x) ((x >> 21) & 0x1f)
900 #define itype_rt(x) ((x >> 16) & 0x1f)
901 #define itype_immediate(x) (x & 0xffff)
903 #define jtype_op(x) (x >> 26)
904 #define jtype_target(x) (x & 0x03ffffff)
906 #define rtype_op(x) (x >> 26)
907 #define rtype_rs(x) ((x >> 21) & 0x1f)
908 #define rtype_rt(x) ((x >> 16) & 0x1f)
909 #define rtype_rd(x) ((x >> 11) & 0x1f)
910 #define rtype_shamt(x) ((x >> 6) & 0x1f)
911 #define rtype_funct(x) (x & 0x3f)
914 mips32_relative_offset (ULONGEST inst)
916 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
919 /* Determine where to set a single step breakpoint while considering
920 branch prediction. */
922 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
926 inst = mips_fetch_instruction (pc);
927 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
929 if (itype_op (inst) >> 2 == 5)
930 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
932 op = (itype_op (inst) & 0x03);
947 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
948 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
950 int tf = itype_rt (inst) & 0x01;
951 int cnum = itype_rt (inst) >> 2;
953 get_frame_register_signed (frame,
954 mips_regnum (get_frame_arch (frame))->
956 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
958 if (((cond >> cnum) & 0x01) == tf)
959 pc += mips32_relative_offset (inst) + 4;
964 pc += 4; /* Not a branch, next instruction is easy */
967 { /* This gets way messy */
969 /* Further subdivide into SPECIAL, REGIMM and other */
970 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
972 case 0: /* SPECIAL */
973 op = rtype_funct (inst);
978 /* Set PC to that address */
979 pc = get_frame_register_signed (frame, rtype_rs (inst));
981 case 12: /* SYSCALL */
983 struct gdbarch_tdep *tdep;
985 tdep = gdbarch_tdep (get_frame_arch (frame));
986 if (tdep->syscall_next_pc != NULL)
987 pc = tdep->syscall_next_pc (frame);
996 break; /* end SPECIAL */
999 op = itype_rt (inst); /* branch condition */
1004 case 16: /* BLTZAL */
1005 case 18: /* BLTZALL */
1007 if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1008 pc += mips32_relative_offset (inst) + 4;
1010 pc += 8; /* after the delay slot */
1014 case 17: /* BGEZAL */
1015 case 19: /* BGEZALL */
1016 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1017 pc += mips32_relative_offset (inst) + 4;
1019 pc += 8; /* after the delay slot */
1021 /* All of the other instructions in the REGIMM category */
1026 break; /* end REGIMM */
1031 reg = jtype_target (inst) << 2;
1032 /* Upper four bits get never changed... */
1033 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1036 /* FIXME case JALX : */
1039 reg = jtype_target (inst) << 2;
1040 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */
1041 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1043 break; /* The new PC will be alternate mode */
1044 case 4: /* BEQ, BEQL */
1046 if (get_frame_register_signed (frame, itype_rs (inst)) ==
1047 get_frame_register_signed (frame, itype_rt (inst)))
1048 pc += mips32_relative_offset (inst) + 4;
1052 case 5: /* BNE, BNEL */
1054 if (get_frame_register_signed (frame, itype_rs (inst)) !=
1055 get_frame_register_signed (frame, itype_rt (inst)))
1056 pc += mips32_relative_offset (inst) + 4;
1060 case 6: /* BLEZ, BLEZL */
1061 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1062 pc += mips32_relative_offset (inst) + 4;
1068 greater_branch: /* BGTZ, BGTZL */
1069 if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1070 pc += mips32_relative_offset (inst) + 4;
1077 } /* mips32_next_pc */
1079 /* Decoding the next place to set a breakpoint is irregular for the
1080 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1081 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1082 We dont want to set a single step instruction on the extend instruction
1086 /* Lots of mips16 instruction formats */
1087 /* Predicting jumps requires itype,ritype,i8type
1088 and their extensions extItype,extritype,extI8type
1090 enum mips16_inst_fmts
1092 itype, /* 0 immediate 5,10 */
1093 ritype, /* 1 5,3,8 */
1094 rrtype, /* 2 5,3,3,5 */
1095 rritype, /* 3 5,3,3,5 */
1096 rrrtype, /* 4 5,3,3,3,2 */
1097 rriatype, /* 5 5,3,3,1,4 */
1098 shifttype, /* 6 5,3,3,3,2 */
1099 i8type, /* 7 5,3,8 */
1100 i8movtype, /* 8 5,3,3,5 */
1101 i8mov32rtype, /* 9 5,3,5,3 */
1102 i64type, /* 10 5,3,8 */
1103 ri64type, /* 11 5,3,3,5 */
1104 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1105 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1106 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1107 extRRItype, /* 15 5,5,5,5,3,3,5 */
1108 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1109 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1110 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1111 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1112 extRi64type, /* 20 5,6,5,5,3,3,5 */
1113 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1115 /* I am heaping all the fields of the formats into one structure and
1116 then, only the fields which are involved in instruction extension */
1120 unsigned int regx; /* Function in i8 type */
1125 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1126 for the bits which make up the immediate extension. */
1129 extended_offset (unsigned int extension)
1132 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1134 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1136 value |= extension & 0x01f; /* extract 4:0 */
1140 /* Only call this function if you know that this is an extendable
1141 instruction. It won't malfunction, but why make excess remote memory
1142 references? If the immediate operands get sign extended or something,
1143 do it after the extension is performed. */
1144 /* FIXME: Every one of these cases needs to worry about sign extension
1145 when the offset is to be used in relative addressing. */
1148 fetch_mips_16 (CORE_ADDR pc)
1151 pc &= 0xfffffffe; /* clear the low order bit */
1152 target_read_memory (pc, buf, 2);
1153 return extract_unsigned_integer (buf, 2);
1157 unpack_mips16 (CORE_ADDR pc,
1158 unsigned int extension,
1160 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1165 switch (insn_format)
1172 value = extended_offset (extension);
1173 value = value << 11; /* rom for the original value */
1174 value |= inst & 0x7ff; /* eleven bits from instruction */
1178 value = inst & 0x7ff;
1179 /* FIXME : Consider sign extension */
1188 { /* A register identifier and an offset */
1189 /* Most of the fields are the same as I type but the
1190 immediate value is of a different length */
1194 value = extended_offset (extension);
1195 value = value << 8; /* from the original instruction */
1196 value |= inst & 0xff; /* eleven bits from instruction */
1197 regx = (extension >> 8) & 0x07; /* or i8 funct */
1198 if (value & 0x4000) /* test the sign bit , bit 26 */
1200 value &= ~0x3fff; /* remove the sign bit */
1206 value = inst & 0xff; /* 8 bits */
1207 regx = (inst >> 8) & 0x07; /* or i8 funct */
1208 /* FIXME: Do sign extension , this format needs it */
1209 if (value & 0x80) /* THIS CONFUSES ME */
1211 value &= 0xef; /* remove the sign bit */
1221 unsigned long value;
1222 unsigned int nexthalf;
1223 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1224 value = value << 16;
1225 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1233 internal_error (__FILE__, __LINE__, _("bad switch"));
1235 upk->offset = offset;
1242 add_offset_16 (CORE_ADDR pc, int offset)
1244 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
1248 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
1249 unsigned int extension, unsigned int insn)
1251 int op = (insn >> 11);
1254 case 2: /* Branch */
1257 struct upk_mips16 upk;
1258 unpack_mips16 (pc, extension, insn, itype, &upk);
1259 offset = upk.offset;
1265 pc += (offset << 1) + 2;
1268 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1270 struct upk_mips16 upk;
1271 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1272 pc = add_offset_16 (pc, upk.offset);
1273 if ((insn >> 10) & 0x01) /* Exchange mode */
1274 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1281 struct upk_mips16 upk;
1283 unpack_mips16 (pc, extension, insn, ritype, &upk);
1284 reg = get_frame_register_signed (frame, upk.regx);
1286 pc += (upk.offset << 1) + 2;
1293 struct upk_mips16 upk;
1295 unpack_mips16 (pc, extension, insn, ritype, &upk);
1296 reg = get_frame_register_signed (frame, upk.regx);
1298 pc += (upk.offset << 1) + 2;
1303 case 12: /* I8 Formats btez btnez */
1305 struct upk_mips16 upk;
1307 unpack_mips16 (pc, extension, insn, i8type, &upk);
1308 /* upk.regx contains the opcode */
1309 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
1310 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1311 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1312 /* pc = add_offset_16(pc,upk.offset) ; */
1313 pc += (upk.offset << 1) + 2;
1318 case 29: /* RR Formats JR, JALR, JALR-RA */
1320 struct upk_mips16 upk;
1321 /* upk.fmt = rrtype; */
1326 upk.regx = (insn >> 8) & 0x07;
1327 upk.regy = (insn >> 5) & 0x07;
1335 break; /* Function return instruction */
1341 break; /* BOGUS Guess */
1343 pc = get_frame_register_signed (frame, reg);
1350 /* This is an instruction extension. Fetch the real instruction
1351 (which follows the extension) and decode things based on
1355 pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc));
1368 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
1370 unsigned int insn = fetch_mips_16 (pc);
1371 return extended_mips16_next_pc (frame, pc, 0, insn);
1374 /* The mips_next_pc function supports single_step when the remote
1375 target monitor or stub is not developed enough to do a single_step.
1376 It works by decoding the current instruction and predicting where a
1377 branch will go. This isnt hard because all the data is available.
1378 The MIPS32 and MIPS16 variants are quite different. */
1380 mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1382 if (is_mips16_addr (pc))
1383 return mips16_next_pc (frame, pc);
1385 return mips32_next_pc (frame, pc);
1388 struct mips_frame_cache
1391 struct trad_frame_saved_reg *saved_regs;
1394 /* Set a register's saved stack address in temp_saved_regs. If an
1395 address has already been set for this register, do nothing; this
1396 way we will only recognize the first save of a given register in a
1399 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1400 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1401 Strictly speaking, only the second range is used as it is only second
1402 range (the ABI instead of ISA registers) that comes into play when finding
1403 saved registers in a frame. */
1406 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
1407 int regnum, CORE_ADDR offset)
1409 if (this_cache != NULL
1410 && this_cache->saved_regs[regnum].addr == -1)
1412 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
1414 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
1420 /* Fetch the immediate value from a MIPS16 instruction.
1421 If the previous instruction was an EXTEND, use it to extend
1422 the upper bits of the immediate value. This is a helper function
1423 for mips16_scan_prologue. */
1426 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1427 unsigned short inst, /* current instruction */
1428 int nbits, /* number of bits in imm field */
1429 int scale, /* scale factor to be applied to imm */
1430 int is_signed) /* is the imm field signed? */
1434 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1436 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1437 if (offset & 0x8000) /* check for negative extend */
1438 offset = 0 - (0x10000 - (offset & 0xffff));
1439 return offset | (inst & 0x1f);
1443 int max_imm = 1 << nbits;
1444 int mask = max_imm - 1;
1445 int sign_bit = max_imm >> 1;
1447 offset = inst & mask;
1448 if (is_signed && (offset & sign_bit))
1449 offset = 0 - (max_imm - offset);
1450 return offset * scale;
1455 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1456 the associated FRAME_CACHE if not null.
1457 Return the address of the first instruction past the prologue. */
1460 mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1461 struct frame_info *this_frame,
1462 struct mips_frame_cache *this_cache)
1465 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1467 long frame_offset = 0; /* Size of stack frame. */
1468 long frame_adjust = 0; /* Offset of FP from SP. */
1469 int frame_reg = MIPS_SP_REGNUM;
1470 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1471 unsigned inst = 0; /* current instruction */
1472 unsigned entry_inst = 0; /* the entry instruction */
1473 unsigned save_inst = 0; /* the save instruction */
1476 int extend_bytes = 0;
1477 int prev_extend_bytes;
1478 CORE_ADDR end_prologue_addr = 0;
1479 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1481 /* Can be called when there's no process, and hence when there's no
1483 if (this_frame != NULL)
1484 sp = get_frame_register_signed (this_frame,
1485 gdbarch_num_regs (gdbarch)
1490 if (limit_pc > start_pc + 200)
1491 limit_pc = start_pc + 200;
1493 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
1495 /* Save the previous instruction. If it's an EXTEND, we'll extract
1496 the immediate offset extension from it in mips16_get_imm. */
1499 /* Fetch and decode the instruction. */
1500 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1502 /* Normally we ignore extend instructions. However, if it is
1503 not followed by a valid prologue instruction, then this
1504 instruction is not part of the prologue either. We must
1505 remember in this case to adjust the end_prologue_addr back
1507 if ((inst & 0xf800) == 0xf000) /* extend */
1509 extend_bytes = MIPS_INSN16_SIZE;
1513 prev_extend_bytes = extend_bytes;
1516 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1517 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1519 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1520 if (offset < 0) /* negative stack adjustment? */
1521 frame_offset -= offset;
1523 /* Exit loop if a positive stack adjustment is found, which
1524 usually means that the stack cleanup code in the function
1525 epilogue is reached. */
1528 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1530 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1531 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1532 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1534 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1536 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1537 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1538 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1540 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1542 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1543 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1545 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1547 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1548 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1550 else if (inst == 0x673d) /* move $s1, $sp */
1555 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1557 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1558 frame_addr = sp + offset;
1560 frame_adjust = offset;
1562 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1564 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1565 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1566 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
1568 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1570 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1571 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1572 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
1574 else if ((inst & 0xf81f) == 0xe809
1575 && (inst & 0x700) != 0x700) /* entry */
1576 entry_inst = inst; /* save for later processing */
1577 else if ((inst & 0xff80) == 0x6480) /* save */
1579 save_inst = inst; /* save for later processing */
1580 if (prev_extend_bytes) /* extend */
1581 save_inst |= prev_inst << 16;
1583 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1584 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
1585 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1587 /* This instruction is part of the prologue, but we don't
1588 need to do anything special to handle it. */
1592 /* This instruction is not an instruction typically found
1593 in a prologue, so we must have reached the end of the
1595 if (end_prologue_addr == 0)
1596 end_prologue_addr = cur_pc - prev_extend_bytes;
1600 /* The entry instruction is typically the first instruction in a function,
1601 and it stores registers at offsets relative to the value of the old SP
1602 (before the prologue). But the value of the sp parameter to this
1603 function is the new SP (after the prologue has been executed). So we
1604 can't calculate those offsets until we've seen the entire prologue,
1605 and can calculate what the old SP must have been. */
1606 if (entry_inst != 0)
1608 int areg_count = (entry_inst >> 8) & 7;
1609 int sreg_count = (entry_inst >> 6) & 3;
1611 /* The entry instruction always subtracts 32 from the SP. */
1614 /* Now we can calculate what the SP must have been at the
1615 start of the function prologue. */
1618 /* Check if a0-a3 were saved in the caller's argument save area. */
1619 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1621 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1622 offset += mips_abi_regsize (gdbarch);
1625 /* Check if the ra register was pushed on the stack. */
1627 if (entry_inst & 0x20)
1629 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1630 offset -= mips_abi_regsize (gdbarch);
1633 /* Check if the s0 and s1 registers were pushed on the stack. */
1634 for (reg = 16; reg < sreg_count + 16; reg++)
1636 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1637 offset -= mips_abi_regsize (gdbarch);
1641 /* The SAVE instruction is similar to ENTRY, except that defined by the
1642 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1643 size of the frame is specified as an immediate field of instruction
1644 and an extended variation exists which lets additional registers and
1645 frame space to be specified. The instruction always treats registers
1646 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1647 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
1649 static int args_table[16] = {
1650 0, 0, 0, 0, 1, 1, 1, 1,
1651 2, 2, 2, 0, 3, 3, 4, -1,
1653 static int astatic_table[16] = {
1654 0, 1, 2, 3, 0, 1, 2, 3,
1655 0, 1, 2, 4, 0, 1, 0, -1,
1657 int aregs = (save_inst >> 16) & 0xf;
1658 int xsregs = (save_inst >> 24) & 0x7;
1659 int args = args_table[aregs];
1660 int astatic = astatic_table[aregs];
1665 warning (_("Invalid number of argument registers encoded in SAVE."));
1670 warning (_("Invalid number of static registers encoded in SAVE."));
1674 /* For standard SAVE the frame size of 0 means 128. */
1675 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
1676 if (frame_size == 0 && (save_inst >> 16) == 0)
1679 frame_offset += frame_size;
1681 /* Now we can calculate what the SP must have been at the
1682 start of the function prologue. */
1685 /* Check if A0-A3 were saved in the caller's argument save area. */
1686 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
1688 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1689 offset += mips_abi_regsize (gdbarch);
1694 /* Check if the RA register was pushed on the stack. */
1695 if (save_inst & 0x40)
1697 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1698 offset -= mips_abi_regsize (gdbarch);
1701 /* Check if the S8 register was pushed on the stack. */
1704 set_reg_offset (gdbarch, this_cache, 30, sp + offset);
1705 offset -= mips_abi_regsize (gdbarch);
1708 /* Check if S2-S7 were pushed on the stack. */
1709 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
1711 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1712 offset -= mips_abi_regsize (gdbarch);
1715 /* Check if the S1 register was pushed on the stack. */
1716 if (save_inst & 0x10)
1718 set_reg_offset (gdbarch, this_cache, 17, sp + offset);
1719 offset -= mips_abi_regsize (gdbarch);
1721 /* Check if the S0 register was pushed on the stack. */
1722 if (save_inst & 0x20)
1724 set_reg_offset (gdbarch, this_cache, 16, sp + offset);
1725 offset -= mips_abi_regsize (gdbarch);
1728 /* Check if A0-A3 were pushed on the stack. */
1729 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
1731 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1732 offset -= mips_abi_regsize (gdbarch);
1736 if (this_cache != NULL)
1739 (get_frame_register_signed (this_frame,
1740 gdbarch_num_regs (gdbarch) + frame_reg)
1741 + frame_offset - frame_adjust);
1742 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1743 be able to get rid of the assignment below, evetually. But it's
1744 still needed for now. */
1745 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
1746 + mips_regnum (gdbarch)->pc]
1747 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
1750 /* If we didn't reach the end of the prologue when scanning the function
1751 instructions, then set end_prologue_addr to the address of the
1752 instruction immediately after the last one we scanned. */
1753 if (end_prologue_addr == 0)
1754 end_prologue_addr = cur_pc;
1756 return end_prologue_addr;
1759 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1760 Procedures that use the 32-bit instruction set are handled by the
1761 mips_insn32 unwinder. */
1763 static struct mips_frame_cache *
1764 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
1766 struct mips_frame_cache *cache;
1768 if ((*this_cache) != NULL)
1769 return (*this_cache);
1770 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1771 (*this_cache) = cache;
1772 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1774 /* Analyze the function prologue. */
1776 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
1777 CORE_ADDR start_addr;
1779 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1780 if (start_addr == 0)
1781 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc);
1782 /* We can't analyze the prologue if we couldn't find the begining
1784 if (start_addr == 0)
1787 mips16_scan_prologue (start_addr, pc, this_frame, *this_cache);
1790 /* gdbarch_sp_regnum contains the value and not the address. */
1791 trad_frame_set_value (cache->saved_regs,
1792 gdbarch_num_regs (get_frame_arch (this_frame))
1796 return (*this_cache);
1800 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
1801 struct frame_id *this_id)
1803 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1805 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
1808 static struct value *
1809 mips_insn16_frame_prev_register (struct frame_info *this_frame,
1810 void **this_cache, int regnum)
1812 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1814 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1818 mips_insn16_frame_sniffer (const struct frame_unwind *self,
1819 struct frame_info *this_frame, void **this_cache)
1821 CORE_ADDR pc = get_frame_pc (this_frame);
1822 if (mips_pc_is_mips16 (pc))
1827 static const struct frame_unwind mips_insn16_frame_unwind =
1830 mips_insn16_frame_this_id,
1831 mips_insn16_frame_prev_register,
1833 mips_insn16_frame_sniffer
1837 mips_insn16_frame_base_address (struct frame_info *this_frame,
1840 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1845 static const struct frame_base mips_insn16_frame_base =
1847 &mips_insn16_frame_unwind,
1848 mips_insn16_frame_base_address,
1849 mips_insn16_frame_base_address,
1850 mips_insn16_frame_base_address
1853 static const struct frame_base *
1854 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
1856 CORE_ADDR pc = get_frame_pc (this_frame);
1857 if (mips_pc_is_mips16 (pc))
1858 return &mips_insn16_frame_base;
1863 /* Mark all the registers as unset in the saved_regs array
1864 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1867 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
1869 if (this_cache == NULL || this_cache->saved_regs == NULL)
1873 const int num_regs = gdbarch_num_regs (gdbarch);
1876 for (i = 0; i < num_regs; i++)
1878 this_cache->saved_regs[i].addr = -1;
1883 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1884 the associated FRAME_CACHE if not null.
1885 Return the address of the first instruction past the prologue. */
1888 mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1889 struct frame_info *this_frame,
1890 struct mips_frame_cache *this_cache)
1893 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1896 int frame_reg = MIPS_SP_REGNUM;
1898 CORE_ADDR end_prologue_addr = 0;
1899 int seen_sp_adjust = 0;
1900 int load_immediate_bytes = 0;
1901 int in_delay_slot = 0;
1902 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1903 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
1905 /* Can be called when there's no process, and hence when there's no
1907 if (this_frame != NULL)
1908 sp = get_frame_register_signed (this_frame,
1909 gdbarch_num_regs (gdbarch)
1914 if (limit_pc > start_pc + 200)
1915 limit_pc = start_pc + 200;
1920 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
1922 unsigned long inst, high_word, low_word;
1925 /* Fetch the instruction. */
1926 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1928 /* Save some code by pre-extracting some useful fields. */
1929 high_word = (inst >> 16) & 0xffff;
1930 low_word = inst & 0xffff;
1931 reg = high_word & 0x1f;
1933 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1934 || high_word == 0x23bd /* addi $sp,$sp,-i */
1935 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1937 if (low_word & 0x8000) /* negative stack adjustment? */
1938 frame_offset += 0x10000 - low_word;
1940 /* Exit loop if a positive stack adjustment is found, which
1941 usually means that the stack cleanup code in the function
1942 epilogue is reached. */
1946 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1947 && !regsize_is_64_bits)
1949 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
1951 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1952 && regsize_is_64_bits)
1954 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1955 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
1957 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1959 /* Old gcc frame, r30 is virtual frame pointer. */
1960 if ((long) low_word != frame_offset)
1961 frame_addr = sp + low_word;
1962 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
1964 unsigned alloca_adjust;
1967 frame_addr = get_frame_register_signed
1968 (this_frame, gdbarch_num_regs (gdbarch) + 30);
1970 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1971 if (alloca_adjust > 0)
1973 /* FP > SP + frame_size. This may be because of
1974 an alloca or somethings similar. Fix sp to
1975 "pre-alloca" value, and try again. */
1976 sp += alloca_adjust;
1977 /* Need to reset the status of all registers. Otherwise,
1978 we will hit a guard that prevents the new address
1979 for each register to be recomputed during the second
1981 reset_saved_regs (gdbarch, this_cache);
1986 /* move $30,$sp. With different versions of gas this will be either
1987 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1988 Accept any one of these. */
1989 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1991 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1992 if (this_frame && frame_reg == MIPS_SP_REGNUM)
1994 unsigned alloca_adjust;
1997 frame_addr = get_frame_register_signed
1998 (this_frame, gdbarch_num_regs (gdbarch) + 30);
2000 alloca_adjust = (unsigned) (frame_addr - sp);
2001 if (alloca_adjust > 0)
2003 /* FP > SP + frame_size. This may be because of
2004 an alloca or somethings similar. Fix sp to
2005 "pre-alloca" value, and try again. */
2007 /* Need to reset the status of all registers. Otherwise,
2008 we will hit a guard that prevents the new address
2009 for each register to be recomputed during the second
2011 reset_saved_regs (gdbarch, this_cache);
2016 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2017 && !regsize_is_64_bits)
2019 set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word);
2021 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2022 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2023 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2024 || high_word == 0x3c1c /* lui $gp,n */
2025 || high_word == 0x279c /* addiu $gp,$gp,n */
2026 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
2027 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
2030 /* These instructions are part of the prologue, but we don't
2031 need to do anything special to handle them. */
2033 /* The instructions below load $at or $t0 with an immediate
2034 value in preparation for a stack adjustment via
2035 subu $sp,$sp,[$at,$t0]. These instructions could also
2036 initialize a local variable, so we accept them only before
2037 a stack adjustment instruction was seen. */
2038 else if (!seen_sp_adjust
2039 && (high_word == 0x3c01 /* lui $at,n */
2040 || high_word == 0x3c08 /* lui $t0,n */
2041 || high_word == 0x3421 /* ori $at,$at,n */
2042 || high_word == 0x3508 /* ori $t0,$t0,n */
2043 || high_word == 0x3401 /* ori $at,$zero,n */
2044 || high_word == 0x3408 /* ori $t0,$zero,n */
2047 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
2051 /* This instruction is not an instruction typically found
2052 in a prologue, so we must have reached the end of the
2054 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2055 loop now? Why would we need to continue scanning the function
2057 if (end_prologue_addr == 0)
2058 end_prologue_addr = cur_pc;
2060 /* Check for branches and jumps. For now, only jump to
2061 register are caught (i.e. returns). */
2062 if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8)
2066 /* If the previous instruction was a jump, we must have reached
2067 the end of the prologue by now. Stop scanning so that we do
2068 not go past the function return. */
2073 if (this_cache != NULL)
2076 (get_frame_register_signed (this_frame,
2077 gdbarch_num_regs (gdbarch) + frame_reg)
2079 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2080 this assignment below, eventually. But it's still needed
2082 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2083 + mips_regnum (gdbarch)->pc]
2084 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2088 /* If we didn't reach the end of the prologue when scanning the function
2089 instructions, then set end_prologue_addr to the address of the
2090 instruction immediately after the last one we scanned. */
2091 /* brobecker/2004-10-10: I don't think this would ever happen, but
2092 we may as well be careful and do our best if we have a null
2093 end_prologue_addr. */
2094 if (end_prologue_addr == 0)
2095 end_prologue_addr = cur_pc;
2097 /* In a frameless function, we might have incorrectly
2098 skipped some load immediate instructions. Undo the skipping
2099 if the load immediate was not followed by a stack adjustment. */
2100 if (load_immediate_bytes && !seen_sp_adjust)
2101 end_prologue_addr -= load_immediate_bytes;
2103 return end_prologue_addr;
2106 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2107 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2108 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2111 static struct mips_frame_cache *
2112 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
2114 struct mips_frame_cache *cache;
2116 if ((*this_cache) != NULL)
2117 return (*this_cache);
2119 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2120 (*this_cache) = cache;
2121 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2123 /* Analyze the function prologue. */
2125 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2126 CORE_ADDR start_addr;
2128 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2129 if (start_addr == 0)
2130 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc);
2131 /* We can't analyze the prologue if we couldn't find the begining
2133 if (start_addr == 0)
2136 mips32_scan_prologue (start_addr, pc, this_frame, *this_cache);
2139 /* gdbarch_sp_regnum contains the value and not the address. */
2140 trad_frame_set_value (cache->saved_regs,
2141 gdbarch_num_regs (get_frame_arch (this_frame))
2145 return (*this_cache);
2149 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
2150 struct frame_id *this_id)
2152 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2154 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2157 static struct value *
2158 mips_insn32_frame_prev_register (struct frame_info *this_frame,
2159 void **this_cache, int regnum)
2161 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2163 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2167 mips_insn32_frame_sniffer (const struct frame_unwind *self,
2168 struct frame_info *this_frame, void **this_cache)
2170 CORE_ADDR pc = get_frame_pc (this_frame);
2171 if (! mips_pc_is_mips16 (pc))
2176 static const struct frame_unwind mips_insn32_frame_unwind =
2179 mips_insn32_frame_this_id,
2180 mips_insn32_frame_prev_register,
2182 mips_insn32_frame_sniffer
2186 mips_insn32_frame_base_address (struct frame_info *this_frame,
2189 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2194 static const struct frame_base mips_insn32_frame_base =
2196 &mips_insn32_frame_unwind,
2197 mips_insn32_frame_base_address,
2198 mips_insn32_frame_base_address,
2199 mips_insn32_frame_base_address
2202 static const struct frame_base *
2203 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
2205 CORE_ADDR pc = get_frame_pc (this_frame);
2206 if (! mips_pc_is_mips16 (pc))
2207 return &mips_insn32_frame_base;
2212 static struct trad_frame_cache *
2213 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
2216 CORE_ADDR start_addr;
2217 CORE_ADDR stack_addr;
2218 struct trad_frame_cache *this_trad_cache;
2219 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2220 int num_regs = gdbarch_num_regs (gdbarch);
2222 if ((*this_cache) != NULL)
2223 return (*this_cache);
2224 this_trad_cache = trad_frame_cache_zalloc (this_frame);
2225 (*this_cache) = this_trad_cache;
2227 /* The return address is in the link register. */
2228 trad_frame_set_reg_realreg (this_trad_cache,
2229 gdbarch_pc_regnum (gdbarch),
2230 num_regs + MIPS_RA_REGNUM);
2232 /* Frame ID, since it's a frameless / stackless function, no stack
2233 space is allocated and SP on entry is the current SP. */
2234 pc = get_frame_pc (this_frame);
2235 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2236 stack_addr = get_frame_register_signed (this_frame,
2237 num_regs + MIPS_SP_REGNUM);
2238 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
2240 /* Assume that the frame's base is the same as the
2242 trad_frame_set_this_base (this_trad_cache, stack_addr);
2244 return this_trad_cache;
2248 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
2249 struct frame_id *this_id)
2251 struct trad_frame_cache *this_trad_cache
2252 = mips_stub_frame_cache (this_frame, this_cache);
2253 trad_frame_get_id (this_trad_cache, this_id);
2256 static struct value *
2257 mips_stub_frame_prev_register (struct frame_info *this_frame,
2258 void **this_cache, int regnum)
2260 struct trad_frame_cache *this_trad_cache
2261 = mips_stub_frame_cache (this_frame, this_cache);
2262 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
2266 mips_stub_frame_sniffer (const struct frame_unwind *self,
2267 struct frame_info *this_frame, void **this_cache)
2270 struct obj_section *s;
2271 CORE_ADDR pc = get_frame_address_in_block (this_frame);
2272 struct minimal_symbol *msym;
2274 /* Use the stub unwinder for unreadable code. */
2275 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2278 if (in_plt_section (pc, NULL))
2281 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2282 s = find_pc_section (pc);
2285 && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
2286 ".MIPS.stubs") == 0)
2289 /* Calling a PIC function from a non-PIC function passes through a
2290 stub. The stub for foo is named ".pic.foo". */
2291 msym = lookup_minimal_symbol_by_pc (pc);
2293 && SYMBOL_LINKAGE_NAME (msym) != NULL
2294 && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0)
2300 static const struct frame_unwind mips_stub_frame_unwind =
2303 mips_stub_frame_this_id,
2304 mips_stub_frame_prev_register,
2306 mips_stub_frame_sniffer
2310 mips_stub_frame_base_address (struct frame_info *this_frame,
2313 struct trad_frame_cache *this_trad_cache
2314 = mips_stub_frame_cache (this_frame, this_cache);
2315 return trad_frame_get_this_base (this_trad_cache);
2318 static const struct frame_base mips_stub_frame_base =
2320 &mips_stub_frame_unwind,
2321 mips_stub_frame_base_address,
2322 mips_stub_frame_base_address,
2323 mips_stub_frame_base_address
2326 static const struct frame_base *
2327 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
2329 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
2330 return &mips_stub_frame_base;
2335 /* mips_addr_bits_remove - remove useless address bits */
2338 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
2340 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2341 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
2342 /* This hack is a work-around for existing boards using PMON, the
2343 simulator, and any other 64-bit targets that doesn't have true
2344 64-bit addressing. On these targets, the upper 32 bits of
2345 addresses are ignored by the hardware. Thus, the PC or SP are
2346 likely to have been sign extended to all 1s by instruction
2347 sequences that load 32-bit addresses. For example, a typical
2348 piece of code that loads an address is this:
2350 lui $r2, <upper 16 bits>
2351 ori $r2, <lower 16 bits>
2353 But the lui sign-extends the value such that the upper 32 bits
2354 may be all 1s. The workaround is simply to mask off these
2355 bits. In the future, gcc may be changed to support true 64-bit
2356 addressing, and this masking will have to be disabled. */
2357 return addr &= 0xffffffffUL;
2362 /* Instructions used during single-stepping of atomic sequences. */
2363 #define LL_OPCODE 0x30
2364 #define LLD_OPCODE 0x34
2365 #define SC_OPCODE 0x38
2366 #define SCD_OPCODE 0x3c
2368 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2369 instruction and ending with a SC/SCD instruction. If such a sequence
2370 is found, attempt to step through it. A breakpoint is placed at the end of
2374 deal_with_atomic_sequence (CORE_ADDR pc)
2376 CORE_ADDR breaks[2] = {-1, -1};
2378 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
2382 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2383 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2388 insn = mips_fetch_instruction (loc);
2389 /* Assume all atomic sequences start with a ll/lld instruction. */
2390 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
2393 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2395 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2398 loc += MIPS_INSN32_SIZE;
2399 insn = mips_fetch_instruction (loc);
2401 /* Assume that there is at most one branch in the atomic
2402 sequence. If a branch is found, put a breakpoint in its
2403 destination address. */
2404 switch (itype_op (insn))
2406 case 0: /* SPECIAL */
2407 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
2408 return 0; /* fallback to the standard single-step code. */
2410 case 1: /* REGIMM */
2411 is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */
2415 return 0; /* fallback to the standard single-step code. */
2422 case 22: /* BLEZL */
2423 case 23: /* BGTTL */
2429 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2434 branch_bp = loc + mips32_relative_offset (insn) + 4;
2435 if (last_breakpoint >= 1)
2436 return 0; /* More than one branch found, fallback to the
2437 standard single-step code. */
2438 breaks[1] = branch_bp;
2442 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
2446 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2447 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
2450 loc += MIPS_INSN32_SIZE;
2452 /* Insert a breakpoint right after the end of the atomic sequence. */
2455 /* Check for duplicated breakpoints. Check also for a breakpoint
2456 placed (branch instruction's destination) in the atomic sequence */
2457 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
2458 last_breakpoint = 0;
2460 /* Effectively inserts the breakpoints. */
2461 for (index = 0; index <= last_breakpoint; index++)
2462 insert_single_step_breakpoint (breaks[index]);
2467 /* mips_software_single_step() is called just before we want to resume
2468 the inferior, if we want to single-step it but there is no hardware
2469 or kernel single-step support (MIPS on GNU/Linux for example). We find
2470 the target of the coming instruction and breakpoint it. */
2473 mips_software_single_step (struct frame_info *frame)
2475 CORE_ADDR pc, next_pc;
2477 pc = get_frame_pc (frame);
2478 if (deal_with_atomic_sequence (pc))
2481 next_pc = mips_next_pc (frame, pc);
2483 insert_single_step_breakpoint (next_pc);
2487 /* Test whether the PC points to the return instruction at the
2488 end of a function. */
2491 mips_about_to_return (CORE_ADDR pc)
2493 if (mips_pc_is_mips16 (pc))
2494 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2495 generates a "jr $ra"; other times it generates code to load
2496 the return address from the stack to an accessible register (such
2497 as $a3), then a "jr" using that register. This second case
2498 is almost impossible to distinguish from an indirect jump
2499 used for switch statements, so we don't even try. */
2500 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
2502 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
2506 /* This fencepost looks highly suspicious to me. Removing it also
2507 seems suspicious as it could affect remote debugging across serial
2511 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
2517 struct inferior *inf;
2519 pc = gdbarch_addr_bits_remove (gdbarch, pc);
2521 fence = start_pc - heuristic_fence_post;
2525 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
2526 fence = VM_MIN_ADDRESS;
2528 instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE;
2530 inf = current_inferior ();
2532 /* search back for previous return */
2533 for (start_pc -= instlen;; start_pc -= instlen)
2534 if (start_pc < fence)
2536 /* It's not clear to me why we reach this point when
2537 stop_soon, but with this test, at least we
2538 don't print out warnings for every child forked (eg, on
2539 decstation). 22apr93 rich@cygnus.com. */
2540 if (inf->stop_soon == NO_STOP_QUIETLY)
2542 static int blurb_printed = 0;
2544 warning (_("GDB can't find the start of the function at 0x%s."),
2549 /* This actually happens frequently in embedded
2550 development, when you first connect to a board
2551 and your stack pointer and pc are nowhere in
2552 particular. This message needs to give people
2553 in that situation enough information to
2554 determine that it's no big deal. */
2555 printf_filtered ("\n\
2556 GDB is unable to find the start of the function at 0x%s\n\
2557 and thus can't determine the size of that function's stack frame.\n\
2558 This means that GDB may be unable to access that stack frame, or\n\
2559 the frames below it.\n\
2560 This problem is most likely caused by an invalid program counter or\n\
2562 However, if you think GDB should simply search farther back\n\
2563 from 0x%s for code which looks like the beginning of a\n\
2564 function, you can increase the range of the search using the `set\n\
2565 heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
2572 else if (mips_pc_is_mips16 (start_pc))
2574 unsigned short inst;
2576 /* On MIPS16, any one of the following is likely to be the
2577 start of a function:
2583 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2584 inst = mips_fetch_instruction (start_pc);
2585 if ((inst & 0xff80) == 0x6480) /* save */
2587 if (start_pc - instlen >= fence)
2589 inst = mips_fetch_instruction (start_pc - instlen);
2590 if ((inst & 0xf800) == 0xf000) /* extend */
2591 start_pc -= instlen;
2595 else if (((inst & 0xf81f) == 0xe809
2596 && (inst & 0x700) != 0x700) /* entry */
2597 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
2598 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
2599 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
2601 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
2602 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2607 else if (mips_about_to_return (start_pc))
2609 /* Skip return and its delay slot. */
2610 start_pc += 2 * MIPS_INSN32_SIZE;
2617 struct mips_objfile_private
2623 /* According to the current ABI, should the type be passed in a
2624 floating-point register (assuming that there is space)? When there
2625 is no FPU, FP are not even considered as possible candidates for
2626 FP registers and, consequently this returns false - forces FP
2627 arguments into integer registers. */
2630 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
2631 struct type *arg_type)
2633 return ((typecode == TYPE_CODE_FLT
2634 || (MIPS_EABI (gdbarch)
2635 && (typecode == TYPE_CODE_STRUCT
2636 || typecode == TYPE_CODE_UNION)
2637 && TYPE_NFIELDS (arg_type) == 1
2638 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
2640 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
2643 /* On o32, argument passing in GPRs depends on the alignment of the type being
2644 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2647 mips_type_needs_double_align (struct type *type)
2649 enum type_code typecode = TYPE_CODE (type);
2651 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2653 else if (typecode == TYPE_CODE_STRUCT)
2655 if (TYPE_NFIELDS (type) < 1)
2657 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2659 else if (typecode == TYPE_CODE_UNION)
2663 n = TYPE_NFIELDS (type);
2664 for (i = 0; i < n; i++)
2665 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2672 /* Adjust the address downward (direction of stack growth) so that it
2673 is correctly aligned for a new stack frame. */
2675 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2677 return align_down (addr, 16);
2681 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2682 struct regcache *regcache, CORE_ADDR bp_addr,
2683 int nargs, struct value **args, CORE_ADDR sp,
2684 int struct_return, CORE_ADDR struct_addr)
2690 int stack_offset = 0;
2691 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2692 CORE_ADDR func_addr = find_function_addr (function, NULL);
2693 int regsize = mips_abi_regsize (gdbarch);
2695 /* For shared libraries, "t9" needs to point at the function
2697 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2699 /* Set the return address register to point to the entry point of
2700 the program, where a breakpoint lies in wait. */
2701 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2703 /* First ensure that the stack and structure return address (if any)
2704 are properly aligned. The stack has to be at least 64-bit
2705 aligned even on 32-bit machines, because doubles must be 64-bit
2706 aligned. For n32 and n64, stack frames need to be 128-bit
2707 aligned, so we round to this widest known alignment. */
2709 sp = align_down (sp, 16);
2710 struct_addr = align_down (struct_addr, 16);
2712 /* Now make space on the stack for the args. We allocate more
2713 than necessary for EABI, because the first few arguments are
2714 passed in registers, but that's OK. */
2715 for (argnum = 0; argnum < nargs; argnum++)
2716 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
2717 sp -= align_up (len, 16);
2720 fprintf_unfiltered (gdb_stdlog,
2721 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2722 paddr_nz (sp), (long) align_up (len, 16));
2724 /* Initialize the integer and float register pointers. */
2725 argreg = MIPS_A0_REGNUM;
2726 float_argreg = mips_fpa0_regnum (gdbarch);
2728 /* The struct_return pointer occupies the first parameter-passing reg. */
2732 fprintf_unfiltered (gdb_stdlog,
2733 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2734 argreg, paddr_nz (struct_addr));
2735 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
2738 /* Now load as many as possible of the first arguments into
2739 registers, and push the rest onto the stack. Loop thru args
2740 from first to last. */
2741 for (argnum = 0; argnum < nargs; argnum++)
2743 const gdb_byte *val;
2744 gdb_byte valbuf[MAX_REGISTER_SIZE];
2745 struct value *arg = args[argnum];
2746 struct type *arg_type = check_typedef (value_type (arg));
2747 int len = TYPE_LENGTH (arg_type);
2748 enum type_code typecode = TYPE_CODE (arg_type);
2751 fprintf_unfiltered (gdb_stdlog,
2752 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2753 argnum + 1, len, (int) typecode);
2755 /* The EABI passes structures that do not fit in a register by
2758 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2760 store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg));
2761 typecode = TYPE_CODE_PTR;
2765 fprintf_unfiltered (gdb_stdlog, " push");
2768 val = value_contents (arg);
2770 /* 32-bit ABIs always start floating point arguments in an
2771 even-numbered floating point register. Round the FP register
2772 up before the check to see if there are any FP registers
2773 left. Non MIPS_EABI targets also pass the FP in the integer
2774 registers so also round up normal registers. */
2775 if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
2777 if ((float_argreg & 1))
2781 /* Floating point arguments passed in registers have to be
2782 treated specially. On 32-bit architectures, doubles
2783 are passed in register pairs; the even register gets
2784 the low word, and the odd register gets the high word.
2785 On non-EABI processors, the first two floating point arguments are
2786 also copied to general registers, because MIPS16 functions
2787 don't use float registers for arguments. This duplication of
2788 arguments in general registers can't hurt non-MIPS16 functions
2789 because those registers are normally skipped. */
2790 /* MIPS_EABI squeezes a struct that contains a single floating
2791 point value into an FP register instead of pushing it onto the
2793 if (fp_register_arg_p (gdbarch, typecode, arg_type)
2794 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
2796 /* EABI32 will pass doubles in consecutive registers, even on
2797 64-bit cores. At one time, we used to check the size of
2798 `float_argreg' to determine whether or not to pass doubles
2799 in consecutive registers, but this is not sufficient for
2800 making the ABI determination. */
2801 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
2803 int low_offset = gdbarch_byte_order (gdbarch)
2804 == BFD_ENDIAN_BIG ? 4 : 0;
2805 unsigned long regval;
2807 /* Write the low word of the double to the even register(s). */
2808 regval = extract_unsigned_integer (val + low_offset, 4);
2810 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2811 float_argreg, phex (regval, 4));
2812 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2814 /* Write the high word of the double to the odd register(s). */
2815 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2817 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2818 float_argreg, phex (regval, 4));
2819 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2823 /* This is a floating point value that fits entirely
2824 in a single register. */
2825 /* On 32 bit ABI's the float_argreg is further adjusted
2826 above to ensure that it is even register aligned. */
2827 LONGEST regval = extract_unsigned_integer (val, len);
2829 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2830 float_argreg, phex (regval, len));
2831 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2836 /* Copy the argument to general registers or the stack in
2837 register-sized pieces. Large arguments are split between
2838 registers and stack. */
2839 /* Note: structs whose size is not a multiple of regsize
2840 are treated specially: Irix cc passes
2841 them in registers where gcc sometimes puts them on the
2842 stack. For maximum compatibility, we will put them in
2844 int odd_sized_struct = (len > regsize && len % regsize != 0);
2846 /* Note: Floating-point values that didn't fit into an FP
2847 register are only written to memory. */
2850 /* Remember if the argument was written to the stack. */
2851 int stack_used_p = 0;
2852 int partial_len = (len < regsize ? len : regsize);
2855 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2858 /* Write this portion of the argument to the stack. */
2859 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
2861 || fp_register_arg_p (gdbarch, typecode, arg_type))
2863 /* Should shorter than int integer values be
2864 promoted to int before being stored? */
2865 int longword_offset = 0;
2868 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2871 && (typecode == TYPE_CODE_INT
2872 || typecode == TYPE_CODE_PTR
2873 || typecode == TYPE_CODE_FLT) && len <= 4)
2874 longword_offset = regsize - len;
2875 else if ((typecode == TYPE_CODE_STRUCT
2876 || typecode == TYPE_CODE_UNION)
2877 && TYPE_LENGTH (arg_type) < regsize)
2878 longword_offset = regsize - len;
2883 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2884 paddr_nz (stack_offset));
2885 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2886 paddr_nz (longword_offset));
2889 addr = sp + stack_offset + longword_offset;
2894 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2896 for (i = 0; i < partial_len; i++)
2898 fprintf_unfiltered (gdb_stdlog, "%02x",
2902 write_memory (addr, val, partial_len);
2905 /* Note!!! This is NOT an else clause. Odd sized
2906 structs may go thru BOTH paths. Floating point
2907 arguments will not. */
2908 /* Write this portion of the argument to a general
2909 purpose register. */
2910 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
2911 && !fp_register_arg_p (gdbarch, typecode, arg_type))
2914 extract_unsigned_integer (val, partial_len);
2917 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2919 phex (regval, regsize));
2920 regcache_cooked_write_unsigned (regcache, argreg, regval);
2927 /* Compute the the offset into the stack at which we
2928 will copy the next parameter.
2930 In the new EABI (and the NABI32), the stack_offset
2931 only needs to be adjusted when it has been used. */
2934 stack_offset += align_up (partial_len, regsize);
2938 fprintf_unfiltered (gdb_stdlog, "\n");
2941 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2943 /* Return adjusted stack pointer. */
2947 /* Determine the return value convention being used. */
2949 static enum return_value_convention
2950 mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type,
2951 struct type *type, struct regcache *regcache,
2952 gdb_byte *readbuf, const gdb_byte *writebuf)
2954 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2955 int fp_return_type = 0;
2956 int offset, regnum, xfer;
2958 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2959 return RETURN_VALUE_STRUCT_CONVENTION;
2961 /* Floating point type? */
2962 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
2964 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2966 /* Structs with a single field of float type
2967 are returned in a floating point register. */
2968 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
2969 || TYPE_CODE (type) == TYPE_CODE_UNION)
2970 && TYPE_NFIELDS (type) == 1)
2972 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
2974 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
2981 /* A floating-point value belongs in the least significant part
2984 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
2985 regnum = mips_regnum (gdbarch)->fp0;
2989 /* An integer value goes in V0/V1. */
2991 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
2992 regnum = MIPS_V0_REGNUM;
2995 offset < TYPE_LENGTH (type);
2996 offset += mips_abi_regsize (gdbarch), regnum++)
2998 xfer = mips_abi_regsize (gdbarch);
2999 if (offset + xfer > TYPE_LENGTH (type))
3000 xfer = TYPE_LENGTH (type) - offset;
3001 mips_xfer_register (gdbarch, regcache,
3002 gdbarch_num_regs (gdbarch) + regnum, xfer,
3003 gdbarch_byte_order (gdbarch), readbuf, writebuf,
3007 return RETURN_VALUE_REGISTER_CONVENTION;
3011 /* N32/N64 ABI stuff. */
3013 /* Search for a naturally aligned double at OFFSET inside a struct
3014 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3018 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
3023 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
3026 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
3029 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
3032 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
3035 struct type *field_type;
3037 /* We're only looking at normal fields. */
3038 if (field_is_static (&TYPE_FIELD (arg_type, i))
3039 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
3042 /* If we have gone past the offset, there is no double to pass. */
3043 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
3047 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
3049 /* If this field is entirely before the requested offset, go
3050 on to the next one. */
3051 if (pos + TYPE_LENGTH (field_type) <= offset)
3054 /* If this is our special aligned double, we can stop. */
3055 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
3056 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
3059 /* This field starts at or before the requested offset, and
3060 overlaps it. If it is a structure, recurse inwards. */
3061 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
3068 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3069 struct regcache *regcache, CORE_ADDR bp_addr,
3070 int nargs, struct value **args, CORE_ADDR sp,
3071 int struct_return, CORE_ADDR struct_addr)
3077 int stack_offset = 0;
3078 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3079 CORE_ADDR func_addr = find_function_addr (function, NULL);
3081 /* For shared libraries, "t9" needs to point at the function
3083 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3085 /* Set the return address register to point to the entry point of
3086 the program, where a breakpoint lies in wait. */
3087 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3089 /* First ensure that the stack and structure return address (if any)
3090 are properly aligned. The stack has to be at least 64-bit
3091 aligned even on 32-bit machines, because doubles must be 64-bit
3092 aligned. For n32 and n64, stack frames need to be 128-bit
3093 aligned, so we round to this widest known alignment. */
3095 sp = align_down (sp, 16);
3096 struct_addr = align_down (struct_addr, 16);
3098 /* Now make space on the stack for the args. */
3099 for (argnum = 0; argnum < nargs; argnum++)
3100 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
3101 sp -= align_up (len, 16);
3104 fprintf_unfiltered (gdb_stdlog,
3105 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3106 paddr_nz (sp), (long) align_up (len, 16));
3108 /* Initialize the integer and float register pointers. */
3109 argreg = MIPS_A0_REGNUM;
3110 float_argreg = mips_fpa0_regnum (gdbarch);
3112 /* The struct_return pointer occupies the first parameter-passing reg. */
3116 fprintf_unfiltered (gdb_stdlog,
3117 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3118 argreg, paddr_nz (struct_addr));
3119 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3122 /* Now load as many as possible of the first arguments into
3123 registers, and push the rest onto the stack. Loop thru args
3124 from first to last. */
3125 for (argnum = 0; argnum < nargs; argnum++)
3127 const gdb_byte *val;
3128 struct value *arg = args[argnum];
3129 struct type *arg_type = check_typedef (value_type (arg));
3130 int len = TYPE_LENGTH (arg_type);
3131 enum type_code typecode = TYPE_CODE (arg_type);
3134 fprintf_unfiltered (gdb_stdlog,
3135 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3136 argnum + 1, len, (int) typecode);
3138 val = value_contents (arg);
3140 /* A 128-bit long double value requires an even-odd pair of
3141 floating-point registers. */
3143 && fp_register_arg_p (gdbarch, typecode, arg_type)
3144 && (float_argreg & 1))
3150 if (fp_register_arg_p (gdbarch, typecode, arg_type)
3151 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3153 /* This is a floating point value that fits entirely
3154 in a single register or a pair of registers. */
3155 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3156 LONGEST regval = extract_unsigned_integer (val, reglen);
3158 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3159 float_argreg, phex (regval, reglen));
3160 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3163 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3164 argreg, phex (regval, reglen));
3165 regcache_cooked_write_unsigned (regcache, argreg, regval);
3170 regval = extract_unsigned_integer (val + reglen, reglen);
3172 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3173 float_argreg, phex (regval, reglen));
3174 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3177 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3178 argreg, phex (regval, reglen));
3179 regcache_cooked_write_unsigned (regcache, argreg, regval);
3186 /* Copy the argument to general registers or the stack in
3187 register-sized pieces. Large arguments are split between
3188 registers and stack. */
3189 /* For N32/N64, structs, unions, or other composite types are
3190 treated as a sequence of doublewords, and are passed in integer
3191 or floating point registers as though they were simple scalar
3192 parameters to the extent that they fit, with any excess on the
3193 stack packed according to the normal memory layout of the
3195 The caller does not reserve space for the register arguments;
3196 the callee is responsible for reserving it if required. */
3197 /* Note: Floating-point values that didn't fit into an FP
3198 register are only written to memory. */
3201 /* Remember if the argument was written to the stack. */
3202 int stack_used_p = 0;
3203 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3206 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3209 if (fp_register_arg_p (gdbarch, typecode, arg_type))
3210 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
3212 /* Write this portion of the argument to the stack. */
3213 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
3215 /* Should shorter than int integer values be
3216 promoted to int before being stored? */
3217 int longword_offset = 0;
3220 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
3222 if ((typecode == TYPE_CODE_INT
3223 || typecode == TYPE_CODE_PTR)
3225 longword_offset = MIPS64_REGSIZE - len;
3230 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3231 paddr_nz (stack_offset));
3232 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3233 paddr_nz (longword_offset));
3236 addr = sp + stack_offset + longword_offset;
3241 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3243 for (i = 0; i < partial_len; i++)
3245 fprintf_unfiltered (gdb_stdlog, "%02x",
3249 write_memory (addr, val, partial_len);
3252 /* Note!!! This is NOT an else clause. Odd sized
3253 structs may go thru BOTH paths. */
3254 /* Write this portion of the argument to a general
3255 purpose register. */
3256 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3260 /* Sign extend pointers, 32-bit integers and signed
3261 16-bit and 8-bit integers; everything else is taken
3264 if ((partial_len == 4
3265 && (typecode == TYPE_CODE_PTR
3266 || typecode == TYPE_CODE_INT))
3268 && typecode == TYPE_CODE_INT
3269 && !TYPE_UNSIGNED (arg_type)))
3270 regval = extract_signed_integer (val, partial_len);
3272 regval = extract_unsigned_integer (val, partial_len);
3274 /* A non-floating-point argument being passed in a
3275 general register. If a struct or union, and if
3276 the remaining length is smaller than the register
3277 size, we have to adjust the register value on
3280 It does not seem to be necessary to do the
3281 same for integral types. */
3283 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3284 && partial_len < MIPS64_REGSIZE
3285 && (typecode == TYPE_CODE_STRUCT
3286 || typecode == TYPE_CODE_UNION))
3287 regval <<= ((MIPS64_REGSIZE - partial_len)
3291 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3293 phex (regval, MIPS64_REGSIZE));
3294 regcache_cooked_write_unsigned (regcache, argreg, regval);
3296 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
3297 TYPE_LENGTH (arg_type) - len))
3300 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
3302 phex (regval, MIPS64_REGSIZE));
3303 regcache_cooked_write_unsigned (regcache, float_argreg,
3314 /* Compute the the offset into the stack at which we
3315 will copy the next parameter.
3317 In N32 (N64?), the stack_offset only needs to be
3318 adjusted when it has been used. */
3321 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
3325 fprintf_unfiltered (gdb_stdlog, "\n");
3328 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3330 /* Return adjusted stack pointer. */
3334 static enum return_value_convention
3335 mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type,
3336 struct type *type, struct regcache *regcache,
3337 gdb_byte *readbuf, const gdb_byte *writebuf)
3339 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3341 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3343 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3344 if needed), as appropriate for the type. Composite results (struct,
3345 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3348 * A struct with only one or two floating point fields is returned in $f0
3349 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3352 * Any other struct or union results of at most 128 bits are returned in
3353 $2 (first 64 bits) and $3 (remainder, if necessary).
3355 * Larger composite results are handled by converting the function to a
3356 procedure with an implicit first parameter, which is a pointer to an area
3357 reserved by the caller to receive the result. [The o32-bit ABI requires
3358 that all composite results be handled by conversion to implicit first
3359 parameters. The MIPS/SGI Fortran implementation has always made a
3360 specific exception to return COMPLEX results in the floating point
3363 if (TYPE_CODE (type) == TYPE_CODE_ARRAY
3364 || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
3365 return RETURN_VALUE_STRUCT_CONVENTION;
3366 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3367 && TYPE_LENGTH (type) == 16
3368 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3370 /* A 128-bit floating-point value fills both $f0 and $f2. The
3371 two registers are used in the same as memory order, so the
3372 eight bytes with the lower memory address are in $f0. */
3374 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
3375 mips_xfer_register (gdbarch, regcache,
3376 gdbarch_num_regs (gdbarch)
3377 + mips_regnum (gdbarch)->fp0,
3378 8, gdbarch_byte_order (gdbarch),
3379 readbuf, writebuf, 0);
3380 mips_xfer_register (gdbarch, regcache,
3381 gdbarch_num_regs (gdbarch)
3382 + mips_regnum (gdbarch)->fp0 + 2,
3383 8, gdbarch_byte_order (gdbarch),
3384 readbuf ? readbuf + 8 : readbuf,
3385 writebuf ? writebuf + 8 : writebuf, 0);
3386 return RETURN_VALUE_REGISTER_CONVENTION;
3388 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3389 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3391 /* A single or double floating-point value that fits in FP0. */
3393 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3394 mips_xfer_register (gdbarch, regcache,
3395 gdbarch_num_regs (gdbarch)
3396 + mips_regnum (gdbarch)->fp0,
3398 gdbarch_byte_order (gdbarch),
3399 readbuf, writebuf, 0);
3400 return RETURN_VALUE_REGISTER_CONVENTION;
3402 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3403 && TYPE_NFIELDS (type) <= 2
3404 && TYPE_NFIELDS (type) >= 1
3405 && ((TYPE_NFIELDS (type) == 1
3406 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3408 || (TYPE_NFIELDS (type) == 2
3409 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3411 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
3412 == TYPE_CODE_FLT))))
3414 /* A struct that contains one or two floats. Each value is part
3415 in the least significant part of their floating point
3416 register (or GPR, for soft float). */
3419 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
3420 ? mips_regnum (gdbarch)->fp0
3422 field < TYPE_NFIELDS (type); field++, regnum += 2)
3424 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3427 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3429 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
3431 /* A 16-byte long double field goes in two consecutive
3433 mips_xfer_register (gdbarch, regcache,
3434 gdbarch_num_regs (gdbarch) + regnum,
3436 gdbarch_byte_order (gdbarch),
3437 readbuf, writebuf, offset);
3438 mips_xfer_register (gdbarch, regcache,
3439 gdbarch_num_regs (gdbarch) + regnum + 1,
3441 gdbarch_byte_order (gdbarch),
3442 readbuf, writebuf, offset + 8);
3445 mips_xfer_register (gdbarch, regcache,
3446 gdbarch_num_regs (gdbarch) + regnum,
3447 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3448 gdbarch_byte_order (gdbarch),
3449 readbuf, writebuf, offset);
3451 return RETURN_VALUE_REGISTER_CONVENTION;
3453 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3454 || TYPE_CODE (type) == TYPE_CODE_UNION)
3456 /* A structure or union. Extract the left justified value,
3457 regardless of the byte order. I.e. DO NOT USE
3461 for (offset = 0, regnum = MIPS_V0_REGNUM;
3462 offset < TYPE_LENGTH (type);
3463 offset += register_size (gdbarch, regnum), regnum++)
3465 int xfer = register_size (gdbarch, regnum);
3466 if (offset + xfer > TYPE_LENGTH (type))
3467 xfer = TYPE_LENGTH (type) - offset;
3469 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3470 offset, xfer, regnum);
3471 mips_xfer_register (gdbarch, regcache,
3472 gdbarch_num_regs (gdbarch) + regnum,
3473 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
3476 return RETURN_VALUE_REGISTER_CONVENTION;
3480 /* A scalar extract each part but least-significant-byte
3484 for (offset = 0, regnum = MIPS_V0_REGNUM;
3485 offset < TYPE_LENGTH (type);
3486 offset += register_size (gdbarch, regnum), regnum++)
3488 int xfer = register_size (gdbarch, regnum);
3489 if (offset + xfer > TYPE_LENGTH (type))
3490 xfer = TYPE_LENGTH (type) - offset;
3492 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3493 offset, xfer, regnum);
3494 mips_xfer_register (gdbarch, regcache,
3495 gdbarch_num_regs (gdbarch) + regnum,
3496 xfer, gdbarch_byte_order (gdbarch),
3497 readbuf, writebuf, offset);
3499 return RETURN_VALUE_REGISTER_CONVENTION;
3503 /* O32 ABI stuff. */
3506 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3507 struct regcache *regcache, CORE_ADDR bp_addr,
3508 int nargs, struct value **args, CORE_ADDR sp,
3509 int struct_return, CORE_ADDR struct_addr)
3515 int stack_offset = 0;
3516 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3517 CORE_ADDR func_addr = find_function_addr (function, NULL);
3519 /* For shared libraries, "t9" needs to point at the function
3521 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3523 /* Set the return address register to point to the entry point of
3524 the program, where a breakpoint lies in wait. */
3525 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3527 /* First ensure that the stack and structure return address (if any)
3528 are properly aligned. The stack has to be at least 64-bit
3529 aligned even on 32-bit machines, because doubles must be 64-bit
3530 aligned. For n32 and n64, stack frames need to be 128-bit
3531 aligned, so we round to this widest known alignment. */
3533 sp = align_down (sp, 16);
3534 struct_addr = align_down (struct_addr, 16);
3536 /* Now make space on the stack for the args. */
3537 for (argnum = 0; argnum < nargs; argnum++)
3539 struct type *arg_type = check_typedef (value_type (args[argnum]));
3540 int arglen = TYPE_LENGTH (arg_type);
3542 /* Align to double-word if necessary. */
3543 if (mips_type_needs_double_align (arg_type))
3544 len = align_up (len, MIPS32_REGSIZE * 2);
3545 /* Allocate space on the stack. */
3546 len += align_up (arglen, MIPS32_REGSIZE);
3548 sp -= align_up (len, 16);
3551 fprintf_unfiltered (gdb_stdlog,
3552 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3553 paddr_nz (sp), (long) align_up (len, 16));
3555 /* Initialize the integer and float register pointers. */
3556 argreg = MIPS_A0_REGNUM;
3557 float_argreg = mips_fpa0_regnum (gdbarch);
3559 /* The struct_return pointer occupies the first parameter-passing reg. */
3563 fprintf_unfiltered (gdb_stdlog,
3564 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3565 argreg, paddr_nz (struct_addr));
3566 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3567 stack_offset += MIPS32_REGSIZE;
3570 /* Now load as many as possible of the first arguments into
3571 registers, and push the rest onto the stack. Loop thru args
3572 from first to last. */
3573 for (argnum = 0; argnum < nargs; argnum++)
3575 const gdb_byte *val;
3576 struct value *arg = args[argnum];
3577 struct type *arg_type = check_typedef (value_type (arg));
3578 int len = TYPE_LENGTH (arg_type);
3579 enum type_code typecode = TYPE_CODE (arg_type);
3582 fprintf_unfiltered (gdb_stdlog,
3583 "mips_o32_push_dummy_call: %d len=%d type=%d",
3584 argnum + 1, len, (int) typecode);
3586 val = value_contents (arg);
3588 /* 32-bit ABIs always start floating point arguments in an
3589 even-numbered floating point register. Round the FP register
3590 up before the check to see if there are any FP registers
3591 left. O32/O64 targets also pass the FP in the integer
3592 registers so also round up normal registers. */
3593 if (fp_register_arg_p (gdbarch, typecode, arg_type))
3595 if ((float_argreg & 1))
3599 /* Floating point arguments passed in registers have to be
3600 treated specially. On 32-bit architectures, doubles
3601 are passed in register pairs; the even register gets
3602 the low word, and the odd register gets the high word.
3603 On O32/O64, the first two floating point arguments are
3604 also copied to general registers, because MIPS16 functions
3605 don't use float registers for arguments. This duplication of
3606 arguments in general registers can't hurt non-MIPS16 functions
3607 because those registers are normally skipped. */
3609 if (fp_register_arg_p (gdbarch, typecode, arg_type)
3610 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
3612 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
3614 int low_offset = gdbarch_byte_order (gdbarch)
3615 == BFD_ENDIAN_BIG ? 4 : 0;
3616 unsigned long regval;
3618 /* Write the low word of the double to the even register(s). */
3619 regval = extract_unsigned_integer (val + low_offset, 4);
3621 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3622 float_argreg, phex (regval, 4));
3623 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3625 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3626 argreg, phex (regval, 4));
3627 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3629 /* Write the high word of the double to the odd register(s). */
3630 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3632 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3633 float_argreg, phex (regval, 4));
3634 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3637 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3638 argreg, phex (regval, 4));
3639 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3643 /* This is a floating point value that fits entirely
3644 in a single register. */
3645 /* On 32 bit ABI's the float_argreg is further adjusted
3646 above to ensure that it is even register aligned. */
3647 LONGEST regval = extract_unsigned_integer (val, len);
3649 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3650 float_argreg, phex (regval, len));
3651 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3652 /* Although two FP registers are reserved for each
3653 argument, only one corresponding integer register is
3656 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3657 argreg, phex (regval, len));
3658 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3660 /* Reserve space for the FP register. */
3661 stack_offset += align_up (len, MIPS32_REGSIZE);
3665 /* Copy the argument to general registers or the stack in
3666 register-sized pieces. Large arguments are split between
3667 registers and stack. */
3668 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3669 are treated specially: Irix cc passes
3670 them in registers where gcc sometimes puts them on the
3671 stack. For maximum compatibility, we will put them in
3673 int odd_sized_struct = (len > MIPS32_REGSIZE
3674 && len % MIPS32_REGSIZE != 0);
3675 /* Structures should be aligned to eight bytes (even arg registers)
3676 on MIPS_ABI_O32, if their first member has double precision. */
3677 if (mips_type_needs_double_align (arg_type))
3682 stack_offset += MIPS32_REGSIZE;
3687 /* Remember if the argument was written to the stack. */
3688 int stack_used_p = 0;
3689 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
3692 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3695 /* Write this portion of the argument to the stack. */
3696 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
3697 || odd_sized_struct)
3699 /* Should shorter than int integer values be
3700 promoted to int before being stored? */
3701 int longword_offset = 0;
3707 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3708 paddr_nz (stack_offset));
3709 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3710 paddr_nz (longword_offset));
3713 addr = sp + stack_offset + longword_offset;
3718 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3720 for (i = 0; i < partial_len; i++)
3722 fprintf_unfiltered (gdb_stdlog, "%02x",
3726 write_memory (addr, val, partial_len);
3729 /* Note!!! This is NOT an else clause. Odd sized
3730 structs may go thru BOTH paths. */
3731 /* Write this portion of the argument to a general
3732 purpose register. */
3733 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3735 LONGEST regval = extract_signed_integer (val, partial_len);
3736 /* Value may need to be sign extended, because
3737 mips_isa_regsize() != mips_abi_regsize(). */
3739 /* A non-floating-point argument being passed in a
3740 general register. If a struct or union, and if
3741 the remaining length is smaller than the register
3742 size, we have to adjust the register value on
3745 It does not seem to be necessary to do the
3746 same for integral types.
3748 Also don't do this adjustment on O64 binaries.
3750 cagney/2001-07-23: gdb/179: Also, GCC, when
3751 outputting LE O32 with sizeof (struct) <
3752 mips_abi_regsize(), generates a left shift
3753 as part of storing the argument in a register
3754 (the left shift isn't generated when
3755 sizeof (struct) >= mips_abi_regsize()). Since
3756 it is quite possible that this is GCC
3757 contradicting the LE/O32 ABI, GDB has not been
3758 adjusted to accommodate this. Either someone
3759 needs to demonstrate that the LE/O32 ABI
3760 specifies such a left shift OR this new ABI gets
3761 identified as such and GDB gets tweaked
3764 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3765 && partial_len < MIPS32_REGSIZE
3766 && (typecode == TYPE_CODE_STRUCT
3767 || typecode == TYPE_CODE_UNION))
3768 regval <<= ((MIPS32_REGSIZE - partial_len)
3772 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3774 phex (regval, MIPS32_REGSIZE));
3775 regcache_cooked_write_unsigned (regcache, argreg, regval);
3778 /* Prevent subsequent floating point arguments from
3779 being passed in floating point registers. */
3780 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
3786 /* Compute the the offset into the stack at which we
3787 will copy the next parameter.
3789 In older ABIs, the caller reserved space for
3790 registers that contained arguments. This was loosely
3791 refered to as their "home". Consequently, space is
3792 always allocated. */
3794 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
3798 fprintf_unfiltered (gdb_stdlog, "\n");
3801 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3803 /* Return adjusted stack pointer. */
3807 static enum return_value_convention
3808 mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type,
3809 struct type *type, struct regcache *regcache,
3810 gdb_byte *readbuf, const gdb_byte *writebuf)
3812 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3814 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3815 || TYPE_CODE (type) == TYPE_CODE_UNION
3816 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3817 return RETURN_VALUE_STRUCT_CONVENTION;
3818 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3819 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3821 /* A single-precision floating-point value. It fits in the
3822 least significant part of FP0. */
3824 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3825 mips_xfer_register (gdbarch, regcache,
3826 gdbarch_num_regs (gdbarch)
3827 + mips_regnum (gdbarch)->fp0,
3829 gdbarch_byte_order (gdbarch),
3830 readbuf, writebuf, 0);
3831 return RETURN_VALUE_REGISTER_CONVENTION;
3833 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3834 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3836 /* A double-precision floating-point value. The most
3837 significant part goes in FP1, and the least significant in
3840 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3841 switch (gdbarch_byte_order (gdbarch))
3843 case BFD_ENDIAN_LITTLE:
3844 mips_xfer_register (gdbarch, regcache,
3845 gdbarch_num_regs (gdbarch)
3846 + mips_regnum (gdbarch)->fp0 +
3847 0, 4, gdbarch_byte_order (gdbarch),
3848 readbuf, writebuf, 0);
3849 mips_xfer_register (gdbarch, regcache,
3850 gdbarch_num_regs (gdbarch)
3851 + mips_regnum (gdbarch)->fp0 + 1,
3852 4, gdbarch_byte_order (gdbarch),
3853 readbuf, writebuf, 4);
3855 case BFD_ENDIAN_BIG:
3856 mips_xfer_register (gdbarch, regcache,
3857 gdbarch_num_regs (gdbarch)
3858 + mips_regnum (gdbarch)->fp0 + 1,
3859 4, gdbarch_byte_order (gdbarch),
3860 readbuf, writebuf, 0);
3861 mips_xfer_register (gdbarch, regcache,
3862 gdbarch_num_regs (gdbarch)
3863 + mips_regnum (gdbarch)->fp0 + 0,
3864 4, gdbarch_byte_order (gdbarch),
3865 readbuf, writebuf, 4);
3868 internal_error (__FILE__, __LINE__, _("bad switch"));
3870 return RETURN_VALUE_REGISTER_CONVENTION;
3873 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3874 && TYPE_NFIELDS (type) <= 2
3875 && TYPE_NFIELDS (type) >= 1
3876 && ((TYPE_NFIELDS (type) == 1
3877 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3879 || (TYPE_NFIELDS (type) == 2
3880 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3882 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3884 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3886 /* A struct that contains one or two floats. Each value is part
3887 in the least significant part of their floating point
3889 gdb_byte reg[MAX_REGISTER_SIZE];
3892 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
3893 field < TYPE_NFIELDS (type); field++, regnum += 2)
3895 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3898 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3900 mips_xfer_register (gdbarch, regcache,
3901 gdbarch_num_regs (gdbarch) + regnum,
3902 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3903 gdbarch_byte_order (gdbarch),
3904 readbuf, writebuf, offset);
3906 return RETURN_VALUE_REGISTER_CONVENTION;
3910 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3911 || TYPE_CODE (type) == TYPE_CODE_UNION)
3913 /* A structure or union. Extract the left justified value,
3914 regardless of the byte order. I.e. DO NOT USE
3918 for (offset = 0, regnum = MIPS_V0_REGNUM;
3919 offset < TYPE_LENGTH (type);
3920 offset += register_size (gdbarch, regnum), regnum++)
3922 int xfer = register_size (gdbarch, regnum);
3923 if (offset + xfer > TYPE_LENGTH (type))
3924 xfer = TYPE_LENGTH (type) - offset;
3926 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3927 offset, xfer, regnum);
3928 mips_xfer_register (gdbarch, regcache,
3929 gdbarch_num_regs (gdbarch) + regnum, xfer,
3930 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3932 return RETURN_VALUE_REGISTER_CONVENTION;
3937 /* A scalar extract each part but least-significant-byte
3938 justified. o32 thinks registers are 4 byte, regardless of
3942 for (offset = 0, regnum = MIPS_V0_REGNUM;
3943 offset < TYPE_LENGTH (type);
3944 offset += MIPS32_REGSIZE, regnum++)
3946 int xfer = MIPS32_REGSIZE;
3947 if (offset + xfer > TYPE_LENGTH (type))
3948 xfer = TYPE_LENGTH (type) - offset;
3950 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3951 offset, xfer, regnum);
3952 mips_xfer_register (gdbarch, regcache,
3953 gdbarch_num_regs (gdbarch) + regnum, xfer,
3954 gdbarch_byte_order (gdbarch),
3955 readbuf, writebuf, offset);
3957 return RETURN_VALUE_REGISTER_CONVENTION;
3961 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3965 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3966 struct regcache *regcache, CORE_ADDR bp_addr,
3968 struct value **args, CORE_ADDR sp,
3969 int struct_return, CORE_ADDR struct_addr)
3975 int stack_offset = 0;
3976 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3977 CORE_ADDR func_addr = find_function_addr (function, NULL);
3979 /* For shared libraries, "t9" needs to point at the function
3981 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3983 /* Set the return address register to point to the entry point of
3984 the program, where a breakpoint lies in wait. */
3985 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3987 /* First ensure that the stack and structure return address (if any)
3988 are properly aligned. The stack has to be at least 64-bit
3989 aligned even on 32-bit machines, because doubles must be 64-bit
3990 aligned. For n32 and n64, stack frames need to be 128-bit
3991 aligned, so we round to this widest known alignment. */
3993 sp = align_down (sp, 16);
3994 struct_addr = align_down (struct_addr, 16);
3996 /* Now make space on the stack for the args. */
3997 for (argnum = 0; argnum < nargs; argnum++)
3999 struct type *arg_type = check_typedef (value_type (args[argnum]));
4000 int arglen = TYPE_LENGTH (arg_type);
4002 /* Allocate space on the stack. */
4003 len += align_up (arglen, MIPS64_REGSIZE);
4005 sp -= align_up (len, 16);
4008 fprintf_unfiltered (gdb_stdlog,
4009 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4010 paddr_nz (sp), (long) align_up (len, 16));
4012 /* Initialize the integer and float register pointers. */
4013 argreg = MIPS_A0_REGNUM;
4014 float_argreg = mips_fpa0_regnum (gdbarch);
4016 /* The struct_return pointer occupies the first parameter-passing reg. */
4020 fprintf_unfiltered (gdb_stdlog,
4021 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4022 argreg, paddr_nz (struct_addr));
4023 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4024 stack_offset += MIPS64_REGSIZE;
4027 /* Now load as many as possible of the first arguments into
4028 registers, and push the rest onto the stack. Loop thru args
4029 from first to last. */
4030 for (argnum = 0; argnum < nargs; argnum++)
4032 const gdb_byte *val;
4033 struct value *arg = args[argnum];
4034 struct type *arg_type = check_typedef (value_type (arg));
4035 int len = TYPE_LENGTH (arg_type);
4036 enum type_code typecode = TYPE_CODE (arg_type);
4039 fprintf_unfiltered (gdb_stdlog,
4040 "mips_o64_push_dummy_call: %d len=%d type=%d",
4041 argnum + 1, len, (int) typecode);
4043 val = value_contents (arg);
4045 /* Floating point arguments passed in registers have to be
4046 treated specially. On 32-bit architectures, doubles
4047 are passed in register pairs; the even register gets
4048 the low word, and the odd register gets the high word.
4049 On O32/O64, the first two floating point arguments are
4050 also copied to general registers, because MIPS16 functions
4051 don't use float registers for arguments. This duplication of
4052 arguments in general registers can't hurt non-MIPS16 functions
4053 because those registers are normally skipped. */
4055 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4056 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4058 LONGEST regval = extract_unsigned_integer (val, len);
4060 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4061 float_argreg, phex (regval, len));
4062 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
4064 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4065 argreg, phex (regval, len));
4066 regcache_cooked_write_unsigned (regcache, argreg, regval);
4068 /* Reserve space for the FP register. */
4069 stack_offset += align_up (len, MIPS64_REGSIZE);
4073 /* Copy the argument to general registers or the stack in
4074 register-sized pieces. Large arguments are split between
4075 registers and stack. */
4076 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4077 are treated specially: Irix cc passes them in registers
4078 where gcc sometimes puts them on the stack. For maximum
4079 compatibility, we will put them in both places. */
4080 int odd_sized_struct = (len > MIPS64_REGSIZE
4081 && len % MIPS64_REGSIZE != 0);
4084 /* Remember if the argument was written to the stack. */
4085 int stack_used_p = 0;
4086 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4089 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4092 /* Write this portion of the argument to the stack. */
4093 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4094 || odd_sized_struct)
4096 /* Should shorter than int integer values be
4097 promoted to int before being stored? */
4098 int longword_offset = 0;
4101 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4103 if ((typecode == TYPE_CODE_INT
4104 || typecode == TYPE_CODE_PTR
4105 || typecode == TYPE_CODE_FLT)
4107 longword_offset = MIPS64_REGSIZE - len;
4112 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
4113 paddr_nz (stack_offset));
4114 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
4115 paddr_nz (longword_offset));
4118 addr = sp + stack_offset + longword_offset;
4123 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
4125 for (i = 0; i < partial_len; i++)
4127 fprintf_unfiltered (gdb_stdlog, "%02x",
4131 write_memory (addr, val, partial_len);
4134 /* Note!!! This is NOT an else clause. Odd sized
4135 structs may go thru BOTH paths. */
4136 /* Write this portion of the argument to a general
4137 purpose register. */
4138 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4140 LONGEST regval = extract_signed_integer (val, partial_len);
4141 /* Value may need to be sign extended, because
4142 mips_isa_regsize() != mips_abi_regsize(). */
4144 /* A non-floating-point argument being passed in a
4145 general register. If a struct or union, and if
4146 the remaining length is smaller than the register
4147 size, we have to adjust the register value on
4150 It does not seem to be necessary to do the
4151 same for integral types. */
4153 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
4154 && partial_len < MIPS64_REGSIZE
4155 && (typecode == TYPE_CODE_STRUCT
4156 || typecode == TYPE_CODE_UNION))
4157 regval <<= ((MIPS64_REGSIZE - partial_len)
4161 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4163 phex (regval, MIPS64_REGSIZE));
4164 regcache_cooked_write_unsigned (regcache, argreg, regval);
4167 /* Prevent subsequent floating point arguments from
4168 being passed in floating point registers. */
4169 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
4175 /* Compute the the offset into the stack at which we
4176 will copy the next parameter.
4178 In older ABIs, the caller reserved space for
4179 registers that contained arguments. This was loosely
4180 refered to as their "home". Consequently, space is
4181 always allocated. */
4183 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
4187 fprintf_unfiltered (gdb_stdlog, "\n");
4190 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4192 /* Return adjusted stack pointer. */
4196 static enum return_value_convention
4197 mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type,
4198 struct type *type, struct regcache *regcache,
4199 gdb_byte *readbuf, const gdb_byte *writebuf)
4201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4203 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4204 || TYPE_CODE (type) == TYPE_CODE_UNION
4205 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
4206 return RETURN_VALUE_STRUCT_CONVENTION;
4207 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
4209 /* A floating-point value. It fits in the least significant
4212 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4213 mips_xfer_register (gdbarch, regcache,
4214 gdbarch_num_regs (gdbarch)
4215 + mips_regnum (gdbarch)->fp0,
4217 gdbarch_byte_order (gdbarch),
4218 readbuf, writebuf, 0);
4219 return RETURN_VALUE_REGISTER_CONVENTION;
4223 /* A scalar extract each part but least-significant-byte
4227 for (offset = 0, regnum = MIPS_V0_REGNUM;
4228 offset < TYPE_LENGTH (type);
4229 offset += MIPS64_REGSIZE, regnum++)
4231 int xfer = MIPS64_REGSIZE;
4232 if (offset + xfer > TYPE_LENGTH (type))
4233 xfer = TYPE_LENGTH (type) - offset;
4235 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4236 offset, xfer, regnum);
4237 mips_xfer_register (gdbarch, regcache,
4238 gdbarch_num_regs (gdbarch) + regnum,
4239 xfer, gdbarch_byte_order (gdbarch),
4240 readbuf, writebuf, offset);
4242 return RETURN_VALUE_REGISTER_CONVENTION;
4246 /* Floating point register management.
4248 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4249 64bit operations, these early MIPS cpus treat fp register pairs
4250 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4251 registers and offer a compatibility mode that emulates the MIPS2 fp
4252 model. When operating in MIPS2 fp compat mode, later cpu's split
4253 double precision floats into two 32-bit chunks and store them in
4254 consecutive fp regs. To display 64-bit floats stored in this
4255 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4256 Throw in user-configurable endianness and you have a real mess.
4258 The way this works is:
4259 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4260 double-precision value will be split across two logical registers.
4261 The lower-numbered logical register will hold the low-order bits,
4262 regardless of the processor's endianness.
4263 - If we are on a 64-bit processor, and we are looking for a
4264 single-precision value, it will be in the low ordered bits
4265 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4266 save slot in memory.
4267 - If we are in 64-bit mode, everything is straightforward.
4269 Note that this code only deals with "live" registers at the top of the
4270 stack. We will attempt to deal with saved registers later, when
4271 the raw/cooked register interface is in place. (We need a general
4272 interface that can deal with dynamic saved register sizes -- fp
4273 regs could be 32 bits wide in one frame and 64 on the frame above
4276 static struct type *
4277 mips_float_register_type (void)
4279 return builtin_type_ieee_single;
4282 static struct type *
4283 mips_double_register_type (void)
4285 return builtin_type_ieee_double;
4288 /* Copy a 32-bit single-precision value from the current frame
4289 into rare_buffer. */
4292 mips_read_fp_register_single (struct frame_info *frame, int regno,
4293 gdb_byte *rare_buffer)
4295 struct gdbarch *gdbarch = get_frame_arch (frame);
4296 int raw_size = register_size (gdbarch, regno);
4297 gdb_byte *raw_buffer = alloca (raw_size);
4299 if (!frame_register_read (frame, regno, raw_buffer))
4300 error (_("can't read register %d (%s)"),
4301 regno, gdbarch_register_name (gdbarch, regno));
4304 /* We have a 64-bit value for this register. Find the low-order
4308 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4313 memcpy (rare_buffer, raw_buffer + offset, 4);
4317 memcpy (rare_buffer, raw_buffer, 4);
4321 /* Copy a 64-bit double-precision value from the current frame into
4322 rare_buffer. This may include getting half of it from the next
4326 mips_read_fp_register_double (struct frame_info *frame, int regno,
4327 gdb_byte *rare_buffer)
4329 struct gdbarch *gdbarch = get_frame_arch (frame);
4330 int raw_size = register_size (gdbarch, regno);
4332 if (raw_size == 8 && !mips2_fp_compat (frame))
4334 /* We have a 64-bit value for this register, and we should use
4336 if (!frame_register_read (frame, regno, rare_buffer))
4337 error (_("can't read register %d (%s)"),
4338 regno, gdbarch_register_name (gdbarch, regno));
4342 int rawnum = regno % gdbarch_num_regs (gdbarch);
4344 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
4345 internal_error (__FILE__, __LINE__,
4346 _("mips_read_fp_register_double: bad access to "
4347 "odd-numbered FP register"));
4349 /* mips_read_fp_register_single will find the correct 32 bits from
4351 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4353 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4354 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4358 mips_read_fp_register_single (frame, regno, rare_buffer);
4359 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4365 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4367 { /* do values for FP (float) regs */
4368 struct gdbarch *gdbarch = get_frame_arch (frame);
4369 gdb_byte *raw_buffer;
4370 double doub, flt1; /* doubles extracted from raw hex data */
4373 raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0));
4375 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
4376 fprintf_filtered (file, "%*s",
4377 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
4380 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
4382 struct value_print_options opts;
4384 /* 4-byte registers: Print hex and floating. Also print even
4385 numbered registers as doubles. */
4386 mips_read_fp_register_single (frame, regnum, raw_buffer);
4387 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4389 get_formatted_print_options (&opts, 'x');
4390 print_scalar_formatted (raw_buffer, builtin_type_uint32, &opts, 'w',
4393 fprintf_filtered (file, " flt: ");
4395 fprintf_filtered (file, " <invalid float> ");
4397 fprintf_filtered (file, "%-17.9g", flt1);
4399 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
4401 mips_read_fp_register_double (frame, regnum, raw_buffer);
4402 doub = unpack_double (mips_double_register_type (), raw_buffer,
4405 fprintf_filtered (file, " dbl: ");
4407 fprintf_filtered (file, "<invalid double>");
4409 fprintf_filtered (file, "%-24.17g", doub);
4414 struct value_print_options opts;
4416 /* Eight byte registers: print each one as hex, float and double. */
4417 mips_read_fp_register_single (frame, regnum, raw_buffer);
4418 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4420 mips_read_fp_register_double (frame, regnum, raw_buffer);
4421 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4423 get_formatted_print_options (&opts, 'x');
4424 print_scalar_formatted (raw_buffer, builtin_type_uint64, &opts, 'g',
4427 fprintf_filtered (file, " flt: ");
4429 fprintf_filtered (file, "<invalid float>");
4431 fprintf_filtered (file, "%-17.9g", flt1);
4433 fprintf_filtered (file, " dbl: ");
4435 fprintf_filtered (file, "<invalid double>");
4437 fprintf_filtered (file, "%-24.17g", doub);
4442 mips_print_register (struct ui_file *file, struct frame_info *frame,
4445 struct gdbarch *gdbarch = get_frame_arch (frame);
4446 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4448 struct value_print_options opts;
4450 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4452 mips_print_fp_register (file, frame, regnum);
4456 /* Get the data in raw format. */
4457 if (!frame_register_read (frame, regnum, raw_buffer))
4459 fprintf_filtered (file, "%s: [Invalid]",
4460 gdbarch_register_name (gdbarch, regnum));
4464 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
4466 /* The problem with printing numeric register names (r26, etc.) is that
4467 the user can't use them on input. Probably the best solution is to
4468 fix it so that either the numeric or the funky (a2, etc.) names
4469 are accepted on input. */
4470 if (regnum < MIPS_NUMREGS)
4471 fprintf_filtered (file, "(r%d): ", regnum);
4473 fprintf_filtered (file, ": ");
4475 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4477 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4481 get_formatted_print_options (&opts, 'x');
4482 print_scalar_formatted (raw_buffer + offset,
4483 register_type (gdbarch, regnum), &opts, 0,
4487 /* Replacement for generic do_registers_info.
4488 Print regs in pretty columns. */
4491 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4494 fprintf_filtered (file, " ");
4495 mips_print_fp_register (file, frame, regnum);
4496 fprintf_filtered (file, "\n");
4501 /* Print a row's worth of GP (int) registers, with name labels above */
4504 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4507 struct gdbarch *gdbarch = get_frame_arch (frame);
4508 /* do values for GP (int) regs */
4509 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4510 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4514 /* For GP registers, we print a separate row of names above the vals */
4515 for (col = 0, regnum = start_regnum;
4516 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4517 + gdbarch_num_pseudo_regs (gdbarch);
4520 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4521 continue; /* unused register */
4522 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4524 break; /* end the row: reached FP register */
4525 /* Large registers are handled separately. */
4526 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4529 break; /* End the row before this register. */
4531 /* Print this register on a row by itself. */
4532 mips_print_register (file, frame, regnum);
4533 fprintf_filtered (file, "\n");
4537 fprintf_filtered (file, " ");
4538 fprintf_filtered (file,
4539 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
4540 gdbarch_register_name (gdbarch, regnum));
4547 /* print the R0 to R31 names */
4548 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
4549 fprintf_filtered (file, "\n R%-4d",
4550 start_regnum % gdbarch_num_regs (gdbarch));
4552 fprintf_filtered (file, "\n ");
4554 /* now print the values in hex, 4 or 8 to the row */
4555 for (col = 0, regnum = start_regnum;
4556 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4557 + gdbarch_num_pseudo_regs (gdbarch);
4560 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4561 continue; /* unused register */
4562 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4564 break; /* end row: reached FP register */
4565 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4566 break; /* End row: large register. */
4568 /* OK: get the data in raw format. */
4569 if (!frame_register_read (frame, regnum, raw_buffer))
4570 error (_("can't read register %d (%s)"),
4571 regnum, gdbarch_register_name (gdbarch, regnum));
4572 /* pad small registers */
4574 byte < (mips_abi_regsize (gdbarch)
4575 - register_size (gdbarch, regnum)); byte++)
4576 printf_filtered (" ");
4577 /* Now print the register value in hex, endian order. */
4578 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4580 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4581 byte < register_size (gdbarch, regnum); byte++)
4582 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4584 for (byte = register_size (gdbarch, regnum) - 1;
4586 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4587 fprintf_filtered (file, " ");
4590 if (col > 0) /* ie. if we actually printed anything... */
4591 fprintf_filtered (file, "\n");
4596 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4599 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4600 struct frame_info *frame, int regnum, int all)
4602 if (regnum != -1) /* do one specified register */
4604 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
4605 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
4606 error (_("Not a valid register for the current processor type"));
4608 mips_print_register (file, frame, regnum);
4609 fprintf_filtered (file, "\n");
4612 /* do all (or most) registers */
4614 regnum = gdbarch_num_regs (gdbarch);
4615 while (regnum < gdbarch_num_regs (gdbarch)
4616 + gdbarch_num_pseudo_regs (gdbarch))
4618 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4621 if (all) /* true for "INFO ALL-REGISTERS" command */
4622 regnum = print_fp_register_row (file, frame, regnum);
4624 regnum += MIPS_NUMREGS; /* skip floating point regs */
4627 regnum = print_gp_register_row (file, frame, regnum);
4632 /* Is this a branch with a delay slot? */
4635 is_delayed (unsigned long insn)
4638 for (i = 0; i < NUMOPCODES; ++i)
4639 if (mips_opcodes[i].pinfo != INSN_MACRO
4640 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4642 return (i < NUMOPCODES
4643 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4644 | INSN_COND_BRANCH_DELAY
4645 | INSN_COND_BRANCH_LIKELY)));
4649 mips_single_step_through_delay (struct gdbarch *gdbarch,
4650 struct frame_info *frame)
4652 CORE_ADDR pc = get_frame_pc (frame);
4653 gdb_byte buf[MIPS_INSN32_SIZE];
4655 /* There is no branch delay slot on MIPS16. */
4656 if (mips_pc_is_mips16 (pc))
4659 if (!breakpoint_here_p (pc + 4))
4662 if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf))
4663 /* If error reading memory, guess that it is not a delayed
4666 return is_delayed (extract_unsigned_integer (buf, sizeof buf));
4669 /* To skip prologues, I use this predicate. Returns either PC itself
4670 if the code at PC does not look like a function prologue; otherwise
4671 returns an address that (if we're lucky) follows the prologue. If
4672 LENIENT, then we must skip everything which is involved in setting
4673 up the frame (it's OK to skip more, just so long as we don't skip
4674 anything which might clobber the registers which are being saved.
4675 We must skip more in the case where part of the prologue is in the
4676 delay slot of a non-prologue instruction). */
4679 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
4682 CORE_ADDR func_addr;
4684 /* See if we can determine the end of the prologue via the symbol table.
4685 If so, then return either PC, or the PC after the prologue, whichever
4687 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
4689 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
4690 if (post_prologue_pc != 0)
4691 return max (pc, post_prologue_pc);
4694 /* Can't determine prologue from the symbol table, need to examine
4697 /* Find an upper limit on the function prologue using the debug
4698 information. If the debug information could not be used to provide
4699 that bound, then use an arbitrary large number as the upper bound. */
4700 limit_pc = skip_prologue_using_sal (pc);
4702 limit_pc = pc + 100; /* Magic. */
4704 if (mips_pc_is_mips16 (pc))
4705 return mips16_scan_prologue (pc, limit_pc, NULL, NULL);
4707 return mips32_scan_prologue (pc, limit_pc, NULL, NULL);
4710 /* Check whether the PC is in a function epilogue (32-bit version).
4711 This is a helper function for mips_in_function_epilogue_p. */
4713 mips32_in_function_epilogue_p (CORE_ADDR pc)
4715 CORE_ADDR func_addr = 0, func_end = 0;
4717 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4719 /* The MIPS epilogue is max. 12 bytes long. */
4720 CORE_ADDR addr = func_end - 12;
4722 if (addr < func_addr + 4)
4723 addr = func_addr + 4;
4727 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
4729 unsigned long high_word;
4732 inst = mips_fetch_instruction (pc);
4733 high_word = (inst >> 16) & 0xffff;
4735 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
4736 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
4737 && inst != 0x03e00008 /* jr $ra */
4738 && inst != 0x00000000) /* nop */
4748 /* Check whether the PC is in a function epilogue (16-bit version).
4749 This is a helper function for mips_in_function_epilogue_p. */
4751 mips16_in_function_epilogue_p (CORE_ADDR pc)
4753 CORE_ADDR func_addr = 0, func_end = 0;
4755 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4757 /* The MIPS epilogue is max. 12 bytes long. */
4758 CORE_ADDR addr = func_end - 12;
4760 if (addr < func_addr + 4)
4761 addr = func_addr + 4;
4765 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
4767 unsigned short inst;
4769 inst = mips_fetch_instruction (pc);
4771 if ((inst & 0xf800) == 0xf000) /* extend */
4774 if (inst != 0x6300 /* addiu $sp,offset */
4775 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
4776 && inst != 0xe820 /* jr $ra */
4777 && inst != 0xe8a0 /* jrc $ra */
4778 && inst != 0x6500) /* nop */
4788 /* The epilogue is defined here as the area at the end of a function,
4789 after an instruction which destroys the function's stack frame. */
4791 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4793 if (mips_pc_is_mips16 (pc))
4794 return mips16_in_function_epilogue_p (pc);
4796 return mips32_in_function_epilogue_p (pc);
4799 /* Root of all "set mips "/"show mips " commands. This will eventually be
4800 used for all MIPS-specific commands. */
4803 show_mips_command (char *args, int from_tty)
4805 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4809 set_mips_command (char *args, int from_tty)
4812 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4813 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4816 /* Commands to show/set the MIPS FPU type. */
4819 show_mipsfpu_command (char *args, int from_tty)
4823 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
4826 ("The MIPS floating-point coprocessor is unknown "
4827 "because the current architecture is not MIPS.\n");
4831 switch (MIPS_FPU_TYPE (target_gdbarch))
4833 case MIPS_FPU_SINGLE:
4834 fpu = "single-precision";
4836 case MIPS_FPU_DOUBLE:
4837 fpu = "double-precision";
4840 fpu = "absent (none)";
4843 internal_error (__FILE__, __LINE__, _("bad switch"));
4845 if (mips_fpu_type_auto)
4847 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4851 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4856 set_mipsfpu_command (char *args, int from_tty)
4859 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4860 show_mipsfpu_command (args, from_tty);
4864 set_mipsfpu_single_command (char *args, int from_tty)
4866 struct gdbarch_info info;
4867 gdbarch_info_init (&info);
4868 mips_fpu_type = MIPS_FPU_SINGLE;
4869 mips_fpu_type_auto = 0;
4870 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4871 instead of relying on globals. Doing that would let generic code
4872 handle the search for this specific architecture. */
4873 if (!gdbarch_update_p (info))
4874 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4878 set_mipsfpu_double_command (char *args, int from_tty)
4880 struct gdbarch_info info;
4881 gdbarch_info_init (&info);
4882 mips_fpu_type = MIPS_FPU_DOUBLE;
4883 mips_fpu_type_auto = 0;
4884 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4885 instead of relying on globals. Doing that would let generic code
4886 handle the search for this specific architecture. */
4887 if (!gdbarch_update_p (info))
4888 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4892 set_mipsfpu_none_command (char *args, int from_tty)
4894 struct gdbarch_info info;
4895 gdbarch_info_init (&info);
4896 mips_fpu_type = MIPS_FPU_NONE;
4897 mips_fpu_type_auto = 0;
4898 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4899 instead of relying on globals. Doing that would let generic code
4900 handle the search for this specific architecture. */
4901 if (!gdbarch_update_p (info))
4902 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4906 set_mipsfpu_auto_command (char *args, int from_tty)
4908 mips_fpu_type_auto = 1;
4911 /* Attempt to identify the particular processor model by reading the
4912 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4913 the relevant processor still exists (it dates back to '94) and
4914 secondly this is not the way to do this. The processor type should
4915 be set by forcing an architecture change. */
4918 deprecated_mips_set_processor_regs_hack (void)
4920 struct regcache *regcache = get_current_regcache ();
4921 struct gdbarch *gdbarch = get_regcache_arch (regcache);
4922 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4925 regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid);
4926 if ((prid & ~0xf) == 0x700)
4927 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4930 /* Just like reinit_frame_cache, but with the right arguments to be
4931 callable as an sfunc. */
4934 reinit_frame_cache_sfunc (char *args, int from_tty,
4935 struct cmd_list_element *c)
4937 reinit_frame_cache ();
4941 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4943 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4944 disassembler needs to be able to locally determine the ISA, and
4945 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4947 if (mips_pc_is_mips16 (memaddr))
4948 info->mach = bfd_mach_mips16;
4950 /* Round down the instruction address to the appropriate boundary. */
4951 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4953 /* Set the disassembler options. */
4954 if (!info->disassembler_options)
4955 /* This string is not recognized explicitly by the disassembler,
4956 but it tells the disassembler to not try to guess the ABI from
4957 the bfd elf headers, such that, if the user overrides the ABI
4958 of a program linked as NewABI, the disassembly will follow the
4959 register naming conventions specified by the user. */
4960 info->disassembler_options = "gpr-names=32";
4962 /* Call the appropriate disassembler based on the target endian-ness. */
4963 if (info->endian == BFD_ENDIAN_BIG)
4964 return print_insn_big_mips (memaddr, info);
4966 return print_insn_little_mips (memaddr, info);
4970 gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
4972 /* Set up the disassembler info, so that we get the right
4973 register names from libopcodes. */
4974 info->disassembler_options = "gpr-names=n32";
4975 info->flavour = bfd_target_elf_flavour;
4977 return gdb_print_insn_mips (memaddr, info);
4981 gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
4983 /* Set up the disassembler info, so that we get the right
4984 register names from libopcodes. */
4985 info->disassembler_options = "gpr-names=64";
4986 info->flavour = bfd_target_elf_flavour;
4988 return gdb_print_insn_mips (memaddr, info);
4991 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4992 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4993 It returns a pointer to a string of bytes that encode a breakpoint
4994 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4995 necessary) to point to the actual memory location where the breakpoint
4996 should be inserted. */
4998 static const gdb_byte *
4999 mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
5001 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5003 if (mips_pc_is_mips16 (*pcptr))
5005 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
5006 *pcptr = unmake_mips16_addr (*pcptr);
5007 *lenptr = sizeof (mips16_big_breakpoint);
5008 return mips16_big_breakpoint;
5012 /* The IDT board uses an unusual breakpoint value, and
5013 sometimes gets confused when it sees the usual MIPS
5014 breakpoint instruction. */
5015 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
5016 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
5017 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
5019 *lenptr = sizeof (big_breakpoint);
5021 if (strcmp (target_shortname, "mips") == 0)
5022 return idt_big_breakpoint;
5023 else if (strcmp (target_shortname, "ddb") == 0
5024 || strcmp (target_shortname, "pmon") == 0
5025 || strcmp (target_shortname, "lsi") == 0)
5026 return pmon_big_breakpoint;
5028 return big_breakpoint;
5033 if (mips_pc_is_mips16 (*pcptr))
5035 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
5036 *pcptr = unmake_mips16_addr (*pcptr);
5037 *lenptr = sizeof (mips16_little_breakpoint);
5038 return mips16_little_breakpoint;
5042 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
5043 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
5044 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
5046 *lenptr = sizeof (little_breakpoint);
5048 if (strcmp (target_shortname, "mips") == 0)
5049 return idt_little_breakpoint;
5050 else if (strcmp (target_shortname, "ddb") == 0
5051 || strcmp (target_shortname, "pmon") == 0
5052 || strcmp (target_shortname, "lsi") == 0)
5053 return pmon_little_breakpoint;
5055 return little_breakpoint;
5060 /* If PC is in a mips16 call or return stub, return the address of the target
5061 PC, which is either the callee or the caller. There are several
5062 cases which must be handled:
5064 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5065 target PC is in $31 ($ra).
5066 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5067 and the target PC is in $2.
5068 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5069 before the jal instruction, this is effectively a call stub
5070 and the the target PC is in $2. Otherwise this is effectively
5071 a return stub and the target PC is in $18.
5073 See the source code for the stubs in gcc/config/mips/mips16.S for
5077 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5080 CORE_ADDR start_addr;
5082 /* Find the starting address and name of the function containing the PC. */
5083 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5086 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5087 target PC is in $31 ($ra). */
5088 if (strcmp (name, "__mips16_ret_sf") == 0
5089 || strcmp (name, "__mips16_ret_df") == 0)
5090 return get_frame_register_signed (frame, MIPS_RA_REGNUM);
5092 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5094 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5095 and the target PC is in $2. */
5096 if (name[19] >= '0' && name[19] <= '9')
5097 return get_frame_register_signed (frame, 2);
5099 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5100 before the jal instruction, this is effectively a call stub
5101 and the the target PC is in $2. Otherwise this is effectively
5102 a return stub and the target PC is in $18. */
5103 else if (name[19] == 's' || name[19] == 'd')
5105 if (pc == start_addr)
5107 /* Check if the target of the stub is a compiler-generated
5108 stub. Such a stub for a function bar might have a name
5109 like __fn_stub_bar, and might look like this:
5114 la $1,bar (becomes a lui/addiu pair)
5116 So scan down to the lui/addi and extract the target
5117 address from those two instructions. */
5119 CORE_ADDR target_pc = get_frame_register_signed (frame, 2);
5123 /* See if the name of the target function is __fn_stub_*. */
5124 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
5127 if (strncmp (name, "__fn_stub_", 10) != 0
5128 && strcmp (name, "etext") != 0
5129 && strcmp (name, "_etext") != 0)
5132 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5133 The limit on the search is arbitrarily set to 20
5134 instructions. FIXME. */
5135 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE)
5137 inst = mips_fetch_instruction (target_pc);
5138 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5139 pc = (inst << 16) & 0xffff0000; /* high word */
5140 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5141 return pc | (inst & 0xffff); /* low word */
5144 /* Couldn't find the lui/addui pair, so return stub address. */
5148 /* This is the 'return' part of a call stub. The return
5149 address is in $r18. */
5150 return get_frame_register_signed (frame, 18);
5153 return 0; /* not a stub */
5156 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5157 PC of the stub target. The stub just loads $t9 and jumps to it,
5158 so that $t9 has the correct value at function entry. */
5161 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5163 struct minimal_symbol *msym;
5165 gdb_byte stub_code[16];
5166 int32_t stub_words[4];
5168 /* The stub for foo is named ".pic.foo", and is either two
5169 instructions inserted before foo or a three instruction sequence
5170 which jumps to foo. */
5171 msym = lookup_minimal_symbol_by_pc (pc);
5173 || SYMBOL_VALUE_ADDRESS (msym) != pc
5174 || SYMBOL_LINKAGE_NAME (msym) == NULL
5175 || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0)
5178 /* A two-instruction header. */
5179 if (MSYMBOL_SIZE (msym) == 8)
5182 /* A three-instruction (plus delay slot) trampoline. */
5183 if (MSYMBOL_SIZE (msym) == 16)
5185 if (target_read_memory (pc, stub_code, 16) != 0)
5187 for (i = 0; i < 4; i++)
5188 stub_words[i] = extract_unsigned_integer (stub_code + i * 4, 4);
5190 /* A stub contains these instructions:
5193 addiu t9, t9, %lo(target)
5196 This works even for N64, since stubs are only generated with
5198 if ((stub_words[0] & 0xffff0000U) == 0x3c190000
5199 && (stub_words[1] & 0xfc000000U) == 0x08000000
5200 && (stub_words[2] & 0xffff0000U) == 0x27390000
5201 && stub_words[3] == 0x00000000)
5202 return (((stub_words[0] & 0x0000ffff) << 16)
5203 + (stub_words[2] & 0x0000ffff));
5206 /* Not a recognized stub. */
5211 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5213 CORE_ADDR target_pc;
5215 target_pc = mips_skip_mips16_trampoline_code (frame, pc);
5219 target_pc = find_solib_trampoline_target (frame, pc);
5223 target_pc = mips_skip_pic_trampoline_code (frame, pc);
5230 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5231 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5234 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
5237 if (num >= 0 && num < 32)
5239 else if (num >= 38 && num < 70)
5240 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
5242 regnum = mips_regnum (gdbarch)->hi;
5244 regnum = mips_regnum (gdbarch)->lo;
5246 /* This will hopefully (eventually) provoke a warning. Should
5247 we be calling complaint() here? */
5248 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5249 return gdbarch_num_regs (gdbarch) + regnum;
5253 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5254 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5257 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
5260 if (num >= 0 && num < 32)
5262 else if (num >= 32 && num < 64)
5263 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
5265 regnum = mips_regnum (gdbarch)->hi;
5267 regnum = mips_regnum (gdbarch)->lo;
5269 /* This will hopefully (eventually) provoke a warning. Should we
5270 be calling complaint() here? */
5271 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5272 return gdbarch_num_regs (gdbarch) + regnum;
5276 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
5278 /* Only makes sense to supply raw registers. */
5279 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
5280 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5281 decide if it is valid. Should instead define a standard sim/gdb
5282 register numbering scheme. */
5283 if (gdbarch_register_name (gdbarch,
5284 gdbarch_num_regs (gdbarch) + regnum) != NULL
5285 && gdbarch_register_name (gdbarch,
5286 gdbarch_num_regs (gdbarch) + regnum)[0] != '\0')
5289 return LEGACY_SIM_REGNO_IGNORE;
5293 /* Convert an integer into an address. Extracting the value signed
5294 guarantees a correctly sign extended address. */
5297 mips_integer_to_address (struct gdbarch *gdbarch,
5298 struct type *type, const gdb_byte *buf)
5300 return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type));
5303 /* Dummy virtual frame pointer method. This is no more or less accurate
5304 than most other architectures; we just need to be explicit about it,
5305 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5306 an assertion failure. */
5309 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
5310 CORE_ADDR pc, int *reg, LONGEST *offset)
5312 *reg = MIPS_SP_REGNUM;
5317 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5319 enum mips_abi *abip = (enum mips_abi *) obj;
5320 const char *name = bfd_get_section_name (abfd, sect);
5322 if (*abip != MIPS_ABI_UNKNOWN)
5325 if (strncmp (name, ".mdebug.", 8) != 0)
5328 if (strcmp (name, ".mdebug.abi32") == 0)
5329 *abip = MIPS_ABI_O32;
5330 else if (strcmp (name, ".mdebug.abiN32") == 0)
5331 *abip = MIPS_ABI_N32;
5332 else if (strcmp (name, ".mdebug.abi64") == 0)
5333 *abip = MIPS_ABI_N64;
5334 else if (strcmp (name, ".mdebug.abiO64") == 0)
5335 *abip = MIPS_ABI_O64;
5336 else if (strcmp (name, ".mdebug.eabi32") == 0)
5337 *abip = MIPS_ABI_EABI32;
5338 else if (strcmp (name, ".mdebug.eabi64") == 0)
5339 *abip = MIPS_ABI_EABI64;
5341 warning (_("unsupported ABI %s."), name + 8);
5345 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
5347 int *lbp = (int *) obj;
5348 const char *name = bfd_get_section_name (abfd, sect);
5350 if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
5352 else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
5354 else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
5355 warning (_("unrecognized .gcc_compiled_longXX"));
5358 static enum mips_abi
5359 global_mips_abi (void)
5363 for (i = 0; mips_abi_strings[i] != NULL; i++)
5364 if (mips_abi_strings[i] == mips_abi_string)
5365 return (enum mips_abi) i;
5367 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
5371 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
5373 /* If the size matches the set of 32-bit or 64-bit integer registers,
5374 assume that's what we've got. */
5375 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
5376 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
5378 /* If the size matches the full set of registers GDB traditionally
5379 knows about, including floating point, for either 32-bit or
5380 64-bit, assume that's what we've got. */
5381 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
5382 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
5384 /* Otherwise we don't have a useful guess. */
5387 static struct value *
5388 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
5390 const int *reg_p = baton;
5391 return value_of_register (*reg_p, frame);
5394 static struct gdbarch *
5395 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5397 struct gdbarch *gdbarch;
5398 struct gdbarch_tdep *tdep;
5400 enum mips_abi mips_abi, found_abi, wanted_abi;
5402 enum mips_fpu_type fpu_type;
5403 struct tdesc_arch_data *tdesc_data = NULL;
5404 int elf_fpu_type = 0;
5406 /* Check any target description for validity. */
5407 if (tdesc_has_registers (info.target_desc))
5409 static const char *const mips_gprs[] = {
5410 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5411 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5412 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5413 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5415 static const char *const mips_fprs[] = {
5416 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5417 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5418 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5419 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5422 const struct tdesc_feature *feature;
5425 feature = tdesc_find_feature (info.target_desc,
5426 "org.gnu.gdb.mips.cpu");
5427 if (feature == NULL)
5430 tdesc_data = tdesc_data_alloc ();
5433 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
5434 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
5438 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5439 MIPS_EMBED_LO_REGNUM, "lo");
5440 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5441 MIPS_EMBED_HI_REGNUM, "hi");
5442 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5443 MIPS_EMBED_PC_REGNUM, "pc");
5447 tdesc_data_cleanup (tdesc_data);
5451 feature = tdesc_find_feature (info.target_desc,
5452 "org.gnu.gdb.mips.cp0");
5453 if (feature == NULL)
5455 tdesc_data_cleanup (tdesc_data);
5460 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5461 MIPS_EMBED_BADVADDR_REGNUM,
5463 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5464 MIPS_PS_REGNUM, "status");
5465 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5466 MIPS_EMBED_CAUSE_REGNUM, "cause");
5470 tdesc_data_cleanup (tdesc_data);
5474 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5475 backend is not prepared for that, though. */
5476 feature = tdesc_find_feature (info.target_desc,
5477 "org.gnu.gdb.mips.fpu");
5478 if (feature == NULL)
5480 tdesc_data_cleanup (tdesc_data);
5485 for (i = 0; i < 32; i++)
5486 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5487 i + MIPS_EMBED_FP0_REGNUM,
5490 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5491 MIPS_EMBED_FP0_REGNUM + 32, "fcsr");
5492 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5493 MIPS_EMBED_FP0_REGNUM + 33, "fir");
5497 tdesc_data_cleanup (tdesc_data);
5501 /* It would be nice to detect an attempt to use a 64-bit ABI
5502 when only 32-bit registers are provided. */
5505 /* First of all, extract the elf_flags, if available. */
5506 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5507 elf_flags = elf_elfheader (info.abfd)->e_flags;
5508 else if (arches != NULL)
5509 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5513 fprintf_unfiltered (gdb_stdlog,
5514 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5516 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5517 switch ((elf_flags & EF_MIPS_ABI))
5519 case E_MIPS_ABI_O32:
5520 found_abi = MIPS_ABI_O32;
5522 case E_MIPS_ABI_O64:
5523 found_abi = MIPS_ABI_O64;
5525 case E_MIPS_ABI_EABI32:
5526 found_abi = MIPS_ABI_EABI32;
5528 case E_MIPS_ABI_EABI64:
5529 found_abi = MIPS_ABI_EABI64;
5532 if ((elf_flags & EF_MIPS_ABI2))
5533 found_abi = MIPS_ABI_N32;
5535 found_abi = MIPS_ABI_UNKNOWN;
5539 /* GCC creates a pseudo-section whose name describes the ABI. */
5540 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5541 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5543 /* If we have no useful BFD information, use the ABI from the last
5544 MIPS architecture (if there is one). */
5545 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5546 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5548 /* Try the architecture for any hint of the correct ABI. */
5549 if (found_abi == MIPS_ABI_UNKNOWN
5550 && info.bfd_arch_info != NULL
5551 && info.bfd_arch_info->arch == bfd_arch_mips)
5553 switch (info.bfd_arch_info->mach)
5555 case bfd_mach_mips3900:
5556 found_abi = MIPS_ABI_EABI32;
5558 case bfd_mach_mips4100:
5559 case bfd_mach_mips5000:
5560 found_abi = MIPS_ABI_EABI64;
5562 case bfd_mach_mips8000:
5563 case bfd_mach_mips10000:
5564 /* On Irix, ELF64 executables use the N64 ABI. The
5565 pseudo-sections which describe the ABI aren't present
5566 on IRIX. (Even for executables created by gcc.) */
5567 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5568 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5569 found_abi = MIPS_ABI_N64;
5571 found_abi = MIPS_ABI_N32;
5576 /* Default 64-bit objects to N64 instead of O32. */
5577 if (found_abi == MIPS_ABI_UNKNOWN
5578 && info.abfd != NULL
5579 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5580 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5581 found_abi = MIPS_ABI_N64;
5584 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5587 /* What has the user specified from the command line? */
5588 wanted_abi = global_mips_abi ();
5590 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5593 /* Now that we have found what the ABI for this binary would be,
5594 check whether the user is overriding it. */
5595 if (wanted_abi != MIPS_ABI_UNKNOWN)
5596 mips_abi = wanted_abi;
5597 else if (found_abi != MIPS_ABI_UNKNOWN)
5598 mips_abi = found_abi;
5600 mips_abi = MIPS_ABI_O32;
5602 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5605 /* Also used when doing an architecture lookup. */
5607 fprintf_unfiltered (gdb_stdlog,
5608 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5609 mips64_transfers_32bit_regs_p);
5611 /* Determine the MIPS FPU type. */
5614 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5615 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5616 Tag_GNU_MIPS_ABI_FP);
5617 #endif /* HAVE_ELF */
5619 if (!mips_fpu_type_auto)
5620 fpu_type = mips_fpu_type;
5621 else if (elf_fpu_type != 0)
5623 switch (elf_fpu_type)
5626 fpu_type = MIPS_FPU_DOUBLE;
5629 fpu_type = MIPS_FPU_SINGLE;
5633 /* Soft float or unknown. */
5634 fpu_type = MIPS_FPU_NONE;
5638 else if (info.bfd_arch_info != NULL
5639 && info.bfd_arch_info->arch == bfd_arch_mips)
5640 switch (info.bfd_arch_info->mach)
5642 case bfd_mach_mips3900:
5643 case bfd_mach_mips4100:
5644 case bfd_mach_mips4111:
5645 case bfd_mach_mips4120:
5646 fpu_type = MIPS_FPU_NONE;
5648 case bfd_mach_mips4650:
5649 fpu_type = MIPS_FPU_SINGLE;
5652 fpu_type = MIPS_FPU_DOUBLE;
5655 else if (arches != NULL)
5656 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5658 fpu_type = MIPS_FPU_DOUBLE;
5660 fprintf_unfiltered (gdb_stdlog,
5661 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5663 /* Check for blatant incompatibilities. */
5665 /* If we have only 32-bit registers, then we can't debug a 64-bit
5667 if (info.target_desc
5668 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
5669 && mips_abi != MIPS_ABI_EABI32
5670 && mips_abi != MIPS_ABI_O32)
5672 if (tdesc_data != NULL)
5673 tdesc_data_cleanup (tdesc_data);
5677 /* try to find a pre-existing architecture */
5678 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5680 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5682 /* MIPS needs to be pedantic about which ABI the object is
5684 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5686 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5688 /* Need to be pedantic about which register virtual size is
5690 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5691 != mips64_transfers_32bit_regs_p)
5693 /* Be pedantic about which FPU is selected. */
5694 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5697 if (tdesc_data != NULL)
5698 tdesc_data_cleanup (tdesc_data);
5699 return arches->gdbarch;
5702 /* Need a new architecture. Fill in a target specific vector. */
5703 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5704 gdbarch = gdbarch_alloc (&info, tdep);
5705 tdep->elf_flags = elf_flags;
5706 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5707 tdep->found_abi = found_abi;
5708 tdep->mips_abi = mips_abi;
5709 tdep->mips_fpu_type = fpu_type;
5710 tdep->register_size_valid_p = 0;
5711 tdep->register_size = 0;
5713 if (info.target_desc)
5715 /* Some useful properties can be inferred from the target. */
5716 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
5718 tdep->register_size_valid_p = 1;
5719 tdep->register_size = 4;
5721 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
5723 tdep->register_size_valid_p = 1;
5724 tdep->register_size = 8;
5728 /* Initially set everything according to the default ABI/ISA. */
5729 set_gdbarch_short_bit (gdbarch, 16);
5730 set_gdbarch_int_bit (gdbarch, 32);
5731 set_gdbarch_float_bit (gdbarch, 32);
5732 set_gdbarch_double_bit (gdbarch, 64);
5733 set_gdbarch_long_double_bit (gdbarch, 64);
5734 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5735 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5736 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5738 set_gdbarch_elf_make_msymbol_special (gdbarch,
5739 mips_elf_make_msymbol_special);
5741 /* Fill in the OS dependant register numbers and names. */
5743 const char **reg_names;
5744 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
5745 struct mips_regnum);
5746 if (tdesc_has_registers (info.target_desc))
5748 regnum->lo = MIPS_EMBED_LO_REGNUM;
5749 regnum->hi = MIPS_EMBED_HI_REGNUM;
5750 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5751 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5752 regnum->pc = MIPS_EMBED_PC_REGNUM;
5753 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5754 regnum->fp_control_status = 70;
5755 regnum->fp_implementation_revision = 71;
5756 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
5759 else if (info.osabi == GDB_OSABI_IRIX)
5764 regnum->badvaddr = 66;
5767 regnum->fp_control_status = 69;
5768 regnum->fp_implementation_revision = 70;
5770 reg_names = mips_irix_reg_names;
5774 regnum->lo = MIPS_EMBED_LO_REGNUM;
5775 regnum->hi = MIPS_EMBED_HI_REGNUM;
5776 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5777 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5778 regnum->pc = MIPS_EMBED_PC_REGNUM;
5779 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5780 regnum->fp_control_status = 70;
5781 regnum->fp_implementation_revision = 71;
5783 if (info.bfd_arch_info != NULL
5784 && info.bfd_arch_info->mach == bfd_mach_mips3900)
5785 reg_names = mips_tx39_reg_names;
5787 reg_names = mips_generic_reg_names;
5789 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5790 replaced by read_pc? */
5791 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
5792 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
5793 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
5794 set_gdbarch_num_regs (gdbarch, num_regs);
5795 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5796 set_gdbarch_register_name (gdbarch, mips_register_name);
5797 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
5798 tdep->mips_processor_reg_names = reg_names;
5799 tdep->regnum = regnum;
5805 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5806 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
5807 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5808 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5809 tdep->default_mask_address_p = 0;
5810 set_gdbarch_long_bit (gdbarch, 32);
5811 set_gdbarch_ptr_bit (gdbarch, 32);
5812 set_gdbarch_long_long_bit (gdbarch, 64);
5815 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5816 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
5817 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5818 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5819 tdep->default_mask_address_p = 0;
5820 set_gdbarch_long_bit (gdbarch, 32);
5821 set_gdbarch_ptr_bit (gdbarch, 32);
5822 set_gdbarch_long_long_bit (gdbarch, 64);
5824 case MIPS_ABI_EABI32:
5825 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5826 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5827 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5828 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5829 tdep->default_mask_address_p = 0;
5830 set_gdbarch_long_bit (gdbarch, 32);
5831 set_gdbarch_ptr_bit (gdbarch, 32);
5832 set_gdbarch_long_long_bit (gdbarch, 64);
5834 case MIPS_ABI_EABI64:
5835 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5836 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5837 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5838 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5839 tdep->default_mask_address_p = 0;
5840 set_gdbarch_long_bit (gdbarch, 64);
5841 set_gdbarch_ptr_bit (gdbarch, 64);
5842 set_gdbarch_long_long_bit (gdbarch, 64);
5845 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5846 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5847 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5848 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5849 tdep->default_mask_address_p = 0;
5850 set_gdbarch_long_bit (gdbarch, 32);
5851 set_gdbarch_ptr_bit (gdbarch, 32);
5852 set_gdbarch_long_long_bit (gdbarch, 64);
5853 set_gdbarch_long_double_bit (gdbarch, 128);
5854 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
5857 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5858 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5859 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5860 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5861 tdep->default_mask_address_p = 0;
5862 set_gdbarch_long_bit (gdbarch, 64);
5863 set_gdbarch_ptr_bit (gdbarch, 64);
5864 set_gdbarch_long_long_bit (gdbarch, 64);
5865 set_gdbarch_long_double_bit (gdbarch, 128);
5866 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
5869 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5872 /* GCC creates a pseudo-section whose name specifies the size of
5873 longs, since -mlong32 or -mlong64 may be used independent of
5874 other options. How those options affect pointer sizes is ABI and
5875 architecture dependent, so use them to override the default sizes
5876 set by the ABI. This table shows the relationship between ABI,
5877 -mlongXX, and size of pointers:
5879 ABI -mlongXX ptr bits
5880 --- -------- --------
5894 Note that for o32 and eabi32, pointers are always 32 bits
5895 regardless of any -mlongXX option. For all others, pointers and
5896 longs are the same, as set by -mlongXX or set by defaults.
5899 if (info.abfd != NULL)
5903 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
5906 set_gdbarch_long_bit (gdbarch, long_bit);
5910 case MIPS_ABI_EABI32:
5915 case MIPS_ABI_EABI64:
5916 set_gdbarch_ptr_bit (gdbarch, long_bit);
5919 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5924 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5925 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5928 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5929 flag in object files because to do so would make it impossible to
5930 link with libraries compiled without "-gp32". This is
5931 unnecessarily restrictive.
5933 We could solve this problem by adding "-gp32" multilibs to gcc,
5934 but to set this flag before gcc is built with such multilibs will
5935 break too many systems.''
5937 But even more unhelpfully, the default linker output target for
5938 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5939 for 64-bit programs - you need to change the ABI to change this,
5940 and not all gcc targets support that currently. Therefore using
5941 this flag to detect 32-bit mode would do the wrong thing given
5942 the current gcc - it would make GDB treat these 64-bit programs
5943 as 32-bit programs by default. */
5945 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5946 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5948 /* Add/remove bits from an address. The MIPS needs be careful to
5949 ensure that all 32 bit addresses are sign extended to 64 bits. */
5950 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5952 /* Unwind the frame. */
5953 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5954 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
5955 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
5957 /* Map debug register numbers onto internal register numbers. */
5958 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5959 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5960 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5961 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5962 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5963 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5965 /* MIPS version of CALL_DUMMY */
5967 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5968 replaced by a command, and all targets will default to on stack
5969 (regardless of the stack's execute status). */
5970 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5971 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5973 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
5974 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
5975 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
5977 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5978 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5980 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5982 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
5984 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5985 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5986 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5988 set_gdbarch_register_type (gdbarch, mips_register_type);
5990 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5992 if (mips_abi == MIPS_ABI_N32)
5993 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
5994 else if (mips_abi == MIPS_ABI_N64)
5995 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
5997 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
5999 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6000 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6001 need to all be folded into the target vector. Since they are
6002 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6003 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6005 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
6007 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
6009 set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay);
6011 /* Virtual tables. */
6012 set_gdbarch_vbit_in_delta (gdbarch, 1);
6014 mips_register_g_packet_guesses (gdbarch);
6016 /* Hook in OS ABI-specific overrides, if they have been registered. */
6017 info.tdep_info = (void *) tdesc_data;
6018 gdbarch_init_osabi (info, gdbarch);
6020 /* Unwind the frame. */
6021 dwarf2_append_unwinders (gdbarch);
6022 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
6023 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
6024 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
6025 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
6026 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
6027 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
6028 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
6032 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
6033 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
6035 /* Override the normal target description methods to handle our
6036 dual real and pseudo registers. */
6037 set_gdbarch_register_name (gdbarch, mips_register_name);
6038 set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p);
6040 num_regs = gdbarch_num_regs (gdbarch);
6041 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
6042 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
6043 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
6046 /* Add ABI-specific aliases for the registers. */
6047 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
6048 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
6049 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
6050 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
6052 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
6053 user_reg_add (gdbarch, mips_o32_aliases[i].name,
6054 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
6056 /* Add some other standard aliases. */
6057 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
6058 user_reg_add (gdbarch, mips_register_aliases[i].name,
6059 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
6065 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
6067 struct gdbarch_info info;
6069 /* Force the architecture to update, and (if it's a MIPS architecture)
6070 mips_gdbarch_init will take care of the rest. */
6071 gdbarch_info_init (&info);
6072 gdbarch_update_p (info);
6075 /* Print out which MIPS ABI is in use. */
6078 show_mips_abi (struct ui_file *file,
6080 struct cmd_list_element *ignored_cmd,
6081 const char *ignored_value)
6083 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
6086 "The MIPS ABI is unknown because the current architecture "
6090 enum mips_abi global_abi = global_mips_abi ();
6091 enum mips_abi actual_abi = mips_abi (target_gdbarch);
6092 const char *actual_abi_str = mips_abi_strings[actual_abi];
6094 if (global_abi == MIPS_ABI_UNKNOWN)
6097 "The MIPS ABI is set automatically (currently \"%s\").\n",
6099 else if (global_abi == actual_abi)
6102 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6106 /* Probably shouldn't happen... */
6109 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6110 actual_abi_str, mips_abi_strings[global_abi]);
6116 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
6118 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6122 int ef_mips_32bitmode;
6123 /* Determine the ISA. */
6124 switch (tdep->elf_flags & EF_MIPS_ARCH)
6142 /* Determine the size of a pointer. */
6143 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6144 fprintf_unfiltered (file,
6145 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6147 fprintf_unfiltered (file,
6148 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6150 fprintf_unfiltered (file,
6151 "mips_dump_tdep: ef_mips_arch = %d\n",
6153 fprintf_unfiltered (file,
6154 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6155 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
6156 fprintf_unfiltered (file,
6157 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6158 mips_mask_address_p (tdep),
6159 tdep->default_mask_address_p);
6161 fprintf_unfiltered (file,
6162 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6163 MIPS_DEFAULT_FPU_TYPE,
6164 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6165 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6166 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6168 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
6169 MIPS_EABI (gdbarch));
6170 fprintf_unfiltered (file,
6171 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6172 MIPS_FPU_TYPE (gdbarch),
6173 (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none"
6174 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single"
6175 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double"
6179 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6182 _initialize_mips_tdep (void)
6184 static struct cmd_list_element *mipsfpulist = NULL;
6185 struct cmd_list_element *c;
6187 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
6188 if (MIPS_ABI_LAST + 1
6189 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6190 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
6192 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6194 mips_pdr_data = register_objfile_data ();
6196 /* Create feature sets with the appropriate properties. The values
6197 are not important. */
6198 mips_tdesc_gp32 = allocate_target_description ();
6199 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
6201 mips_tdesc_gp64 = allocate_target_description ();
6202 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
6204 /* Add root prefix command for all "set mips"/"show mips" commands */
6205 add_prefix_cmd ("mips", no_class, set_mips_command,
6206 _("Various MIPS specific commands."),
6207 &setmipscmdlist, "set mips ", 0, &setlist);
6209 add_prefix_cmd ("mips", no_class, show_mips_command,
6210 _("Various MIPS specific commands."),
6211 &showmipscmdlist, "show mips ", 0, &showlist);
6213 /* Allow the user to override the ABI. */
6214 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
6215 &mips_abi_string, _("\
6216 Set the MIPS ABI used by this program."), _("\
6217 Show the MIPS ABI used by this program."), _("\
6218 This option can be set to one of:\n\
6219 auto - the default ABI associated with the current binary\n\
6228 &setmipscmdlist, &showmipscmdlist);
6230 /* Let the user turn off floating point and set the fence post for
6231 heuristic_proc_start. */
6233 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6234 _("Set use of MIPS floating-point coprocessor."),
6235 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6236 add_cmd ("single", class_support, set_mipsfpu_single_command,
6237 _("Select single-precision MIPS floating-point coprocessor."),
6239 add_cmd ("double", class_support, set_mipsfpu_double_command,
6240 _("Select double-precision MIPS floating-point coprocessor."),
6242 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6243 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6244 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6245 add_cmd ("none", class_support, set_mipsfpu_none_command,
6246 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
6247 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6248 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6249 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6250 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6251 _("Select MIPS floating-point coprocessor automatically."),
6253 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6254 _("Show current use of MIPS floating-point coprocessor target."),
6257 /* We really would like to have both "0" and "unlimited" work, but
6258 command.c doesn't deal with that. So make it a var_zinteger
6259 because the user can always use "999999" or some such for unlimited. */
6260 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
6261 &heuristic_fence_post, _("\
6262 Set the distance searched for the start of a function."), _("\
6263 Show the distance searched for the start of a function."), _("\
6264 If you are debugging a stripped executable, GDB needs to search through the\n\
6265 program for the start of a function. This command sets the distance of the\n\
6266 search. The only need to set it is when debugging a stripped executable."),
6267 reinit_frame_cache_sfunc,
6268 NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6269 &setlist, &showlist);
6271 /* Allow the user to control whether the upper bits of 64-bit
6272 addresses should be zeroed. */
6273 add_setshow_auto_boolean_cmd ("mask-address", no_class,
6274 &mask_address_var, _("\
6275 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6276 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6277 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6278 allow GDB to determine the correct value."),
6279 NULL, show_mask_address,
6280 &setmipscmdlist, &showmipscmdlist);
6282 /* Allow the user to control the size of 32 bit registers within the
6283 raw remote packet. */
6284 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6285 &mips64_transfers_32bit_regs_p, _("\
6286 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6288 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6290 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6291 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6292 64 bits for others. Use \"off\" to disable compatibility mode"),
6293 set_mips64_transfers_32bit_regs,
6294 NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6295 &setlist, &showlist);
6297 /* Debug this files internals. */
6298 add_setshow_zinteger_cmd ("mips", class_maintenance,
6300 Set mips debugging."), _("\
6301 Show mips debugging."), _("\
6302 When non-zero, mips specific debugging is enabled."),
6304 NULL, /* FIXME: i18n: Mips debugging is currently %s. */
6305 &setdebuglist, &showdebuglist);