1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
62 static const struct objfile_data *mips_pdr_data;
64 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE = 4,
75 MIPS_FPU_DOUBLE_REGSIZE = 8
84 static const char *mips_abi_string;
86 static const char *mips_abi_strings[] = {
97 /* The standard register names, and all the valid aliases for them. */
104 /* Aliases for o32 and most other ABIs. */
105 const struct register_alias mips_o32_aliases[] = {
112 /* Aliases for n32 and n64. */
113 const struct register_alias mips_n32_n64_aliases[] = {
120 /* Aliases for ABI-independent registers. */
121 const struct register_alias mips_register_aliases[] = {
122 /* The architecture manuals specify these ABI-independent names for
124 #define R(n) { "r" #n, n }
125 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
131 /* k0 and k1 are sometimes called these instead (for "kernel
136 /* This is the traditional GDB name for the CP0 status register. */
137 { "sr", MIPS_PS_REGNUM },
139 /* This is the traditional GDB name for the CP0 BadVAddr register. */
140 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
142 /* This is the traditional GDB name for the FCSR. */
143 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
146 const struct register_alias mips_numeric_register_aliases[] = {
147 #define R(n) { #n, n }
148 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
149 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
150 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
151 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto = 1;
159 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
161 static int mips_debug = 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc *mips_tdesc_gp32;
169 struct target_desc *mips_tdesc_gp64;
171 const struct mips_regnum *
172 mips_regnum (struct gdbarch *gdbarch)
174 return gdbarch_tdep (gdbarch)->regnum;
178 mips_fpa0_regnum (struct gdbarch *gdbarch)
180 return mips_regnum (gdbarch)->fp0 + 12;
183 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
185 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr)
203 unmake_mips16_addr (CORE_ADDR addr)
205 return ((addr) & ~(CORE_ADDR) 1);
208 /* Return the MIPS ABI associated with GDBARCH. */
210 mips_abi (struct gdbarch *gdbarch)
212 return gdbarch_tdep (gdbarch)->mips_abi;
216 mips_isa_regsize (struct gdbarch *gdbarch)
218 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
220 /* If we know how big the registers are, use that size. */
221 if (tdep->register_size_valid_p)
222 return tdep->register_size;
224 /* Fall back to the previous behavior. */
225 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
226 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
229 /* Return the currently configured (or set) saved register size. */
232 mips_abi_regsize (struct gdbarch *gdbarch)
234 switch (mips_abi (gdbarch))
236 case MIPS_ABI_EABI32:
242 case MIPS_ABI_EABI64:
244 case MIPS_ABI_UNKNOWN:
247 internal_error (__FILE__, __LINE__, _("bad switch"));
251 /* Functions for setting and testing a bit in a minimal symbol that
252 marks it as 16-bit function. The MSB of the minimal symbol's
253 "info" field is used for this purpose.
255 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
256 i.e. refers to a 16-bit function, and sets a "special" bit in a
257 minimal symbol to mark it as a 16-bit function
259 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
262 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
264 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
266 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
267 SYMBOL_VALUE_ADDRESS (msym) |= 1;
272 msymbol_is_special (struct minimal_symbol *msym)
274 return MSYMBOL_TARGET_FLAG_1 (msym);
277 /* XFER a value from the big/little/left end of the register.
278 Depending on the size of the value it might occupy the entire
279 register or just part of it. Make an allowance for this, aligning
280 things accordingly. */
283 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
284 int reg_num, int length,
285 enum bfd_endian endian, gdb_byte *in,
286 const gdb_byte *out, int buf_offset)
290 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
291 /* Need to transfer the left or right part of the register, based on
292 the targets byte order. */
296 reg_offset = register_size (gdbarch, reg_num) - length;
298 case BFD_ENDIAN_LITTLE:
301 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
305 internal_error (__FILE__, __LINE__, _("bad switch"));
308 fprintf_unfiltered (gdb_stderr,
309 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310 reg_num, reg_offset, buf_offset, length);
311 if (mips_debug && out != NULL)
314 fprintf_unfiltered (gdb_stdlog, "out ");
315 for (i = 0; i < length; i++)
316 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
319 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
322 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
324 if (mips_debug && in != NULL)
327 fprintf_unfiltered (gdb_stdlog, "in ");
328 for (i = 0; i < length; i++)
329 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
332 fprintf_unfiltered (gdb_stdlog, "\n");
335 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
336 compatiblity mode. A return value of 1 means that we have
337 physical 64-bit registers, but should treat them as 32-bit registers. */
340 mips2_fp_compat (struct frame_info *frame)
342 struct gdbarch *gdbarch = get_frame_arch (frame);
343 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
345 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
349 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
350 in all the places we deal with FP registers. PR gdb/413. */
351 /* Otherwise check the FR bit in the status register - it controls
352 the FP compatiblity mode. If it is clear we are in compatibility
354 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
361 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
363 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
365 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
367 /* The list of available "set mips " and "show mips " commands */
369 static struct cmd_list_element *setmipscmdlist = NULL;
370 static struct cmd_list_element *showmipscmdlist = NULL;
372 /* Integer registers 0 thru 31 are handled explicitly by
373 mips_register_name(). Processor specific registers 32 and above
374 are listed in the following tables. */
377 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
381 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
382 "sr", "lo", "hi", "bad", "cause", "pc",
383 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
384 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
385 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
386 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
387 "fsr", "fir", "" /*"fp" */ , "",
388 "", "", "", "", "", "", "", "",
389 "", "", "", "", "", "", "", "",
392 /* Names of IDT R3041 registers. */
394 static const char *mips_r3041_reg_names[] = {
395 "sr", "lo", "hi", "bad", "cause", "pc",
396 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
397 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
398 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
399 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
400 "fsr", "fir", "", /*"fp" */ "",
401 "", "", "bus", "ccfg", "", "", "", "",
402 "", "", "port", "cmp", "", "", "epc", "prid",
405 /* Names of tx39 registers. */
407 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
408 "sr", "lo", "hi", "bad", "cause", "pc",
409 "", "", "", "", "", "", "", "",
410 "", "", "", "", "", "", "", "",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
414 "", "", "", "", "", "", "", "",
415 "", "", "config", "cache", "debug", "depc", "epc", ""
418 /* Names of IRIX registers. */
419 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
420 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
421 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
422 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
423 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
424 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
428 /* Return the name of the register corresponding to REGNO. */
430 mips_register_name (struct gdbarch *gdbarch, int regno)
432 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
433 /* GPR names for all ABIs other than n32/n64. */
434 static char *mips_gpr_names[] = {
435 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
436 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
437 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
438 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
441 /* GPR names for n32 and n64 ABIs. */
442 static char *mips_n32_n64_gpr_names[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
449 enum mips_abi abi = mips_abi (gdbarch);
451 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
452 but then don't make the raw register names visible. */
453 int rawnum = regno % gdbarch_num_regs (gdbarch);
454 if (regno < gdbarch_num_regs (gdbarch))
457 /* The MIPS integer registers are always mapped from 0 to 31. The
458 names of the registers (which reflects the conventions regarding
459 register use) vary depending on the ABI. */
460 if (0 <= rawnum && rawnum < 32)
462 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
463 return mips_n32_n64_gpr_names[rawnum];
465 return mips_gpr_names[rawnum];
467 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
468 return tdesc_register_name (gdbarch, rawnum);
469 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
471 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
472 return tdep->mips_processor_reg_names[rawnum - 32];
475 internal_error (__FILE__, __LINE__,
476 _("mips_register_name: bad register number %d"), rawnum);
479 /* Return the groups that a MIPS register can be categorised into. */
482 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
483 struct reggroup *reggroup)
488 int rawnum = regnum % gdbarch_num_regs (gdbarch);
489 int pseudo = regnum / gdbarch_num_regs (gdbarch);
490 if (reggroup == all_reggroup)
492 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
493 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
494 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
495 (gdbarch), as not all architectures are multi-arch. */
496 raw_p = rawnum < gdbarch_num_regs (gdbarch);
497 if (gdbarch_register_name (gdbarch, regnum) == NULL
498 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
500 if (reggroup == float_reggroup)
501 return float_p && pseudo;
502 if (reggroup == vector_reggroup)
503 return vector_p && pseudo;
504 if (reggroup == general_reggroup)
505 return (!vector_p && !float_p) && pseudo;
506 /* Save the pseudo registers. Need to make certain that any code
507 extracting register values from a saved register cache also uses
509 if (reggroup == save_reggroup)
510 return raw_p && pseudo;
511 /* Restore the same pseudo register. */
512 if (reggroup == restore_reggroup)
513 return raw_p && pseudo;
517 /* Return the groups that a MIPS register can be categorised into.
518 This version is only used if we have a target description which
519 describes real registers (and their groups). */
522 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
523 struct reggroup *reggroup)
525 int rawnum = regnum % gdbarch_num_regs (gdbarch);
526 int pseudo = regnum / gdbarch_num_regs (gdbarch);
529 /* Only save, restore, and display the pseudo registers. Need to
530 make certain that any code extracting register values from a
531 saved register cache also uses pseudo registers.
533 Note: saving and restoring the pseudo registers is slightly
534 strange; if we have 64 bits, we should save and restore all
535 64 bits. But this is hard and has little benefit. */
539 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
543 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
546 /* Map the symbol table registers which live in the range [1 *
547 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
548 registers. Take care of alignment and size problems. */
551 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
552 int cookednum, gdb_byte *buf)
554 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
555 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
556 && cookednum < 2 * gdbarch_num_regs (gdbarch));
557 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
558 regcache_raw_read (regcache, rawnum, buf);
559 else if (register_size (gdbarch, rawnum) >
560 register_size (gdbarch, cookednum))
562 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
563 || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
564 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
566 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
569 internal_error (__FILE__, __LINE__, _("bad register size"));
573 mips_pseudo_register_write (struct gdbarch *gdbarch,
574 struct regcache *regcache, int cookednum,
577 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
578 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
579 && cookednum < 2 * gdbarch_num_regs (gdbarch));
580 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
581 regcache_raw_write (regcache, rawnum, buf);
582 else if (register_size (gdbarch, rawnum) >
583 register_size (gdbarch, cookednum))
585 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
586 || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
587 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
589 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
592 internal_error (__FILE__, __LINE__, _("bad register size"));
595 /* Table to translate MIPS16 register field to actual register number. */
596 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
598 /* Heuristic_proc_start may hunt through the text section for a long
599 time across a 2400 baud serial line. Allows the user to limit this
602 static unsigned int heuristic_fence_post = 0;
604 /* Number of bytes of storage in the actual machine representation for
605 register N. NOTE: This defines the pseudo register type so need to
606 rebuild the architecture vector. */
608 static int mips64_transfers_32bit_regs_p = 0;
611 set_mips64_transfers_32bit_regs (char *args, int from_tty,
612 struct cmd_list_element *c)
614 struct gdbarch_info info;
615 gdbarch_info_init (&info);
616 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
617 instead of relying on globals. Doing that would let generic code
618 handle the search for this specific architecture. */
619 if (!gdbarch_update_p (info))
621 mips64_transfers_32bit_regs_p = 0;
622 error (_("32-bit compatibility mode not supported"));
626 /* Convert to/from a register and the corresponding memory value. */
629 mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
631 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
632 && register_size (gdbarch, regnum) == 4
633 && (regnum % gdbarch_num_regs (gdbarch))
634 >= mips_regnum (gdbarch)->fp0
635 && (regnum % gdbarch_num_regs (gdbarch))
636 < mips_regnum (gdbarch)->fp0 + 32
637 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
641 mips_register_to_value (struct frame_info *frame, int regnum,
642 struct type *type, gdb_byte *to)
644 get_frame_register (frame, regnum + 0, to + 4);
645 get_frame_register (frame, regnum + 1, to + 0);
649 mips_value_to_register (struct frame_info *frame, int regnum,
650 struct type *type, const gdb_byte *from)
652 put_frame_register (frame, regnum + 0, from + 4);
653 put_frame_register (frame, regnum + 1, from + 0);
656 /* Return the GDB type object for the "standard" data type of data in
660 mips_register_type (struct gdbarch *gdbarch, int regnum)
662 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
663 if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0
664 && (regnum % gdbarch_num_regs (gdbarch))
665 < mips_regnum (gdbarch)->fp0 + 32)
667 /* The floating-point registers raw, or cooked, always match
668 mips_isa_regsize(), and also map 1:1, byte for byte. */
669 if (mips_isa_regsize (gdbarch) == 4)
670 return builtin_type (gdbarch)->builtin_float;
672 return builtin_type (gdbarch)->builtin_double;
674 else if (regnum < gdbarch_num_regs (gdbarch))
676 /* The raw or ISA registers. These are all sized according to
678 if (mips_isa_regsize (gdbarch) == 4)
679 return builtin_type (gdbarch)->builtin_int32;
681 return builtin_type (gdbarch)->builtin_int64;
685 /* The cooked or ABI registers. These are sized according to
686 the ABI (with a few complications). */
687 if (regnum >= (gdbarch_num_regs (gdbarch)
688 + mips_regnum (gdbarch)->fp_control_status)
689 && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM)
690 /* The pseudo/cooked view of the embedded registers is always
691 32-bit. The raw view is handled below. */
692 return builtin_type (gdbarch)->builtin_int32;
693 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
694 /* The target, while possibly using a 64-bit register buffer,
695 is only transfering 32-bits of each integer register.
696 Reflect this in the cooked/pseudo (ABI) register value. */
697 return builtin_type (gdbarch)->builtin_int32;
698 else if (mips_abi_regsize (gdbarch) == 4)
699 /* The ABI is restricted to 32-bit registers (the ISA could be
701 return builtin_type (gdbarch)->builtin_int32;
704 return builtin_type (gdbarch)->builtin_int64;
708 /* Return the GDB type for the pseudo register REGNUM, which is the
709 ABI-level view. This function is only called if there is a target
710 description which includes registers, so we know precisely the
711 types of hardware registers. */
714 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
716 const int num_regs = gdbarch_num_regs (gdbarch);
717 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
718 int rawnum = regnum % num_regs;
719 struct type *rawtype;
721 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
723 /* Absent registers are still absent. */
724 rawtype = gdbarch_register_type (gdbarch, rawnum);
725 if (TYPE_LENGTH (rawtype) == 0)
728 if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32)
729 /* Present the floating point registers however the hardware did;
730 do not try to convert between FPU layouts. */
733 if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM)
735 /* The pseudo/cooked view of embedded registers is always
736 32-bit, even if the target transfers 64-bit values for them.
737 New targets relying on XML descriptions should only transfer
738 the necessary 32 bits, but older versions of GDB expected 64,
739 so allow the target to provide 64 bits without interfering
740 with the displayed type. */
741 return builtin_type (gdbarch)->builtin_int32;
744 /* Use pointer types for registers if we can. For n32 we can not,
745 since we do not have a 64-bit pointer type. */
746 if (mips_abi_regsize (gdbarch)
747 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
749 if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM)
750 return builtin_type (gdbarch)->builtin_data_ptr;
751 else if (rawnum == MIPS_EMBED_PC_REGNUM)
752 return builtin_type (gdbarch)->builtin_func_ptr;
755 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
756 && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM)
757 return builtin_type (gdbarch)->builtin_int32;
759 /* For all other registers, pass through the hardware type. */
763 /* Should the upper word of 64-bit addresses be zeroed? */
764 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
767 mips_mask_address_p (struct gdbarch_tdep *tdep)
769 switch (mask_address_var)
771 case AUTO_BOOLEAN_TRUE:
773 case AUTO_BOOLEAN_FALSE:
776 case AUTO_BOOLEAN_AUTO:
777 return tdep->default_mask_address_p;
779 internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch"));
785 show_mask_address (struct ui_file *file, int from_tty,
786 struct cmd_list_element *c, const char *value)
788 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
790 deprecated_show_value_hack (file, from_tty, c, value);
791 switch (mask_address_var)
793 case AUTO_BOOLEAN_TRUE:
794 printf_filtered ("The 32 bit mips address mask is enabled\n");
796 case AUTO_BOOLEAN_FALSE:
797 printf_filtered ("The 32 bit mips address mask is disabled\n");
799 case AUTO_BOOLEAN_AUTO:
801 ("The 32 bit address mask is set automatically. Currently %s\n",
802 mips_mask_address_p (tdep) ? "enabled" : "disabled");
805 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
810 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
813 mips_pc_is_mips16 (CORE_ADDR memaddr)
815 struct minimal_symbol *sym;
817 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
818 if (is_mips16_addr (memaddr))
821 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
822 the high bit of the info field. Use this to decide if the function is
823 MIPS16 or normal MIPS. */
824 sym = lookup_minimal_symbol_by_pc (memaddr);
826 return msymbol_is_special (sym);
831 /* MIPS believes that the PC has a sign extended value. Perhaps the
832 all registers should be sign extended for simplicity? */
835 mips_read_pc (struct regcache *regcache)
838 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
839 regcache_cooked_read_signed (regcache, regnum, &pc);
844 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
846 return frame_unwind_register_signed
847 (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc);
851 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
853 return frame_unwind_register_signed
854 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
857 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
858 dummy frame. The frame ID's base needs to match the TOS value
859 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
862 static struct frame_id
863 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
865 return frame_id_build
866 (get_frame_register_signed (this_frame,
867 gdbarch_num_regs (gdbarch)
869 get_frame_pc (this_frame));
873 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
875 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
876 regcache_cooked_write_unsigned (regcache, regnum, pc);
879 /* Fetch and return instruction from the specified location. If the PC
880 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
883 mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr)
885 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
886 gdb_byte buf[MIPS_INSN32_SIZE];
890 if (mips_pc_is_mips16 (addr))
892 instlen = MIPS_INSN16_SIZE;
893 addr = unmake_mips16_addr (addr);
896 instlen = MIPS_INSN32_SIZE;
897 status = target_read_memory (addr, buf, instlen);
899 memory_error (status, addr);
900 return extract_unsigned_integer (buf, instlen, byte_order);
903 /* These the fields of 32 bit mips instructions */
904 #define mips32_op(x) (x >> 26)
905 #define itype_op(x) (x >> 26)
906 #define itype_rs(x) ((x >> 21) & 0x1f)
907 #define itype_rt(x) ((x >> 16) & 0x1f)
908 #define itype_immediate(x) (x & 0xffff)
910 #define jtype_op(x) (x >> 26)
911 #define jtype_target(x) (x & 0x03ffffff)
913 #define rtype_op(x) (x >> 26)
914 #define rtype_rs(x) ((x >> 21) & 0x1f)
915 #define rtype_rt(x) ((x >> 16) & 0x1f)
916 #define rtype_rd(x) ((x >> 11) & 0x1f)
917 #define rtype_shamt(x) ((x >> 6) & 0x1f)
918 #define rtype_funct(x) (x & 0x3f)
921 mips32_relative_offset (ULONGEST inst)
923 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
926 /* Determine where to set a single step breakpoint while considering
927 branch prediction. */
929 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
931 struct gdbarch *gdbarch = get_frame_arch (frame);
934 inst = mips_fetch_instruction (gdbarch, pc);
935 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
937 if (itype_op (inst) >> 2 == 5)
938 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
940 op = (itype_op (inst) & 0x03);
955 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
956 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
958 int tf = itype_rt (inst) & 0x01;
959 int cnum = itype_rt (inst) >> 2;
961 get_frame_register_signed (frame,
962 mips_regnum (get_frame_arch (frame))->
964 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
966 if (((cond >> cnum) & 0x01) == tf)
967 pc += mips32_relative_offset (inst) + 4;
972 pc += 4; /* Not a branch, next instruction is easy */
975 { /* This gets way messy */
977 /* Further subdivide into SPECIAL, REGIMM and other */
978 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
980 case 0: /* SPECIAL */
981 op = rtype_funct (inst);
986 /* Set PC to that address */
987 pc = get_frame_register_signed (frame, rtype_rs (inst));
989 case 12: /* SYSCALL */
991 struct gdbarch_tdep *tdep;
993 tdep = gdbarch_tdep (get_frame_arch (frame));
994 if (tdep->syscall_next_pc != NULL)
995 pc = tdep->syscall_next_pc (frame);
1004 break; /* end SPECIAL */
1005 case 1: /* REGIMM */
1007 op = itype_rt (inst); /* branch condition */
1012 case 16: /* BLTZAL */
1013 case 18: /* BLTZALL */
1015 if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1016 pc += mips32_relative_offset (inst) + 4;
1018 pc += 8; /* after the delay slot */
1022 case 17: /* BGEZAL */
1023 case 19: /* BGEZALL */
1024 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1025 pc += mips32_relative_offset (inst) + 4;
1027 pc += 8; /* after the delay slot */
1029 /* All of the other instructions in the REGIMM category */
1034 break; /* end REGIMM */
1039 reg = jtype_target (inst) << 2;
1040 /* Upper four bits get never changed... */
1041 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1044 /* FIXME case JALX : */
1047 reg = jtype_target (inst) << 2;
1048 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */
1049 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1051 break; /* The new PC will be alternate mode */
1052 case 4: /* BEQ, BEQL */
1054 if (get_frame_register_signed (frame, itype_rs (inst)) ==
1055 get_frame_register_signed (frame, itype_rt (inst)))
1056 pc += mips32_relative_offset (inst) + 4;
1060 case 5: /* BNE, BNEL */
1062 if (get_frame_register_signed (frame, itype_rs (inst)) !=
1063 get_frame_register_signed (frame, itype_rt (inst)))
1064 pc += mips32_relative_offset (inst) + 4;
1068 case 6: /* BLEZ, BLEZL */
1069 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1070 pc += mips32_relative_offset (inst) + 4;
1076 greater_branch: /* BGTZ, BGTZL */
1077 if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1078 pc += mips32_relative_offset (inst) + 4;
1085 } /* mips32_next_pc */
1087 /* Decoding the next place to set a breakpoint is irregular for the
1088 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1089 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1090 We dont want to set a single step instruction on the extend instruction
1094 /* Lots of mips16 instruction formats */
1095 /* Predicting jumps requires itype,ritype,i8type
1096 and their extensions extItype,extritype,extI8type
1098 enum mips16_inst_fmts
1100 itype, /* 0 immediate 5,10 */
1101 ritype, /* 1 5,3,8 */
1102 rrtype, /* 2 5,3,3,5 */
1103 rritype, /* 3 5,3,3,5 */
1104 rrrtype, /* 4 5,3,3,3,2 */
1105 rriatype, /* 5 5,3,3,1,4 */
1106 shifttype, /* 6 5,3,3,3,2 */
1107 i8type, /* 7 5,3,8 */
1108 i8movtype, /* 8 5,3,3,5 */
1109 i8mov32rtype, /* 9 5,3,5,3 */
1110 i64type, /* 10 5,3,8 */
1111 ri64type, /* 11 5,3,3,5 */
1112 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1113 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1114 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1115 extRRItype, /* 15 5,5,5,5,3,3,5 */
1116 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1117 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1118 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1119 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1120 extRi64type, /* 20 5,6,5,5,3,3,5 */
1121 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1123 /* I am heaping all the fields of the formats into one structure and
1124 then, only the fields which are involved in instruction extension */
1128 unsigned int regx; /* Function in i8 type */
1133 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1134 for the bits which make up the immediate extension. */
1137 extended_offset (unsigned int extension)
1140 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1142 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1144 value |= extension & 0x01f; /* extract 4:0 */
1148 /* Only call this function if you know that this is an extendable
1149 instruction. It won't malfunction, but why make excess remote memory
1150 references? If the immediate operands get sign extended or something,
1151 do it after the extension is performed. */
1152 /* FIXME: Every one of these cases needs to worry about sign extension
1153 when the offset is to be used in relative addressing. */
1156 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc)
1158 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1160 pc &= 0xfffffffe; /* clear the low order bit */
1161 target_read_memory (pc, buf, 2);
1162 return extract_unsigned_integer (buf, 2, byte_order);
1166 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc,
1167 unsigned int extension,
1169 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1174 switch (insn_format)
1181 value = extended_offset (extension);
1182 value = value << 11; /* rom for the original value */
1183 value |= inst & 0x7ff; /* eleven bits from instruction */
1187 value = inst & 0x7ff;
1188 /* FIXME : Consider sign extension */
1197 { /* A register identifier and an offset */
1198 /* Most of the fields are the same as I type but the
1199 immediate value is of a different length */
1203 value = extended_offset (extension);
1204 value = value << 8; /* from the original instruction */
1205 value |= inst & 0xff; /* eleven bits from instruction */
1206 regx = (extension >> 8) & 0x07; /* or i8 funct */
1207 if (value & 0x4000) /* test the sign bit , bit 26 */
1209 value &= ~0x3fff; /* remove the sign bit */
1215 value = inst & 0xff; /* 8 bits */
1216 regx = (inst >> 8) & 0x07; /* or i8 funct */
1217 /* FIXME: Do sign extension , this format needs it */
1218 if (value & 0x80) /* THIS CONFUSES ME */
1220 value &= 0xef; /* remove the sign bit */
1230 unsigned long value;
1231 unsigned int nexthalf;
1232 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1233 value = value << 16;
1234 nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit still set */
1242 internal_error (__FILE__, __LINE__, _("bad switch"));
1244 upk->offset = offset;
1251 add_offset_16 (CORE_ADDR pc, int offset)
1253 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
1257 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
1258 unsigned int extension, unsigned int insn)
1260 struct gdbarch *gdbarch = get_frame_arch (frame);
1261 int op = (insn >> 11);
1264 case 2: /* Branch */
1267 struct upk_mips16 upk;
1268 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk);
1269 offset = upk.offset;
1275 pc += (offset << 1) + 2;
1278 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1280 struct upk_mips16 upk;
1281 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk);
1282 pc = add_offset_16 (pc, upk.offset);
1283 if ((insn >> 10) & 0x01) /* Exchange mode */
1284 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1291 struct upk_mips16 upk;
1293 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
1294 reg = get_frame_register_signed (frame, upk.regx);
1296 pc += (upk.offset << 1) + 2;
1303 struct upk_mips16 upk;
1305 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
1306 reg = get_frame_register_signed (frame, upk.regx);
1308 pc += (upk.offset << 1) + 2;
1313 case 12: /* I8 Formats btez btnez */
1315 struct upk_mips16 upk;
1317 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
1318 /* upk.regx contains the opcode */
1319 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
1320 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1321 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1322 /* pc = add_offset_16(pc,upk.offset) ; */
1323 pc += (upk.offset << 1) + 2;
1328 case 29: /* RR Formats JR, JALR, JALR-RA */
1330 struct upk_mips16 upk;
1331 /* upk.fmt = rrtype; */
1336 upk.regx = (insn >> 8) & 0x07;
1337 upk.regy = (insn >> 5) & 0x07;
1345 break; /* Function return instruction */
1351 break; /* BOGUS Guess */
1353 pc = get_frame_register_signed (frame, reg);
1360 /* This is an instruction extension. Fetch the real instruction
1361 (which follows the extension) and decode things based on
1365 pc = extended_mips16_next_pc (frame, pc, insn,
1366 fetch_mips_16 (gdbarch, pc));
1379 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
1381 struct gdbarch *gdbarch = get_frame_arch (frame);
1382 unsigned int insn = fetch_mips_16 (gdbarch, pc);
1383 return extended_mips16_next_pc (frame, pc, 0, insn);
1386 /* The mips_next_pc function supports single_step when the remote
1387 target monitor or stub is not developed enough to do a single_step.
1388 It works by decoding the current instruction and predicting where a
1389 branch will go. This isnt hard because all the data is available.
1390 The MIPS32 and MIPS16 variants are quite different. */
1392 mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1394 if (is_mips16_addr (pc))
1395 return mips16_next_pc (frame, pc);
1397 return mips32_next_pc (frame, pc);
1400 struct mips_frame_cache
1403 struct trad_frame_saved_reg *saved_regs;
1406 /* Set a register's saved stack address in temp_saved_regs. If an
1407 address has already been set for this register, do nothing; this
1408 way we will only recognize the first save of a given register in a
1411 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1412 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1413 Strictly speaking, only the second range is used as it is only second
1414 range (the ABI instead of ISA registers) that comes into play when finding
1415 saved registers in a frame. */
1418 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
1419 int regnum, CORE_ADDR offset)
1421 if (this_cache != NULL
1422 && this_cache->saved_regs[regnum].addr == -1)
1424 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
1426 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
1432 /* Fetch the immediate value from a MIPS16 instruction.
1433 If the previous instruction was an EXTEND, use it to extend
1434 the upper bits of the immediate value. This is a helper function
1435 for mips16_scan_prologue. */
1438 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1439 unsigned short inst, /* current instruction */
1440 int nbits, /* number of bits in imm field */
1441 int scale, /* scale factor to be applied to imm */
1442 int is_signed) /* is the imm field signed? */
1446 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1448 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1449 if (offset & 0x8000) /* check for negative extend */
1450 offset = 0 - (0x10000 - (offset & 0xffff));
1451 return offset | (inst & 0x1f);
1455 int max_imm = 1 << nbits;
1456 int mask = max_imm - 1;
1457 int sign_bit = max_imm >> 1;
1459 offset = inst & mask;
1460 if (is_signed && (offset & sign_bit))
1461 offset = 0 - (max_imm - offset);
1462 return offset * scale;
1467 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1468 the associated FRAME_CACHE if not null.
1469 Return the address of the first instruction past the prologue. */
1472 mips16_scan_prologue (struct gdbarch *gdbarch,
1473 CORE_ADDR start_pc, CORE_ADDR limit_pc,
1474 struct frame_info *this_frame,
1475 struct mips_frame_cache *this_cache)
1478 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1480 long frame_offset = 0; /* Size of stack frame. */
1481 long frame_adjust = 0; /* Offset of FP from SP. */
1482 int frame_reg = MIPS_SP_REGNUM;
1483 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1484 unsigned inst = 0; /* current instruction */
1485 unsigned entry_inst = 0; /* the entry instruction */
1486 unsigned save_inst = 0; /* the save instruction */
1489 int extend_bytes = 0;
1490 int prev_extend_bytes;
1491 CORE_ADDR end_prologue_addr = 0;
1493 /* Can be called when there's no process, and hence when there's no
1495 if (this_frame != NULL)
1496 sp = get_frame_register_signed (this_frame,
1497 gdbarch_num_regs (gdbarch)
1502 if (limit_pc > start_pc + 200)
1503 limit_pc = start_pc + 200;
1505 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
1507 /* Save the previous instruction. If it's an EXTEND, we'll extract
1508 the immediate offset extension from it in mips16_get_imm. */
1511 /* Fetch and decode the instruction. */
1512 inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc);
1514 /* Normally we ignore extend instructions. However, if it is
1515 not followed by a valid prologue instruction, then this
1516 instruction is not part of the prologue either. We must
1517 remember in this case to adjust the end_prologue_addr back
1519 if ((inst & 0xf800) == 0xf000) /* extend */
1521 extend_bytes = MIPS_INSN16_SIZE;
1525 prev_extend_bytes = extend_bytes;
1528 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1529 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1531 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1532 if (offset < 0) /* negative stack adjustment? */
1533 frame_offset -= offset;
1535 /* Exit loop if a positive stack adjustment is found, which
1536 usually means that the stack cleanup code in the function
1537 epilogue is reached. */
1540 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1542 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1543 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1544 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1546 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1548 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1549 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1550 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1552 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1554 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1555 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1557 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1559 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1560 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1562 else if (inst == 0x673d) /* move $s1, $sp */
1567 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1569 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1570 frame_addr = sp + offset;
1572 frame_adjust = offset;
1574 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1576 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1577 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1578 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
1580 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1582 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1583 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1584 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
1586 else if ((inst & 0xf81f) == 0xe809
1587 && (inst & 0x700) != 0x700) /* entry */
1588 entry_inst = inst; /* save for later processing */
1589 else if ((inst & 0xff80) == 0x6480) /* save */
1591 save_inst = inst; /* save for later processing */
1592 if (prev_extend_bytes) /* extend */
1593 save_inst |= prev_inst << 16;
1595 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1596 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
1597 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1599 /* This instruction is part of the prologue, but we don't
1600 need to do anything special to handle it. */
1604 /* This instruction is not an instruction typically found
1605 in a prologue, so we must have reached the end of the
1607 if (end_prologue_addr == 0)
1608 end_prologue_addr = cur_pc - prev_extend_bytes;
1612 /* The entry instruction is typically the first instruction in a function,
1613 and it stores registers at offsets relative to the value of the old SP
1614 (before the prologue). But the value of the sp parameter to this
1615 function is the new SP (after the prologue has been executed). So we
1616 can't calculate those offsets until we've seen the entire prologue,
1617 and can calculate what the old SP must have been. */
1618 if (entry_inst != 0)
1620 int areg_count = (entry_inst >> 8) & 7;
1621 int sreg_count = (entry_inst >> 6) & 3;
1623 /* The entry instruction always subtracts 32 from the SP. */
1626 /* Now we can calculate what the SP must have been at the
1627 start of the function prologue. */
1630 /* Check if a0-a3 were saved in the caller's argument save area. */
1631 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1633 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1634 offset += mips_abi_regsize (gdbarch);
1637 /* Check if the ra register was pushed on the stack. */
1639 if (entry_inst & 0x20)
1641 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1642 offset -= mips_abi_regsize (gdbarch);
1645 /* Check if the s0 and s1 registers were pushed on the stack. */
1646 for (reg = 16; reg < sreg_count + 16; reg++)
1648 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1649 offset -= mips_abi_regsize (gdbarch);
1653 /* The SAVE instruction is similar to ENTRY, except that defined by the
1654 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1655 size of the frame is specified as an immediate field of instruction
1656 and an extended variation exists which lets additional registers and
1657 frame space to be specified. The instruction always treats registers
1658 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1659 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
1661 static int args_table[16] = {
1662 0, 0, 0, 0, 1, 1, 1, 1,
1663 2, 2, 2, 0, 3, 3, 4, -1,
1665 static int astatic_table[16] = {
1666 0, 1, 2, 3, 0, 1, 2, 3,
1667 0, 1, 2, 4, 0, 1, 0, -1,
1669 int aregs = (save_inst >> 16) & 0xf;
1670 int xsregs = (save_inst >> 24) & 0x7;
1671 int args = args_table[aregs];
1672 int astatic = astatic_table[aregs];
1677 warning (_("Invalid number of argument registers encoded in SAVE."));
1682 warning (_("Invalid number of static registers encoded in SAVE."));
1686 /* For standard SAVE the frame size of 0 means 128. */
1687 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
1688 if (frame_size == 0 && (save_inst >> 16) == 0)
1691 frame_offset += frame_size;
1693 /* Now we can calculate what the SP must have been at the
1694 start of the function prologue. */
1697 /* Check if A0-A3 were saved in the caller's argument save area. */
1698 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
1700 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1701 offset += mips_abi_regsize (gdbarch);
1706 /* Check if the RA register was pushed on the stack. */
1707 if (save_inst & 0x40)
1709 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1710 offset -= mips_abi_regsize (gdbarch);
1713 /* Check if the S8 register was pushed on the stack. */
1716 set_reg_offset (gdbarch, this_cache, 30, sp + offset);
1717 offset -= mips_abi_regsize (gdbarch);
1720 /* Check if S2-S7 were pushed on the stack. */
1721 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
1723 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1724 offset -= mips_abi_regsize (gdbarch);
1727 /* Check if the S1 register was pushed on the stack. */
1728 if (save_inst & 0x10)
1730 set_reg_offset (gdbarch, this_cache, 17, sp + offset);
1731 offset -= mips_abi_regsize (gdbarch);
1733 /* Check if the S0 register was pushed on the stack. */
1734 if (save_inst & 0x20)
1736 set_reg_offset (gdbarch, this_cache, 16, sp + offset);
1737 offset -= mips_abi_regsize (gdbarch);
1740 /* Check if A0-A3 were pushed on the stack. */
1741 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
1743 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1744 offset -= mips_abi_regsize (gdbarch);
1748 if (this_cache != NULL)
1751 (get_frame_register_signed (this_frame,
1752 gdbarch_num_regs (gdbarch) + frame_reg)
1753 + frame_offset - frame_adjust);
1754 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1755 be able to get rid of the assignment below, evetually. But it's
1756 still needed for now. */
1757 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
1758 + mips_regnum (gdbarch)->pc]
1759 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
1762 /* If we didn't reach the end of the prologue when scanning the function
1763 instructions, then set end_prologue_addr to the address of the
1764 instruction immediately after the last one we scanned. */
1765 if (end_prologue_addr == 0)
1766 end_prologue_addr = cur_pc;
1768 return end_prologue_addr;
1771 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1772 Procedures that use the 32-bit instruction set are handled by the
1773 mips_insn32 unwinder. */
1775 static struct mips_frame_cache *
1776 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
1778 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1779 struct mips_frame_cache *cache;
1781 if ((*this_cache) != NULL)
1782 return (*this_cache);
1783 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1784 (*this_cache) = cache;
1785 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1787 /* Analyze the function prologue. */
1789 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
1790 CORE_ADDR start_addr;
1792 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1793 if (start_addr == 0)
1794 start_addr = heuristic_proc_start (gdbarch, pc);
1795 /* We can't analyze the prologue if we couldn't find the begining
1797 if (start_addr == 0)
1800 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
1803 /* gdbarch_sp_regnum contains the value and not the address. */
1804 trad_frame_set_value (cache->saved_regs,
1805 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
1808 return (*this_cache);
1812 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
1813 struct frame_id *this_id)
1815 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1817 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
1820 static struct value *
1821 mips_insn16_frame_prev_register (struct frame_info *this_frame,
1822 void **this_cache, int regnum)
1824 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1826 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1830 mips_insn16_frame_sniffer (const struct frame_unwind *self,
1831 struct frame_info *this_frame, void **this_cache)
1833 CORE_ADDR pc = get_frame_pc (this_frame);
1834 if (mips_pc_is_mips16 (pc))
1839 static const struct frame_unwind mips_insn16_frame_unwind =
1842 mips_insn16_frame_this_id,
1843 mips_insn16_frame_prev_register,
1845 mips_insn16_frame_sniffer
1849 mips_insn16_frame_base_address (struct frame_info *this_frame,
1852 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1857 static const struct frame_base mips_insn16_frame_base =
1859 &mips_insn16_frame_unwind,
1860 mips_insn16_frame_base_address,
1861 mips_insn16_frame_base_address,
1862 mips_insn16_frame_base_address
1865 static const struct frame_base *
1866 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
1868 CORE_ADDR pc = get_frame_pc (this_frame);
1869 if (mips_pc_is_mips16 (pc))
1870 return &mips_insn16_frame_base;
1875 /* Mark all the registers as unset in the saved_regs array
1876 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1879 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
1881 if (this_cache == NULL || this_cache->saved_regs == NULL)
1885 const int num_regs = gdbarch_num_regs (gdbarch);
1888 for (i = 0; i < num_regs; i++)
1890 this_cache->saved_regs[i].addr = -1;
1895 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1896 the associated FRAME_CACHE if not null.
1897 Return the address of the first instruction past the prologue. */
1900 mips32_scan_prologue (struct gdbarch *gdbarch,
1901 CORE_ADDR start_pc, CORE_ADDR limit_pc,
1902 struct frame_info *this_frame,
1903 struct mips_frame_cache *this_cache)
1906 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1909 int frame_reg = MIPS_SP_REGNUM;
1911 CORE_ADDR end_prologue_addr = 0;
1912 int seen_sp_adjust = 0;
1913 int load_immediate_bytes = 0;
1914 int in_delay_slot = 0;
1915 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
1917 /* Can be called when there's no process, and hence when there's no
1919 if (this_frame != NULL)
1920 sp = get_frame_register_signed (this_frame,
1921 gdbarch_num_regs (gdbarch)
1926 if (limit_pc > start_pc + 200)
1927 limit_pc = start_pc + 200;
1932 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
1934 unsigned long inst, high_word, low_word;
1937 /* Fetch the instruction. */
1938 inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc);
1940 /* Save some code by pre-extracting some useful fields. */
1941 high_word = (inst >> 16) & 0xffff;
1942 low_word = inst & 0xffff;
1943 reg = high_word & 0x1f;
1945 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1946 || high_word == 0x23bd /* addi $sp,$sp,-i */
1947 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1949 if (low_word & 0x8000) /* negative stack adjustment? */
1950 frame_offset += 0x10000 - low_word;
1952 /* Exit loop if a positive stack adjustment is found, which
1953 usually means that the stack cleanup code in the function
1954 epilogue is reached. */
1958 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1959 && !regsize_is_64_bits)
1961 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
1963 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1964 && regsize_is_64_bits)
1966 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1967 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
1969 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1971 /* Old gcc frame, r30 is virtual frame pointer. */
1972 if ((long) low_word != frame_offset)
1973 frame_addr = sp + low_word;
1974 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
1976 unsigned alloca_adjust;
1979 frame_addr = get_frame_register_signed
1980 (this_frame, gdbarch_num_regs (gdbarch) + 30);
1982 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1983 if (alloca_adjust > 0)
1985 /* FP > SP + frame_size. This may be because of
1986 an alloca or somethings similar. Fix sp to
1987 "pre-alloca" value, and try again. */
1988 sp += alloca_adjust;
1989 /* Need to reset the status of all registers. Otherwise,
1990 we will hit a guard that prevents the new address
1991 for each register to be recomputed during the second
1993 reset_saved_regs (gdbarch, this_cache);
1998 /* move $30,$sp. With different versions of gas this will be either
1999 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2000 Accept any one of these. */
2001 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2003 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2004 if (this_frame && frame_reg == MIPS_SP_REGNUM)
2006 unsigned alloca_adjust;
2009 frame_addr = get_frame_register_signed
2010 (this_frame, gdbarch_num_regs (gdbarch) + 30);
2012 alloca_adjust = (unsigned) (frame_addr - sp);
2013 if (alloca_adjust > 0)
2015 /* FP > SP + frame_size. This may be because of
2016 an alloca or somethings similar. Fix sp to
2017 "pre-alloca" value, and try again. */
2019 /* Need to reset the status of all registers. Otherwise,
2020 we will hit a guard that prevents the new address
2021 for each register to be recomputed during the second
2023 reset_saved_regs (gdbarch, this_cache);
2028 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2029 && !regsize_is_64_bits)
2031 set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word);
2033 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2034 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2035 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2036 || high_word == 0x3c1c /* lui $gp,n */
2037 || high_word == 0x279c /* addiu $gp,$gp,n */
2038 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
2039 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
2042 /* These instructions are part of the prologue, but we don't
2043 need to do anything special to handle them. */
2045 /* The instructions below load $at or $t0 with an immediate
2046 value in preparation for a stack adjustment via
2047 subu $sp,$sp,[$at,$t0]. These instructions could also
2048 initialize a local variable, so we accept them only before
2049 a stack adjustment instruction was seen. */
2050 else if (!seen_sp_adjust
2051 && (high_word == 0x3c01 /* lui $at,n */
2052 || high_word == 0x3c08 /* lui $t0,n */
2053 || high_word == 0x3421 /* ori $at,$at,n */
2054 || high_word == 0x3508 /* ori $t0,$t0,n */
2055 || high_word == 0x3401 /* ori $at,$zero,n */
2056 || high_word == 0x3408 /* ori $t0,$zero,n */
2059 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
2063 /* This instruction is not an instruction typically found
2064 in a prologue, so we must have reached the end of the
2066 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2067 loop now? Why would we need to continue scanning the function
2069 if (end_prologue_addr == 0)
2070 end_prologue_addr = cur_pc;
2072 /* Check for branches and jumps. For now, only jump to
2073 register are caught (i.e. returns). */
2074 if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8)
2078 /* If the previous instruction was a jump, we must have reached
2079 the end of the prologue by now. Stop scanning so that we do
2080 not go past the function return. */
2085 if (this_cache != NULL)
2088 (get_frame_register_signed (this_frame,
2089 gdbarch_num_regs (gdbarch) + frame_reg)
2091 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2092 this assignment below, eventually. But it's still needed
2094 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2095 + mips_regnum (gdbarch)->pc]
2096 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2100 /* If we didn't reach the end of the prologue when scanning the function
2101 instructions, then set end_prologue_addr to the address of the
2102 instruction immediately after the last one we scanned. */
2103 /* brobecker/2004-10-10: I don't think this would ever happen, but
2104 we may as well be careful and do our best if we have a null
2105 end_prologue_addr. */
2106 if (end_prologue_addr == 0)
2107 end_prologue_addr = cur_pc;
2109 /* In a frameless function, we might have incorrectly
2110 skipped some load immediate instructions. Undo the skipping
2111 if the load immediate was not followed by a stack adjustment. */
2112 if (load_immediate_bytes && !seen_sp_adjust)
2113 end_prologue_addr -= load_immediate_bytes;
2115 return end_prologue_addr;
2118 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2119 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2120 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2123 static struct mips_frame_cache *
2124 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
2126 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2127 struct mips_frame_cache *cache;
2129 if ((*this_cache) != NULL)
2130 return (*this_cache);
2132 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2133 (*this_cache) = cache;
2134 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2136 /* Analyze the function prologue. */
2138 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2139 CORE_ADDR start_addr;
2141 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2142 if (start_addr == 0)
2143 start_addr = heuristic_proc_start (gdbarch, pc);
2144 /* We can't analyze the prologue if we couldn't find the begining
2146 if (start_addr == 0)
2149 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
2152 /* gdbarch_sp_regnum contains the value and not the address. */
2153 trad_frame_set_value (cache->saved_regs,
2154 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
2157 return (*this_cache);
2161 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
2162 struct frame_id *this_id)
2164 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2166 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2169 static struct value *
2170 mips_insn32_frame_prev_register (struct frame_info *this_frame,
2171 void **this_cache, int regnum)
2173 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2175 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2179 mips_insn32_frame_sniffer (const struct frame_unwind *self,
2180 struct frame_info *this_frame, void **this_cache)
2182 CORE_ADDR pc = get_frame_pc (this_frame);
2183 if (! mips_pc_is_mips16 (pc))
2188 static const struct frame_unwind mips_insn32_frame_unwind =
2191 mips_insn32_frame_this_id,
2192 mips_insn32_frame_prev_register,
2194 mips_insn32_frame_sniffer
2198 mips_insn32_frame_base_address (struct frame_info *this_frame,
2201 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2206 static const struct frame_base mips_insn32_frame_base =
2208 &mips_insn32_frame_unwind,
2209 mips_insn32_frame_base_address,
2210 mips_insn32_frame_base_address,
2211 mips_insn32_frame_base_address
2214 static const struct frame_base *
2215 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
2217 CORE_ADDR pc = get_frame_pc (this_frame);
2218 if (! mips_pc_is_mips16 (pc))
2219 return &mips_insn32_frame_base;
2224 static struct trad_frame_cache *
2225 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
2228 CORE_ADDR start_addr;
2229 CORE_ADDR stack_addr;
2230 struct trad_frame_cache *this_trad_cache;
2231 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2232 int num_regs = gdbarch_num_regs (gdbarch);
2234 if ((*this_cache) != NULL)
2235 return (*this_cache);
2236 this_trad_cache = trad_frame_cache_zalloc (this_frame);
2237 (*this_cache) = this_trad_cache;
2239 /* The return address is in the link register. */
2240 trad_frame_set_reg_realreg (this_trad_cache,
2241 gdbarch_pc_regnum (gdbarch),
2242 num_regs + MIPS_RA_REGNUM);
2244 /* Frame ID, since it's a frameless / stackless function, no stack
2245 space is allocated and SP on entry is the current SP. */
2246 pc = get_frame_pc (this_frame);
2247 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2248 stack_addr = get_frame_register_signed (this_frame,
2249 num_regs + MIPS_SP_REGNUM);
2250 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
2252 /* Assume that the frame's base is the same as the
2254 trad_frame_set_this_base (this_trad_cache, stack_addr);
2256 return this_trad_cache;
2260 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
2261 struct frame_id *this_id)
2263 struct trad_frame_cache *this_trad_cache
2264 = mips_stub_frame_cache (this_frame, this_cache);
2265 trad_frame_get_id (this_trad_cache, this_id);
2268 static struct value *
2269 mips_stub_frame_prev_register (struct frame_info *this_frame,
2270 void **this_cache, int regnum)
2272 struct trad_frame_cache *this_trad_cache
2273 = mips_stub_frame_cache (this_frame, this_cache);
2274 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
2278 mips_stub_frame_sniffer (const struct frame_unwind *self,
2279 struct frame_info *this_frame, void **this_cache)
2282 struct obj_section *s;
2283 CORE_ADDR pc = get_frame_address_in_block (this_frame);
2284 struct minimal_symbol *msym;
2286 /* Use the stub unwinder for unreadable code. */
2287 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2290 if (in_plt_section (pc, NULL))
2293 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2294 s = find_pc_section (pc);
2297 && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
2298 ".MIPS.stubs") == 0)
2301 /* Calling a PIC function from a non-PIC function passes through a
2302 stub. The stub for foo is named ".pic.foo". */
2303 msym = lookup_minimal_symbol_by_pc (pc);
2305 && SYMBOL_LINKAGE_NAME (msym) != NULL
2306 && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0)
2312 static const struct frame_unwind mips_stub_frame_unwind =
2315 mips_stub_frame_this_id,
2316 mips_stub_frame_prev_register,
2318 mips_stub_frame_sniffer
2322 mips_stub_frame_base_address (struct frame_info *this_frame,
2325 struct trad_frame_cache *this_trad_cache
2326 = mips_stub_frame_cache (this_frame, this_cache);
2327 return trad_frame_get_this_base (this_trad_cache);
2330 static const struct frame_base mips_stub_frame_base =
2332 &mips_stub_frame_unwind,
2333 mips_stub_frame_base_address,
2334 mips_stub_frame_base_address,
2335 mips_stub_frame_base_address
2338 static const struct frame_base *
2339 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
2341 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
2342 return &mips_stub_frame_base;
2347 /* mips_addr_bits_remove - remove useless address bits */
2350 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
2352 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2353 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
2354 /* This hack is a work-around for existing boards using PMON, the
2355 simulator, and any other 64-bit targets that doesn't have true
2356 64-bit addressing. On these targets, the upper 32 bits of
2357 addresses are ignored by the hardware. Thus, the PC or SP are
2358 likely to have been sign extended to all 1s by instruction
2359 sequences that load 32-bit addresses. For example, a typical
2360 piece of code that loads an address is this:
2362 lui $r2, <upper 16 bits>
2363 ori $r2, <lower 16 bits>
2365 But the lui sign-extends the value such that the upper 32 bits
2366 may be all 1s. The workaround is simply to mask off these
2367 bits. In the future, gcc may be changed to support true 64-bit
2368 addressing, and this masking will have to be disabled. */
2369 return addr &= 0xffffffffUL;
2374 /* Instructions used during single-stepping of atomic sequences. */
2375 #define LL_OPCODE 0x30
2376 #define LLD_OPCODE 0x34
2377 #define SC_OPCODE 0x38
2378 #define SCD_OPCODE 0x3c
2380 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2381 instruction and ending with a SC/SCD instruction. If such a sequence
2382 is found, attempt to step through it. A breakpoint is placed at the end of
2386 deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
2388 CORE_ADDR breaks[2] = {-1, -1};
2390 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
2394 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2395 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2400 insn = mips_fetch_instruction (gdbarch, loc);
2401 /* Assume all atomic sequences start with a ll/lld instruction. */
2402 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
2405 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2407 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2410 loc += MIPS_INSN32_SIZE;
2411 insn = mips_fetch_instruction (gdbarch, loc);
2413 /* Assume that there is at most one branch in the atomic
2414 sequence. If a branch is found, put a breakpoint in its
2415 destination address. */
2416 switch (itype_op (insn))
2418 case 0: /* SPECIAL */
2419 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
2420 return 0; /* fallback to the standard single-step code. */
2422 case 1: /* REGIMM */
2423 is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */
2427 return 0; /* fallback to the standard single-step code. */
2434 case 22: /* BLEZL */
2435 case 23: /* BGTTL */
2441 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2446 branch_bp = loc + mips32_relative_offset (insn) + 4;
2447 if (last_breakpoint >= 1)
2448 return 0; /* More than one branch found, fallback to the
2449 standard single-step code. */
2450 breaks[1] = branch_bp;
2454 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
2458 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2459 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
2462 loc += MIPS_INSN32_SIZE;
2464 /* Insert a breakpoint right after the end of the atomic sequence. */
2467 /* Check for duplicated breakpoints. Check also for a breakpoint
2468 placed (branch instruction's destination) in the atomic sequence */
2469 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
2470 last_breakpoint = 0;
2472 /* Effectively inserts the breakpoints. */
2473 for (index = 0; index <= last_breakpoint; index++)
2474 insert_single_step_breakpoint (gdbarch, breaks[index]);
2479 /* mips_software_single_step() is called just before we want to resume
2480 the inferior, if we want to single-step it but there is no hardware
2481 or kernel single-step support (MIPS on GNU/Linux for example). We find
2482 the target of the coming instruction and breakpoint it. */
2485 mips_software_single_step (struct frame_info *frame)
2487 struct gdbarch *gdbarch = get_frame_arch (frame);
2488 CORE_ADDR pc, next_pc;
2490 pc = get_frame_pc (frame);
2491 if (deal_with_atomic_sequence (gdbarch, pc))
2494 next_pc = mips_next_pc (frame, pc);
2496 insert_single_step_breakpoint (gdbarch, next_pc);
2500 /* Test whether the PC points to the return instruction at the
2501 end of a function. */
2504 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
2506 if (mips_pc_is_mips16 (pc))
2507 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2508 generates a "jr $ra"; other times it generates code to load
2509 the return address from the stack to an accessible register (such
2510 as $a3), then a "jr" using that register. This second case
2511 is almost impossible to distinguish from an indirect jump
2512 used for switch statements, so we don't even try. */
2513 return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */
2515 return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */
2519 /* This fencepost looks highly suspicious to me. Removing it also
2520 seems suspicious as it could affect remote debugging across serial
2524 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
2530 struct inferior *inf;
2532 pc = gdbarch_addr_bits_remove (gdbarch, pc);
2534 fence = start_pc - heuristic_fence_post;
2538 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
2539 fence = VM_MIN_ADDRESS;
2541 instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE;
2543 inf = current_inferior ();
2545 /* search back for previous return */
2546 for (start_pc -= instlen;; start_pc -= instlen)
2547 if (start_pc < fence)
2549 /* It's not clear to me why we reach this point when
2550 stop_soon, but with this test, at least we
2551 don't print out warnings for every child forked (eg, on
2552 decstation). 22apr93 rich@cygnus.com. */
2553 if (inf->stop_soon == NO_STOP_QUIETLY)
2555 static int blurb_printed = 0;
2557 warning (_("GDB can't find the start of the function at %s."),
2558 paddress (gdbarch, pc));
2562 /* This actually happens frequently in embedded
2563 development, when you first connect to a board
2564 and your stack pointer and pc are nowhere in
2565 particular. This message needs to give people
2566 in that situation enough information to
2567 determine that it's no big deal. */
2568 printf_filtered ("\n\
2569 GDB is unable to find the start of the function at %s\n\
2570 and thus can't determine the size of that function's stack frame.\n\
2571 This means that GDB may be unable to access that stack frame, or\n\
2572 the frames below it.\n\
2573 This problem is most likely caused by an invalid program counter or\n\
2575 However, if you think GDB should simply search farther back\n\
2576 from %s for code which looks like the beginning of a\n\
2577 function, you can increase the range of the search using the `set\n\
2578 heuristic-fence-post' command.\n",
2579 paddress (gdbarch, pc), paddress (gdbarch, pc));
2586 else if (mips_pc_is_mips16 (start_pc))
2588 unsigned short inst;
2590 /* On MIPS16, any one of the following is likely to be the
2591 start of a function:
2597 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2598 inst = mips_fetch_instruction (gdbarch, start_pc);
2599 if ((inst & 0xff80) == 0x6480) /* save */
2601 if (start_pc - instlen >= fence)
2603 inst = mips_fetch_instruction (gdbarch, start_pc - instlen);
2604 if ((inst & 0xf800) == 0xf000) /* extend */
2605 start_pc -= instlen;
2609 else if (((inst & 0xf81f) == 0xe809
2610 && (inst & 0x700) != 0x700) /* entry */
2611 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
2612 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
2613 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
2615 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
2616 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2621 else if (mips_about_to_return (gdbarch, start_pc))
2623 /* Skip return and its delay slot. */
2624 start_pc += 2 * MIPS_INSN32_SIZE;
2631 struct mips_objfile_private
2637 /* According to the current ABI, should the type be passed in a
2638 floating-point register (assuming that there is space)? When there
2639 is no FPU, FP are not even considered as possible candidates for
2640 FP registers and, consequently this returns false - forces FP
2641 arguments into integer registers. */
2644 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
2645 struct type *arg_type)
2647 return ((typecode == TYPE_CODE_FLT
2648 || (MIPS_EABI (gdbarch)
2649 && (typecode == TYPE_CODE_STRUCT
2650 || typecode == TYPE_CODE_UNION)
2651 && TYPE_NFIELDS (arg_type) == 1
2652 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
2654 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
2657 /* On o32, argument passing in GPRs depends on the alignment of the type being
2658 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2661 mips_type_needs_double_align (struct type *type)
2663 enum type_code typecode = TYPE_CODE (type);
2665 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2667 else if (typecode == TYPE_CODE_STRUCT)
2669 if (TYPE_NFIELDS (type) < 1)
2671 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2673 else if (typecode == TYPE_CODE_UNION)
2677 n = TYPE_NFIELDS (type);
2678 for (i = 0; i < n; i++)
2679 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2686 /* Adjust the address downward (direction of stack growth) so that it
2687 is correctly aligned for a new stack frame. */
2689 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2691 return align_down (addr, 16);
2695 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2696 struct regcache *regcache, CORE_ADDR bp_addr,
2697 int nargs, struct value **args, CORE_ADDR sp,
2698 int struct_return, CORE_ADDR struct_addr)
2704 int stack_offset = 0;
2705 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2706 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2707 CORE_ADDR func_addr = find_function_addr (function, NULL);
2708 int regsize = mips_abi_regsize (gdbarch);
2710 /* For shared libraries, "t9" needs to point at the function
2712 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2714 /* Set the return address register to point to the entry point of
2715 the program, where a breakpoint lies in wait. */
2716 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2718 /* First ensure that the stack and structure return address (if any)
2719 are properly aligned. The stack has to be at least 64-bit
2720 aligned even on 32-bit machines, because doubles must be 64-bit
2721 aligned. For n32 and n64, stack frames need to be 128-bit
2722 aligned, so we round to this widest known alignment. */
2724 sp = align_down (sp, 16);
2725 struct_addr = align_down (struct_addr, 16);
2727 /* Now make space on the stack for the args. We allocate more
2728 than necessary for EABI, because the first few arguments are
2729 passed in registers, but that's OK. */
2730 for (argnum = 0; argnum < nargs; argnum++)
2731 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
2732 sp -= align_up (len, 16);
2735 fprintf_unfiltered (gdb_stdlog,
2736 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2737 paddress (gdbarch, sp), (long) align_up (len, 16));
2739 /* Initialize the integer and float register pointers. */
2740 argreg = MIPS_A0_REGNUM;
2741 float_argreg = mips_fpa0_regnum (gdbarch);
2743 /* The struct_return pointer occupies the first parameter-passing reg. */
2747 fprintf_unfiltered (gdb_stdlog,
2748 "mips_eabi_push_dummy_call: struct_return reg=%d %s\n",
2749 argreg, paddress (gdbarch, struct_addr));
2750 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
2753 /* Now load as many as possible of the first arguments into
2754 registers, and push the rest onto the stack. Loop thru args
2755 from first to last. */
2756 for (argnum = 0; argnum < nargs; argnum++)
2758 const gdb_byte *val;
2759 gdb_byte valbuf[MAX_REGISTER_SIZE];
2760 struct value *arg = args[argnum];
2761 struct type *arg_type = check_typedef (value_type (arg));
2762 int len = TYPE_LENGTH (arg_type);
2763 enum type_code typecode = TYPE_CODE (arg_type);
2766 fprintf_unfiltered (gdb_stdlog,
2767 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2768 argnum + 1, len, (int) typecode);
2770 /* The EABI passes structures that do not fit in a register by
2773 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2775 store_unsigned_integer (valbuf, regsize, byte_order,
2776 value_address (arg));
2777 typecode = TYPE_CODE_PTR;
2781 fprintf_unfiltered (gdb_stdlog, " push");
2784 val = value_contents (arg);
2786 /* 32-bit ABIs always start floating point arguments in an
2787 even-numbered floating point register. Round the FP register
2788 up before the check to see if there are any FP registers
2789 left. Non MIPS_EABI targets also pass the FP in the integer
2790 registers so also round up normal registers. */
2791 if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
2793 if ((float_argreg & 1))
2797 /* Floating point arguments passed in registers have to be
2798 treated specially. On 32-bit architectures, doubles
2799 are passed in register pairs; the even register gets
2800 the low word, and the odd register gets the high word.
2801 On non-EABI processors, the first two floating point arguments are
2802 also copied to general registers, because MIPS16 functions
2803 don't use float registers for arguments. This duplication of
2804 arguments in general registers can't hurt non-MIPS16 functions
2805 because those registers are normally skipped. */
2806 /* MIPS_EABI squeezes a struct that contains a single floating
2807 point value into an FP register instead of pushing it onto the
2809 if (fp_register_arg_p (gdbarch, typecode, arg_type)
2810 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
2812 /* EABI32 will pass doubles in consecutive registers, even on
2813 64-bit cores. At one time, we used to check the size of
2814 `float_argreg' to determine whether or not to pass doubles
2815 in consecutive registers, but this is not sufficient for
2816 making the ABI determination. */
2817 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
2819 int low_offset = gdbarch_byte_order (gdbarch)
2820 == BFD_ENDIAN_BIG ? 4 : 0;
2821 unsigned long regval;
2823 /* Write the low word of the double to the even register(s). */
2824 regval = extract_unsigned_integer (val + low_offset,
2827 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2828 float_argreg, phex (regval, 4));
2829 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2831 /* Write the high word of the double to the odd register(s). */
2832 regval = extract_unsigned_integer (val + 4 - low_offset,
2835 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2836 float_argreg, phex (regval, 4));
2837 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2841 /* This is a floating point value that fits entirely
2842 in a single register. */
2843 /* On 32 bit ABI's the float_argreg is further adjusted
2844 above to ensure that it is even register aligned. */
2845 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
2847 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2848 float_argreg, phex (regval, len));
2849 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2854 /* Copy the argument to general registers or the stack in
2855 register-sized pieces. Large arguments are split between
2856 registers and stack. */
2857 /* Note: structs whose size is not a multiple of regsize
2858 are treated specially: Irix cc passes
2859 them in registers where gcc sometimes puts them on the
2860 stack. For maximum compatibility, we will put them in
2862 int odd_sized_struct = (len > regsize && len % regsize != 0);
2864 /* Note: Floating-point values that didn't fit into an FP
2865 register are only written to memory. */
2868 /* Remember if the argument was written to the stack. */
2869 int stack_used_p = 0;
2870 int partial_len = (len < regsize ? len : regsize);
2873 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2876 /* Write this portion of the argument to the stack. */
2877 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
2879 || fp_register_arg_p (gdbarch, typecode, arg_type))
2881 /* Should shorter than int integer values be
2882 promoted to int before being stored? */
2883 int longword_offset = 0;
2886 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2889 && (typecode == TYPE_CODE_INT
2890 || typecode == TYPE_CODE_PTR
2891 || typecode == TYPE_CODE_FLT) && len <= 4)
2892 longword_offset = regsize - len;
2893 else if ((typecode == TYPE_CODE_STRUCT
2894 || typecode == TYPE_CODE_UNION)
2895 && TYPE_LENGTH (arg_type) < regsize)
2896 longword_offset = regsize - len;
2901 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
2902 paddress (gdbarch, stack_offset));
2903 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
2904 paddress (gdbarch, longword_offset));
2907 addr = sp + stack_offset + longword_offset;
2912 fprintf_unfiltered (gdb_stdlog, " @%s ",
2913 paddress (gdbarch, addr));
2914 for (i = 0; i < partial_len; i++)
2916 fprintf_unfiltered (gdb_stdlog, "%02x",
2920 write_memory (addr, val, partial_len);
2923 /* Note!!! This is NOT an else clause. Odd sized
2924 structs may go thru BOTH paths. Floating point
2925 arguments will not. */
2926 /* Write this portion of the argument to a general
2927 purpose register. */
2928 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
2929 && !fp_register_arg_p (gdbarch, typecode, arg_type))
2932 extract_unsigned_integer (val, partial_len, byte_order);
2935 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2937 phex (regval, regsize));
2938 regcache_cooked_write_unsigned (regcache, argreg, regval);
2945 /* Compute the the offset into the stack at which we
2946 will copy the next parameter.
2948 In the new EABI (and the NABI32), the stack_offset
2949 only needs to be adjusted when it has been used. */
2952 stack_offset += align_up (partial_len, regsize);
2956 fprintf_unfiltered (gdb_stdlog, "\n");
2959 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2961 /* Return adjusted stack pointer. */
2965 /* Determine the return value convention being used. */
2967 static enum return_value_convention
2968 mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type,
2969 struct type *type, struct regcache *regcache,
2970 gdb_byte *readbuf, const gdb_byte *writebuf)
2972 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2973 int fp_return_type = 0;
2974 int offset, regnum, xfer;
2976 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2977 return RETURN_VALUE_STRUCT_CONVENTION;
2979 /* Floating point type? */
2980 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
2982 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2984 /* Structs with a single field of float type
2985 are returned in a floating point register. */
2986 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
2987 || TYPE_CODE (type) == TYPE_CODE_UNION)
2988 && TYPE_NFIELDS (type) == 1)
2990 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
2992 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
2999 /* A floating-point value belongs in the least significant part
3002 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3003 regnum = mips_regnum (gdbarch)->fp0;
3007 /* An integer value goes in V0/V1. */
3009 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
3010 regnum = MIPS_V0_REGNUM;
3013 offset < TYPE_LENGTH (type);
3014 offset += mips_abi_regsize (gdbarch), regnum++)
3016 xfer = mips_abi_regsize (gdbarch);
3017 if (offset + xfer > TYPE_LENGTH (type))
3018 xfer = TYPE_LENGTH (type) - offset;
3019 mips_xfer_register (gdbarch, regcache,
3020 gdbarch_num_regs (gdbarch) + regnum, xfer,
3021 gdbarch_byte_order (gdbarch), readbuf, writebuf,
3025 return RETURN_VALUE_REGISTER_CONVENTION;
3029 /* N32/N64 ABI stuff. */
3031 /* Search for a naturally aligned double at OFFSET inside a struct
3032 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3036 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
3041 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
3044 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
3047 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
3050 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
3053 struct type *field_type;
3055 /* We're only looking at normal fields. */
3056 if (field_is_static (&TYPE_FIELD (arg_type, i))
3057 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
3060 /* If we have gone past the offset, there is no double to pass. */
3061 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
3065 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
3067 /* If this field is entirely before the requested offset, go
3068 on to the next one. */
3069 if (pos + TYPE_LENGTH (field_type) <= offset)
3072 /* If this is our special aligned double, we can stop. */
3073 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
3074 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
3077 /* This field starts at or before the requested offset, and
3078 overlaps it. If it is a structure, recurse inwards. */
3079 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
3086 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3087 struct regcache *regcache, CORE_ADDR bp_addr,
3088 int nargs, struct value **args, CORE_ADDR sp,
3089 int struct_return, CORE_ADDR struct_addr)
3095 int stack_offset = 0;
3096 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3097 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3098 CORE_ADDR func_addr = find_function_addr (function, NULL);
3100 /* For shared libraries, "t9" needs to point at the function
3102 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3104 /* Set the return address register to point to the entry point of
3105 the program, where a breakpoint lies in wait. */
3106 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3108 /* First ensure that the stack and structure return address (if any)
3109 are properly aligned. The stack has to be at least 64-bit
3110 aligned even on 32-bit machines, because doubles must be 64-bit
3111 aligned. For n32 and n64, stack frames need to be 128-bit
3112 aligned, so we round to this widest known alignment. */
3114 sp = align_down (sp, 16);
3115 struct_addr = align_down (struct_addr, 16);
3117 /* Now make space on the stack for the args. */
3118 for (argnum = 0; argnum < nargs; argnum++)
3119 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
3120 sp -= align_up (len, 16);
3123 fprintf_unfiltered (gdb_stdlog,
3124 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3125 paddress (gdbarch, sp), (long) align_up (len, 16));
3127 /* Initialize the integer and float register pointers. */
3128 argreg = MIPS_A0_REGNUM;
3129 float_argreg = mips_fpa0_regnum (gdbarch);
3131 /* The struct_return pointer occupies the first parameter-passing reg. */
3135 fprintf_unfiltered (gdb_stdlog,
3136 "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n",
3137 argreg, paddress (gdbarch, struct_addr));
3138 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3141 /* Now load as many as possible of the first arguments into
3142 registers, and push the rest onto the stack. Loop thru args
3143 from first to last. */
3144 for (argnum = 0; argnum < nargs; argnum++)
3146 const gdb_byte *val;
3147 struct value *arg = args[argnum];
3148 struct type *arg_type = check_typedef (value_type (arg));
3149 int len = TYPE_LENGTH (arg_type);
3150 enum type_code typecode = TYPE_CODE (arg_type);
3153 fprintf_unfiltered (gdb_stdlog,
3154 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3155 argnum + 1, len, (int) typecode);
3157 val = value_contents (arg);
3159 /* A 128-bit long double value requires an even-odd pair of
3160 floating-point registers. */
3162 && fp_register_arg_p (gdbarch, typecode, arg_type)
3163 && (float_argreg & 1))
3169 if (fp_register_arg_p (gdbarch, typecode, arg_type)
3170 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3172 /* This is a floating point value that fits entirely
3173 in a single register or a pair of registers. */
3174 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3175 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
3177 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3178 float_argreg, phex (regval, reglen));
3179 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3182 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3183 argreg, phex (regval, reglen));
3184 regcache_cooked_write_unsigned (regcache, argreg, regval);
3189 regval = extract_unsigned_integer (val + reglen,
3190 reglen, byte_order);
3192 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3193 float_argreg, phex (regval, reglen));
3194 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3197 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3198 argreg, phex (regval, reglen));
3199 regcache_cooked_write_unsigned (regcache, argreg, regval);
3206 /* Copy the argument to general registers or the stack in
3207 register-sized pieces. Large arguments are split between
3208 registers and stack. */
3209 /* For N32/N64, structs, unions, or other composite types are
3210 treated as a sequence of doublewords, and are passed in integer
3211 or floating point registers as though they were simple scalar
3212 parameters to the extent that they fit, with any excess on the
3213 stack packed according to the normal memory layout of the
3215 The caller does not reserve space for the register arguments;
3216 the callee is responsible for reserving it if required. */
3217 /* Note: Floating-point values that didn't fit into an FP
3218 register are only written to memory. */
3221 /* Remember if the argument was written to the stack. */
3222 int stack_used_p = 0;
3223 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3226 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3229 if (fp_register_arg_p (gdbarch, typecode, arg_type))
3230 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
3232 /* Write this portion of the argument to the stack. */
3233 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
3235 /* Should shorter than int integer values be
3236 promoted to int before being stored? */
3237 int longword_offset = 0;
3240 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
3242 if ((typecode == TYPE_CODE_INT
3243 || typecode == TYPE_CODE_PTR)
3245 longword_offset = MIPS64_REGSIZE - len;
3250 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
3251 paddress (gdbarch, stack_offset));
3252 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
3253 paddress (gdbarch, longword_offset));
3256 addr = sp + stack_offset + longword_offset;
3261 fprintf_unfiltered (gdb_stdlog, " @%s ",
3262 paddress (gdbarch, addr));
3263 for (i = 0; i < partial_len; i++)
3265 fprintf_unfiltered (gdb_stdlog, "%02x",
3269 write_memory (addr, val, partial_len);
3272 /* Note!!! This is NOT an else clause. Odd sized
3273 structs may go thru BOTH paths. */
3274 /* Write this portion of the argument to a general
3275 purpose register. */
3276 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3280 /* Sign extend pointers, 32-bit integers and signed
3281 16-bit and 8-bit integers; everything else is taken
3284 if ((partial_len == 4
3285 && (typecode == TYPE_CODE_PTR
3286 || typecode == TYPE_CODE_INT))
3288 && typecode == TYPE_CODE_INT
3289 && !TYPE_UNSIGNED (arg_type)))
3290 regval = extract_signed_integer (val, partial_len,
3293 regval = extract_unsigned_integer (val, partial_len,
3296 /* A non-floating-point argument being passed in a
3297 general register. If a struct or union, and if
3298 the remaining length is smaller than the register
3299 size, we have to adjust the register value on
3302 It does not seem to be necessary to do the
3303 same for integral types. */
3305 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3306 && partial_len < MIPS64_REGSIZE
3307 && (typecode == TYPE_CODE_STRUCT
3308 || typecode == TYPE_CODE_UNION))
3309 regval <<= ((MIPS64_REGSIZE - partial_len)
3313 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3315 phex (regval, MIPS64_REGSIZE));
3316 regcache_cooked_write_unsigned (regcache, argreg, regval);
3318 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
3319 TYPE_LENGTH (arg_type) - len))
3322 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
3324 phex (regval, MIPS64_REGSIZE));
3325 regcache_cooked_write_unsigned (regcache, float_argreg,
3336 /* Compute the the offset into the stack at which we
3337 will copy the next parameter.
3339 In N32 (N64?), the stack_offset only needs to be
3340 adjusted when it has been used. */
3343 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
3347 fprintf_unfiltered (gdb_stdlog, "\n");
3350 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3352 /* Return adjusted stack pointer. */
3356 static enum return_value_convention
3357 mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type,
3358 struct type *type, struct regcache *regcache,
3359 gdb_byte *readbuf, const gdb_byte *writebuf)
3361 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3363 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3365 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3366 if needed), as appropriate for the type. Composite results (struct,
3367 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3370 * A struct with only one or two floating point fields is returned in $f0
3371 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3374 * Any other struct or union results of at most 128 bits are returned in
3375 $2 (first 64 bits) and $3 (remainder, if necessary).
3377 * Larger composite results are handled by converting the function to a
3378 procedure with an implicit first parameter, which is a pointer to an area
3379 reserved by the caller to receive the result. [The o32-bit ABI requires
3380 that all composite results be handled by conversion to implicit first
3381 parameters. The MIPS/SGI Fortran implementation has always made a
3382 specific exception to return COMPLEX results in the floating point
3385 if (TYPE_CODE (type) == TYPE_CODE_ARRAY
3386 || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
3387 return RETURN_VALUE_STRUCT_CONVENTION;
3388 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3389 && TYPE_LENGTH (type) == 16
3390 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3392 /* A 128-bit floating-point value fills both $f0 and $f2. The
3393 two registers are used in the same as memory order, so the
3394 eight bytes with the lower memory address are in $f0. */
3396 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
3397 mips_xfer_register (gdbarch, regcache,
3398 gdbarch_num_regs (gdbarch)
3399 + mips_regnum (gdbarch)->fp0,
3400 8, gdbarch_byte_order (gdbarch),
3401 readbuf, writebuf, 0);
3402 mips_xfer_register (gdbarch, regcache,
3403 gdbarch_num_regs (gdbarch)
3404 + mips_regnum (gdbarch)->fp0 + 2,
3405 8, gdbarch_byte_order (gdbarch),
3406 readbuf ? readbuf + 8 : readbuf,
3407 writebuf ? writebuf + 8 : writebuf, 0);
3408 return RETURN_VALUE_REGISTER_CONVENTION;
3410 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3411 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3413 /* A single or double floating-point value that fits in FP0. */
3415 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3416 mips_xfer_register (gdbarch, regcache,
3417 gdbarch_num_regs (gdbarch)
3418 + mips_regnum (gdbarch)->fp0,
3420 gdbarch_byte_order (gdbarch),
3421 readbuf, writebuf, 0);
3422 return RETURN_VALUE_REGISTER_CONVENTION;
3424 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3425 && TYPE_NFIELDS (type) <= 2
3426 && TYPE_NFIELDS (type) >= 1
3427 && ((TYPE_NFIELDS (type) == 1
3428 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3430 || (TYPE_NFIELDS (type) == 2
3431 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3433 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
3434 == TYPE_CODE_FLT))))
3436 /* A struct that contains one or two floats. Each value is part
3437 in the least significant part of their floating point
3438 register (or GPR, for soft float). */
3441 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
3442 ? mips_regnum (gdbarch)->fp0
3444 field < TYPE_NFIELDS (type); field++, regnum += 2)
3446 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3449 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3451 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
3453 /* A 16-byte long double field goes in two consecutive
3455 mips_xfer_register (gdbarch, regcache,
3456 gdbarch_num_regs (gdbarch) + regnum,
3458 gdbarch_byte_order (gdbarch),
3459 readbuf, writebuf, offset);
3460 mips_xfer_register (gdbarch, regcache,
3461 gdbarch_num_regs (gdbarch) + regnum + 1,
3463 gdbarch_byte_order (gdbarch),
3464 readbuf, writebuf, offset + 8);
3467 mips_xfer_register (gdbarch, regcache,
3468 gdbarch_num_regs (gdbarch) + regnum,
3469 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3470 gdbarch_byte_order (gdbarch),
3471 readbuf, writebuf, offset);
3473 return RETURN_VALUE_REGISTER_CONVENTION;
3475 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3476 || TYPE_CODE (type) == TYPE_CODE_UNION)
3478 /* A structure or union. Extract the left justified value,
3479 regardless of the byte order. I.e. DO NOT USE
3483 for (offset = 0, regnum = MIPS_V0_REGNUM;
3484 offset < TYPE_LENGTH (type);
3485 offset += register_size (gdbarch, regnum), regnum++)
3487 int xfer = register_size (gdbarch, regnum);
3488 if (offset + xfer > TYPE_LENGTH (type))
3489 xfer = TYPE_LENGTH (type) - offset;
3491 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3492 offset, xfer, regnum);
3493 mips_xfer_register (gdbarch, regcache,
3494 gdbarch_num_regs (gdbarch) + regnum,
3495 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
3498 return RETURN_VALUE_REGISTER_CONVENTION;
3502 /* A scalar extract each part but least-significant-byte
3506 for (offset = 0, regnum = MIPS_V0_REGNUM;
3507 offset < TYPE_LENGTH (type);
3508 offset += register_size (gdbarch, regnum), regnum++)
3510 int xfer = register_size (gdbarch, regnum);
3511 if (offset + xfer > TYPE_LENGTH (type))
3512 xfer = TYPE_LENGTH (type) - offset;
3514 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3515 offset, xfer, regnum);
3516 mips_xfer_register (gdbarch, regcache,
3517 gdbarch_num_regs (gdbarch) + regnum,
3518 xfer, gdbarch_byte_order (gdbarch),
3519 readbuf, writebuf, offset);
3521 return RETURN_VALUE_REGISTER_CONVENTION;
3525 /* O32 ABI stuff. */
3528 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3529 struct regcache *regcache, CORE_ADDR bp_addr,
3530 int nargs, struct value **args, CORE_ADDR sp,
3531 int struct_return, CORE_ADDR struct_addr)
3537 int stack_offset = 0;
3538 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3539 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3540 CORE_ADDR func_addr = find_function_addr (function, NULL);
3542 /* For shared libraries, "t9" needs to point at the function
3544 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3546 /* Set the return address register to point to the entry point of
3547 the program, where a breakpoint lies in wait. */
3548 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3550 /* First ensure that the stack and structure return address (if any)
3551 are properly aligned. The stack has to be at least 64-bit
3552 aligned even on 32-bit machines, because doubles must be 64-bit
3553 aligned. For n32 and n64, stack frames need to be 128-bit
3554 aligned, so we round to this widest known alignment. */
3556 sp = align_down (sp, 16);
3557 struct_addr = align_down (struct_addr, 16);
3559 /* Now make space on the stack for the args. */
3560 for (argnum = 0; argnum < nargs; argnum++)
3562 struct type *arg_type = check_typedef (value_type (args[argnum]));
3563 int arglen = TYPE_LENGTH (arg_type);
3565 /* Align to double-word if necessary. */
3566 if (mips_type_needs_double_align (arg_type))
3567 len = align_up (len, MIPS32_REGSIZE * 2);
3568 /* Allocate space on the stack. */
3569 len += align_up (arglen, MIPS32_REGSIZE);
3571 sp -= align_up (len, 16);
3574 fprintf_unfiltered (gdb_stdlog,
3575 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3576 paddress (gdbarch, sp), (long) align_up (len, 16));
3578 /* Initialize the integer and float register pointers. */
3579 argreg = MIPS_A0_REGNUM;
3580 float_argreg = mips_fpa0_regnum (gdbarch);
3582 /* The struct_return pointer occupies the first parameter-passing reg. */
3586 fprintf_unfiltered (gdb_stdlog,
3587 "mips_o32_push_dummy_call: struct_return reg=%d %s\n",
3588 argreg, paddress (gdbarch, struct_addr));
3589 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3590 stack_offset += MIPS32_REGSIZE;
3593 /* Now load as many as possible of the first arguments into
3594 registers, and push the rest onto the stack. Loop thru args
3595 from first to last. */
3596 for (argnum = 0; argnum < nargs; argnum++)
3598 const gdb_byte *val;
3599 struct value *arg = args[argnum];
3600 struct type *arg_type = check_typedef (value_type (arg));
3601 int len = TYPE_LENGTH (arg_type);
3602 enum type_code typecode = TYPE_CODE (arg_type);
3605 fprintf_unfiltered (gdb_stdlog,
3606 "mips_o32_push_dummy_call: %d len=%d type=%d",
3607 argnum + 1, len, (int) typecode);
3609 val = value_contents (arg);
3611 /* 32-bit ABIs always start floating point arguments in an
3612 even-numbered floating point register. Round the FP register
3613 up before the check to see if there are any FP registers
3614 left. O32/O64 targets also pass the FP in the integer
3615 registers so also round up normal registers. */
3616 if (fp_register_arg_p (gdbarch, typecode, arg_type))
3618 if ((float_argreg & 1))
3622 /* Floating point arguments passed in registers have to be
3623 treated specially. On 32-bit architectures, doubles
3624 are passed in register pairs; the even register gets
3625 the low word, and the odd register gets the high word.
3626 On O32/O64, the first two floating point arguments are
3627 also copied to general registers, because MIPS16 functions
3628 don't use float registers for arguments. This duplication of
3629 arguments in general registers can't hurt non-MIPS16 functions
3630 because those registers are normally skipped. */
3632 if (fp_register_arg_p (gdbarch, typecode, arg_type)
3633 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
3635 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
3637 int low_offset = gdbarch_byte_order (gdbarch)
3638 == BFD_ENDIAN_BIG ? 4 : 0;
3639 unsigned long regval;
3641 /* Write the low word of the double to the even register(s). */
3642 regval = extract_unsigned_integer (val + low_offset,
3645 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3646 float_argreg, phex (regval, 4));
3647 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3649 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3650 argreg, phex (regval, 4));
3651 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3653 /* Write the high word of the double to the odd register(s). */
3654 regval = extract_unsigned_integer (val + 4 - low_offset,
3657 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3658 float_argreg, phex (regval, 4));
3659 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3662 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3663 argreg, phex (regval, 4));
3664 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3668 /* This is a floating point value that fits entirely
3669 in a single register. */
3670 /* On 32 bit ABI's the float_argreg is further adjusted
3671 above to ensure that it is even register aligned. */
3672 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
3674 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3675 float_argreg, phex (regval, len));
3676 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3677 /* Although two FP registers are reserved for each
3678 argument, only one corresponding integer register is
3681 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3682 argreg, phex (regval, len));
3683 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3685 /* Reserve space for the FP register. */
3686 stack_offset += align_up (len, MIPS32_REGSIZE);
3690 /* Copy the argument to general registers or the stack in
3691 register-sized pieces. Large arguments are split between
3692 registers and stack. */
3693 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3694 are treated specially: Irix cc passes
3695 them in registers where gcc sometimes puts them on the
3696 stack. For maximum compatibility, we will put them in
3698 int odd_sized_struct = (len > MIPS32_REGSIZE
3699 && len % MIPS32_REGSIZE != 0);
3700 /* Structures should be aligned to eight bytes (even arg registers)
3701 on MIPS_ABI_O32, if their first member has double precision. */
3702 if (mips_type_needs_double_align (arg_type))
3707 stack_offset += MIPS32_REGSIZE;
3712 /* Remember if the argument was written to the stack. */
3713 int stack_used_p = 0;
3714 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
3717 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3720 /* Write this portion of the argument to the stack. */
3721 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
3722 || odd_sized_struct)
3724 /* Should shorter than int integer values be
3725 promoted to int before being stored? */
3726 int longword_offset = 0;
3732 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
3733 paddress (gdbarch, stack_offset));
3734 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
3735 paddress (gdbarch, longword_offset));
3738 addr = sp + stack_offset + longword_offset;
3743 fprintf_unfiltered (gdb_stdlog, " @%s ",
3744 paddress (gdbarch, addr));
3745 for (i = 0; i < partial_len; i++)
3747 fprintf_unfiltered (gdb_stdlog, "%02x",
3751 write_memory (addr, val, partial_len);
3754 /* Note!!! This is NOT an else clause. Odd sized
3755 structs may go thru BOTH paths. */
3756 /* Write this portion of the argument to a general
3757 purpose register. */
3758 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3760 LONGEST regval = extract_signed_integer (val, partial_len,
3762 /* Value may need to be sign extended, because
3763 mips_isa_regsize() != mips_abi_regsize(). */
3765 /* A non-floating-point argument being passed in a
3766 general register. If a struct or union, and if
3767 the remaining length is smaller than the register
3768 size, we have to adjust the register value on
3771 It does not seem to be necessary to do the
3772 same for integral types.
3774 Also don't do this adjustment on O64 binaries.
3776 cagney/2001-07-23: gdb/179: Also, GCC, when
3777 outputting LE O32 with sizeof (struct) <
3778 mips_abi_regsize(), generates a left shift
3779 as part of storing the argument in a register
3780 (the left shift isn't generated when
3781 sizeof (struct) >= mips_abi_regsize()). Since
3782 it is quite possible that this is GCC
3783 contradicting the LE/O32 ABI, GDB has not been
3784 adjusted to accommodate this. Either someone
3785 needs to demonstrate that the LE/O32 ABI
3786 specifies such a left shift OR this new ABI gets
3787 identified as such and GDB gets tweaked
3790 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3791 && partial_len < MIPS32_REGSIZE
3792 && (typecode == TYPE_CODE_STRUCT
3793 || typecode == TYPE_CODE_UNION))
3794 regval <<= ((MIPS32_REGSIZE - partial_len)
3798 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3800 phex (regval, MIPS32_REGSIZE));
3801 regcache_cooked_write_unsigned (regcache, argreg, regval);
3804 /* Prevent subsequent floating point arguments from
3805 being passed in floating point registers. */
3806 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
3812 /* Compute the the offset into the stack at which we
3813 will copy the next parameter.
3815 In older ABIs, the caller reserved space for
3816 registers that contained arguments. This was loosely
3817 refered to as their "home". Consequently, space is
3818 always allocated. */
3820 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
3824 fprintf_unfiltered (gdb_stdlog, "\n");
3827 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3829 /* Return adjusted stack pointer. */
3833 static enum return_value_convention
3834 mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type,
3835 struct type *type, struct regcache *regcache,
3836 gdb_byte *readbuf, const gdb_byte *writebuf)
3838 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3840 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3841 || TYPE_CODE (type) == TYPE_CODE_UNION
3842 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3843 return RETURN_VALUE_STRUCT_CONVENTION;
3844 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3845 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3847 /* A single-precision floating-point value. It fits in the
3848 least significant part of FP0. */
3850 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3851 mips_xfer_register (gdbarch, regcache,
3852 gdbarch_num_regs (gdbarch)
3853 + mips_regnum (gdbarch)->fp0,
3855 gdbarch_byte_order (gdbarch),
3856 readbuf, writebuf, 0);
3857 return RETURN_VALUE_REGISTER_CONVENTION;
3859 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3860 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3862 /* A double-precision floating-point value. The most
3863 significant part goes in FP1, and the least significant in
3866 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3867 switch (gdbarch_byte_order (gdbarch))
3869 case BFD_ENDIAN_LITTLE:
3870 mips_xfer_register (gdbarch, regcache,
3871 gdbarch_num_regs (gdbarch)
3872 + mips_regnum (gdbarch)->fp0 +
3873 0, 4, gdbarch_byte_order (gdbarch),
3874 readbuf, writebuf, 0);
3875 mips_xfer_register (gdbarch, regcache,
3876 gdbarch_num_regs (gdbarch)
3877 + mips_regnum (gdbarch)->fp0 + 1,
3878 4, gdbarch_byte_order (gdbarch),
3879 readbuf, writebuf, 4);
3881 case BFD_ENDIAN_BIG:
3882 mips_xfer_register (gdbarch, regcache,
3883 gdbarch_num_regs (gdbarch)
3884 + mips_regnum (gdbarch)->fp0 + 1,
3885 4, gdbarch_byte_order (gdbarch),
3886 readbuf, writebuf, 0);
3887 mips_xfer_register (gdbarch, regcache,
3888 gdbarch_num_regs (gdbarch)
3889 + mips_regnum (gdbarch)->fp0 + 0,
3890 4, gdbarch_byte_order (gdbarch),
3891 readbuf, writebuf, 4);
3894 internal_error (__FILE__, __LINE__, _("bad switch"));
3896 return RETURN_VALUE_REGISTER_CONVENTION;
3899 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3900 && TYPE_NFIELDS (type) <= 2
3901 && TYPE_NFIELDS (type) >= 1
3902 && ((TYPE_NFIELDS (type) == 1
3903 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3905 || (TYPE_NFIELDS (type) == 2
3906 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3908 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3910 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3912 /* A struct that contains one or two floats. Each value is part
3913 in the least significant part of their floating point
3915 gdb_byte reg[MAX_REGISTER_SIZE];
3918 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
3919 field < TYPE_NFIELDS (type); field++, regnum += 2)
3921 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3924 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3926 mips_xfer_register (gdbarch, regcache,
3927 gdbarch_num_regs (gdbarch) + regnum,
3928 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3929 gdbarch_byte_order (gdbarch),
3930 readbuf, writebuf, offset);
3932 return RETURN_VALUE_REGISTER_CONVENTION;
3936 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3937 || TYPE_CODE (type) == TYPE_CODE_UNION)
3939 /* A structure or union. Extract the left justified value,
3940 regardless of the byte order. I.e. DO NOT USE
3944 for (offset = 0, regnum = MIPS_V0_REGNUM;
3945 offset < TYPE_LENGTH (type);
3946 offset += register_size (gdbarch, regnum), regnum++)
3948 int xfer = register_size (gdbarch, regnum);
3949 if (offset + xfer > TYPE_LENGTH (type))
3950 xfer = TYPE_LENGTH (type) - offset;
3952 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3953 offset, xfer, regnum);
3954 mips_xfer_register (gdbarch, regcache,
3955 gdbarch_num_regs (gdbarch) + regnum, xfer,
3956 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3958 return RETURN_VALUE_REGISTER_CONVENTION;
3963 /* A scalar extract each part but least-significant-byte
3964 justified. o32 thinks registers are 4 byte, regardless of
3968 for (offset = 0, regnum = MIPS_V0_REGNUM;
3969 offset < TYPE_LENGTH (type);
3970 offset += MIPS32_REGSIZE, regnum++)
3972 int xfer = MIPS32_REGSIZE;
3973 if (offset + xfer > TYPE_LENGTH (type))
3974 xfer = TYPE_LENGTH (type) - offset;
3976 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3977 offset, xfer, regnum);
3978 mips_xfer_register (gdbarch, regcache,
3979 gdbarch_num_regs (gdbarch) + regnum, xfer,
3980 gdbarch_byte_order (gdbarch),
3981 readbuf, writebuf, offset);
3983 return RETURN_VALUE_REGISTER_CONVENTION;
3987 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3991 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3992 struct regcache *regcache, CORE_ADDR bp_addr,
3994 struct value **args, CORE_ADDR sp,
3995 int struct_return, CORE_ADDR struct_addr)
4001 int stack_offset = 0;
4002 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4003 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4004 CORE_ADDR func_addr = find_function_addr (function, NULL);
4006 /* For shared libraries, "t9" needs to point at the function
4008 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4010 /* Set the return address register to point to the entry point of
4011 the program, where a breakpoint lies in wait. */
4012 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4014 /* First ensure that the stack and structure return address (if any)
4015 are properly aligned. The stack has to be at least 64-bit
4016 aligned even on 32-bit machines, because doubles must be 64-bit
4017 aligned. For n32 and n64, stack frames need to be 128-bit
4018 aligned, so we round to this widest known alignment. */
4020 sp = align_down (sp, 16);
4021 struct_addr = align_down (struct_addr, 16);
4023 /* Now make space on the stack for the args. */
4024 for (argnum = 0; argnum < nargs; argnum++)
4026 struct type *arg_type = check_typedef (value_type (args[argnum]));
4027 int arglen = TYPE_LENGTH (arg_type);
4029 /* Allocate space on the stack. */
4030 len += align_up (arglen, MIPS64_REGSIZE);
4032 sp -= align_up (len, 16);
4035 fprintf_unfiltered (gdb_stdlog,
4036 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4037 paddress (gdbarch, sp), (long) align_up (len, 16));
4039 /* Initialize the integer and float register pointers. */
4040 argreg = MIPS_A0_REGNUM;
4041 float_argreg = mips_fpa0_regnum (gdbarch);
4043 /* The struct_return pointer occupies the first parameter-passing reg. */
4047 fprintf_unfiltered (gdb_stdlog,
4048 "mips_o64_push_dummy_call: struct_return reg=%d %s\n",
4049 argreg, paddress (gdbarch, struct_addr));
4050 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4051 stack_offset += MIPS64_REGSIZE;
4054 /* Now load as many as possible of the first arguments into
4055 registers, and push the rest onto the stack. Loop thru args
4056 from first to last. */
4057 for (argnum = 0; argnum < nargs; argnum++)
4059 const gdb_byte *val;
4060 struct value *arg = args[argnum];
4061 struct type *arg_type = check_typedef (value_type (arg));
4062 int len = TYPE_LENGTH (arg_type);
4063 enum type_code typecode = TYPE_CODE (arg_type);
4066 fprintf_unfiltered (gdb_stdlog,
4067 "mips_o64_push_dummy_call: %d len=%d type=%d",
4068 argnum + 1, len, (int) typecode);
4070 val = value_contents (arg);
4072 /* Floating point arguments passed in registers have to be
4073 treated specially. On 32-bit architectures, doubles
4074 are passed in register pairs; the even register gets
4075 the low word, and the odd register gets the high word.
4076 On O32/O64, the first two floating point arguments are
4077 also copied to general registers, because MIPS16 functions
4078 don't use float registers for arguments. This duplication of
4079 arguments in general registers can't hurt non-MIPS16 functions
4080 because those registers are normally skipped. */
4082 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4083 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4085 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
4087 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4088 float_argreg, phex (regval, len));
4089 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
4091 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4092 argreg, phex (regval, len));
4093 regcache_cooked_write_unsigned (regcache, argreg, regval);
4095 /* Reserve space for the FP register. */
4096 stack_offset += align_up (len, MIPS64_REGSIZE);
4100 /* Copy the argument to general registers or the stack in
4101 register-sized pieces. Large arguments are split between
4102 registers and stack. */
4103 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4104 are treated specially: Irix cc passes them in registers
4105 where gcc sometimes puts them on the stack. For maximum
4106 compatibility, we will put them in both places. */
4107 int odd_sized_struct = (len > MIPS64_REGSIZE
4108 && len % MIPS64_REGSIZE != 0);
4111 /* Remember if the argument was written to the stack. */
4112 int stack_used_p = 0;
4113 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4116 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4119 /* Write this portion of the argument to the stack. */
4120 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4121 || odd_sized_struct)
4123 /* Should shorter than int integer values be
4124 promoted to int before being stored? */
4125 int longword_offset = 0;
4128 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4130 if ((typecode == TYPE_CODE_INT
4131 || typecode == TYPE_CODE_PTR
4132 || typecode == TYPE_CODE_FLT)
4134 longword_offset = MIPS64_REGSIZE - len;
4139 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4140 paddress (gdbarch, stack_offset));
4141 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4142 paddress (gdbarch, longword_offset));
4145 addr = sp + stack_offset + longword_offset;
4150 fprintf_unfiltered (gdb_stdlog, " @%s ",
4151 paddress (gdbarch, addr));
4152 for (i = 0; i < partial_len; i++)
4154 fprintf_unfiltered (gdb_stdlog, "%02x",
4158 write_memory (addr, val, partial_len);
4161 /* Note!!! This is NOT an else clause. Odd sized
4162 structs may go thru BOTH paths. */
4163 /* Write this portion of the argument to a general
4164 purpose register. */
4165 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4167 LONGEST regval = extract_signed_integer (val, partial_len,
4169 /* Value may need to be sign extended, because
4170 mips_isa_regsize() != mips_abi_regsize(). */
4172 /* A non-floating-point argument being passed in a
4173 general register. If a struct or union, and if
4174 the remaining length is smaller than the register
4175 size, we have to adjust the register value on
4178 It does not seem to be necessary to do the
4179 same for integral types. */
4181 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
4182 && partial_len < MIPS64_REGSIZE
4183 && (typecode == TYPE_CODE_STRUCT
4184 || typecode == TYPE_CODE_UNION))
4185 regval <<= ((MIPS64_REGSIZE - partial_len)
4189 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4191 phex (regval, MIPS64_REGSIZE));
4192 regcache_cooked_write_unsigned (regcache, argreg, regval);
4195 /* Prevent subsequent floating point arguments from
4196 being passed in floating point registers. */
4197 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
4203 /* Compute the the offset into the stack at which we
4204 will copy the next parameter.
4206 In older ABIs, the caller reserved space for
4207 registers that contained arguments. This was loosely
4208 refered to as their "home". Consequently, space is
4209 always allocated. */
4211 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
4215 fprintf_unfiltered (gdb_stdlog, "\n");
4218 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4220 /* Return adjusted stack pointer. */
4224 static enum return_value_convention
4225 mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type,
4226 struct type *type, struct regcache *regcache,
4227 gdb_byte *readbuf, const gdb_byte *writebuf)
4229 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4231 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4232 || TYPE_CODE (type) == TYPE_CODE_UNION
4233 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
4234 return RETURN_VALUE_STRUCT_CONVENTION;
4235 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
4237 /* A floating-point value. It fits in the least significant
4240 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4241 mips_xfer_register (gdbarch, regcache,
4242 gdbarch_num_regs (gdbarch)
4243 + mips_regnum (gdbarch)->fp0,
4245 gdbarch_byte_order (gdbarch),
4246 readbuf, writebuf, 0);
4247 return RETURN_VALUE_REGISTER_CONVENTION;
4251 /* A scalar extract each part but least-significant-byte
4255 for (offset = 0, regnum = MIPS_V0_REGNUM;
4256 offset < TYPE_LENGTH (type);
4257 offset += MIPS64_REGSIZE, regnum++)
4259 int xfer = MIPS64_REGSIZE;
4260 if (offset + xfer > TYPE_LENGTH (type))
4261 xfer = TYPE_LENGTH (type) - offset;
4263 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4264 offset, xfer, regnum);
4265 mips_xfer_register (gdbarch, regcache,
4266 gdbarch_num_regs (gdbarch) + regnum,
4267 xfer, gdbarch_byte_order (gdbarch),
4268 readbuf, writebuf, offset);
4270 return RETURN_VALUE_REGISTER_CONVENTION;
4274 /* Floating point register management.
4276 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4277 64bit operations, these early MIPS cpus treat fp register pairs
4278 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4279 registers and offer a compatibility mode that emulates the MIPS2 fp
4280 model. When operating in MIPS2 fp compat mode, later cpu's split
4281 double precision floats into two 32-bit chunks and store them in
4282 consecutive fp regs. To display 64-bit floats stored in this
4283 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4284 Throw in user-configurable endianness and you have a real mess.
4286 The way this works is:
4287 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4288 double-precision value will be split across two logical registers.
4289 The lower-numbered logical register will hold the low-order bits,
4290 regardless of the processor's endianness.
4291 - If we are on a 64-bit processor, and we are looking for a
4292 single-precision value, it will be in the low ordered bits
4293 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4294 save slot in memory.
4295 - If we are in 64-bit mode, everything is straightforward.
4297 Note that this code only deals with "live" registers at the top of the
4298 stack. We will attempt to deal with saved registers later, when
4299 the raw/cooked register interface is in place. (We need a general
4300 interface that can deal with dynamic saved register sizes -- fp
4301 regs could be 32 bits wide in one frame and 64 on the frame above
4304 /* Copy a 32-bit single-precision value from the current frame
4305 into rare_buffer. */
4308 mips_read_fp_register_single (struct frame_info *frame, int regno,
4309 gdb_byte *rare_buffer)
4311 struct gdbarch *gdbarch = get_frame_arch (frame);
4312 int raw_size = register_size (gdbarch, regno);
4313 gdb_byte *raw_buffer = alloca (raw_size);
4315 if (!frame_register_read (frame, regno, raw_buffer))
4316 error (_("can't read register %d (%s)"),
4317 regno, gdbarch_register_name (gdbarch, regno));
4320 /* We have a 64-bit value for this register. Find the low-order
4324 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4329 memcpy (rare_buffer, raw_buffer + offset, 4);
4333 memcpy (rare_buffer, raw_buffer, 4);
4337 /* Copy a 64-bit double-precision value from the current frame into
4338 rare_buffer. This may include getting half of it from the next
4342 mips_read_fp_register_double (struct frame_info *frame, int regno,
4343 gdb_byte *rare_buffer)
4345 struct gdbarch *gdbarch = get_frame_arch (frame);
4346 int raw_size = register_size (gdbarch, regno);
4348 if (raw_size == 8 && !mips2_fp_compat (frame))
4350 /* We have a 64-bit value for this register, and we should use
4352 if (!frame_register_read (frame, regno, rare_buffer))
4353 error (_("can't read register %d (%s)"),
4354 regno, gdbarch_register_name (gdbarch, regno));
4358 int rawnum = regno % gdbarch_num_regs (gdbarch);
4360 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
4361 internal_error (__FILE__, __LINE__,
4362 _("mips_read_fp_register_double: bad access to "
4363 "odd-numbered FP register"));
4365 /* mips_read_fp_register_single will find the correct 32 bits from
4367 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4369 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4370 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4374 mips_read_fp_register_single (frame, regno, rare_buffer);
4375 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4381 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4383 { /* do values for FP (float) regs */
4384 struct gdbarch *gdbarch = get_frame_arch (frame);
4385 gdb_byte *raw_buffer;
4386 double doub, flt1; /* doubles extracted from raw hex data */
4389 raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0));
4391 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
4392 fprintf_filtered (file, "%*s",
4393 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
4396 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
4398 struct value_print_options opts;
4400 /* 4-byte registers: Print hex and floating. Also print even
4401 numbered registers as doubles. */
4402 mips_read_fp_register_single (frame, regnum, raw_buffer);
4403 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv1);
4405 get_formatted_print_options (&opts, 'x');
4406 print_scalar_formatted (raw_buffer,
4407 builtin_type (gdbarch)->builtin_uint32,
4410 fprintf_filtered (file, " flt: ");
4412 fprintf_filtered (file, " <invalid float> ");
4414 fprintf_filtered (file, "%-17.9g", flt1);
4416 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
4418 mips_read_fp_register_double (frame, regnum, raw_buffer);
4419 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
4422 fprintf_filtered (file, " dbl: ");
4424 fprintf_filtered (file, "<invalid double>");
4426 fprintf_filtered (file, "%-24.17g", doub);
4431 struct value_print_options opts;
4433 /* Eight byte registers: print each one as hex, float and double. */
4434 mips_read_fp_register_single (frame, regnum, raw_buffer);
4435 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
4438 mips_read_fp_register_double (frame, regnum, raw_buffer);
4439 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
4442 get_formatted_print_options (&opts, 'x');
4443 print_scalar_formatted (raw_buffer,
4444 builtin_type (gdbarch)->builtin_uint64,
4447 fprintf_filtered (file, " flt: ");
4449 fprintf_filtered (file, "<invalid float>");
4451 fprintf_filtered (file, "%-17.9g", flt1);
4453 fprintf_filtered (file, " dbl: ");
4455 fprintf_filtered (file, "<invalid double>");
4457 fprintf_filtered (file, "%-24.17g", doub);
4462 mips_print_register (struct ui_file *file, struct frame_info *frame,
4465 struct gdbarch *gdbarch = get_frame_arch (frame);
4466 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4468 struct value_print_options opts;
4470 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4472 mips_print_fp_register (file, frame, regnum);
4476 /* Get the data in raw format. */
4477 if (!frame_register_read (frame, regnum, raw_buffer))
4479 fprintf_filtered (file, "%s: [Invalid]",
4480 gdbarch_register_name (gdbarch, regnum));
4484 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
4486 /* The problem with printing numeric register names (r26, etc.) is that
4487 the user can't use them on input. Probably the best solution is to
4488 fix it so that either the numeric or the funky (a2, etc.) names
4489 are accepted on input. */
4490 if (regnum < MIPS_NUMREGS)
4491 fprintf_filtered (file, "(r%d): ", regnum);
4493 fprintf_filtered (file, ": ");
4495 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4497 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4501 get_formatted_print_options (&opts, 'x');
4502 print_scalar_formatted (raw_buffer + offset,
4503 register_type (gdbarch, regnum), &opts, 0,
4507 /* Replacement for generic do_registers_info.
4508 Print regs in pretty columns. */
4511 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4514 fprintf_filtered (file, " ");
4515 mips_print_fp_register (file, frame, regnum);
4516 fprintf_filtered (file, "\n");
4521 /* Print a row's worth of GP (int) registers, with name labels above */
4524 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4527 struct gdbarch *gdbarch = get_frame_arch (frame);
4528 /* do values for GP (int) regs */
4529 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4530 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4534 /* For GP registers, we print a separate row of names above the vals */
4535 for (col = 0, regnum = start_regnum;
4536 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4537 + gdbarch_num_pseudo_regs (gdbarch);
4540 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4541 continue; /* unused register */
4542 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4544 break; /* end the row: reached FP register */
4545 /* Large registers are handled separately. */
4546 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4549 break; /* End the row before this register. */
4551 /* Print this register on a row by itself. */
4552 mips_print_register (file, frame, regnum);
4553 fprintf_filtered (file, "\n");
4557 fprintf_filtered (file, " ");
4558 fprintf_filtered (file,
4559 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
4560 gdbarch_register_name (gdbarch, regnum));
4567 /* print the R0 to R31 names */
4568 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
4569 fprintf_filtered (file, "\n R%-4d",
4570 start_regnum % gdbarch_num_regs (gdbarch));
4572 fprintf_filtered (file, "\n ");
4574 /* now print the values in hex, 4 or 8 to the row */
4575 for (col = 0, regnum = start_regnum;
4576 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4577 + gdbarch_num_pseudo_regs (gdbarch);
4580 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4581 continue; /* unused register */
4582 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4584 break; /* end row: reached FP register */
4585 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4586 break; /* End row: large register. */
4588 /* OK: get the data in raw format. */
4589 if (!frame_register_read (frame, regnum, raw_buffer))
4590 error (_("can't read register %d (%s)"),
4591 regnum, gdbarch_register_name (gdbarch, regnum));
4592 /* pad small registers */
4594 byte < (mips_abi_regsize (gdbarch)
4595 - register_size (gdbarch, regnum)); byte++)
4596 printf_filtered (" ");
4597 /* Now print the register value in hex, endian order. */
4598 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4600 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4601 byte < register_size (gdbarch, regnum); byte++)
4602 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4604 for (byte = register_size (gdbarch, regnum) - 1;
4606 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4607 fprintf_filtered (file, " ");
4610 if (col > 0) /* ie. if we actually printed anything... */
4611 fprintf_filtered (file, "\n");
4616 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4619 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4620 struct frame_info *frame, int regnum, int all)
4622 if (regnum != -1) /* do one specified register */
4624 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
4625 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
4626 error (_("Not a valid register for the current processor type"));
4628 mips_print_register (file, frame, regnum);
4629 fprintf_filtered (file, "\n");
4632 /* do all (or most) registers */
4634 regnum = gdbarch_num_regs (gdbarch);
4635 while (regnum < gdbarch_num_regs (gdbarch)
4636 + gdbarch_num_pseudo_regs (gdbarch))
4638 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4641 if (all) /* true for "INFO ALL-REGISTERS" command */
4642 regnum = print_fp_register_row (file, frame, regnum);
4644 regnum += MIPS_NUMREGS; /* skip floating point regs */
4647 regnum = print_gp_register_row (file, frame, regnum);
4652 /* Is this a branch with a delay slot? */
4655 is_delayed (unsigned long insn)
4658 for (i = 0; i < NUMOPCODES; ++i)
4659 if (mips_opcodes[i].pinfo != INSN_MACRO
4660 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4662 return (i < NUMOPCODES
4663 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4664 | INSN_COND_BRANCH_DELAY
4665 | INSN_COND_BRANCH_LIKELY)));
4669 mips_single_step_through_delay (struct gdbarch *gdbarch,
4670 struct frame_info *frame)
4672 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4673 CORE_ADDR pc = get_frame_pc (frame);
4674 gdb_byte buf[MIPS_INSN32_SIZE];
4676 /* There is no branch delay slot on MIPS16. */
4677 if (mips_pc_is_mips16 (pc))
4680 if (!breakpoint_here_p (pc + 4))
4683 if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf))
4684 /* If error reading memory, guess that it is not a delayed
4687 return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order));
4690 /* To skip prologues, I use this predicate. Returns either PC itself
4691 if the code at PC does not look like a function prologue; otherwise
4692 returns an address that (if we're lucky) follows the prologue. If
4693 LENIENT, then we must skip everything which is involved in setting
4694 up the frame (it's OK to skip more, just so long as we don't skip
4695 anything which might clobber the registers which are being saved.
4696 We must skip more in the case where part of the prologue is in the
4697 delay slot of a non-prologue instruction). */
4700 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
4703 CORE_ADDR func_addr;
4705 /* See if we can determine the end of the prologue via the symbol table.
4706 If so, then return either PC, or the PC after the prologue, whichever
4708 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
4710 CORE_ADDR post_prologue_pc
4711 = skip_prologue_using_sal (gdbarch, func_addr);
4712 if (post_prologue_pc != 0)
4713 return max (pc, post_prologue_pc);
4716 /* Can't determine prologue from the symbol table, need to examine
4719 /* Find an upper limit on the function prologue using the debug
4720 information. If the debug information could not be used to provide
4721 that bound, then use an arbitrary large number as the upper bound. */
4722 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4724 limit_pc = pc + 100; /* Magic. */
4726 if (mips_pc_is_mips16 (pc))
4727 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
4729 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
4732 /* Check whether the PC is in a function epilogue (32-bit version).
4733 This is a helper function for mips_in_function_epilogue_p. */
4735 mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4737 CORE_ADDR func_addr = 0, func_end = 0;
4739 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4741 /* The MIPS epilogue is max. 12 bytes long. */
4742 CORE_ADDR addr = func_end - 12;
4744 if (addr < func_addr + 4)
4745 addr = func_addr + 4;
4749 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
4751 unsigned long high_word;
4754 inst = mips_fetch_instruction (gdbarch, pc);
4755 high_word = (inst >> 16) & 0xffff;
4757 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
4758 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
4759 && inst != 0x03e00008 /* jr $ra */
4760 && inst != 0x00000000) /* nop */
4770 /* Check whether the PC is in a function epilogue (16-bit version).
4771 This is a helper function for mips_in_function_epilogue_p. */
4773 mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4775 CORE_ADDR func_addr = 0, func_end = 0;
4777 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4779 /* The MIPS epilogue is max. 12 bytes long. */
4780 CORE_ADDR addr = func_end - 12;
4782 if (addr < func_addr + 4)
4783 addr = func_addr + 4;
4787 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
4789 unsigned short inst;
4791 inst = mips_fetch_instruction (gdbarch, pc);
4793 if ((inst & 0xf800) == 0xf000) /* extend */
4796 if (inst != 0x6300 /* addiu $sp,offset */
4797 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
4798 && inst != 0xe820 /* jr $ra */
4799 && inst != 0xe8a0 /* jrc $ra */
4800 && inst != 0x6500) /* nop */
4810 /* The epilogue is defined here as the area at the end of a function,
4811 after an instruction which destroys the function's stack frame. */
4813 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4815 if (mips_pc_is_mips16 (pc))
4816 return mips16_in_function_epilogue_p (gdbarch, pc);
4818 return mips32_in_function_epilogue_p (gdbarch, pc);
4821 /* Root of all "set mips "/"show mips " commands. This will eventually be
4822 used for all MIPS-specific commands. */
4825 show_mips_command (char *args, int from_tty)
4827 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4831 set_mips_command (char *args, int from_tty)
4834 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4835 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4838 /* Commands to show/set the MIPS FPU type. */
4841 show_mipsfpu_command (char *args, int from_tty)
4845 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
4848 ("The MIPS floating-point coprocessor is unknown "
4849 "because the current architecture is not MIPS.\n");
4853 switch (MIPS_FPU_TYPE (target_gdbarch))
4855 case MIPS_FPU_SINGLE:
4856 fpu = "single-precision";
4858 case MIPS_FPU_DOUBLE:
4859 fpu = "double-precision";
4862 fpu = "absent (none)";
4865 internal_error (__FILE__, __LINE__, _("bad switch"));
4867 if (mips_fpu_type_auto)
4869 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4873 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4878 set_mipsfpu_command (char *args, int from_tty)
4881 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4882 show_mipsfpu_command (args, from_tty);
4886 set_mipsfpu_single_command (char *args, int from_tty)
4888 struct gdbarch_info info;
4889 gdbarch_info_init (&info);
4890 mips_fpu_type = MIPS_FPU_SINGLE;
4891 mips_fpu_type_auto = 0;
4892 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4893 instead of relying on globals. Doing that would let generic code
4894 handle the search for this specific architecture. */
4895 if (!gdbarch_update_p (info))
4896 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4900 set_mipsfpu_double_command (char *args, int from_tty)
4902 struct gdbarch_info info;
4903 gdbarch_info_init (&info);
4904 mips_fpu_type = MIPS_FPU_DOUBLE;
4905 mips_fpu_type_auto = 0;
4906 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4907 instead of relying on globals. Doing that would let generic code
4908 handle the search for this specific architecture. */
4909 if (!gdbarch_update_p (info))
4910 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4914 set_mipsfpu_none_command (char *args, int from_tty)
4916 struct gdbarch_info info;
4917 gdbarch_info_init (&info);
4918 mips_fpu_type = MIPS_FPU_NONE;
4919 mips_fpu_type_auto = 0;
4920 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4921 instead of relying on globals. Doing that would let generic code
4922 handle the search for this specific architecture. */
4923 if (!gdbarch_update_p (info))
4924 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4928 set_mipsfpu_auto_command (char *args, int from_tty)
4930 mips_fpu_type_auto = 1;
4933 /* Attempt to identify the particular processor model by reading the
4934 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4935 the relevant processor still exists (it dates back to '94) and
4936 secondly this is not the way to do this. The processor type should
4937 be set by forcing an architecture change. */
4940 deprecated_mips_set_processor_regs_hack (void)
4942 struct regcache *regcache = get_current_regcache ();
4943 struct gdbarch *gdbarch = get_regcache_arch (regcache);
4944 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4947 regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid);
4948 if ((prid & ~0xf) == 0x700)
4949 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4952 /* Just like reinit_frame_cache, but with the right arguments to be
4953 callable as an sfunc. */
4956 reinit_frame_cache_sfunc (char *args, int from_tty,
4957 struct cmd_list_element *c)
4959 reinit_frame_cache ();
4963 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4965 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4966 disassembler needs to be able to locally determine the ISA, and
4967 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4969 if (mips_pc_is_mips16 (memaddr))
4970 info->mach = bfd_mach_mips16;
4972 /* Round down the instruction address to the appropriate boundary. */
4973 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4975 /* Set the disassembler options. */
4976 if (!info->disassembler_options)
4977 /* This string is not recognized explicitly by the disassembler,
4978 but it tells the disassembler to not try to guess the ABI from
4979 the bfd elf headers, such that, if the user overrides the ABI
4980 of a program linked as NewABI, the disassembly will follow the
4981 register naming conventions specified by the user. */
4982 info->disassembler_options = "gpr-names=32";
4984 /* Call the appropriate disassembler based on the target endian-ness. */
4985 if (info->endian == BFD_ENDIAN_BIG)
4986 return print_insn_big_mips (memaddr, info);
4988 return print_insn_little_mips (memaddr, info);
4992 gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
4994 /* Set up the disassembler info, so that we get the right
4995 register names from libopcodes. */
4996 info->disassembler_options = "gpr-names=n32";
4997 info->flavour = bfd_target_elf_flavour;
4999 return gdb_print_insn_mips (memaddr, info);
5003 gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
5005 /* Set up the disassembler info, so that we get the right
5006 register names from libopcodes. */
5007 info->disassembler_options = "gpr-names=64";
5008 info->flavour = bfd_target_elf_flavour;
5010 return gdb_print_insn_mips (memaddr, info);
5013 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
5014 counter value to determine whether a 16- or 32-bit breakpoint should be used.
5015 It returns a pointer to a string of bytes that encode a breakpoint
5016 instruction, stores the length of the string to *lenptr, and adjusts pc (if
5017 necessary) to point to the actual memory location where the breakpoint
5018 should be inserted. */
5020 static const gdb_byte *
5021 mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
5023 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5025 if (mips_pc_is_mips16 (*pcptr))
5027 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
5028 *pcptr = unmake_mips16_addr (*pcptr);
5029 *lenptr = sizeof (mips16_big_breakpoint);
5030 return mips16_big_breakpoint;
5034 /* The IDT board uses an unusual breakpoint value, and
5035 sometimes gets confused when it sees the usual MIPS
5036 breakpoint instruction. */
5037 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
5038 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
5039 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
5041 *lenptr = sizeof (big_breakpoint);
5043 if (strcmp (target_shortname, "mips") == 0)
5044 return idt_big_breakpoint;
5045 else if (strcmp (target_shortname, "ddb") == 0
5046 || strcmp (target_shortname, "pmon") == 0
5047 || strcmp (target_shortname, "lsi") == 0)
5048 return pmon_big_breakpoint;
5050 return big_breakpoint;
5055 if (mips_pc_is_mips16 (*pcptr))
5057 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
5058 *pcptr = unmake_mips16_addr (*pcptr);
5059 *lenptr = sizeof (mips16_little_breakpoint);
5060 return mips16_little_breakpoint;
5064 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
5065 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
5066 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
5068 *lenptr = sizeof (little_breakpoint);
5070 if (strcmp (target_shortname, "mips") == 0)
5071 return idt_little_breakpoint;
5072 else if (strcmp (target_shortname, "ddb") == 0
5073 || strcmp (target_shortname, "pmon") == 0
5074 || strcmp (target_shortname, "lsi") == 0)
5075 return pmon_little_breakpoint;
5077 return little_breakpoint;
5082 /* If PC is in a mips16 call or return stub, return the address of the target
5083 PC, which is either the callee or the caller. There are several
5084 cases which must be handled:
5086 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5087 target PC is in $31 ($ra).
5088 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5089 and the target PC is in $2.
5090 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5091 before the jal instruction, this is effectively a call stub
5092 and the the target PC is in $2. Otherwise this is effectively
5093 a return stub and the target PC is in $18.
5095 See the source code for the stubs in gcc/config/mips/mips16.S for
5099 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5101 struct gdbarch *gdbarch = get_frame_arch (frame);
5103 CORE_ADDR start_addr;
5105 /* Find the starting address and name of the function containing the PC. */
5106 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5109 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5110 target PC is in $31 ($ra). */
5111 if (strcmp (name, "__mips16_ret_sf") == 0
5112 || strcmp (name, "__mips16_ret_df") == 0)
5113 return get_frame_register_signed (frame, MIPS_RA_REGNUM);
5115 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5117 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5118 and the target PC is in $2. */
5119 if (name[19] >= '0' && name[19] <= '9')
5120 return get_frame_register_signed (frame, 2);
5122 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5123 before the jal instruction, this is effectively a call stub
5124 and the the target PC is in $2. Otherwise this is effectively
5125 a return stub and the target PC is in $18. */
5126 else if (name[19] == 's' || name[19] == 'd')
5128 if (pc == start_addr)
5130 /* Check if the target of the stub is a compiler-generated
5131 stub. Such a stub for a function bar might have a name
5132 like __fn_stub_bar, and might look like this:
5137 la $1,bar (becomes a lui/addiu pair)
5139 So scan down to the lui/addi and extract the target
5140 address from those two instructions. */
5142 CORE_ADDR target_pc = get_frame_register_signed (frame, 2);
5146 /* See if the name of the target function is __fn_stub_*. */
5147 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
5150 if (strncmp (name, "__fn_stub_", 10) != 0
5151 && strcmp (name, "etext") != 0
5152 && strcmp (name, "_etext") != 0)
5155 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5156 The limit on the search is arbitrarily set to 20
5157 instructions. FIXME. */
5158 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE)
5160 inst = mips_fetch_instruction (gdbarch, target_pc);
5161 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5162 pc = (inst << 16) & 0xffff0000; /* high word */
5163 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5164 return pc | (inst & 0xffff); /* low word */
5167 /* Couldn't find the lui/addui pair, so return stub address. */
5171 /* This is the 'return' part of a call stub. The return
5172 address is in $r18. */
5173 return get_frame_register_signed (frame, 18);
5176 return 0; /* not a stub */
5179 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5180 PC of the stub target. The stub just loads $t9 and jumps to it,
5181 so that $t9 has the correct value at function entry. */
5184 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5186 struct gdbarch *gdbarch = get_frame_arch (frame);
5187 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5188 struct minimal_symbol *msym;
5190 gdb_byte stub_code[16];
5191 int32_t stub_words[4];
5193 /* The stub for foo is named ".pic.foo", and is either two
5194 instructions inserted before foo or a three instruction sequence
5195 which jumps to foo. */
5196 msym = lookup_minimal_symbol_by_pc (pc);
5198 || SYMBOL_VALUE_ADDRESS (msym) != pc
5199 || SYMBOL_LINKAGE_NAME (msym) == NULL
5200 || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0)
5203 /* A two-instruction header. */
5204 if (MSYMBOL_SIZE (msym) == 8)
5207 /* A three-instruction (plus delay slot) trampoline. */
5208 if (MSYMBOL_SIZE (msym) == 16)
5210 if (target_read_memory (pc, stub_code, 16) != 0)
5212 for (i = 0; i < 4; i++)
5213 stub_words[i] = extract_unsigned_integer (stub_code + i * 4,
5216 /* A stub contains these instructions:
5219 addiu t9, t9, %lo(target)
5222 This works even for N64, since stubs are only generated with
5224 if ((stub_words[0] & 0xffff0000U) == 0x3c190000
5225 && (stub_words[1] & 0xfc000000U) == 0x08000000
5226 && (stub_words[2] & 0xffff0000U) == 0x27390000
5227 && stub_words[3] == 0x00000000)
5228 return (((stub_words[0] & 0x0000ffff) << 16)
5229 + (stub_words[2] & 0x0000ffff));
5232 /* Not a recognized stub. */
5237 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5239 CORE_ADDR target_pc;
5241 target_pc = mips_skip_mips16_trampoline_code (frame, pc);
5245 target_pc = find_solib_trampoline_target (frame, pc);
5249 target_pc = mips_skip_pic_trampoline_code (frame, pc);
5256 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5257 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5260 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
5263 if (num >= 0 && num < 32)
5265 else if (num >= 38 && num < 70)
5266 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
5268 regnum = mips_regnum (gdbarch)->hi;
5270 regnum = mips_regnum (gdbarch)->lo;
5272 /* This will hopefully (eventually) provoke a warning. Should
5273 we be calling complaint() here? */
5274 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5275 return gdbarch_num_regs (gdbarch) + regnum;
5279 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5280 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5283 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
5286 if (num >= 0 && num < 32)
5288 else if (num >= 32 && num < 64)
5289 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
5291 regnum = mips_regnum (gdbarch)->hi;
5293 regnum = mips_regnum (gdbarch)->lo;
5295 /* This will hopefully (eventually) provoke a warning. Should we
5296 be calling complaint() here? */
5297 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5298 return gdbarch_num_regs (gdbarch) + regnum;
5302 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
5304 /* Only makes sense to supply raw registers. */
5305 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
5306 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5307 decide if it is valid. Should instead define a standard sim/gdb
5308 register numbering scheme. */
5309 if (gdbarch_register_name (gdbarch,
5310 gdbarch_num_regs (gdbarch) + regnum) != NULL
5311 && gdbarch_register_name (gdbarch,
5312 gdbarch_num_regs (gdbarch) + regnum)[0] != '\0')
5315 return LEGACY_SIM_REGNO_IGNORE;
5319 /* Convert an integer into an address. Extracting the value signed
5320 guarantees a correctly sign extended address. */
5323 mips_integer_to_address (struct gdbarch *gdbarch,
5324 struct type *type, const gdb_byte *buf)
5326 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5327 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
5330 /* Dummy virtual frame pointer method. This is no more or less accurate
5331 than most other architectures; we just need to be explicit about it,
5332 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5333 an assertion failure. */
5336 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
5337 CORE_ADDR pc, int *reg, LONGEST *offset)
5339 *reg = MIPS_SP_REGNUM;
5344 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5346 enum mips_abi *abip = (enum mips_abi *) obj;
5347 const char *name = bfd_get_section_name (abfd, sect);
5349 if (*abip != MIPS_ABI_UNKNOWN)
5352 if (strncmp (name, ".mdebug.", 8) != 0)
5355 if (strcmp (name, ".mdebug.abi32") == 0)
5356 *abip = MIPS_ABI_O32;
5357 else if (strcmp (name, ".mdebug.abiN32") == 0)
5358 *abip = MIPS_ABI_N32;
5359 else if (strcmp (name, ".mdebug.abi64") == 0)
5360 *abip = MIPS_ABI_N64;
5361 else if (strcmp (name, ".mdebug.abiO64") == 0)
5362 *abip = MIPS_ABI_O64;
5363 else if (strcmp (name, ".mdebug.eabi32") == 0)
5364 *abip = MIPS_ABI_EABI32;
5365 else if (strcmp (name, ".mdebug.eabi64") == 0)
5366 *abip = MIPS_ABI_EABI64;
5368 warning (_("unsupported ABI %s."), name + 8);
5372 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
5374 int *lbp = (int *) obj;
5375 const char *name = bfd_get_section_name (abfd, sect);
5377 if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
5379 else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
5381 else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
5382 warning (_("unrecognized .gcc_compiled_longXX"));
5385 static enum mips_abi
5386 global_mips_abi (void)
5390 for (i = 0; mips_abi_strings[i] != NULL; i++)
5391 if (mips_abi_strings[i] == mips_abi_string)
5392 return (enum mips_abi) i;
5394 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
5398 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
5400 /* If the size matches the set of 32-bit or 64-bit integer registers,
5401 assume that's what we've got. */
5402 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
5403 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
5405 /* If the size matches the full set of registers GDB traditionally
5406 knows about, including floating point, for either 32-bit or
5407 64-bit, assume that's what we've got. */
5408 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
5409 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
5411 /* Otherwise we don't have a useful guess. */
5414 static struct value *
5415 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
5417 const int *reg_p = baton;
5418 return value_of_register (*reg_p, frame);
5421 static struct gdbarch *
5422 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5424 struct gdbarch *gdbarch;
5425 struct gdbarch_tdep *tdep;
5427 enum mips_abi mips_abi, found_abi, wanted_abi;
5429 enum mips_fpu_type fpu_type;
5430 struct tdesc_arch_data *tdesc_data = NULL;
5431 int elf_fpu_type = 0;
5433 /* Check any target description for validity. */
5434 if (tdesc_has_registers (info.target_desc))
5436 static const char *const mips_gprs[] = {
5437 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5438 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5439 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5440 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5442 static const char *const mips_fprs[] = {
5443 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5444 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5445 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5446 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5449 const struct tdesc_feature *feature;
5452 feature = tdesc_find_feature (info.target_desc,
5453 "org.gnu.gdb.mips.cpu");
5454 if (feature == NULL)
5457 tdesc_data = tdesc_data_alloc ();
5460 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
5461 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
5465 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5466 MIPS_EMBED_LO_REGNUM, "lo");
5467 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5468 MIPS_EMBED_HI_REGNUM, "hi");
5469 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5470 MIPS_EMBED_PC_REGNUM, "pc");
5474 tdesc_data_cleanup (tdesc_data);
5478 feature = tdesc_find_feature (info.target_desc,
5479 "org.gnu.gdb.mips.cp0");
5480 if (feature == NULL)
5482 tdesc_data_cleanup (tdesc_data);
5487 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5488 MIPS_EMBED_BADVADDR_REGNUM,
5490 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5491 MIPS_PS_REGNUM, "status");
5492 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5493 MIPS_EMBED_CAUSE_REGNUM, "cause");
5497 tdesc_data_cleanup (tdesc_data);
5501 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5502 backend is not prepared for that, though. */
5503 feature = tdesc_find_feature (info.target_desc,
5504 "org.gnu.gdb.mips.fpu");
5505 if (feature == NULL)
5507 tdesc_data_cleanup (tdesc_data);
5512 for (i = 0; i < 32; i++)
5513 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5514 i + MIPS_EMBED_FP0_REGNUM,
5517 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5518 MIPS_EMBED_FP0_REGNUM + 32, "fcsr");
5519 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5520 MIPS_EMBED_FP0_REGNUM + 33, "fir");
5524 tdesc_data_cleanup (tdesc_data);
5528 /* It would be nice to detect an attempt to use a 64-bit ABI
5529 when only 32-bit registers are provided. */
5532 /* First of all, extract the elf_flags, if available. */
5533 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5534 elf_flags = elf_elfheader (info.abfd)->e_flags;
5535 else if (arches != NULL)
5536 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5540 fprintf_unfiltered (gdb_stdlog,
5541 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5543 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5544 switch ((elf_flags & EF_MIPS_ABI))
5546 case E_MIPS_ABI_O32:
5547 found_abi = MIPS_ABI_O32;
5549 case E_MIPS_ABI_O64:
5550 found_abi = MIPS_ABI_O64;
5552 case E_MIPS_ABI_EABI32:
5553 found_abi = MIPS_ABI_EABI32;
5555 case E_MIPS_ABI_EABI64:
5556 found_abi = MIPS_ABI_EABI64;
5559 if ((elf_flags & EF_MIPS_ABI2))
5560 found_abi = MIPS_ABI_N32;
5562 found_abi = MIPS_ABI_UNKNOWN;
5566 /* GCC creates a pseudo-section whose name describes the ABI. */
5567 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5568 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5570 /* If we have no useful BFD information, use the ABI from the last
5571 MIPS architecture (if there is one). */
5572 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5573 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5575 /* Try the architecture for any hint of the correct ABI. */
5576 if (found_abi == MIPS_ABI_UNKNOWN
5577 && info.bfd_arch_info != NULL
5578 && info.bfd_arch_info->arch == bfd_arch_mips)
5580 switch (info.bfd_arch_info->mach)
5582 case bfd_mach_mips3900:
5583 found_abi = MIPS_ABI_EABI32;
5585 case bfd_mach_mips4100:
5586 case bfd_mach_mips5000:
5587 found_abi = MIPS_ABI_EABI64;
5589 case bfd_mach_mips8000:
5590 case bfd_mach_mips10000:
5591 /* On Irix, ELF64 executables use the N64 ABI. The
5592 pseudo-sections which describe the ABI aren't present
5593 on IRIX. (Even for executables created by gcc.) */
5594 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5595 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5596 found_abi = MIPS_ABI_N64;
5598 found_abi = MIPS_ABI_N32;
5603 /* Default 64-bit objects to N64 instead of O32. */
5604 if (found_abi == MIPS_ABI_UNKNOWN
5605 && info.abfd != NULL
5606 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5607 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5608 found_abi = MIPS_ABI_N64;
5611 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5614 /* What has the user specified from the command line? */
5615 wanted_abi = global_mips_abi ();
5617 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5620 /* Now that we have found what the ABI for this binary would be,
5621 check whether the user is overriding it. */
5622 if (wanted_abi != MIPS_ABI_UNKNOWN)
5623 mips_abi = wanted_abi;
5624 else if (found_abi != MIPS_ABI_UNKNOWN)
5625 mips_abi = found_abi;
5627 mips_abi = MIPS_ABI_O32;
5629 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5632 /* Also used when doing an architecture lookup. */
5634 fprintf_unfiltered (gdb_stdlog,
5635 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5636 mips64_transfers_32bit_regs_p);
5638 /* Determine the MIPS FPU type. */
5641 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5642 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5643 Tag_GNU_MIPS_ABI_FP);
5644 #endif /* HAVE_ELF */
5646 if (!mips_fpu_type_auto)
5647 fpu_type = mips_fpu_type;
5648 else if (elf_fpu_type != 0)
5650 switch (elf_fpu_type)
5653 fpu_type = MIPS_FPU_DOUBLE;
5656 fpu_type = MIPS_FPU_SINGLE;
5660 /* Soft float or unknown. */
5661 fpu_type = MIPS_FPU_NONE;
5665 else if (info.bfd_arch_info != NULL
5666 && info.bfd_arch_info->arch == bfd_arch_mips)
5667 switch (info.bfd_arch_info->mach)
5669 case bfd_mach_mips3900:
5670 case bfd_mach_mips4100:
5671 case bfd_mach_mips4111:
5672 case bfd_mach_mips4120:
5673 fpu_type = MIPS_FPU_NONE;
5675 case bfd_mach_mips4650:
5676 fpu_type = MIPS_FPU_SINGLE;
5679 fpu_type = MIPS_FPU_DOUBLE;
5682 else if (arches != NULL)
5683 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5685 fpu_type = MIPS_FPU_DOUBLE;
5687 fprintf_unfiltered (gdb_stdlog,
5688 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5690 /* Check for blatant incompatibilities. */
5692 /* If we have only 32-bit registers, then we can't debug a 64-bit
5694 if (info.target_desc
5695 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
5696 && mips_abi != MIPS_ABI_EABI32
5697 && mips_abi != MIPS_ABI_O32)
5699 if (tdesc_data != NULL)
5700 tdesc_data_cleanup (tdesc_data);
5704 /* try to find a pre-existing architecture */
5705 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5707 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5709 /* MIPS needs to be pedantic about which ABI the object is
5711 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5713 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5715 /* Need to be pedantic about which register virtual size is
5717 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5718 != mips64_transfers_32bit_regs_p)
5720 /* Be pedantic about which FPU is selected. */
5721 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5724 if (tdesc_data != NULL)
5725 tdesc_data_cleanup (tdesc_data);
5726 return arches->gdbarch;
5729 /* Need a new architecture. Fill in a target specific vector. */
5730 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5731 gdbarch = gdbarch_alloc (&info, tdep);
5732 tdep->elf_flags = elf_flags;
5733 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5734 tdep->found_abi = found_abi;
5735 tdep->mips_abi = mips_abi;
5736 tdep->mips_fpu_type = fpu_type;
5737 tdep->register_size_valid_p = 0;
5738 tdep->register_size = 0;
5740 if (info.target_desc)
5742 /* Some useful properties can be inferred from the target. */
5743 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
5745 tdep->register_size_valid_p = 1;
5746 tdep->register_size = 4;
5748 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
5750 tdep->register_size_valid_p = 1;
5751 tdep->register_size = 8;
5755 /* Initially set everything according to the default ABI/ISA. */
5756 set_gdbarch_short_bit (gdbarch, 16);
5757 set_gdbarch_int_bit (gdbarch, 32);
5758 set_gdbarch_float_bit (gdbarch, 32);
5759 set_gdbarch_double_bit (gdbarch, 64);
5760 set_gdbarch_long_double_bit (gdbarch, 64);
5761 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5762 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5763 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5765 set_gdbarch_elf_make_msymbol_special (gdbarch,
5766 mips_elf_make_msymbol_special);
5768 /* Fill in the OS dependant register numbers and names. */
5770 const char **reg_names;
5771 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
5772 struct mips_regnum);
5773 if (tdesc_has_registers (info.target_desc))
5775 regnum->lo = MIPS_EMBED_LO_REGNUM;
5776 regnum->hi = MIPS_EMBED_HI_REGNUM;
5777 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5778 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5779 regnum->pc = MIPS_EMBED_PC_REGNUM;
5780 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5781 regnum->fp_control_status = 70;
5782 regnum->fp_implementation_revision = 71;
5783 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
5786 else if (info.osabi == GDB_OSABI_IRIX)
5791 regnum->badvaddr = 66;
5794 regnum->fp_control_status = 69;
5795 regnum->fp_implementation_revision = 70;
5797 reg_names = mips_irix_reg_names;
5801 regnum->lo = MIPS_EMBED_LO_REGNUM;
5802 regnum->hi = MIPS_EMBED_HI_REGNUM;
5803 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5804 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5805 regnum->pc = MIPS_EMBED_PC_REGNUM;
5806 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5807 regnum->fp_control_status = 70;
5808 regnum->fp_implementation_revision = 71;
5810 if (info.bfd_arch_info != NULL
5811 && info.bfd_arch_info->mach == bfd_mach_mips3900)
5812 reg_names = mips_tx39_reg_names;
5814 reg_names = mips_generic_reg_names;
5816 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5817 replaced by gdbarch_read_pc? */
5818 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
5819 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
5820 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
5821 set_gdbarch_num_regs (gdbarch, num_regs);
5822 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5823 set_gdbarch_register_name (gdbarch, mips_register_name);
5824 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
5825 tdep->mips_processor_reg_names = reg_names;
5826 tdep->regnum = regnum;
5832 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5833 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
5834 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5835 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5836 tdep->default_mask_address_p = 0;
5837 set_gdbarch_long_bit (gdbarch, 32);
5838 set_gdbarch_ptr_bit (gdbarch, 32);
5839 set_gdbarch_long_long_bit (gdbarch, 64);
5842 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5843 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
5844 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5845 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5846 tdep->default_mask_address_p = 0;
5847 set_gdbarch_long_bit (gdbarch, 32);
5848 set_gdbarch_ptr_bit (gdbarch, 32);
5849 set_gdbarch_long_long_bit (gdbarch, 64);
5851 case MIPS_ABI_EABI32:
5852 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5853 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5854 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5855 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5856 tdep->default_mask_address_p = 0;
5857 set_gdbarch_long_bit (gdbarch, 32);
5858 set_gdbarch_ptr_bit (gdbarch, 32);
5859 set_gdbarch_long_long_bit (gdbarch, 64);
5861 case MIPS_ABI_EABI64:
5862 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5863 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5864 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5865 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5866 tdep->default_mask_address_p = 0;
5867 set_gdbarch_long_bit (gdbarch, 64);
5868 set_gdbarch_ptr_bit (gdbarch, 64);
5869 set_gdbarch_long_long_bit (gdbarch, 64);
5872 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5873 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5874 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5875 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5876 tdep->default_mask_address_p = 0;
5877 set_gdbarch_long_bit (gdbarch, 32);
5878 set_gdbarch_ptr_bit (gdbarch, 32);
5879 set_gdbarch_long_long_bit (gdbarch, 64);
5880 set_gdbarch_long_double_bit (gdbarch, 128);
5881 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
5884 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5885 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5886 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5887 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5888 tdep->default_mask_address_p = 0;
5889 set_gdbarch_long_bit (gdbarch, 64);
5890 set_gdbarch_ptr_bit (gdbarch, 64);
5891 set_gdbarch_long_long_bit (gdbarch, 64);
5892 set_gdbarch_long_double_bit (gdbarch, 128);
5893 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
5896 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5899 /* GCC creates a pseudo-section whose name specifies the size of
5900 longs, since -mlong32 or -mlong64 may be used independent of
5901 other options. How those options affect pointer sizes is ABI and
5902 architecture dependent, so use them to override the default sizes
5903 set by the ABI. This table shows the relationship between ABI,
5904 -mlongXX, and size of pointers:
5906 ABI -mlongXX ptr bits
5907 --- -------- --------
5921 Note that for o32 and eabi32, pointers are always 32 bits
5922 regardless of any -mlongXX option. For all others, pointers and
5923 longs are the same, as set by -mlongXX or set by defaults.
5926 if (info.abfd != NULL)
5930 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
5933 set_gdbarch_long_bit (gdbarch, long_bit);
5937 case MIPS_ABI_EABI32:
5942 case MIPS_ABI_EABI64:
5943 set_gdbarch_ptr_bit (gdbarch, long_bit);
5946 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5951 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5952 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5955 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5956 flag in object files because to do so would make it impossible to
5957 link with libraries compiled without "-gp32". This is
5958 unnecessarily restrictive.
5960 We could solve this problem by adding "-gp32" multilibs to gcc,
5961 but to set this flag before gcc is built with such multilibs will
5962 break too many systems.''
5964 But even more unhelpfully, the default linker output target for
5965 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5966 for 64-bit programs - you need to change the ABI to change this,
5967 and not all gcc targets support that currently. Therefore using
5968 this flag to detect 32-bit mode would do the wrong thing given
5969 the current gcc - it would make GDB treat these 64-bit programs
5970 as 32-bit programs by default. */
5972 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5973 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5975 /* Add/remove bits from an address. The MIPS needs be careful to
5976 ensure that all 32 bit addresses are sign extended to 64 bits. */
5977 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5979 /* Unwind the frame. */
5980 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5981 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
5982 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
5984 /* Map debug register numbers onto internal register numbers. */
5985 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5986 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5987 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5988 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5989 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5990 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5992 /* MIPS version of CALL_DUMMY */
5994 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5995 replaced by a command, and all targets will default to on stack
5996 (regardless of the stack's execute status). */
5997 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5998 set_gdbarch_frame_align (gdbarch, mips_frame_align);
6000 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
6001 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
6002 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
6004 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6005 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
6007 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
6009 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
6011 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
6012 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
6013 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
6015 set_gdbarch_register_type (gdbarch, mips_register_type);
6017 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
6019 if (mips_abi == MIPS_ABI_N32)
6020 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
6021 else if (mips_abi == MIPS_ABI_N64)
6022 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
6024 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
6026 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6027 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6028 need to all be folded into the target vector. Since they are
6029 being used as guards for target_stopped_by_watchpoint, why not have
6030 target_stopped_by_watchpoint return the type of watchpoint that the code
6032 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
6034 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
6036 set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay);
6038 /* Virtual tables. */
6039 set_gdbarch_vbit_in_delta (gdbarch, 1);
6041 mips_register_g_packet_guesses (gdbarch);
6043 /* Hook in OS ABI-specific overrides, if they have been registered. */
6044 info.tdep_info = (void *) tdesc_data;
6045 gdbarch_init_osabi (info, gdbarch);
6047 /* Unwind the frame. */
6048 dwarf2_append_unwinders (gdbarch);
6049 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
6050 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
6051 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
6052 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
6053 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
6054 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
6055 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
6059 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
6060 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
6062 /* Override the normal target description methods to handle our
6063 dual real and pseudo registers. */
6064 set_gdbarch_register_name (gdbarch, mips_register_name);
6065 set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p);
6067 num_regs = gdbarch_num_regs (gdbarch);
6068 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
6069 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
6070 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
6073 /* Add ABI-specific aliases for the registers. */
6074 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
6075 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
6076 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
6077 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
6079 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
6080 user_reg_add (gdbarch, mips_o32_aliases[i].name,
6081 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
6083 /* Add some other standard aliases. */
6084 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
6085 user_reg_add (gdbarch, mips_register_aliases[i].name,
6086 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
6088 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)
6089 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,
6090 value_of_mips_user_reg,
6091 &mips_numeric_register_aliases[i].regnum);
6097 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
6099 struct gdbarch_info info;
6101 /* Force the architecture to update, and (if it's a MIPS architecture)
6102 mips_gdbarch_init will take care of the rest. */
6103 gdbarch_info_init (&info);
6104 gdbarch_update_p (info);
6107 /* Print out which MIPS ABI is in use. */
6110 show_mips_abi (struct ui_file *file,
6112 struct cmd_list_element *ignored_cmd,
6113 const char *ignored_value)
6115 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
6118 "The MIPS ABI is unknown because the current architecture "
6122 enum mips_abi global_abi = global_mips_abi ();
6123 enum mips_abi actual_abi = mips_abi (target_gdbarch);
6124 const char *actual_abi_str = mips_abi_strings[actual_abi];
6126 if (global_abi == MIPS_ABI_UNKNOWN)
6129 "The MIPS ABI is set automatically (currently \"%s\").\n",
6131 else if (global_abi == actual_abi)
6134 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6138 /* Probably shouldn't happen... */
6141 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6142 actual_abi_str, mips_abi_strings[global_abi]);
6148 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
6150 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6154 int ef_mips_32bitmode;
6155 /* Determine the ISA. */
6156 switch (tdep->elf_flags & EF_MIPS_ARCH)
6174 /* Determine the size of a pointer. */
6175 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6176 fprintf_unfiltered (file,
6177 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6179 fprintf_unfiltered (file,
6180 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6182 fprintf_unfiltered (file,
6183 "mips_dump_tdep: ef_mips_arch = %d\n",
6185 fprintf_unfiltered (file,
6186 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6187 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
6188 fprintf_unfiltered (file,
6189 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6190 mips_mask_address_p (tdep),
6191 tdep->default_mask_address_p);
6193 fprintf_unfiltered (file,
6194 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6195 MIPS_DEFAULT_FPU_TYPE,
6196 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6197 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6198 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6200 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
6201 MIPS_EABI (gdbarch));
6202 fprintf_unfiltered (file,
6203 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6204 MIPS_FPU_TYPE (gdbarch),
6205 (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none"
6206 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single"
6207 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double"
6211 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6214 _initialize_mips_tdep (void)
6216 static struct cmd_list_element *mipsfpulist = NULL;
6217 struct cmd_list_element *c;
6219 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
6220 if (MIPS_ABI_LAST + 1
6221 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6222 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
6224 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6226 mips_pdr_data = register_objfile_data ();
6228 /* Create feature sets with the appropriate properties. The values
6229 are not important. */
6230 mips_tdesc_gp32 = allocate_target_description ();
6231 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
6233 mips_tdesc_gp64 = allocate_target_description ();
6234 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
6236 /* Add root prefix command for all "set mips"/"show mips" commands */
6237 add_prefix_cmd ("mips", no_class, set_mips_command,
6238 _("Various MIPS specific commands."),
6239 &setmipscmdlist, "set mips ", 0, &setlist);
6241 add_prefix_cmd ("mips", no_class, show_mips_command,
6242 _("Various MIPS specific commands."),
6243 &showmipscmdlist, "show mips ", 0, &showlist);
6245 /* Allow the user to override the ABI. */
6246 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
6247 &mips_abi_string, _("\
6248 Set the MIPS ABI used by this program."), _("\
6249 Show the MIPS ABI used by this program."), _("\
6250 This option can be set to one of:\n\
6251 auto - the default ABI associated with the current binary\n\
6260 &setmipscmdlist, &showmipscmdlist);
6262 /* Let the user turn off floating point and set the fence post for
6263 heuristic_proc_start. */
6265 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6266 _("Set use of MIPS floating-point coprocessor."),
6267 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6268 add_cmd ("single", class_support, set_mipsfpu_single_command,
6269 _("Select single-precision MIPS floating-point coprocessor."),
6271 add_cmd ("double", class_support, set_mipsfpu_double_command,
6272 _("Select double-precision MIPS floating-point coprocessor."),
6274 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6275 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6276 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6277 add_cmd ("none", class_support, set_mipsfpu_none_command,
6278 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
6279 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6280 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6281 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6282 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6283 _("Select MIPS floating-point coprocessor automatically."),
6285 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6286 _("Show current use of MIPS floating-point coprocessor target."),
6289 /* We really would like to have both "0" and "unlimited" work, but
6290 command.c doesn't deal with that. So make it a var_zinteger
6291 because the user can always use "999999" or some such for unlimited. */
6292 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
6293 &heuristic_fence_post, _("\
6294 Set the distance searched for the start of a function."), _("\
6295 Show the distance searched for the start of a function."), _("\
6296 If you are debugging a stripped executable, GDB needs to search through the\n\
6297 program for the start of a function. This command sets the distance of the\n\
6298 search. The only need to set it is when debugging a stripped executable."),
6299 reinit_frame_cache_sfunc,
6300 NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6301 &setlist, &showlist);
6303 /* Allow the user to control whether the upper bits of 64-bit
6304 addresses should be zeroed. */
6305 add_setshow_auto_boolean_cmd ("mask-address", no_class,
6306 &mask_address_var, _("\
6307 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6308 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6309 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6310 allow GDB to determine the correct value."),
6311 NULL, show_mask_address,
6312 &setmipscmdlist, &showmipscmdlist);
6314 /* Allow the user to control the size of 32 bit registers within the
6315 raw remote packet. */
6316 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6317 &mips64_transfers_32bit_regs_p, _("\
6318 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6320 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6322 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6323 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6324 64 bits for others. Use \"off\" to disable compatibility mode"),
6325 set_mips64_transfers_32bit_regs,
6326 NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6327 &setlist, &showlist);
6329 /* Debug this files internals. */
6330 add_setshow_zinteger_cmd ("mips", class_maintenance,
6332 Set mips debugging."), _("\
6333 Show mips debugging."), _("\
6334 When non-zero, mips specific debugging is enabled."),
6336 NULL, /* FIXME: i18n: Mips debugging is currently %s. */
6337 &setdebuglist, &showdebuglist);