1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data *mips_pdr_data;
61 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
63 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE = 4,
72 MIPS_FPU_DOUBLE_REGSIZE = 8
76 static const char *mips_abi_string;
78 static const char *mips_abi_strings[] = {
89 /* Various MIPS ISA options (related to stack analysis) can be
90 overridden dynamically. Establish an enum/array for managing
93 static const char size_auto[] = "auto";
94 static const char size_32[] = "32";
95 static const char size_64[] = "64";
97 static const char *size_enums[] = {
104 /* Some MIPS boards don't support floating point while others only
105 support single-precision floating-point operations. */
109 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE /* No floating point. */
114 #ifndef MIPS_DEFAULT_FPU_TYPE
115 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
117 static int mips_fpu_type_auto = 1;
118 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
120 static int mips_debug = 0;
122 /* MIPS specific per-architecture information */
125 /* from the elf header */
129 enum mips_abi mips_abi;
130 enum mips_abi found_abi;
131 enum mips_fpu_type mips_fpu_type;
132 int mips_last_arg_regnum;
133 int mips_last_fp_arg_regnum;
134 int default_mask_address_p;
135 /* Is the target using 64-bit raw integer registers but only
136 storing a left-aligned 32-bit value in each? */
137 int mips64_transfers_32bit_regs_p;
138 /* Indexes for various registers. IRIX and embedded have
139 different values. This contains the "public" fields. Don't
140 add any that do not need to be public. */
141 const struct mips_regnum *regnum;
142 /* Register names table for the current register set. */
143 const char **mips_processor_reg_names;
147 n32n64_floatformat_always_valid (const struct floatformat *fmt,
153 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
154 They are implemented as a pair of 64bit doubles where the high
155 part holds the result of the operation rounded to double, and
156 the low double holds the difference between the exact result and
157 the rounded result. So "high" + "low" contains the result with
158 added precision. Unfortunately, the floatformat structure used
159 by GDB is not powerful enough to describe this format. As a temporary
160 measure, we define a 128bit floatformat that only uses the high part.
161 We lose a bit of precision but that's probably the best we can do
162 for now with the current infrastructure. */
164 static const struct floatformat floatformat_n32n64_long_double_big =
166 floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52,
167 floatformat_intbit_no,
168 "floatformat_ieee_double_big",
169 n32n64_floatformat_always_valid
172 const struct mips_regnum *
173 mips_regnum (struct gdbarch *gdbarch)
175 return gdbarch_tdep (gdbarch)->regnum;
179 mips_fpa0_regnum (struct gdbarch *gdbarch)
181 return mips_regnum (gdbarch)->fp0 + 12;
184 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
185 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr)
203 unmake_mips16_addr (CORE_ADDR addr)
205 return ((addr) & ~(CORE_ADDR) 1);
208 /* Return the contents of register REGNUM as a signed integer. */
211 read_signed_register (int regnum)
214 regcache_cooked_read_signed (current_regcache, regnum, &val);
219 read_signed_register_pid (int regnum, ptid_t ptid)
224 if (ptid_equal (ptid, inferior_ptid))
225 return read_signed_register (regnum);
227 save_ptid = inferior_ptid;
229 inferior_ptid = ptid;
231 retval = read_signed_register (regnum);
233 inferior_ptid = save_ptid;
238 /* Return the MIPS ABI associated with GDBARCH. */
240 mips_abi (struct gdbarch *gdbarch)
242 return gdbarch_tdep (gdbarch)->mips_abi;
246 mips_isa_regsize (struct gdbarch *gdbarch)
248 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
249 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
252 /* Return the currently configured (or set) saved register size. */
254 static const char *mips_abi_regsize_string = size_auto;
257 mips_abi_regsize (struct gdbarch *gdbarch)
259 if (mips_abi_regsize_string == size_auto)
260 switch (mips_abi (gdbarch))
262 case MIPS_ABI_EABI32:
268 case MIPS_ABI_EABI64:
270 case MIPS_ABI_UNKNOWN:
273 internal_error (__FILE__, __LINE__, _("bad switch"));
275 else if (mips_abi_regsize_string == size_64)
277 else /* if (mips_abi_regsize_string == size_32) */
281 /* Functions for setting and testing a bit in a minimal symbol that
282 marks it as 16-bit function. The MSB of the minimal symbol's
283 "info" field is used for this purpose.
285 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
286 i.e. refers to a 16-bit function, and sets a "special" bit in a
287 minimal symbol to mark it as a 16-bit function
289 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
292 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
294 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
296 MSYMBOL_INFO (msym) = (char *)
297 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
298 SYMBOL_VALUE_ADDRESS (msym) |= 1;
303 msymbol_is_special (struct minimal_symbol *msym)
305 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
308 /* XFER a value from the big/little/left end of the register.
309 Depending on the size of the value it might occupy the entire
310 register or just part of it. Make an allowance for this, aligning
311 things accordingly. */
314 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
315 enum bfd_endian endian, gdb_byte *in,
316 const gdb_byte *out, int buf_offset)
319 gdb_assert (reg_num >= NUM_REGS);
320 /* Need to transfer the left or right part of the register, based on
321 the targets byte order. */
325 reg_offset = register_size (current_gdbarch, reg_num) - length;
327 case BFD_ENDIAN_LITTLE:
330 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
334 internal_error (__FILE__, __LINE__, _("bad switch"));
337 fprintf_unfiltered (gdb_stderr,
338 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
339 reg_num, reg_offset, buf_offset, length);
340 if (mips_debug && out != NULL)
343 fprintf_unfiltered (gdb_stdlog, "out ");
344 for (i = 0; i < length; i++)
345 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
348 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
351 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
353 if (mips_debug && in != NULL)
356 fprintf_unfiltered (gdb_stdlog, "in ");
357 for (i = 0; i < length; i++)
358 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
361 fprintf_unfiltered (gdb_stdlog, "\n");
364 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
365 compatiblity mode. A return value of 1 means that we have
366 physical 64-bit registers, but should treat them as 32-bit registers. */
369 mips2_fp_compat (void)
371 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
373 if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) ==
378 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
379 in all the places we deal with FP registers. PR gdb/413. */
380 /* Otherwise check the FR bit in the status register - it controls
381 the FP compatiblity mode. If it is clear we are in compatibility
383 if ((read_register (MIPS_PS_REGNUM) & ST0_FR) == 0)
390 /* The amount of space reserved on the stack for registers. This is
391 different to MIPS_ABI_REGSIZE as it determines the alignment of
392 data allocated after the registers have run out. */
394 static const char *mips_stack_argsize_string = size_auto;
397 mips_stack_argsize (struct gdbarch *gdbarch)
399 if (mips_stack_argsize_string == size_auto)
400 return mips_abi_regsize (gdbarch);
401 else if (mips_stack_argsize_string == size_64)
403 else /* if (mips_stack_argsize_string == size_32) */
407 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
409 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
411 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
413 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
415 static struct type *mips_float_register_type (void);
416 static struct type *mips_double_register_type (void);
418 /* The list of available "set mips " and "show mips " commands */
420 static struct cmd_list_element *setmipscmdlist = NULL;
421 static struct cmd_list_element *showmipscmdlist = NULL;
423 /* Integer registers 0 thru 31 are handled explicitly by
424 mips_register_name(). Processor specific registers 32 and above
425 are listed in the followign tables. */
428 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
432 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
433 "sr", "lo", "hi", "bad", "cause", "pc",
434 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
435 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
436 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
437 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
438 "fsr", "fir", "" /*"fp" */ , "",
439 "", "", "", "", "", "", "", "",
440 "", "", "", "", "", "", "", "",
443 /* Names of IDT R3041 registers. */
445 static const char *mips_r3041_reg_names[] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
448 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
449 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
450 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
451 "fsr", "fir", "", /*"fp" */ "",
452 "", "", "bus", "ccfg", "", "", "", "",
453 "", "", "port", "cmp", "", "", "epc", "prid",
456 /* Names of tx39 registers. */
458 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
459 "sr", "lo", "hi", "bad", "cause", "pc",
460 "", "", "", "", "", "", "", "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
463 "", "", "", "", "", "", "", "",
465 "", "", "", "", "", "", "", "",
466 "", "", "config", "cache", "debug", "depc", "epc", ""
469 /* Names of IRIX registers. */
470 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
471 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
472 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
473 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
474 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
475 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
479 /* Return the name of the register corresponding to REGNO. */
481 mips_register_name (int regno)
483 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
484 /* GPR names for all ABIs other than n32/n64. */
485 static char *mips_gpr_names[] = {
486 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
487 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
488 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
489 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
492 /* GPR names for n32 and n64 ABIs. */
493 static char *mips_n32_n64_gpr_names[] = {
494 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
495 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
496 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
497 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
500 enum mips_abi abi = mips_abi (current_gdbarch);
502 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
503 don't make the raw register names visible. */
504 int rawnum = regno % NUM_REGS;
505 if (regno < NUM_REGS)
508 /* The MIPS integer registers are always mapped from 0 to 31. The
509 names of the registers (which reflects the conventions regarding
510 register use) vary depending on the ABI. */
511 if (0 <= rawnum && rawnum < 32)
513 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
514 return mips_n32_n64_gpr_names[rawnum];
516 return mips_gpr_names[rawnum];
518 else if (32 <= rawnum && rawnum < NUM_REGS)
520 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
521 return tdep->mips_processor_reg_names[rawnum - 32];
524 internal_error (__FILE__, __LINE__,
525 _("mips_register_name: bad register number %d"), rawnum);
528 /* Return the groups that a MIPS register can be categorised into. */
531 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
532 struct reggroup *reggroup)
537 int rawnum = regnum % NUM_REGS;
538 int pseudo = regnum / NUM_REGS;
539 if (reggroup == all_reggroup)
541 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
542 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
543 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
544 (gdbarch), as not all architectures are multi-arch. */
545 raw_p = rawnum < NUM_REGS;
546 if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0')
548 if (reggroup == float_reggroup)
549 return float_p && pseudo;
550 if (reggroup == vector_reggroup)
551 return vector_p && pseudo;
552 if (reggroup == general_reggroup)
553 return (!vector_p && !float_p) && pseudo;
554 /* Save the pseudo registers. Need to make certain that any code
555 extracting register values from a saved register cache also uses
557 if (reggroup == save_reggroup)
558 return raw_p && pseudo;
559 /* Restore the same pseudo register. */
560 if (reggroup == restore_reggroup)
561 return raw_p && pseudo;
565 /* Map the symbol table registers which live in the range [1 *
566 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
567 registers. Take care of alignment and size problems. */
570 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
571 int cookednum, gdb_byte *buf)
573 int rawnum = cookednum % NUM_REGS;
574 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
575 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
576 regcache_raw_read (regcache, rawnum, buf);
577 else if (register_size (gdbarch, rawnum) >
578 register_size (gdbarch, cookednum))
580 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
581 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
582 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
584 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
587 internal_error (__FILE__, __LINE__, _("bad register size"));
591 mips_pseudo_register_write (struct gdbarch *gdbarch,
592 struct regcache *regcache, int cookednum,
595 int rawnum = cookednum % NUM_REGS;
596 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
597 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
598 regcache_raw_write (regcache, rawnum, buf);
599 else if (register_size (gdbarch, rawnum) >
600 register_size (gdbarch, cookednum))
602 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
604 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
606 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
609 internal_error (__FILE__, __LINE__, _("bad register size"));
612 /* Table to translate MIPS16 register field to actual register number. */
613 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
615 /* Heuristic_proc_start may hunt through the text section for a long
616 time across a 2400 baud serial line. Allows the user to limit this
619 static unsigned int heuristic_fence_post = 0;
621 /* Number of bytes of storage in the actual machine representation for
622 register N. NOTE: This defines the pseudo register type so need to
623 rebuild the architecture vector. */
625 static int mips64_transfers_32bit_regs_p = 0;
628 set_mips64_transfers_32bit_regs (char *args, int from_tty,
629 struct cmd_list_element *c)
631 struct gdbarch_info info;
632 gdbarch_info_init (&info);
633 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
634 instead of relying on globals. Doing that would let generic code
635 handle the search for this specific architecture. */
636 if (!gdbarch_update_p (info))
638 mips64_transfers_32bit_regs_p = 0;
639 error (_("32-bit compatibility mode not supported"));
643 /* Convert to/from a register and the corresponding memory value. */
646 mips_convert_register_p (int regnum, struct type *type)
648 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
649 && register_size (current_gdbarch, regnum) == 4
650 && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
651 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32
652 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
656 mips_register_to_value (struct frame_info *frame, int regnum,
657 struct type *type, gdb_byte *to)
659 get_frame_register (frame, regnum + 0, to + 4);
660 get_frame_register (frame, regnum + 1, to + 0);
664 mips_value_to_register (struct frame_info *frame, int regnum,
665 struct type *type, const gdb_byte *from)
667 put_frame_register (frame, regnum + 0, from + 4);
668 put_frame_register (frame, regnum + 1, from + 0);
671 /* Return the GDB type object for the "standard" data type of data in
675 mips_register_type (struct gdbarch *gdbarch, int regnum)
677 gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS);
678 if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
679 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32)
681 /* The floating-point registers raw, or cooked, always match
682 mips_isa_regsize(), and also map 1:1, byte for byte. */
683 switch (gdbarch_byte_order (gdbarch))
686 if (mips_isa_regsize (gdbarch) == 4)
687 return builtin_type_ieee_single_big;
689 return builtin_type_ieee_double_big;
690 case BFD_ENDIAN_LITTLE:
691 if (mips_isa_regsize (gdbarch) == 4)
692 return builtin_type_ieee_single_little;
694 return builtin_type_ieee_double_little;
695 case BFD_ENDIAN_UNKNOWN:
697 internal_error (__FILE__, __LINE__, _("bad switch"));
700 else if (regnum < NUM_REGS)
702 /* The raw or ISA registers. These are all sized according to
704 if (mips_isa_regsize (gdbarch) == 4)
705 return builtin_type_int32;
707 return builtin_type_int64;
711 /* The cooked or ABI registers. These are sized according to
712 the ABI (with a few complications). */
713 if (regnum >= (NUM_REGS
714 + mips_regnum (current_gdbarch)->fp_control_status)
715 && regnum <= NUM_REGS + MIPS_LAST_EMBED_REGNUM)
716 /* The pseudo/cooked view of the embedded registers is always
717 32-bit. The raw view is handled below. */
718 return builtin_type_int32;
719 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
720 /* The target, while possibly using a 64-bit register buffer,
721 is only transfering 32-bits of each integer register.
722 Reflect this in the cooked/pseudo (ABI) register value. */
723 return builtin_type_int32;
724 else if (mips_abi_regsize (gdbarch) == 4)
725 /* The ABI is restricted to 32-bit registers (the ISA could be
727 return builtin_type_int32;
730 return builtin_type_int64;
734 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
739 return read_signed_register (MIPS_SP_REGNUM);
742 /* Should the upper word of 64-bit addresses be zeroed? */
743 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
746 mips_mask_address_p (struct gdbarch_tdep *tdep)
748 switch (mask_address_var)
750 case AUTO_BOOLEAN_TRUE:
752 case AUTO_BOOLEAN_FALSE:
755 case AUTO_BOOLEAN_AUTO:
756 return tdep->default_mask_address_p;
758 internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch"));
764 show_mask_address (struct ui_file *file, int from_tty,
765 struct cmd_list_element *c, const char *value)
767 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
769 deprecated_show_value_hack (file, from_tty, c, value);
770 switch (mask_address_var)
772 case AUTO_BOOLEAN_TRUE:
773 printf_filtered ("The 32 bit mips address mask is enabled\n");
775 case AUTO_BOOLEAN_FALSE:
776 printf_filtered ("The 32 bit mips address mask is disabled\n");
778 case AUTO_BOOLEAN_AUTO:
780 ("The 32 bit address mask is set automatically. Currently %s\n",
781 mips_mask_address_p (tdep) ? "enabled" : "disabled");
784 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
789 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
792 mips_pc_is_mips16 (CORE_ADDR memaddr)
794 struct minimal_symbol *sym;
796 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
797 if (is_mips16_addr (memaddr))
800 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
801 the high bit of the info field. Use this to decide if the function is
802 MIPS16 or normal MIPS. */
803 sym = lookup_minimal_symbol_by_pc (memaddr);
805 return msymbol_is_special (sym);
810 /* MIPS believes that the PC has a sign extended value. Perhaps the
811 all registers should be sign extended for simplicity? */
814 mips_read_pc (ptid_t ptid)
816 return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid);
820 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
822 return frame_unwind_register_signed (next_frame,
823 NUM_REGS + mips_regnum (gdbarch)->pc);
826 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
827 dummy frame. The frame ID's base needs to match the TOS value
828 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
831 static struct frame_id
832 mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
834 return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM),
835 frame_pc_unwind (next_frame));
839 mips_write_pc (CORE_ADDR pc, ptid_t ptid)
841 write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid);
844 /* Fetch and return instruction from the specified location. If the PC
845 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
848 mips_fetch_instruction (CORE_ADDR addr)
850 gdb_byte buf[MIPS_INSN32_SIZE];
854 if (mips_pc_is_mips16 (addr))
856 instlen = MIPS_INSN16_SIZE;
857 addr = unmake_mips16_addr (addr);
860 instlen = MIPS_INSN32_SIZE;
861 status = deprecated_read_memory_nobpt (addr, buf, instlen);
863 memory_error (status, addr);
864 return extract_unsigned_integer (buf, instlen);
867 /* These the fields of 32 bit mips instructions */
868 #define mips32_op(x) (x >> 26)
869 #define itype_op(x) (x >> 26)
870 #define itype_rs(x) ((x >> 21) & 0x1f)
871 #define itype_rt(x) ((x >> 16) & 0x1f)
872 #define itype_immediate(x) (x & 0xffff)
874 #define jtype_op(x) (x >> 26)
875 #define jtype_target(x) (x & 0x03ffffff)
877 #define rtype_op(x) (x >> 26)
878 #define rtype_rs(x) ((x >> 21) & 0x1f)
879 #define rtype_rt(x) ((x >> 16) & 0x1f)
880 #define rtype_rd(x) ((x >> 11) & 0x1f)
881 #define rtype_shamt(x) ((x >> 6) & 0x1f)
882 #define rtype_funct(x) (x & 0x3f)
885 mips32_relative_offset (ULONGEST inst)
887 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
890 /* Determine whate to set a single step breakpoint while considering
893 mips32_next_pc (CORE_ADDR pc)
897 inst = mips_fetch_instruction (pc);
898 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
900 if (itype_op (inst) >> 2 == 5)
901 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
903 op = (itype_op (inst) & 0x03);
918 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
919 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
921 int tf = itype_rt (inst) & 0x01;
922 int cnum = itype_rt (inst) >> 2;
924 read_signed_register (mips_regnum (current_gdbarch)->
926 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
928 if (((cond >> cnum) & 0x01) == tf)
929 pc += mips32_relative_offset (inst) + 4;
934 pc += 4; /* Not a branch, next instruction is easy */
937 { /* This gets way messy */
939 /* Further subdivide into SPECIAL, REGIMM and other */
940 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
942 case 0: /* SPECIAL */
943 op = rtype_funct (inst);
948 /* Set PC to that address */
949 pc = read_signed_register (rtype_rs (inst));
955 break; /* end SPECIAL */
958 op = itype_rt (inst); /* branch condition */
963 case 16: /* BLTZAL */
964 case 18: /* BLTZALL */
966 if (read_signed_register (itype_rs (inst)) < 0)
967 pc += mips32_relative_offset (inst) + 4;
969 pc += 8; /* after the delay slot */
973 case 17: /* BGEZAL */
974 case 19: /* BGEZALL */
975 if (read_signed_register (itype_rs (inst)) >= 0)
976 pc += mips32_relative_offset (inst) + 4;
978 pc += 8; /* after the delay slot */
980 /* All of the other instructions in the REGIMM category */
985 break; /* end REGIMM */
990 reg = jtype_target (inst) << 2;
991 /* Upper four bits get never changed... */
992 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
995 /* FIXME case JALX : */
998 reg = jtype_target (inst) << 2;
999 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */
1000 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1002 break; /* The new PC will be alternate mode */
1003 case 4: /* BEQ, BEQL */
1005 if (read_signed_register (itype_rs (inst)) ==
1006 read_signed_register (itype_rt (inst)))
1007 pc += mips32_relative_offset (inst) + 4;
1011 case 5: /* BNE, BNEL */
1013 if (read_signed_register (itype_rs (inst)) !=
1014 read_signed_register (itype_rt (inst)))
1015 pc += mips32_relative_offset (inst) + 4;
1019 case 6: /* BLEZ, BLEZL */
1020 if (read_signed_register (itype_rs (inst)) <= 0)
1021 pc += mips32_relative_offset (inst) + 4;
1027 greater_branch: /* BGTZ, BGTZL */
1028 if (read_signed_register (itype_rs (inst)) > 0)
1029 pc += mips32_relative_offset (inst) + 4;
1036 } /* mips32_next_pc */
1038 /* Decoding the next place to set a breakpoint is irregular for the
1039 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1040 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1041 We dont want to set a single step instruction on the extend instruction
1045 /* Lots of mips16 instruction formats */
1046 /* Predicting jumps requires itype,ritype,i8type
1047 and their extensions extItype,extritype,extI8type
1049 enum mips16_inst_fmts
1051 itype, /* 0 immediate 5,10 */
1052 ritype, /* 1 5,3,8 */
1053 rrtype, /* 2 5,3,3,5 */
1054 rritype, /* 3 5,3,3,5 */
1055 rrrtype, /* 4 5,3,3,3,2 */
1056 rriatype, /* 5 5,3,3,1,4 */
1057 shifttype, /* 6 5,3,3,3,2 */
1058 i8type, /* 7 5,3,8 */
1059 i8movtype, /* 8 5,3,3,5 */
1060 i8mov32rtype, /* 9 5,3,5,3 */
1061 i64type, /* 10 5,3,8 */
1062 ri64type, /* 11 5,3,3,5 */
1063 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1064 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1065 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1066 extRRItype, /* 15 5,5,5,5,3,3,5 */
1067 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1068 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1069 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1070 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1071 extRi64type, /* 20 5,6,5,5,3,3,5 */
1072 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1074 /* I am heaping all the fields of the formats into one structure and
1075 then, only the fields which are involved in instruction extension */
1079 unsigned int regx; /* Function in i8 type */
1084 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1085 for the bits which make up the immediatate extension. */
1088 extended_offset (unsigned int extension)
1091 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1093 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1095 value |= extension & 0x01f; /* extract 4:0 */
1099 /* Only call this function if you know that this is an extendable
1100 instruction, It wont malfunction, but why make excess remote memory references?
1101 If the immediate operands get sign extended or somthing, do it after
1102 the extension is performed.
1104 /* FIXME: Every one of these cases needs to worry about sign extension
1105 when the offset is to be used in relative addressing */
1109 fetch_mips_16 (CORE_ADDR pc)
1112 pc &= 0xfffffffe; /* clear the low order bit */
1113 target_read_memory (pc, buf, 2);
1114 return extract_unsigned_integer (buf, 2);
1118 unpack_mips16 (CORE_ADDR pc,
1119 unsigned int extension,
1121 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1126 switch (insn_format)
1133 value = extended_offset (extension);
1134 value = value << 11; /* rom for the original value */
1135 value |= inst & 0x7ff; /* eleven bits from instruction */
1139 value = inst & 0x7ff;
1140 /* FIXME : Consider sign extension */
1149 { /* A register identifier and an offset */
1150 /* Most of the fields are the same as I type but the
1151 immediate value is of a different length */
1155 value = extended_offset (extension);
1156 value = value << 8; /* from the original instruction */
1157 value |= inst & 0xff; /* eleven bits from instruction */
1158 regx = (extension >> 8) & 0x07; /* or i8 funct */
1159 if (value & 0x4000) /* test the sign bit , bit 26 */
1161 value &= ~0x3fff; /* remove the sign bit */
1167 value = inst & 0xff; /* 8 bits */
1168 regx = (inst >> 8) & 0x07; /* or i8 funct */
1169 /* FIXME: Do sign extension , this format needs it */
1170 if (value & 0x80) /* THIS CONFUSES ME */
1172 value &= 0xef; /* remove the sign bit */
1182 unsigned long value;
1183 unsigned int nexthalf;
1184 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1185 value = value << 16;
1186 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1194 internal_error (__FILE__, __LINE__, _("bad switch"));
1196 upk->offset = offset;
1203 add_offset_16 (CORE_ADDR pc, int offset)
1205 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
1209 extended_mips16_next_pc (CORE_ADDR pc,
1210 unsigned int extension, unsigned int insn)
1212 int op = (insn >> 11);
1215 case 2: /* Branch */
1218 struct upk_mips16 upk;
1219 unpack_mips16 (pc, extension, insn, itype, &upk);
1220 offset = upk.offset;
1226 pc += (offset << 1) + 2;
1229 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1231 struct upk_mips16 upk;
1232 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1233 pc = add_offset_16 (pc, upk.offset);
1234 if ((insn >> 10) & 0x01) /* Exchange mode */
1235 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1242 struct upk_mips16 upk;
1244 unpack_mips16 (pc, extension, insn, ritype, &upk);
1245 reg = read_signed_register (upk.regx);
1247 pc += (upk.offset << 1) + 2;
1254 struct upk_mips16 upk;
1256 unpack_mips16 (pc, extension, insn, ritype, &upk);
1257 reg = read_signed_register (upk.regx);
1259 pc += (upk.offset << 1) + 2;
1264 case 12: /* I8 Formats btez btnez */
1266 struct upk_mips16 upk;
1268 unpack_mips16 (pc, extension, insn, i8type, &upk);
1269 /* upk.regx contains the opcode */
1270 reg = read_signed_register (24); /* Test register is 24 */
1271 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1272 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1273 /* pc = add_offset_16(pc,upk.offset) ; */
1274 pc += (upk.offset << 1) + 2;
1279 case 29: /* RR Formats JR, JALR, JALR-RA */
1281 struct upk_mips16 upk;
1282 /* upk.fmt = rrtype; */
1287 upk.regx = (insn >> 8) & 0x07;
1288 upk.regy = (insn >> 5) & 0x07;
1296 break; /* Function return instruction */
1302 break; /* BOGUS Guess */
1304 pc = read_signed_register (reg);
1311 /* This is an instruction extension. Fetch the real instruction
1312 (which follows the extension) and decode things based on
1316 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1329 mips16_next_pc (CORE_ADDR pc)
1331 unsigned int insn = fetch_mips_16 (pc);
1332 return extended_mips16_next_pc (pc, 0, insn);
1335 /* The mips_next_pc function supports single_step when the remote
1336 target monitor or stub is not developed enough to do a single_step.
1337 It works by decoding the current instruction and predicting where a
1338 branch will go. This isnt hard because all the data is available.
1339 The MIPS32 and MIPS16 variants are quite different */
1341 mips_next_pc (CORE_ADDR pc)
1344 return mips16_next_pc (pc);
1346 return mips32_next_pc (pc);
1349 struct mips_frame_cache
1352 struct trad_frame_saved_reg *saved_regs;
1355 /* Set a register's saved stack address in temp_saved_regs. If an
1356 address has already been set for this register, do nothing; this
1357 way we will only recognize the first save of a given register in a
1360 For simplicity, save the address in both [0 .. NUM_REGS) and
1361 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1362 is used as it is only second range (the ABI instead of ISA
1363 registers) that comes into play when finding saved registers in a
1367 set_reg_offset (struct mips_frame_cache *this_cache, int regnum,
1370 if (this_cache != NULL
1371 && this_cache->saved_regs[regnum].addr == -1)
1373 this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset;
1374 this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset;
1379 /* Fetch the immediate value from a MIPS16 instruction.
1380 If the previous instruction was an EXTEND, use it to extend
1381 the upper bits of the immediate value. This is a helper function
1382 for mips16_scan_prologue. */
1385 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1386 unsigned short inst, /* current instruction */
1387 int nbits, /* number of bits in imm field */
1388 int scale, /* scale factor to be applied to imm */
1389 int is_signed) /* is the imm field signed? */
1393 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1395 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1396 if (offset & 0x8000) /* check for negative extend */
1397 offset = 0 - (0x10000 - (offset & 0xffff));
1398 return offset | (inst & 0x1f);
1402 int max_imm = 1 << nbits;
1403 int mask = max_imm - 1;
1404 int sign_bit = max_imm >> 1;
1406 offset = inst & mask;
1407 if (is_signed && (offset & sign_bit))
1408 offset = 0 - (max_imm - offset);
1409 return offset * scale;
1414 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1415 the associated FRAME_CACHE if not null.
1416 Return the address of the first instruction past the prologue. */
1419 mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1420 struct frame_info *next_frame,
1421 struct mips_frame_cache *this_cache)
1424 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1426 long frame_offset = 0; /* Size of stack frame. */
1427 long frame_adjust = 0; /* Offset of FP from SP. */
1428 int frame_reg = MIPS_SP_REGNUM;
1429 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1430 unsigned inst = 0; /* current instruction */
1431 unsigned entry_inst = 0; /* the entry instruction */
1434 int extend_bytes = 0;
1435 int prev_extend_bytes;
1436 CORE_ADDR end_prologue_addr = 0;
1438 /* Can be called when there's no process, and hence when there's no
1440 if (next_frame != NULL)
1441 sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM);
1445 if (limit_pc > start_pc + 200)
1446 limit_pc = start_pc + 200;
1448 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
1450 /* Save the previous instruction. If it's an EXTEND, we'll extract
1451 the immediate offset extension from it in mips16_get_imm. */
1454 /* Fetch and decode the instruction. */
1455 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1457 /* Normally we ignore extend instructions. However, if it is
1458 not followed by a valid prologue instruction, then this
1459 instruction is not part of the prologue either. We must
1460 remember in this case to adjust the end_prologue_addr back
1462 if ((inst & 0xf800) == 0xf000) /* extend */
1464 extend_bytes = MIPS_INSN16_SIZE;
1468 prev_extend_bytes = extend_bytes;
1471 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1472 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1474 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1475 if (offset < 0) /* negative stack adjustment? */
1476 frame_offset -= offset;
1478 /* Exit loop if a positive stack adjustment is found, which
1479 usually means that the stack cleanup code in the function
1480 epilogue is reached. */
1483 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1485 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1486 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1487 set_reg_offset (this_cache, reg, sp + offset);
1489 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1491 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1492 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1493 set_reg_offset (this_cache, reg, sp + offset);
1495 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1497 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1498 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1500 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1502 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1503 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1505 else if (inst == 0x673d) /* move $s1, $sp */
1510 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1512 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1513 frame_addr = sp + offset;
1515 frame_adjust = offset;
1517 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1519 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1520 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1521 set_reg_offset (this_cache, reg, frame_addr + offset);
1523 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1525 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1526 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1527 set_reg_offset (this_cache, reg, frame_addr + offset);
1529 else if ((inst & 0xf81f) == 0xe809
1530 && (inst & 0x700) != 0x700) /* entry */
1531 entry_inst = inst; /* save for later processing */
1532 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1533 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
1534 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1536 /* This instruction is part of the prologue, but we don't
1537 need to do anything special to handle it. */
1541 /* This instruction is not an instruction typically found
1542 in a prologue, so we must have reached the end of the
1544 if (end_prologue_addr == 0)
1545 end_prologue_addr = cur_pc - prev_extend_bytes;
1549 /* The entry instruction is typically the first instruction in a function,
1550 and it stores registers at offsets relative to the value of the old SP
1551 (before the prologue). But the value of the sp parameter to this
1552 function is the new SP (after the prologue has been executed). So we
1553 can't calculate those offsets until we've seen the entire prologue,
1554 and can calculate what the old SP must have been. */
1555 if (entry_inst != 0)
1557 int areg_count = (entry_inst >> 8) & 7;
1558 int sreg_count = (entry_inst >> 6) & 3;
1560 /* The entry instruction always subtracts 32 from the SP. */
1563 /* Now we can calculate what the SP must have been at the
1564 start of the function prologue. */
1567 /* Check if a0-a3 were saved in the caller's argument save area. */
1568 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1570 set_reg_offset (this_cache, reg, sp + offset);
1571 offset += mips_abi_regsize (current_gdbarch);
1574 /* Check if the ra register was pushed on the stack. */
1576 if (entry_inst & 0x20)
1578 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1579 offset -= mips_abi_regsize (current_gdbarch);
1582 /* Check if the s0 and s1 registers were pushed on the stack. */
1583 for (reg = 16; reg < sreg_count + 16; reg++)
1585 set_reg_offset (this_cache, reg, sp + offset);
1586 offset -= mips_abi_regsize (current_gdbarch);
1590 if (this_cache != NULL)
1593 (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg)
1594 + frame_offset - frame_adjust);
1595 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1596 be able to get rid of the assignment below, evetually. But it's
1597 still needed for now. */
1598 this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
1599 = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM];
1602 /* If we didn't reach the end of the prologue when scanning the function
1603 instructions, then set end_prologue_addr to the address of the
1604 instruction immediately after the last one we scanned. */
1605 if (end_prologue_addr == 0)
1606 end_prologue_addr = cur_pc;
1608 return end_prologue_addr;
1611 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1612 Procedures that use the 32-bit instruction set are handled by the
1613 mips_insn32 unwinder. */
1615 static struct mips_frame_cache *
1616 mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache)
1618 struct mips_frame_cache *cache;
1620 if ((*this_cache) != NULL)
1621 return (*this_cache);
1622 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1623 (*this_cache) = cache;
1624 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1626 /* Analyze the function prologue. */
1628 const CORE_ADDR pc = frame_pc_unwind (next_frame);
1629 CORE_ADDR start_addr;
1631 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1632 if (start_addr == 0)
1633 start_addr = heuristic_proc_start (pc);
1634 /* We can't analyze the prologue if we couldn't find the begining
1636 if (start_addr == 0)
1639 mips16_scan_prologue (start_addr, pc, next_frame, *this_cache);
1642 /* SP_REGNUM, contains the value and not the address. */
1643 trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
1645 return (*this_cache);
1649 mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache,
1650 struct frame_id *this_id)
1652 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1654 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
1658 mips_insn16_frame_prev_register (struct frame_info *next_frame,
1660 int regnum, int *optimizedp,
1661 enum lval_type *lvalp, CORE_ADDR *addrp,
1662 int *realnump, gdb_byte *valuep)
1664 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1666 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
1667 optimizedp, lvalp, addrp, realnump, valuep);
1670 static const struct frame_unwind mips_insn16_frame_unwind =
1673 mips_insn16_frame_this_id,
1674 mips_insn16_frame_prev_register
1677 static const struct frame_unwind *
1678 mips_insn16_frame_sniffer (struct frame_info *next_frame)
1680 CORE_ADDR pc = frame_pc_unwind (next_frame);
1681 if (mips_pc_is_mips16 (pc))
1682 return &mips_insn16_frame_unwind;
1687 mips_insn16_frame_base_address (struct frame_info *next_frame,
1690 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1695 static const struct frame_base mips_insn16_frame_base =
1697 &mips_insn16_frame_unwind,
1698 mips_insn16_frame_base_address,
1699 mips_insn16_frame_base_address,
1700 mips_insn16_frame_base_address
1703 static const struct frame_base *
1704 mips_insn16_frame_base_sniffer (struct frame_info *next_frame)
1706 if (mips_insn16_frame_sniffer (next_frame) != NULL)
1707 return &mips_insn16_frame_base;
1712 /* Mark all the registers as unset in the saved_regs array
1713 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1716 reset_saved_regs (struct mips_frame_cache *this_cache)
1718 if (this_cache == NULL || this_cache->saved_regs == NULL)
1722 const int num_regs = NUM_REGS;
1725 for (i = 0; i < num_regs; i++)
1727 this_cache->saved_regs[i].addr = -1;
1732 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1733 the associated FRAME_CACHE if not null.
1734 Return the address of the first instruction past the prologue. */
1737 mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1738 struct frame_info *next_frame,
1739 struct mips_frame_cache *this_cache)
1742 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1745 int frame_reg = MIPS_SP_REGNUM;
1747 CORE_ADDR end_prologue_addr = 0;
1748 int seen_sp_adjust = 0;
1749 int load_immediate_bytes = 0;
1751 /* Can be called when there's no process, and hence when there's no
1753 if (next_frame != NULL)
1754 sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM);
1758 if (limit_pc > start_pc + 200)
1759 limit_pc = start_pc + 200;
1764 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
1766 unsigned long inst, high_word, low_word;
1769 /* Fetch the instruction. */
1770 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1772 /* Save some code by pre-extracting some useful fields. */
1773 high_word = (inst >> 16) & 0xffff;
1774 low_word = inst & 0xffff;
1775 reg = high_word & 0x1f;
1777 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1778 || high_word == 0x23bd /* addi $sp,$sp,-i */
1779 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1781 if (low_word & 0x8000) /* negative stack adjustment? */
1782 frame_offset += 0x10000 - low_word;
1784 /* Exit loop if a positive stack adjustment is found, which
1785 usually means that the stack cleanup code in the function
1786 epilogue is reached. */
1790 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1792 set_reg_offset (this_cache, reg, sp + low_word);
1794 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1796 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1797 set_reg_offset (this_cache, reg, sp + low_word);
1799 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1801 /* Old gcc frame, r30 is virtual frame pointer. */
1802 if ((long) low_word != frame_offset)
1803 frame_addr = sp + low_word;
1804 else if (frame_reg == MIPS_SP_REGNUM)
1806 unsigned alloca_adjust;
1809 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
1810 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1811 if (alloca_adjust > 0)
1813 /* FP > SP + frame_size. This may be because of
1814 an alloca or somethings similar. Fix sp to
1815 "pre-alloca" value, and try again. */
1816 sp += alloca_adjust;
1817 /* Need to reset the status of all registers. Otherwise,
1818 we will hit a guard that prevents the new address
1819 for each register to be recomputed during the second
1821 reset_saved_regs (this_cache);
1826 /* move $30,$sp. With different versions of gas this will be either
1827 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1828 Accept any one of these. */
1829 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1831 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1832 if (frame_reg == MIPS_SP_REGNUM)
1834 unsigned alloca_adjust;
1837 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
1838 alloca_adjust = (unsigned) (frame_addr - sp);
1839 if (alloca_adjust > 0)
1841 /* FP > SP + frame_size. This may be because of
1842 an alloca or somethings similar. Fix sp to
1843 "pre-alloca" value, and try again. */
1845 /* Need to reset the status of all registers. Otherwise,
1846 we will hit a guard that prevents the new address
1847 for each register to be recomputed during the second
1849 reset_saved_regs (this_cache);
1854 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1856 set_reg_offset (this_cache, reg, frame_addr + low_word);
1858 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1859 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1860 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1861 || high_word == 0x3c1c /* lui $gp,n */
1862 || high_word == 0x279c /* addiu $gp,$gp,n */
1863 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
1864 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
1867 /* These instructions are part of the prologue, but we don't
1868 need to do anything special to handle them. */
1870 /* The instructions below load $at or $t0 with an immediate
1871 value in preparation for a stack adjustment via
1872 subu $sp,$sp,[$at,$t0]. These instructions could also
1873 initialize a local variable, so we accept them only before
1874 a stack adjustment instruction was seen. */
1875 else if (!seen_sp_adjust
1876 && (high_word == 0x3c01 /* lui $at,n */
1877 || high_word == 0x3c08 /* lui $t0,n */
1878 || high_word == 0x3421 /* ori $at,$at,n */
1879 || high_word == 0x3508 /* ori $t0,$t0,n */
1880 || high_word == 0x3401 /* ori $at,$zero,n */
1881 || high_word == 0x3408 /* ori $t0,$zero,n */
1884 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
1888 /* This instruction is not an instruction typically found
1889 in a prologue, so we must have reached the end of the
1891 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1892 loop now? Why would we need to continue scanning the function
1894 if (end_prologue_addr == 0)
1895 end_prologue_addr = cur_pc;
1899 if (this_cache != NULL)
1902 (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg)
1904 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1905 this assignment below, eventually. But it's still needed
1907 this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
1908 = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM];
1911 /* If we didn't reach the end of the prologue when scanning the function
1912 instructions, then set end_prologue_addr to the address of the
1913 instruction immediately after the last one we scanned. */
1914 /* brobecker/2004-10-10: I don't think this would ever happen, but
1915 we may as well be careful and do our best if we have a null
1916 end_prologue_addr. */
1917 if (end_prologue_addr == 0)
1918 end_prologue_addr = cur_pc;
1920 /* In a frameless function, we might have incorrectly
1921 skipped some load immediate instructions. Undo the skipping
1922 if the load immediate was not followed by a stack adjustment. */
1923 if (load_immediate_bytes && !seen_sp_adjust)
1924 end_prologue_addr -= load_immediate_bytes;
1926 return end_prologue_addr;
1929 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1930 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1931 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1934 static struct mips_frame_cache *
1935 mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
1937 struct mips_frame_cache *cache;
1939 if ((*this_cache) != NULL)
1940 return (*this_cache);
1942 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1943 (*this_cache) = cache;
1944 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1946 /* Analyze the function prologue. */
1948 const CORE_ADDR pc = frame_pc_unwind (next_frame);
1949 CORE_ADDR start_addr;
1951 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1952 if (start_addr == 0)
1953 start_addr = heuristic_proc_start (pc);
1954 /* We can't analyze the prologue if we couldn't find the begining
1956 if (start_addr == 0)
1959 mips32_scan_prologue (start_addr, pc, next_frame, *this_cache);
1962 /* SP_REGNUM, contains the value and not the address. */
1963 trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
1965 return (*this_cache);
1969 mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache,
1970 struct frame_id *this_id)
1972 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
1974 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
1978 mips_insn32_frame_prev_register (struct frame_info *next_frame,
1980 int regnum, int *optimizedp,
1981 enum lval_type *lvalp, CORE_ADDR *addrp,
1982 int *realnump, gdb_byte *valuep)
1984 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
1986 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
1987 optimizedp, lvalp, addrp, realnump, valuep);
1990 static const struct frame_unwind mips_insn32_frame_unwind =
1993 mips_insn32_frame_this_id,
1994 mips_insn32_frame_prev_register
1997 static const struct frame_unwind *
1998 mips_insn32_frame_sniffer (struct frame_info *next_frame)
2000 CORE_ADDR pc = frame_pc_unwind (next_frame);
2001 if (! mips_pc_is_mips16 (pc))
2002 return &mips_insn32_frame_unwind;
2007 mips_insn32_frame_base_address (struct frame_info *next_frame,
2010 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
2015 static const struct frame_base mips_insn32_frame_base =
2017 &mips_insn32_frame_unwind,
2018 mips_insn32_frame_base_address,
2019 mips_insn32_frame_base_address,
2020 mips_insn32_frame_base_address
2023 static const struct frame_base *
2024 mips_insn32_frame_base_sniffer (struct frame_info *next_frame)
2026 if (mips_insn32_frame_sniffer (next_frame) != NULL)
2027 return &mips_insn32_frame_base;
2032 static struct trad_frame_cache *
2033 mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache)
2036 CORE_ADDR start_addr;
2037 CORE_ADDR stack_addr;
2038 struct trad_frame_cache *this_trad_cache;
2040 if ((*this_cache) != NULL)
2041 return (*this_cache);
2042 this_trad_cache = trad_frame_cache_zalloc (next_frame);
2043 (*this_cache) = this_trad_cache;
2045 /* The return address is in the link register. */
2046 trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM);
2048 /* Frame ID, since it's a frameless / stackless function, no stack
2049 space is allocated and SP on entry is the current SP. */
2050 pc = frame_pc_unwind (next_frame);
2051 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2052 stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM);
2053 trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr));
2055 /* Assume that the frame's base is the same as the
2057 trad_frame_set_this_base (this_trad_cache, stack_addr);
2059 return this_trad_cache;
2063 mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache,
2064 struct frame_id *this_id)
2066 struct trad_frame_cache *this_trad_cache
2067 = mips_stub_frame_cache (next_frame, this_cache);
2068 trad_frame_get_id (this_trad_cache, this_id);
2072 mips_stub_frame_prev_register (struct frame_info *next_frame,
2074 int regnum, int *optimizedp,
2075 enum lval_type *lvalp, CORE_ADDR *addrp,
2076 int *realnump, gdb_byte *valuep)
2078 struct trad_frame_cache *this_trad_cache
2079 = mips_stub_frame_cache (next_frame, this_cache);
2080 trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp,
2081 lvalp, addrp, realnump, valuep);
2084 static const struct frame_unwind mips_stub_frame_unwind =
2087 mips_stub_frame_this_id,
2088 mips_stub_frame_prev_register
2091 static const struct frame_unwind *
2092 mips_stub_frame_sniffer (struct frame_info *next_frame)
2094 struct obj_section *s;
2095 CORE_ADDR pc = frame_pc_unwind (next_frame);
2097 if (in_plt_section (pc, NULL))
2098 return &mips_stub_frame_unwind;
2100 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2101 s = find_pc_section (pc);
2104 && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
2105 ".MIPS.stubs") == 0)
2106 return &mips_stub_frame_unwind;
2112 mips_stub_frame_base_address (struct frame_info *next_frame,
2115 struct trad_frame_cache *this_trad_cache
2116 = mips_stub_frame_cache (next_frame, this_cache);
2117 return trad_frame_get_this_base (this_trad_cache);
2120 static const struct frame_base mips_stub_frame_base =
2122 &mips_stub_frame_unwind,
2123 mips_stub_frame_base_address,
2124 mips_stub_frame_base_address,
2125 mips_stub_frame_base_address
2128 static const struct frame_base *
2129 mips_stub_frame_base_sniffer (struct frame_info *next_frame)
2131 if (mips_stub_frame_sniffer (next_frame) != NULL)
2132 return &mips_stub_frame_base;
2138 read_next_frame_reg (struct frame_info *fi, int regno)
2140 /* Always a pseudo. */
2141 gdb_assert (regno >= NUM_REGS);
2145 regcache_cooked_read_signed (current_regcache, regno, &val);
2149 return frame_unwind_register_signed (fi, regno);
2153 /* mips_addr_bits_remove - remove useless address bits */
2156 mips_addr_bits_remove (CORE_ADDR addr)
2158 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2159 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
2160 /* This hack is a work-around for existing boards using PMON, the
2161 simulator, and any other 64-bit targets that doesn't have true
2162 64-bit addressing. On these targets, the upper 32 bits of
2163 addresses are ignored by the hardware. Thus, the PC or SP are
2164 likely to have been sign extended to all 1s by instruction
2165 sequences that load 32-bit addresses. For example, a typical
2166 piece of code that loads an address is this:
2168 lui $r2, <upper 16 bits>
2169 ori $r2, <lower 16 bits>
2171 But the lui sign-extends the value such that the upper 32 bits
2172 may be all 1s. The workaround is simply to mask off these
2173 bits. In the future, gcc may be changed to support true 64-bit
2174 addressing, and this masking will have to be disabled. */
2175 return addr &= 0xffffffffUL;
2180 /* mips_software_single_step() is called just before we want to resume
2181 the inferior, if we want to single-step it but there is no hardware
2182 or kernel single-step support (MIPS on GNU/Linux for example). We find
2183 the target of the coming instruction and breakpoint it.
2185 single_step is also called just after the inferior stops. If we had
2186 set up a simulated single-step, we undo our damage. */
2189 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
2191 static CORE_ADDR next_pc;
2192 typedef char binsn_quantum[BREAKPOINT_MAX];
2193 static binsn_quantum break_mem;
2196 if (insert_breakpoints_p)
2198 pc = read_register (mips_regnum (current_gdbarch)->pc);
2199 next_pc = mips_next_pc (pc);
2201 target_insert_breakpoint (next_pc, break_mem);
2204 target_remove_breakpoint (next_pc, break_mem);
2207 /* Test whether the PC points to the return instruction at the
2208 end of a function. */
2211 mips_about_to_return (CORE_ADDR pc)
2213 if (mips_pc_is_mips16 (pc))
2214 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2215 generates a "jr $ra"; other times it generates code to load
2216 the return address from the stack to an accessible register (such
2217 as $a3), then a "jr" using that register. This second case
2218 is almost impossible to distinguish from an indirect jump
2219 used for switch statements, so we don't even try. */
2220 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
2222 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
2226 /* This fencepost looks highly suspicious to me. Removing it also
2227 seems suspicious as it could affect remote debugging across serial
2231 heuristic_proc_start (CORE_ADDR pc)
2238 pc = ADDR_BITS_REMOVE (pc);
2240 fence = start_pc - heuristic_fence_post;
2244 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
2245 fence = VM_MIN_ADDRESS;
2247 instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE;
2249 /* search back for previous return */
2250 for (start_pc -= instlen;; start_pc -= instlen)
2251 if (start_pc < fence)
2253 /* It's not clear to me why we reach this point when
2254 stop_soon, but with this test, at least we
2255 don't print out warnings for every child forked (eg, on
2256 decstation). 22apr93 rich@cygnus.com. */
2257 if (stop_soon == NO_STOP_QUIETLY)
2259 static int blurb_printed = 0;
2261 warning (_("GDB can't find the start of the function at 0x%s."),
2266 /* This actually happens frequently in embedded
2267 development, when you first connect to a board
2268 and your stack pointer and pc are nowhere in
2269 particular. This message needs to give people
2270 in that situation enough information to
2271 determine that it's no big deal. */
2272 printf_filtered ("\n\
2273 GDB is unable to find the start of the function at 0x%s\n\
2274 and thus can't determine the size of that function's stack frame.\n\
2275 This means that GDB may be unable to access that stack frame, or\n\
2276 the frames below it.\n\
2277 This problem is most likely caused by an invalid program counter or\n\
2279 However, if you think GDB should simply search farther back\n\
2280 from 0x%s for code which looks like the beginning of a\n\
2281 function, you can increase the range of the search using the `set\n\
2282 heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
2289 else if (mips_pc_is_mips16 (start_pc))
2291 unsigned short inst;
2293 /* On MIPS16, any one of the following is likely to be the
2294 start of a function:
2298 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2299 inst = mips_fetch_instruction (start_pc);
2300 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2301 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
2302 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
2303 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
2305 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
2306 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2311 else if (mips_about_to_return (start_pc))
2313 /* Skip return and its delay slot. */
2314 start_pc += 2 * MIPS_INSN32_SIZE;
2321 struct mips_objfile_private
2327 /* According to the current ABI, should the type be passed in a
2328 floating-point register (assuming that there is space)? When there
2329 is no FPU, FP are not even considered as possibile candidates for
2330 FP registers and, consequently this returns false - forces FP
2331 arguments into integer registers. */
2334 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2336 return ((typecode == TYPE_CODE_FLT
2338 && (typecode == TYPE_CODE_STRUCT
2339 || typecode == TYPE_CODE_UNION)
2340 && TYPE_NFIELDS (arg_type) == 1
2341 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2342 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2345 /* On o32, argument passing in GPRs depends on the alignment of the type being
2346 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2349 mips_type_needs_double_align (struct type *type)
2351 enum type_code typecode = TYPE_CODE (type);
2353 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2355 else if (typecode == TYPE_CODE_STRUCT)
2357 if (TYPE_NFIELDS (type) < 1)
2359 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2361 else if (typecode == TYPE_CODE_UNION)
2365 n = TYPE_NFIELDS (type);
2366 for (i = 0; i < n; i++)
2367 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2374 /* Adjust the address downward (direction of stack growth) so that it
2375 is correctly aligned for a new stack frame. */
2377 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2379 return align_down (addr, 16);
2383 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2384 struct regcache *regcache, CORE_ADDR bp_addr,
2385 int nargs, struct value **args, CORE_ADDR sp,
2386 int struct_return, CORE_ADDR struct_addr)
2392 int stack_offset = 0;
2393 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2394 CORE_ADDR func_addr = find_function_addr (function, NULL);
2396 /* For shared libraries, "t9" needs to point at the function
2398 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2400 /* Set the return address register to point to the entry point of
2401 the program, where a breakpoint lies in wait. */
2402 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2404 /* First ensure that the stack and structure return address (if any)
2405 are properly aligned. The stack has to be at least 64-bit
2406 aligned even on 32-bit machines, because doubles must be 64-bit
2407 aligned. For n32 and n64, stack frames need to be 128-bit
2408 aligned, so we round to this widest known alignment. */
2410 sp = align_down (sp, 16);
2411 struct_addr = align_down (struct_addr, 16);
2413 /* Now make space on the stack for the args. We allocate more
2414 than necessary for EABI, because the first few arguments are
2415 passed in registers, but that's OK. */
2416 for (argnum = 0; argnum < nargs; argnum++)
2417 len += align_up (TYPE_LENGTH (value_type (args[argnum])),
2418 mips_stack_argsize (gdbarch));
2419 sp -= align_up (len, 16);
2422 fprintf_unfiltered (gdb_stdlog,
2423 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2424 paddr_nz (sp), (long) align_up (len, 16));
2426 /* Initialize the integer and float register pointers. */
2427 argreg = MIPS_A0_REGNUM;
2428 float_argreg = mips_fpa0_regnum (current_gdbarch);
2430 /* The struct_return pointer occupies the first parameter-passing reg. */
2434 fprintf_unfiltered (gdb_stdlog,
2435 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2436 argreg, paddr_nz (struct_addr));
2437 write_register (argreg++, struct_addr);
2440 /* Now load as many as possible of the first arguments into
2441 registers, and push the rest onto the stack. Loop thru args
2442 from first to last. */
2443 for (argnum = 0; argnum < nargs; argnum++)
2445 const gdb_byte *val;
2446 gdb_byte valbuf[MAX_REGISTER_SIZE];
2447 struct value *arg = args[argnum];
2448 struct type *arg_type = check_typedef (value_type (arg));
2449 int len = TYPE_LENGTH (arg_type);
2450 enum type_code typecode = TYPE_CODE (arg_type);
2453 fprintf_unfiltered (gdb_stdlog,
2454 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2455 argnum + 1, len, (int) typecode);
2457 /* The EABI passes structures that do not fit in a register by
2459 if (len > mips_abi_regsize (gdbarch)
2460 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2462 store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch),
2463 VALUE_ADDRESS (arg));
2464 typecode = TYPE_CODE_PTR;
2465 len = mips_abi_regsize (gdbarch);
2468 fprintf_unfiltered (gdb_stdlog, " push");
2471 val = value_contents (arg);
2473 /* 32-bit ABIs always start floating point arguments in an
2474 even-numbered floating point register. Round the FP register
2475 up before the check to see if there are any FP registers
2476 left. Non MIPS_EABI targets also pass the FP in the integer
2477 registers so also round up normal registers. */
2478 if (mips_abi_regsize (gdbarch) < 8
2479 && fp_register_arg_p (typecode, arg_type))
2481 if ((float_argreg & 1))
2485 /* Floating point arguments passed in registers have to be
2486 treated specially. On 32-bit architectures, doubles
2487 are passed in register pairs; the even register gets
2488 the low word, and the odd register gets the high word.
2489 On non-EABI processors, the first two floating point arguments are
2490 also copied to general registers, because MIPS16 functions
2491 don't use float registers for arguments. This duplication of
2492 arguments in general registers can't hurt non-MIPS16 functions
2493 because those registers are normally skipped. */
2494 /* MIPS_EABI squeezes a struct that contains a single floating
2495 point value into an FP register instead of pushing it onto the
2497 if (fp_register_arg_p (typecode, arg_type)
2498 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2500 if (mips_abi_regsize (gdbarch) < 8 && len == 8)
2502 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2503 unsigned long regval;
2505 /* Write the low word of the double to the even register(s). */
2506 regval = extract_unsigned_integer (val + low_offset, 4);
2508 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2509 float_argreg, phex (regval, 4));
2510 write_register (float_argreg++, regval);
2512 /* Write the high word of the double to the odd register(s). */
2513 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2515 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2516 float_argreg, phex (regval, 4));
2517 write_register (float_argreg++, regval);
2521 /* This is a floating point value that fits entirely
2522 in a single register. */
2523 /* On 32 bit ABI's the float_argreg is further adjusted
2524 above to ensure that it is even register aligned. */
2525 LONGEST regval = extract_unsigned_integer (val, len);
2527 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2528 float_argreg, phex (regval, len));
2529 write_register (float_argreg++, regval);
2534 /* Copy the argument to general registers or the stack in
2535 register-sized pieces. Large arguments are split between
2536 registers and stack. */
2537 /* Note: structs whose size is not a multiple of
2538 mips_abi_regsize() are treated specially: Irix cc passes
2539 them in registers where gcc sometimes puts them on the
2540 stack. For maximum compatibility, we will put them in
2542 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
2543 && (len % mips_abi_regsize (gdbarch) != 0));
2545 /* Note: Floating-point values that didn't fit into an FP
2546 register are only written to memory. */
2549 /* Remember if the argument was written to the stack. */
2550 int stack_used_p = 0;
2551 int partial_len = (len < mips_abi_regsize (gdbarch)
2552 ? len : mips_abi_regsize (gdbarch));
2555 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2558 /* Write this portion of the argument to the stack. */
2559 if (argreg > MIPS_LAST_ARG_REGNUM
2561 || fp_register_arg_p (typecode, arg_type))
2563 /* Should shorter than int integer values be
2564 promoted to int before being stored? */
2565 int longword_offset = 0;
2568 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2570 if (mips_stack_argsize (gdbarch) == 8
2571 && (typecode == TYPE_CODE_INT
2572 || typecode == TYPE_CODE_PTR
2573 || typecode == TYPE_CODE_FLT) && len <= 4)
2574 longword_offset = mips_stack_argsize (gdbarch) - len;
2575 else if ((typecode == TYPE_CODE_STRUCT
2576 || typecode == TYPE_CODE_UNION)
2577 && (TYPE_LENGTH (arg_type)
2578 < mips_stack_argsize (gdbarch)))
2579 longword_offset = mips_stack_argsize (gdbarch) - len;
2584 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2585 paddr_nz (stack_offset));
2586 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2587 paddr_nz (longword_offset));
2590 addr = sp + stack_offset + longword_offset;
2595 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2597 for (i = 0; i < partial_len; i++)
2599 fprintf_unfiltered (gdb_stdlog, "%02x",
2603 write_memory (addr, val, partial_len);
2606 /* Note!!! This is NOT an else clause. Odd sized
2607 structs may go thru BOTH paths. Floating point
2608 arguments will not. */
2609 /* Write this portion of the argument to a general
2610 purpose register. */
2611 if (argreg <= MIPS_LAST_ARG_REGNUM
2612 && !fp_register_arg_p (typecode, arg_type))
2615 extract_unsigned_integer (val, partial_len);
2618 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2621 mips_abi_regsize (gdbarch)));
2622 write_register (argreg, regval);
2629 /* Compute the the offset into the stack at which we
2630 will copy the next parameter.
2632 In the new EABI (and the NABI32), the stack_offset
2633 only needs to be adjusted when it has been used. */
2636 stack_offset += align_up (partial_len,
2637 mips_stack_argsize (gdbarch));
2641 fprintf_unfiltered (gdb_stdlog, "\n");
2644 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2646 /* Return adjusted stack pointer. */
2650 /* Determin the return value convention being used. */
2652 static enum return_value_convention
2653 mips_eabi_return_value (struct gdbarch *gdbarch,
2654 struct type *type, struct regcache *regcache,
2655 gdb_byte *readbuf, const gdb_byte *writebuf)
2657 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2658 return RETURN_VALUE_STRUCT_CONVENTION;
2660 memset (readbuf, 0, TYPE_LENGTH (type));
2661 return RETURN_VALUE_REGISTER_CONVENTION;
2665 /* N32/N64 ABI stuff. */
2668 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2669 struct regcache *regcache, CORE_ADDR bp_addr,
2670 int nargs, struct value **args, CORE_ADDR sp,
2671 int struct_return, CORE_ADDR struct_addr)
2677 int stack_offset = 0;
2678 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2679 CORE_ADDR func_addr = find_function_addr (function, NULL);
2681 /* For shared libraries, "t9" needs to point at the function
2683 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2685 /* Set the return address register to point to the entry point of
2686 the program, where a breakpoint lies in wait. */
2687 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2689 /* First ensure that the stack and structure return address (if any)
2690 are properly aligned. The stack has to be at least 64-bit
2691 aligned even on 32-bit machines, because doubles must be 64-bit
2692 aligned. For n32 and n64, stack frames need to be 128-bit
2693 aligned, so we round to this widest known alignment. */
2695 sp = align_down (sp, 16);
2696 struct_addr = align_down (struct_addr, 16);
2698 /* Now make space on the stack for the args. */
2699 for (argnum = 0; argnum < nargs; argnum++)
2700 len += align_up (TYPE_LENGTH (value_type (args[argnum])),
2701 mips_stack_argsize (gdbarch));
2702 sp -= align_up (len, 16);
2705 fprintf_unfiltered (gdb_stdlog,
2706 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2707 paddr_nz (sp), (long) align_up (len, 16));
2709 /* Initialize the integer and float register pointers. */
2710 argreg = MIPS_A0_REGNUM;
2711 float_argreg = mips_fpa0_regnum (current_gdbarch);
2713 /* The struct_return pointer occupies the first parameter-passing reg. */
2717 fprintf_unfiltered (gdb_stdlog,
2718 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2719 argreg, paddr_nz (struct_addr));
2720 write_register (argreg++, struct_addr);
2723 /* Now load as many as possible of the first arguments into
2724 registers, and push the rest onto the stack. Loop thru args
2725 from first to last. */
2726 for (argnum = 0; argnum < nargs; argnum++)
2728 const gdb_byte *val;
2729 struct value *arg = args[argnum];
2730 struct type *arg_type = check_typedef (value_type (arg));
2731 int len = TYPE_LENGTH (arg_type);
2732 enum type_code typecode = TYPE_CODE (arg_type);
2735 fprintf_unfiltered (gdb_stdlog,
2736 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2737 argnum + 1, len, (int) typecode);
2739 val = value_contents (arg);
2741 if (fp_register_arg_p (typecode, arg_type)
2742 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2744 /* This is a floating point value that fits entirely
2745 in a single register. */
2746 /* On 32 bit ABI's the float_argreg is further adjusted
2747 above to ensure that it is even register aligned. */
2748 LONGEST regval = extract_unsigned_integer (val, len);
2750 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2751 float_argreg, phex (regval, len));
2752 write_register (float_argreg++, regval);
2755 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2756 argreg, phex (regval, len));
2757 write_register (argreg, regval);
2762 /* Copy the argument to general registers or the stack in
2763 register-sized pieces. Large arguments are split between
2764 registers and stack. */
2765 /* Note: structs whose size is not a multiple of
2766 mips_abi_regsize() are treated specially: Irix cc passes
2767 them in registers where gcc sometimes puts them on the
2768 stack. For maximum compatibility, we will put them in
2770 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
2771 && (len % mips_abi_regsize (gdbarch) != 0));
2772 /* Note: Floating-point values that didn't fit into an FP
2773 register are only written to memory. */
2776 /* Rememer if the argument was written to the stack. */
2777 int stack_used_p = 0;
2778 int partial_len = (len < mips_abi_regsize (gdbarch)
2779 ? len : mips_abi_regsize (gdbarch));
2782 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2785 /* Write this portion of the argument to the stack. */
2786 if (argreg > MIPS_LAST_ARG_REGNUM
2788 || fp_register_arg_p (typecode, arg_type))
2790 /* Should shorter than int integer values be
2791 promoted to int before being stored? */
2792 int longword_offset = 0;
2795 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2797 if (mips_stack_argsize (gdbarch) == 8
2798 && (typecode == TYPE_CODE_INT
2799 || typecode == TYPE_CODE_PTR
2800 || typecode == TYPE_CODE_FLT) && len <= 4)
2801 longword_offset = mips_stack_argsize (gdbarch) - len;
2806 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2807 paddr_nz (stack_offset));
2808 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2809 paddr_nz (longword_offset));
2812 addr = sp + stack_offset + longword_offset;
2817 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2819 for (i = 0; i < partial_len; i++)
2821 fprintf_unfiltered (gdb_stdlog, "%02x",
2825 write_memory (addr, val, partial_len);
2828 /* Note!!! This is NOT an else clause. Odd sized
2829 structs may go thru BOTH paths. Floating point
2830 arguments will not. */
2831 /* Write this portion of the argument to a general
2832 purpose register. */
2833 if (argreg <= MIPS_LAST_ARG_REGNUM
2834 && !fp_register_arg_p (typecode, arg_type))
2837 extract_unsigned_integer (val, partial_len);
2839 /* A non-floating-point argument being passed in a
2840 general register. If a struct or union, and if
2841 the remaining length is smaller than the register
2842 size, we have to adjust the register value on
2845 It does not seem to be necessary to do the
2846 same for integral types.
2848 cagney/2001-07-23: gdb/179: Also, GCC, when
2849 outputting LE O32 with sizeof (struct) <
2850 mips_abi_regsize(), generates a left shift as
2851 part of storing the argument in a register a
2852 register (the left shift isn't generated when
2853 sizeof (struct) >= mips_abi_regsize()). Since
2854 it is quite possible that this is GCC
2855 contradicting the LE/O32 ABI, GDB has not been
2856 adjusted to accommodate this. Either someone
2857 needs to demonstrate that the LE/O32 ABI
2858 specifies such a left shift OR this new ABI gets
2859 identified as such and GDB gets tweaked
2862 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2863 && partial_len < mips_abi_regsize (gdbarch)
2864 && (typecode == TYPE_CODE_STRUCT ||
2865 typecode == TYPE_CODE_UNION))
2866 regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
2870 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2873 mips_abi_regsize (gdbarch)));
2874 write_register (argreg, regval);
2881 /* Compute the the offset into the stack at which we
2882 will copy the next parameter.
2884 In N32 (N64?), the stack_offset only needs to be
2885 adjusted when it has been used. */
2888 stack_offset += align_up (partial_len,
2889 mips_stack_argsize (gdbarch));
2893 fprintf_unfiltered (gdb_stdlog, "\n");
2896 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2898 /* Return adjusted stack pointer. */
2902 static enum return_value_convention
2903 mips_n32n64_return_value (struct gdbarch *gdbarch,
2904 struct type *type, struct regcache *regcache,
2905 gdb_byte *readbuf, const gdb_byte *writebuf)
2907 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2908 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2909 || TYPE_CODE (type) == TYPE_CODE_UNION
2910 || TYPE_CODE (type) == TYPE_CODE_ARRAY
2911 || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2912 return RETURN_VALUE_STRUCT_CONVENTION;
2913 else if (TYPE_CODE (type) == TYPE_CODE_FLT
2914 && TYPE_LENGTH (type) == 16
2915 && tdep->mips_fpu_type != MIPS_FPU_NONE)
2917 /* A 128-bit floating-point value fills both $f0 and $f2. The
2918 two registers are used in the same as memory order, so the
2919 eight bytes with the lower memory address are in $f0. */
2921 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
2922 mips_xfer_register (regcache,
2923 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
2924 8, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
2925 mips_xfer_register (regcache,
2926 NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 2,
2927 8, TARGET_BYTE_ORDER, readbuf ? readbuf + 8 : readbuf,
2928 writebuf ? writebuf + 8 : writebuf, 0);
2929 return RETURN_VALUE_REGISTER_CONVENTION;
2931 else if (TYPE_CODE (type) == TYPE_CODE_FLT
2932 && tdep->mips_fpu_type != MIPS_FPU_NONE)
2934 /* A floating-point value belongs in the least significant part
2937 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
2938 mips_xfer_register (regcache,
2939 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
2941 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
2942 return RETURN_VALUE_REGISTER_CONVENTION;
2944 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2945 && TYPE_NFIELDS (type) <= 2
2946 && TYPE_NFIELDS (type) >= 1
2947 && ((TYPE_NFIELDS (type) == 1
2948 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
2950 || (TYPE_NFIELDS (type) == 2
2951 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
2953 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
2955 && tdep->mips_fpu_type != MIPS_FPU_NONE)
2957 /* A struct that contains one or two floats. Each value is part
2958 in the least significant part of their floating point
2962 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
2963 field < TYPE_NFIELDS (type); field++, regnum += 2)
2965 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
2968 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
2970 mips_xfer_register (regcache, NUM_REGS + regnum,
2971 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
2972 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
2974 return RETURN_VALUE_REGISTER_CONVENTION;
2976 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2977 || TYPE_CODE (type) == TYPE_CODE_UNION)
2979 /* A structure or union. Extract the left justified value,
2980 regardless of the byte order. I.e. DO NOT USE
2984 for (offset = 0, regnum = MIPS_V0_REGNUM;
2985 offset < TYPE_LENGTH (type);
2986 offset += register_size (current_gdbarch, regnum), regnum++)
2988 int xfer = register_size (current_gdbarch, regnum);
2989 if (offset + xfer > TYPE_LENGTH (type))
2990 xfer = TYPE_LENGTH (type) - offset;
2992 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
2993 offset, xfer, regnum);
2994 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
2995 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
2997 return RETURN_VALUE_REGISTER_CONVENTION;
3001 /* A scalar extract each part but least-significant-byte
3005 for (offset = 0, regnum = MIPS_V0_REGNUM;
3006 offset < TYPE_LENGTH (type);
3007 offset += register_size (current_gdbarch, regnum), regnum++)
3009 int xfer = register_size (current_gdbarch, regnum);
3010 if (offset + xfer > TYPE_LENGTH (type))
3011 xfer = TYPE_LENGTH (type) - offset;
3013 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3014 offset, xfer, regnum);
3015 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3016 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3018 return RETURN_VALUE_REGISTER_CONVENTION;
3022 /* O32 ABI stuff. */
3025 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3026 struct regcache *regcache, CORE_ADDR bp_addr,
3027 int nargs, struct value **args, CORE_ADDR sp,
3028 int struct_return, CORE_ADDR struct_addr)
3034 int stack_offset = 0;
3035 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3036 CORE_ADDR func_addr = find_function_addr (function, NULL);
3038 /* For shared libraries, "t9" needs to point at the function
3040 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3042 /* Set the return address register to point to the entry point of
3043 the program, where a breakpoint lies in wait. */
3044 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3046 /* First ensure that the stack and structure return address (if any)
3047 are properly aligned. The stack has to be at least 64-bit
3048 aligned even on 32-bit machines, because doubles must be 64-bit
3049 aligned. For n32 and n64, stack frames need to be 128-bit
3050 aligned, so we round to this widest known alignment. */
3052 sp = align_down (sp, 16);
3053 struct_addr = align_down (struct_addr, 16);
3055 /* Now make space on the stack for the args. */
3056 for (argnum = 0; argnum < nargs; argnum++)
3057 len += align_up (TYPE_LENGTH (value_type (args[argnum])),
3058 mips_stack_argsize (gdbarch));
3059 sp -= align_up (len, 16);
3062 fprintf_unfiltered (gdb_stdlog,
3063 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3064 paddr_nz (sp), (long) align_up (len, 16));
3066 /* Initialize the integer and float register pointers. */
3067 argreg = MIPS_A0_REGNUM;
3068 float_argreg = mips_fpa0_regnum (current_gdbarch);
3070 /* The struct_return pointer occupies the first parameter-passing reg. */
3074 fprintf_unfiltered (gdb_stdlog,
3075 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3076 argreg, paddr_nz (struct_addr));
3077 write_register (argreg++, struct_addr);
3078 stack_offset += mips_stack_argsize (gdbarch);
3081 /* Now load as many as possible of the first arguments into
3082 registers, and push the rest onto the stack. Loop thru args
3083 from first to last. */
3084 for (argnum = 0; argnum < nargs; argnum++)
3086 const gdb_byte *val;
3087 struct value *arg = args[argnum];
3088 struct type *arg_type = check_typedef (value_type (arg));
3089 int len = TYPE_LENGTH (arg_type);
3090 enum type_code typecode = TYPE_CODE (arg_type);
3093 fprintf_unfiltered (gdb_stdlog,
3094 "mips_o32_push_dummy_call: %d len=%d type=%d",
3095 argnum + 1, len, (int) typecode);
3097 val = value_contents (arg);
3099 /* 32-bit ABIs always start floating point arguments in an
3100 even-numbered floating point register. Round the FP register
3101 up before the check to see if there are any FP registers
3102 left. O32/O64 targets also pass the FP in the integer
3103 registers so also round up normal registers. */
3104 if (mips_abi_regsize (gdbarch) < 8
3105 && fp_register_arg_p (typecode, arg_type))
3107 if ((float_argreg & 1))
3111 /* Floating point arguments passed in registers have to be
3112 treated specially. On 32-bit architectures, doubles
3113 are passed in register pairs; the even register gets
3114 the low word, and the odd register gets the high word.
3115 On O32/O64, the first two floating point arguments are
3116 also copied to general registers, because MIPS16 functions
3117 don't use float registers for arguments. This duplication of
3118 arguments in general registers can't hurt non-MIPS16 functions
3119 because those registers are normally skipped. */
3121 if (fp_register_arg_p (typecode, arg_type)
3122 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3124 if (mips_abi_regsize (gdbarch) < 8 && len == 8)
3126 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3127 unsigned long regval;
3129 /* Write the low word of the double to the even register(s). */
3130 regval = extract_unsigned_integer (val + low_offset, 4);
3132 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3133 float_argreg, phex (regval, 4));
3134 write_register (float_argreg++, regval);
3136 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3137 argreg, phex (regval, 4));
3138 write_register (argreg++, regval);
3140 /* Write the high word of the double to the odd register(s). */
3141 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3143 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3144 float_argreg, phex (regval, 4));
3145 write_register (float_argreg++, regval);
3148 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3149 argreg, phex (regval, 4));
3150 write_register (argreg++, regval);
3154 /* This is a floating point value that fits entirely
3155 in a single register. */
3156 /* On 32 bit ABI's the float_argreg is further adjusted
3157 above to ensure that it is even register aligned. */
3158 LONGEST regval = extract_unsigned_integer (val, len);
3160 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3161 float_argreg, phex (regval, len));
3162 write_register (float_argreg++, regval);
3163 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3164 registers for each argument. The below is (my
3165 guess) to ensure that the corresponding integer
3166 register has reserved the same space. */
3168 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3169 argreg, phex (regval, len));
3170 write_register (argreg, regval);
3171 argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2;
3173 /* Reserve space for the FP register. */
3174 stack_offset += align_up (len, mips_stack_argsize (gdbarch));
3178 /* Copy the argument to general registers or the stack in
3179 register-sized pieces. Large arguments are split between
3180 registers and stack. */
3181 /* Note: structs whose size is not a multiple of
3182 mips_abi_regsize() are treated specially: Irix cc passes
3183 them in registers where gcc sometimes puts them on the
3184 stack. For maximum compatibility, we will put them in
3186 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
3187 && (len % mips_abi_regsize (gdbarch) != 0));
3188 /* Structures should be aligned to eight bytes (even arg registers)
3189 on MIPS_ABI_O32, if their first member has double precision. */
3190 if (mips_abi_regsize (gdbarch) < 8
3191 && mips_type_needs_double_align (arg_type))
3196 /* Note: Floating-point values that didn't fit into an FP
3197 register are only written to memory. */
3200 /* Remember if the argument was written to the stack. */
3201 int stack_used_p = 0;
3202 int partial_len = (len < mips_abi_regsize (gdbarch)
3203 ? len : mips_abi_regsize (gdbarch));
3206 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3209 /* Write this portion of the argument to the stack. */
3210 if (argreg > MIPS_LAST_ARG_REGNUM
3212 || fp_register_arg_p (typecode, arg_type))
3214 /* Should shorter than int integer values be
3215 promoted to int before being stored? */
3216 int longword_offset = 0;
3219 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3221 if (mips_stack_argsize (gdbarch) == 8
3222 && (typecode == TYPE_CODE_INT
3223 || typecode == TYPE_CODE_PTR
3224 || typecode == TYPE_CODE_FLT) && len <= 4)
3225 longword_offset = mips_stack_argsize (gdbarch) - len;
3230 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3231 paddr_nz (stack_offset));
3232 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3233 paddr_nz (longword_offset));
3236 addr = sp + stack_offset + longword_offset;
3241 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3243 for (i = 0; i < partial_len; i++)
3245 fprintf_unfiltered (gdb_stdlog, "%02x",
3249 write_memory (addr, val, partial_len);
3252 /* Note!!! This is NOT an else clause. Odd sized
3253 structs may go thru BOTH paths. Floating point
3254 arguments will not. */
3255 /* Write this portion of the argument to a general
3256 purpose register. */
3257 if (argreg <= MIPS_LAST_ARG_REGNUM
3258 && !fp_register_arg_p (typecode, arg_type))
3260 LONGEST regval = extract_signed_integer (val, partial_len);
3261 /* Value may need to be sign extended, because
3262 mips_isa_regsize() != mips_abi_regsize(). */
3264 /* A non-floating-point argument being passed in a
3265 general register. If a struct or union, and if
3266 the remaining length is smaller than the register
3267 size, we have to adjust the register value on
3270 It does not seem to be necessary to do the
3271 same for integral types.
3273 Also don't do this adjustment on O64 binaries.
3275 cagney/2001-07-23: gdb/179: Also, GCC, when
3276 outputting LE O32 with sizeof (struct) <
3277 mips_abi_regsize(), generates a left shift as
3278 part of storing the argument in a register a
3279 register (the left shift isn't generated when
3280 sizeof (struct) >= mips_abi_regsize()). Since
3281 it is quite possible that this is GCC
3282 contradicting the LE/O32 ABI, GDB has not been
3283 adjusted to accommodate this. Either someone
3284 needs to demonstrate that the LE/O32 ABI
3285 specifies such a left shift OR this new ABI gets
3286 identified as such and GDB gets tweaked
3289 if (mips_abi_regsize (gdbarch) < 8
3290 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3291 && partial_len < mips_abi_regsize (gdbarch)
3292 && (typecode == TYPE_CODE_STRUCT ||
3293 typecode == TYPE_CODE_UNION))
3294 regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
3298 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3301 mips_abi_regsize (gdbarch)));
3302 write_register (argreg, regval);
3305 /* Prevent subsequent floating point arguments from
3306 being passed in floating point registers. */
3307 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3313 /* Compute the the offset into the stack at which we
3314 will copy the next parameter.
3316 In older ABIs, the caller reserved space for
3317 registers that contained arguments. This was loosely
3318 refered to as their "home". Consequently, space is
3319 always allocated. */
3321 stack_offset += align_up (partial_len,
3322 mips_stack_argsize (gdbarch));
3326 fprintf_unfiltered (gdb_stdlog, "\n");
3329 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3331 /* Return adjusted stack pointer. */
3335 static enum return_value_convention
3336 mips_o32_return_value (struct gdbarch *gdbarch, struct type *type,
3337 struct regcache *regcache,
3338 gdb_byte *readbuf, const gdb_byte *writebuf)
3340 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3342 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3343 || TYPE_CODE (type) == TYPE_CODE_UNION
3344 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3345 return RETURN_VALUE_STRUCT_CONVENTION;
3346 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3347 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3349 /* A single-precision floating-point value. It fits in the
3350 least significant part of FP0. */
3352 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3353 mips_xfer_register (regcache,
3354 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3356 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3357 return RETURN_VALUE_REGISTER_CONVENTION;
3359 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3360 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3362 /* A double-precision floating-point value. The most
3363 significant part goes in FP1, and the least significant in
3366 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3367 switch (TARGET_BYTE_ORDER)
3369 case BFD_ENDIAN_LITTLE:
3370 mips_xfer_register (regcache,
3371 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3372 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3373 mips_xfer_register (regcache,
3374 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3375 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3377 case BFD_ENDIAN_BIG:
3378 mips_xfer_register (regcache,
3379 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3380 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3381 mips_xfer_register (regcache,
3382 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3383 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3386 internal_error (__FILE__, __LINE__, _("bad switch"));
3388 return RETURN_VALUE_REGISTER_CONVENTION;
3391 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3392 && TYPE_NFIELDS (type) <= 2
3393 && TYPE_NFIELDS (type) >= 1
3394 && ((TYPE_NFIELDS (type) == 1
3395 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3397 || (TYPE_NFIELDS (type) == 2
3398 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3400 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3402 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3404 /* A struct that contains one or two floats. Each value is part
3405 in the least significant part of their floating point
3407 gdb_byte reg[MAX_REGISTER_SIZE];
3410 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
3411 field < TYPE_NFIELDS (type); field++, regnum += 2)
3413 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3416 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3418 mips_xfer_register (regcache, NUM_REGS + regnum,
3419 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3420 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3422 return RETURN_VALUE_REGISTER_CONVENTION;
3426 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3427 || TYPE_CODE (type) == TYPE_CODE_UNION)
3429 /* A structure or union. Extract the left justified value,
3430 regardless of the byte order. I.e. DO NOT USE
3434 for (offset = 0, regnum = MIPS_V0_REGNUM;
3435 offset < TYPE_LENGTH (type);
3436 offset += register_size (current_gdbarch, regnum), regnum++)
3438 int xfer = register_size (current_gdbarch, regnum);
3439 if (offset + xfer > TYPE_LENGTH (type))
3440 xfer = TYPE_LENGTH (type) - offset;
3442 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3443 offset, xfer, regnum);
3444 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3445 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3447 return RETURN_VALUE_REGISTER_CONVENTION;
3452 /* A scalar extract each part but least-significant-byte
3453 justified. o32 thinks registers are 4 byte, regardless of
3454 the ISA. mips_stack_argsize controls this. */
3457 for (offset = 0, regnum = MIPS_V0_REGNUM;
3458 offset < TYPE_LENGTH (type);
3459 offset += mips_stack_argsize (gdbarch), regnum++)
3461 int xfer = mips_stack_argsize (gdbarch);
3462 if (offset + xfer > TYPE_LENGTH (type))
3463 xfer = TYPE_LENGTH (type) - offset;
3465 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3466 offset, xfer, regnum);
3467 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3468 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3470 return RETURN_VALUE_REGISTER_CONVENTION;
3474 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3478 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3479 struct regcache *regcache, CORE_ADDR bp_addr,
3481 struct value **args, CORE_ADDR sp,
3482 int struct_return, CORE_ADDR struct_addr)
3488 int stack_offset = 0;
3489 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3490 CORE_ADDR func_addr = find_function_addr (function, NULL);
3492 /* For shared libraries, "t9" needs to point at the function
3494 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3496 /* Set the return address register to point to the entry point of
3497 the program, where a breakpoint lies in wait. */
3498 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3500 /* First ensure that the stack and structure return address (if any)
3501 are properly aligned. The stack has to be at least 64-bit
3502 aligned even on 32-bit machines, because doubles must be 64-bit
3503 aligned. For n32 and n64, stack frames need to be 128-bit
3504 aligned, so we round to this widest known alignment. */
3506 sp = align_down (sp, 16);
3507 struct_addr = align_down (struct_addr, 16);
3509 /* Now make space on the stack for the args. */
3510 for (argnum = 0; argnum < nargs; argnum++)
3511 len += align_up (TYPE_LENGTH (value_type (args[argnum])),
3512 mips_stack_argsize (gdbarch));
3513 sp -= align_up (len, 16);
3516 fprintf_unfiltered (gdb_stdlog,
3517 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3518 paddr_nz (sp), (long) align_up (len, 16));
3520 /* Initialize the integer and float register pointers. */
3521 argreg = MIPS_A0_REGNUM;
3522 float_argreg = mips_fpa0_regnum (current_gdbarch);
3524 /* The struct_return pointer occupies the first parameter-passing reg. */
3528 fprintf_unfiltered (gdb_stdlog,
3529 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3530 argreg, paddr_nz (struct_addr));
3531 write_register (argreg++, struct_addr);
3532 stack_offset += mips_stack_argsize (gdbarch);
3535 /* Now load as many as possible of the first arguments into
3536 registers, and push the rest onto the stack. Loop thru args
3537 from first to last. */
3538 for (argnum = 0; argnum < nargs; argnum++)
3540 const gdb_byte *val;
3541 struct value *arg = args[argnum];
3542 struct type *arg_type = check_typedef (value_type (arg));
3543 int len = TYPE_LENGTH (arg_type);
3544 enum type_code typecode = TYPE_CODE (arg_type);
3547 fprintf_unfiltered (gdb_stdlog,
3548 "mips_o64_push_dummy_call: %d len=%d type=%d",
3549 argnum + 1, len, (int) typecode);
3551 val = value_contents (arg);
3553 /* 32-bit ABIs always start floating point arguments in an
3554 even-numbered floating point register. Round the FP register
3555 up before the check to see if there are any FP registers
3556 left. O32/O64 targets also pass the FP in the integer
3557 registers so also round up normal registers. */
3558 if (mips_abi_regsize (gdbarch) < 8
3559 && fp_register_arg_p (typecode, arg_type))
3561 if ((float_argreg & 1))
3565 /* Floating point arguments passed in registers have to be
3566 treated specially. On 32-bit architectures, doubles
3567 are passed in register pairs; the even register gets
3568 the low word, and the odd register gets the high word.
3569 On O32/O64, the first two floating point arguments are
3570 also copied to general registers, because MIPS16 functions
3571 don't use float registers for arguments. This duplication of
3572 arguments in general registers can't hurt non-MIPS16 functions
3573 because those registers are normally skipped. */
3575 if (fp_register_arg_p (typecode, arg_type)
3576 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3578 if (mips_abi_regsize (gdbarch) < 8 && len == 8)
3580 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3581 unsigned long regval;
3583 /* Write the low word of the double to the even register(s). */
3584 regval = extract_unsigned_integer (val + low_offset, 4);
3586 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3587 float_argreg, phex (regval, 4));
3588 write_register (float_argreg++, regval);
3590 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3591 argreg, phex (regval, 4));
3592 write_register (argreg++, regval);
3594 /* Write the high word of the double to the odd register(s). */
3595 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3597 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3598 float_argreg, phex (regval, 4));
3599 write_register (float_argreg++, regval);
3602 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3603 argreg, phex (regval, 4));
3604 write_register (argreg++, regval);
3608 /* This is a floating point value that fits entirely
3609 in a single register. */
3610 /* On 32 bit ABI's the float_argreg is further adjusted
3611 above to ensure that it is even register aligned. */
3612 LONGEST regval = extract_unsigned_integer (val, len);
3614 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3615 float_argreg, phex (regval, len));
3616 write_register (float_argreg++, regval);
3617 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3618 registers for each argument. The below is (my
3619 guess) to ensure that the corresponding integer
3620 register has reserved the same space. */
3622 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3623 argreg, phex (regval, len));
3624 write_register (argreg, regval);
3625 argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2;
3627 /* Reserve space for the FP register. */
3628 stack_offset += align_up (len, mips_stack_argsize (gdbarch));
3632 /* Copy the argument to general registers or the stack in
3633 register-sized pieces. Large arguments are split between
3634 registers and stack. */
3635 /* Note: structs whose size is not a multiple of
3636 mips_abi_regsize() are treated specially: Irix cc passes
3637 them in registers where gcc sometimes puts them on the
3638 stack. For maximum compatibility, we will put them in
3640 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
3641 && (len % mips_abi_regsize (gdbarch) != 0));
3642 /* Structures should be aligned to eight bytes (even arg registers)
3643 on MIPS_ABI_O32, if their first member has double precision. */
3644 if (mips_abi_regsize (gdbarch) < 8
3645 && mips_type_needs_double_align (arg_type))
3650 /* Note: Floating-point values that didn't fit into an FP
3651 register are only written to memory. */
3654 /* Remember if the argument was written to the stack. */
3655 int stack_used_p = 0;
3656 int partial_len = (len < mips_abi_regsize (gdbarch)
3657 ? len : mips_abi_regsize (gdbarch));
3660 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3663 /* Write this portion of the argument to the stack. */
3664 if (argreg > MIPS_LAST_ARG_REGNUM
3666 || fp_register_arg_p (typecode, arg_type))
3668 /* Should shorter than int integer values be
3669 promoted to int before being stored? */
3670 int longword_offset = 0;
3673 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3675 if (mips_stack_argsize (gdbarch) == 8
3676 && (typecode == TYPE_CODE_INT
3677 || typecode == TYPE_CODE_PTR
3678 || typecode == TYPE_CODE_FLT) && len <= 4)
3679 longword_offset = mips_stack_argsize (gdbarch) - len;
3684 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3685 paddr_nz (stack_offset));
3686 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3687 paddr_nz (longword_offset));
3690 addr = sp + stack_offset + longword_offset;
3695 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3697 for (i = 0; i < partial_len; i++)
3699 fprintf_unfiltered (gdb_stdlog, "%02x",
3703 write_memory (addr, val, partial_len);
3706 /* Note!!! This is NOT an else clause. Odd sized
3707 structs may go thru BOTH paths. Floating point
3708 arguments will not. */
3709 /* Write this portion of the argument to a general
3710 purpose register. */
3711 if (argreg <= MIPS_LAST_ARG_REGNUM
3712 && !fp_register_arg_p (typecode, arg_type))
3714 LONGEST regval = extract_signed_integer (val, partial_len);
3715 /* Value may need to be sign extended, because
3716 mips_isa_regsize() != mips_abi_regsize(). */
3718 /* A non-floating-point argument being passed in a
3719 general register. If a struct or union, and if
3720 the remaining length is smaller than the register
3721 size, we have to adjust the register value on
3724 It does not seem to be necessary to do the
3725 same for integral types.
3727 Also don't do this adjustment on O64 binaries.
3729 cagney/2001-07-23: gdb/179: Also, GCC, when
3730 outputting LE O32 with sizeof (struct) <
3731 mips_abi_regsize(), generates a left shift as
3732 part of storing the argument in a register a
3733 register (the left shift isn't generated when
3734 sizeof (struct) >= mips_abi_regsize()). Since
3735 it is quite possible that this is GCC
3736 contradicting the LE/O32 ABI, GDB has not been
3737 adjusted to accommodate this. Either someone
3738 needs to demonstrate that the LE/O32 ABI
3739 specifies such a left shift OR this new ABI gets
3740 identified as such and GDB gets tweaked
3743 if (mips_abi_regsize (gdbarch) < 8
3744 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3745 && partial_len < mips_abi_regsize (gdbarch)
3746 && (typecode == TYPE_CODE_STRUCT ||
3747 typecode == TYPE_CODE_UNION))
3748 regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
3752 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3755 mips_abi_regsize (gdbarch)));
3756 write_register (argreg, regval);
3759 /* Prevent subsequent floating point arguments from
3760 being passed in floating point registers. */
3761 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3767 /* Compute the the offset into the stack at which we
3768 will copy the next parameter.
3770 In older ABIs, the caller reserved space for
3771 registers that contained arguments. This was loosely
3772 refered to as their "home". Consequently, space is
3773 always allocated. */
3775 stack_offset += align_up (partial_len,
3776 mips_stack_argsize (gdbarch));
3780 fprintf_unfiltered (gdb_stdlog, "\n");
3783 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3785 /* Return adjusted stack pointer. */
3789 static enum return_value_convention
3790 mips_o64_return_value (struct gdbarch *gdbarch,
3791 struct type *type, struct regcache *regcache,
3792 gdb_byte *readbuf, const gdb_byte *writebuf)
3794 return RETURN_VALUE_STRUCT_CONVENTION;
3797 /* Floating point register management.
3799 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3800 64bit operations, these early MIPS cpus treat fp register pairs
3801 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3802 registers and offer a compatibility mode that emulates the MIPS2 fp
3803 model. When operating in MIPS2 fp compat mode, later cpu's split
3804 double precision floats into two 32-bit chunks and store them in
3805 consecutive fp regs. To display 64-bit floats stored in this
3806 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3807 Throw in user-configurable endianness and you have a real mess.
3809 The way this works is:
3810 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3811 double-precision value will be split across two logical registers.
3812 The lower-numbered logical register will hold the low-order bits,
3813 regardless of the processor's endianness.
3814 - If we are on a 64-bit processor, and we are looking for a
3815 single-precision value, it will be in the low ordered bits
3816 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3817 save slot in memory.
3818 - If we are in 64-bit mode, everything is straightforward.
3820 Note that this code only deals with "live" registers at the top of the
3821 stack. We will attempt to deal with saved registers later, when
3822 the raw/cooked register interface is in place. (We need a general
3823 interface that can deal with dynamic saved register sizes -- fp
3824 regs could be 32 bits wide in one frame and 64 on the frame above
3827 static struct type *
3828 mips_float_register_type (void)
3830 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3831 return builtin_type_ieee_single_big;
3833 return builtin_type_ieee_single_little;
3836 static struct type *
3837 mips_double_register_type (void)
3839 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3840 return builtin_type_ieee_double_big;
3842 return builtin_type_ieee_double_little;
3845 /* Copy a 32-bit single-precision value from the current frame
3846 into rare_buffer. */
3849 mips_read_fp_register_single (struct frame_info *frame, int regno,
3850 gdb_byte *rare_buffer)
3852 int raw_size = register_size (current_gdbarch, regno);
3853 gdb_byte *raw_buffer = alloca (raw_size);
3855 if (!frame_register_read (frame, regno, raw_buffer))
3856 error (_("can't read register %d (%s)"), regno, REGISTER_NAME (regno));
3859 /* We have a 64-bit value for this register. Find the low-order
3863 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3868 memcpy (rare_buffer, raw_buffer + offset, 4);
3872 memcpy (rare_buffer, raw_buffer, 4);
3876 /* Copy a 64-bit double-precision value from the current frame into
3877 rare_buffer. This may include getting half of it from the next
3881 mips_read_fp_register_double (struct frame_info *frame, int regno,
3882 gdb_byte *rare_buffer)
3884 int raw_size = register_size (current_gdbarch, regno);
3886 if (raw_size == 8 && !mips2_fp_compat ())
3888 /* We have a 64-bit value for this register, and we should use
3890 if (!frame_register_read (frame, regno, rare_buffer))
3891 error (_("can't read register %d (%s)"), regno, REGISTER_NAME (regno));
3895 if ((regno - mips_regnum (current_gdbarch)->fp0) & 1)
3896 internal_error (__FILE__, __LINE__,
3897 _("mips_read_fp_register_double: bad access to "
3898 "odd-numbered FP register"));
3900 /* mips_read_fp_register_single will find the correct 32 bits from
3902 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3904 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
3905 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
3909 mips_read_fp_register_single (frame, regno, rare_buffer);
3910 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
3916 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
3918 { /* do values for FP (float) regs */
3919 gdb_byte *raw_buffer;
3920 double doub, flt1; /* doubles extracted from raw hex data */
3923 raw_buffer = alloca (2 * register_size (current_gdbarch,
3924 mips_regnum (current_gdbarch)->fp0));
3926 fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
3927 fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
3930 if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ())
3932 /* 4-byte registers: Print hex and floating. Also print even
3933 numbered registers as doubles. */
3934 mips_read_fp_register_single (frame, regnum, raw_buffer);
3935 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
3937 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
3940 fprintf_filtered (file, " flt: ");
3942 fprintf_filtered (file, " <invalid float> ");
3944 fprintf_filtered (file, "%-17.9g", flt1);
3946 if (regnum % 2 == 0)
3948 mips_read_fp_register_double (frame, regnum, raw_buffer);
3949 doub = unpack_double (mips_double_register_type (), raw_buffer,
3952 fprintf_filtered (file, " dbl: ");
3954 fprintf_filtered (file, "<invalid double>");
3956 fprintf_filtered (file, "%-24.17g", doub);
3961 /* Eight byte registers: print each one as hex, float and double. */
3962 mips_read_fp_register_single (frame, regnum, raw_buffer);
3963 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
3965 mips_read_fp_register_double (frame, regnum, raw_buffer);
3966 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
3969 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
3972 fprintf_filtered (file, " flt: ");
3974 fprintf_filtered (file, "<invalid float>");
3976 fprintf_filtered (file, "%-17.9g", flt1);
3978 fprintf_filtered (file, " dbl: ");
3980 fprintf_filtered (file, "<invalid double>");
3982 fprintf_filtered (file, "%-24.17g", doub);
3987 mips_print_register (struct ui_file *file, struct frame_info *frame,
3988 int regnum, int all)
3990 struct gdbarch *gdbarch = get_frame_arch (frame);
3991 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
3994 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
3996 mips_print_fp_register (file, frame, regnum);
4000 /* Get the data in raw format. */
4001 if (!frame_register_read (frame, regnum, raw_buffer))
4003 fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum));
4007 fputs_filtered (REGISTER_NAME (regnum), file);
4009 /* The problem with printing numeric register names (r26, etc.) is that
4010 the user can't use them on input. Probably the best solution is to
4011 fix it so that either the numeric or the funky (a2, etc.) names
4012 are accepted on input. */
4013 if (regnum < MIPS_NUMREGS)
4014 fprintf_filtered (file, "(r%d): ", regnum);
4016 fprintf_filtered (file, ": ");
4018 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4020 register_size (current_gdbarch,
4021 regnum) - register_size (current_gdbarch, regnum);
4025 print_scalar_formatted (raw_buffer + offset,
4026 gdbarch_register_type (gdbarch, regnum), 'x', 0,
4030 /* Replacement for generic do_registers_info.
4031 Print regs in pretty columns. */
4034 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4037 fprintf_filtered (file, " ");
4038 mips_print_fp_register (file, frame, regnum);
4039 fprintf_filtered (file, "\n");
4044 /* Print a row's worth of GP (int) registers, with name labels above */
4047 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4050 struct gdbarch *gdbarch = get_frame_arch (frame);
4051 /* do values for GP (int) regs */
4052 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4053 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4057 /* For GP registers, we print a separate row of names above the vals */
4058 for (col = 0, regnum = start_regnum;
4059 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4061 if (*REGISTER_NAME (regnum) == '\0')
4062 continue; /* unused register */
4063 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4065 break; /* end the row: reached FP register */
4067 fprintf_filtered (file, " ");
4068 fprintf_filtered (file,
4069 mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
4070 REGISTER_NAME (regnum));
4077 /* print the R0 to R31 names */
4078 if ((start_regnum % NUM_REGS) < MIPS_NUMREGS)
4079 fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS);
4081 fprintf_filtered (file, "\n ");
4083 /* now print the values in hex, 4 or 8 to the row */
4084 for (col = 0, regnum = start_regnum;
4085 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4087 if (*REGISTER_NAME (regnum) == '\0')
4088 continue; /* unused register */
4089 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4091 break; /* end row: reached FP register */
4092 /* OK: get the data in raw format. */
4093 if (!frame_register_read (frame, regnum, raw_buffer))
4094 error (_("can't read register %d (%s)"), regnum, REGISTER_NAME (regnum));
4095 /* pad small registers */
4097 byte < (mips_abi_regsize (current_gdbarch)
4098 - register_size (current_gdbarch, regnum)); byte++)
4099 printf_filtered (" ");
4100 /* Now print the register value in hex, endian order. */
4101 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4103 register_size (current_gdbarch,
4104 regnum) - register_size (current_gdbarch, regnum);
4105 byte < register_size (current_gdbarch, regnum); byte++)
4106 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4108 for (byte = register_size (current_gdbarch, regnum) - 1;
4110 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4111 fprintf_filtered (file, " ");
4114 if (col > 0) /* ie. if we actually printed anything... */
4115 fprintf_filtered (file, "\n");
4120 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4123 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4124 struct frame_info *frame, int regnum, int all)
4126 if (regnum != -1) /* do one specified register */
4128 gdb_assert (regnum >= NUM_REGS);
4129 if (*(REGISTER_NAME (regnum)) == '\0')
4130 error (_("Not a valid register for the current processor type"));
4132 mips_print_register (file, frame, regnum, 0);
4133 fprintf_filtered (file, "\n");
4136 /* do all (or most) registers */
4139 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4141 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4144 if (all) /* true for "INFO ALL-REGISTERS" command */
4145 regnum = print_fp_register_row (file, frame, regnum);
4147 regnum += MIPS_NUMREGS; /* skip floating point regs */
4150 regnum = print_gp_register_row (file, frame, regnum);
4155 /* Is this a branch with a delay slot? */
4158 is_delayed (unsigned long insn)
4161 for (i = 0; i < NUMOPCODES; ++i)
4162 if (mips_opcodes[i].pinfo != INSN_MACRO
4163 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4165 return (i < NUMOPCODES
4166 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4167 | INSN_COND_BRANCH_DELAY
4168 | INSN_COND_BRANCH_LIKELY)));
4172 mips_single_step_through_delay (struct gdbarch *gdbarch,
4173 struct frame_info *frame)
4175 CORE_ADDR pc = get_frame_pc (frame);
4176 gdb_byte buf[MIPS_INSN32_SIZE];
4178 /* There is no branch delay slot on MIPS16. */
4179 if (mips_pc_is_mips16 (pc))
4182 if (!breakpoint_here_p (pc + 4))
4185 if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf))
4186 /* If error reading memory, guess that it is not a delayed
4189 return is_delayed (extract_unsigned_integer (buf, sizeof buf));
4192 /* To skip prologues, I use this predicate. Returns either PC itself
4193 if the code at PC does not look like a function prologue; otherwise
4194 returns an address that (if we're lucky) follows the prologue. If
4195 LENIENT, then we must skip everything which is involved in setting
4196 up the frame (it's OK to skip more, just so long as we don't skip
4197 anything which might clobber the registers which are being saved.
4198 We must skip more in the case where part of the prologue is in the
4199 delay slot of a non-prologue instruction). */
4202 mips_skip_prologue (CORE_ADDR pc)
4205 CORE_ADDR func_addr;
4207 /* See if we can determine the end of the prologue via the symbol table.
4208 If so, then return either PC, or the PC after the prologue, whichever
4210 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
4212 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
4213 if (post_prologue_pc != 0)
4214 return max (pc, post_prologue_pc);
4217 /* Can't determine prologue from the symbol table, need to examine
4220 /* Find an upper limit on the function prologue using the debug
4221 information. If the debug information could not be used to provide
4222 that bound, then use an arbitrary large number as the upper bound. */
4223 limit_pc = skip_prologue_using_sal (pc);
4225 limit_pc = pc + 100; /* Magic. */
4227 if (mips_pc_is_mips16 (pc))
4228 return mips16_scan_prologue (pc, limit_pc, NULL, NULL);
4230 return mips32_scan_prologue (pc, limit_pc, NULL, NULL);
4233 /* Root of all "set mips "/"show mips " commands. This will eventually be
4234 used for all MIPS-specific commands. */
4237 show_mips_command (char *args, int from_tty)
4239 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4243 set_mips_command (char *args, int from_tty)
4246 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4247 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4250 /* Commands to show/set the MIPS FPU type. */
4253 show_mipsfpu_command (char *args, int from_tty)
4256 switch (MIPS_FPU_TYPE)
4258 case MIPS_FPU_SINGLE:
4259 fpu = "single-precision";
4261 case MIPS_FPU_DOUBLE:
4262 fpu = "double-precision";
4265 fpu = "absent (none)";
4268 internal_error (__FILE__, __LINE__, _("bad switch"));
4270 if (mips_fpu_type_auto)
4272 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4276 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4281 set_mipsfpu_command (char *args, int from_tty)
4284 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4285 show_mipsfpu_command (args, from_tty);
4289 set_mipsfpu_single_command (char *args, int from_tty)
4291 struct gdbarch_info info;
4292 gdbarch_info_init (&info);
4293 mips_fpu_type = MIPS_FPU_SINGLE;
4294 mips_fpu_type_auto = 0;
4295 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4296 instead of relying on globals. Doing that would let generic code
4297 handle the search for this specific architecture. */
4298 if (!gdbarch_update_p (info))
4299 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4303 set_mipsfpu_double_command (char *args, int from_tty)
4305 struct gdbarch_info info;
4306 gdbarch_info_init (&info);
4307 mips_fpu_type = MIPS_FPU_DOUBLE;
4308 mips_fpu_type_auto = 0;
4309 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4310 instead of relying on globals. Doing that would let generic code
4311 handle the search for this specific architecture. */
4312 if (!gdbarch_update_p (info))
4313 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4317 set_mipsfpu_none_command (char *args, int from_tty)
4319 struct gdbarch_info info;
4320 gdbarch_info_init (&info);
4321 mips_fpu_type = MIPS_FPU_NONE;
4322 mips_fpu_type_auto = 0;
4323 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4324 instead of relying on globals. Doing that would let generic code
4325 handle the search for this specific architecture. */
4326 if (!gdbarch_update_p (info))
4327 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4331 set_mipsfpu_auto_command (char *args, int from_tty)
4333 mips_fpu_type_auto = 1;
4336 /* Attempt to identify the particular processor model by reading the
4337 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4338 the relevant processor still exists (it dates back to '94) and
4339 secondly this is not the way to do this. The processor type should
4340 be set by forcing an architecture change. */
4343 deprecated_mips_set_processor_regs_hack (void)
4345 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4348 prid = read_register (MIPS_PRID_REGNUM);
4350 if ((prid & ~0xf) == 0x700)
4351 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4354 /* Just like reinit_frame_cache, but with the right arguments to be
4355 callable as an sfunc. */
4358 reinit_frame_cache_sfunc (char *args, int from_tty,
4359 struct cmd_list_element *c)
4361 reinit_frame_cache ();
4365 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4367 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4369 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4370 disassembler needs to be able to locally determine the ISA, and
4371 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4373 if (mips_pc_is_mips16 (memaddr))
4374 info->mach = bfd_mach_mips16;
4376 /* Round down the instruction address to the appropriate boundary. */
4377 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4379 /* Set the disassembler options. */
4380 if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64)
4382 /* Set up the disassembler info, so that we get the right
4383 register names from libopcodes. */
4384 if (tdep->mips_abi == MIPS_ABI_N32)
4385 info->disassembler_options = "gpr-names=n32";
4387 info->disassembler_options = "gpr-names=64";
4388 info->flavour = bfd_target_elf_flavour;
4391 /* This string is not recognized explicitly by the disassembler,
4392 but it tells the disassembler to not try to guess the ABI from
4393 the bfd elf headers, such that, if the user overrides the ABI
4394 of a program linked as NewABI, the disassembly will follow the
4395 register naming conventions specified by the user. */
4396 info->disassembler_options = "gpr-names=32";
4398 /* Call the appropriate disassembler based on the target endian-ness. */
4399 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4400 return print_insn_big_mips (memaddr, info);
4402 return print_insn_little_mips (memaddr, info);
4405 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4406 counter value to determine whether a 16- or 32-bit breakpoint should be
4407 used. It returns a pointer to a string of bytes that encode a breakpoint
4408 instruction, stores the length of the string to *lenptr, and adjusts pc
4409 (if necessary) to point to the actual memory location where the
4410 breakpoint should be inserted. */
4412 static const gdb_byte *
4413 mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
4415 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4417 if (mips_pc_is_mips16 (*pcptr))
4419 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
4420 *pcptr = unmake_mips16_addr (*pcptr);
4421 *lenptr = sizeof (mips16_big_breakpoint);
4422 return mips16_big_breakpoint;
4426 /* The IDT board uses an unusual breakpoint value, and
4427 sometimes gets confused when it sees the usual MIPS
4428 breakpoint instruction. */
4429 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
4430 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
4431 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
4433 *lenptr = sizeof (big_breakpoint);
4435 if (strcmp (target_shortname, "mips") == 0)
4436 return idt_big_breakpoint;
4437 else if (strcmp (target_shortname, "ddb") == 0
4438 || strcmp (target_shortname, "pmon") == 0
4439 || strcmp (target_shortname, "lsi") == 0)
4440 return pmon_big_breakpoint;
4442 return big_breakpoint;
4447 if (mips_pc_is_mips16 (*pcptr))
4449 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
4450 *pcptr = unmake_mips16_addr (*pcptr);
4451 *lenptr = sizeof (mips16_little_breakpoint);
4452 return mips16_little_breakpoint;
4456 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
4457 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
4458 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
4460 *lenptr = sizeof (little_breakpoint);
4462 if (strcmp (target_shortname, "mips") == 0)
4463 return idt_little_breakpoint;
4464 else if (strcmp (target_shortname, "ddb") == 0
4465 || strcmp (target_shortname, "pmon") == 0
4466 || strcmp (target_shortname, "lsi") == 0)
4467 return pmon_little_breakpoint;
4469 return little_breakpoint;
4474 /* If PC is in a mips16 call or return stub, return the address of the target
4475 PC, which is either the callee or the caller. There are several
4476 cases which must be handled:
4478 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4479 target PC is in $31 ($ra).
4480 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4481 and the target PC is in $2.
4482 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4483 before the jal instruction, this is effectively a call stub
4484 and the the target PC is in $2. Otherwise this is effectively
4485 a return stub and the target PC is in $18.
4487 See the source code for the stubs in gcc/config/mips/mips16.S for
4491 mips_skip_trampoline_code (CORE_ADDR pc)
4494 CORE_ADDR start_addr;
4496 /* Find the starting address and name of the function containing the PC. */
4497 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
4500 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4501 target PC is in $31 ($ra). */
4502 if (strcmp (name, "__mips16_ret_sf") == 0
4503 || strcmp (name, "__mips16_ret_df") == 0)
4504 return read_signed_register (MIPS_RA_REGNUM);
4506 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
4508 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4509 and the target PC is in $2. */
4510 if (name[19] >= '0' && name[19] <= '9')
4511 return read_signed_register (2);
4513 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4514 before the jal instruction, this is effectively a call stub
4515 and the the target PC is in $2. Otherwise this is effectively
4516 a return stub and the target PC is in $18. */
4517 else if (name[19] == 's' || name[19] == 'd')
4519 if (pc == start_addr)
4521 /* Check if the target of the stub is a compiler-generated
4522 stub. Such a stub for a function bar might have a name
4523 like __fn_stub_bar, and might look like this:
4528 la $1,bar (becomes a lui/addiu pair)
4530 So scan down to the lui/addi and extract the target
4531 address from those two instructions. */
4533 CORE_ADDR target_pc = read_signed_register (2);
4537 /* See if the name of the target function is __fn_stub_*. */
4538 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
4541 if (strncmp (name, "__fn_stub_", 10) != 0
4542 && strcmp (name, "etext") != 0
4543 && strcmp (name, "_etext") != 0)
4546 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4547 The limit on the search is arbitrarily set to 20
4548 instructions. FIXME. */
4549 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE)
4551 inst = mips_fetch_instruction (target_pc);
4552 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
4553 pc = (inst << 16) & 0xffff0000; /* high word */
4554 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
4555 return pc | (inst & 0xffff); /* low word */
4558 /* Couldn't find the lui/addui pair, so return stub address. */
4562 /* This is the 'return' part of a call stub. The return
4563 address is in $r18. */
4564 return read_signed_register (18);
4567 return 0; /* not a stub */
4570 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4571 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4574 mips_stab_reg_to_regnum (int num)
4577 if (num >= 0 && num < 32)
4579 else if (num >= 38 && num < 70)
4580 regnum = num + mips_regnum (current_gdbarch)->fp0 - 38;
4582 regnum = mips_regnum (current_gdbarch)->hi;
4584 regnum = mips_regnum (current_gdbarch)->lo;
4586 /* This will hopefully (eventually) provoke a warning. Should
4587 we be calling complaint() here? */
4588 return NUM_REGS + NUM_PSEUDO_REGS;
4589 return NUM_REGS + regnum;
4593 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4594 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4597 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
4600 if (num >= 0 && num < 32)
4602 else if (num >= 32 && num < 64)
4603 regnum = num + mips_regnum (current_gdbarch)->fp0 - 32;
4605 regnum = mips_regnum (current_gdbarch)->hi;
4607 regnum = mips_regnum (current_gdbarch)->lo;
4609 /* This will hopefully (eventually) provoke a warning. Should we
4610 be calling complaint() here? */
4611 return NUM_REGS + NUM_PSEUDO_REGS;
4612 return NUM_REGS + regnum;
4616 mips_register_sim_regno (int regnum)
4618 /* Only makes sense to supply raw registers. */
4619 gdb_assert (regnum >= 0 && regnum < NUM_REGS);
4620 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4621 decide if it is valid. Should instead define a standard sim/gdb
4622 register numbering scheme. */
4623 if (REGISTER_NAME (NUM_REGS + regnum) != NULL
4624 && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0')
4627 return LEGACY_SIM_REGNO_IGNORE;
4631 /* Convert an integer into an address. By first converting the value
4632 into a pointer and then extracting it signed, the address is
4633 guarenteed to be correctly sign extended. */
4636 mips_integer_to_address (struct gdbarch *gdbarch,
4637 struct type *type, const gdb_byte *buf)
4639 gdb_byte *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
4640 LONGEST val = unpack_long (type, buf);
4641 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
4642 return extract_signed_integer (tmp,
4643 TYPE_LENGTH (builtin_type_void_data_ptr));
4647 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
4649 enum mips_abi *abip = (enum mips_abi *) obj;
4650 const char *name = bfd_get_section_name (abfd, sect);
4652 if (*abip != MIPS_ABI_UNKNOWN)
4655 if (strncmp (name, ".mdebug.", 8) != 0)
4658 if (strcmp (name, ".mdebug.abi32") == 0)
4659 *abip = MIPS_ABI_O32;
4660 else if (strcmp (name, ".mdebug.abiN32") == 0)
4661 *abip = MIPS_ABI_N32;
4662 else if (strcmp (name, ".mdebug.abi64") == 0)
4663 *abip = MIPS_ABI_N64;
4664 else if (strcmp (name, ".mdebug.abiO64") == 0)
4665 *abip = MIPS_ABI_O64;
4666 else if (strcmp (name, ".mdebug.eabi32") == 0)
4667 *abip = MIPS_ABI_EABI32;
4668 else if (strcmp (name, ".mdebug.eabi64") == 0)
4669 *abip = MIPS_ABI_EABI64;
4671 warning (_("unsupported ABI %s."), name + 8);
4674 static enum mips_abi
4675 global_mips_abi (void)
4679 for (i = 0; mips_abi_strings[i] != NULL; i++)
4680 if (mips_abi_strings[i] == mips_abi_string)
4681 return (enum mips_abi) i;
4683 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
4686 static struct gdbarch *
4687 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4689 struct gdbarch *gdbarch;
4690 struct gdbarch_tdep *tdep;
4692 enum mips_abi mips_abi, found_abi, wanted_abi;
4694 enum mips_fpu_type fpu_type;
4696 /* First of all, extract the elf_flags, if available. */
4697 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
4698 elf_flags = elf_elfheader (info.abfd)->e_flags;
4699 else if (arches != NULL)
4700 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
4704 fprintf_unfiltered (gdb_stdlog,
4705 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
4707 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4708 switch ((elf_flags & EF_MIPS_ABI))
4710 case E_MIPS_ABI_O32:
4711 found_abi = MIPS_ABI_O32;
4713 case E_MIPS_ABI_O64:
4714 found_abi = MIPS_ABI_O64;
4716 case E_MIPS_ABI_EABI32:
4717 found_abi = MIPS_ABI_EABI32;
4719 case E_MIPS_ABI_EABI64:
4720 found_abi = MIPS_ABI_EABI64;
4723 if ((elf_flags & EF_MIPS_ABI2))
4724 found_abi = MIPS_ABI_N32;
4726 found_abi = MIPS_ABI_UNKNOWN;
4730 /* GCC creates a pseudo-section whose name describes the ABI. */
4731 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
4732 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
4734 /* If we have no useful BFD information, use the ABI from the last
4735 MIPS architecture (if there is one). */
4736 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
4737 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
4739 /* Try the architecture for any hint of the correct ABI. */
4740 if (found_abi == MIPS_ABI_UNKNOWN
4741 && info.bfd_arch_info != NULL
4742 && info.bfd_arch_info->arch == bfd_arch_mips)
4744 switch (info.bfd_arch_info->mach)
4746 case bfd_mach_mips3900:
4747 found_abi = MIPS_ABI_EABI32;
4749 case bfd_mach_mips4100:
4750 case bfd_mach_mips5000:
4751 found_abi = MIPS_ABI_EABI64;
4753 case bfd_mach_mips8000:
4754 case bfd_mach_mips10000:
4755 /* On Irix, ELF64 executables use the N64 ABI. The
4756 pseudo-sections which describe the ABI aren't present
4757 on IRIX. (Even for executables created by gcc.) */
4758 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
4759 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
4760 found_abi = MIPS_ABI_N64;
4762 found_abi = MIPS_ABI_N32;
4767 /* Default 64-bit objects to N64 instead of O32. */
4768 if (found_abi == MIPS_ABI_UNKNOWN
4769 && info.abfd != NULL
4770 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
4771 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
4772 found_abi = MIPS_ABI_N64;
4775 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
4778 /* What has the user specified from the command line? */
4779 wanted_abi = global_mips_abi ();
4781 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
4784 /* Now that we have found what the ABI for this binary would be,
4785 check whether the user is overriding it. */
4786 if (wanted_abi != MIPS_ABI_UNKNOWN)
4787 mips_abi = wanted_abi;
4788 else if (found_abi != MIPS_ABI_UNKNOWN)
4789 mips_abi = found_abi;
4791 mips_abi = MIPS_ABI_O32;
4793 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
4796 /* Also used when doing an architecture lookup. */
4798 fprintf_unfiltered (gdb_stdlog,
4799 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4800 mips64_transfers_32bit_regs_p);
4802 /* Determine the MIPS FPU type. */
4803 if (!mips_fpu_type_auto)
4804 fpu_type = mips_fpu_type;
4805 else if (info.bfd_arch_info != NULL
4806 && info.bfd_arch_info->arch == bfd_arch_mips)
4807 switch (info.bfd_arch_info->mach)
4809 case bfd_mach_mips3900:
4810 case bfd_mach_mips4100:
4811 case bfd_mach_mips4111:
4812 case bfd_mach_mips4120:
4813 fpu_type = MIPS_FPU_NONE;
4815 case bfd_mach_mips4650:
4816 fpu_type = MIPS_FPU_SINGLE;
4819 fpu_type = MIPS_FPU_DOUBLE;
4822 else if (arches != NULL)
4823 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
4825 fpu_type = MIPS_FPU_DOUBLE;
4827 fprintf_unfiltered (gdb_stdlog,
4828 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
4830 /* try to find a pre-existing architecture */
4831 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4833 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4835 /* MIPS needs to be pedantic about which ABI the object is
4837 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
4839 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
4841 /* Need to be pedantic about which register virtual size is
4843 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
4844 != mips64_transfers_32bit_regs_p)
4846 /* Be pedantic about which FPU is selected. */
4847 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
4849 return arches->gdbarch;
4852 /* Need a new architecture. Fill in a target specific vector. */
4853 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4854 gdbarch = gdbarch_alloc (&info, tdep);
4855 tdep->elf_flags = elf_flags;
4856 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
4857 tdep->found_abi = found_abi;
4858 tdep->mips_abi = mips_abi;
4859 tdep->mips_fpu_type = fpu_type;
4861 /* Initially set everything according to the default ABI/ISA. */
4862 set_gdbarch_short_bit (gdbarch, 16);
4863 set_gdbarch_int_bit (gdbarch, 32);
4864 set_gdbarch_float_bit (gdbarch, 32);
4865 set_gdbarch_double_bit (gdbarch, 64);
4866 set_gdbarch_long_double_bit (gdbarch, 64);
4867 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
4868 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
4869 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
4871 set_gdbarch_elf_make_msymbol_special (gdbarch,
4872 mips_elf_make_msymbol_special);
4874 /* Fill in the OS dependant register numbers and names. */
4876 const char **reg_names;
4877 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
4878 struct mips_regnum);
4879 if (info.osabi == GDB_OSABI_IRIX)
4884 regnum->badvaddr = 66;
4887 regnum->fp_control_status = 69;
4888 regnum->fp_implementation_revision = 70;
4890 reg_names = mips_irix_reg_names;
4894 regnum->lo = MIPS_EMBED_LO_REGNUM;
4895 regnum->hi = MIPS_EMBED_HI_REGNUM;
4896 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
4897 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
4898 regnum->pc = MIPS_EMBED_PC_REGNUM;
4899 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
4900 regnum->fp_control_status = 70;
4901 regnum->fp_implementation_revision = 71;
4903 if (info.bfd_arch_info != NULL
4904 && info.bfd_arch_info->mach == bfd_mach_mips3900)
4905 reg_names = mips_tx39_reg_names;
4907 reg_names = mips_generic_reg_names;
4909 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
4910 replaced by read_pc? */
4911 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
4912 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
4913 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
4914 set_gdbarch_num_regs (gdbarch, num_regs);
4915 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
4916 set_gdbarch_register_name (gdbarch, mips_register_name);
4917 tdep->mips_processor_reg_names = reg_names;
4918 tdep->regnum = regnum;
4924 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
4925 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
4926 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
4927 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
4928 tdep->default_mask_address_p = 0;
4929 set_gdbarch_long_bit (gdbarch, 32);
4930 set_gdbarch_ptr_bit (gdbarch, 32);
4931 set_gdbarch_long_long_bit (gdbarch, 64);
4934 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
4935 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
4936 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
4937 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
4938 tdep->default_mask_address_p = 0;
4939 set_gdbarch_long_bit (gdbarch, 32);
4940 set_gdbarch_ptr_bit (gdbarch, 32);
4941 set_gdbarch_long_long_bit (gdbarch, 64);
4943 case MIPS_ABI_EABI32:
4944 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
4945 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
4946 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
4947 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
4948 tdep->default_mask_address_p = 0;
4949 set_gdbarch_long_bit (gdbarch, 32);
4950 set_gdbarch_ptr_bit (gdbarch, 32);
4951 set_gdbarch_long_long_bit (gdbarch, 64);
4953 case MIPS_ABI_EABI64:
4954 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
4955 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
4956 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
4957 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
4958 tdep->default_mask_address_p = 0;
4959 set_gdbarch_long_bit (gdbarch, 64);
4960 set_gdbarch_ptr_bit (gdbarch, 64);
4961 set_gdbarch_long_long_bit (gdbarch, 64);
4964 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
4965 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
4966 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
4967 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
4968 tdep->default_mask_address_p = 0;
4969 set_gdbarch_long_bit (gdbarch, 32);
4970 set_gdbarch_ptr_bit (gdbarch, 32);
4971 set_gdbarch_long_long_bit (gdbarch, 64);
4972 set_gdbarch_long_double_bit (gdbarch, 128);
4973 set_gdbarch_long_double_format (gdbarch,
4974 &floatformat_n32n64_long_double_big);
4977 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
4978 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
4979 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
4980 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
4981 tdep->default_mask_address_p = 0;
4982 set_gdbarch_long_bit (gdbarch, 64);
4983 set_gdbarch_ptr_bit (gdbarch, 64);
4984 set_gdbarch_long_long_bit (gdbarch, 64);
4985 set_gdbarch_long_double_bit (gdbarch, 128);
4986 set_gdbarch_long_double_format (gdbarch,
4987 &floatformat_n32n64_long_double_big);
4990 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
4993 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4994 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4997 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4998 flag in object files because to do so would make it impossible to
4999 link with libraries compiled without "-gp32". This is
5000 unnecessarily restrictive.
5002 We could solve this problem by adding "-gp32" multilibs to gcc,
5003 but to set this flag before gcc is built with such multilibs will
5004 break too many systems.''
5006 But even more unhelpfully, the default linker output target for
5007 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5008 for 64-bit programs - you need to change the ABI to change this,
5009 and not all gcc targets support that currently. Therefore using
5010 this flag to detect 32-bit mode would do the wrong thing given
5011 the current gcc - it would make GDB treat these 64-bit programs
5012 as 32-bit programs by default. */
5014 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5015 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5016 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5018 /* Add/remove bits from an address. The MIPS needs be careful to
5019 ensure that all 32 bit addresses are sign extended to 64 bits. */
5020 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5022 /* Unwind the frame. */
5023 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5024 set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id);
5026 /* Map debug register numbers onto internal register numbers. */
5027 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5028 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5029 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5030 set_gdbarch_dwarf_reg_to_regnum (gdbarch,
5031 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5032 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5033 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5034 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5036 /* MIPS version of CALL_DUMMY */
5038 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5039 replaced by a command, and all targets will default to on stack
5040 (regardless of the stack's execute status). */
5041 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5042 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5044 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
5045 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
5046 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
5048 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5049 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5051 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5053 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5054 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5055 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5057 set_gdbarch_register_type (gdbarch, mips_register_type);
5059 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5061 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
5063 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5064 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5065 need to all be folded into the target vector. Since they are
5066 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5067 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5069 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
5071 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
5073 set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay);
5075 /* Hook in OS ABI-specific overrides, if they have been registered. */
5076 gdbarch_init_osabi (info, gdbarch);
5078 /* Unwind the frame. */
5079 frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer);
5080 frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer);
5081 frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer);
5082 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
5083 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
5084 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
5090 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
5092 struct gdbarch_info info;
5094 /* Force the architecture to update, and (if it's a MIPS architecture)
5095 mips_gdbarch_init will take care of the rest. */
5096 gdbarch_info_init (&info);
5097 gdbarch_update_p (info);
5100 /* Print out which MIPS ABI is in use. */
5103 show_mips_abi (struct ui_file *file,
5105 struct cmd_list_element *ignored_cmd,
5106 const char *ignored_value)
5108 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
5111 "The MIPS ABI is unknown because the current architecture "
5115 enum mips_abi global_abi = global_mips_abi ();
5116 enum mips_abi actual_abi = mips_abi (current_gdbarch);
5117 const char *actual_abi_str = mips_abi_strings[actual_abi];
5119 if (global_abi == MIPS_ABI_UNKNOWN)
5122 "The MIPS ABI is set automatically (currently \"%s\").\n",
5124 else if (global_abi == actual_abi)
5127 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5131 /* Probably shouldn't happen... */
5134 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5135 actual_abi_str, mips_abi_strings[global_abi]);
5141 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
5143 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
5147 int ef_mips_32bitmode;
5148 /* determine the ISA */
5149 switch (tdep->elf_flags & EF_MIPS_ARCH)
5167 /* determine the size of a pointer */
5168 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
5169 fprintf_unfiltered (file,
5170 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5172 fprintf_unfiltered (file,
5173 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5175 fprintf_unfiltered (file,
5176 "mips_dump_tdep: ef_mips_arch = %d\n",
5178 fprintf_unfiltered (file,
5179 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5180 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
5181 fprintf_unfiltered (file,
5182 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5183 mips_mask_address_p (tdep),
5184 tdep->default_mask_address_p);
5186 fprintf_unfiltered (file,
5187 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5188 MIPS_DEFAULT_FPU_TYPE,
5189 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
5190 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5191 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5193 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI);
5194 fprintf_unfiltered (file,
5195 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5197 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
5198 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5199 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5201 fprintf_unfiltered (file,
5202 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5203 mips_stack_argsize (current_gdbarch));
5206 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
5209 _initialize_mips_tdep (void)
5211 static struct cmd_list_element *mipsfpulist = NULL;
5212 struct cmd_list_element *c;
5214 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
5215 if (MIPS_ABI_LAST + 1
5216 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
5217 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
5219 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
5221 mips_pdr_data = register_objfile_data ();
5223 /* Add root prefix command for all "set mips"/"show mips" commands */
5224 add_prefix_cmd ("mips", no_class, set_mips_command,
5225 _("Various MIPS specific commands."),
5226 &setmipscmdlist, "set mips ", 0, &setlist);
5228 add_prefix_cmd ("mips", no_class, show_mips_command,
5229 _("Various MIPS specific commands."),
5230 &showmipscmdlist, "show mips ", 0, &showlist);
5232 /* Allow the user to override the saved register size. */
5233 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure,
5234 size_enums, &mips_abi_regsize_string, _("\
5235 Set size of general purpose registers saved on the stack."), _("\
5236 Show size of general purpose registers saved on the stack."), _("\
5237 This option can be set to one of:\n\
5238 32 - Force GDB to treat saved GP registers as 32-bit\n\
5239 64 - Force GDB to treat saved GP registers as 64-bit\n\
5240 auto - Allow GDB to use the target's default setting or autodetect the\n\
5241 saved GP register size from information contained in the\n\
5242 executable (default)."),
5244 NULL, /* FIXME: i18n: Size of general purpose registers saved on the stack is %s. */
5245 &setmipscmdlist, &showmipscmdlist);
5247 /* Allow the user to override the argument stack size. */
5248 add_setshow_enum_cmd ("stack-arg-size", class_obscure,
5249 size_enums, &mips_stack_argsize_string, _("\
5250 Set the amount of stack space reserved for each argument."), _("\
5251 Show the amount of stack space reserved for each argument."), _("\
5252 This option can be set to one of:\n\
5253 32 - Force GDB to allocate 32-bit chunks per argument\n\
5254 64 - Force GDB to allocate 64-bit chunks per argument\n\
5255 auto - Allow GDB to determine the correct setting from the current\n\
5256 target and executable (default)"),
5258 NULL, /* FIXME: i18n: The amount of stack space reserved for each argument is %s. */
5259 &setmipscmdlist, &showmipscmdlist);
5261 /* Allow the user to override the ABI. */
5262 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
5263 &mips_abi_string, _("\
5264 Set the MIPS ABI used by this program."), _("\
5265 Show the MIPS ABI used by this program."), _("\
5266 This option can be set to one of:\n\
5267 auto - the default ABI associated with the current binary\n\
5276 &setmipscmdlist, &showmipscmdlist);
5278 /* Let the user turn off floating point and set the fence post for
5279 heuristic_proc_start. */
5281 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
5282 _("Set use of MIPS floating-point coprocessor."),
5283 &mipsfpulist, "set mipsfpu ", 0, &setlist);
5284 add_cmd ("single", class_support, set_mipsfpu_single_command,
5285 _("Select single-precision MIPS floating-point coprocessor."),
5287 add_cmd ("double", class_support, set_mipsfpu_double_command,
5288 _("Select double-precision MIPS floating-point coprocessor."),
5290 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
5291 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
5292 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
5293 add_cmd ("none", class_support, set_mipsfpu_none_command,
5294 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
5295 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
5296 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
5297 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
5298 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
5299 _("Select MIPS floating-point coprocessor automatically."),
5301 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
5302 _("Show current use of MIPS floating-point coprocessor target."),
5305 /* We really would like to have both "0" and "unlimited" work, but
5306 command.c doesn't deal with that. So make it a var_zinteger
5307 because the user can always use "999999" or some such for unlimited. */
5308 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
5309 &heuristic_fence_post, _("\
5310 Set the distance searched for the start of a function."), _("\
5311 Show the distance searched for the start of a function."), _("\
5312 If you are debugging a stripped executable, GDB needs to search through the\n\
5313 program for the start of a function. This command sets the distance of the\n\
5314 search. The only need to set it is when debugging a stripped executable."),
5315 reinit_frame_cache_sfunc,
5316 NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5317 &setlist, &showlist);
5319 /* Allow the user to control whether the upper bits of 64-bit
5320 addresses should be zeroed. */
5321 add_setshow_auto_boolean_cmd ("mask-address", no_class,
5322 &mask_address_var, _("\
5323 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5324 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5325 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5326 allow GDB to determine the correct value."),
5327 NULL, show_mask_address,
5328 &setmipscmdlist, &showmipscmdlist);
5330 /* Allow the user to control the size of 32 bit registers within the
5331 raw remote packet. */
5332 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
5333 &mips64_transfers_32bit_regs_p, _("\
5334 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5336 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5338 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5339 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5340 64 bits for others. Use \"off\" to disable compatibility mode"),
5341 set_mips64_transfers_32bit_regs,
5342 NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5343 &setlist, &showlist);
5345 /* Debug this files internals. */
5346 add_setshow_zinteger_cmd ("mips", class_maintenance,
5348 Set mips debugging."), _("\
5349 Show mips debugging."), _("\
5350 When non-zero, mips specific debugging is enabled."),
5352 NULL, /* FIXME: i18n: Mips debugging is currently %s. */
5353 &setdebuglist, &showdebuglist);