1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
40 #include "arch-utils.h"
43 #include "mips-tdep.h"
46 #include "opcode/mips.h"
51 static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off);
53 /* A useful bit in the CP0 status register (PS_REGNUM). */
54 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
55 #define ST0_FR (1 << 26)
57 /* The sizes of floating point registers. */
61 MIPS_FPU_SINGLE_REGSIZE = 4,
62 MIPS_FPU_DOUBLE_REGSIZE = 8
66 static const char *mips_abi_string;
68 static const char *mips_abi_strings[] = {
79 struct frame_extra_info
81 mips_extra_func_info_t proc_desc;
85 /* Various MIPS ISA options (related to stack analysis) can be
86 overridden dynamically. Establish an enum/array for managing
89 static const char size_auto[] = "auto";
90 static const char size_32[] = "32";
91 static const char size_64[] = "64";
93 static const char *size_enums[] = {
100 /* Some MIPS boards don't support floating point while others only
101 support single-precision floating-point operations. See also
102 FP_REGISTER_DOUBLE. */
106 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
107 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
108 MIPS_FPU_NONE /* No floating point. */
111 #ifndef MIPS_DEFAULT_FPU_TYPE
112 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
114 static int mips_fpu_type_auto = 1;
115 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
117 static int mips_debug = 0;
119 /* MIPS specific per-architecture information */
122 /* from the elf header */
126 enum mips_abi mips_abi;
127 enum mips_abi found_abi;
128 enum mips_fpu_type mips_fpu_type;
129 int mips_last_arg_regnum;
130 int mips_last_fp_arg_regnum;
131 int mips_default_saved_regsize;
132 int mips_fp_register_double;
133 int mips_default_stack_argsize;
134 int gdb_target_is_mips64;
135 int default_mask_address_p;
138 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
139 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
141 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
143 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
145 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
147 /* Return the currently configured (or set) saved register size. */
149 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
151 static const char *mips_saved_regsize_string = size_auto;
153 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
155 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
156 functions to test, set, or clear bit 0 of addresses. */
159 is_mips16_addr (CORE_ADDR addr)
165 make_mips16_addr (CORE_ADDR addr)
171 unmake_mips16_addr (CORE_ADDR addr)
173 return ((addr) & ~1);
176 /* Return the contents of register REGNUM as a signed integer. */
179 read_signed_register (int regnum)
181 void *buf = alloca (REGISTER_RAW_SIZE (regnum));
182 deprecated_read_register_gen (regnum, buf);
183 return (extract_signed_integer (buf, REGISTER_RAW_SIZE (regnum)));
187 read_signed_register_pid (int regnum, ptid_t ptid)
192 if (ptid_equal (ptid, inferior_ptid))
193 return read_signed_register (regnum);
195 save_ptid = inferior_ptid;
197 inferior_ptid = ptid;
199 retval = read_signed_register (regnum);
201 inferior_ptid = save_ptid;
206 /* Return the MIPS ABI associated with GDBARCH. */
208 mips_abi (struct gdbarch *gdbarch)
210 return gdbarch_tdep (gdbarch)->mips_abi;
214 mips_saved_regsize (void)
216 if (mips_saved_regsize_string == size_auto)
217 return MIPS_DEFAULT_SAVED_REGSIZE;
218 else if (mips_saved_regsize_string == size_64)
220 else /* if (mips_saved_regsize_string == size_32) */
224 /* Functions for setting and testing a bit in a minimal symbol that
225 marks it as 16-bit function. The MSB of the minimal symbol's
226 "info" field is used for this purpose. This field is already
227 being used to store the symbol size, so the assumption is
228 that the symbol size cannot exceed 2^31.
230 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
231 i.e. refers to a 16-bit function, and sets a "special" bit in a
232 minimal symbol to mark it as a 16-bit function
234 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
235 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
236 the "info" field with the "special" bit masked out */
239 mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
241 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16)
243 MSYMBOL_INFO (msym) = (char *)
244 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
245 SYMBOL_VALUE_ADDRESS (msym) |= 1;
250 msymbol_is_special (struct minimal_symbol *msym)
252 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
256 msymbol_size (struct minimal_symbol *msym)
258 return ((long) MSYMBOL_INFO (msym) & 0x7fffffff);
261 /* XFER a value from the big/little/left end of the register.
262 Depending on the size of the value it might occupy the entire
263 register or just part of it. Make an allowance for this, aligning
264 things accordingly. */
267 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
268 enum bfd_endian endian, bfd_byte *in, const bfd_byte *out,
271 bfd_byte reg[MAX_REGISTER_SIZE];
273 /* Need to transfer the left or right part of the register, based on
274 the targets byte order. */
278 reg_offset = REGISTER_RAW_SIZE (reg_num) - length;
280 case BFD_ENDIAN_LITTLE:
283 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
287 internal_error (__FILE__, __LINE__, "bad switch");
290 fprintf_unfiltered (gdb_stderr,
291 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
292 reg_num, reg_offset, buf_offset, length);
293 if (mips_debug && out != NULL)
296 fprintf_unfiltered (gdb_stdlog, "out ");
297 for (i = 0; i < length; i++)
298 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
301 regcache_raw_read_part (regcache, reg_num, reg_offset, length, in + buf_offset);
303 regcache_raw_write_part (regcache, reg_num, reg_offset, length, out + buf_offset);
304 if (mips_debug && in != NULL)
307 fprintf_unfiltered (gdb_stdlog, "in ");
308 for (i = 0; i < length; i++)
309 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
312 fprintf_unfiltered (gdb_stdlog, "\n");
315 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
316 compatiblity mode. A return value of 1 means that we have
317 physical 64-bit registers, but should treat them as 32-bit registers. */
320 mips2_fp_compat (void)
322 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
324 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
328 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
329 in all the places we deal with FP registers. PR gdb/413. */
330 /* Otherwise check the FR bit in the status register - it controls
331 the FP compatiblity mode. If it is clear we are in compatibility
333 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
340 /* Indicate that the ABI makes use of double-precision registers
341 provided by the FPU (rather than combining pairs of registers to
342 form double-precision values). Do not use "TARGET_IS_MIPS64" to
343 determine if the ABI is using double-precision registers. See also
345 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
347 /* The amount of space reserved on the stack for registers. This is
348 different to MIPS_SAVED_REGSIZE as it determines the alignment of
349 data allocated after the registers have run out. */
351 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
353 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
355 static const char *mips_stack_argsize_string = size_auto;
358 mips_stack_argsize (void)
360 if (mips_stack_argsize_string == size_auto)
361 return MIPS_DEFAULT_STACK_ARGSIZE;
362 else if (mips_stack_argsize_string == size_64)
364 else /* if (mips_stack_argsize_string == size_32) */
368 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
370 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
372 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
374 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
376 static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR,
377 struct frame_info *, int);
379 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
381 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
383 static int mips_set_processor_type (char *);
385 static void mips_show_processor_type_command (char *, int);
387 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
389 static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc,
390 struct frame_info *next_frame,
393 static CORE_ADDR after_prologue (CORE_ADDR pc,
394 mips_extra_func_info_t proc_desc);
396 static struct type *mips_float_register_type (void);
397 static struct type *mips_double_register_type (void);
399 /* This value is the model of MIPS in use. It is derived from the value
400 of the PrID register. */
402 char *mips_processor_type;
404 char *tmp_mips_processor_type;
406 /* The list of available "set mips " and "show mips " commands */
408 static struct cmd_list_element *setmipscmdlist = NULL;
409 static struct cmd_list_element *showmipscmdlist = NULL;
411 /* A set of original names, to be used when restoring back to generic
412 registers from a specific set. */
413 static char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
415 /* Integer registers 0 thru 31 are handled explicitly by
416 mips_register_name(). Processor specific registers 32 and above
417 are listed in the sets of register names assigned to
418 mips_processor_reg_names. */
419 static char **mips_processor_reg_names = mips_generic_reg_names;
421 /* Return the name of the register corresponding to REGNO. */
423 mips_register_name (int regno)
425 /* GPR names for all ABIs other than n32/n64. */
426 static char *mips_gpr_names[] = {
427 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
428 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
429 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
430 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
433 /* GPR names for n32 and n64 ABIs. */
434 static char *mips_n32_n64_gpr_names[] = {
435 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
436 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
437 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
438 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
441 enum mips_abi abi = mips_abi (current_gdbarch);
443 /* The MIPS integer registers are always mapped from 0 to 31. The
444 names of the registers (which reflects the conventions regarding
445 register use) vary depending on the ABI. */
446 if (0 <= regno && regno < 32)
448 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
449 return mips_n32_n64_gpr_names[regno];
451 return mips_gpr_names[regno];
453 else if (32 <= regno && regno < NUM_REGS)
454 return mips_processor_reg_names[regno - 32];
456 internal_error (__FILE__, __LINE__,
457 "mips_register_name: bad register number %d", regno);
461 /* Names of IDT R3041 registers. */
463 char *mips_r3041_reg_names[] = {
464 "sr", "lo", "hi", "bad", "cause","pc",
465 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
466 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
467 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
468 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
469 "fsr", "fir", "",/*"fp"*/ "",
470 "", "", "bus", "ccfg", "", "", "", "",
471 "", "", "port", "cmp", "", "", "epc", "prid",
474 /* Names of IDT R3051 registers. */
476 char *mips_r3051_reg_names[] = {
477 "sr", "lo", "hi", "bad", "cause","pc",
478 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
479 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
480 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
481 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
482 "fsr", "fir", ""/*"fp"*/, "",
483 "inx", "rand", "elo", "", "ctxt", "", "", "",
484 "", "", "ehi", "", "", "", "epc", "prid",
487 /* Names of IDT R3081 registers. */
489 char *mips_r3081_reg_names[] = {
490 "sr", "lo", "hi", "bad", "cause","pc",
491 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
492 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
493 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
494 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
495 "fsr", "fir", ""/*"fp"*/, "",
496 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
497 "", "", "ehi", "", "", "", "epc", "prid",
500 /* Names of LSI 33k registers. */
502 char *mips_lsi33k_reg_names[] = {
503 "epc", "hi", "lo", "sr", "cause","badvaddr",
504 "dcic", "bpc", "bda", "", "", "", "", "",
505 "", "", "", "", "", "", "", "",
506 "", "", "", "", "", "", "", "",
507 "", "", "", "", "", "", "", "",
509 "", "", "", "", "", "", "", "",
510 "", "", "", "", "", "", "", "",
516 } mips_processor_type_table[] = {
517 { "generic", mips_generic_reg_names },
518 { "r3041", mips_r3041_reg_names },
519 { "r3051", mips_r3051_reg_names },
520 { "r3071", mips_r3081_reg_names },
521 { "r3081", mips_r3081_reg_names },
522 { "lsi33k", mips_lsi33k_reg_names },
530 /* Table to translate MIPS16 register field to actual register number. */
531 static int mips16_to_32_reg[8] =
532 {16, 17, 2, 3, 4, 5, 6, 7};
534 /* Heuristic_proc_start may hunt through the text section for a long
535 time across a 2400 baud serial line. Allows the user to limit this
538 static unsigned int heuristic_fence_post = 0;
540 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
541 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
542 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
543 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
544 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
545 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
546 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
547 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
548 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
549 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
550 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
551 this will corrupt pdr.iline. Fortunately we don't use it. */
552 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
553 #define _PROC_MAGIC_ 0x0F0F0F0F
554 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
555 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
557 struct linked_proc_info
559 struct mips_extra_func_info info;
560 struct linked_proc_info *next;
562 *linked_proc_desc_table = NULL;
565 mips_print_extra_frame_info (struct frame_info *fi)
568 && get_frame_extra_info (fi)
569 && get_frame_extra_info (fi)->proc_desc
570 && get_frame_extra_info (fi)->proc_desc->pdr.framereg < NUM_REGS)
571 printf_filtered (" frame pointer is at %s+%s\n",
572 REGISTER_NAME (get_frame_extra_info (fi)->proc_desc->pdr.framereg),
573 paddr_d (get_frame_extra_info (fi)->proc_desc->pdr.frameoffset));
576 /* Number of bytes of storage in the actual machine representation for
577 register N. NOTE: This indirectly defines the register size
578 transfered by the GDB protocol. */
580 static int mips64_transfers_32bit_regs_p = 0;
583 mips_register_raw_size (int reg_nr)
585 if (mips64_transfers_32bit_regs_p)
586 return REGISTER_VIRTUAL_SIZE (reg_nr);
587 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
588 && FP_REGISTER_DOUBLE)
589 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
596 /* Convert between RAW and VIRTUAL registers. The RAW register size
597 defines the remote-gdb packet. */
600 mips_register_convertible (int reg_nr)
602 if (mips64_transfers_32bit_regs_p)
605 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
609 mips_register_convert_to_virtual (int n, struct type *virtual_type,
610 char *raw_buf, char *virt_buf)
612 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
614 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
615 TYPE_LENGTH (virtual_type));
619 TYPE_LENGTH (virtual_type));
623 mips_register_convert_to_raw (struct type *virtual_type, int n,
624 char *virt_buf, char *raw_buf)
626 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
627 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
628 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
630 TYPE_LENGTH (virtual_type));
634 TYPE_LENGTH (virtual_type));
638 mips_register_convert_to_type (int regnum, struct type *type, char *buffer)
640 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
641 && REGISTER_RAW_SIZE (regnum) == 4
642 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
643 && TYPE_CODE(type) == TYPE_CODE_FLT
644 && TYPE_LENGTH(type) == 8)
647 memcpy (temp, ((char *)(buffer))+4, 4);
648 memcpy (((char *)(buffer))+4, (buffer), 4);
649 memcpy (((char *)(buffer)), temp, 4);
654 mips_register_convert_from_type (int regnum, struct type *type, char *buffer)
656 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
657 && REGISTER_RAW_SIZE (regnum) == 4
658 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
659 && TYPE_CODE(type) == TYPE_CODE_FLT
660 && TYPE_LENGTH(type) == 8)
663 memcpy (temp, ((char *)(buffer))+4, 4);
664 memcpy (((char *)(buffer))+4, (buffer), 4);
665 memcpy (((char *)(buffer)), temp, 4);
669 /* Return the GDB type object for the "standard" data type
670 of data in register REG.
672 Note: kevinb/2002-08-01: The definition below should faithfully
673 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
674 definitions found in config/mips/tm-*.h. I'm concerned about the
675 ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause though.
676 In some cases DEPRECATED_FP_REGNUM is in this range, and I doubt
677 that this code is correct for the 64-bit case. */
680 mips_register_virtual_type (int reg)
682 if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32)
684 /* Floating point registers... */
685 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
686 return builtin_type_ieee_double_big;
688 return builtin_type_ieee_double_little;
690 else if (reg == PS_REGNUM /* CR */)
691 return builtin_type_uint32;
692 else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM)
693 return builtin_type_uint32;
696 /* Everything else...
697 Return type appropriate for width of register. */
698 if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64))
699 return builtin_type_uint64;
701 return builtin_type_uint32;
705 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
710 return read_signed_register (SP_REGNUM);
713 /* Should the upper word of 64-bit addresses be zeroed? */
714 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
717 mips_mask_address_p (void)
719 switch (mask_address_var)
721 case AUTO_BOOLEAN_TRUE:
723 case AUTO_BOOLEAN_FALSE:
726 case AUTO_BOOLEAN_AUTO:
727 return MIPS_DEFAULT_MASK_ADDRESS_P;
729 internal_error (__FILE__, __LINE__,
730 "mips_mask_address_p: bad switch");
736 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
738 switch (mask_address_var)
740 case AUTO_BOOLEAN_TRUE:
741 printf_filtered ("The 32 bit mips address mask is enabled\n");
743 case AUTO_BOOLEAN_FALSE:
744 printf_filtered ("The 32 bit mips address mask is disabled\n");
746 case AUTO_BOOLEAN_AUTO:
747 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
748 mips_mask_address_p () ? "enabled" : "disabled");
751 internal_error (__FILE__, __LINE__,
752 "show_mask_address: bad switch");
757 /* Should call_function allocate stack space for a struct return? */
760 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
762 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
766 mips_n32n64_use_struct_convention (int gcc_p, struct type *type)
768 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
772 mips_o32_use_struct_convention (int gcc_p, struct type *type)
774 return 1; /* Structures are returned by ref in extra arg0. */
777 /* Should call_function pass struct by reference?
778 For each architecture, structs are passed either by
779 value or by reference, depending on their size. */
782 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
784 enum type_code typecode = TYPE_CODE (check_typedef (type));
785 int len = TYPE_LENGTH (check_typedef (type));
787 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
788 return (len > MIPS_SAVED_REGSIZE);
794 mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type)
796 return 0; /* Assumption: N32/N64 never passes struct by ref. */
800 mips_o32_reg_struct_has_addr (int gcc_p, struct type *type)
802 return 0; /* Assumption: O32/O64 never passes struct by ref. */
805 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
808 pc_is_mips16 (bfd_vma memaddr)
810 struct minimal_symbol *sym;
812 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
813 if (is_mips16_addr (memaddr))
816 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
817 the high bit of the info field. Use this to decide if the function is
818 MIPS16 or normal MIPS. */
819 sym = lookup_minimal_symbol_by_pc (memaddr);
821 return msymbol_is_special (sym);
826 /* MIPS believes that the PC has a sign extended value. Perhaphs the
827 all registers should be sign extended for simplicity? */
830 mips_read_pc (ptid_t ptid)
832 return read_signed_register_pid (PC_REGNUM, ptid);
835 /* This returns the PC of the first inst after the prologue. If we can't
836 find the prologue, then return 0. */
839 after_prologue (CORE_ADDR pc,
840 mips_extra_func_info_t proc_desc)
842 struct symtab_and_line sal;
843 CORE_ADDR func_addr, func_end;
845 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
846 to read the stack pointer from the current machine state, because
847 the current machine state has nothing to do with the information
848 we need from the proc_desc; and the process may or may not exist
851 proc_desc = find_proc_desc (pc, NULL, 0);
855 /* If function is frameless, then we need to do it the hard way. I
856 strongly suspect that frameless always means prologueless... */
857 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
858 && PROC_FRAME_OFFSET (proc_desc) == 0)
862 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
863 return 0; /* Unknown */
865 sal = find_pc_line (func_addr, 0);
867 if (sal.end < func_end)
870 /* The line after the prologue is after the end of the function. In this
871 case, tell the caller to find the prologue the hard way. */
876 /* Decode a MIPS32 instruction that saves a register in the stack, and
877 set the appropriate bit in the general register mask or float register mask
878 to indicate which register is saved. This is a helper function
879 for mips_find_saved_regs. */
882 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
883 unsigned long *float_mask)
887 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
888 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
889 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
891 /* It might be possible to use the instruction to
892 find the offset, rather than the code below which
893 is based on things being in a certain order in the
894 frame, but figuring out what the instruction's offset
895 is relative to might be a little tricky. */
896 reg = (inst & 0x001f0000) >> 16;
897 *gen_mask |= (1 << reg);
899 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
900 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
901 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
904 reg = ((inst & 0x001f0000) >> 16);
905 *float_mask |= (1 << reg);
909 /* Decode a MIPS16 instruction that saves a register in the stack, and
910 set the appropriate bit in the general register or float register mask
911 to indicate which register is saved. This is a helper function
912 for mips_find_saved_regs. */
915 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
917 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
919 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
920 *gen_mask |= (1 << reg);
922 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
924 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
925 *gen_mask |= (1 << reg);
927 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
928 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
929 *gen_mask |= (1 << RA_REGNUM);
933 /* Fetch and return instruction from the specified location. If the PC
934 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
937 mips_fetch_instruction (CORE_ADDR addr)
939 char buf[MIPS_INSTLEN];
943 if (pc_is_mips16 (addr))
945 instlen = MIPS16_INSTLEN;
946 addr = unmake_mips16_addr (addr);
949 instlen = MIPS_INSTLEN;
950 status = read_memory_nobpt (addr, buf, instlen);
952 memory_error (status, addr);
953 return extract_unsigned_integer (buf, instlen);
957 /* These the fields of 32 bit mips instructions */
958 #define mips32_op(x) (x >> 26)
959 #define itype_op(x) (x >> 26)
960 #define itype_rs(x) ((x >> 21) & 0x1f)
961 #define itype_rt(x) ((x >> 16) & 0x1f)
962 #define itype_immediate(x) (x & 0xffff)
964 #define jtype_op(x) (x >> 26)
965 #define jtype_target(x) (x & 0x03ffffff)
967 #define rtype_op(x) (x >> 26)
968 #define rtype_rs(x) ((x >> 21) & 0x1f)
969 #define rtype_rt(x) ((x >> 16) & 0x1f)
970 #define rtype_rd(x) ((x >> 11) & 0x1f)
971 #define rtype_shamt(x) ((x >> 6) & 0x1f)
972 #define rtype_funct(x) (x & 0x3f)
975 mips32_relative_offset (unsigned long inst)
978 x = itype_immediate (inst);
979 if (x & 0x8000) /* sign bit set */
981 x |= 0xffff0000; /* sign extension */
987 /* Determine whate to set a single step breakpoint while considering
990 mips32_next_pc (CORE_ADDR pc)
994 inst = mips_fetch_instruction (pc);
995 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
997 if (itype_op (inst) >> 2 == 5)
998 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1000 op = (itype_op (inst) & 0x03);
1010 goto greater_branch;
1015 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
1016 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1018 int tf = itype_rt (inst) & 0x01;
1019 int cnum = itype_rt (inst) >> 2;
1020 int fcrcs = read_signed_register (FCRCS_REGNUM);
1021 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
1023 if (((cond >> cnum) & 0x01) == tf)
1024 pc += mips32_relative_offset (inst) + 4;
1029 pc += 4; /* Not a branch, next instruction is easy */
1032 { /* This gets way messy */
1034 /* Further subdivide into SPECIAL, REGIMM and other */
1035 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
1037 case 0: /* SPECIAL */
1038 op = rtype_funct (inst);
1043 /* Set PC to that address */
1044 pc = read_signed_register (rtype_rs (inst));
1050 break; /* end SPECIAL */
1051 case 1: /* REGIMM */
1053 op = itype_rt (inst); /* branch condition */
1058 case 16: /* BLTZAL */
1059 case 18: /* BLTZALL */
1061 if (read_signed_register (itype_rs (inst)) < 0)
1062 pc += mips32_relative_offset (inst) + 4;
1064 pc += 8; /* after the delay slot */
1068 case 17: /* BGEZAL */
1069 case 19: /* BGEZALL */
1070 greater_equal_branch:
1071 if (read_signed_register (itype_rs (inst)) >= 0)
1072 pc += mips32_relative_offset (inst) + 4;
1074 pc += 8; /* after the delay slot */
1076 /* All of the other instructions in the REGIMM category */
1081 break; /* end REGIMM */
1086 reg = jtype_target (inst) << 2;
1087 /* Upper four bits get never changed... */
1088 pc = reg + ((pc + 4) & 0xf0000000);
1091 /* FIXME case JALX : */
1094 reg = jtype_target (inst) << 2;
1095 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
1096 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1098 break; /* The new PC will be alternate mode */
1099 case 4: /* BEQ, BEQL */
1101 if (read_signed_register (itype_rs (inst)) ==
1102 read_signed_register (itype_rt (inst)))
1103 pc += mips32_relative_offset (inst) + 4;
1107 case 5: /* BNE, BNEL */
1109 if (read_signed_register (itype_rs (inst)) !=
1110 read_signed_register (itype_rt (inst)))
1111 pc += mips32_relative_offset (inst) + 4;
1115 case 6: /* BLEZ, BLEZL */
1117 if (read_signed_register (itype_rs (inst) <= 0))
1118 pc += mips32_relative_offset (inst) + 4;
1124 greater_branch: /* BGTZ, BGTZL */
1125 if (read_signed_register (itype_rs (inst) > 0))
1126 pc += mips32_relative_offset (inst) + 4;
1133 } /* mips32_next_pc */
1135 /* Decoding the next place to set a breakpoint is irregular for the
1136 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1137 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1138 We dont want to set a single step instruction on the extend instruction
1142 /* Lots of mips16 instruction formats */
1143 /* Predicting jumps requires itype,ritype,i8type
1144 and their extensions extItype,extritype,extI8type
1146 enum mips16_inst_fmts
1148 itype, /* 0 immediate 5,10 */
1149 ritype, /* 1 5,3,8 */
1150 rrtype, /* 2 5,3,3,5 */
1151 rritype, /* 3 5,3,3,5 */
1152 rrrtype, /* 4 5,3,3,3,2 */
1153 rriatype, /* 5 5,3,3,1,4 */
1154 shifttype, /* 6 5,3,3,3,2 */
1155 i8type, /* 7 5,3,8 */
1156 i8movtype, /* 8 5,3,3,5 */
1157 i8mov32rtype, /* 9 5,3,5,3 */
1158 i64type, /* 10 5,3,8 */
1159 ri64type, /* 11 5,3,3,5 */
1160 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1161 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1162 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1163 extRRItype, /* 15 5,5,5,5,3,3,5 */
1164 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1165 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1166 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1167 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1168 extRi64type, /* 20 5,6,5,5,3,3,5 */
1169 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1171 /* I am heaping all the fields of the formats into one structure and
1172 then, only the fields which are involved in instruction extension */
1176 unsigned int regx; /* Function in i8 type */
1181 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1182 for the bits which make up the immediatate extension. */
1185 extended_offset (unsigned int extension)
1188 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1190 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1192 value |= extension & 0x01f; /* extract 4:0 */
1196 /* Only call this function if you know that this is an extendable
1197 instruction, It wont malfunction, but why make excess remote memory references?
1198 If the immediate operands get sign extended or somthing, do it after
1199 the extension is performed.
1201 /* FIXME: Every one of these cases needs to worry about sign extension
1202 when the offset is to be used in relative addressing */
1206 fetch_mips_16 (CORE_ADDR pc)
1209 pc &= 0xfffffffe; /* clear the low order bit */
1210 target_read_memory (pc, buf, 2);
1211 return extract_unsigned_integer (buf, 2);
1215 unpack_mips16 (CORE_ADDR pc,
1216 unsigned int extension,
1218 enum mips16_inst_fmts insn_format,
1219 struct upk_mips16 *upk)
1224 switch (insn_format)
1231 value = extended_offset (extension);
1232 value = value << 11; /* rom for the original value */
1233 value |= inst & 0x7ff; /* eleven bits from instruction */
1237 value = inst & 0x7ff;
1238 /* FIXME : Consider sign extension */
1247 { /* A register identifier and an offset */
1248 /* Most of the fields are the same as I type but the
1249 immediate value is of a different length */
1253 value = extended_offset (extension);
1254 value = value << 8; /* from the original instruction */
1255 value |= inst & 0xff; /* eleven bits from instruction */
1256 regx = (extension >> 8) & 0x07; /* or i8 funct */
1257 if (value & 0x4000) /* test the sign bit , bit 26 */
1259 value &= ~0x3fff; /* remove the sign bit */
1265 value = inst & 0xff; /* 8 bits */
1266 regx = (inst >> 8) & 0x07; /* or i8 funct */
1267 /* FIXME: Do sign extension , this format needs it */
1268 if (value & 0x80) /* THIS CONFUSES ME */
1270 value &= 0xef; /* remove the sign bit */
1280 unsigned long value;
1281 unsigned int nexthalf;
1282 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1283 value = value << 16;
1284 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1292 internal_error (__FILE__, __LINE__,
1295 upk->offset = offset;
1302 add_offset_16 (CORE_ADDR pc, int offset)
1304 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1308 extended_mips16_next_pc (CORE_ADDR pc,
1309 unsigned int extension,
1312 int op = (insn >> 11);
1315 case 2: /* Branch */
1318 struct upk_mips16 upk;
1319 unpack_mips16 (pc, extension, insn, itype, &upk);
1320 offset = upk.offset;
1326 pc += (offset << 1) + 2;
1329 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1331 struct upk_mips16 upk;
1332 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1333 pc = add_offset_16 (pc, upk.offset);
1334 if ((insn >> 10) & 0x01) /* Exchange mode */
1335 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1342 struct upk_mips16 upk;
1344 unpack_mips16 (pc, extension, insn, ritype, &upk);
1345 reg = read_signed_register (upk.regx);
1347 pc += (upk.offset << 1) + 2;
1354 struct upk_mips16 upk;
1356 unpack_mips16 (pc, extension, insn, ritype, &upk);
1357 reg = read_signed_register (upk.regx);
1359 pc += (upk.offset << 1) + 2;
1364 case 12: /* I8 Formats btez btnez */
1366 struct upk_mips16 upk;
1368 unpack_mips16 (pc, extension, insn, i8type, &upk);
1369 /* upk.regx contains the opcode */
1370 reg = read_signed_register (24); /* Test register is 24 */
1371 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1372 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1373 /* pc = add_offset_16(pc,upk.offset) ; */
1374 pc += (upk.offset << 1) + 2;
1379 case 29: /* RR Formats JR, JALR, JALR-RA */
1381 struct upk_mips16 upk;
1382 /* upk.fmt = rrtype; */
1387 upk.regx = (insn >> 8) & 0x07;
1388 upk.regy = (insn >> 5) & 0x07;
1396 break; /* Function return instruction */
1402 break; /* BOGUS Guess */
1404 pc = read_signed_register (reg);
1411 /* This is an instruction extension. Fetch the real instruction
1412 (which follows the extension) and decode things based on
1416 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1429 mips16_next_pc (CORE_ADDR pc)
1431 unsigned int insn = fetch_mips_16 (pc);
1432 return extended_mips16_next_pc (pc, 0, insn);
1435 /* The mips_next_pc function supports single_step when the remote
1436 target monitor or stub is not developed enough to do a single_step.
1437 It works by decoding the current instruction and predicting where a
1438 branch will go. This isnt hard because all the data is available.
1439 The MIPS32 and MIPS16 variants are quite different */
1441 mips_next_pc (CORE_ADDR pc)
1444 return mips16_next_pc (pc);
1446 return mips32_next_pc (pc);
1449 /* Set up the 'saved_regs' array. This is a data structure containing
1450 the addresses on the stack where each register has been saved, for
1451 each stack frame. Registers that have not been saved will have
1452 zero here. The stack pointer register is special: rather than the
1453 address where the stack register has been saved,
1454 saved_regs[SP_REGNUM] will have the actual value of the previous
1455 frame's stack register. */
1458 mips_find_saved_regs (struct frame_info *fci)
1461 /* r0 bit means kernel trap */
1463 /* What registers have been saved? Bitmasks. */
1464 unsigned long gen_mask, float_mask;
1465 mips_extra_func_info_t proc_desc;
1467 CORE_ADDR *saved_regs;
1469 if (get_frame_saved_regs (fci) != NULL)
1471 saved_regs = frame_saved_regs_zalloc (fci);
1473 /* If it is the frame for sigtramp, the saved registers are located
1474 in a sigcontext structure somewhere on the stack. If the stack
1475 layout for sigtramp changes we might have to change these
1476 constants and the companion fixup_sigtramp in mdebugread.c */
1477 #ifndef SIGFRAME_BASE
1478 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1479 above the sigtramp frame. */
1480 #define SIGFRAME_BASE MIPS_REGSIZE
1481 /* FIXME! Are these correct?? */
1482 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1483 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1484 #define SIGFRAME_FPREGSAVE_OFF \
1485 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1487 #ifndef SIGFRAME_REG_SIZE
1488 /* FIXME! Is this correct?? */
1489 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1491 if ((get_frame_type (fci) == SIGTRAMP_FRAME))
1493 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1495 CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF
1496 + ireg * SIGFRAME_REG_SIZE);
1497 set_reg_offset (saved_regs, ireg, reg_position);
1499 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1501 CORE_ADDR reg_position = (get_frame_base (fci)
1502 + SIGFRAME_FPREGSAVE_OFF
1503 + ireg * SIGFRAME_REG_SIZE);
1504 set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position);
1507 set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF);
1508 /* SP_REGNUM, contains the value and not the address. */
1509 set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci));
1513 proc_desc = get_frame_extra_info (fci)->proc_desc;
1514 if (proc_desc == NULL)
1515 /* I'm not sure how/whether this can happen. Normally when we
1516 can't find a proc_desc, we "synthesize" one using
1517 heuristic_proc_desc and set the saved_regs right away. */
1520 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1521 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1522 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1524 if (/* In any frame other than the innermost or a frame interrupted
1525 by a signal, we assume that all registers have been saved.
1526 This assumes that all register saves in a function happen
1527 before the first function call. */
1528 (get_next_frame (fci) == NULL
1529 || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME))
1531 /* In a dummy frame we know exactly where things are saved. */
1532 && !PROC_DESC_IS_DUMMY (proc_desc)
1534 /* Don't bother unless we are inside a function prologue.
1535 Outside the prologue, we know where everything is. */
1537 && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc))
1539 /* Not sure exactly what kernel_trap means, but if it means the
1540 kernel saves the registers without a prologue doing it, we
1541 better not examine the prologue to see whether registers
1542 have been saved yet. */
1545 /* We need to figure out whether the registers that the
1546 proc_desc claims are saved have been saved yet. */
1550 /* Bitmasks; set if we have found a save for the register. */
1551 unsigned long gen_save_found = 0;
1552 unsigned long float_save_found = 0;
1555 /* If the address is odd, assume this is MIPS16 code. */
1556 addr = PROC_LOW_ADDR (proc_desc);
1557 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1559 /* Scan through this function's instructions preceding the
1560 current PC, and look for those that save registers. */
1561 while (addr < get_frame_pc (fci))
1563 inst = mips_fetch_instruction (addr);
1564 if (pc_is_mips16 (addr))
1565 mips16_decode_reg_save (inst, &gen_save_found);
1567 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1570 gen_mask = gen_save_found;
1571 float_mask = float_save_found;
1574 /* Fill in the offsets for the registers which gen_mask says were
1577 CORE_ADDR reg_position = (get_frame_base (fci)
1578 + PROC_REG_OFFSET (proc_desc));
1579 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1580 if (gen_mask & 0x80000000)
1582 set_reg_offset (saved_regs, ireg, reg_position);
1583 reg_position -= MIPS_SAVED_REGSIZE;
1587 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1588 order of that normally used by gcc. Therefore, we have to fetch
1589 the first instruction of the function, and if it's an entry
1590 instruction that saves $s0 or $s1, correct their saved addresses. */
1591 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1593 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1594 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
1598 int sreg_count = (inst >> 6) & 3;
1600 /* Check if the ra register was pushed on the stack. */
1601 CORE_ADDR reg_position = (get_frame_base (fci)
1602 + PROC_REG_OFFSET (proc_desc));
1604 reg_position -= MIPS_SAVED_REGSIZE;
1606 /* Check if the s0 and s1 registers were pushed on the
1608 for (reg = 16; reg < sreg_count + 16; reg++)
1610 set_reg_offset (saved_regs, reg, reg_position);
1611 reg_position -= MIPS_SAVED_REGSIZE;
1616 /* Fill in the offsets for the registers which float_mask says were
1619 CORE_ADDR reg_position = (get_frame_base (fci)
1620 + PROC_FREG_OFFSET (proc_desc));
1622 /* Apparently, the freg_offset gives the offset to the first 64
1625 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1626 designates the first saved 64 bit register.
1628 When the ABI specifies 32 bit saved registers, the ``64 bit
1629 saved DOUBLE'' consists of two adjacent 32 bit registers, Hence
1630 FREG_OFFSET, designates the address of the lower register of
1631 the register pair. Adjust the offset so that it designates the
1632 upper register of the pair -- i.e., the address of the first
1633 saved 32 bit register. */
1635 if (MIPS_SAVED_REGSIZE == 4)
1636 reg_position += MIPS_SAVED_REGSIZE;
1638 /* Fill in the offsets for the float registers which float_mask
1640 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1641 if (float_mask & 0x80000000)
1643 set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position);
1644 reg_position -= MIPS_SAVED_REGSIZE;
1647 set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]);
1650 /* SP_REGNUM, contains the value and not the address. */
1651 set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci));
1655 read_next_frame_reg (struct frame_info *fi, int regno)
1660 enum lval_type lval;
1661 char raw_buffer[MAX_REGISTER_SIZE];
1665 regcache_cooked_read (current_regcache, regno, raw_buffer);
1669 frame_register_unwind (fi, regno, &optimized, &lval, &addr, &realnum,
1671 /* FIXME: cagney/2002-09-13: This is just soooo bad. The MIPS
1672 should have a pseudo register range that correspons to the ABI's,
1673 rather than the ISA's, view of registers. These registers would
1674 then implicitly describe their size and hence could be used
1675 without the below munging. */
1676 if (lval == lval_memory)
1680 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
1682 return read_memory_integer (addr, MIPS_SAVED_REGSIZE);
1687 return extract_signed_integer (raw_buffer, REGISTER_VIRTUAL_SIZE (regno));
1690 /* mips_addr_bits_remove - remove useless address bits */
1693 mips_addr_bits_remove (CORE_ADDR addr)
1695 if (GDB_TARGET_IS_MIPS64)
1697 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1699 /* This hack is a work-around for existing boards using
1700 PMON, the simulator, and any other 64-bit targets that
1701 doesn't have true 64-bit addressing. On these targets,
1702 the upper 32 bits of addresses are ignored by the
1703 hardware. Thus, the PC or SP are likely to have been
1704 sign extended to all 1s by instruction sequences that
1705 load 32-bit addresses. For example, a typical piece of
1706 code that loads an address is this:
1707 lui $r2, <upper 16 bits>
1708 ori $r2, <lower 16 bits>
1709 But the lui sign-extends the value such that the upper 32
1710 bits may be all 1s. The workaround is simply to mask off
1711 these bits. In the future, gcc may be changed to support
1712 true 64-bit addressing, and this masking will have to be
1714 addr &= (CORE_ADDR) 0xffffffff;
1717 else if (mips_mask_address_p ())
1719 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1720 masking off bits, instead, the actual target should be asking
1721 for the address to be converted to a valid pointer. */
1722 /* Even when GDB is configured for some 32-bit targets
1723 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1724 so CORE_ADDR is 64 bits. So we still have to mask off
1725 useless bits from addresses. */
1726 addr &= (CORE_ADDR) 0xffffffff;
1731 /* mips_software_single_step() is called just before we want to resume
1732 the inferior, if we want to single-step it but there is no hardware
1733 or kernel single-step support (MIPS on GNU/Linux for example). We find
1734 the target of the coming instruction and breakpoint it.
1736 single_step is also called just after the inferior stops. If we had
1737 set up a simulated single-step, we undo our damage. */
1740 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1742 static CORE_ADDR next_pc;
1743 typedef char binsn_quantum[BREAKPOINT_MAX];
1744 static binsn_quantum break_mem;
1747 if (insert_breakpoints_p)
1749 pc = read_register (PC_REGNUM);
1750 next_pc = mips_next_pc (pc);
1752 target_insert_breakpoint (next_pc, break_mem);
1755 target_remove_breakpoint (next_pc, break_mem);
1759 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1764 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev))
1765 : get_next_frame (prev)
1766 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev))
1768 tmp = SKIP_TRAMPOLINE_CODE (pc);
1769 return tmp ? tmp : pc;
1774 mips_frame_saved_pc (struct frame_info *frame)
1777 mips_extra_func_info_t proc_desc = get_frame_extra_info (frame)->proc_desc;
1778 /* We have to get the saved pc from the sigcontext
1779 if it is a signal handler frame. */
1780 int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME) ? PC_REGNUM
1781 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1783 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
1786 frame_unwind_signed_register (frame, PC_REGNUM, &tmp);
1789 else if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1790 saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1792 saved_pc = read_next_frame_reg (frame, pcreg);
1794 return ADDR_BITS_REMOVE (saved_pc);
1797 static struct mips_extra_func_info temp_proc_desc;
1799 /* This hack will go away once the get_prev_frame() code has been
1800 modified to set the frame's type first. That is BEFORE init extra
1801 frame info et.al. is called. This is because it will become
1802 possible to skip the init extra info call for sigtramp and dummy
1804 static CORE_ADDR *temp_saved_regs;
1806 /* Set a register's saved stack address in temp_saved_regs. If an
1807 address has already been set for this register, do nothing; this
1808 way we will only recognize the first save of a given register in a
1809 function prologue. */
1812 set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset)
1814 if (saved_regs[regno] == 0)
1815 saved_regs[regno] = offset;
1819 /* Test whether the PC points to the return instruction at the
1820 end of a function. */
1823 mips_about_to_return (CORE_ADDR pc)
1825 if (pc_is_mips16 (pc))
1826 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1827 generates a "jr $ra"; other times it generates code to load
1828 the return address from the stack to an accessible register (such
1829 as $a3), then a "jr" using that register. This second case
1830 is almost impossible to distinguish from an indirect jump
1831 used for switch statements, so we don't even try. */
1832 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1834 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1838 /* This fencepost looks highly suspicious to me. Removing it also
1839 seems suspicious as it could affect remote debugging across serial
1843 heuristic_proc_start (CORE_ADDR pc)
1850 pc = ADDR_BITS_REMOVE (pc);
1852 fence = start_pc - heuristic_fence_post;
1856 if (heuristic_fence_post == UINT_MAX
1857 || fence < VM_MIN_ADDRESS)
1858 fence = VM_MIN_ADDRESS;
1860 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1862 /* search back for previous return */
1863 for (start_pc -= instlen;; start_pc -= instlen)
1864 if (start_pc < fence)
1866 /* It's not clear to me why we reach this point when
1867 stop_soon, but with this test, at least we
1868 don't print out warnings for every child forked (eg, on
1869 decstation). 22apr93 rich@cygnus.com. */
1870 if (stop_soon == NO_STOP_QUIETLY)
1872 static int blurb_printed = 0;
1874 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1879 /* This actually happens frequently in embedded
1880 development, when you first connect to a board
1881 and your stack pointer and pc are nowhere in
1882 particular. This message needs to give people
1883 in that situation enough information to
1884 determine that it's no big deal. */
1885 printf_filtered ("\n\
1886 GDB is unable to find the start of the function at 0x%s\n\
1887 and thus can't determine the size of that function's stack frame.\n\
1888 This means that GDB may be unable to access that stack frame, or\n\
1889 the frames below it.\n\
1890 This problem is most likely caused by an invalid program counter or\n\
1892 However, if you think GDB should simply search farther back\n\
1893 from 0x%s for code which looks like the beginning of a\n\
1894 function, you can increase the range of the search using the `set\n\
1895 heuristic-fence-post' command.\n",
1896 paddr_nz (pc), paddr_nz (pc));
1903 else if (pc_is_mips16 (start_pc))
1905 unsigned short inst;
1907 /* On MIPS16, any one of the following is likely to be the
1908 start of a function:
1912 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1913 inst = mips_fetch_instruction (start_pc);
1914 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1915 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1916 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1917 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1919 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1920 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1925 else if (mips_about_to_return (start_pc))
1927 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1934 /* Fetch the immediate value from a MIPS16 instruction.
1935 If the previous instruction was an EXTEND, use it to extend
1936 the upper bits of the immediate value. This is a helper function
1937 for mips16_heuristic_proc_desc. */
1940 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1941 unsigned short inst, /* current instruction */
1942 int nbits, /* number of bits in imm field */
1943 int scale, /* scale factor to be applied to imm */
1944 int is_signed) /* is the imm field signed? */
1948 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1950 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1951 if (offset & 0x8000) /* check for negative extend */
1952 offset = 0 - (0x10000 - (offset & 0xffff));
1953 return offset | (inst & 0x1f);
1957 int max_imm = 1 << nbits;
1958 int mask = max_imm - 1;
1959 int sign_bit = max_imm >> 1;
1961 offset = inst & mask;
1962 if (is_signed && (offset & sign_bit))
1963 offset = 0 - (max_imm - offset);
1964 return offset * scale;
1969 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1970 stream from start_pc to limit_pc. */
1973 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1974 struct frame_info *next_frame, CORE_ADDR sp)
1977 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1978 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1979 unsigned inst = 0; /* current instruction */
1980 unsigned entry_inst = 0; /* the entry instruction */
1983 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1984 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1986 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1988 /* Save the previous instruction. If it's an EXTEND, we'll extract
1989 the immediate offset extension from it in mips16_get_imm. */
1992 /* Fetch and decode the instruction. */
1993 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1994 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1995 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1997 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1998 if (offset < 0) /* negative stack adjustment? */
1999 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
2001 /* Exit loop if a positive stack adjustment is found, which
2002 usually means that the stack cleanup code in the function
2003 epilogue is reached. */
2006 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2008 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2009 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
2010 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2011 set_reg_offset (temp_saved_regs, reg, sp + offset);
2013 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2015 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2016 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2017 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2018 set_reg_offset (temp_saved_regs, reg, sp + offset);
2020 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2022 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2023 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2024 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2026 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2028 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2029 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2030 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2032 else if (inst == 0x673d) /* move $s1, $sp */
2035 PROC_FRAME_REG (&temp_proc_desc) = 17;
2037 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2039 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2040 frame_addr = sp + offset;
2041 PROC_FRAME_REG (&temp_proc_desc) = 17;
2042 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
2044 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2046 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2047 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2048 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2049 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2051 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2053 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2054 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2055 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2056 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2058 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2059 entry_inst = inst; /* save for later processing */
2060 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
2061 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
2064 /* The entry instruction is typically the first instruction in a function,
2065 and it stores registers at offsets relative to the value of the old SP
2066 (before the prologue). But the value of the sp parameter to this
2067 function is the new SP (after the prologue has been executed). So we
2068 can't calculate those offsets until we've seen the entire prologue,
2069 and can calculate what the old SP must have been. */
2070 if (entry_inst != 0)
2072 int areg_count = (entry_inst >> 8) & 7;
2073 int sreg_count = (entry_inst >> 6) & 3;
2075 /* The entry instruction always subtracts 32 from the SP. */
2076 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
2078 /* Now we can calculate what the SP must have been at the
2079 start of the function prologue. */
2080 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
2082 /* Check if a0-a3 were saved in the caller's argument save area. */
2083 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2085 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2086 set_reg_offset (temp_saved_regs, reg, sp + offset);
2087 offset += MIPS_SAVED_REGSIZE;
2090 /* Check if the ra register was pushed on the stack. */
2092 if (entry_inst & 0x20)
2094 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
2095 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2096 offset -= MIPS_SAVED_REGSIZE;
2099 /* Check if the s0 and s1 registers were pushed on the stack. */
2100 for (reg = 16; reg < sreg_count + 16; reg++)
2102 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2103 set_reg_offset (temp_saved_regs, reg, sp + offset);
2104 offset -= MIPS_SAVED_REGSIZE;
2110 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2111 struct frame_info *next_frame, CORE_ADDR sp)
2114 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
2116 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2117 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2118 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
2119 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2120 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2122 unsigned long inst, high_word, low_word;
2125 /* Fetch the instruction. */
2126 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2128 /* Save some code by pre-extracting some useful fields. */
2129 high_word = (inst >> 16) & 0xffff;
2130 low_word = inst & 0xffff;
2131 reg = high_word & 0x1f;
2133 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2134 || high_word == 0x23bd /* addi $sp,$sp,-i */
2135 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2137 if (low_word & 0x8000) /* negative stack adjustment? */
2138 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
2140 /* Exit loop if a positive stack adjustment is found, which
2141 usually means that the stack cleanup code in the function
2142 epilogue is reached. */
2145 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2147 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2148 set_reg_offset (temp_saved_regs, reg, sp + low_word);
2150 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2152 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2153 but the register size used is only 32 bits. Make the address
2154 for the saved register point to the lower 32 bits. */
2155 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2156 set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - MIPS_REGSIZE);
2158 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2160 /* Old gcc frame, r30 is virtual frame pointer. */
2161 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2162 frame_addr = sp + low_word;
2163 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2165 unsigned alloca_adjust;
2166 PROC_FRAME_REG (&temp_proc_desc) = 30;
2167 frame_addr = read_next_frame_reg (next_frame, 30);
2168 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2169 if (alloca_adjust > 0)
2171 /* FP > SP + frame_size. This may be because
2172 * of an alloca or somethings similar.
2173 * Fix sp to "pre-alloca" value, and try again.
2175 sp += alloca_adjust;
2180 /* move $30,$sp. With different versions of gas this will be either
2181 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2182 Accept any one of these. */
2183 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2185 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2186 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2188 unsigned alloca_adjust;
2189 PROC_FRAME_REG (&temp_proc_desc) = 30;
2190 frame_addr = read_next_frame_reg (next_frame, 30);
2191 alloca_adjust = (unsigned) (frame_addr - sp);
2192 if (alloca_adjust > 0)
2194 /* FP > SP + frame_size. This may be because
2195 * of an alloca or somethings similar.
2196 * Fix sp to "pre-alloca" value, and try again.
2198 sp += alloca_adjust;
2203 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2205 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2206 set_reg_offset (temp_saved_regs, reg, frame_addr + low_word);
2211 static mips_extra_func_info_t
2212 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2213 struct frame_info *next_frame, int cur_frame)
2218 sp = read_next_frame_reg (next_frame, SP_REGNUM);
2224 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2225 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2226 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2227 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2228 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2229 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2231 if (start_pc + 200 < limit_pc)
2232 limit_pc = start_pc + 200;
2233 if (pc_is_mips16 (start_pc))
2234 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2236 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2237 return &temp_proc_desc;
2240 struct mips_objfile_private
2246 /* Global used to communicate between non_heuristic_proc_desc and
2247 compare_pdr_entries within qsort (). */
2248 static bfd *the_bfd;
2251 compare_pdr_entries (const void *a, const void *b)
2253 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2254 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2258 else if (lhs == rhs)
2264 static mips_extra_func_info_t
2265 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2267 CORE_ADDR startaddr;
2268 mips_extra_func_info_t proc_desc;
2269 struct block *b = block_for_pc (pc);
2271 struct obj_section *sec;
2272 struct mips_objfile_private *priv;
2274 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
2277 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2279 *addrptr = startaddr;
2283 sec = find_pc_section (pc);
2286 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2288 /* Search the ".pdr" section generated by GAS. This includes most of
2289 the information normally found in ECOFF PDRs. */
2291 the_bfd = sec->objfile->obfd;
2293 && (the_bfd->format == bfd_object
2294 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2295 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2297 /* Right now GAS only outputs the address as a four-byte sequence.
2298 This means that we should not bother with this method on 64-bit
2299 targets (until that is fixed). */
2301 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2302 sizeof (struct mips_objfile_private));
2304 sec->objfile->obj_private = priv;
2306 else if (priv == NULL)
2310 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2311 sizeof (struct mips_objfile_private));
2313 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2316 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2317 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2319 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2320 priv->contents, 0, priv->size);
2322 /* In general, the .pdr section is sorted. However, in the
2323 presence of multiple code sections (and other corner cases)
2324 it can become unsorted. Sort it so that we can use a faster
2326 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2331 sec->objfile->obj_private = priv;
2335 if (priv->size != 0)
2341 high = priv->size / 32;
2347 mid = (low + high) / 2;
2349 ptr = priv->contents + mid * 32;
2350 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2351 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2352 SECT_OFF_TEXT (sec->objfile));
2353 if (pdr_pc == startaddr)
2355 if (pdr_pc > startaddr)
2360 while (low != high);
2364 struct symbol *sym = find_pc_function (pc);
2366 /* Fill in what we need of the proc_desc. */
2367 proc_desc = (mips_extra_func_info_t)
2368 obstack_alloc (&sec->objfile->psymbol_obstack,
2369 sizeof (struct mips_extra_func_info));
2370 PROC_LOW_ADDR (proc_desc) = startaddr;
2372 /* Only used for dummy frames. */
2373 PROC_HIGH_ADDR (proc_desc) = 0;
2375 PROC_FRAME_OFFSET (proc_desc)
2376 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2377 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2379 PROC_FRAME_ADJUST (proc_desc) = 0;
2380 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2382 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2384 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2386 PROC_FREG_OFFSET (proc_desc)
2387 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2388 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2390 proc_desc->pdr.isym = (long) sym;
2400 if (startaddr > BLOCK_START (b))
2402 /* This is the "pathological" case referred to in a comment in
2403 print_frame_info. It might be better to move this check into
2408 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL);
2410 /* If we never found a PDR for this function in symbol reading, then
2411 examine prologues to find the information. */
2414 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2415 if (PROC_FRAME_REG (proc_desc) == -1)
2425 static mips_extra_func_info_t
2426 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2428 mips_extra_func_info_t proc_desc;
2429 CORE_ADDR startaddr = 0;
2431 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2435 /* IF this is the topmost frame AND
2436 * (this proc does not have debugging information OR
2437 * the PC is in the procedure prologue)
2438 * THEN create a "heuristic" proc_desc (by analyzing
2439 * the actual code) to replace the "official" proc_desc.
2441 if (next_frame == NULL)
2443 struct symtab_and_line val;
2444 struct symbol *proc_symbol =
2445 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2449 val = find_pc_line (BLOCK_START
2450 (SYMBOL_BLOCK_VALUE (proc_symbol)),
2452 val.pc = val.end ? val.end : pc;
2454 if (!proc_symbol || pc < val.pc)
2456 mips_extra_func_info_t found_heuristic =
2457 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2458 pc, next_frame, cur_frame);
2459 if (found_heuristic)
2460 proc_desc = found_heuristic;
2466 /* Is linked_proc_desc_table really necessary? It only seems to be used
2467 by procedure call dummys. However, the procedures being called ought
2468 to have their own proc_descs, and even if they don't,
2469 heuristic_proc_desc knows how to create them! */
2471 register struct linked_proc_info *link;
2473 for (link = linked_proc_desc_table; link; link = link->next)
2474 if (PROC_LOW_ADDR (&link->info) <= pc
2475 && PROC_HIGH_ADDR (&link->info) > pc)
2479 startaddr = heuristic_proc_start (pc);
2482 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2488 get_frame_pointer (struct frame_info *frame,
2489 mips_extra_func_info_t proc_desc)
2491 return (read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc))
2492 + PROC_FRAME_OFFSET (proc_desc)
2493 - PROC_FRAME_ADJUST (proc_desc));
2496 static mips_extra_func_info_t cached_proc_desc;
2499 mips_frame_chain (struct frame_info *frame)
2501 mips_extra_func_info_t proc_desc;
2503 CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame);
2505 if (saved_pc == 0 || inside_entry_file (saved_pc))
2508 /* Check if the PC is inside a call stub. If it is, fetch the
2509 PC of the caller of that stub. */
2510 if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0)
2513 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0))
2515 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2516 is well, frame->frame the bottom of the current frame will
2517 contain that value. */
2518 return get_frame_base (frame);
2521 /* Look up the procedure descriptor for this PC. */
2522 proc_desc = find_proc_desc (saved_pc, frame, 1);
2526 cached_proc_desc = proc_desc;
2528 /* If no frame pointer and frame size is zero, we must be at end
2529 of stack (or otherwise hosed). If we don't check frame size,
2530 we loop forever if we see a zero size frame. */
2531 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2532 && PROC_FRAME_OFFSET (proc_desc) == 0
2533 /* The previous frame from a sigtramp frame might be frameless
2534 and have frame size zero. */
2535 && !(get_frame_type (frame) == SIGTRAMP_FRAME)
2536 /* For a generic dummy frame, let get_frame_pointer() unwind a
2537 register value saved as part of the dummy frame call. */
2538 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)))
2541 return get_frame_pointer (frame, proc_desc);
2545 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2548 mips_extra_func_info_t proc_desc;
2550 if (get_frame_type (fci) == DUMMY_FRAME)
2553 /* Use proc_desc calculated in frame_chain. When there is no
2554 next frame, i.e, get_next_frame (fci) == NULL, we call
2555 find_proc_desc () to calculate it, passing an explicit
2556 NULL as the frame parameter. */
2558 get_next_frame (fci)
2560 : find_proc_desc (get_frame_pc (fci),
2561 NULL /* i.e, get_next_frame (fci) */,
2564 frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info));
2566 deprecated_set_frame_saved_regs_hack (fci, NULL);
2567 get_frame_extra_info (fci)->proc_desc =
2568 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2571 /* Fixup frame-pointer - only needed for top frame */
2572 /* This may not be quite right, if proc has a real frame register.
2573 Get the value of the frame relative sp, procedure might have been
2574 interrupted by a signal at it's very start. */
2575 if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc)
2576 && !PROC_DESC_IS_DUMMY (proc_desc))
2577 deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), SP_REGNUM));
2578 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0))
2579 /* Do not ``fix'' fci->frame. It will have the value of the
2580 generic dummy frame's top-of-stack (since the draft
2581 fci->frame is obtained by returning the unwound stack
2582 pointer) and that is what we want. That way the fci->frame
2583 value will match the top-of-stack value that was saved as
2584 part of the dummy frames data. */
2587 deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc));
2589 if (proc_desc == &temp_proc_desc)
2593 /* Do not set the saved registers for a sigtramp frame,
2594 mips_find_saved_registers will do that for us. We can't
2595 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2597 /* FIXME: cagney/2002-11-18: This problem will go away once
2598 frame.c:get_prev_frame() is modified to set the frame's
2599 type before calling functions like this. */
2600 find_pc_partial_function (get_frame_pc (fci), &name,
2601 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2602 if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name))
2604 frame_saved_regs_zalloc (fci);
2605 /* Set value of previous frame's stack pointer.
2606 Remember that saved_regs[SP_REGNUM] is special in
2607 that it contains the value of the stack pointer
2608 register. The other saved_regs values are addresses
2609 (in the inferior) at which a given register's value
2611 set_reg_offset (temp_saved_regs, SP_REGNUM,
2612 get_frame_base (fci));
2613 set_reg_offset (temp_saved_regs, PC_REGNUM,
2614 temp_saved_regs[RA_REGNUM]);
2615 memcpy (get_frame_saved_regs (fci), temp_saved_regs,
2616 SIZEOF_FRAME_SAVED_REGS);
2620 /* hack: if argument regs are saved, guess these contain args */
2621 /* assume we can't tell how many args for now */
2622 get_frame_extra_info (fci)->num_args = -1;
2623 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2625 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2627 get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1;
2634 /* MIPS stack frames are almost impenetrable. When execution stops,
2635 we basically have to look at symbol information for the function
2636 that we stopped in, which tells us *which* register (if any) is
2637 the base of the frame pointer, and what offset from that register
2638 the frame itself is at.
2640 This presents a problem when trying to examine a stack in memory
2641 (that isn't executing at the moment), using the "frame" command. We
2642 don't have a PC, nor do we have any registers except SP.
2644 This routine takes two arguments, SP and PC, and tries to make the
2645 cached frames look as if these two arguments defined a frame on the
2646 cache. This allows the rest of info frame to extract the important
2647 arguments without difficulty. */
2650 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2653 error ("MIPS frame specifications require two arguments: sp and pc");
2655 return create_new_frame (argv[0], argv[1]);
2658 /* According to the current ABI, should the type be passed in a
2659 floating-point register (assuming that there is space)? When there
2660 is no FPU, FP are not even considered as possibile candidates for
2661 FP registers and, consequently this returns false - forces FP
2662 arguments into integer registers. */
2665 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2667 return ((typecode == TYPE_CODE_FLT
2669 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2670 && TYPE_NFIELDS (arg_type) == 1
2671 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2672 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2675 /* On o32, argument passing in GPRs depends on the alignment of the type being
2676 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2679 mips_type_needs_double_align (struct type *type)
2681 enum type_code typecode = TYPE_CODE (type);
2683 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2685 else if (typecode == TYPE_CODE_STRUCT)
2687 if (TYPE_NFIELDS (type) < 1)
2689 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2691 else if (typecode == TYPE_CODE_UNION)
2695 n = TYPE_NFIELDS (type);
2696 for (i = 0; i < n; i++)
2697 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2704 /* Macros to round N up or down to the next A boundary;
2705 A must be a power of two. */
2707 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2708 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2710 /* Adjust the address downward (direction of stack growth) so that it
2711 is correctly aligned for a new stack frame. */
2713 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2715 return ROUND_DOWN (addr, 16);
2719 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2720 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2721 struct value **args, CORE_ADDR sp, int struct_return,
2722 CORE_ADDR struct_addr)
2728 int stack_offset = 0;
2730 /* For shared libraries, "t9" needs to point at the function
2732 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
2734 /* Set the return address register to point to the entry point of
2735 the program, where a breakpoint lies in wait. */
2736 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
2738 /* First ensure that the stack and structure return address (if any)
2739 are properly aligned. The stack has to be at least 64-bit
2740 aligned even on 32-bit machines, because doubles must be 64-bit
2741 aligned. For n32 and n64, stack frames need to be 128-bit
2742 aligned, so we round to this widest known alignment. */
2744 sp = ROUND_DOWN (sp, 16);
2745 struct_addr = ROUND_DOWN (struct_addr, 16);
2747 /* Now make space on the stack for the args. We allocate more
2748 than necessary for EABI, because the first few arguments are
2749 passed in registers, but that's OK. */
2750 for (argnum = 0; argnum < nargs; argnum++)
2751 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2752 MIPS_STACK_ARGSIZE);
2753 sp -= ROUND_UP (len, 16);
2756 fprintf_unfiltered (gdb_stdlog,
2757 "mips_eabi_push_dummy_call: sp=0x%s allocated %d\n",
2758 paddr_nz (sp), ROUND_UP (len, 16));
2760 /* Initialize the integer and float register pointers. */
2762 float_argreg = FPA0_REGNUM;
2764 /* The struct_return pointer occupies the first parameter-passing reg. */
2768 fprintf_unfiltered (gdb_stdlog,
2769 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2770 argreg, paddr_nz (struct_addr));
2771 write_register (argreg++, struct_addr);
2774 /* Now load as many as possible of the first arguments into
2775 registers, and push the rest onto the stack. Loop thru args
2776 from first to last. */
2777 for (argnum = 0; argnum < nargs; argnum++)
2780 char valbuf[MAX_REGISTER_SIZE];
2781 struct value *arg = args[argnum];
2782 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2783 int len = TYPE_LENGTH (arg_type);
2784 enum type_code typecode = TYPE_CODE (arg_type);
2787 fprintf_unfiltered (gdb_stdlog,
2788 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2789 argnum + 1, len, (int) typecode);
2791 /* The EABI passes structures that do not fit in a register by
2793 if (len > MIPS_SAVED_REGSIZE
2794 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2796 store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2797 typecode = TYPE_CODE_PTR;
2798 len = MIPS_SAVED_REGSIZE;
2801 fprintf_unfiltered (gdb_stdlog, " push");
2804 val = (char *) VALUE_CONTENTS (arg);
2806 /* 32-bit ABIs always start floating point arguments in an
2807 even-numbered floating point register. Round the FP register
2808 up before the check to see if there are any FP registers
2809 left. Non MIPS_EABI targets also pass the FP in the integer
2810 registers so also round up normal registers. */
2811 if (!FP_REGISTER_DOUBLE
2812 && fp_register_arg_p (typecode, arg_type))
2814 if ((float_argreg & 1))
2818 /* Floating point arguments passed in registers have to be
2819 treated specially. On 32-bit architectures, doubles
2820 are passed in register pairs; the even register gets
2821 the low word, and the odd register gets the high word.
2822 On non-EABI processors, the first two floating point arguments are
2823 also copied to general registers, because MIPS16 functions
2824 don't use float registers for arguments. This duplication of
2825 arguments in general registers can't hurt non-MIPS16 functions
2826 because those registers are normally skipped. */
2827 /* MIPS_EABI squeezes a struct that contains a single floating
2828 point value into an FP register instead of pushing it onto the
2830 if (fp_register_arg_p (typecode, arg_type)
2831 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2833 if (!FP_REGISTER_DOUBLE && len == 8)
2835 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2836 unsigned long regval;
2838 /* Write the low word of the double to the even register(s). */
2839 regval = extract_unsigned_integer (val + low_offset, 4);
2841 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2842 float_argreg, phex (regval, 4));
2843 write_register (float_argreg++, regval);
2845 /* Write the high word of the double to the odd register(s). */
2846 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2848 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2849 float_argreg, phex (regval, 4));
2850 write_register (float_argreg++, regval);
2854 /* This is a floating point value that fits entirely
2855 in a single register. */
2856 /* On 32 bit ABI's the float_argreg is further adjusted
2857 above to ensure that it is even register aligned. */
2858 LONGEST regval = extract_unsigned_integer (val, len);
2860 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2861 float_argreg, phex (regval, len));
2862 write_register (float_argreg++, regval);
2867 /* Copy the argument to general registers or the stack in
2868 register-sized pieces. Large arguments are split between
2869 registers and stack. */
2870 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2871 are treated specially: Irix cc passes them in registers
2872 where gcc sometimes puts them on the stack. For maximum
2873 compatibility, we will put them in both places. */
2874 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2875 (len % MIPS_SAVED_REGSIZE != 0));
2877 /* Note: Floating-point values that didn't fit into an FP
2878 register are only written to memory. */
2881 /* Remember if the argument was written to the stack. */
2882 int stack_used_p = 0;
2884 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2887 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2890 /* Write this portion of the argument to the stack. */
2891 if (argreg > MIPS_LAST_ARG_REGNUM
2893 || fp_register_arg_p (typecode, arg_type))
2895 /* Should shorter than int integer values be
2896 promoted to int before being stored? */
2897 int longword_offset = 0;
2900 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2902 if (MIPS_STACK_ARGSIZE == 8 &&
2903 (typecode == TYPE_CODE_INT ||
2904 typecode == TYPE_CODE_PTR ||
2905 typecode == TYPE_CODE_FLT) && len <= 4)
2906 longword_offset = MIPS_STACK_ARGSIZE - len;
2907 else if ((typecode == TYPE_CODE_STRUCT ||
2908 typecode == TYPE_CODE_UNION) &&
2909 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2910 longword_offset = MIPS_STACK_ARGSIZE - len;
2915 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2916 paddr_nz (stack_offset));
2917 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2918 paddr_nz (longword_offset));
2921 addr = sp + stack_offset + longword_offset;
2926 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2928 for (i = 0; i < partial_len; i++)
2930 fprintf_unfiltered (gdb_stdlog, "%02x",
2934 write_memory (addr, val, partial_len);
2937 /* Note!!! This is NOT an else clause. Odd sized
2938 structs may go thru BOTH paths. Floating point
2939 arguments will not. */
2940 /* Write this portion of the argument to a general
2941 purpose register. */
2942 if (argreg <= MIPS_LAST_ARG_REGNUM
2943 && !fp_register_arg_p (typecode, arg_type))
2945 LONGEST regval = extract_unsigned_integer (val, partial_len);
2948 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2950 phex (regval, MIPS_SAVED_REGSIZE));
2951 write_register (argreg, regval);
2958 /* Compute the the offset into the stack at which we
2959 will copy the next parameter.
2961 In the new EABI (and the NABI32), the stack_offset
2962 only needs to be adjusted when it has been used. */
2965 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2969 fprintf_unfiltered (gdb_stdlog, "\n");
2972 /* Return adjusted stack pointer. */
2976 /* N32/N64 version of push_dummy_call. */
2979 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2980 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2981 struct value **args, CORE_ADDR sp, int struct_return,
2982 CORE_ADDR struct_addr)
2988 int stack_offset = 0;
2990 /* For shared libraries, "t9" needs to point at the function
2992 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
2994 /* Set the return address register to point to the entry point of
2995 the program, where a breakpoint lies in wait. */
2996 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
2998 /* First ensure that the stack and structure return address (if any)
2999 are properly aligned. The stack has to be at least 64-bit
3000 aligned even on 32-bit machines, because doubles must be 64-bit
3001 aligned. For n32 and n64, stack frames need to be 128-bit
3002 aligned, so we round to this widest known alignment. */
3004 sp = ROUND_DOWN (sp, 16);
3005 struct_addr = ROUND_DOWN (struct_addr, 16);
3007 /* Now make space on the stack for the args. */
3008 for (argnum = 0; argnum < nargs; argnum++)
3009 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3010 MIPS_STACK_ARGSIZE);
3011 sp -= ROUND_UP (len, 16);
3014 fprintf_unfiltered (gdb_stdlog,
3015 "mips_n32n64_push_dummy_call: sp=0x%s allocated %d\n",
3016 paddr_nz (sp), ROUND_UP (len, 16));
3018 /* Initialize the integer and float register pointers. */
3020 float_argreg = FPA0_REGNUM;
3022 /* The struct_return pointer occupies the first parameter-passing reg. */
3026 fprintf_unfiltered (gdb_stdlog,
3027 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3028 argreg, paddr_nz (struct_addr));
3029 write_register (argreg++, struct_addr);
3032 /* Now load as many as possible of the first arguments into
3033 registers, and push the rest onto the stack. Loop thru args
3034 from first to last. */
3035 for (argnum = 0; argnum < nargs; argnum++)
3038 char valbuf[MAX_REGISTER_SIZE];
3039 struct value *arg = args[argnum];
3040 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3041 int len = TYPE_LENGTH (arg_type);
3042 enum type_code typecode = TYPE_CODE (arg_type);
3045 fprintf_unfiltered (gdb_stdlog,
3046 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3047 argnum + 1, len, (int) typecode);
3049 val = (char *) VALUE_CONTENTS (arg);
3051 if (fp_register_arg_p (typecode, arg_type)
3052 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3054 /* This is a floating point value that fits entirely
3055 in a single register. */
3056 /* On 32 bit ABI's the float_argreg is further adjusted
3057 above to ensure that it is even register aligned. */
3058 LONGEST regval = extract_unsigned_integer (val, len);
3060 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3061 float_argreg, phex (regval, len));
3062 write_register (float_argreg++, regval);
3065 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3066 argreg, phex (regval, len));
3067 write_register (argreg, regval);
3072 /* Copy the argument to general registers or the stack in
3073 register-sized pieces. Large arguments are split between
3074 registers and stack. */
3075 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3076 are treated specially: Irix cc passes them in registers
3077 where gcc sometimes puts them on the stack. For maximum
3078 compatibility, we will put them in both places. */
3079 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3080 (len % MIPS_SAVED_REGSIZE != 0));
3081 /* Note: Floating-point values that didn't fit into an FP
3082 register are only written to memory. */
3085 /* Rememer if the argument was written to the stack. */
3086 int stack_used_p = 0;
3087 int partial_len = len < MIPS_SAVED_REGSIZE ?
3088 len : MIPS_SAVED_REGSIZE;
3091 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3094 /* Write this portion of the argument to the stack. */
3095 if (argreg > MIPS_LAST_ARG_REGNUM
3097 || fp_register_arg_p (typecode, arg_type))
3099 /* Should shorter than int integer values be
3100 promoted to int before being stored? */
3101 int longword_offset = 0;
3104 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3106 if (MIPS_STACK_ARGSIZE == 8 &&
3107 (typecode == TYPE_CODE_INT ||
3108 typecode == TYPE_CODE_PTR ||
3109 typecode == TYPE_CODE_FLT) && len <= 4)
3110 longword_offset = MIPS_STACK_ARGSIZE - len;
3115 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3116 paddr_nz (stack_offset));
3117 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3118 paddr_nz (longword_offset));
3121 addr = sp + stack_offset + longword_offset;
3126 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3128 for (i = 0; i < partial_len; i++)
3130 fprintf_unfiltered (gdb_stdlog, "%02x",
3134 write_memory (addr, val, partial_len);
3137 /* Note!!! This is NOT an else clause. Odd sized
3138 structs may go thru BOTH paths. Floating point
3139 arguments will not. */
3140 /* Write this portion of the argument to a general
3141 purpose register. */
3142 if (argreg <= MIPS_LAST_ARG_REGNUM
3143 && !fp_register_arg_p (typecode, arg_type))
3145 LONGEST regval = extract_unsigned_integer (val, partial_len);
3147 /* A non-floating-point argument being passed in a
3148 general register. If a struct or union, and if
3149 the remaining length is smaller than the register
3150 size, we have to adjust the register value on
3153 It does not seem to be necessary to do the
3154 same for integral types.
3156 cagney/2001-07-23: gdb/179: Also, GCC, when
3157 outputting LE O32 with sizeof (struct) <
3158 MIPS_SAVED_REGSIZE, generates a left shift as
3159 part of storing the argument in a register a
3160 register (the left shift isn't generated when
3161 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3162 is quite possible that this is GCC contradicting
3163 the LE/O32 ABI, GDB has not been adjusted to
3164 accommodate this. Either someone needs to
3165 demonstrate that the LE/O32 ABI specifies such a
3166 left shift OR this new ABI gets identified as
3167 such and GDB gets tweaked accordingly. */
3169 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3170 && partial_len < MIPS_SAVED_REGSIZE
3171 && (typecode == TYPE_CODE_STRUCT ||
3172 typecode == TYPE_CODE_UNION))
3173 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3177 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3179 phex (regval, MIPS_SAVED_REGSIZE));
3180 write_register (argreg, regval);
3187 /* Compute the the offset into the stack at which we
3188 will copy the next parameter.
3190 In N32 (N64?), the stack_offset only needs to be
3191 adjusted when it has been used. */
3194 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3198 fprintf_unfiltered (gdb_stdlog, "\n");
3201 /* Return adjusted stack pointer. */
3205 /* O32 version of push_dummy_call. */
3208 mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3209 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3210 struct value **args, CORE_ADDR sp, int struct_return,
3211 CORE_ADDR struct_addr)
3217 int stack_offset = 0;
3219 /* For shared libraries, "t9" needs to point at the function
3221 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3223 /* Set the return address register to point to the entry point of
3224 the program, where a breakpoint lies in wait. */
3225 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3227 /* First ensure that the stack and structure return address (if any)
3228 are properly aligned. The stack has to be at least 64-bit
3229 aligned even on 32-bit machines, because doubles must be 64-bit
3230 aligned. For n32 and n64, stack frames need to be 128-bit
3231 aligned, so we round to this widest known alignment. */
3233 sp = ROUND_DOWN (sp, 16);
3234 struct_addr = ROUND_DOWN (struct_addr, 16);
3236 /* Now make space on the stack for the args. */
3237 for (argnum = 0; argnum < nargs; argnum++)
3238 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3239 MIPS_STACK_ARGSIZE);
3240 sp -= ROUND_UP (len, 16);
3243 fprintf_unfiltered (gdb_stdlog,
3244 "mips_o32_push_dummy_call: sp=0x%s allocated %d\n",
3245 paddr_nz (sp), ROUND_UP (len, 16));
3247 /* Initialize the integer and float register pointers. */
3249 float_argreg = FPA0_REGNUM;
3251 /* The struct_return pointer occupies the first parameter-passing reg. */
3255 fprintf_unfiltered (gdb_stdlog,
3256 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3257 argreg, paddr_nz (struct_addr));
3258 write_register (argreg++, struct_addr);
3259 stack_offset += MIPS_STACK_ARGSIZE;
3262 /* Now load as many as possible of the first arguments into
3263 registers, and push the rest onto the stack. Loop thru args
3264 from first to last. */
3265 for (argnum = 0; argnum < nargs; argnum++)
3268 char valbuf[MAX_REGISTER_SIZE];
3269 struct value *arg = args[argnum];
3270 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3271 int len = TYPE_LENGTH (arg_type);
3272 enum type_code typecode = TYPE_CODE (arg_type);
3275 fprintf_unfiltered (gdb_stdlog,
3276 "mips_o32_push_dummy_call: %d len=%d type=%d",
3277 argnum + 1, len, (int) typecode);
3279 val = (char *) VALUE_CONTENTS (arg);
3281 /* 32-bit ABIs always start floating point arguments in an
3282 even-numbered floating point register. Round the FP register
3283 up before the check to see if there are any FP registers
3284 left. O32/O64 targets also pass the FP in the integer
3285 registers so also round up normal registers. */
3286 if (!FP_REGISTER_DOUBLE
3287 && fp_register_arg_p (typecode, arg_type))
3289 if ((float_argreg & 1))
3293 /* Floating point arguments passed in registers have to be
3294 treated specially. On 32-bit architectures, doubles
3295 are passed in register pairs; the even register gets
3296 the low word, and the odd register gets the high word.
3297 On O32/O64, the first two floating point arguments are
3298 also copied to general registers, because MIPS16 functions
3299 don't use float registers for arguments. This duplication of
3300 arguments in general registers can't hurt non-MIPS16 functions
3301 because those registers are normally skipped. */
3303 if (fp_register_arg_p (typecode, arg_type)
3304 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3306 if (!FP_REGISTER_DOUBLE && len == 8)
3308 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3309 unsigned long regval;
3311 /* Write the low word of the double to the even register(s). */
3312 regval = extract_unsigned_integer (val + low_offset, 4);
3314 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3315 float_argreg, phex (regval, 4));
3316 write_register (float_argreg++, regval);
3318 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3319 argreg, phex (regval, 4));
3320 write_register (argreg++, regval);
3322 /* Write the high word of the double to the odd register(s). */
3323 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3325 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3326 float_argreg, phex (regval, 4));
3327 write_register (float_argreg++, regval);
3330 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3331 argreg, phex (regval, 4));
3332 write_register (argreg++, regval);
3336 /* This is a floating point value that fits entirely
3337 in a single register. */
3338 /* On 32 bit ABI's the float_argreg is further adjusted
3339 above to ensure that it is even register aligned. */
3340 LONGEST regval = extract_unsigned_integer (val, len);
3342 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3343 float_argreg, phex (regval, len));
3344 write_register (float_argreg++, regval);
3345 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3346 registers for each argument. The below is (my
3347 guess) to ensure that the corresponding integer
3348 register has reserved the same space. */
3350 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3351 argreg, phex (regval, len));
3352 write_register (argreg, regval);
3353 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3355 /* Reserve space for the FP register. */
3356 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3360 /* Copy the argument to general registers or the stack in
3361 register-sized pieces. Large arguments are split between
3362 registers and stack. */
3363 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3364 are treated specially: Irix cc passes them in registers
3365 where gcc sometimes puts them on the stack. For maximum
3366 compatibility, we will put them in both places. */
3367 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3368 (len % MIPS_SAVED_REGSIZE != 0));
3369 /* Structures should be aligned to eight bytes (even arg registers)
3370 on MIPS_ABI_O32, if their first member has double precision. */
3371 if (MIPS_SAVED_REGSIZE < 8
3372 && mips_type_needs_double_align (arg_type))
3377 /* Note: Floating-point values that didn't fit into an FP
3378 register are only written to memory. */
3381 /* Remember if the argument was written to the stack. */
3382 int stack_used_p = 0;
3384 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3387 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3390 /* Write this portion of the argument to the stack. */
3391 if (argreg > MIPS_LAST_ARG_REGNUM
3393 || fp_register_arg_p (typecode, arg_type))
3395 /* Should shorter than int integer values be
3396 promoted to int before being stored? */
3397 int longword_offset = 0;
3400 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3402 if (MIPS_STACK_ARGSIZE == 8 &&
3403 (typecode == TYPE_CODE_INT ||
3404 typecode == TYPE_CODE_PTR ||
3405 typecode == TYPE_CODE_FLT) && len <= 4)
3406 longword_offset = MIPS_STACK_ARGSIZE - len;
3411 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3412 paddr_nz (stack_offset));
3413 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3414 paddr_nz (longword_offset));
3417 addr = sp + stack_offset + longword_offset;
3422 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3424 for (i = 0; i < partial_len; i++)
3426 fprintf_unfiltered (gdb_stdlog, "%02x",
3430 write_memory (addr, val, partial_len);
3433 /* Note!!! This is NOT an else clause. Odd sized
3434 structs may go thru BOTH paths. Floating point
3435 arguments will not. */
3436 /* Write this portion of the argument to a general
3437 purpose register. */
3438 if (argreg <= MIPS_LAST_ARG_REGNUM
3439 && !fp_register_arg_p (typecode, arg_type))
3441 LONGEST regval = extract_signed_integer (val, partial_len);
3442 /* Value may need to be sign extended, because
3443 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3445 /* A non-floating-point argument being passed in a
3446 general register. If a struct or union, and if
3447 the remaining length is smaller than the register
3448 size, we have to adjust the register value on
3451 It does not seem to be necessary to do the
3452 same for integral types.
3454 Also don't do this adjustment on O64 binaries.
3456 cagney/2001-07-23: gdb/179: Also, GCC, when
3457 outputting LE O32 with sizeof (struct) <
3458 MIPS_SAVED_REGSIZE, generates a left shift as
3459 part of storing the argument in a register a
3460 register (the left shift isn't generated when
3461 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3462 is quite possible that this is GCC contradicting
3463 the LE/O32 ABI, GDB has not been adjusted to
3464 accommodate this. Either someone needs to
3465 demonstrate that the LE/O32 ABI specifies such a
3466 left shift OR this new ABI gets identified as
3467 such and GDB gets tweaked accordingly. */
3469 if (MIPS_SAVED_REGSIZE < 8
3470 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3471 && partial_len < MIPS_SAVED_REGSIZE
3472 && (typecode == TYPE_CODE_STRUCT ||
3473 typecode == TYPE_CODE_UNION))
3474 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3478 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3480 phex (regval, MIPS_SAVED_REGSIZE));
3481 write_register (argreg, regval);
3484 /* Prevent subsequent floating point arguments from
3485 being passed in floating point registers. */
3486 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3492 /* Compute the the offset into the stack at which we
3493 will copy the next parameter.
3495 In older ABIs, the caller reserved space for
3496 registers that contained arguments. This was loosely
3497 refered to as their "home". Consequently, space is
3498 always allocated. */
3500 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3504 fprintf_unfiltered (gdb_stdlog, "\n");
3507 /* Return adjusted stack pointer. */
3511 /* O64 version of push_dummy_call. */
3514 mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3515 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3516 struct value **args, CORE_ADDR sp, int struct_return,
3517 CORE_ADDR struct_addr)
3523 int stack_offset = 0;
3525 /* For shared libraries, "t9" needs to point at the function
3527 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3529 /* Set the return address register to point to the entry point of
3530 the program, where a breakpoint lies in wait. */
3531 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3533 /* First ensure that the stack and structure return address (if any)
3534 are properly aligned. The stack has to be at least 64-bit
3535 aligned even on 32-bit machines, because doubles must be 64-bit
3536 aligned. For n32 and n64, stack frames need to be 128-bit
3537 aligned, so we round to this widest known alignment. */
3539 sp = ROUND_DOWN (sp, 16);
3540 struct_addr = ROUND_DOWN (struct_addr, 16);
3542 /* Now make space on the stack for the args. */
3543 for (argnum = 0; argnum < nargs; argnum++)
3544 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3545 MIPS_STACK_ARGSIZE);
3546 sp -= ROUND_UP (len, 16);
3549 fprintf_unfiltered (gdb_stdlog,
3550 "mips_o64_push_dummy_call: sp=0x%s allocated %d\n",
3551 paddr_nz (sp), ROUND_UP (len, 16));
3553 /* Initialize the integer and float register pointers. */
3555 float_argreg = FPA0_REGNUM;
3557 /* The struct_return pointer occupies the first parameter-passing reg. */
3561 fprintf_unfiltered (gdb_stdlog,
3562 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3563 argreg, paddr_nz (struct_addr));
3564 write_register (argreg++, struct_addr);
3565 stack_offset += MIPS_STACK_ARGSIZE;
3568 /* Now load as many as possible of the first arguments into
3569 registers, and push the rest onto the stack. Loop thru args
3570 from first to last. */
3571 for (argnum = 0; argnum < nargs; argnum++)
3574 char valbuf[MAX_REGISTER_SIZE];
3575 struct value *arg = args[argnum];
3576 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3577 int len = TYPE_LENGTH (arg_type);
3578 enum type_code typecode = TYPE_CODE (arg_type);
3581 fprintf_unfiltered (gdb_stdlog,
3582 "mips_o64_push_dummy_call: %d len=%d type=%d",
3583 argnum + 1, len, (int) typecode);
3585 val = (char *) VALUE_CONTENTS (arg);
3587 /* 32-bit ABIs always start floating point arguments in an
3588 even-numbered floating point register. Round the FP register
3589 up before the check to see if there are any FP registers
3590 left. O32/O64 targets also pass the FP in the integer
3591 registers so also round up normal registers. */
3592 if (!FP_REGISTER_DOUBLE
3593 && fp_register_arg_p (typecode, arg_type))
3595 if ((float_argreg & 1))
3599 /* Floating point arguments passed in registers have to be
3600 treated specially. On 32-bit architectures, doubles
3601 are passed in register pairs; the even register gets
3602 the low word, and the odd register gets the high word.
3603 On O32/O64, the first two floating point arguments are
3604 also copied to general registers, because MIPS16 functions
3605 don't use float registers for arguments. This duplication of
3606 arguments in general registers can't hurt non-MIPS16 functions
3607 because those registers are normally skipped. */
3609 if (fp_register_arg_p (typecode, arg_type)
3610 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3612 if (!FP_REGISTER_DOUBLE && len == 8)
3614 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3615 unsigned long regval;
3617 /* Write the low word of the double to the even register(s). */
3618 regval = extract_unsigned_integer (val + low_offset, 4);
3620 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3621 float_argreg, phex (regval, 4));
3622 write_register (float_argreg++, regval);
3624 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3625 argreg, phex (regval, 4));
3626 write_register (argreg++, regval);
3628 /* Write the high word of the double to the odd register(s). */
3629 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3631 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3632 float_argreg, phex (regval, 4));
3633 write_register (float_argreg++, regval);
3636 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3637 argreg, phex (regval, 4));
3638 write_register (argreg++, regval);
3642 /* This is a floating point value that fits entirely
3643 in a single register. */
3644 /* On 32 bit ABI's the float_argreg is further adjusted
3645 above to ensure that it is even register aligned. */
3646 LONGEST regval = extract_unsigned_integer (val, len);
3648 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3649 float_argreg, phex (regval, len));
3650 write_register (float_argreg++, regval);
3651 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3652 registers for each argument. The below is (my
3653 guess) to ensure that the corresponding integer
3654 register has reserved the same space. */
3656 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3657 argreg, phex (regval, len));
3658 write_register (argreg, regval);
3659 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3661 /* Reserve space for the FP register. */
3662 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3666 /* Copy the argument to general registers or the stack in
3667 register-sized pieces. Large arguments are split between
3668 registers and stack. */
3669 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3670 are treated specially: Irix cc passes them in registers
3671 where gcc sometimes puts them on the stack. For maximum
3672 compatibility, we will put them in both places. */
3673 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3674 (len % MIPS_SAVED_REGSIZE != 0));
3675 /* Structures should be aligned to eight bytes (even arg registers)
3676 on MIPS_ABI_O32, if their first member has double precision. */
3677 if (MIPS_SAVED_REGSIZE < 8
3678 && mips_type_needs_double_align (arg_type))
3683 /* Note: Floating-point values that didn't fit into an FP
3684 register are only written to memory. */
3687 /* Remember if the argument was written to the stack. */
3688 int stack_used_p = 0;
3690 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3693 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3696 /* Write this portion of the argument to the stack. */
3697 if (argreg > MIPS_LAST_ARG_REGNUM
3699 || fp_register_arg_p (typecode, arg_type))
3701 /* Should shorter than int integer values be
3702 promoted to int before being stored? */
3703 int longword_offset = 0;
3706 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3708 if (MIPS_STACK_ARGSIZE == 8 &&
3709 (typecode == TYPE_CODE_INT ||
3710 typecode == TYPE_CODE_PTR ||
3711 typecode == TYPE_CODE_FLT) && len <= 4)
3712 longword_offset = MIPS_STACK_ARGSIZE - len;
3717 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3718 paddr_nz (stack_offset));
3719 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3720 paddr_nz (longword_offset));
3723 addr = sp + stack_offset + longword_offset;
3728 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3730 for (i = 0; i < partial_len; i++)
3732 fprintf_unfiltered (gdb_stdlog, "%02x",
3736 write_memory (addr, val, partial_len);
3739 /* Note!!! This is NOT an else clause. Odd sized
3740 structs may go thru BOTH paths. Floating point
3741 arguments will not. */
3742 /* Write this portion of the argument to a general
3743 purpose register. */
3744 if (argreg <= MIPS_LAST_ARG_REGNUM
3745 && !fp_register_arg_p (typecode, arg_type))
3747 LONGEST regval = extract_signed_integer (val, partial_len);
3748 /* Value may need to be sign extended, because
3749 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3751 /* A non-floating-point argument being passed in a
3752 general register. If a struct or union, and if
3753 the remaining length is smaller than the register
3754 size, we have to adjust the register value on
3757 It does not seem to be necessary to do the
3758 same for integral types.
3760 Also don't do this adjustment on O64 binaries.
3762 cagney/2001-07-23: gdb/179: Also, GCC, when
3763 outputting LE O32 with sizeof (struct) <
3764 MIPS_SAVED_REGSIZE, generates a left shift as
3765 part of storing the argument in a register a
3766 register (the left shift isn't generated when
3767 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3768 is quite possible that this is GCC contradicting
3769 the LE/O32 ABI, GDB has not been adjusted to
3770 accommodate this. Either someone needs to
3771 demonstrate that the LE/O32 ABI specifies such a
3772 left shift OR this new ABI gets identified as
3773 such and GDB gets tweaked accordingly. */
3775 if (MIPS_SAVED_REGSIZE < 8
3776 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3777 && partial_len < MIPS_SAVED_REGSIZE
3778 && (typecode == TYPE_CODE_STRUCT ||
3779 typecode == TYPE_CODE_UNION))
3780 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3784 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3786 phex (regval, MIPS_SAVED_REGSIZE));
3787 write_register (argreg, regval);
3790 /* Prevent subsequent floating point arguments from
3791 being passed in floating point registers. */
3792 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3798 /* Compute the the offset into the stack at which we
3799 will copy the next parameter.
3801 In older ABIs, the caller reserved space for
3802 registers that contained arguments. This was loosely
3803 refered to as their "home". Consequently, space is
3804 always allocated. */
3806 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3810 fprintf_unfiltered (gdb_stdlog, "\n");
3813 /* Return adjusted stack pointer. */
3818 mips_pop_frame (void)
3820 register int regnum;
3821 struct frame_info *frame = get_current_frame ();
3822 CORE_ADDR new_sp = get_frame_base (frame);
3823 mips_extra_func_info_t proc_desc;
3825 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
3827 generic_pop_dummy_frame ();
3828 flush_cached_frames ();
3832 proc_desc = get_frame_extra_info (frame)->proc_desc;
3833 write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame));
3834 mips_find_saved_regs (frame);
3835 for (regnum = 0; regnum < NUM_REGS; regnum++)
3836 if (regnum != SP_REGNUM && regnum != PC_REGNUM
3837 && get_frame_saved_regs (frame)[regnum])
3839 /* Floating point registers must not be sign extended,
3840 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3842 if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32)
3843 write_register (regnum,
3844 read_memory_unsigned_integer (get_frame_saved_regs (frame)[regnum],
3845 MIPS_SAVED_REGSIZE));
3847 write_register (regnum,
3848 read_memory_integer (get_frame_saved_regs (frame)[regnum],
3849 MIPS_SAVED_REGSIZE));
3852 write_register (SP_REGNUM, new_sp);
3853 flush_cached_frames ();
3855 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
3857 struct linked_proc_info *pi_ptr, *prev_ptr;
3859 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
3861 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
3863 if (&pi_ptr->info == proc_desc)
3868 error ("Can't locate dummy extra frame info\n");
3870 if (prev_ptr != NULL)
3871 prev_ptr->next = pi_ptr->next;
3873 linked_proc_desc_table = pi_ptr->next;
3877 write_register (HI_REGNUM,
3878 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
3879 MIPS_SAVED_REGSIZE));
3880 write_register (LO_REGNUM,
3881 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
3882 MIPS_SAVED_REGSIZE));
3883 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
3884 write_register (FCRCS_REGNUM,
3885 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
3886 MIPS_SAVED_REGSIZE));
3890 /* Floating point register management.
3892 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3893 64bit operations, these early MIPS cpus treat fp register pairs
3894 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3895 registers and offer a compatibility mode that emulates the MIPS2 fp
3896 model. When operating in MIPS2 fp compat mode, later cpu's split
3897 double precision floats into two 32-bit chunks and store them in
3898 consecutive fp regs. To display 64-bit floats stored in this
3899 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3900 Throw in user-configurable endianness and you have a real mess.
3902 The way this works is:
3903 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3904 double-precision value will be split across two logical registers.
3905 The lower-numbered logical register will hold the low-order bits,
3906 regardless of the processor's endianness.
3907 - If we are on a 64-bit processor, and we are looking for a
3908 single-precision value, it will be in the low ordered bits
3909 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3910 save slot in memory.
3911 - If we are in 64-bit mode, everything is straightforward.
3913 Note that this code only deals with "live" registers at the top of the
3914 stack. We will attempt to deal with saved registers later, when
3915 the raw/cooked register interface is in place. (We need a general
3916 interface that can deal with dynamic saved register sizes -- fp
3917 regs could be 32 bits wide in one frame and 64 on the frame above
3920 static struct type *
3921 mips_float_register_type (void)
3923 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3924 return builtin_type_ieee_single_big;
3926 return builtin_type_ieee_single_little;
3929 static struct type *
3930 mips_double_register_type (void)
3932 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3933 return builtin_type_ieee_double_big;
3935 return builtin_type_ieee_double_little;
3938 /* Copy a 32-bit single-precision value from the current frame
3939 into rare_buffer. */
3942 mips_read_fp_register_single (struct frame_info *frame, int regno,
3945 int raw_size = REGISTER_RAW_SIZE (regno);
3946 char *raw_buffer = alloca (raw_size);
3948 if (!frame_register_read (frame, regno, raw_buffer))
3949 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3952 /* We have a 64-bit value for this register. Find the low-order
3956 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3961 memcpy (rare_buffer, raw_buffer + offset, 4);
3965 memcpy (rare_buffer, raw_buffer, 4);
3969 /* Copy a 64-bit double-precision value from the current frame into
3970 rare_buffer. This may include getting half of it from the next
3974 mips_read_fp_register_double (struct frame_info *frame, int regno,
3977 int raw_size = REGISTER_RAW_SIZE (regno);
3979 if (raw_size == 8 && !mips2_fp_compat ())
3981 /* We have a 64-bit value for this register, and we should use
3983 if (!frame_register_read (frame, regno, rare_buffer))
3984 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3988 if ((regno - FP0_REGNUM) & 1)
3989 internal_error (__FILE__, __LINE__,
3990 "mips_read_fp_register_double: bad access to "
3991 "odd-numbered FP register");
3993 /* mips_read_fp_register_single will find the correct 32 bits from
3995 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3997 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
3998 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4002 mips_read_fp_register_single (frame, regno, rare_buffer);
4003 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4009 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4011 { /* do values for FP (float) regs */
4013 double doub, flt1, flt2; /* doubles extracted from raw hex data */
4014 int inv1, inv2, namelen;
4016 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
4018 fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
4019 fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
4022 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
4024 /* 4-byte registers: Print hex and floating. Also print even
4025 numbered registers as doubles. */
4026 mips_read_fp_register_single (frame, regnum, raw_buffer);
4027 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4029 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file);
4031 fprintf_filtered (file, " flt: ");
4033 fprintf_filtered (file, " <invalid float> ");
4035 fprintf_filtered (file, "%-17.9g", flt1);
4037 if (regnum % 2 == 0)
4039 mips_read_fp_register_double (frame, regnum, raw_buffer);
4040 doub = unpack_double (mips_double_register_type (), raw_buffer,
4043 fprintf_filtered (file, " dbl: ");
4045 fprintf_filtered (file, "<invalid double>");
4047 fprintf_filtered (file, "%-24.17g", doub);
4052 /* Eight byte registers: print each one as hex, float and double. */
4053 mips_read_fp_register_single (frame, regnum, raw_buffer);
4054 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4056 mips_read_fp_register_double (frame, regnum, raw_buffer);
4057 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4060 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file);
4062 fprintf_filtered (file, " flt: ");
4064 fprintf_filtered (file, "<invalid float>");
4066 fprintf_filtered (file, "%-17.9g", flt1);
4068 fprintf_filtered (file, " dbl: ");
4070 fprintf_filtered (file, "<invalid double>");
4072 fprintf_filtered (file, "%-24.17g", doub);
4077 mips_print_register (struct ui_file *file, struct frame_info *frame,
4078 int regnum, int all)
4080 char raw_buffer[MAX_REGISTER_SIZE];
4083 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4085 mips_print_fp_register (file, frame, regnum);
4089 /* Get the data in raw format. */
4090 if (!frame_register_read (frame, regnum, raw_buffer))
4092 fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum));
4096 fputs_filtered (REGISTER_NAME (regnum), file);
4098 /* The problem with printing numeric register names (r26, etc.) is that
4099 the user can't use them on input. Probably the best solution is to
4100 fix it so that either the numeric or the funky (a2, etc.) names
4101 are accepted on input. */
4102 if (regnum < MIPS_NUMREGS)
4103 fprintf_filtered (file, "(r%d): ", regnum);
4105 fprintf_filtered (file, ": ");
4107 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4108 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4112 print_scalar_formatted (raw_buffer + offset,
4113 REGISTER_VIRTUAL_TYPE (regnum),
4117 /* Replacement for generic do_registers_info.
4118 Print regs in pretty columns. */
4121 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4124 fprintf_filtered (file, " ");
4125 mips_print_fp_register (file, frame, regnum);
4126 fprintf_filtered (file, "\n");
4131 /* Print a row's worth of GP (int) registers, with name labels above */
4134 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4137 /* do values for GP (int) regs */
4138 char raw_buffer[MAX_REGISTER_SIZE];
4139 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
4141 int start_regnum = regnum;
4142 int numregs = NUM_REGS;
4145 /* For GP registers, we print a separate row of names above the vals */
4146 fprintf_filtered (file, " ");
4147 for (col = 0; col < ncols && regnum < numregs; regnum++)
4149 if (*REGISTER_NAME (regnum) == '\0')
4150 continue; /* unused register */
4151 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4152 break; /* end the row: reached FP register */
4153 fprintf_filtered (file, MIPS_REGSIZE == 8 ? "%17s" : "%9s",
4154 REGISTER_NAME (regnum));
4157 fprintf_filtered (file,
4158 start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
4159 start_regnum); /* print the R0 to R31 names */
4161 regnum = start_regnum; /* go back to start of row */
4162 /* now print the values in hex, 4 or 8 to the row */
4163 for (col = 0; col < ncols && regnum < numregs; regnum++)
4165 if (*REGISTER_NAME (regnum) == '\0')
4166 continue; /* unused register */
4167 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4168 break; /* end row: reached FP register */
4169 /* OK: get the data in raw format. */
4170 if (!frame_register_read (frame, regnum, raw_buffer))
4171 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4172 /* pad small registers */
4173 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
4174 printf_filtered (" ");
4175 /* Now print the register value in hex, endian order. */
4176 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4177 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4178 byte < REGISTER_RAW_SIZE (regnum);
4180 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4182 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
4185 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4186 fprintf_filtered (file, " ");
4189 if (col > 0) /* ie. if we actually printed anything... */
4190 fprintf_filtered (file, "\n");
4195 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4198 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4199 struct frame_info *frame, int regnum, int all)
4201 if (regnum != -1) /* do one specified register */
4203 if (*(REGISTER_NAME (regnum)) == '\0')
4204 error ("Not a valid register for the current processor type");
4206 mips_print_register (file, frame, regnum, 0);
4207 fprintf_filtered (file, "\n");
4210 /* do all (or most) registers */
4213 while (regnum < NUM_REGS)
4215 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4217 if (all) /* true for "INFO ALL-REGISTERS" command */
4218 regnum = print_fp_register_row (file, frame, regnum);
4220 regnum += MIPS_NUMREGS; /* skip floating point regs */
4223 regnum = print_gp_register_row (file, frame, regnum);
4228 /* Is this a branch with a delay slot? */
4230 static int is_delayed (unsigned long);
4233 is_delayed (unsigned long insn)
4236 for (i = 0; i < NUMOPCODES; ++i)
4237 if (mips_opcodes[i].pinfo != INSN_MACRO
4238 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4240 return (i < NUMOPCODES
4241 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4242 | INSN_COND_BRANCH_DELAY
4243 | INSN_COND_BRANCH_LIKELY)));
4247 mips_step_skips_delay (CORE_ADDR pc)
4249 char buf[MIPS_INSTLEN];
4251 /* There is no branch delay slot on MIPS16. */
4252 if (pc_is_mips16 (pc))
4255 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4256 /* If error reading memory, guess that it is not a delayed branch. */
4258 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
4262 /* Skip the PC past function prologue instructions (32-bit version).
4263 This is a helper function for mips_skip_prologue. */
4266 mips32_skip_prologue (CORE_ADDR pc)
4270 int seen_sp_adjust = 0;
4271 int load_immediate_bytes = 0;
4273 /* Skip the typical prologue instructions. These are the stack adjustment
4274 instruction and the instructions that save registers on the stack
4275 or in the gcc frame. */
4276 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
4278 unsigned long high_word;
4280 inst = mips_fetch_instruction (pc);
4281 high_word = (inst >> 16) & 0xffff;
4283 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4284 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4286 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4287 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4289 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4290 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4291 && (inst & 0x001F0000)) /* reg != $zero */
4294 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4296 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4298 continue; /* reg != $zero */
4300 /* move $s8,$sp. With different versions of gas this will be either
4301 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4302 Accept any one of these. */
4303 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4306 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4308 else if (high_word == 0x3c1c) /* lui $gp,n */
4310 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4312 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4313 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4315 /* The following instructions load $at or $t0 with an immediate
4316 value in preparation for a stack adjustment via
4317 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4318 a local variable, so we accept them only before a stack adjustment
4319 instruction was seen. */
4320 else if (!seen_sp_adjust)
4322 if (high_word == 0x3c01 || /* lui $at,n */
4323 high_word == 0x3c08) /* lui $t0,n */
4325 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4328 else if (high_word == 0x3421 || /* ori $at,$at,n */
4329 high_word == 0x3508 || /* ori $t0,$t0,n */
4330 high_word == 0x3401 || /* ori $at,$zero,n */
4331 high_word == 0x3408) /* ori $t0,$zero,n */
4333 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4343 /* In a frameless function, we might have incorrectly
4344 skipped some load immediate instructions. Undo the skipping
4345 if the load immediate was not followed by a stack adjustment. */
4346 if (load_immediate_bytes && !seen_sp_adjust)
4347 pc -= load_immediate_bytes;
4351 /* Skip the PC past function prologue instructions (16-bit version).
4352 This is a helper function for mips_skip_prologue. */
4355 mips16_skip_prologue (CORE_ADDR pc)
4358 int extend_bytes = 0;
4359 int prev_extend_bytes;
4361 /* Table of instructions likely to be found in a function prologue. */
4364 unsigned short inst;
4365 unsigned short mask;
4372 , /* addiu $sp,offset */
4376 , /* daddiu $sp,offset */
4380 , /* sw reg,n($sp) */
4384 , /* sd reg,n($sp) */
4388 , /* sw $ra,n($sp) */
4392 , /* sd $ra,n($sp) */
4400 , /* sw $a0-$a3,n($s1) */
4404 , /* move reg,$a0-$a3 */
4408 , /* entry pseudo-op */
4412 , /* addiu $s1,$sp,n */
4415 } /* end of table marker */
4418 /* Skip the typical prologue instructions. These are the stack adjustment
4419 instruction and the instructions that save registers on the stack
4420 or in the gcc frame. */
4421 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
4423 unsigned short inst;
4426 inst = mips_fetch_instruction (pc);
4428 /* Normally we ignore an extend instruction. However, if it is
4429 not followed by a valid prologue instruction, we must adjust
4430 the pc back over the extend so that it won't be considered
4431 part of the prologue. */
4432 if ((inst & 0xf800) == 0xf000) /* extend */
4434 extend_bytes = MIPS16_INSTLEN;
4437 prev_extend_bytes = extend_bytes;
4440 /* Check for other valid prologue instructions besides extend. */
4441 for (i = 0; table[i].mask != 0; i++)
4442 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4444 if (table[i].mask != 0) /* it was in table? */
4445 continue; /* ignore it */
4449 /* Return the current pc, adjusted backwards by 2 if
4450 the previous instruction was an extend. */
4451 return pc - prev_extend_bytes;
4457 /* To skip prologues, I use this predicate. Returns either PC itself
4458 if the code at PC does not look like a function prologue; otherwise
4459 returns an address that (if we're lucky) follows the prologue. If
4460 LENIENT, then we must skip everything which is involved in setting
4461 up the frame (it's OK to skip more, just so long as we don't skip
4462 anything which might clobber the registers which are being saved.
4463 We must skip more in the case where part of the prologue is in the
4464 delay slot of a non-prologue instruction). */
4467 mips_skip_prologue (CORE_ADDR pc)
4469 /* See if we can determine the end of the prologue via the symbol table.
4470 If so, then return either PC, or the PC after the prologue, whichever
4473 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4475 if (post_prologue_pc != 0)
4476 return max (pc, post_prologue_pc);
4478 /* Can't determine prologue from the symbol table, need to examine
4481 if (pc_is_mips16 (pc))
4482 return mips16_skip_prologue (pc);
4484 return mips32_skip_prologue (pc);
4487 /* Determine how a return value is stored within the MIPS register
4488 file, given the return type `valtype'. */
4490 struct return_value_word
4499 return_value_location (struct type *valtype,
4500 struct return_value_word *hi,
4501 struct return_value_word *lo)
4503 int len = TYPE_LENGTH (valtype);
4505 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
4506 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
4507 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
4509 if (!FP_REGISTER_DOUBLE && len == 8)
4511 /* We need to break a 64bit float in two 32 bit halves and
4512 spread them across a floating-point register pair. */
4513 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
4514 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
4515 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4516 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
4518 hi->reg_offset = lo->reg_offset;
4519 lo->reg = FP0_REGNUM + 0;
4520 hi->reg = FP0_REGNUM + 1;
4526 /* The floating point value fits in a single floating-point
4528 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4529 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
4532 lo->reg = FP0_REGNUM;
4543 /* Locate a result possibly spread across two registers. */
4545 lo->reg = regnum + 0;
4546 hi->reg = regnum + 1;
4547 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4548 && len < MIPS_SAVED_REGSIZE)
4550 /* "un-left-justify" the value in the low register */
4551 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
4556 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4557 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
4558 && len < MIPS_SAVED_REGSIZE * 2
4559 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
4560 TYPE_CODE (valtype) == TYPE_CODE_UNION))
4562 /* "un-left-justify" the value spread across two registers. */
4563 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
4564 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
4566 hi->len = len - lo->len;
4570 /* Only perform a partial copy of the second register. */
4573 if (len > MIPS_SAVED_REGSIZE)
4575 lo->len = MIPS_SAVED_REGSIZE;
4576 hi->len = len - MIPS_SAVED_REGSIZE;
4584 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4585 && REGISTER_RAW_SIZE (regnum) == 8
4586 && MIPS_SAVED_REGSIZE == 4)
4588 /* Account for the fact that only the least-signficant part
4589 of the register is being used */
4590 lo->reg_offset += 4;
4591 hi->reg_offset += 4;
4594 hi->buf_offset = lo->len;
4598 /* Given a return value in `regbuf' with a type `valtype', extract and
4599 copy its value into `valbuf'. */
4602 mips_eabi_extract_return_value (struct type *valtype,
4606 struct return_value_word lo;
4607 struct return_value_word hi;
4608 return_value_location (valtype, &hi, &lo);
4610 memcpy (valbuf + lo.buf_offset,
4611 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4615 memcpy (valbuf + hi.buf_offset,
4616 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4621 mips_o64_extract_return_value (struct type *valtype,
4625 struct return_value_word lo;
4626 struct return_value_word hi;
4627 return_value_location (valtype, &hi, &lo);
4629 memcpy (valbuf + lo.buf_offset,
4630 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4634 memcpy (valbuf + hi.buf_offset,
4635 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4639 /* Given a return value in `valbuf' with a type `valtype', write it's
4640 value into the appropriate register. */
4643 mips_eabi_store_return_value (struct type *valtype, char *valbuf)
4645 char raw_buffer[MAX_REGISTER_SIZE];
4646 struct return_value_word lo;
4647 struct return_value_word hi;
4648 return_value_location (valtype, &hi, &lo);
4650 memset (raw_buffer, 0, sizeof (raw_buffer));
4651 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4652 deprecated_write_register_bytes (REGISTER_BYTE (lo.reg), raw_buffer,
4653 REGISTER_RAW_SIZE (lo.reg));
4657 memset (raw_buffer, 0, sizeof (raw_buffer));
4658 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4659 deprecated_write_register_bytes (REGISTER_BYTE (hi.reg), raw_buffer,
4660 REGISTER_RAW_SIZE (hi.reg));
4665 mips_o64_store_return_value (struct type *valtype, char *valbuf)
4667 char raw_buffer[MAX_REGISTER_SIZE];
4668 struct return_value_word lo;
4669 struct return_value_word hi;
4670 return_value_location (valtype, &hi, &lo);
4672 memset (raw_buffer, 0, sizeof (raw_buffer));
4673 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4674 deprecated_write_register_bytes (REGISTER_BYTE (lo.reg), raw_buffer,
4675 REGISTER_RAW_SIZE (lo.reg));
4679 memset (raw_buffer, 0, sizeof (raw_buffer));
4680 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4681 deprecated_write_register_bytes (REGISTER_BYTE (hi.reg), raw_buffer,
4682 REGISTER_RAW_SIZE (hi.reg));
4686 /* O32 ABI stuff. */
4689 mips_o32_xfer_return_value (struct type *type,
4690 struct regcache *regcache,
4691 bfd_byte *in, const bfd_byte *out)
4693 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4694 if (TYPE_CODE (type) == TYPE_CODE_FLT
4695 && TYPE_LENGTH (type) == 4
4696 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4698 /* A single-precision floating-point value. It fits in the
4699 least significant part of FP0. */
4701 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4702 mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type),
4703 TARGET_BYTE_ORDER, in, out, 0);
4705 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4706 && TYPE_LENGTH (type) == 8
4707 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4709 /* A double-precision floating-point value. It fits in the
4710 least significant part of FP0/FP1 but with byte ordering
4711 based on the target (???). */
4713 fprintf_unfiltered (gdb_stderr, "Return float in $fp0/$fp1\n");
4714 switch (TARGET_BYTE_ORDER)
4716 case BFD_ENDIAN_LITTLE:
4717 mips_xfer_register (regcache, FP0_REGNUM + 0, 4,
4718 TARGET_BYTE_ORDER, in, out, 0);
4719 mips_xfer_register (regcache, FP0_REGNUM + 1, 4,
4720 TARGET_BYTE_ORDER, in, out, 4);
4722 case BFD_ENDIAN_BIG:
4723 mips_xfer_register (regcache, FP0_REGNUM + 1, 4,
4724 TARGET_BYTE_ORDER, in, out, 0);
4725 mips_xfer_register (regcache, FP0_REGNUM + 0, 4,
4726 TARGET_BYTE_ORDER, in, out, 4);
4729 internal_error (__FILE__, __LINE__, "bad switch");
4733 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4734 && TYPE_NFIELDS (type) <= 2
4735 && TYPE_NFIELDS (type) >= 1
4736 && ((TYPE_NFIELDS (type) == 1
4737 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4739 || (TYPE_NFIELDS (type) == 2
4740 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4742 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4744 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4746 /* A struct that contains one or two floats. Each value is part
4747 in the least significant part of their floating point
4749 bfd_byte reg[MAX_REGISTER_SIZE];
4752 for (field = 0, regnum = FP0_REGNUM;
4753 field < TYPE_NFIELDS (type);
4754 field++, regnum += 2)
4756 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4759 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4760 mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4761 TARGET_BYTE_ORDER, in, out, offset);
4766 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4767 || TYPE_CODE (type) == TYPE_CODE_UNION)
4769 /* A structure or union. Extract the left justified value,
4770 regardless of the byte order. I.e. DO NOT USE
4774 for (offset = 0, regnum = V0_REGNUM;
4775 offset < TYPE_LENGTH (type);
4776 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4778 int xfer = REGISTER_RAW_SIZE (regnum);
4779 if (offset + xfer > TYPE_LENGTH (type))
4780 xfer = TYPE_LENGTH (type) - offset;
4782 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4783 offset, xfer, regnum);
4784 mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN,
4791 /* A scalar extract each part but least-significant-byte
4792 justified. o32 thinks registers are 4 byte, regardless of
4793 the ISA. mips_stack_argsize controls this. */
4796 for (offset = 0, regnum = V0_REGNUM;
4797 offset < TYPE_LENGTH (type);
4798 offset += mips_stack_argsize (), regnum++)
4800 int xfer = mips_stack_argsize ();
4802 if (offset + xfer > TYPE_LENGTH (type))
4803 xfer = TYPE_LENGTH (type) - offset;
4805 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4806 offset, xfer, regnum);
4807 mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER,
4814 mips_o32_extract_return_value (struct type *type,
4815 struct regcache *regcache,
4818 mips_o32_xfer_return_value (type, regcache, valbuf, NULL);
4822 mips_o32_store_return_value (struct type *type, char *valbuf)
4824 mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf);
4827 /* N32/N44 ABI stuff. */
4830 mips_n32n64_xfer_return_value (struct type *type,
4831 struct regcache *regcache,
4832 bfd_byte *in, const bfd_byte *out)
4834 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4835 if (TYPE_CODE (type) == TYPE_CODE_FLT
4836 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4838 /* A floating-point value belongs in the least significant part
4841 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4842 mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type),
4843 TARGET_BYTE_ORDER, in, out, 0);
4845 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4846 && TYPE_NFIELDS (type) <= 2
4847 && TYPE_NFIELDS (type) >= 1
4848 && ((TYPE_NFIELDS (type) == 1
4849 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4851 || (TYPE_NFIELDS (type) == 2
4852 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4854 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4856 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4858 /* A struct that contains one or two floats. Each value is part
4859 in the least significant part of their floating point
4861 bfd_byte reg[MAX_REGISTER_SIZE];
4864 for (field = 0, regnum = FP0_REGNUM;
4865 field < TYPE_NFIELDS (type);
4866 field++, regnum += 2)
4868 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4871 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4872 mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4873 TARGET_BYTE_ORDER, in, out, offset);
4876 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4877 || TYPE_CODE (type) == TYPE_CODE_UNION)
4879 /* A structure or union. Extract the left justified value,
4880 regardless of the byte order. I.e. DO NOT USE
4884 for (offset = 0, regnum = V0_REGNUM;
4885 offset < TYPE_LENGTH (type);
4886 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4888 int xfer = REGISTER_RAW_SIZE (regnum);
4889 if (offset + xfer > TYPE_LENGTH (type))
4890 xfer = TYPE_LENGTH (type) - offset;
4892 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4893 offset, xfer, regnum);
4894 mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN,
4900 /* A scalar extract each part but least-significant-byte
4904 for (offset = 0, regnum = V0_REGNUM;
4905 offset < TYPE_LENGTH (type);
4906 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4908 int xfer = REGISTER_RAW_SIZE (regnum);
4910 if (offset + xfer > TYPE_LENGTH (type))
4911 xfer = TYPE_LENGTH (type) - offset;
4913 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4914 offset, xfer, regnum);
4915 mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER,
4922 mips_n32n64_extract_return_value (struct type *type,
4923 struct regcache *regcache,
4926 mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL);
4930 mips_n32n64_store_return_value (struct type *type, char *valbuf)
4932 mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf);
4936 mips_extract_struct_value_address (struct regcache *regcache)
4938 /* FIXME: This will only work at random. The caller passes the
4939 struct_return address in V0, but it is not preserved. It may
4940 still be there, or this may be a random value. */
4943 regcache_cooked_read_signed (regcache, V0_REGNUM, &val);
4947 /* Exported procedure: Is PC in the signal trampoline code */
4950 mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore)
4952 if (sigtramp_address == 0)
4954 return (pc >= sigtramp_address && pc < sigtramp_end);
4957 /* Root of all "set mips "/"show mips " commands. This will eventually be
4958 used for all MIPS-specific commands. */
4961 show_mips_command (char *args, int from_tty)
4963 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4967 set_mips_command (char *args, int from_tty)
4969 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4970 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4973 /* Commands to show/set the MIPS FPU type. */
4976 show_mipsfpu_command (char *args, int from_tty)
4979 switch (MIPS_FPU_TYPE)
4981 case MIPS_FPU_SINGLE:
4982 fpu = "single-precision";
4984 case MIPS_FPU_DOUBLE:
4985 fpu = "double-precision";
4988 fpu = "absent (none)";
4991 internal_error (__FILE__, __LINE__, "bad switch");
4993 if (mips_fpu_type_auto)
4994 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4997 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5003 set_mipsfpu_command (char *args, int from_tty)
5005 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5006 show_mipsfpu_command (args, from_tty);
5010 set_mipsfpu_single_command (char *args, int from_tty)
5012 mips_fpu_type = MIPS_FPU_SINGLE;
5013 mips_fpu_type_auto = 0;
5014 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
5018 set_mipsfpu_double_command (char *args, int from_tty)
5020 mips_fpu_type = MIPS_FPU_DOUBLE;
5021 mips_fpu_type_auto = 0;
5022 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
5026 set_mipsfpu_none_command (char *args, int from_tty)
5028 mips_fpu_type = MIPS_FPU_NONE;
5029 mips_fpu_type_auto = 0;
5030 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
5034 set_mipsfpu_auto_command (char *args, int from_tty)
5036 mips_fpu_type_auto = 1;
5039 /* Command to set the processor type. */
5042 mips_set_processor_type_command (char *args, int from_tty)
5046 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
5048 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5049 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5050 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
5052 /* Restore the value. */
5053 tmp_mips_processor_type = xstrdup (mips_processor_type);
5058 if (!mips_set_processor_type (tmp_mips_processor_type))
5060 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
5061 /* Restore its value. */
5062 tmp_mips_processor_type = xstrdup (mips_processor_type);
5067 mips_show_processor_type_command (char *args, int from_tty)
5071 /* Modify the actual processor type. */
5074 mips_set_processor_type (char *str)
5081 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5083 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
5085 mips_processor_type = str;
5086 mips_processor_reg_names = mips_processor_type_table[i].regnames;
5088 /* FIXME tweak fpu flag too */
5095 /* Attempt to identify the particular processor model by reading the
5099 mips_read_processor_type (void)
5103 prid = read_register (PRID_REGNUM);
5105 if ((prid & ~0xf) == 0x700)
5106 return savestring ("r3041", strlen ("r3041"));
5111 /* Just like reinit_frame_cache, but with the right arguments to be
5112 callable as an sfunc. */
5115 reinit_frame_cache_sfunc (char *args, int from_tty,
5116 struct cmd_list_element *c)
5118 reinit_frame_cache ();
5122 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
5124 mips_extra_func_info_t proc_desc;
5126 /* Search for the function containing this address. Set the low bit
5127 of the address when searching, in case we were given an even address
5128 that is the start of a 16-bit function. If we didn't do this,
5129 the search would fail because the symbol table says the function
5130 starts at an odd address, i.e. 1 byte past the given address. */
5131 memaddr = ADDR_BITS_REMOVE (memaddr);
5132 proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL);
5134 /* Make an attempt to determine if this is a 16-bit function. If
5135 the procedure descriptor exists and the address therein is odd,
5136 it's definitely a 16-bit function. Otherwise, we have to just
5137 guess that if the address passed in is odd, it's 16-bits. */
5139 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
5140 bfd_mach_mips16 : 0;
5142 info->mach = pc_is_mips16 (memaddr) ?
5143 bfd_mach_mips16 : 0;
5145 /* Round down the instruction address to the appropriate boundary. */
5146 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
5148 /* Call the appropriate disassembler based on the target endian-ness. */
5149 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5150 return print_insn_big_mips (memaddr, info);
5152 return print_insn_little_mips (memaddr, info);
5155 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5156 counter value to determine whether a 16- or 32-bit breakpoint should be
5157 used. It returns a pointer to a string of bytes that encode a breakpoint
5158 instruction, stores the length of the string to *lenptr, and adjusts pc
5159 (if necessary) to point to the actual memory location where the
5160 breakpoint should be inserted. */
5162 static const unsigned char *
5163 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
5165 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5167 if (pc_is_mips16 (*pcptr))
5169 static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5};
5170 *pcptr = unmake_mips16_addr (*pcptr);
5171 *lenptr = sizeof (mips16_big_breakpoint);
5172 return mips16_big_breakpoint;
5176 /* The IDT board uses an unusual breakpoint value, and
5177 sometimes gets confused when it sees the usual MIPS
5178 breakpoint instruction. */
5179 static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd};
5180 static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd};
5181 static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd};
5183 *lenptr = sizeof (big_breakpoint);
5185 if (strcmp (target_shortname, "mips") == 0)
5186 return idt_big_breakpoint;
5187 else if (strcmp (target_shortname, "ddb") == 0
5188 || strcmp (target_shortname, "pmon") == 0
5189 || strcmp (target_shortname, "lsi") == 0)
5190 return pmon_big_breakpoint;
5192 return big_breakpoint;
5197 if (pc_is_mips16 (*pcptr))
5199 static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8};
5200 *pcptr = unmake_mips16_addr (*pcptr);
5201 *lenptr = sizeof (mips16_little_breakpoint);
5202 return mips16_little_breakpoint;
5206 static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0};
5207 static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0};
5208 static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0};
5210 *lenptr = sizeof (little_breakpoint);
5212 if (strcmp (target_shortname, "mips") == 0)
5213 return idt_little_breakpoint;
5214 else if (strcmp (target_shortname, "ddb") == 0
5215 || strcmp (target_shortname, "pmon") == 0
5216 || strcmp (target_shortname, "lsi") == 0)
5217 return pmon_little_breakpoint;
5219 return little_breakpoint;
5224 /* If PC is in a mips16 call or return stub, return the address of the target
5225 PC, which is either the callee or the caller. There are several
5226 cases which must be handled:
5228 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5229 target PC is in $31 ($ra).
5230 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5231 and the target PC is in $2.
5232 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5233 before the jal instruction, this is effectively a call stub
5234 and the the target PC is in $2. Otherwise this is effectively
5235 a return stub and the target PC is in $18.
5237 See the source code for the stubs in gcc/config/mips/mips16.S for
5240 This function implements the SKIP_TRAMPOLINE_CODE macro.
5244 mips_skip_stub (CORE_ADDR pc)
5247 CORE_ADDR start_addr;
5249 /* Find the starting address and name of the function containing the PC. */
5250 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5253 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5254 target PC is in $31 ($ra). */
5255 if (strcmp (name, "__mips16_ret_sf") == 0
5256 || strcmp (name, "__mips16_ret_df") == 0)
5257 return read_signed_register (RA_REGNUM);
5259 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5261 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5262 and the target PC is in $2. */
5263 if (name[19] >= '0' && name[19] <= '9')
5264 return read_signed_register (2);
5266 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5267 before the jal instruction, this is effectively a call stub
5268 and the the target PC is in $2. Otherwise this is effectively
5269 a return stub and the target PC is in $18. */
5270 else if (name[19] == 's' || name[19] == 'd')
5272 if (pc == start_addr)
5274 /* Check if the target of the stub is a compiler-generated
5275 stub. Such a stub for a function bar might have a name
5276 like __fn_stub_bar, and might look like this:
5281 la $1,bar (becomes a lui/addiu pair)
5283 So scan down to the lui/addi and extract the target
5284 address from those two instructions. */
5286 CORE_ADDR target_pc = read_signed_register (2);
5290 /* See if the name of the target function is __fn_stub_*. */
5291 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
5293 if (strncmp (name, "__fn_stub_", 10) != 0
5294 && strcmp (name, "etext") != 0
5295 && strcmp (name, "_etext") != 0)
5298 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5299 The limit on the search is arbitrarily set to 20
5300 instructions. FIXME. */
5301 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5303 inst = mips_fetch_instruction (target_pc);
5304 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5305 pc = (inst << 16) & 0xffff0000; /* high word */
5306 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5307 return pc | (inst & 0xffff); /* low word */
5310 /* Couldn't find the lui/addui pair, so return stub address. */
5314 /* This is the 'return' part of a call stub. The return
5315 address is in $r18. */
5316 return read_signed_register (18);
5319 return 0; /* not a stub */
5323 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5324 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5327 mips_in_call_stub (CORE_ADDR pc, char *name)
5329 CORE_ADDR start_addr;
5331 /* Find the starting address of the function containing the PC. If the
5332 caller didn't give us a name, look it up at the same time. */
5333 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
5336 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5338 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5339 if (name[19] >= '0' && name[19] <= '9')
5341 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5342 before the jal instruction, this is effectively a call stub. */
5343 else if (name[19] == 's' || name[19] == 'd')
5344 return pc == start_addr;
5347 return 0; /* not a stub */
5351 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5352 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5355 mips_in_return_stub (CORE_ADDR pc, char *name)
5357 CORE_ADDR start_addr;
5359 /* Find the starting address of the function containing the PC. */
5360 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5363 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5364 if (strcmp (name, "__mips16_ret_sf") == 0
5365 || strcmp (name, "__mips16_ret_df") == 0)
5368 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5369 i.e. after the jal instruction, this is effectively a return stub. */
5370 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5371 && (name[19] == 's' || name[19] == 'd')
5372 && pc != start_addr)
5375 return 0; /* not a stub */
5379 /* Return non-zero if the PC is in a library helper function that should
5380 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5383 mips_ignore_helper (CORE_ADDR pc)
5387 /* Find the starting address and name of the function containing the PC. */
5388 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5391 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5392 that we want to ignore. */
5393 return (strcmp (name, "__mips16_ret_sf") == 0
5394 || strcmp (name, "__mips16_ret_df") == 0);
5398 /* Return a location where we can set a breakpoint that will be hit
5399 when an inferior function call returns. This is normally the
5400 program's entry point. Executables that don't have an entry
5401 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
5402 whose address is the location where the breakpoint should be placed. */
5405 mips_call_dummy_address (void)
5407 struct minimal_symbol *sym;
5409 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
5411 return SYMBOL_VALUE_ADDRESS (sym);
5413 return entry_point_address ();
5417 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5418 the register stored on the stack (32) is different to its real raw
5419 size (64). The below ensures that registers are fetched from the
5420 stack using their ABI size and then stored into the RAW_BUFFER
5421 using their raw size.
5423 The alternative to adding this function would be to add an ABI
5424 macro - REGISTER_STACK_SIZE(). */
5427 mips_get_saved_register (char *raw_buffer,
5430 struct frame_info *frame,
5432 enum lval_type *lvalp)
5435 enum lval_type lvalx;
5438 if (!target_has_registers)
5439 error ("No registers.");
5441 /* Make certain that all needed parameters are present. */
5446 if (optimizedp == NULL)
5447 optimizedp = &optimizedx;
5448 generic_unwind_get_saved_register (raw_buffer, optimizedp, addrp, frame,
5450 /* FIXME: cagney/2002-09-13: This is just so bad. The MIPS should
5451 have a pseudo register range that correspons to the ABI's, rather
5452 than the ISA's, view of registers. These registers would then
5453 implicitly describe their size and hence could be used without
5454 the below munging. */
5455 if ((*lvalp) == lval_memory)
5457 if (raw_buffer != NULL)
5461 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
5463 LONGEST val = read_memory_integer ((*addrp), MIPS_SAVED_REGSIZE);
5464 store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
5470 /* Immediately after a function call, return the saved pc.
5471 Can't always go through the frames for this because on some machines
5472 the new frame is not set up until the new function executes
5473 some instructions. */
5476 mips_saved_pc_after_call (struct frame_info *frame)
5478 return read_signed_register (RA_REGNUM);
5482 /* Convert a dbx stab register number (from `r' declaration) to a gdb
5486 mips_stab_reg_to_regnum (int num)
5488 if (num >= 0 && num < 32)
5490 else if (num >= 38 && num < 70)
5491 return num + FP0_REGNUM - 38;
5498 /* This will hopefully (eventually) provoke a warning. Should
5499 we be calling complaint() here? */
5500 return NUM_REGS + NUM_PSEUDO_REGS;
5505 /* Convert a dwarf, dwarf2, or ecoff register number to a gdb REGNUM */
5508 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
5510 if (num >= 0 && num < 32)
5512 else if (num >= 32 && num < 64)
5513 return num + FP0_REGNUM - 32;
5520 /* This will hopefully (eventually) provoke a warning. Should
5521 we be calling complaint() here? */
5522 return NUM_REGS + NUM_PSEUDO_REGS;
5527 /* Convert an integer into an address. By first converting the value
5528 into a pointer and then extracting it signed, the address is
5529 guarenteed to be correctly sign extended. */
5532 mips_integer_to_address (struct type *type, void *buf)
5534 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5535 LONGEST val = unpack_long (type, buf);
5536 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5537 return extract_signed_integer (tmp,
5538 TYPE_LENGTH (builtin_type_void_data_ptr));
5542 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5544 enum mips_abi *abip = (enum mips_abi *) obj;
5545 const char *name = bfd_get_section_name (abfd, sect);
5547 if (*abip != MIPS_ABI_UNKNOWN)
5550 if (strncmp (name, ".mdebug.", 8) != 0)
5553 if (strcmp (name, ".mdebug.abi32") == 0)
5554 *abip = MIPS_ABI_O32;
5555 else if (strcmp (name, ".mdebug.abiN32") == 0)
5556 *abip = MIPS_ABI_N32;
5557 else if (strcmp (name, ".mdebug.abi64") == 0)
5558 *abip = MIPS_ABI_N64;
5559 else if (strcmp (name, ".mdebug.abiO64") == 0)
5560 *abip = MIPS_ABI_O64;
5561 else if (strcmp (name, ".mdebug.eabi32") == 0)
5562 *abip = MIPS_ABI_EABI32;
5563 else if (strcmp (name, ".mdebug.eabi64") == 0)
5564 *abip = MIPS_ABI_EABI64;
5566 warning ("unsupported ABI %s.", name + 8);
5569 static enum mips_abi
5570 global_mips_abi (void)
5574 for (i = 0; mips_abi_strings[i] != NULL; i++)
5575 if (mips_abi_strings[i] == mips_abi_string)
5576 return (enum mips_abi) i;
5578 internal_error (__FILE__, __LINE__,
5579 "unknown ABI string");
5582 static struct gdbarch *
5583 mips_gdbarch_init (struct gdbarch_info info,
5584 struct gdbarch_list *arches)
5586 struct gdbarch *gdbarch;
5587 struct gdbarch_tdep *tdep;
5589 enum mips_abi mips_abi, found_abi, wanted_abi;
5591 /* Reset the disassembly info, in case it was set to something
5593 deprecated_tm_print_insn_info.flavour = bfd_target_unknown_flavour;
5594 deprecated_tm_print_insn_info.arch = bfd_arch_unknown;
5595 deprecated_tm_print_insn_info.mach = 0;
5601 /* First of all, extract the elf_flags, if available. */
5602 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5603 elf_flags = elf_elfheader (info.abfd)->e_flags;
5606 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5607 switch ((elf_flags & EF_MIPS_ABI))
5609 case E_MIPS_ABI_O32:
5610 mips_abi = MIPS_ABI_O32;
5612 case E_MIPS_ABI_O64:
5613 mips_abi = MIPS_ABI_O64;
5615 case E_MIPS_ABI_EABI32:
5616 mips_abi = MIPS_ABI_EABI32;
5618 case E_MIPS_ABI_EABI64:
5619 mips_abi = MIPS_ABI_EABI64;
5622 if ((elf_flags & EF_MIPS_ABI2))
5623 mips_abi = MIPS_ABI_N32;
5625 mips_abi = MIPS_ABI_UNKNOWN;
5629 /* GCC creates a pseudo-section whose name describes the ABI. */
5630 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5631 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
5633 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5634 Use the ABI from the last architecture if there is one. */
5635 if (info.abfd == NULL && arches != NULL)
5636 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5638 /* Try the architecture for any hint of the correct ABI. */
5639 if (mips_abi == MIPS_ABI_UNKNOWN
5640 && info.bfd_arch_info != NULL
5641 && info.bfd_arch_info->arch == bfd_arch_mips)
5643 switch (info.bfd_arch_info->mach)
5645 case bfd_mach_mips3900:
5646 mips_abi = MIPS_ABI_EABI32;
5648 case bfd_mach_mips4100:
5649 case bfd_mach_mips5000:
5650 mips_abi = MIPS_ABI_EABI64;
5652 case bfd_mach_mips8000:
5653 case bfd_mach_mips10000:
5654 /* On Irix, ELF64 executables use the N64 ABI. The
5655 pseudo-sections which describe the ABI aren't present
5656 on IRIX. (Even for executables created by gcc.) */
5657 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5658 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5659 mips_abi = MIPS_ABI_N64;
5661 mips_abi = MIPS_ABI_N32;
5666 if (mips_abi == MIPS_ABI_UNKNOWN)
5667 mips_abi = MIPS_ABI_O32;
5669 /* Now that we have found what the ABI for this binary would be,
5670 check whether the user is overriding it. */
5671 found_abi = mips_abi;
5672 wanted_abi = global_mips_abi ();
5673 if (wanted_abi != MIPS_ABI_UNKNOWN)
5674 mips_abi = wanted_abi;
5676 /* We have to set deprecated_tm_print_insn_info before looking for a
5677 pre-existing architecture, otherwise we may return before we get
5678 a chance to set it up. */
5679 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
5681 /* Set up the disassembler info, so that we get the right
5682 register names from libopcodes. */
5683 if (mips_abi == MIPS_ABI_N32)
5684 deprecated_tm_print_insn_info.disassembler_options = "gpr-names=n32";
5686 deprecated_tm_print_insn_info.disassembler_options = "gpr-names=64";
5687 deprecated_tm_print_insn_info.flavour = bfd_target_elf_flavour;
5688 deprecated_tm_print_insn_info.arch = bfd_arch_mips;
5689 if (info.bfd_arch_info != NULL
5690 && info.bfd_arch_info->arch == bfd_arch_mips
5691 && info.bfd_arch_info->mach)
5692 deprecated_tm_print_insn_info.mach = info.bfd_arch_info->mach;
5694 deprecated_tm_print_insn_info.mach = bfd_mach_mips8000;
5697 /* This string is not recognized explicitly by the disassembler,
5698 but it tells the disassembler to not try to guess the ABI from
5699 the bfd elf headers, such that, if the user overrides the ABI
5700 of a program linked as NewABI, the disassembly will follow the
5701 register naming conventions specified by the user. */
5702 deprecated_tm_print_insn_info.disassembler_options = "gpr-names=32";
5706 fprintf_unfiltered (gdb_stdlog,
5707 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5709 fprintf_unfiltered (gdb_stdlog,
5710 "mips_gdbarch_init: mips_abi = %d\n",
5712 fprintf_unfiltered (gdb_stdlog,
5713 "mips_gdbarch_init: found_mips_abi = %d\n",
5717 /* try to find a pre-existing architecture */
5718 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5720 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5722 /* MIPS needs to be pedantic about which ABI the object is
5724 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5726 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5728 return arches->gdbarch;
5731 /* Need a new architecture. Fill in a target specific vector. */
5732 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5733 gdbarch = gdbarch_alloc (&info, tdep);
5734 tdep->elf_flags = elf_flags;
5736 /* Initially set everything according to the default ABI/ISA. */
5737 set_gdbarch_short_bit (gdbarch, 16);
5738 set_gdbarch_int_bit (gdbarch, 32);
5739 set_gdbarch_float_bit (gdbarch, 32);
5740 set_gdbarch_double_bit (gdbarch, 64);
5741 set_gdbarch_long_double_bit (gdbarch, 64);
5742 set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size);
5743 tdep->found_abi = found_abi;
5744 tdep->mips_abi = mips_abi;
5746 set_gdbarch_elf_make_msymbol_special (gdbarch,
5747 mips_elf_make_msymbol_special);
5749 if (info.osabi == GDB_OSABI_IRIX)
5750 set_gdbarch_num_regs (gdbarch, 71);
5752 set_gdbarch_num_regs (gdbarch, 90);
5757 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5758 set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value);
5759 set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value);
5760 tdep->mips_default_saved_regsize = 4;
5761 tdep->mips_default_stack_argsize = 4;
5762 tdep->mips_fp_register_double = 0;
5763 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5764 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5765 tdep->gdb_target_is_mips64 = 0;
5766 tdep->default_mask_address_p = 0;
5767 set_gdbarch_long_bit (gdbarch, 32);
5768 set_gdbarch_ptr_bit (gdbarch, 32);
5769 set_gdbarch_long_long_bit (gdbarch, 64);
5770 set_gdbarch_reg_struct_has_addr (gdbarch,
5771 mips_o32_reg_struct_has_addr);
5772 set_gdbarch_use_struct_convention (gdbarch,
5773 mips_o32_use_struct_convention);
5776 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5777 set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value);
5778 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value);
5779 tdep->mips_default_saved_regsize = 8;
5780 tdep->mips_default_stack_argsize = 8;
5781 tdep->mips_fp_register_double = 1;
5782 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5783 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5784 tdep->gdb_target_is_mips64 = 1;
5785 tdep->default_mask_address_p = 0;
5786 set_gdbarch_long_bit (gdbarch, 32);
5787 set_gdbarch_ptr_bit (gdbarch, 32);
5788 set_gdbarch_long_long_bit (gdbarch, 64);
5789 set_gdbarch_reg_struct_has_addr (gdbarch,
5790 mips_o32_reg_struct_has_addr);
5791 set_gdbarch_use_struct_convention (gdbarch,
5792 mips_o32_use_struct_convention);
5794 case MIPS_ABI_EABI32:
5795 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5796 set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
5797 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5798 tdep->mips_default_saved_regsize = 4;
5799 tdep->mips_default_stack_argsize = 4;
5800 tdep->mips_fp_register_double = 0;
5801 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5802 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5803 tdep->gdb_target_is_mips64 = 0;
5804 tdep->default_mask_address_p = 0;
5805 set_gdbarch_long_bit (gdbarch, 32);
5806 set_gdbarch_ptr_bit (gdbarch, 32);
5807 set_gdbarch_long_long_bit (gdbarch, 64);
5808 set_gdbarch_reg_struct_has_addr (gdbarch,
5809 mips_eabi_reg_struct_has_addr);
5810 set_gdbarch_use_struct_convention (gdbarch,
5811 mips_eabi_use_struct_convention);
5813 case MIPS_ABI_EABI64:
5814 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5815 set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
5816 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5817 tdep->mips_default_saved_regsize = 8;
5818 tdep->mips_default_stack_argsize = 8;
5819 tdep->mips_fp_register_double = 1;
5820 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5821 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5822 tdep->gdb_target_is_mips64 = 1;
5823 tdep->default_mask_address_p = 0;
5824 set_gdbarch_long_bit (gdbarch, 64);
5825 set_gdbarch_ptr_bit (gdbarch, 64);
5826 set_gdbarch_long_long_bit (gdbarch, 64);
5827 set_gdbarch_reg_struct_has_addr (gdbarch,
5828 mips_eabi_reg_struct_has_addr);
5829 set_gdbarch_use_struct_convention (gdbarch,
5830 mips_eabi_use_struct_convention);
5833 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5834 set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value);
5835 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5836 tdep->mips_default_saved_regsize = 8;
5837 tdep->mips_default_stack_argsize = 8;
5838 tdep->mips_fp_register_double = 1;
5839 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5840 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5841 tdep->gdb_target_is_mips64 = 1;
5842 tdep->default_mask_address_p = 0;
5843 set_gdbarch_long_bit (gdbarch, 32);
5844 set_gdbarch_ptr_bit (gdbarch, 32);
5845 set_gdbarch_long_long_bit (gdbarch, 64);
5846 set_gdbarch_use_struct_convention (gdbarch,
5847 mips_n32n64_use_struct_convention);
5848 set_gdbarch_reg_struct_has_addr (gdbarch,
5849 mips_n32n64_reg_struct_has_addr);
5852 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5853 set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value);
5854 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5855 tdep->mips_default_saved_regsize = 8;
5856 tdep->mips_default_stack_argsize = 8;
5857 tdep->mips_fp_register_double = 1;
5858 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5859 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5860 tdep->gdb_target_is_mips64 = 1;
5861 tdep->default_mask_address_p = 0;
5862 set_gdbarch_long_bit (gdbarch, 64);
5863 set_gdbarch_ptr_bit (gdbarch, 64);
5864 set_gdbarch_long_long_bit (gdbarch, 64);
5865 set_gdbarch_use_struct_convention (gdbarch,
5866 mips_n32n64_use_struct_convention);
5867 set_gdbarch_reg_struct_has_addr (gdbarch,
5868 mips_n32n64_reg_struct_has_addr);
5871 internal_error (__FILE__, __LINE__,
5872 "unknown ABI in switch");
5875 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5876 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5879 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5880 flag in object files because to do so would make it impossible to
5881 link with libraries compiled without "-gp32". This is
5882 unnecessarily restrictive.
5884 We could solve this problem by adding "-gp32" multilibs to gcc,
5885 but to set this flag before gcc is built with such multilibs will
5886 break too many systems.''
5888 But even more unhelpfully, the default linker output target for
5889 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5890 for 64-bit programs - you need to change the ABI to change this,
5891 and not all gcc targets support that currently. Therefore using
5892 this flag to detect 32-bit mode would do the wrong thing given
5893 the current gcc - it would make GDB treat these 64-bit programs
5894 as 32-bit programs by default. */
5896 /* enable/disable the MIPS FPU */
5897 if (!mips_fpu_type_auto)
5898 tdep->mips_fpu_type = mips_fpu_type;
5899 else if (info.bfd_arch_info != NULL
5900 && info.bfd_arch_info->arch == bfd_arch_mips)
5901 switch (info.bfd_arch_info->mach)
5903 case bfd_mach_mips3900:
5904 case bfd_mach_mips4100:
5905 case bfd_mach_mips4111:
5906 tdep->mips_fpu_type = MIPS_FPU_NONE;
5908 case bfd_mach_mips4650:
5909 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
5912 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5916 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5918 /* MIPS version of register names. NOTE: At present the MIPS
5919 register name management is part way between the old -
5920 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5921 Further work on it is required. */
5922 /* NOTE: many targets (esp. embedded) do not go thru the
5923 gdbarch_register_name vector at all, instead bypassing it
5924 by defining REGISTER_NAMES. */
5925 set_gdbarch_register_name (gdbarch, mips_register_name);
5926 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5927 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
5928 set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */
5929 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5930 set_gdbarch_deprecated_dummy_write_sp (gdbarch, generic_target_write_sp);
5932 /* Add/remove bits from an address. The MIPS needs be careful to
5933 ensure that all 32 bit addresses are sign extended to 64 bits. */
5934 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5936 /* There's a mess in stack frame creation. See comments in
5937 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
5938 set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
5939 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_noop);
5941 /* Map debug register numbers onto internal register numbers. */
5942 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5943 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5944 set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5945 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5947 /* Initialize a frame */
5948 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs);
5949 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
5951 /* MIPS version of CALL_DUMMY */
5953 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
5954 set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame);
5955 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5956 set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
5957 set_gdbarch_register_convertible (gdbarch, mips_register_convertible);
5958 set_gdbarch_register_convert_to_virtual (gdbarch,
5959 mips_register_convert_to_virtual);
5960 set_gdbarch_register_convert_to_raw (gdbarch,
5961 mips_register_convert_to_raw);
5963 set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain);
5964 set_gdbarch_frameless_function_invocation (gdbarch,
5965 generic_frameless_function_invocation_not);
5966 set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc);
5967 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
5968 set_gdbarch_frame_args_skip (gdbarch, 0);
5970 set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register);
5972 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5973 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5974 set_gdbarch_decr_pc_after_break (gdbarch, 0);
5976 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5977 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
5979 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5980 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5981 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5983 set_gdbarch_function_start_offset (gdbarch, 0);
5985 /* There are MIPS targets which do not yet use this since they still
5986 define REGISTER_VIRTUAL_TYPE. */
5987 set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type);
5989 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5990 set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp);
5992 /* Hook in OS ABI-specific overrides, if they have been registered. */
5993 gdbarch_init_osabi (info, gdbarch);
5995 set_gdbarch_extract_struct_value_address (gdbarch,
5996 mips_extract_struct_value_address);
5998 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
6000 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
6001 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
6007 mips_abi_update (char *ignore_args, int from_tty,
6008 struct cmd_list_element *c)
6010 struct gdbarch_info info;
6012 /* Force the architecture to update, and (if it's a MIPS architecture)
6013 mips_gdbarch_init will take care of the rest. */
6014 gdbarch_info_init (&info);
6015 gdbarch_update_p (info);
6018 /* Print out which MIPS ABI is in use. */
6021 show_mips_abi (char *ignore_args, int from_tty)
6023 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
6025 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6028 enum mips_abi global_abi = global_mips_abi ();
6029 enum mips_abi actual_abi = mips_abi (current_gdbarch);
6030 const char *actual_abi_str = mips_abi_strings[actual_abi];
6032 if (global_abi == MIPS_ABI_UNKNOWN)
6033 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6035 else if (global_abi == actual_abi)
6037 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6041 /* Probably shouldn't happen... */
6043 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6045 mips_abi_strings[global_abi]);
6051 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
6053 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
6057 int ef_mips_32bitmode;
6058 /* determine the ISA */
6059 switch (tdep->elf_flags & EF_MIPS_ARCH)
6077 /* determine the size of a pointer */
6078 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6079 fprintf_unfiltered (file,
6080 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6082 fprintf_unfiltered (file,
6083 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6085 fprintf_unfiltered (file,
6086 "mips_dump_tdep: ef_mips_arch = %d\n",
6088 fprintf_unfiltered (file,
6089 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6091 mips_abi_strings[tdep->mips_abi]);
6092 fprintf_unfiltered (file,
6093 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6094 mips_mask_address_p (),
6095 tdep->default_mask_address_p);
6097 fprintf_unfiltered (file,
6098 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6099 FP_REGISTER_DOUBLE);
6100 fprintf_unfiltered (file,
6101 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6102 MIPS_DEFAULT_FPU_TYPE,
6103 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6104 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6105 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6107 fprintf_unfiltered (file,
6108 "mips_dump_tdep: MIPS_EABI = %d\n",
6110 fprintf_unfiltered (file,
6111 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6112 MIPS_LAST_FP_ARG_REGNUM,
6113 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
6114 fprintf_unfiltered (file,
6115 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6117 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
6118 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6119 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6121 fprintf_unfiltered (file,
6122 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6123 MIPS_DEFAULT_SAVED_REGSIZE);
6124 fprintf_unfiltered (file,
6125 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6126 FP_REGISTER_DOUBLE);
6127 fprintf_unfiltered (file,
6128 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6129 MIPS_DEFAULT_STACK_ARGSIZE);
6130 fprintf_unfiltered (file,
6131 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6132 MIPS_STACK_ARGSIZE);
6133 fprintf_unfiltered (file,
6134 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
6136 fprintf_unfiltered (file,
6137 "mips_dump_tdep: A0_REGNUM = %d\n",
6139 fprintf_unfiltered (file,
6140 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6141 XSTRING (ADDR_BITS_REMOVE(ADDR)));
6142 fprintf_unfiltered (file,
6143 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6144 XSTRING (ATTACH_DETACH));
6145 fprintf_unfiltered (file,
6146 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6148 fprintf_unfiltered (file,
6149 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6151 fprintf_unfiltered (file,
6152 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6153 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
6154 fprintf_unfiltered (file,
6155 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6156 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
6157 fprintf_unfiltered (file,
6158 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6160 fprintf_unfiltered (file,
6161 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6163 fprintf_unfiltered (file,
6164 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6165 FIRST_EMBED_REGNUM);
6166 fprintf_unfiltered (file,
6167 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6169 fprintf_unfiltered (file,
6170 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6171 GDB_TARGET_IS_MIPS64);
6172 fprintf_unfiltered (file,
6173 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
6174 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
6175 fprintf_unfiltered (file,
6176 "mips_dump_tdep: HI_REGNUM = %d\n",
6178 fprintf_unfiltered (file,
6179 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6180 XSTRING (IGNORE_HELPER_CALL (PC)));
6181 fprintf_unfiltered (file,
6182 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6183 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
6184 fprintf_unfiltered (file,
6185 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6186 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
6187 fprintf_unfiltered (file,
6188 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6190 fprintf_unfiltered (file,
6191 "mips_dump_tdep: LO_REGNUM = %d\n",
6193 #ifdef MACHINE_CPROC_FP_OFFSET
6194 fprintf_unfiltered (file,
6195 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6196 MACHINE_CPROC_FP_OFFSET);
6198 #ifdef MACHINE_CPROC_PC_OFFSET
6199 fprintf_unfiltered (file,
6200 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6201 MACHINE_CPROC_PC_OFFSET);
6203 #ifdef MACHINE_CPROC_SP_OFFSET
6204 fprintf_unfiltered (file,
6205 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6206 MACHINE_CPROC_SP_OFFSET);
6208 fprintf_unfiltered (file,
6209 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6211 fprintf_unfiltered (file,
6212 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6213 fprintf_unfiltered (file,
6214 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6215 fprintf_unfiltered (file,
6216 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6218 fprintf_unfiltered (file,
6219 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6220 MIPS_LAST_ARG_REGNUM,
6221 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
6222 fprintf_unfiltered (file,
6223 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6225 fprintf_unfiltered (file,
6226 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6227 fprintf_unfiltered (file,
6228 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6229 MIPS_SAVED_REGSIZE);
6230 fprintf_unfiltered (file,
6231 "mips_dump_tdep: OP_LDFPR = used?\n");
6232 fprintf_unfiltered (file,
6233 "mips_dump_tdep: OP_LDGPR = used?\n");
6234 fprintf_unfiltered (file,
6235 "mips_dump_tdep: PRID_REGNUM = %d\n",
6237 fprintf_unfiltered (file,
6238 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
6239 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
6240 fprintf_unfiltered (file,
6241 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6242 fprintf_unfiltered (file,
6243 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6244 fprintf_unfiltered (file,
6245 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6246 fprintf_unfiltered (file,
6247 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6248 fprintf_unfiltered (file,
6249 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6250 fprintf_unfiltered (file,
6251 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6252 fprintf_unfiltered (file,
6253 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6254 fprintf_unfiltered (file,
6255 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6256 fprintf_unfiltered (file,
6257 "mips_dump_tdep: PROC_PC_REG = function?\n");
6258 fprintf_unfiltered (file,
6259 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6260 fprintf_unfiltered (file,
6261 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6262 fprintf_unfiltered (file,
6263 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6264 fprintf_unfiltered (file,
6265 "mips_dump_tdep: PS_REGNUM = %d\n",
6267 fprintf_unfiltered (file,
6268 "mips_dump_tdep: RA_REGNUM = %d\n",
6270 fprintf_unfiltered (file,
6271 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
6272 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
6273 fprintf_unfiltered (file,
6274 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
6275 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
6276 fprintf_unfiltered (file,
6277 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
6278 fprintf_unfiltered (file,
6279 "mips_dump_tdep: ROUND_DOWN = function?\n");
6280 fprintf_unfiltered (file,
6281 "mips_dump_tdep: ROUND_UP = function?\n");
6283 fprintf_unfiltered (file,
6284 "mips_dump_tdep: SAVED_BYTES = %d\n",
6288 fprintf_unfiltered (file,
6289 "mips_dump_tdep: SAVED_FP = %d\n",
6293 fprintf_unfiltered (file,
6294 "mips_dump_tdep: SAVED_PC = %d\n",
6297 fprintf_unfiltered (file,
6298 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6299 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
6300 fprintf_unfiltered (file,
6301 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6302 fprintf_unfiltered (file,
6303 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6305 fprintf_unfiltered (file,
6306 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6307 SIGFRAME_FPREGSAVE_OFF);
6308 fprintf_unfiltered (file,
6309 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6311 fprintf_unfiltered (file,
6312 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6313 SIGFRAME_REGSAVE_OFF);
6314 fprintf_unfiltered (file,
6315 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6317 fprintf_unfiltered (file,
6318 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6319 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
6320 fprintf_unfiltered (file,
6321 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6322 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
6323 fprintf_unfiltered (file,
6324 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6325 SOFTWARE_SINGLE_STEP_P ());
6326 fprintf_unfiltered (file,
6327 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6328 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6329 #ifdef STACK_END_ADDR
6330 fprintf_unfiltered (file,
6331 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6334 fprintf_unfiltered (file,
6335 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6336 XSTRING (STEP_SKIPS_DELAY (PC)));
6337 fprintf_unfiltered (file,
6338 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6339 STEP_SKIPS_DELAY_P);
6340 fprintf_unfiltered (file,
6341 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6342 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6343 fprintf_unfiltered (file,
6344 "mips_dump_tdep: T9_REGNUM = %d\n",
6346 fprintf_unfiltered (file,
6347 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6348 fprintf_unfiltered (file,
6349 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6350 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
6351 fprintf_unfiltered (file,
6352 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6353 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
6355 fprintf_unfiltered (file,
6356 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6357 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6360 fprintf_unfiltered (file,
6361 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6364 #ifdef TRACE_FLAVOR_SIZE
6365 fprintf_unfiltered (file,
6366 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6370 fprintf_unfiltered (file,
6371 "mips_dump_tdep: TRACE_SET # %s\n",
6372 XSTRING (TRACE_SET (X,STATE)));
6374 #ifdef UNUSED_REGNUM
6375 fprintf_unfiltered (file,
6376 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6379 fprintf_unfiltered (file,
6380 "mips_dump_tdep: V0_REGNUM = %d\n",
6382 fprintf_unfiltered (file,
6383 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6384 (long) VM_MIN_ADDRESS);
6386 fprintf_unfiltered (file,
6387 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
6390 fprintf_unfiltered (file,
6391 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6393 fprintf_unfiltered (file,
6394 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6399 _initialize_mips_tdep (void)
6401 static struct cmd_list_element *mipsfpulist = NULL;
6402 struct cmd_list_element *c;
6404 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
6405 if (MIPS_ABI_LAST + 1
6406 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6407 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6409 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6410 if (!deprecated_tm_print_insn) /* Someone may have already set it */
6411 deprecated_tm_print_insn = gdb_print_insn_mips;
6413 /* Add root prefix command for all "set mips"/"show mips" commands */
6414 add_prefix_cmd ("mips", no_class, set_mips_command,
6415 "Various MIPS specific commands.",
6416 &setmipscmdlist, "set mips ", 0, &setlist);
6418 add_prefix_cmd ("mips", no_class, show_mips_command,
6419 "Various MIPS specific commands.",
6420 &showmipscmdlist, "show mips ", 0, &showlist);
6422 /* Allow the user to override the saved register size. */
6423 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6426 &mips_saved_regsize_string, "\
6427 Set size of general purpose registers saved on the stack.\n\
6428 This option can be set to one of:\n\
6429 32 - Force GDB to treat saved GP registers as 32-bit\n\
6430 64 - Force GDB to treat saved GP registers as 64-bit\n\
6431 auto - Allow GDB to use the target's default setting or autodetect the\n\
6432 saved GP register size from information contained in the executable.\n\
6437 /* Allow the user to override the argument stack size. */
6438 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6441 &mips_stack_argsize_string, "\
6442 Set the amount of stack space reserved for each argument.\n\
6443 This option can be set to one of:\n\
6444 32 - Force GDB to allocate 32-bit chunks per argument\n\
6445 64 - Force GDB to allocate 64-bit chunks per argument\n\
6446 auto - Allow GDB to determine the correct setting from the current\n\
6447 target and executable (default)",
6451 /* Allow the user to override the ABI. */
6452 c = add_set_enum_cmd
6453 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6454 "Set the ABI used by this program.\n"
6455 "This option can be set to one of:\n"
6456 " auto - the default ABI associated with the current binary\n"
6464 set_cmd_sfunc (c, mips_abi_update);
6465 add_cmd ("abi", class_obscure, show_mips_abi,
6466 "Show ABI in use by MIPS target", &showmipscmdlist);
6468 /* Let the user turn off floating point and set the fence post for
6469 heuristic_proc_start. */
6471 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6472 "Set use of MIPS floating-point coprocessor.",
6473 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6474 add_cmd ("single", class_support, set_mipsfpu_single_command,
6475 "Select single-precision MIPS floating-point coprocessor.",
6477 add_cmd ("double", class_support, set_mipsfpu_double_command,
6478 "Select double-precision MIPS floating-point coprocessor.",
6480 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6481 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6482 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6483 add_cmd ("none", class_support, set_mipsfpu_none_command,
6484 "Select no MIPS floating-point coprocessor.",
6486 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6487 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6488 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6489 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6490 "Select MIPS floating-point coprocessor automatically.",
6492 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6493 "Show current use of MIPS floating-point coprocessor target.",
6496 /* We really would like to have both "0" and "unlimited" work, but
6497 command.c doesn't deal with that. So make it a var_zinteger
6498 because the user can always use "999999" or some such for unlimited. */
6499 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6500 (char *) &heuristic_fence_post,
6502 Set the distance searched for the start of a function.\n\
6503 If you are debugging a stripped executable, GDB needs to search through the\n\
6504 program for the start of a function. This command sets the distance of the\n\
6505 search. The only need to set it is when debugging a stripped executable.",
6507 /* We need to throw away the frame cache when we set this, since it
6508 might change our ability to get backtraces. */
6509 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
6510 add_show_from_set (c, &showlist);
6512 /* Allow the user to control whether the upper bits of 64-bit
6513 addresses should be zeroed. */
6514 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6515 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6516 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6517 allow GDB to determine the correct value.\n", "\
6518 Show zeroing of upper 32 bits of 64-bit addresses.",
6519 NULL, show_mask_address,
6520 &setmipscmdlist, &showmipscmdlist);
6522 /* Allow the user to control the size of 32 bit registers within the
6523 raw remote packet. */
6524 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6527 (char *)&mips64_transfers_32bit_regs_p, "\
6528 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6529 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6530 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6531 64 bits for others. Use \"off\" to disable compatibility mode",
6535 /* Debug this files internals. */
6536 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6537 &mips_debug, "Set mips debugging.\n\
6538 When non-zero, mips specific debugging is enabled.", &setdebuglist),