1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data *mips_pdr_data;
63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
65 static int mips32_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR);
66 static int micromips_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR,
68 static int mips16_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR,
71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
73 #define ST0_FR (1 << 26)
75 /* The sizes of floating point registers. */
79 MIPS_FPU_SINGLE_REGSIZE = 4,
80 MIPS_FPU_DOUBLE_REGSIZE = 8
89 static const char *mips_abi_string;
91 static const char *const mips_abi_strings[] = {
102 /* For backwards compatibility we default to MIPS16. This flag is
103 overridden as soon as unambiguous ELF file flags tell us the
104 compressed ISA encoding used. */
105 static const char mips_compression_mips16[] = "mips16";
106 static const char mips_compression_micromips[] = "micromips";
107 static const char *const mips_compression_strings[] =
109 mips_compression_mips16,
110 mips_compression_micromips,
114 static const char *mips_compression_string = mips_compression_mips16;
116 /* The standard register names, and all the valid aliases for them. */
117 struct register_alias
123 /* Aliases for o32 and most other ABIs. */
124 const struct register_alias mips_o32_aliases[] = {
131 /* Aliases for n32 and n64. */
132 const struct register_alias mips_n32_n64_aliases[] = {
139 /* Aliases for ABI-independent registers. */
140 const struct register_alias mips_register_aliases[] = {
141 /* The architecture manuals specify these ABI-independent names for
143 #define R(n) { "r" #n, n }
144 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
145 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
146 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
147 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
150 /* k0 and k1 are sometimes called these instead (for "kernel
155 /* This is the traditional GDB name for the CP0 status register. */
156 { "sr", MIPS_PS_REGNUM },
158 /* This is the traditional GDB name for the CP0 BadVAddr register. */
159 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
161 /* This is the traditional GDB name for the FCSR. */
162 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
165 const struct register_alias mips_numeric_register_aliases[] = {
166 #define R(n) { #n, n }
167 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
168 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
169 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
170 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
174 #ifndef MIPS_DEFAULT_FPU_TYPE
175 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
177 static int mips_fpu_type_auto = 1;
178 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
180 static unsigned int mips_debug = 0;
182 /* Properties (for struct target_desc) describing the g/G packet
184 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
185 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
187 struct target_desc *mips_tdesc_gp32;
188 struct target_desc *mips_tdesc_gp64;
190 const struct mips_regnum *
191 mips_regnum (struct gdbarch *gdbarch)
193 return gdbarch_tdep (gdbarch)->regnum;
197 mips_fpa0_regnum (struct gdbarch *gdbarch)
199 return mips_regnum (gdbarch)->fp0 + 12;
202 /* Return 1 if REGNUM refers to a floating-point general register, raw
203 or cooked. Otherwise return 0. */
206 mips_float_register_p (struct gdbarch *gdbarch, int regnum)
208 int rawnum = regnum % gdbarch_num_regs (gdbarch);
210 return (rawnum >= mips_regnum (gdbarch)->fp0
211 && rawnum < mips_regnum (gdbarch)->fp0 + 32);
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch *gdbarch)
230 return gdbarch_tdep (gdbarch)->mips_abi;
234 mips_isa_regsize (struct gdbarch *gdbarch)
236 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
238 /* If we know how big the registers are, use that size. */
239 if (tdep->register_size_valid_p)
240 return tdep->register_size;
242 /* Fall back to the previous behavior. */
243 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
244 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
247 /* Return the currently configured (or set) saved register size. */
250 mips_abi_regsize (struct gdbarch *gdbarch)
252 switch (mips_abi (gdbarch))
254 case MIPS_ABI_EABI32:
260 case MIPS_ABI_EABI64:
262 case MIPS_ABI_UNKNOWN:
265 internal_error (__FILE__, __LINE__, _("bad switch"));
269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
270 are some functions to handle addresses associated with compressed
271 code including but not limited to testing, setting, or clearing
272 bit 0 of such addresses. */
274 /* Return one iff compressed code is the MIPS16 instruction set. */
277 is_mips16_isa (struct gdbarch *gdbarch)
279 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16;
282 /* Return one iff compressed code is the microMIPS instruction set. */
285 is_micromips_isa (struct gdbarch *gdbarch)
287 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS;
290 /* Return one iff ADDR denotes compressed code. */
293 is_compact_addr (CORE_ADDR addr)
298 /* Return one iff ADDR denotes standard ISA code. */
301 is_mips_addr (CORE_ADDR addr)
303 return !is_compact_addr (addr);
306 /* Return one iff ADDR denotes MIPS16 code. */
309 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
311 return is_compact_addr (addr) && is_mips16_isa (gdbarch);
314 /* Return one iff ADDR denotes microMIPS code. */
317 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
319 return is_compact_addr (addr) && is_micromips_isa (gdbarch);
322 /* Strip the ISA (compression) bit off from ADDR. */
325 unmake_compact_addr (CORE_ADDR addr)
327 return ((addr) & ~(CORE_ADDR) 1);
330 /* Add the ISA (compression) bit to ADDR. */
333 make_compact_addr (CORE_ADDR addr)
335 return ((addr) | (CORE_ADDR) 1);
338 /* Functions for setting and testing a bit in a minimal symbol that
339 marks it as MIPS16 or microMIPS function. The MSB of the minimal
340 symbol's "info" field is used for this purpose.
342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
344 one of the "special" bits in a minimal symbol to mark it accordingly.
345 The test checks an ELF-private flag that is valid for true function
346 symbols only; for synthetic symbols such as for PLT stubs that have
347 no ELF-private part at all the MIPS BFD backend arranges for this
348 information to be carried in the asymbol's udata field instead.
350 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
351 in a minimal symbol. */
354 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
356 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
357 unsigned char st_other;
359 if ((sym->flags & BSF_SYNTHETIC) == 0)
360 st_other = elfsym->internal_elf_sym.st_other;
361 else if ((sym->flags & BSF_FUNCTION) != 0)
362 st_other = sym->udata.i;
366 if (ELF_ST_IS_MICROMIPS (st_other))
367 MSYMBOL_TARGET_FLAG_2 (msym) = 1;
368 else if (ELF_ST_IS_MIPS16 (st_other))
369 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
372 /* Return one iff MSYM refers to standard ISA code. */
375 msymbol_is_mips (struct minimal_symbol *msym)
377 return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym));
380 /* Return one iff MSYM refers to MIPS16 code. */
383 msymbol_is_mips16 (struct minimal_symbol *msym)
385 return MSYMBOL_TARGET_FLAG_1 (msym);
388 /* Return one iff MSYM refers to microMIPS code. */
391 msymbol_is_micromips (struct minimal_symbol *msym)
393 return MSYMBOL_TARGET_FLAG_2 (msym);
396 /* XFER a value from the big/little/left end of the register.
397 Depending on the size of the value it might occupy the entire
398 register or just part of it. Make an allowance for this, aligning
399 things accordingly. */
402 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
403 int reg_num, int length,
404 enum bfd_endian endian, gdb_byte *in,
405 const gdb_byte *out, int buf_offset)
409 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
410 /* Need to transfer the left or right part of the register, based on
411 the targets byte order. */
415 reg_offset = register_size (gdbarch, reg_num) - length;
417 case BFD_ENDIAN_LITTLE:
420 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
424 internal_error (__FILE__, __LINE__, _("bad switch"));
427 fprintf_unfiltered (gdb_stderr,
428 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
429 reg_num, reg_offset, buf_offset, length);
430 if (mips_debug && out != NULL)
433 fprintf_unfiltered (gdb_stdlog, "out ");
434 for (i = 0; i < length; i++)
435 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
438 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
441 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
443 if (mips_debug && in != NULL)
446 fprintf_unfiltered (gdb_stdlog, "in ");
447 for (i = 0; i < length; i++)
448 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
451 fprintf_unfiltered (gdb_stdlog, "\n");
454 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
455 compatiblity mode. A return value of 1 means that we have
456 physical 64-bit registers, but should treat them as 32-bit registers. */
459 mips2_fp_compat (struct frame_info *frame)
461 struct gdbarch *gdbarch = get_frame_arch (frame);
462 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
464 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
468 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
469 in all the places we deal with FP registers. PR gdb/413. */
470 /* Otherwise check the FR bit in the status register - it controls
471 the FP compatiblity mode. If it is clear we are in compatibility
473 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
480 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
482 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
484 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
486 /* The list of available "set mips " and "show mips " commands. */
488 static struct cmd_list_element *setmipscmdlist = NULL;
489 static struct cmd_list_element *showmipscmdlist = NULL;
491 /* Integer registers 0 thru 31 are handled explicitly by
492 mips_register_name(). Processor specific registers 32 and above
493 are listed in the following tables. */
496 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
500 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
501 "sr", "lo", "hi", "bad", "cause", "pc",
502 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
503 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
504 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
505 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
509 /* Names of IDT R3041 registers. */
511 static const char *mips_r3041_reg_names[] = {
512 "sr", "lo", "hi", "bad", "cause", "pc",
513 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
514 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
515 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
516 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
517 "fsr", "fir", "", /*"fp" */ "",
518 "", "", "bus", "ccfg", "", "", "", "",
519 "", "", "port", "cmp", "", "", "epc", "prid",
522 /* Names of tx39 registers. */
524 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
525 "sr", "lo", "hi", "bad", "cause", "pc",
526 "", "", "", "", "", "", "", "",
527 "", "", "", "", "", "", "", "",
528 "", "", "", "", "", "", "", "",
529 "", "", "", "", "", "", "", "",
531 "", "", "", "", "", "", "", "",
532 "", "", "config", "cache", "debug", "depc", "epc",
535 /* Names of IRIX registers. */
536 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
537 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
538 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
539 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
540 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
541 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
544 /* Names of registers with Linux kernels. */
545 static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
546 "sr", "lo", "hi", "bad", "cause", "pc",
547 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
548 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
549 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
550 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
555 /* Return the name of the register corresponding to REGNO. */
557 mips_register_name (struct gdbarch *gdbarch, int regno)
559 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
560 /* GPR names for all ABIs other than n32/n64. */
561 static char *mips_gpr_names[] = {
562 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
563 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
564 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
565 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
568 /* GPR names for n32 and n64 ABIs. */
569 static char *mips_n32_n64_gpr_names[] = {
570 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
571 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
572 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
573 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
576 enum mips_abi abi = mips_abi (gdbarch);
578 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
579 but then don't make the raw register names visible. This (upper)
580 range of user visible register numbers are the pseudo-registers.
582 This approach was adopted accommodate the following scenario:
583 It is possible to debug a 64-bit device using a 32-bit
584 programming model. In such instances, the raw registers are
585 configured to be 64-bits wide, while the pseudo registers are
586 configured to be 32-bits wide. The registers that the user
587 sees - the pseudo registers - match the users expectations
588 given the programming model being used. */
589 int rawnum = regno % gdbarch_num_regs (gdbarch);
590 if (regno < gdbarch_num_regs (gdbarch))
593 /* The MIPS integer registers are always mapped from 0 to 31. The
594 names of the registers (which reflects the conventions regarding
595 register use) vary depending on the ABI. */
596 if (0 <= rawnum && rawnum < 32)
598 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
599 return mips_n32_n64_gpr_names[rawnum];
601 return mips_gpr_names[rawnum];
603 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
604 return tdesc_register_name (gdbarch, rawnum);
605 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
607 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
608 if (tdep->mips_processor_reg_names[rawnum - 32])
609 return tdep->mips_processor_reg_names[rawnum - 32];
613 internal_error (__FILE__, __LINE__,
614 _("mips_register_name: bad register number %d"), rawnum);
617 /* Return the groups that a MIPS register can be categorised into. */
620 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
621 struct reggroup *reggroup)
626 int rawnum = regnum % gdbarch_num_regs (gdbarch);
627 int pseudo = regnum / gdbarch_num_regs (gdbarch);
628 if (reggroup == all_reggroup)
630 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
631 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
632 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
633 (gdbarch), as not all architectures are multi-arch. */
634 raw_p = rawnum < gdbarch_num_regs (gdbarch);
635 if (gdbarch_register_name (gdbarch, regnum) == NULL
636 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
638 if (reggroup == float_reggroup)
639 return float_p && pseudo;
640 if (reggroup == vector_reggroup)
641 return vector_p && pseudo;
642 if (reggroup == general_reggroup)
643 return (!vector_p && !float_p) && pseudo;
644 /* Save the pseudo registers. Need to make certain that any code
645 extracting register values from a saved register cache also uses
647 if (reggroup == save_reggroup)
648 return raw_p && pseudo;
649 /* Restore the same pseudo register. */
650 if (reggroup == restore_reggroup)
651 return raw_p && pseudo;
655 /* Return the groups that a MIPS register can be categorised into.
656 This version is only used if we have a target description which
657 describes real registers (and their groups). */
660 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
661 struct reggroup *reggroup)
663 int rawnum = regnum % gdbarch_num_regs (gdbarch);
664 int pseudo = regnum / gdbarch_num_regs (gdbarch);
667 /* Only save, restore, and display the pseudo registers. Need to
668 make certain that any code extracting register values from a
669 saved register cache also uses pseudo registers.
671 Note: saving and restoring the pseudo registers is slightly
672 strange; if we have 64 bits, we should save and restore all
673 64 bits. But this is hard and has little benefit. */
677 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
681 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
684 /* Map the symbol table registers which live in the range [1 *
685 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
686 registers. Take care of alignment and size problems. */
688 static enum register_status
689 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
690 int cookednum, gdb_byte *buf)
692 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
693 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
694 && cookednum < 2 * gdbarch_num_regs (gdbarch));
695 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
696 return regcache_raw_read (regcache, rawnum, buf);
697 else if (register_size (gdbarch, rawnum) >
698 register_size (gdbarch, cookednum))
700 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
701 return regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
704 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
706 enum register_status status;
708 status = regcache_raw_read_signed (regcache, rawnum, ®val);
709 if (status == REG_VALID)
710 store_signed_integer (buf, 4, byte_order, regval);
715 internal_error (__FILE__, __LINE__, _("bad register size"));
719 mips_pseudo_register_write (struct gdbarch *gdbarch,
720 struct regcache *regcache, int cookednum,
723 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
724 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
725 && cookednum < 2 * gdbarch_num_regs (gdbarch));
726 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
727 regcache_raw_write (regcache, rawnum, buf);
728 else if (register_size (gdbarch, rawnum) >
729 register_size (gdbarch, cookednum))
731 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
732 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
735 /* Sign extend the shortened version of the register prior
736 to placing it in the raw register. This is required for
737 some mips64 parts in order to avoid unpredictable behavior. */
738 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
739 LONGEST regval = extract_signed_integer (buf, 4, byte_order);
740 regcache_raw_write_signed (regcache, rawnum, regval);
744 internal_error (__FILE__, __LINE__, _("bad register size"));
748 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch,
749 struct agent_expr *ax, int reg)
751 int rawnum = reg % gdbarch_num_regs (gdbarch);
752 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
753 && reg < 2 * gdbarch_num_regs (gdbarch));
755 ax_reg_mask (ax, rawnum);
761 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
762 struct agent_expr *ax, int reg)
764 int rawnum = reg % gdbarch_num_regs (gdbarch);
765 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
766 && reg < 2 * gdbarch_num_regs (gdbarch));
767 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg))
771 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg))
773 if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
774 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG)
777 ax_simple (ax, aop_lsh);
780 ax_simple (ax, aop_rsh_signed);
784 internal_error (__FILE__, __LINE__, _("bad register size"));
789 /* Table to translate 3-bit register field to actual register number. */
790 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
792 /* Heuristic_proc_start may hunt through the text section for a long
793 time across a 2400 baud serial line. Allows the user to limit this
796 static int heuristic_fence_post = 0;
798 /* Number of bytes of storage in the actual machine representation for
799 register N. NOTE: This defines the pseudo register type so need to
800 rebuild the architecture vector. */
802 static int mips64_transfers_32bit_regs_p = 0;
805 set_mips64_transfers_32bit_regs (char *args, int from_tty,
806 struct cmd_list_element *c)
808 struct gdbarch_info info;
809 gdbarch_info_init (&info);
810 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
811 instead of relying on globals. Doing that would let generic code
812 handle the search for this specific architecture. */
813 if (!gdbarch_update_p (info))
815 mips64_transfers_32bit_regs_p = 0;
816 error (_("32-bit compatibility mode not supported"));
820 /* Convert to/from a register and the corresponding memory value. */
822 /* This predicate tests for the case of an 8 byte floating point
823 value that is being transferred to or from a pair of floating point
824 registers each of which are (or are considered to be) only 4 bytes
827 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum,
830 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
831 && register_size (gdbarch, regnum) == 4
832 && mips_float_register_p (gdbarch, regnum)
833 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
836 /* This predicate tests for the case of a value of less than 8
837 bytes in width that is being transfered to or from an 8 byte
838 general purpose register. */
840 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum,
843 int num_regs = gdbarch_num_regs (gdbarch);
845 return (register_size (gdbarch, regnum) == 8
846 && regnum % num_regs > 0 && regnum % num_regs < 32
847 && TYPE_LENGTH (type) < 8);
851 mips_convert_register_p (struct gdbarch *gdbarch,
852 int regnum, struct type *type)
854 return (mips_convert_register_float_case_p (gdbarch, regnum, type)
855 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type));
859 mips_register_to_value (struct frame_info *frame, int regnum,
860 struct type *type, gdb_byte *to,
861 int *optimizedp, int *unavailablep)
863 struct gdbarch *gdbarch = get_frame_arch (frame);
865 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
867 get_frame_register (frame, regnum + 0, to + 4);
868 get_frame_register (frame, regnum + 1, to + 0);
870 if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4,
871 optimizedp, unavailablep))
874 if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0,
875 optimizedp, unavailablep))
877 *optimizedp = *unavailablep = 0;
880 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
882 int len = TYPE_LENGTH (type);
885 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0;
886 if (!get_frame_register_bytes (frame, regnum, offset, len, to,
887 optimizedp, unavailablep))
890 *optimizedp = *unavailablep = 0;
895 internal_error (__FILE__, __LINE__,
896 _("mips_register_to_value: unrecognized case"));
901 mips_value_to_register (struct frame_info *frame, int regnum,
902 struct type *type, const gdb_byte *from)
904 struct gdbarch *gdbarch = get_frame_arch (frame);
906 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
908 put_frame_register (frame, regnum + 0, from + 4);
909 put_frame_register (frame, regnum + 1, from + 0);
911 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
914 int len = TYPE_LENGTH (type);
916 /* Sign extend values, irrespective of type, that are stored to
917 a 64-bit general purpose register. (32-bit unsigned values
918 are stored as signed quantities within a 64-bit register.
919 When performing an operation, in compiled code, that combines
920 a 32-bit unsigned value with a signed 64-bit value, a type
921 conversion is first performed that zeroes out the high 32 bits.) */
922 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
925 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1);
927 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0);
928 put_frame_register_bytes (frame, regnum, 0, 8 - len, fill);
929 put_frame_register_bytes (frame, regnum, 8 - len, len, from);
933 if (from[len-1] & 0x80)
934 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1);
936 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0);
937 put_frame_register_bytes (frame, regnum, 0, len, from);
938 put_frame_register_bytes (frame, regnum, len, 8 - len, fill);
943 internal_error (__FILE__, __LINE__,
944 _("mips_value_to_register: unrecognized case"));
948 /* Return the GDB type object for the "standard" data type of data in
952 mips_register_type (struct gdbarch *gdbarch, int regnum)
954 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
955 if (mips_float_register_p (gdbarch, regnum))
957 /* The floating-point registers raw, or cooked, always match
958 mips_isa_regsize(), and also map 1:1, byte for byte. */
959 if (mips_isa_regsize (gdbarch) == 4)
960 return builtin_type (gdbarch)->builtin_float;
962 return builtin_type (gdbarch)->builtin_double;
964 else if (regnum < gdbarch_num_regs (gdbarch))
966 /* The raw or ISA registers. These are all sized according to
968 if (mips_isa_regsize (gdbarch) == 4)
969 return builtin_type (gdbarch)->builtin_int32;
971 return builtin_type (gdbarch)->builtin_int64;
975 int rawnum = regnum - gdbarch_num_regs (gdbarch);
977 /* The cooked or ABI registers. These are sized according to
978 the ABI (with a few complications). */
979 if (rawnum == mips_regnum (gdbarch)->fp_control_status
980 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision)
981 return builtin_type (gdbarch)->builtin_int32;
982 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX
983 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
984 && rawnum >= MIPS_FIRST_EMBED_REGNUM
985 && rawnum <= MIPS_LAST_EMBED_REGNUM)
986 /* The pseudo/cooked view of the embedded registers is always
987 32-bit. The raw view is handled below. */
988 return builtin_type (gdbarch)->builtin_int32;
989 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
990 /* The target, while possibly using a 64-bit register buffer,
991 is only transfering 32-bits of each integer register.
992 Reflect this in the cooked/pseudo (ABI) register value. */
993 return builtin_type (gdbarch)->builtin_int32;
994 else if (mips_abi_regsize (gdbarch) == 4)
995 /* The ABI is restricted to 32-bit registers (the ISA could be
997 return builtin_type (gdbarch)->builtin_int32;
1000 return builtin_type (gdbarch)->builtin_int64;
1004 /* Return the GDB type for the pseudo register REGNUM, which is the
1005 ABI-level view. This function is only called if there is a target
1006 description which includes registers, so we know precisely the
1007 types of hardware registers. */
1009 static struct type *
1010 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
1012 const int num_regs = gdbarch_num_regs (gdbarch);
1013 int rawnum = regnum % num_regs;
1014 struct type *rawtype;
1016 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
1018 /* Absent registers are still absent. */
1019 rawtype = gdbarch_register_type (gdbarch, rawnum);
1020 if (TYPE_LENGTH (rawtype) == 0)
1023 if (mips_float_register_p (gdbarch, rawnum))
1024 /* Present the floating point registers however the hardware did;
1025 do not try to convert between FPU layouts. */
1028 /* Use pointer types for registers if we can. For n32 we can not,
1029 since we do not have a 64-bit pointer type. */
1030 if (mips_abi_regsize (gdbarch)
1031 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
1033 if (rawnum == MIPS_SP_REGNUM
1034 || rawnum == mips_regnum (gdbarch)->badvaddr)
1035 return builtin_type (gdbarch)->builtin_data_ptr;
1036 else if (rawnum == mips_regnum (gdbarch)->pc)
1037 return builtin_type (gdbarch)->builtin_func_ptr;
1040 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
1041 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM)
1042 || rawnum == mips_regnum (gdbarch)->lo
1043 || rawnum == mips_regnum (gdbarch)->hi
1044 || rawnum == mips_regnum (gdbarch)->badvaddr
1045 || rawnum == mips_regnum (gdbarch)->cause
1046 || rawnum == mips_regnum (gdbarch)->pc
1047 || (mips_regnum (gdbarch)->dspacc != -1
1048 && rawnum >= mips_regnum (gdbarch)->dspacc
1049 && rawnum < mips_regnum (gdbarch)->dspacc + 6)))
1050 return builtin_type (gdbarch)->builtin_int32;
1052 if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX
1053 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
1054 && rawnum >= MIPS_EMBED_FP0_REGNUM + 32
1055 && rawnum <= MIPS_LAST_EMBED_REGNUM)
1057 /* The pseudo/cooked view of embedded registers is always
1058 32-bit, even if the target transfers 64-bit values for them.
1059 New targets relying on XML descriptions should only transfer
1060 the necessary 32 bits, but older versions of GDB expected 64,
1061 so allow the target to provide 64 bits without interfering
1062 with the displayed type. */
1063 return builtin_type (gdbarch)->builtin_int32;
1066 /* For all other registers, pass through the hardware type. */
1070 /* Should the upper word of 64-bit addresses be zeroed? */
1071 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
1074 mips_mask_address_p (struct gdbarch_tdep *tdep)
1076 switch (mask_address_var)
1078 case AUTO_BOOLEAN_TRUE:
1080 case AUTO_BOOLEAN_FALSE:
1083 case AUTO_BOOLEAN_AUTO:
1084 return tdep->default_mask_address_p;
1086 internal_error (__FILE__, __LINE__,
1087 _("mips_mask_address_p: bad switch"));
1093 show_mask_address (struct ui_file *file, int from_tty,
1094 struct cmd_list_element *c, const char *value)
1096 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
1098 deprecated_show_value_hack (file, from_tty, c, value);
1099 switch (mask_address_var)
1101 case AUTO_BOOLEAN_TRUE:
1102 printf_filtered ("The 32 bit mips address mask is enabled\n");
1104 case AUTO_BOOLEAN_FALSE:
1105 printf_filtered ("The 32 bit mips address mask is disabled\n");
1107 case AUTO_BOOLEAN_AUTO:
1109 ("The 32 bit address mask is set automatically. Currently %s\n",
1110 mips_mask_address_p (tdep) ? "enabled" : "disabled");
1113 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
1118 /* Tell if the program counter value in MEMADDR is in a standard ISA
1122 mips_pc_is_mips (CORE_ADDR memaddr)
1124 struct bound_minimal_symbol sym;
1126 /* Flags indicating that this is a MIPS16 or microMIPS function is
1127 stored by elfread.c in the high bit of the info field. Use this
1128 to decide if the function is standard MIPS. Otherwise if bit 0
1129 of the address is clear, then this is a standard MIPS function. */
1130 sym = lookup_minimal_symbol_by_pc (memaddr);
1132 return msymbol_is_mips (sym.minsym);
1134 return is_mips_addr (memaddr);
1137 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1140 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1142 struct bound_minimal_symbol sym;
1144 /* A flag indicating that this is a MIPS16 function is stored by
1145 elfread.c in the high bit of the info field. Use this to decide
1146 if the function is MIPS16. Otherwise if bit 0 of the address is
1147 set, then ELF file flags will tell if this is a MIPS16 function. */
1148 sym = lookup_minimal_symbol_by_pc (memaddr);
1150 return msymbol_is_mips16 (sym.minsym);
1152 return is_mips16_addr (gdbarch, memaddr);
1155 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1158 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1160 struct bound_minimal_symbol sym;
1162 /* A flag indicating that this is a microMIPS function is stored by
1163 elfread.c in the high bit of the info field. Use this to decide
1164 if the function is microMIPS. Otherwise if bit 0 of the address
1165 is set, then ELF file flags will tell if this is a microMIPS
1167 sym = lookup_minimal_symbol_by_pc (memaddr);
1169 return msymbol_is_micromips (sym.minsym);
1171 return is_micromips_addr (gdbarch, memaddr);
1174 /* Tell the ISA type of the function the program counter value in MEMADDR
1177 static enum mips_isa
1178 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1180 struct bound_minimal_symbol sym;
1182 /* A flag indicating that this is a MIPS16 or a microMIPS function
1183 is stored by elfread.c in the high bit of the info field. Use
1184 this to decide if the function is MIPS16 or microMIPS or normal
1185 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1186 flags will tell if this is a MIPS16 or a microMIPS function. */
1187 sym = lookup_minimal_symbol_by_pc (memaddr);
1190 if (msymbol_is_micromips (sym.minsym))
1191 return ISA_MICROMIPS;
1192 else if (msymbol_is_mips16 (sym.minsym))
1199 if (is_mips_addr (memaddr))
1201 else if (is_micromips_addr (gdbarch, memaddr))
1202 return ISA_MICROMIPS;
1208 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1210 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_";
1211 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_";
1212 static const char mips_str_call_fp_stub[] = "__call_stub_fp_";
1213 static const char mips_str_call_stub[] = "__call_stub_";
1214 static const char mips_str_fn_stub[] = "__fn_stub_";
1216 /* This is used as a PIC thunk prefix. */
1218 static const char mips_str_pic[] = ".pic.";
1220 /* Return non-zero if the PC is inside a call thunk (aka stub or
1221 trampoline) that should be treated as a temporary frame. */
1224 mips_in_frame_stub (CORE_ADDR pc)
1226 CORE_ADDR start_addr;
1229 /* Find the starting address of the function containing the PC. */
1230 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
1233 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1234 if (strncmp (name, mips_str_mips16_call_stub,
1235 strlen (mips_str_mips16_call_stub)) == 0)
1237 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1238 if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0)
1240 /* If the PC is in __fn_stub_*, this is a call stub. */
1241 if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0)
1244 return 0; /* Not a stub. */
1247 /* MIPS believes that the PC has a sign extended value. Perhaps the
1248 all registers should be sign extended for simplicity? */
1251 mips_read_pc (struct regcache *regcache)
1253 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache));
1256 regcache_cooked_read_signed (regcache, regnum, &pc);
1257 if (is_compact_addr (pc))
1258 pc = unmake_compact_addr (pc);
1263 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1267 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch));
1268 if (is_compact_addr (pc))
1269 pc = unmake_compact_addr (pc);
1270 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1271 intermediate frames. In this case we can get the caller's address
1272 from $ra, or if $ra contains an address within a thunk as well, then
1273 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1274 and thus the caller's address is in $s2. */
1275 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc))
1277 pc = frame_unwind_register_signed
1278 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
1279 if (is_compact_addr (pc))
1280 pc = unmake_compact_addr (pc);
1281 if (mips_in_frame_stub (pc))
1283 pc = frame_unwind_register_signed
1284 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
1285 if (is_compact_addr (pc))
1286 pc = unmake_compact_addr (pc);
1293 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1295 return frame_unwind_register_signed
1296 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
1299 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1300 dummy frame. The frame ID's base needs to match the TOS value
1301 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1304 static struct frame_id
1305 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1307 return frame_id_build
1308 (get_frame_register_signed (this_frame,
1309 gdbarch_num_regs (gdbarch)
1311 get_frame_pc (this_frame));
1314 /* Implement the "write_pc" gdbarch method. */
1317 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
1319 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache));
1321 if (mips_pc_is_mips (pc))
1322 regcache_cooked_write_unsigned (regcache, regnum, pc);
1324 regcache_cooked_write_unsigned (regcache, regnum, make_compact_addr (pc));
1327 /* Fetch and return instruction from the specified location. Handle
1328 MIPS16/microMIPS as appropriate. */
1331 mips_fetch_instruction (struct gdbarch *gdbarch,
1332 enum mips_isa isa, CORE_ADDR addr, int *statusp)
1334 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1335 gdb_byte buf[MIPS_INSN32_SIZE];
1343 instlen = MIPS_INSN16_SIZE;
1344 addr = unmake_compact_addr (addr);
1347 instlen = MIPS_INSN32_SIZE;
1350 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1353 status = target_read_memory (addr, buf, instlen);
1354 if (statusp != NULL)
1358 if (statusp == NULL)
1359 memory_error (status, addr);
1362 return extract_unsigned_integer (buf, instlen, byte_order);
1365 /* These are the fields of 32 bit mips instructions. */
1366 #define mips32_op(x) (x >> 26)
1367 #define itype_op(x) (x >> 26)
1368 #define itype_rs(x) ((x >> 21) & 0x1f)
1369 #define itype_rt(x) ((x >> 16) & 0x1f)
1370 #define itype_immediate(x) (x & 0xffff)
1372 #define jtype_op(x) (x >> 26)
1373 #define jtype_target(x) (x & 0x03ffffff)
1375 #define rtype_op(x) (x >> 26)
1376 #define rtype_rs(x) ((x >> 21) & 0x1f)
1377 #define rtype_rt(x) ((x >> 16) & 0x1f)
1378 #define rtype_rd(x) ((x >> 11) & 0x1f)
1379 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1380 #define rtype_funct(x) (x & 0x3f)
1382 /* MicroMIPS instruction fields. */
1383 #define micromips_op(x) ((x) >> 10)
1385 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1386 bit and the size respectively of the field extracted. */
1387 #define b0s4_imm(x) ((x) & 0xf)
1388 #define b0s5_imm(x) ((x) & 0x1f)
1389 #define b0s5_reg(x) ((x) & 0x1f)
1390 #define b0s7_imm(x) ((x) & 0x7f)
1391 #define b0s10_imm(x) ((x) & 0x3ff)
1392 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1393 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1394 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1395 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1396 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1397 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1398 #define b6s4_op(x) (((x) >> 6) & 0xf)
1399 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1401 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1402 respectively of the field extracted. */
1403 #define b0s6_op(x) ((x) & 0x3f)
1404 #define b0s11_op(x) ((x) & 0x7ff)
1405 #define b0s12_imm(x) ((x) & 0xfff)
1406 #define b0s16_imm(x) ((x) & 0xffff)
1407 #define b0s26_imm(x) ((x) & 0x3ffffff)
1408 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1409 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1410 #define b12s4_op(x) (((x) >> 12) & 0xf)
1412 /* Return the size in bytes of the instruction INSN encoded in the ISA
1416 mips_insn_size (enum mips_isa isa, ULONGEST insn)
1421 if (micromips_op (insn) == 0x1f)
1422 return 3 * MIPS_INSN16_SIZE;
1423 else if (((micromips_op (insn) & 0x4) == 0x4)
1424 || ((micromips_op (insn) & 0x7) == 0x0))
1425 return 2 * MIPS_INSN16_SIZE;
1427 return MIPS_INSN16_SIZE;
1429 if ((insn & 0xf800) == 0xf000)
1430 return 2 * MIPS_INSN16_SIZE;
1432 return MIPS_INSN16_SIZE;
1434 return MIPS_INSN32_SIZE;
1436 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1440 mips32_relative_offset (ULONGEST inst)
1442 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
1445 /* Determine the address of the next instruction executed after the INST
1446 floating condition branch instruction at PC. COUNT specifies the
1447 number of the floating condition bits tested by the branch. */
1450 mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
1451 ULONGEST inst, CORE_ADDR pc, int count)
1453 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1454 int cnum = (itype_rt (inst) >> 2) & (count - 1);
1455 int tf = itype_rt (inst) & 1;
1456 int mask = (1 << count) - 1;
1461 /* No way to handle; it'll most likely trap anyway. */
1464 fcs = get_frame_register_unsigned (frame, fcsr);
1465 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1467 if (((cond >> cnum) & mask) != mask * !tf)
1468 pc += mips32_relative_offset (inst);
1475 /* Return nonzero if the gdbarch is an Octeon series. */
1478 is_octeon (struct gdbarch *gdbarch)
1480 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
1482 return (info->mach == bfd_mach_mips_octeon
1483 || info->mach == bfd_mach_mips_octeonp
1484 || info->mach == bfd_mach_mips_octeon2);
1487 /* Return true if the OP represents the Octeon's BBIT instruction. */
1490 is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
1492 if (!is_octeon (gdbarch))
1494 /* BBIT0 is encoded as LWC2: 110 010. */
1495 /* BBIT032 is encoded as LDC2: 110 110. */
1496 /* BBIT1 is encoded as SWC2: 111 010. */
1497 /* BBIT132 is encoded as SDC2: 111 110. */
1498 if (op == 50 || op == 54 || op == 58 || op == 62)
1504 /* Determine where to set a single step breakpoint while considering
1505 branch prediction. */
1508 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
1510 struct gdbarch *gdbarch = get_frame_arch (frame);
1513 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
1514 op = itype_op (inst);
1515 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch
1519 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1530 goto greater_branch;
1535 else if (op == 17 && itype_rs (inst) == 8)
1536 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1537 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1);
1538 else if (op == 17 && itype_rs (inst) == 9
1539 && (itype_rt (inst) & 2) == 0)
1540 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1541 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2);
1542 else if (op == 17 && itype_rs (inst) == 10
1543 && (itype_rt (inst) & 2) == 0)
1544 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1545 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4);
1548 /* The new PC will be alternate mode. */
1552 reg = jtype_target (inst) << 2;
1553 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1554 pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1;
1556 else if (is_octeon_bbit_op (op, gdbarch))
1560 branch_if = op == 58 || op == 62;
1561 bit = itype_rt (inst);
1563 /* Take into account the *32 instructions. */
1564 if (op == 54 || op == 62)
1567 if (((get_frame_register_signed (frame,
1568 itype_rs (inst)) >> bit) & 1)
1570 pc += mips32_relative_offset (inst) + 4;
1572 pc += 8; /* After the delay slot. */
1576 pc += 4; /* Not a branch, next instruction is easy. */
1579 { /* This gets way messy. */
1581 /* Further subdivide into SPECIAL, REGIMM and other. */
1582 switch (op & 0x07) /* Extract bits 28,27,26. */
1584 case 0: /* SPECIAL */
1585 op = rtype_funct (inst);
1590 /* Set PC to that address. */
1591 pc = get_frame_register_signed (frame, rtype_rs (inst));
1593 case 12: /* SYSCALL */
1595 struct gdbarch_tdep *tdep;
1597 tdep = gdbarch_tdep (get_frame_arch (frame));
1598 if (tdep->syscall_next_pc != NULL)
1599 pc = tdep->syscall_next_pc (frame);
1608 break; /* end SPECIAL */
1609 case 1: /* REGIMM */
1611 op = itype_rt (inst); /* branch condition */
1616 case 16: /* BLTZAL */
1617 case 18: /* BLTZALL */
1619 if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1620 pc += mips32_relative_offset (inst) + 4;
1622 pc += 8; /* after the delay slot */
1626 case 17: /* BGEZAL */
1627 case 19: /* BGEZALL */
1628 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1629 pc += mips32_relative_offset (inst) + 4;
1631 pc += 8; /* after the delay slot */
1633 case 0x1c: /* BPOSGE32 */
1634 case 0x1e: /* BPOSGE64 */
1636 if (itype_rs (inst) == 0)
1638 unsigned int pos = (op & 2) ? 64 : 32;
1639 int dspctl = mips_regnum (gdbarch)->dspctl;
1642 /* No way to handle; it'll most likely trap anyway. */
1645 if ((get_frame_register_unsigned (frame,
1646 dspctl) & 0x7f) >= pos)
1647 pc += mips32_relative_offset (inst);
1652 /* All of the other instructions in the REGIMM category */
1657 break; /* end REGIMM */
1662 reg = jtype_target (inst) << 2;
1663 /* Upper four bits get never changed... */
1664 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1667 case 4: /* BEQ, BEQL */
1669 if (get_frame_register_signed (frame, itype_rs (inst)) ==
1670 get_frame_register_signed (frame, itype_rt (inst)))
1671 pc += mips32_relative_offset (inst) + 4;
1675 case 5: /* BNE, BNEL */
1677 if (get_frame_register_signed (frame, itype_rs (inst)) !=
1678 get_frame_register_signed (frame, itype_rt (inst)))
1679 pc += mips32_relative_offset (inst) + 4;
1683 case 6: /* BLEZ, BLEZL */
1684 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1685 pc += mips32_relative_offset (inst) + 4;
1691 greater_branch: /* BGTZ, BGTZL */
1692 if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1693 pc += mips32_relative_offset (inst) + 4;
1700 } /* mips32_next_pc */
1702 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1706 micromips_relative_offset7 (ULONGEST insn)
1708 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1;
1711 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1715 micromips_relative_offset10 (ULONGEST insn)
1717 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1;
1720 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1724 micromips_relative_offset16 (ULONGEST insn)
1726 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1;
1729 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1732 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc)
1736 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1737 return mips_insn_size (ISA_MICROMIPS, insn);
1740 /* Calculate the address of the next microMIPS instruction to execute
1741 after the INSN coprocessor 1 conditional branch instruction at the
1742 address PC. COUNT denotes the number of coprocessor condition bits
1743 examined by the branch. */
1746 micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
1747 ULONGEST insn, CORE_ADDR pc, int count)
1749 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1750 int cnum = b2s3_cc (insn >> 16) & (count - 1);
1751 int tf = b5s5_op (insn >> 16) & 1;
1752 int mask = (1 << count) - 1;
1757 /* No way to handle; it'll most likely trap anyway. */
1760 fcs = get_frame_register_unsigned (frame, fcsr);
1761 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1763 if (((cond >> cnum) & mask) != mask * !tf)
1764 pc += micromips_relative_offset16 (insn);
1766 pc += micromips_pc_insn_size (gdbarch, pc);
1771 /* Calculate the address of the next microMIPS instruction to execute
1772 after the instruction at the address PC. */
1775 micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1777 struct gdbarch *gdbarch = get_frame_arch (frame);
1780 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1781 pc += MIPS_INSN16_SIZE;
1782 switch (mips_insn_size (ISA_MICROMIPS, insn))
1784 /* 48-bit instructions. */
1785 case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
1786 /* No branch or jump instructions in this category. */
1787 pc += 2 * MIPS_INSN16_SIZE;
1790 /* 32-bit instructions. */
1791 case 2 * MIPS_INSN16_SIZE:
1793 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1794 pc += MIPS_INSN16_SIZE;
1795 switch (micromips_op (insn >> 16))
1797 case 0x00: /* POOL32A: bits 000000 */
1798 if (b0s6_op (insn) == 0x3c
1799 /* POOL32Axf: bits 000000 ... 111100 */
1800 && (b6s10_ext (insn) & 0x2bf) == 0x3c)
1801 /* JALR, JALR.HB: 000000 000x111100 111100 */
1802 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1803 pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16));
1806 case 0x10: /* POOL32I: bits 010000 */
1807 switch (b5s5_op (insn >> 16))
1809 case 0x00: /* BLTZ: bits 010000 00000 */
1810 case 0x01: /* BLTZAL: bits 010000 00001 */
1811 case 0x11: /* BLTZALS: bits 010000 10001 */
1812 if (get_frame_register_signed (frame,
1813 b0s5_reg (insn >> 16)) < 0)
1814 pc += micromips_relative_offset16 (insn);
1816 pc += micromips_pc_insn_size (gdbarch, pc);
1819 case 0x02: /* BGEZ: bits 010000 00010 */
1820 case 0x03: /* BGEZAL: bits 010000 00011 */
1821 case 0x13: /* BGEZALS: bits 010000 10011 */
1822 if (get_frame_register_signed (frame,
1823 b0s5_reg (insn >> 16)) >= 0)
1824 pc += micromips_relative_offset16 (insn);
1826 pc += micromips_pc_insn_size (gdbarch, pc);
1829 case 0x04: /* BLEZ: bits 010000 00100 */
1830 if (get_frame_register_signed (frame,
1831 b0s5_reg (insn >> 16)) <= 0)
1832 pc += micromips_relative_offset16 (insn);
1834 pc += micromips_pc_insn_size (gdbarch, pc);
1837 case 0x05: /* BNEZC: bits 010000 00101 */
1838 if (get_frame_register_signed (frame,
1839 b0s5_reg (insn >> 16)) != 0)
1840 pc += micromips_relative_offset16 (insn);
1843 case 0x06: /* BGTZ: bits 010000 00110 */
1844 if (get_frame_register_signed (frame,
1845 b0s5_reg (insn >> 16)) > 0)
1846 pc += micromips_relative_offset16 (insn);
1848 pc += micromips_pc_insn_size (gdbarch, pc);
1851 case 0x07: /* BEQZC: bits 010000 00111 */
1852 if (get_frame_register_signed (frame,
1853 b0s5_reg (insn >> 16)) == 0)
1854 pc += micromips_relative_offset16 (insn);
1857 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1858 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1859 if (((insn >> 16) & 0x3) == 0x0)
1860 /* BC2F, BC2T: don't know how to handle these. */
1864 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1865 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1867 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64;
1868 int dspctl = mips_regnum (gdbarch)->dspctl;
1871 /* No way to handle; it'll most likely trap anyway. */
1874 if ((get_frame_register_unsigned (frame,
1875 dspctl) & 0x7f) >= pos)
1876 pc += micromips_relative_offset16 (insn);
1878 pc += micromips_pc_insn_size (gdbarch, pc);
1882 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1883 /* BC1ANY2F: bits 010000 11100 xxx01 */
1884 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1885 /* BC1ANY2T: bits 010000 11101 xxx01 */
1886 if (((insn >> 16) & 0x2) == 0x0)
1887 pc = micromips_bc1_pc (gdbarch, frame, insn, pc,
1888 ((insn >> 16) & 0x1) + 1);
1891 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1892 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1893 if (((insn >> 16) & 0x3) == 0x1)
1894 pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4);
1899 case 0x1d: /* JALS: bits 011101 */
1900 case 0x35: /* J: bits 110101 */
1901 case 0x3d: /* JAL: bits 111101 */
1902 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1);
1905 case 0x25: /* BEQ: bits 100101 */
1906 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16))
1907 == get_frame_register_signed (frame, b5s5_reg (insn >> 16)))
1908 pc += micromips_relative_offset16 (insn);
1910 pc += micromips_pc_insn_size (gdbarch, pc);
1913 case 0x2d: /* BNE: bits 101101 */
1914 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16))
1915 != get_frame_register_signed (frame, b5s5_reg (insn >> 16)))
1916 pc += micromips_relative_offset16 (insn);
1918 pc += micromips_pc_insn_size (gdbarch, pc);
1921 case 0x3c: /* JALX: bits 111100 */
1922 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2);
1927 /* 16-bit instructions. */
1928 case MIPS_INSN16_SIZE:
1929 switch (micromips_op (insn))
1931 case 0x11: /* POOL16C: bits 010001 */
1932 if ((b5s5_op (insn) & 0x1c) == 0xc)
1933 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1934 pc = get_frame_register_signed (frame, b0s5_reg (insn));
1935 else if (b5s5_op (insn) == 0x18)
1936 /* JRADDIUSP: bits 010001 11000 */
1937 pc = get_frame_register_signed (frame, MIPS_RA_REGNUM);
1940 case 0x23: /* BEQZ16: bits 100011 */
1942 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
1944 if (get_frame_register_signed (frame, rs) == 0)
1945 pc += micromips_relative_offset7 (insn);
1947 pc += micromips_pc_insn_size (gdbarch, pc);
1951 case 0x2b: /* BNEZ16: bits 101011 */
1953 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
1955 if (get_frame_register_signed (frame, rs) != 0)
1956 pc += micromips_relative_offset7 (insn);
1958 pc += micromips_pc_insn_size (gdbarch, pc);
1962 case 0x33: /* B16: bits 110011 */
1963 pc += micromips_relative_offset10 (insn);
1972 /* Decoding the next place to set a breakpoint is irregular for the
1973 mips 16 variant, but fortunately, there fewer instructions. We have
1974 to cope ith extensions for 16 bit instructions and a pair of actual
1975 32 bit instructions. We dont want to set a single step instruction
1976 on the extend instruction either. */
1978 /* Lots of mips16 instruction formats */
1979 /* Predicting jumps requires itype,ritype,i8type
1980 and their extensions extItype,extritype,extI8type. */
1981 enum mips16_inst_fmts
1983 itype, /* 0 immediate 5,10 */
1984 ritype, /* 1 5,3,8 */
1985 rrtype, /* 2 5,3,3,5 */
1986 rritype, /* 3 5,3,3,5 */
1987 rrrtype, /* 4 5,3,3,3,2 */
1988 rriatype, /* 5 5,3,3,1,4 */
1989 shifttype, /* 6 5,3,3,3,2 */
1990 i8type, /* 7 5,3,8 */
1991 i8movtype, /* 8 5,3,3,5 */
1992 i8mov32rtype, /* 9 5,3,5,3 */
1993 i64type, /* 10 5,3,8 */
1994 ri64type, /* 11 5,3,3,5 */
1995 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1996 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1997 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1998 extRRItype, /* 15 5,5,5,5,3,3,5 */
1999 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
2000 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2001 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
2002 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
2003 extRi64type, /* 20 5,6,5,5,3,3,5 */
2004 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2006 /* I am heaping all the fields of the formats into one structure and
2007 then, only the fields which are involved in instruction extension. */
2011 unsigned int regx; /* Function in i8 type. */
2016 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2017 for the bits which make up the immediate extension. */
2020 extended_offset (unsigned int extension)
2024 value = (extension >> 16) & 0x1f; /* Extract 15:11. */
2026 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */
2028 value |= extension & 0x1f; /* Extract 4:0. */
2033 /* Only call this function if you know that this is an extendable
2034 instruction. It won't malfunction, but why make excess remote memory
2035 references? If the immediate operands get sign extended or something,
2036 do it after the extension is performed. */
2037 /* FIXME: Every one of these cases needs to worry about sign extension
2038 when the offset is to be used in relative addressing. */
2041 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc)
2043 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2045 pc &= 0xfffffffe; /* Clear the low order bit. */
2046 target_read_memory (pc, buf, 2);
2047 return extract_unsigned_integer (buf, 2, byte_order);
2051 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc,
2052 unsigned int extension,
2054 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
2059 switch (insn_format)
2066 value = extended_offset ((extension << 16) | inst);
2067 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2071 value = inst & 0x7ff;
2072 value = (value ^ 0x400) - 0x400; /* Sign-extend. */
2081 { /* A register identifier and an offset. */
2082 /* Most of the fields are the same as I type but the
2083 immediate value is of a different length. */
2087 value = extended_offset ((extension << 16) | inst);
2088 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2092 value = inst & 0xff; /* 8 bits */
2093 value = (value ^ 0x80) - 0x80; /* Sign-extend. */
2096 regx = (inst >> 8) & 0x07; /* i8 funct */
2102 unsigned long value;
2103 unsigned int nexthalf;
2104 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
2105 value = value << 16;
2106 nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL);
2107 /* Low bit still set. */
2115 internal_error (__FILE__, __LINE__, _("bad switch"));
2117 upk->offset = offset;
2124 add_offset_16 (CORE_ADDR pc, int offset)
2126 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
2130 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
2131 unsigned int extension, unsigned int insn)
2133 struct gdbarch *gdbarch = get_frame_arch (frame);
2134 int op = (insn >> 11);
2137 case 2: /* Branch */
2139 struct upk_mips16 upk;
2140 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk);
2141 pc += (upk.offset << 1) + 2;
2144 case 3: /* JAL , JALX - Watch out, these are 32 bit
2147 struct upk_mips16 upk;
2148 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk);
2149 pc = add_offset_16 (pc, upk.offset);
2150 if ((insn >> 10) & 0x01) /* Exchange mode */
2151 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */
2158 struct upk_mips16 upk;
2160 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2161 reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]);
2163 pc += (upk.offset << 1) + 2;
2170 struct upk_mips16 upk;
2172 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2173 reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]);
2175 pc += (upk.offset << 1) + 2;
2180 case 12: /* I8 Formats btez btnez */
2182 struct upk_mips16 upk;
2184 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
2185 /* upk.regx contains the opcode */
2186 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
2187 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
2188 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
2189 /* pc = add_offset_16(pc,upk.offset) ; */
2190 pc += (upk.offset << 1) + 2;
2195 case 29: /* RR Formats JR, JALR, JALR-RA */
2197 struct upk_mips16 upk;
2198 /* upk.fmt = rrtype; */
2203 upk.regx = (insn >> 8) & 0x07;
2204 upk.regy = (insn >> 5) & 0x07;
2205 if ((upk.regy & 1) == 0)
2206 reg = mips_reg3_to_reg[upk.regx];
2208 reg = 31; /* Function return instruction. */
2209 pc = get_frame_register_signed (frame, reg);
2216 /* This is an instruction extension. Fetch the real instruction
2217 (which follows the extension) and decode things based on
2221 pc = extended_mips16_next_pc (frame, pc, insn,
2222 fetch_mips_16 (gdbarch, pc));
2235 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
2237 struct gdbarch *gdbarch = get_frame_arch (frame);
2238 unsigned int insn = fetch_mips_16 (gdbarch, pc);
2239 return extended_mips16_next_pc (frame, pc, 0, insn);
2242 /* The mips_next_pc function supports single_step when the remote
2243 target monitor or stub is not developed enough to do a single_step.
2244 It works by decoding the current instruction and predicting where a
2245 branch will go. This isnt hard because all the data is available.
2246 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2248 mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
2250 struct gdbarch *gdbarch = get_frame_arch (frame);
2252 if (mips_pc_is_mips16 (gdbarch, pc))
2253 return mips16_next_pc (frame, pc);
2254 else if (mips_pc_is_micromips (gdbarch, pc))
2255 return micromips_next_pc (frame, pc);
2257 return mips32_next_pc (frame, pc);
2260 struct mips_frame_cache
2263 struct trad_frame_saved_reg *saved_regs;
2266 /* Set a register's saved stack address in temp_saved_regs. If an
2267 address has already been set for this register, do nothing; this
2268 way we will only recognize the first save of a given register in a
2271 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2272 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2273 Strictly speaking, only the second range is used as it is only second
2274 range (the ABI instead of ISA registers) that comes into play when finding
2275 saved registers in a frame. */
2278 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
2279 int regnum, CORE_ADDR offset)
2281 if (this_cache != NULL
2282 && this_cache->saved_regs[regnum].addr == -1)
2284 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
2286 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
2292 /* Fetch the immediate value from a MIPS16 instruction.
2293 If the previous instruction was an EXTEND, use it to extend
2294 the upper bits of the immediate value. This is a helper function
2295 for mips16_scan_prologue. */
2298 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
2299 unsigned short inst, /* current instruction */
2300 int nbits, /* number of bits in imm field */
2301 int scale, /* scale factor to be applied to imm */
2302 int is_signed) /* is the imm field signed? */
2306 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2308 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
2309 if (offset & 0x8000) /* check for negative extend */
2310 offset = 0 - (0x10000 - (offset & 0xffff));
2311 return offset | (inst & 0x1f);
2315 int max_imm = 1 << nbits;
2316 int mask = max_imm - 1;
2317 int sign_bit = max_imm >> 1;
2319 offset = inst & mask;
2320 if (is_signed && (offset & sign_bit))
2321 offset = 0 - (max_imm - offset);
2322 return offset * scale;
2327 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2328 the associated FRAME_CACHE if not null.
2329 Return the address of the first instruction past the prologue. */
2332 mips16_scan_prologue (struct gdbarch *gdbarch,
2333 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2334 struct frame_info *this_frame,
2335 struct mips_frame_cache *this_cache)
2338 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */
2340 long frame_offset = 0; /* Size of stack frame. */
2341 long frame_adjust = 0; /* Offset of FP from SP. */
2342 int frame_reg = MIPS_SP_REGNUM;
2343 unsigned short prev_inst = 0; /* saved copy of previous instruction. */
2344 unsigned inst = 0; /* current instruction */
2345 unsigned entry_inst = 0; /* the entry instruction */
2346 unsigned save_inst = 0; /* the save instruction */
2349 int extend_bytes = 0;
2350 int prev_extend_bytes;
2351 CORE_ADDR end_prologue_addr = 0;
2353 /* Can be called when there's no process, and hence when there's no
2355 if (this_frame != NULL)
2356 sp = get_frame_register_signed (this_frame,
2357 gdbarch_num_regs (gdbarch)
2362 if (limit_pc > start_pc + 200)
2363 limit_pc = start_pc + 200;
2365 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
2367 /* Save the previous instruction. If it's an EXTEND, we'll extract
2368 the immediate offset extension from it in mips16_get_imm. */
2371 /* Fetch and decode the instruction. */
2372 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16,
2375 /* Normally we ignore extend instructions. However, if it is
2376 not followed by a valid prologue instruction, then this
2377 instruction is not part of the prologue either. We must
2378 remember in this case to adjust the end_prologue_addr back
2380 if ((inst & 0xf800) == 0xf000) /* extend */
2382 extend_bytes = MIPS_INSN16_SIZE;
2386 prev_extend_bytes = extend_bytes;
2389 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2390 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2392 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2393 if (offset < 0) /* Negative stack adjustment? */
2394 frame_offset -= offset;
2396 /* Exit loop if a positive stack adjustment is found, which
2397 usually means that the stack cleanup code in the function
2398 epilogue is reached. */
2401 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2403 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2404 reg = mips_reg3_to_reg[(inst & 0x700) >> 8];
2405 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2407 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2409 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2410 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2411 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2413 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2415 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2416 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2418 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2420 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2421 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2423 else if (inst == 0x673d) /* move $s1, $sp */
2428 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2430 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2431 frame_addr = sp + offset;
2433 frame_adjust = offset;
2435 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2437 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2438 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2439 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2441 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2443 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2444 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2445 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2447 else if ((inst & 0xf81f) == 0xe809
2448 && (inst & 0x700) != 0x700) /* entry */
2449 entry_inst = inst; /* Save for later processing. */
2450 else if ((inst & 0xff80) == 0x6480) /* save */
2452 save_inst = inst; /* Save for later processing. */
2453 if (prev_extend_bytes) /* extend */
2454 save_inst |= prev_inst << 16;
2456 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
2457 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
2458 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2460 /* This instruction is part of the prologue, but we don't
2461 need to do anything special to handle it. */
2465 /* This instruction is not an instruction typically found
2466 in a prologue, so we must have reached the end of the
2468 if (end_prologue_addr == 0)
2469 end_prologue_addr = cur_pc - prev_extend_bytes;
2473 /* The entry instruction is typically the first instruction in a function,
2474 and it stores registers at offsets relative to the value of the old SP
2475 (before the prologue). But the value of the sp parameter to this
2476 function is the new SP (after the prologue has been executed). So we
2477 can't calculate those offsets until we've seen the entire prologue,
2478 and can calculate what the old SP must have been. */
2479 if (entry_inst != 0)
2481 int areg_count = (entry_inst >> 8) & 7;
2482 int sreg_count = (entry_inst >> 6) & 3;
2484 /* The entry instruction always subtracts 32 from the SP. */
2487 /* Now we can calculate what the SP must have been at the
2488 start of the function prologue. */
2491 /* Check if a0-a3 were saved in the caller's argument save area. */
2492 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2494 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2495 offset += mips_abi_regsize (gdbarch);
2498 /* Check if the ra register was pushed on the stack. */
2500 if (entry_inst & 0x20)
2502 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2503 offset -= mips_abi_regsize (gdbarch);
2506 /* Check if the s0 and s1 registers were pushed on the stack. */
2507 for (reg = 16; reg < sreg_count + 16; reg++)
2509 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2510 offset -= mips_abi_regsize (gdbarch);
2514 /* The SAVE instruction is similar to ENTRY, except that defined by the
2515 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2516 size of the frame is specified as an immediate field of instruction
2517 and an extended variation exists which lets additional registers and
2518 frame space to be specified. The instruction always treats registers
2519 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2520 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
2522 static int args_table[16] = {
2523 0, 0, 0, 0, 1, 1, 1, 1,
2524 2, 2, 2, 0, 3, 3, 4, -1,
2526 static int astatic_table[16] = {
2527 0, 1, 2, 3, 0, 1, 2, 3,
2528 0, 1, 2, 4, 0, 1, 0, -1,
2530 int aregs = (save_inst >> 16) & 0xf;
2531 int xsregs = (save_inst >> 24) & 0x7;
2532 int args = args_table[aregs];
2533 int astatic = astatic_table[aregs];
2538 warning (_("Invalid number of argument registers encoded in SAVE."));
2543 warning (_("Invalid number of static registers encoded in SAVE."));
2547 /* For standard SAVE the frame size of 0 means 128. */
2548 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
2549 if (frame_size == 0 && (save_inst >> 16) == 0)
2552 frame_offset += frame_size;
2554 /* Now we can calculate what the SP must have been at the
2555 start of the function prologue. */
2558 /* Check if A0-A3 were saved in the caller's argument save area. */
2559 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
2561 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2562 offset += mips_abi_regsize (gdbarch);
2567 /* Check if the RA register was pushed on the stack. */
2568 if (save_inst & 0x40)
2570 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2571 offset -= mips_abi_regsize (gdbarch);
2574 /* Check if the S8 register was pushed on the stack. */
2577 set_reg_offset (gdbarch, this_cache, 30, sp + offset);
2578 offset -= mips_abi_regsize (gdbarch);
2581 /* Check if S2-S7 were pushed on the stack. */
2582 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
2584 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2585 offset -= mips_abi_regsize (gdbarch);
2588 /* Check if the S1 register was pushed on the stack. */
2589 if (save_inst & 0x10)
2591 set_reg_offset (gdbarch, this_cache, 17, sp + offset);
2592 offset -= mips_abi_regsize (gdbarch);
2594 /* Check if the S0 register was pushed on the stack. */
2595 if (save_inst & 0x20)
2597 set_reg_offset (gdbarch, this_cache, 16, sp + offset);
2598 offset -= mips_abi_regsize (gdbarch);
2601 /* Check if A0-A3 were pushed on the stack. */
2602 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
2604 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2605 offset -= mips_abi_regsize (gdbarch);
2609 if (this_cache != NULL)
2612 (get_frame_register_signed (this_frame,
2613 gdbarch_num_regs (gdbarch) + frame_reg)
2614 + frame_offset - frame_adjust);
2615 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2616 be able to get rid of the assignment below, evetually. But it's
2617 still needed for now. */
2618 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2619 + mips_regnum (gdbarch)->pc]
2620 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
2623 /* If we didn't reach the end of the prologue when scanning the function
2624 instructions, then set end_prologue_addr to the address of the
2625 instruction immediately after the last one we scanned. */
2626 if (end_prologue_addr == 0)
2627 end_prologue_addr = cur_pc;
2629 return end_prologue_addr;
2632 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2633 Procedures that use the 32-bit instruction set are handled by the
2634 mips_insn32 unwinder. */
2636 static struct mips_frame_cache *
2637 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
2639 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2640 struct mips_frame_cache *cache;
2642 if ((*this_cache) != NULL)
2643 return (*this_cache);
2644 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2645 (*this_cache) = cache;
2646 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2648 /* Analyze the function prologue. */
2650 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2651 CORE_ADDR start_addr;
2653 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2654 if (start_addr == 0)
2655 start_addr = heuristic_proc_start (gdbarch, pc);
2656 /* We can't analyze the prologue if we couldn't find the begining
2658 if (start_addr == 0)
2661 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
2664 /* gdbarch_sp_regnum contains the value and not the address. */
2665 trad_frame_set_value (cache->saved_regs,
2666 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
2669 return (*this_cache);
2673 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
2674 struct frame_id *this_id)
2676 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2678 /* This marks the outermost frame. */
2679 if (info->base == 0)
2681 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2684 static struct value *
2685 mips_insn16_frame_prev_register (struct frame_info *this_frame,
2686 void **this_cache, int regnum)
2688 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2690 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2694 mips_insn16_frame_sniffer (const struct frame_unwind *self,
2695 struct frame_info *this_frame, void **this_cache)
2697 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2698 CORE_ADDR pc = get_frame_pc (this_frame);
2699 if (mips_pc_is_mips16 (gdbarch, pc))
2704 static const struct frame_unwind mips_insn16_frame_unwind =
2707 default_frame_unwind_stop_reason,
2708 mips_insn16_frame_this_id,
2709 mips_insn16_frame_prev_register,
2711 mips_insn16_frame_sniffer
2715 mips_insn16_frame_base_address (struct frame_info *this_frame,
2718 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2723 static const struct frame_base mips_insn16_frame_base =
2725 &mips_insn16_frame_unwind,
2726 mips_insn16_frame_base_address,
2727 mips_insn16_frame_base_address,
2728 mips_insn16_frame_base_address
2731 static const struct frame_base *
2732 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
2734 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2735 CORE_ADDR pc = get_frame_pc (this_frame);
2736 if (mips_pc_is_mips16 (gdbarch, pc))
2737 return &mips_insn16_frame_base;
2742 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2743 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2744 interpreted directly, and then multiplied by 4. */
2747 micromips_decode_imm9 (int imm)
2749 imm = (imm ^ 0x100) - 0x100;
2750 if (imm > -3 && imm < 2)
2755 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2756 the address of the first instruction past the prologue. */
2759 micromips_scan_prologue (struct gdbarch *gdbarch,
2760 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2761 struct frame_info *this_frame,
2762 struct mips_frame_cache *this_cache)
2764 CORE_ADDR end_prologue_addr = 0;
2765 int prev_non_prologue_insn = 0;
2766 int frame_reg = MIPS_SP_REGNUM;
2767 int this_non_prologue_insn;
2768 int non_prologue_insns = 0;
2769 long frame_offset = 0; /* Size of stack frame. */
2770 long frame_adjust = 0; /* Offset of FP from SP. */
2771 CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */
2774 ULONGEST insn; /* current instruction */
2778 long v1_off = 0; /* The assumption is LUI will replace it. */
2789 /* Can be called when there's no process, and hence when there's no
2791 if (this_frame != NULL)
2792 sp = get_frame_register_signed (this_frame,
2793 gdbarch_num_regs (gdbarch)
2798 if (limit_pc > start_pc + 200)
2799 limit_pc = start_pc + 200;
2802 /* Permit at most one non-prologue non-control-transfer instruction
2803 in the middle which may have been reordered by the compiler for
2805 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc)
2807 this_non_prologue_insn = 0;
2810 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL);
2811 loc += MIPS_INSN16_SIZE;
2812 switch (mips_insn_size (ISA_MICROMIPS, insn))
2814 /* 48-bit instructions. */
2815 case 3 * MIPS_INSN16_SIZE:
2816 /* No prologue instructions in this category. */
2817 this_non_prologue_insn = 1;
2818 loc += 2 * MIPS_INSN16_SIZE;
2821 /* 32-bit instructions. */
2822 case 2 * MIPS_INSN16_SIZE:
2824 insn |= mips_fetch_instruction (gdbarch,
2825 ISA_MICROMIPS, cur_pc + loc, NULL);
2826 loc += MIPS_INSN16_SIZE;
2827 switch (micromips_op (insn >> 16))
2829 /* Record $sp/$fp adjustment. */
2830 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2831 case 0x0: /* POOL32A: bits 000000 */
2832 case 0x16: /* POOL32S: bits 010110 */
2833 op = b0s11_op (insn);
2834 sreg = b0s5_reg (insn >> 16);
2835 treg = b5s5_reg (insn >> 16);
2836 dreg = b11s5_reg (insn);
2838 /* SUBU: bits 000000 00111010000 */
2839 /* DSUBU: bits 010110 00111010000 */
2840 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM
2842 /* (D)SUBU $sp, $v1 */
2844 else if (op != 0x150
2845 /* ADDU: bits 000000 00101010000 */
2846 /* DADDU: bits 010110 00101010000 */
2847 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM)
2848 this_non_prologue_insn = 1;
2851 case 0x8: /* POOL32B: bits 001000 */
2852 op = b12s4_op (insn);
2853 breg = b0s5_reg (insn >> 16);
2854 reglist = sreg = b5s5_reg (insn >> 16);
2855 offset = (b0s12_imm (insn) ^ 0x800) - 0x800;
2856 if ((op == 0x9 || op == 0xc)
2857 /* SWP: bits 001000 1001 */
2858 /* SDP: bits 001000 1100 */
2859 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM)
2860 /* S[DW]P reg,offset($sp) */
2862 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4);
2863 set_reg_offset (gdbarch, this_cache,
2865 set_reg_offset (gdbarch, this_cache,
2866 sreg + 1, sp + offset + s);
2868 else if ((op == 0xd || op == 0xf)
2869 /* SWM: bits 001000 1101 */
2870 /* SDM: bits 001000 1111 */
2871 && breg == MIPS_SP_REGNUM
2872 /* SWM reglist,offset($sp) */
2873 && ((reglist >= 1 && reglist <= 9)
2874 || (reglist >= 16 && reglist <= 25)))
2876 int sreglist = min(reglist & 0xf, 8);
2878 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2);
2879 for (i = 0; i < sreglist; i++)
2880 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i);
2881 if ((reglist & 0xf) > 8)
2882 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++);
2883 if ((reglist & 0x10) == 0x10)
2884 set_reg_offset (gdbarch, this_cache,
2885 MIPS_RA_REGNUM, sp + s * i++);
2888 this_non_prologue_insn = 1;
2891 /* Record $sp/$fp adjustment. */
2892 /* Discard (D)ADDIU $gp used for PIC code. */
2893 case 0xc: /* ADDIU: bits 001100 */
2894 case 0x17: /* DADDIU: bits 010111 */
2895 sreg = b0s5_reg (insn >> 16);
2896 dreg = b5s5_reg (insn >> 16);
2897 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
2898 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM)
2899 /* (D)ADDIU $sp, imm */
2901 else if (sreg == MIPS_SP_REGNUM && dreg == 30)
2902 /* (D)ADDIU $fp, $sp, imm */
2904 frame_addr = sp + offset;
2905 frame_adjust = offset;
2908 else if (sreg != 28 || dreg != 28)
2909 /* (D)ADDIU $gp, imm */
2910 this_non_prologue_insn = 1;
2913 /* LUI $v1 is used for larger $sp adjustments. */
2914 /* Discard LUI $gp is used for PIC code. */
2915 case 0x10: /* POOL32I: bits 010000 */
2916 if (b5s5_op (insn >> 16) == 0xd
2917 /* LUI: bits 010000 001101 */
2918 && b0s5_reg (insn >> 16) == 3)
2920 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000;
2921 else if (b5s5_op (insn >> 16) != 0xd
2922 /* LUI: bits 010000 001101 */
2923 || b0s5_reg (insn >> 16) != 28)
2925 this_non_prologue_insn = 1;
2928 /* ORI $v1 is used for larger $sp adjustments. */
2929 case 0x14: /* ORI: bits 010100 */
2930 sreg = b0s5_reg (insn >> 16);
2931 dreg = b5s5_reg (insn >> 16);
2932 if (sreg == 3 && dreg == 3)
2934 v1_off |= b0s16_imm (insn);
2936 this_non_prologue_insn = 1;
2939 case 0x26: /* SWC1: bits 100110 */
2940 case 0x2e: /* SDC1: bits 101110 */
2941 breg = b0s5_reg (insn >> 16);
2942 if (breg != MIPS_SP_REGNUM)
2943 /* S[DW]C1 reg,offset($sp) */
2944 this_non_prologue_insn = 1;
2947 case 0x36: /* SD: bits 110110 */
2948 case 0x3e: /* SW: bits 111110 */
2949 breg = b0s5_reg (insn >> 16);
2950 sreg = b5s5_reg (insn >> 16);
2951 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
2952 if (breg == MIPS_SP_REGNUM)
2953 /* S[DW] reg,offset($sp) */
2954 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
2956 this_non_prologue_insn = 1;
2960 this_non_prologue_insn = 1;
2965 /* 16-bit instructions. */
2966 case MIPS_INSN16_SIZE:
2967 switch (micromips_op (insn))
2969 case 0x3: /* MOVE: bits 000011 */
2970 sreg = b0s5_reg (insn);
2971 dreg = b5s5_reg (insn);
2972 if (sreg == MIPS_SP_REGNUM && dreg == 30)
2978 else if ((sreg & 0x1c) != 0x4)
2979 /* MOVE reg, $a0-$a3 */
2980 this_non_prologue_insn = 1;
2983 case 0x11: /* POOL16C: bits 010001 */
2984 if (b6s4_op (insn) == 0x5)
2985 /* SWM: bits 010001 0101 */
2987 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20;
2988 reglist = b4s2_regl (insn);
2989 for (i = 0; i <= reglist; i++)
2990 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i);
2991 set_reg_offset (gdbarch, this_cache,
2992 MIPS_RA_REGNUM, sp + 4 * i++);
2995 this_non_prologue_insn = 1;
2998 case 0x13: /* POOL16D: bits 010011 */
2999 if ((insn & 0x1) == 0x1)
3000 /* ADDIUSP: bits 010011 1 */
3001 sp_adj = micromips_decode_imm9 (b1s9_imm (insn));
3002 else if (b5s5_reg (insn) == MIPS_SP_REGNUM)
3003 /* ADDIUS5: bits 010011 0 */
3004 /* ADDIUS5 $sp, imm */
3005 sp_adj = (b1s4_imm (insn) ^ 8) - 8;
3007 this_non_prologue_insn = 1;
3010 case 0x32: /* SWSP: bits 110010 */
3011 offset = b0s5_imm (insn) << 2;
3012 sreg = b5s5_reg (insn);
3013 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
3017 this_non_prologue_insn = 1;
3023 frame_offset -= sp_adj;
3025 non_prologue_insns += this_non_prologue_insn;
3026 /* Enough non-prologue insns seen or positive stack adjustment? */
3027 if (end_prologue_addr == 0 && (non_prologue_insns > 1 || sp_adj > 0))
3029 end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc;
3032 prev_non_prologue_insn = this_non_prologue_insn;
3036 if (this_cache != NULL)
3039 (get_frame_register_signed (this_frame,
3040 gdbarch_num_regs (gdbarch) + frame_reg)
3041 + frame_offset - frame_adjust);
3042 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3043 be able to get rid of the assignment below, evetually. But it's
3044 still needed for now. */
3045 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3046 + mips_regnum (gdbarch)->pc]
3047 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
3050 /* If we didn't reach the end of the prologue when scanning the function
3051 instructions, then set end_prologue_addr to the address of the
3052 instruction immediately after the last one we scanned. Unless the
3053 last one looked like a non-prologue instruction (and we looked ahead),
3054 in which case use its address instead. */
3055 if (end_prologue_addr == 0)
3056 end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc;
3058 return end_prologue_addr;
3061 /* Heuristic unwinder for procedures using microMIPS instructions.
3062 Procedures that use the 32-bit instruction set are handled by the
3063 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3065 static struct mips_frame_cache *
3066 mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache)
3068 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3069 struct mips_frame_cache *cache;
3071 if ((*this_cache) != NULL)
3072 return (*this_cache);
3074 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3075 (*this_cache) = cache;
3076 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3078 /* Analyze the function prologue. */
3080 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3081 CORE_ADDR start_addr;
3083 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3084 if (start_addr == 0)
3085 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc);
3086 /* We can't analyze the prologue if we couldn't find the begining
3088 if (start_addr == 0)
3091 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
3094 /* gdbarch_sp_regnum contains the value and not the address. */
3095 trad_frame_set_value (cache->saved_regs,
3096 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3099 return (*this_cache);
3103 mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache,
3104 struct frame_id *this_id)
3106 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3108 /* This marks the outermost frame. */
3109 if (info->base == 0)
3111 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3114 static struct value *
3115 mips_micro_frame_prev_register (struct frame_info *this_frame,
3116 void **this_cache, int regnum)
3118 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3120 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3124 mips_micro_frame_sniffer (const struct frame_unwind *self,
3125 struct frame_info *this_frame, void **this_cache)
3127 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3128 CORE_ADDR pc = get_frame_pc (this_frame);
3130 if (mips_pc_is_micromips (gdbarch, pc))
3135 static const struct frame_unwind mips_micro_frame_unwind =
3138 default_frame_unwind_stop_reason,
3139 mips_micro_frame_this_id,
3140 mips_micro_frame_prev_register,
3142 mips_micro_frame_sniffer
3146 mips_micro_frame_base_address (struct frame_info *this_frame,
3149 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3154 static const struct frame_base mips_micro_frame_base =
3156 &mips_micro_frame_unwind,
3157 mips_micro_frame_base_address,
3158 mips_micro_frame_base_address,
3159 mips_micro_frame_base_address
3162 static const struct frame_base *
3163 mips_micro_frame_base_sniffer (struct frame_info *this_frame)
3165 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3166 CORE_ADDR pc = get_frame_pc (this_frame);
3168 if (mips_pc_is_micromips (gdbarch, pc))
3169 return &mips_micro_frame_base;
3174 /* Mark all the registers as unset in the saved_regs array
3175 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3178 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
3180 if (this_cache == NULL || this_cache->saved_regs == NULL)
3184 const int num_regs = gdbarch_num_regs (gdbarch);
3187 for (i = 0; i < num_regs; i++)
3189 this_cache->saved_regs[i].addr = -1;
3194 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3195 the associated FRAME_CACHE if not null.
3196 Return the address of the first instruction past the prologue. */
3199 mips32_scan_prologue (struct gdbarch *gdbarch,
3200 CORE_ADDR start_pc, CORE_ADDR limit_pc,
3201 struct frame_info *this_frame,
3202 struct mips_frame_cache *this_cache)
3205 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for
3209 int frame_reg = MIPS_SP_REGNUM;
3211 CORE_ADDR end_prologue_addr = 0;
3212 int seen_sp_adjust = 0;
3213 int load_immediate_bytes = 0;
3214 int in_delay_slot = 0;
3215 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
3217 /* Can be called when there's no process, and hence when there's no
3219 if (this_frame != NULL)
3220 sp = get_frame_register_signed (this_frame,
3221 gdbarch_num_regs (gdbarch)
3226 if (limit_pc > start_pc + 200)
3227 limit_pc = start_pc + 200;
3232 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
3234 unsigned long inst, high_word, low_word;
3237 /* Fetch the instruction. */
3238 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS,
3241 /* Save some code by pre-extracting some useful fields. */
3242 high_word = (inst >> 16) & 0xffff;
3243 low_word = inst & 0xffff;
3244 reg = high_word & 0x1f;
3246 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
3247 || high_word == 0x23bd /* addi $sp,$sp,-i */
3248 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
3250 if (low_word & 0x8000) /* Negative stack adjustment? */
3251 frame_offset += 0x10000 - low_word;
3253 /* Exit loop if a positive stack adjustment is found, which
3254 usually means that the stack cleanup code in the function
3255 epilogue is reached. */
3259 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3260 && !regsize_is_64_bits)
3262 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
3264 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3265 && regsize_is_64_bits)
3267 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3268 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
3270 else if (high_word == 0x27be) /* addiu $30,$sp,size */
3272 /* Old gcc frame, r30 is virtual frame pointer. */
3273 if ((long) low_word != frame_offset)
3274 frame_addr = sp + low_word;
3275 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
3277 unsigned alloca_adjust;
3280 frame_addr = get_frame_register_signed
3281 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3284 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
3285 if (alloca_adjust > 0)
3287 /* FP > SP + frame_size. This may be because of
3288 an alloca or somethings similar. Fix sp to
3289 "pre-alloca" value, and try again. */
3290 sp += alloca_adjust;
3291 /* Need to reset the status of all registers. Otherwise,
3292 we will hit a guard that prevents the new address
3293 for each register to be recomputed during the second
3295 reset_saved_regs (gdbarch, this_cache);
3300 /* move $30,$sp. With different versions of gas this will be either
3301 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3302 Accept any one of these. */
3303 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3305 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3306 if (this_frame && frame_reg == MIPS_SP_REGNUM)
3308 unsigned alloca_adjust;
3311 frame_addr = get_frame_register_signed
3312 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3314 alloca_adjust = (unsigned) (frame_addr - sp);
3315 if (alloca_adjust > 0)
3317 /* FP > SP + frame_size. This may be because of
3318 an alloca or somethings similar. Fix sp to
3319 "pre-alloca" value, and try again. */
3321 /* Need to reset the status of all registers. Otherwise,
3322 we will hit a guard that prevents the new address
3323 for each register to be recomputed during the second
3325 reset_saved_regs (gdbarch, this_cache);
3330 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3331 && !regsize_is_64_bits)
3333 set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word);
3335 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3336 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3337 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3338 || high_word == 0x3c1c /* lui $gp,n */
3339 || high_word == 0x279c /* addiu $gp,$gp,n */
3340 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3341 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
3344 /* These instructions are part of the prologue, but we don't
3345 need to do anything special to handle them. */
3347 /* The instructions below load $at or $t0 with an immediate
3348 value in preparation for a stack adjustment via
3349 subu $sp,$sp,[$at,$t0]. These instructions could also
3350 initialize a local variable, so we accept them only before
3351 a stack adjustment instruction was seen. */
3352 else if (!seen_sp_adjust
3353 && (high_word == 0x3c01 /* lui $at,n */
3354 || high_word == 0x3c08 /* lui $t0,n */
3355 || high_word == 0x3421 /* ori $at,$at,n */
3356 || high_word == 0x3508 /* ori $t0,$t0,n */
3357 || high_word == 0x3401 /* ori $at,$zero,n */
3358 || high_word == 0x3408 /* ori $t0,$zero,n */
3361 if (end_prologue_addr == 0)
3362 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
3366 /* This instruction is not an instruction typically found
3367 in a prologue, so we must have reached the end of the
3369 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3370 loop now? Why would we need to continue scanning the function
3372 if (end_prologue_addr == 0)
3373 end_prologue_addr = cur_pc;
3375 /* Check for branches and jumps. For now, only jump to
3376 register are caught (i.e. returns). */
3377 if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8)
3381 /* If the previous instruction was a jump, we must have reached
3382 the end of the prologue by now. Stop scanning so that we do
3383 not go past the function return. */
3388 if (this_cache != NULL)
3391 (get_frame_register_signed (this_frame,
3392 gdbarch_num_regs (gdbarch) + frame_reg)
3394 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3395 this assignment below, eventually. But it's still needed
3397 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3398 + mips_regnum (gdbarch)->pc]
3399 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3403 /* If we didn't reach the end of the prologue when scanning the function
3404 instructions, then set end_prologue_addr to the address of the
3405 instruction immediately after the last one we scanned. */
3406 /* brobecker/2004-10-10: I don't think this would ever happen, but
3407 we may as well be careful and do our best if we have a null
3408 end_prologue_addr. */
3409 if (end_prologue_addr == 0)
3410 end_prologue_addr = cur_pc;
3412 /* In a frameless function, we might have incorrectly
3413 skipped some load immediate instructions. Undo the skipping
3414 if the load immediate was not followed by a stack adjustment. */
3415 if (load_immediate_bytes && !seen_sp_adjust)
3416 end_prologue_addr -= load_immediate_bytes;
3418 return end_prologue_addr;
3421 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3422 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3423 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3424 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3426 static struct mips_frame_cache *
3427 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
3429 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3430 struct mips_frame_cache *cache;
3432 if ((*this_cache) != NULL)
3433 return (*this_cache);
3435 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3436 (*this_cache) = cache;
3437 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3439 /* Analyze the function prologue. */
3441 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3442 CORE_ADDR start_addr;
3444 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3445 if (start_addr == 0)
3446 start_addr = heuristic_proc_start (gdbarch, pc);
3447 /* We can't analyze the prologue if we couldn't find the begining
3449 if (start_addr == 0)
3452 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
3455 /* gdbarch_sp_regnum contains the value and not the address. */
3456 trad_frame_set_value (cache->saved_regs,
3457 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3460 return (*this_cache);
3464 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
3465 struct frame_id *this_id)
3467 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3469 /* This marks the outermost frame. */
3470 if (info->base == 0)
3472 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3475 static struct value *
3476 mips_insn32_frame_prev_register (struct frame_info *this_frame,
3477 void **this_cache, int regnum)
3479 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3481 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3485 mips_insn32_frame_sniffer (const struct frame_unwind *self,
3486 struct frame_info *this_frame, void **this_cache)
3488 CORE_ADDR pc = get_frame_pc (this_frame);
3489 if (mips_pc_is_mips (pc))
3494 static const struct frame_unwind mips_insn32_frame_unwind =
3497 default_frame_unwind_stop_reason,
3498 mips_insn32_frame_this_id,
3499 mips_insn32_frame_prev_register,
3501 mips_insn32_frame_sniffer
3505 mips_insn32_frame_base_address (struct frame_info *this_frame,
3508 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3513 static const struct frame_base mips_insn32_frame_base =
3515 &mips_insn32_frame_unwind,
3516 mips_insn32_frame_base_address,
3517 mips_insn32_frame_base_address,
3518 mips_insn32_frame_base_address
3521 static const struct frame_base *
3522 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
3524 CORE_ADDR pc = get_frame_pc (this_frame);
3525 if (mips_pc_is_mips (pc))
3526 return &mips_insn32_frame_base;
3531 static struct trad_frame_cache *
3532 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
3535 CORE_ADDR start_addr;
3536 CORE_ADDR stack_addr;
3537 struct trad_frame_cache *this_trad_cache;
3538 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3539 int num_regs = gdbarch_num_regs (gdbarch);
3541 if ((*this_cache) != NULL)
3542 return (*this_cache);
3543 this_trad_cache = trad_frame_cache_zalloc (this_frame);
3544 (*this_cache) = this_trad_cache;
3546 /* The return address is in the link register. */
3547 trad_frame_set_reg_realreg (this_trad_cache,
3548 gdbarch_pc_regnum (gdbarch),
3549 num_regs + MIPS_RA_REGNUM);
3551 /* Frame ID, since it's a frameless / stackless function, no stack
3552 space is allocated and SP on entry is the current SP. */
3553 pc = get_frame_pc (this_frame);
3554 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3555 stack_addr = get_frame_register_signed (this_frame,
3556 num_regs + MIPS_SP_REGNUM);
3557 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
3559 /* Assume that the frame's base is the same as the
3561 trad_frame_set_this_base (this_trad_cache, stack_addr);
3563 return this_trad_cache;
3567 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
3568 struct frame_id *this_id)
3570 struct trad_frame_cache *this_trad_cache
3571 = mips_stub_frame_cache (this_frame, this_cache);
3572 trad_frame_get_id (this_trad_cache, this_id);
3575 static struct value *
3576 mips_stub_frame_prev_register (struct frame_info *this_frame,
3577 void **this_cache, int regnum)
3579 struct trad_frame_cache *this_trad_cache
3580 = mips_stub_frame_cache (this_frame, this_cache);
3581 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
3585 mips_stub_frame_sniffer (const struct frame_unwind *self,
3586 struct frame_info *this_frame, void **this_cache)
3589 struct obj_section *s;
3590 CORE_ADDR pc = get_frame_address_in_block (this_frame);
3591 struct bound_minimal_symbol msym;
3593 /* Use the stub unwinder for unreadable code. */
3594 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
3597 if (in_plt_section (pc) || in_mips_stubs_section (pc))
3600 /* Calling a PIC function from a non-PIC function passes through a
3601 stub. The stub for foo is named ".pic.foo". */
3602 msym = lookup_minimal_symbol_by_pc (pc);
3603 if (msym.minsym != NULL
3604 && SYMBOL_LINKAGE_NAME (msym.minsym) != NULL
3605 && strncmp (SYMBOL_LINKAGE_NAME (msym.minsym), ".pic.", 5) == 0)
3611 static const struct frame_unwind mips_stub_frame_unwind =
3614 default_frame_unwind_stop_reason,
3615 mips_stub_frame_this_id,
3616 mips_stub_frame_prev_register,
3618 mips_stub_frame_sniffer
3622 mips_stub_frame_base_address (struct frame_info *this_frame,
3625 struct trad_frame_cache *this_trad_cache
3626 = mips_stub_frame_cache (this_frame, this_cache);
3627 return trad_frame_get_this_base (this_trad_cache);
3630 static const struct frame_base mips_stub_frame_base =
3632 &mips_stub_frame_unwind,
3633 mips_stub_frame_base_address,
3634 mips_stub_frame_base_address,
3635 mips_stub_frame_base_address
3638 static const struct frame_base *
3639 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
3641 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
3642 return &mips_stub_frame_base;
3647 /* mips_addr_bits_remove - remove useless address bits */
3650 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
3652 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3654 if (is_compact_addr (addr))
3655 addr = unmake_compact_addr (addr);
3657 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
3658 /* This hack is a work-around for existing boards using PMON, the
3659 simulator, and any other 64-bit targets that doesn't have true
3660 64-bit addressing. On these targets, the upper 32 bits of
3661 addresses are ignored by the hardware. Thus, the PC or SP are
3662 likely to have been sign extended to all 1s by instruction
3663 sequences that load 32-bit addresses. For example, a typical
3664 piece of code that loads an address is this:
3666 lui $r2, <upper 16 bits>
3667 ori $r2, <lower 16 bits>
3669 But the lui sign-extends the value such that the upper 32 bits
3670 may be all 1s. The workaround is simply to mask off these
3671 bits. In the future, gcc may be changed to support true 64-bit
3672 addressing, and this masking will have to be disabled. */
3673 return addr &= 0xffffffffUL;
3679 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3680 instruction and ending with a SC/SCD instruction. If such a sequence
3681 is found, attempt to step through it. A breakpoint is placed at the end of
3684 /* Instructions used during single-stepping of atomic sequences, standard
3686 #define LL_OPCODE 0x30
3687 #define LLD_OPCODE 0x34
3688 #define SC_OPCODE 0x38
3689 #define SCD_OPCODE 0x3c
3692 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
3693 struct address_space *aspace, CORE_ADDR pc)
3695 CORE_ADDR breaks[2] = {-1, -1};
3697 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
3701 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
3702 const int atomic_sequence_length = 16; /* Instruction sequence length. */
3704 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3705 /* Assume all atomic sequences start with a ll/lld instruction. */
3706 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
3709 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3711 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
3714 loc += MIPS_INSN32_SIZE;
3715 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3717 /* Assume that there is at most one branch in the atomic
3718 sequence. If a branch is found, put a breakpoint in its
3719 destination address. */
3720 switch (itype_op (insn))
3722 case 0: /* SPECIAL */
3723 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
3724 return 0; /* fallback to the standard single-step code. */
3726 case 1: /* REGIMM */
3727 is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */
3728 || ((itype_rt (insn) & 0x1e) == 0
3729 && itype_rs (insn) == 0)); /* BPOSGE* */
3733 return 0; /* fallback to the standard single-step code. */
3740 case 22: /* BLEZL */
3741 case 23: /* BGTTL */
3745 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10)
3746 && (itype_rt (insn) & 0x2) == 0);
3747 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3752 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3757 branch_bp = loc + mips32_relative_offset (insn) + 4;
3758 if (last_breakpoint >= 1)
3759 return 0; /* More than one branch found, fallback to the
3760 standard single-step code. */
3761 breaks[1] = branch_bp;
3765 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
3769 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3770 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
3773 loc += MIPS_INSN32_SIZE;
3775 /* Insert a breakpoint right after the end of the atomic sequence. */
3778 /* Check for duplicated breakpoints. Check also for a breakpoint
3779 placed (branch instruction's destination) in the atomic sequence. */
3780 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
3781 last_breakpoint = 0;
3783 /* Effectively inserts the breakpoints. */
3784 for (index = 0; index <= last_breakpoint; index++)
3785 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
3791 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
3792 struct address_space *aspace,
3795 const int atomic_sequence_length = 16; /* Instruction sequence length. */
3796 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
3797 CORE_ADDR breaks[2] = {-1, -1};
3798 CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's
3806 /* Assume all atomic sequences start with a ll/lld instruction. */
3807 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
3808 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */
3810 loc += MIPS_INSN16_SIZE;
3812 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
3813 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3815 loc += MIPS_INSN16_SIZE;
3817 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3818 that no atomic sequence is longer than "atomic_sequence_length"
3820 for (insn_count = 0;
3821 !sc_found && insn_count < atomic_sequence_length;
3826 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
3827 loc += MIPS_INSN16_SIZE;
3829 /* Assume that there is at most one conditional branch in the
3830 atomic sequence. If a branch is found, put a breakpoint in
3831 its destination address. */
3832 switch (mips_insn_size (ISA_MICROMIPS, insn))
3834 /* 48-bit instructions. */
3835 case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
3836 loc += 2 * MIPS_INSN16_SIZE;
3839 /* 32-bit instructions. */
3840 case 2 * MIPS_INSN16_SIZE:
3841 switch (micromips_op (insn))
3843 case 0x10: /* POOL32I: bits 010000 */
3844 if ((b5s5_op (insn) & 0x18) != 0x0
3845 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3846 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3847 && (b5s5_op (insn) & 0x1d) != 0x11
3848 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3849 && ((b5s5_op (insn) & 0x1e) != 0x14
3850 || (insn & 0x3) != 0x0)
3851 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3852 && (b5s5_op (insn) & 0x1e) != 0x1a
3853 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3854 && ((b5s5_op (insn) & 0x1e) != 0x1c
3855 || (insn & 0x3) != 0x0)
3856 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3857 && ((b5s5_op (insn) & 0x1c) != 0x1c
3858 || (insn & 0x3) != 0x1))
3859 /* BC1ANY*: bits 010000 111xx xxx01 */
3863 case 0x25: /* BEQ: bits 100101 */
3864 case 0x2d: /* BNE: bits 101101 */
3866 insn |= mips_fetch_instruction (gdbarch,
3867 ISA_MICROMIPS, loc, NULL);
3868 branch_bp = (loc + MIPS_INSN16_SIZE
3869 + micromips_relative_offset16 (insn));
3873 case 0x00: /* POOL32A: bits 000000 */
3875 insn |= mips_fetch_instruction (gdbarch,
3876 ISA_MICROMIPS, loc, NULL);
3877 if (b0s6_op (insn) != 0x3c
3878 /* POOL32Axf: bits 000000 ... 111100 */
3879 || (b6s10_ext (insn) & 0x2bf) != 0x3c)
3880 /* JALR, JALR.HB: 000000 000x111100 111100 */
3881 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3885 case 0x1d: /* JALS: bits 011101 */
3886 case 0x35: /* J: bits 110101 */
3887 case 0x3d: /* JAL: bits 111101 */
3888 case 0x3c: /* JALX: bits 111100 */
3889 return 0; /* Fall back to the standard single-step code. */
3891 case 0x18: /* POOL32C: bits 011000 */
3892 if ((b12s4_op (insn) & 0xb) == 0xb)
3893 /* SC, SCD: bits 011000 1x11 */
3897 loc += MIPS_INSN16_SIZE;
3900 /* 16-bit instructions. */
3901 case MIPS_INSN16_SIZE:
3902 switch (micromips_op (insn))
3904 case 0x23: /* BEQZ16: bits 100011 */
3905 case 0x2b: /* BNEZ16: bits 101011 */
3906 branch_bp = loc + micromips_relative_offset7 (insn);
3910 case 0x11: /* POOL16C: bits 010001 */
3911 if ((b5s5_op (insn) & 0x1c) != 0xc
3912 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3913 && b5s5_op (insn) != 0x18)
3914 /* JRADDIUSP: bits 010001 11000 */
3916 return 0; /* Fall back to the standard single-step code. */
3918 case 0x33: /* B16: bits 110011 */
3919 return 0; /* Fall back to the standard single-step code. */
3925 if (last_breakpoint >= 1)
3926 return 0; /* More than one branch found, fallback to the
3927 standard single-step code. */
3928 breaks[1] = branch_bp;
3935 /* Insert a breakpoint right after the end of the atomic sequence. */
3938 /* Check for duplicated breakpoints. Check also for a breakpoint
3939 placed (branch instruction's destination) in the atomic sequence */
3940 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
3941 last_breakpoint = 0;
3943 /* Effectively inserts the breakpoints. */
3944 for (index = 0; index <= last_breakpoint; index++)
3945 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
3951 deal_with_atomic_sequence (struct gdbarch *gdbarch,
3952 struct address_space *aspace, CORE_ADDR pc)
3954 if (mips_pc_is_mips (pc))
3955 return mips_deal_with_atomic_sequence (gdbarch, aspace, pc);
3956 else if (mips_pc_is_micromips (gdbarch, pc))
3957 return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc);
3962 /* mips_software_single_step() is called just before we want to resume
3963 the inferior, if we want to single-step it but there is no hardware
3964 or kernel single-step support (MIPS on GNU/Linux for example). We find
3965 the target of the coming instruction and breakpoint it. */
3968 mips_software_single_step (struct frame_info *frame)
3970 struct gdbarch *gdbarch = get_frame_arch (frame);
3971 struct address_space *aspace = get_frame_address_space (frame);
3972 CORE_ADDR pc, next_pc;
3974 pc = get_frame_pc (frame);
3975 if (deal_with_atomic_sequence (gdbarch, aspace, pc))
3978 next_pc = mips_next_pc (frame, pc);
3980 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
3984 /* Test whether the PC points to the return instruction at the
3985 end of a function. */
3988 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
3993 /* This used to check for MIPS16, but this piece of code is never
3994 called for MIPS16 functions. And likewise microMIPS ones. */
3995 gdb_assert (mips_pc_is_mips (pc));
3997 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
3999 return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */
4003 /* This fencepost looks highly suspicious to me. Removing it also
4004 seems suspicious as it could affect remote debugging across serial
4008 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
4014 struct inferior *inf;
4016 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4018 fence = start_pc - heuristic_fence_post;
4022 if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS)
4023 fence = VM_MIN_ADDRESS;
4025 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE;
4027 inf = current_inferior ();
4029 /* Search back for previous return. */
4030 for (start_pc -= instlen;; start_pc -= instlen)
4031 if (start_pc < fence)
4033 /* It's not clear to me why we reach this point when
4034 stop_soon, but with this test, at least we
4035 don't print out warnings for every child forked (eg, on
4036 decstation). 22apr93 rich@cygnus.com. */
4037 if (inf->control.stop_soon == NO_STOP_QUIETLY)
4039 static int blurb_printed = 0;
4041 warning (_("GDB can't find the start of the function at %s."),
4042 paddress (gdbarch, pc));
4046 /* This actually happens frequently in embedded
4047 development, when you first connect to a board
4048 and your stack pointer and pc are nowhere in
4049 particular. This message needs to give people
4050 in that situation enough information to
4051 determine that it's no big deal. */
4052 printf_filtered ("\n\
4053 GDB is unable to find the start of the function at %s\n\
4054 and thus can't determine the size of that function's stack frame.\n\
4055 This means that GDB may be unable to access that stack frame, or\n\
4056 the frames below it.\n\
4057 This problem is most likely caused by an invalid program counter or\n\
4059 However, if you think GDB should simply search farther back\n\
4060 from %s for code which looks like the beginning of a\n\
4061 function, you can increase the range of the search using the `set\n\
4062 heuristic-fence-post' command.\n",
4063 paddress (gdbarch, pc), paddress (gdbarch, pc));
4070 else if (mips_pc_is_mips16 (gdbarch, start_pc))
4072 unsigned short inst;
4074 /* On MIPS16, any one of the following is likely to be the
4075 start of a function:
4081 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4082 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL);
4083 if ((inst & 0xff80) == 0x6480) /* save */
4085 if (start_pc - instlen >= fence)
4087 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16,
4088 start_pc - instlen, NULL);
4089 if ((inst & 0xf800) == 0xf000) /* extend */
4090 start_pc -= instlen;
4094 else if (((inst & 0xf81f) == 0xe809
4095 && (inst & 0x700) != 0x700) /* entry */
4096 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
4097 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
4098 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
4100 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
4101 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
4106 else if (mips_pc_is_micromips (gdbarch, start_pc))
4114 /* On microMIPS, any one of the following is likely to be the
4115 start of a function:
4119 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
4120 switch (micromips_op (insn))
4122 case 0xc: /* ADDIU: bits 001100 */
4123 case 0x17: /* DADDIU: bits 010111 */
4124 sreg = b0s5_reg (insn);
4125 dreg = b5s5_reg (insn);
4127 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS,
4128 pc + MIPS_INSN16_SIZE, NULL);
4129 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
4130 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
4131 /* (D)ADDIU $sp, imm */
4136 case 0x10: /* POOL32I: bits 010000 */
4137 if (b5s5_op (insn) == 0xd
4138 /* LUI: bits 010000 001101 */
4139 && b0s5_reg (insn >> 16) == 28)
4144 case 0x13: /* POOL16D: bits 010011 */
4145 if ((insn & 0x1) == 0x1)
4146 /* ADDIUSP: bits 010011 1 */
4148 offset = micromips_decode_imm9 (b1s9_imm (insn));
4154 /* ADDIUS5: bits 010011 0 */
4156 dreg = b5s5_reg (insn);
4157 offset = (b1s4_imm (insn) ^ 8) - 8;
4158 if (dreg == MIPS_SP_REGNUM && offset < 0)
4159 /* ADDIUS5 $sp, -imm */
4167 else if (mips_about_to_return (gdbarch, start_pc))
4169 /* Skip return and its delay slot. */
4170 start_pc += 2 * MIPS_INSN32_SIZE;
4177 struct mips_objfile_private
4183 /* According to the current ABI, should the type be passed in a
4184 floating-point register (assuming that there is space)? When there
4185 is no FPU, FP are not even considered as possible candidates for
4186 FP registers and, consequently this returns false - forces FP
4187 arguments into integer registers. */
4190 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
4191 struct type *arg_type)
4193 return ((typecode == TYPE_CODE_FLT
4194 || (MIPS_EABI (gdbarch)
4195 && (typecode == TYPE_CODE_STRUCT
4196 || typecode == TYPE_CODE_UNION)
4197 && TYPE_NFIELDS (arg_type) == 1
4198 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
4200 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
4203 /* On o32, argument passing in GPRs depends on the alignment of the type being
4204 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4207 mips_type_needs_double_align (struct type *type)
4209 enum type_code typecode = TYPE_CODE (type);
4211 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
4213 else if (typecode == TYPE_CODE_STRUCT)
4215 if (TYPE_NFIELDS (type) < 1)
4217 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
4219 else if (typecode == TYPE_CODE_UNION)
4223 n = TYPE_NFIELDS (type);
4224 for (i = 0; i < n; i++)
4225 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
4232 /* Adjust the address downward (direction of stack growth) so that it
4233 is correctly aligned for a new stack frame. */
4235 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
4237 return align_down (addr, 16);
4240 /* Implement the "push_dummy_code" gdbarch method. */
4243 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
4244 CORE_ADDR funaddr, struct value **args,
4245 int nargs, struct type *value_type,
4246 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
4247 struct regcache *regcache)
4249 static gdb_byte nop_insn[] = { 0, 0, 0, 0 };
4253 /* Reserve enough room on the stack for our breakpoint instruction. */
4254 bp_slot = sp - sizeof (nop_insn);
4256 /* Return to microMIPS mode if calling microMIPS code to avoid
4257 triggering an address error exception on processors that only
4258 support microMIPS execution. */
4259 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr)
4260 ? make_compact_addr (bp_slot) : bp_slot);
4262 /* The breakpoint layer automatically adjusts the address of
4263 breakpoints inserted in a branch delay slot. With enough
4264 bad luck, the 4 bytes located just before our breakpoint
4265 instruction could look like a branch instruction, and thus
4266 trigger the adjustement, and break the function call entirely.
4267 So, we reserve those 4 bytes and write a nop instruction
4268 to prevent that from happening. */
4269 nop_addr = bp_slot - sizeof (nop_insn);
4270 write_memory (nop_addr, nop_insn, sizeof (nop_insn));
4271 sp = mips_frame_align (gdbarch, nop_addr);
4273 /* Inferior resumes at the function entry point. */
4280 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4281 struct regcache *regcache, CORE_ADDR bp_addr,
4282 int nargs, struct value **args, CORE_ADDR sp,
4283 int struct_return, CORE_ADDR struct_addr)
4289 int stack_offset = 0;
4290 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4291 CORE_ADDR func_addr = find_function_addr (function, NULL);
4292 int regsize = mips_abi_regsize (gdbarch);
4294 /* For shared libraries, "t9" needs to point at the function
4296 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4298 /* Set the return address register to point to the entry point of
4299 the program, where a breakpoint lies in wait. */
4300 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4302 /* First ensure that the stack and structure return address (if any)
4303 are properly aligned. The stack has to be at least 64-bit
4304 aligned even on 32-bit machines, because doubles must be 64-bit
4305 aligned. For n32 and n64, stack frames need to be 128-bit
4306 aligned, so we round to this widest known alignment. */
4308 sp = align_down (sp, 16);
4309 struct_addr = align_down (struct_addr, 16);
4311 /* Now make space on the stack for the args. We allocate more
4312 than necessary for EABI, because the first few arguments are
4313 passed in registers, but that's OK. */
4314 for (argnum = 0; argnum < nargs; argnum++)
4315 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
4316 sp -= align_up (len, 16);
4319 fprintf_unfiltered (gdb_stdlog,
4320 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4321 paddress (gdbarch, sp), (long) align_up (len, 16));
4323 /* Initialize the integer and float register pointers. */
4324 argreg = MIPS_A0_REGNUM;
4325 float_argreg = mips_fpa0_regnum (gdbarch);
4327 /* The struct_return pointer occupies the first parameter-passing reg. */
4331 fprintf_unfiltered (gdb_stdlog,
4332 "mips_eabi_push_dummy_call: "
4333 "struct_return reg=%d %s\n",
4334 argreg, paddress (gdbarch, struct_addr));
4335 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4338 /* Now load as many as possible of the first arguments into
4339 registers, and push the rest onto the stack. Loop thru args
4340 from first to last. */
4341 for (argnum = 0; argnum < nargs; argnum++)
4343 const gdb_byte *val;
4344 gdb_byte valbuf[MAX_REGISTER_SIZE];
4345 struct value *arg = args[argnum];
4346 struct type *arg_type = check_typedef (value_type (arg));
4347 int len = TYPE_LENGTH (arg_type);
4348 enum type_code typecode = TYPE_CODE (arg_type);
4351 fprintf_unfiltered (gdb_stdlog,
4352 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4353 argnum + 1, len, (int) typecode);
4355 /* Function pointer arguments to mips16 code need to be made into
4357 if (typecode == TYPE_CODE_PTR
4358 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
4360 CORE_ADDR addr = extract_signed_integer (value_contents (arg),
4362 if (mips_pc_is_mips (addr))
4363 val = value_contents (arg);
4366 store_signed_integer (valbuf, len, byte_order,
4367 make_compact_addr (addr));
4371 /* The EABI passes structures that do not fit in a register by
4373 else if (len > regsize
4374 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
4376 store_unsigned_integer (valbuf, regsize, byte_order,
4377 value_address (arg));
4378 typecode = TYPE_CODE_PTR;
4382 fprintf_unfiltered (gdb_stdlog, " push");
4385 val = value_contents (arg);
4387 /* 32-bit ABIs always start floating point arguments in an
4388 even-numbered floating point register. Round the FP register
4389 up before the check to see if there are any FP registers
4390 left. Non MIPS_EABI targets also pass the FP in the integer
4391 registers so also round up normal registers. */
4392 if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
4394 if ((float_argreg & 1))
4398 /* Floating point arguments passed in registers have to be
4399 treated specially. On 32-bit architectures, doubles
4400 are passed in register pairs; the even register gets
4401 the low word, and the odd register gets the high word.
4402 On non-EABI processors, the first two floating point arguments are
4403 also copied to general registers, because MIPS16 functions
4404 don't use float registers for arguments. This duplication of
4405 arguments in general registers can't hurt non-MIPS16 functions
4406 because those registers are normally skipped. */
4407 /* MIPS_EABI squeezes a struct that contains a single floating
4408 point value into an FP register instead of pushing it onto the
4410 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4411 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4413 /* EABI32 will pass doubles in consecutive registers, even on
4414 64-bit cores. At one time, we used to check the size of
4415 `float_argreg' to determine whether or not to pass doubles
4416 in consecutive registers, but this is not sufficient for
4417 making the ABI determination. */
4418 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
4420 int low_offset = gdbarch_byte_order (gdbarch)
4421 == BFD_ENDIAN_BIG ? 4 : 0;
4424 /* Write the low word of the double to the even register(s). */
4425 regval = extract_signed_integer (val + low_offset,
4428 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4429 float_argreg, phex (regval, 4));
4430 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4432 /* Write the high word of the double to the odd register(s). */
4433 regval = extract_signed_integer (val + 4 - low_offset,
4436 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4437 float_argreg, phex (regval, 4));
4438 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4442 /* This is a floating point value that fits entirely
4443 in a single register. */
4444 /* On 32 bit ABI's the float_argreg is further adjusted
4445 above to ensure that it is even register aligned. */
4446 LONGEST regval = extract_signed_integer (val, len, byte_order);
4448 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4449 float_argreg, phex (regval, len));
4450 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4455 /* Copy the argument to general registers or the stack in
4456 register-sized pieces. Large arguments are split between
4457 registers and stack. */
4458 /* Note: structs whose size is not a multiple of regsize
4459 are treated specially: Irix cc passes
4460 them in registers where gcc sometimes puts them on the
4461 stack. For maximum compatibility, we will put them in
4463 int odd_sized_struct = (len > regsize && len % regsize != 0);
4465 /* Note: Floating-point values that didn't fit into an FP
4466 register are only written to memory. */
4469 /* Remember if the argument was written to the stack. */
4470 int stack_used_p = 0;
4471 int partial_len = (len < regsize ? len : regsize);
4474 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4477 /* Write this portion of the argument to the stack. */
4478 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4480 || fp_register_arg_p (gdbarch, typecode, arg_type))
4482 /* Should shorter than int integer values be
4483 promoted to int before being stored? */
4484 int longword_offset = 0;
4487 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4490 && (typecode == TYPE_CODE_INT
4491 || typecode == TYPE_CODE_PTR
4492 || typecode == TYPE_CODE_FLT) && len <= 4)
4493 longword_offset = regsize - len;
4494 else if ((typecode == TYPE_CODE_STRUCT
4495 || typecode == TYPE_CODE_UNION)
4496 && TYPE_LENGTH (arg_type) < regsize)
4497 longword_offset = regsize - len;
4502 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4503 paddress (gdbarch, stack_offset));
4504 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4505 paddress (gdbarch, longword_offset));
4508 addr = sp + stack_offset + longword_offset;
4513 fprintf_unfiltered (gdb_stdlog, " @%s ",
4514 paddress (gdbarch, addr));
4515 for (i = 0; i < partial_len; i++)
4517 fprintf_unfiltered (gdb_stdlog, "%02x",
4521 write_memory (addr, val, partial_len);
4524 /* Note!!! This is NOT an else clause. Odd sized
4525 structs may go thru BOTH paths. Floating point
4526 arguments will not. */
4527 /* Write this portion of the argument to a general
4528 purpose register. */
4529 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
4530 && !fp_register_arg_p (gdbarch, typecode, arg_type))
4533 extract_signed_integer (val, partial_len, byte_order);
4536 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4538 phex (regval, regsize));
4539 regcache_cooked_write_signed (regcache, argreg, regval);
4546 /* Compute the offset into the stack at which we will
4547 copy the next parameter.
4549 In the new EABI (and the NABI32), the stack_offset
4550 only needs to be adjusted when it has been used. */
4553 stack_offset += align_up (partial_len, regsize);
4557 fprintf_unfiltered (gdb_stdlog, "\n");
4560 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4562 /* Return adjusted stack pointer. */
4566 /* Determine the return value convention being used. */
4568 static enum return_value_convention
4569 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function,
4570 struct type *type, struct regcache *regcache,
4571 gdb_byte *readbuf, const gdb_byte *writebuf)
4573 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4574 int fp_return_type = 0;
4575 int offset, regnum, xfer;
4577 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
4578 return RETURN_VALUE_STRUCT_CONVENTION;
4580 /* Floating point type? */
4581 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
4583 if (TYPE_CODE (type) == TYPE_CODE_FLT)
4585 /* Structs with a single field of float type
4586 are returned in a floating point register. */
4587 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
4588 || TYPE_CODE (type) == TYPE_CODE_UNION)
4589 && TYPE_NFIELDS (type) == 1)
4591 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
4593 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
4600 /* A floating-point value belongs in the least significant part
4603 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4604 regnum = mips_regnum (gdbarch)->fp0;
4608 /* An integer value goes in V0/V1. */
4610 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
4611 regnum = MIPS_V0_REGNUM;
4614 offset < TYPE_LENGTH (type);
4615 offset += mips_abi_regsize (gdbarch), regnum++)
4617 xfer = mips_abi_regsize (gdbarch);
4618 if (offset + xfer > TYPE_LENGTH (type))
4619 xfer = TYPE_LENGTH (type) - offset;
4620 mips_xfer_register (gdbarch, regcache,
4621 gdbarch_num_regs (gdbarch) + regnum, xfer,
4622 gdbarch_byte_order (gdbarch), readbuf, writebuf,
4626 return RETURN_VALUE_REGISTER_CONVENTION;
4630 /* N32/N64 ABI stuff. */
4632 /* Search for a naturally aligned double at OFFSET inside a struct
4633 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4637 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
4642 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
4645 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
4648 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
4651 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
4654 struct type *field_type;
4656 /* We're only looking at normal fields. */
4657 if (field_is_static (&TYPE_FIELD (arg_type, i))
4658 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
4661 /* If we have gone past the offset, there is no double to pass. */
4662 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
4666 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
4668 /* If this field is entirely before the requested offset, go
4669 on to the next one. */
4670 if (pos + TYPE_LENGTH (field_type) <= offset)
4673 /* If this is our special aligned double, we can stop. */
4674 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
4675 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
4678 /* This field starts at or before the requested offset, and
4679 overlaps it. If it is a structure, recurse inwards. */
4680 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
4687 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4688 struct regcache *regcache, CORE_ADDR bp_addr,
4689 int nargs, struct value **args, CORE_ADDR sp,
4690 int struct_return, CORE_ADDR struct_addr)
4696 int stack_offset = 0;
4697 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4698 CORE_ADDR func_addr = find_function_addr (function, NULL);
4700 /* For shared libraries, "t9" needs to point at the function
4702 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4704 /* Set the return address register to point to the entry point of
4705 the program, where a breakpoint lies in wait. */
4706 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4708 /* First ensure that the stack and structure return address (if any)
4709 are properly aligned. The stack has to be at least 64-bit
4710 aligned even on 32-bit machines, because doubles must be 64-bit
4711 aligned. For n32 and n64, stack frames need to be 128-bit
4712 aligned, so we round to this widest known alignment. */
4714 sp = align_down (sp, 16);
4715 struct_addr = align_down (struct_addr, 16);
4717 /* Now make space on the stack for the args. */
4718 for (argnum = 0; argnum < nargs; argnum++)
4719 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
4720 sp -= align_up (len, 16);
4723 fprintf_unfiltered (gdb_stdlog,
4724 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4725 paddress (gdbarch, sp), (long) align_up (len, 16));
4727 /* Initialize the integer and float register pointers. */
4728 argreg = MIPS_A0_REGNUM;
4729 float_argreg = mips_fpa0_regnum (gdbarch);
4731 /* The struct_return pointer occupies the first parameter-passing reg. */
4735 fprintf_unfiltered (gdb_stdlog,
4736 "mips_n32n64_push_dummy_call: "
4737 "struct_return reg=%d %s\n",
4738 argreg, paddress (gdbarch, struct_addr));
4739 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4742 /* Now load as many as possible of the first arguments into
4743 registers, and push the rest onto the stack. Loop thru args
4744 from first to last. */
4745 for (argnum = 0; argnum < nargs; argnum++)
4747 const gdb_byte *val;
4748 struct value *arg = args[argnum];
4749 struct type *arg_type = check_typedef (value_type (arg));
4750 int len = TYPE_LENGTH (arg_type);
4751 enum type_code typecode = TYPE_CODE (arg_type);
4754 fprintf_unfiltered (gdb_stdlog,
4755 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4756 argnum + 1, len, (int) typecode);
4758 val = value_contents (arg);
4760 /* A 128-bit long double value requires an even-odd pair of
4761 floating-point registers. */
4763 && fp_register_arg_p (gdbarch, typecode, arg_type)
4764 && (float_argreg & 1))
4770 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4771 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4773 /* This is a floating point value that fits entirely
4774 in a single register or a pair of registers. */
4775 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4776 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
4778 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4779 float_argreg, phex (regval, reglen));
4780 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4783 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4784 argreg, phex (regval, reglen));
4785 regcache_cooked_write_unsigned (regcache, argreg, regval);
4790 regval = extract_unsigned_integer (val + reglen,
4791 reglen, byte_order);
4793 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4794 float_argreg, phex (regval, reglen));
4795 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4798 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4799 argreg, phex (regval, reglen));
4800 regcache_cooked_write_unsigned (regcache, argreg, regval);
4807 /* Copy the argument to general registers or the stack in
4808 register-sized pieces. Large arguments are split between
4809 registers and stack. */
4810 /* For N32/N64, structs, unions, or other composite types are
4811 treated as a sequence of doublewords, and are passed in integer
4812 or floating point registers as though they were simple scalar
4813 parameters to the extent that they fit, with any excess on the
4814 stack packed according to the normal memory layout of the
4816 The caller does not reserve space for the register arguments;
4817 the callee is responsible for reserving it if required. */
4818 /* Note: Floating-point values that didn't fit into an FP
4819 register are only written to memory. */
4822 /* Remember if the argument was written to the stack. */
4823 int stack_used_p = 0;
4824 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4827 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4830 if (fp_register_arg_p (gdbarch, typecode, arg_type))
4831 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
4833 /* Write this portion of the argument to the stack. */
4834 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
4836 /* Should shorter than int integer values be
4837 promoted to int before being stored? */
4838 int longword_offset = 0;
4841 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4843 if ((typecode == TYPE_CODE_INT
4844 || typecode == TYPE_CODE_PTR)
4846 longword_offset = MIPS64_REGSIZE - len;
4851 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4852 paddress (gdbarch, stack_offset));
4853 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4854 paddress (gdbarch, longword_offset));
4857 addr = sp + stack_offset + longword_offset;
4862 fprintf_unfiltered (gdb_stdlog, " @%s ",
4863 paddress (gdbarch, addr));
4864 for (i = 0; i < partial_len; i++)
4866 fprintf_unfiltered (gdb_stdlog, "%02x",
4870 write_memory (addr, val, partial_len);
4873 /* Note!!! This is NOT an else clause. Odd sized
4874 structs may go thru BOTH paths. */
4875 /* Write this portion of the argument to a general
4876 purpose register. */
4877 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4881 /* Sign extend pointers, 32-bit integers and signed
4882 16-bit and 8-bit integers; everything else is taken
4885 if ((partial_len == 4
4886 && (typecode == TYPE_CODE_PTR
4887 || typecode == TYPE_CODE_INT))
4889 && typecode == TYPE_CODE_INT
4890 && !TYPE_UNSIGNED (arg_type)))
4891 regval = extract_signed_integer (val, partial_len,
4894 regval = extract_unsigned_integer (val, partial_len,
4897 /* A non-floating-point argument being passed in a
4898 general register. If a struct or union, and if
4899 the remaining length is smaller than the register
4900 size, we have to adjust the register value on
4903 It does not seem to be necessary to do the
4904 same for integral types. */
4906 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
4907 && partial_len < MIPS64_REGSIZE
4908 && (typecode == TYPE_CODE_STRUCT
4909 || typecode == TYPE_CODE_UNION))
4910 regval <<= ((MIPS64_REGSIZE - partial_len)
4914 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4916 phex (regval, MIPS64_REGSIZE));
4917 regcache_cooked_write_unsigned (regcache, argreg, regval);
4919 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
4920 TYPE_LENGTH (arg_type) - len))
4923 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
4925 phex (regval, MIPS64_REGSIZE));
4926 regcache_cooked_write_unsigned (regcache, float_argreg,
4937 /* Compute the offset into the stack at which we will
4938 copy the next parameter.
4940 In N32 (N64?), the stack_offset only needs to be
4941 adjusted when it has been used. */
4944 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
4948 fprintf_unfiltered (gdb_stdlog, "\n");
4951 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4953 /* Return adjusted stack pointer. */
4957 static enum return_value_convention
4958 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function,
4959 struct type *type, struct regcache *regcache,
4960 gdb_byte *readbuf, const gdb_byte *writebuf)
4962 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4964 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4966 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4967 if needed), as appropriate for the type. Composite results (struct,
4968 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4971 * A struct with only one or two floating point fields is returned in $f0
4972 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4975 * Any other composite results of at most 128 bits are returned in
4976 $2 (first 64 bits) and $3 (remainder, if necessary).
4978 * Larger composite results are handled by converting the function to a
4979 procedure with an implicit first parameter, which is a pointer to an area
4980 reserved by the caller to receive the result. [The o32-bit ABI requires
4981 that all composite results be handled by conversion to implicit first
4982 parameters. The MIPS/SGI Fortran implementation has always made a
4983 specific exception to return COMPLEX results in the floating point
4986 if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
4987 return RETURN_VALUE_STRUCT_CONVENTION;
4988 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4989 && TYPE_LENGTH (type) == 16
4990 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4992 /* A 128-bit floating-point value fills both $f0 and $f2. The
4993 two registers are used in the same as memory order, so the
4994 eight bytes with the lower memory address are in $f0. */
4996 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
4997 mips_xfer_register (gdbarch, regcache,
4998 (gdbarch_num_regs (gdbarch)
4999 + mips_regnum (gdbarch)->fp0),
5000 8, gdbarch_byte_order (gdbarch),
5001 readbuf, writebuf, 0);
5002 mips_xfer_register (gdbarch, regcache,
5003 (gdbarch_num_regs (gdbarch)
5004 + mips_regnum (gdbarch)->fp0 + 2),
5005 8, gdbarch_byte_order (gdbarch),
5006 readbuf ? readbuf + 8 : readbuf,
5007 writebuf ? writebuf + 8 : writebuf, 0);
5008 return RETURN_VALUE_REGISTER_CONVENTION;
5010 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5011 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5013 /* A single or double floating-point value that fits in FP0. */
5015 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5016 mips_xfer_register (gdbarch, regcache,
5017 (gdbarch_num_regs (gdbarch)
5018 + mips_regnum (gdbarch)->fp0),
5020 gdbarch_byte_order (gdbarch),
5021 readbuf, writebuf, 0);
5022 return RETURN_VALUE_REGISTER_CONVENTION;
5024 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5025 && TYPE_NFIELDS (type) <= 2
5026 && TYPE_NFIELDS (type) >= 1
5027 && ((TYPE_NFIELDS (type) == 1
5028 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5030 || (TYPE_NFIELDS (type) == 2
5031 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5033 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
5034 == TYPE_CODE_FLT))))
5036 /* A struct that contains one or two floats. Each value is part
5037 in the least significant part of their floating point
5038 register (or GPR, for soft float). */
5041 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
5042 ? mips_regnum (gdbarch)->fp0
5044 field < TYPE_NFIELDS (type); field++, regnum += 2)
5046 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5049 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5051 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
5053 /* A 16-byte long double field goes in two consecutive
5055 mips_xfer_register (gdbarch, regcache,
5056 gdbarch_num_regs (gdbarch) + regnum,
5058 gdbarch_byte_order (gdbarch),
5059 readbuf, writebuf, offset);
5060 mips_xfer_register (gdbarch, regcache,
5061 gdbarch_num_regs (gdbarch) + regnum + 1,
5063 gdbarch_byte_order (gdbarch),
5064 readbuf, writebuf, offset + 8);
5067 mips_xfer_register (gdbarch, regcache,
5068 gdbarch_num_regs (gdbarch) + regnum,
5069 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5070 gdbarch_byte_order (gdbarch),
5071 readbuf, writebuf, offset);
5073 return RETURN_VALUE_REGISTER_CONVENTION;
5075 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5076 || TYPE_CODE (type) == TYPE_CODE_UNION
5077 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5079 /* A composite type. Extract the left justified value,
5080 regardless of the byte order. I.e. DO NOT USE
5084 for (offset = 0, regnum = MIPS_V0_REGNUM;
5085 offset < TYPE_LENGTH (type);
5086 offset += register_size (gdbarch, regnum), regnum++)
5088 int xfer = register_size (gdbarch, regnum);
5089 if (offset + xfer > TYPE_LENGTH (type))
5090 xfer = TYPE_LENGTH (type) - offset;
5092 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5093 offset, xfer, regnum);
5094 mips_xfer_register (gdbarch, regcache,
5095 gdbarch_num_regs (gdbarch) + regnum,
5096 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
5099 return RETURN_VALUE_REGISTER_CONVENTION;
5103 /* A scalar extract each part but least-significant-byte
5107 for (offset = 0, regnum = MIPS_V0_REGNUM;
5108 offset < TYPE_LENGTH (type);
5109 offset += register_size (gdbarch, regnum), regnum++)
5111 int xfer = register_size (gdbarch, regnum);
5112 if (offset + xfer > TYPE_LENGTH (type))
5113 xfer = TYPE_LENGTH (type) - offset;
5115 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5116 offset, xfer, regnum);
5117 mips_xfer_register (gdbarch, regcache,
5118 gdbarch_num_regs (gdbarch) + regnum,
5119 xfer, gdbarch_byte_order (gdbarch),
5120 readbuf, writebuf, offset);
5122 return RETURN_VALUE_REGISTER_CONVENTION;
5126 /* Which registers to use for passing floating-point values between
5127 function calls, one of floating-point, general and both kinds of
5128 registers. O32 and O64 use different register kinds for standard
5129 MIPS and MIPS16 code; to make the handling of cases where we may
5130 not know what kind of code is being used (e.g. no debug information)
5131 easier we sometimes use both kinds. */
5140 /* O32 ABI stuff. */
5143 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5144 struct regcache *regcache, CORE_ADDR bp_addr,
5145 int nargs, struct value **args, CORE_ADDR sp,
5146 int struct_return, CORE_ADDR struct_addr)
5152 int stack_offset = 0;
5153 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5154 CORE_ADDR func_addr = find_function_addr (function, NULL);
5156 /* For shared libraries, "t9" needs to point at the function
5158 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5160 /* Set the return address register to point to the entry point of
5161 the program, where a breakpoint lies in wait. */
5162 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5164 /* First ensure that the stack and structure return address (if any)
5165 are properly aligned. The stack has to be at least 64-bit
5166 aligned even on 32-bit machines, because doubles must be 64-bit
5167 aligned. For n32 and n64, stack frames need to be 128-bit
5168 aligned, so we round to this widest known alignment. */
5170 sp = align_down (sp, 16);
5171 struct_addr = align_down (struct_addr, 16);
5173 /* Now make space on the stack for the args. */
5174 for (argnum = 0; argnum < nargs; argnum++)
5176 struct type *arg_type = check_typedef (value_type (args[argnum]));
5178 /* Align to double-word if necessary. */
5179 if (mips_type_needs_double_align (arg_type))
5180 len = align_up (len, MIPS32_REGSIZE * 2);
5181 /* Allocate space on the stack. */
5182 len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE);
5184 sp -= align_up (len, 16);
5187 fprintf_unfiltered (gdb_stdlog,
5188 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5189 paddress (gdbarch, sp), (long) align_up (len, 16));
5191 /* Initialize the integer and float register pointers. */
5192 argreg = MIPS_A0_REGNUM;
5193 float_argreg = mips_fpa0_regnum (gdbarch);
5195 /* The struct_return pointer occupies the first parameter-passing reg. */
5199 fprintf_unfiltered (gdb_stdlog,
5200 "mips_o32_push_dummy_call: "
5201 "struct_return reg=%d %s\n",
5202 argreg, paddress (gdbarch, struct_addr));
5203 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5204 stack_offset += MIPS32_REGSIZE;
5207 /* Now load as many as possible of the first arguments into
5208 registers, and push the rest onto the stack. Loop thru args
5209 from first to last. */
5210 for (argnum = 0; argnum < nargs; argnum++)
5212 const gdb_byte *val;
5213 struct value *arg = args[argnum];
5214 struct type *arg_type = check_typedef (value_type (arg));
5215 int len = TYPE_LENGTH (arg_type);
5216 enum type_code typecode = TYPE_CODE (arg_type);
5219 fprintf_unfiltered (gdb_stdlog,
5220 "mips_o32_push_dummy_call: %d len=%d type=%d",
5221 argnum + 1, len, (int) typecode);
5223 val = value_contents (arg);
5225 /* 32-bit ABIs always start floating point arguments in an
5226 even-numbered floating point register. Round the FP register
5227 up before the check to see if there are any FP registers
5228 left. O32 targets also pass the FP in the integer registers
5229 so also round up normal registers. */
5230 if (fp_register_arg_p (gdbarch, typecode, arg_type))
5232 if ((float_argreg & 1))
5236 /* Floating point arguments passed in registers have to be
5237 treated specially. On 32-bit architectures, doubles are
5238 passed in register pairs; the even FP register gets the
5239 low word, and the odd FP register gets the high word.
5240 On O32, the first two floating point arguments are also
5241 copied to general registers, following their memory order,
5242 because MIPS16 functions don't use float registers for
5243 arguments. This duplication of arguments in general
5244 registers can't hurt non-MIPS16 functions, because those
5245 registers are normally skipped. */
5247 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5248 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5250 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
5252 int freg_offset = gdbarch_byte_order (gdbarch)
5253 == BFD_ENDIAN_BIG ? 1 : 0;
5254 unsigned long regval;
5257 regval = extract_unsigned_integer (val, 4, byte_order);
5259 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5260 float_argreg + freg_offset,
5262 regcache_cooked_write_unsigned (regcache,
5263 float_argreg++ + freg_offset,
5266 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5267 argreg, phex (regval, 4));
5268 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5271 regval = extract_unsigned_integer (val + 4, 4, byte_order);
5273 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5274 float_argreg - freg_offset,
5276 regcache_cooked_write_unsigned (regcache,
5277 float_argreg++ - freg_offset,
5280 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5281 argreg, phex (regval, 4));
5282 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5286 /* This is a floating point value that fits entirely
5287 in a single register. */
5288 /* On 32 bit ABI's the float_argreg is further adjusted
5289 above to ensure that it is even register aligned. */
5290 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5292 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5293 float_argreg, phex (regval, len));
5294 regcache_cooked_write_unsigned (regcache,
5295 float_argreg++, regval);
5296 /* Although two FP registers are reserved for each
5297 argument, only one corresponding integer register is
5300 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5301 argreg, phex (regval, len));
5302 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5304 /* Reserve space for the FP register. */
5305 stack_offset += align_up (len, MIPS32_REGSIZE);
5309 /* Copy the argument to general registers or the stack in
5310 register-sized pieces. Large arguments are split between
5311 registers and stack. */
5312 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5313 are treated specially: Irix cc passes
5314 them in registers where gcc sometimes puts them on the
5315 stack. For maximum compatibility, we will put them in
5317 int odd_sized_struct = (len > MIPS32_REGSIZE
5318 && len % MIPS32_REGSIZE != 0);
5319 /* Structures should be aligned to eight bytes (even arg registers)
5320 on MIPS_ABI_O32, if their first member has double precision. */
5321 if (mips_type_needs_double_align (arg_type))
5326 stack_offset += MIPS32_REGSIZE;
5331 /* Remember if the argument was written to the stack. */
5332 int stack_used_p = 0;
5333 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
5336 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5339 /* Write this portion of the argument to the stack. */
5340 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5341 || odd_sized_struct)
5343 /* Should shorter than int integer values be
5344 promoted to int before being stored? */
5345 int longword_offset = 0;
5351 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5352 paddress (gdbarch, stack_offset));
5353 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5354 paddress (gdbarch, longword_offset));
5357 addr = sp + stack_offset + longword_offset;
5362 fprintf_unfiltered (gdb_stdlog, " @%s ",
5363 paddress (gdbarch, addr));
5364 for (i = 0; i < partial_len; i++)
5366 fprintf_unfiltered (gdb_stdlog, "%02x",
5370 write_memory (addr, val, partial_len);
5373 /* Note!!! This is NOT an else clause. Odd sized
5374 structs may go thru BOTH paths. */
5375 /* Write this portion of the argument to a general
5376 purpose register. */
5377 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5379 LONGEST regval = extract_signed_integer (val, partial_len,
5381 /* Value may need to be sign extended, because
5382 mips_isa_regsize() != mips_abi_regsize(). */
5384 /* A non-floating-point argument being passed in a
5385 general register. If a struct or union, and if
5386 the remaining length is smaller than the register
5387 size, we have to adjust the register value on
5390 It does not seem to be necessary to do the
5391 same for integral types.
5393 Also don't do this adjustment on O64 binaries.
5395 cagney/2001-07-23: gdb/179: Also, GCC, when
5396 outputting LE O32 with sizeof (struct) <
5397 mips_abi_regsize(), generates a left shift
5398 as part of storing the argument in a register
5399 (the left shift isn't generated when
5400 sizeof (struct) >= mips_abi_regsize()). Since
5401 it is quite possible that this is GCC
5402 contradicting the LE/O32 ABI, GDB has not been
5403 adjusted to accommodate this. Either someone
5404 needs to demonstrate that the LE/O32 ABI
5405 specifies such a left shift OR this new ABI gets
5406 identified as such and GDB gets tweaked
5409 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5410 && partial_len < MIPS32_REGSIZE
5411 && (typecode == TYPE_CODE_STRUCT
5412 || typecode == TYPE_CODE_UNION))
5413 regval <<= ((MIPS32_REGSIZE - partial_len)
5417 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5419 phex (regval, MIPS32_REGSIZE));
5420 regcache_cooked_write_unsigned (regcache, argreg, regval);
5423 /* Prevent subsequent floating point arguments from
5424 being passed in floating point registers. */
5425 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
5431 /* Compute the offset into the stack at which we will
5432 copy the next parameter.
5434 In older ABIs, the caller reserved space for
5435 registers that contained arguments. This was loosely
5436 refered to as their "home". Consequently, space is
5437 always allocated. */
5439 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
5443 fprintf_unfiltered (gdb_stdlog, "\n");
5446 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5448 /* Return adjusted stack pointer. */
5452 static enum return_value_convention
5453 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function,
5454 struct type *type, struct regcache *regcache,
5455 gdb_byte *readbuf, const gdb_byte *writebuf)
5457 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
5458 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
5459 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5460 enum mips_fval_reg fval_reg;
5462 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
5463 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5464 || TYPE_CODE (type) == TYPE_CODE_UNION
5465 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5466 return RETURN_VALUE_STRUCT_CONVENTION;
5467 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5468 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5470 /* A single-precision floating-point value. If reading in or copying,
5471 then we get it from/put it to FP0 for standard MIPS code or GPR2
5472 for MIPS16 code. If writing out only, then we put it to both FP0
5473 and GPR2. We do not support reading in with no function known, if
5474 this safety check ever triggers, then we'll have to try harder. */
5475 gdb_assert (function || !readbuf);
5480 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5483 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
5485 case mips_fval_both:
5486 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
5489 if (fval_reg != mips_fval_gpr)
5490 mips_xfer_register (gdbarch, regcache,
5491 (gdbarch_num_regs (gdbarch)
5492 + mips_regnum (gdbarch)->fp0),
5494 gdbarch_byte_order (gdbarch),
5495 readbuf, writebuf, 0);
5496 if (fval_reg != mips_fval_fpr)
5497 mips_xfer_register (gdbarch, regcache,
5498 gdbarch_num_regs (gdbarch) + 2,
5500 gdbarch_byte_order (gdbarch),
5501 readbuf, writebuf, 0);
5502 return RETURN_VALUE_REGISTER_CONVENTION;
5504 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5505 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5507 /* A double-precision floating-point value. If reading in or copying,
5508 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5509 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5510 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5511 no function known, if this safety check ever triggers, then we'll
5512 have to try harder. */
5513 gdb_assert (function || !readbuf);
5518 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
5521 fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n");
5523 case mips_fval_both:
5524 fprintf_unfiltered (gdb_stderr,
5525 "Return float in $fp1/$fp0 and $2/$3\n");
5528 if (fval_reg != mips_fval_gpr)
5530 /* The most significant part goes in FP1, and the least significant
5532 switch (gdbarch_byte_order (gdbarch))
5534 case BFD_ENDIAN_LITTLE:
5535 mips_xfer_register (gdbarch, regcache,
5536 (gdbarch_num_regs (gdbarch)
5537 + mips_regnum (gdbarch)->fp0 + 0),
5538 4, gdbarch_byte_order (gdbarch),
5539 readbuf, writebuf, 0);
5540 mips_xfer_register (gdbarch, regcache,
5541 (gdbarch_num_regs (gdbarch)
5542 + mips_regnum (gdbarch)->fp0 + 1),
5543 4, gdbarch_byte_order (gdbarch),
5544 readbuf, writebuf, 4);
5546 case BFD_ENDIAN_BIG:
5547 mips_xfer_register (gdbarch, regcache,
5548 (gdbarch_num_regs (gdbarch)
5549 + mips_regnum (gdbarch)->fp0 + 1),
5550 4, gdbarch_byte_order (gdbarch),
5551 readbuf, writebuf, 0);
5552 mips_xfer_register (gdbarch, regcache,
5553 (gdbarch_num_regs (gdbarch)
5554 + mips_regnum (gdbarch)->fp0 + 0),
5555 4, gdbarch_byte_order (gdbarch),
5556 readbuf, writebuf, 4);
5559 internal_error (__FILE__, __LINE__, _("bad switch"));
5562 if (fval_reg != mips_fval_fpr)
5564 /* The two 32-bit parts are always placed in GPR2 and GPR3
5565 following these registers' memory order. */
5566 mips_xfer_register (gdbarch, regcache,
5567 gdbarch_num_regs (gdbarch) + 2,
5568 4, gdbarch_byte_order (gdbarch),
5569 readbuf, writebuf, 0);
5570 mips_xfer_register (gdbarch, regcache,
5571 gdbarch_num_regs (gdbarch) + 3,
5572 4, gdbarch_byte_order (gdbarch),
5573 readbuf, writebuf, 4);
5575 return RETURN_VALUE_REGISTER_CONVENTION;
5578 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5579 && TYPE_NFIELDS (type) <= 2
5580 && TYPE_NFIELDS (type) >= 1
5581 && ((TYPE_NFIELDS (type) == 1
5582 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5584 || (TYPE_NFIELDS (type) == 2
5585 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5587 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
5589 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5591 /* A struct that contains one or two floats. Each value is part
5592 in the least significant part of their floating point
5594 gdb_byte reg[MAX_REGISTER_SIZE];
5597 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
5598 field < TYPE_NFIELDS (type); field++, regnum += 2)
5600 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5603 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5605 mips_xfer_register (gdbarch, regcache,
5606 gdbarch_num_regs (gdbarch) + regnum,
5607 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5608 gdbarch_byte_order (gdbarch),
5609 readbuf, writebuf, offset);
5611 return RETURN_VALUE_REGISTER_CONVENTION;
5615 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5616 || TYPE_CODE (type) == TYPE_CODE_UNION)
5618 /* A structure or union. Extract the left justified value,
5619 regardless of the byte order. I.e. DO NOT USE
5623 for (offset = 0, regnum = MIPS_V0_REGNUM;
5624 offset < TYPE_LENGTH (type);
5625 offset += register_size (gdbarch, regnum), regnum++)
5627 int xfer = register_size (gdbarch, regnum);
5628 if (offset + xfer > TYPE_LENGTH (type))
5629 xfer = TYPE_LENGTH (type) - offset;
5631 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5632 offset, xfer, regnum);
5633 mips_xfer_register (gdbarch, regcache,
5634 gdbarch_num_regs (gdbarch) + regnum, xfer,
5635 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
5637 return RETURN_VALUE_REGISTER_CONVENTION;
5642 /* A scalar extract each part but least-significant-byte
5643 justified. o32 thinks registers are 4 byte, regardless of
5647 for (offset = 0, regnum = MIPS_V0_REGNUM;
5648 offset < TYPE_LENGTH (type);
5649 offset += MIPS32_REGSIZE, regnum++)
5651 int xfer = MIPS32_REGSIZE;
5652 if (offset + xfer > TYPE_LENGTH (type))
5653 xfer = TYPE_LENGTH (type) - offset;
5655 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5656 offset, xfer, regnum);
5657 mips_xfer_register (gdbarch, regcache,
5658 gdbarch_num_regs (gdbarch) + regnum, xfer,
5659 gdbarch_byte_order (gdbarch),
5660 readbuf, writebuf, offset);
5662 return RETURN_VALUE_REGISTER_CONVENTION;
5666 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5670 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5671 struct regcache *regcache, CORE_ADDR bp_addr,
5673 struct value **args, CORE_ADDR sp,
5674 int struct_return, CORE_ADDR struct_addr)
5680 int stack_offset = 0;
5681 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5682 CORE_ADDR func_addr = find_function_addr (function, NULL);
5684 /* For shared libraries, "t9" needs to point at the function
5686 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5688 /* Set the return address register to point to the entry point of
5689 the program, where a breakpoint lies in wait. */
5690 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5692 /* First ensure that the stack and structure return address (if any)
5693 are properly aligned. The stack has to be at least 64-bit
5694 aligned even on 32-bit machines, because doubles must be 64-bit
5695 aligned. For n32 and n64, stack frames need to be 128-bit
5696 aligned, so we round to this widest known alignment. */
5698 sp = align_down (sp, 16);
5699 struct_addr = align_down (struct_addr, 16);
5701 /* Now make space on the stack for the args. */
5702 for (argnum = 0; argnum < nargs; argnum++)
5704 struct type *arg_type = check_typedef (value_type (args[argnum]));
5706 /* Allocate space on the stack. */
5707 len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE);
5709 sp -= align_up (len, 16);
5712 fprintf_unfiltered (gdb_stdlog,
5713 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5714 paddress (gdbarch, sp), (long) align_up (len, 16));
5716 /* Initialize the integer and float register pointers. */
5717 argreg = MIPS_A0_REGNUM;
5718 float_argreg = mips_fpa0_regnum (gdbarch);
5720 /* The struct_return pointer occupies the first parameter-passing reg. */
5724 fprintf_unfiltered (gdb_stdlog,
5725 "mips_o64_push_dummy_call: "
5726 "struct_return reg=%d %s\n",
5727 argreg, paddress (gdbarch, struct_addr));
5728 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5729 stack_offset += MIPS64_REGSIZE;
5732 /* Now load as many as possible of the first arguments into
5733 registers, and push the rest onto the stack. Loop thru args
5734 from first to last. */
5735 for (argnum = 0; argnum < nargs; argnum++)
5737 const gdb_byte *val;
5738 gdb_byte valbuf[MAX_REGISTER_SIZE];
5739 struct value *arg = args[argnum];
5740 struct type *arg_type = check_typedef (value_type (arg));
5741 int len = TYPE_LENGTH (arg_type);
5742 enum type_code typecode = TYPE_CODE (arg_type);
5745 fprintf_unfiltered (gdb_stdlog,
5746 "mips_o64_push_dummy_call: %d len=%d type=%d",
5747 argnum + 1, len, (int) typecode);
5749 val = value_contents (arg);
5751 /* Function pointer arguments to mips16 code need to be made into
5753 if (typecode == TYPE_CODE_PTR
5754 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
5756 CORE_ADDR addr = extract_signed_integer (value_contents (arg),
5758 if (!mips_pc_is_mips (addr))
5760 store_signed_integer (valbuf, len, byte_order,
5761 make_compact_addr (addr));
5766 /* Floating point arguments passed in registers have to be
5767 treated specially. On 32-bit architectures, doubles are
5768 passed in register pairs; the even FP register gets the
5769 low word, and the odd FP register gets the high word.
5770 On O64, the first two floating point arguments are also
5771 copied to general registers, because MIPS16 functions
5772 don't use float registers for arguments. This duplication
5773 of arguments in general registers can't hurt non-MIPS16
5774 functions because those registers are normally skipped. */
5776 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5777 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5779 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5781 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5782 float_argreg, phex (regval, len));
5783 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
5785 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5786 argreg, phex (regval, len));
5787 regcache_cooked_write_unsigned (regcache, argreg, regval);
5789 /* Reserve space for the FP register. */
5790 stack_offset += align_up (len, MIPS64_REGSIZE);
5794 /* Copy the argument to general registers or the stack in
5795 register-sized pieces. Large arguments are split between
5796 registers and stack. */
5797 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5798 are treated specially: Irix cc passes them in registers
5799 where gcc sometimes puts them on the stack. For maximum
5800 compatibility, we will put them in both places. */
5801 int odd_sized_struct = (len > MIPS64_REGSIZE
5802 && len % MIPS64_REGSIZE != 0);
5805 /* Remember if the argument was written to the stack. */
5806 int stack_used_p = 0;
5807 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
5810 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5813 /* Write this portion of the argument to the stack. */
5814 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5815 || odd_sized_struct)
5817 /* Should shorter than int integer values be
5818 promoted to int before being stored? */
5819 int longword_offset = 0;
5822 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5824 if ((typecode == TYPE_CODE_INT
5825 || typecode == TYPE_CODE_PTR
5826 || typecode == TYPE_CODE_FLT)
5828 longword_offset = MIPS64_REGSIZE - len;
5833 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5834 paddress (gdbarch, stack_offset));
5835 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5836 paddress (gdbarch, longword_offset));
5839 addr = sp + stack_offset + longword_offset;
5844 fprintf_unfiltered (gdb_stdlog, " @%s ",
5845 paddress (gdbarch, addr));
5846 for (i = 0; i < partial_len; i++)
5848 fprintf_unfiltered (gdb_stdlog, "%02x",
5852 write_memory (addr, val, partial_len);
5855 /* Note!!! This is NOT an else clause. Odd sized
5856 structs may go thru BOTH paths. */
5857 /* Write this portion of the argument to a general
5858 purpose register. */
5859 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5861 LONGEST regval = extract_signed_integer (val, partial_len,
5863 /* Value may need to be sign extended, because
5864 mips_isa_regsize() != mips_abi_regsize(). */
5866 /* A non-floating-point argument being passed in a
5867 general register. If a struct or union, and if
5868 the remaining length is smaller than the register
5869 size, we have to adjust the register value on
5872 It does not seem to be necessary to do the
5873 same for integral types. */
5875 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5876 && partial_len < MIPS64_REGSIZE
5877 && (typecode == TYPE_CODE_STRUCT
5878 || typecode == TYPE_CODE_UNION))
5879 regval <<= ((MIPS64_REGSIZE - partial_len)
5883 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5885 phex (regval, MIPS64_REGSIZE));
5886 regcache_cooked_write_unsigned (regcache, argreg, regval);
5889 /* Prevent subsequent floating point arguments from
5890 being passed in floating point registers. */
5891 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
5897 /* Compute the offset into the stack at which we will
5898 copy the next parameter.
5900 In older ABIs, the caller reserved space for
5901 registers that contained arguments. This was loosely
5902 refered to as their "home". Consequently, space is
5903 always allocated. */
5905 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
5909 fprintf_unfiltered (gdb_stdlog, "\n");
5912 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5914 /* Return adjusted stack pointer. */
5918 static enum return_value_convention
5919 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function,
5920 struct type *type, struct regcache *regcache,
5921 gdb_byte *readbuf, const gdb_byte *writebuf)
5923 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
5924 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
5925 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5926 enum mips_fval_reg fval_reg;
5928 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
5929 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5930 || TYPE_CODE (type) == TYPE_CODE_UNION
5931 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5932 return RETURN_VALUE_STRUCT_CONVENTION;
5933 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
5935 /* A floating-point value. If reading in or copying, then we get it
5936 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5937 If writing out only, then we put it to both FP0 and GPR2. We do
5938 not support reading in with no function known, if this safety
5939 check ever triggers, then we'll have to try harder. */
5940 gdb_assert (function || !readbuf);
5945 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5948 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
5950 case mips_fval_both:
5951 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
5954 if (fval_reg != mips_fval_gpr)
5955 mips_xfer_register (gdbarch, regcache,
5956 (gdbarch_num_regs (gdbarch)
5957 + mips_regnum (gdbarch)->fp0),
5959 gdbarch_byte_order (gdbarch),
5960 readbuf, writebuf, 0);
5961 if (fval_reg != mips_fval_fpr)
5962 mips_xfer_register (gdbarch, regcache,
5963 gdbarch_num_regs (gdbarch) + 2,
5965 gdbarch_byte_order (gdbarch),
5966 readbuf, writebuf, 0);
5967 return RETURN_VALUE_REGISTER_CONVENTION;
5971 /* A scalar extract each part but least-significant-byte
5975 for (offset = 0, regnum = MIPS_V0_REGNUM;
5976 offset < TYPE_LENGTH (type);
5977 offset += MIPS64_REGSIZE, regnum++)
5979 int xfer = MIPS64_REGSIZE;
5980 if (offset + xfer > TYPE_LENGTH (type))
5981 xfer = TYPE_LENGTH (type) - offset;
5983 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5984 offset, xfer, regnum);
5985 mips_xfer_register (gdbarch, regcache,
5986 gdbarch_num_regs (gdbarch) + regnum,
5987 xfer, gdbarch_byte_order (gdbarch),
5988 readbuf, writebuf, offset);
5990 return RETURN_VALUE_REGISTER_CONVENTION;
5994 /* Floating point register management.
5996 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5997 64bit operations, these early MIPS cpus treat fp register pairs
5998 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
5999 registers and offer a compatibility mode that emulates the MIPS2 fp
6000 model. When operating in MIPS2 fp compat mode, later cpu's split
6001 double precision floats into two 32-bit chunks and store them in
6002 consecutive fp regs. To display 64-bit floats stored in this
6003 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6004 Throw in user-configurable endianness and you have a real mess.
6006 The way this works is:
6007 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6008 double-precision value will be split across two logical registers.
6009 The lower-numbered logical register will hold the low-order bits,
6010 regardless of the processor's endianness.
6011 - If we are on a 64-bit processor, and we are looking for a
6012 single-precision value, it will be in the low ordered bits
6013 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6014 save slot in memory.
6015 - If we are in 64-bit mode, everything is straightforward.
6017 Note that this code only deals with "live" registers at the top of the
6018 stack. We will attempt to deal with saved registers later, when
6019 the raw/cooked register interface is in place. (We need a general
6020 interface that can deal with dynamic saved register sizes -- fp
6021 regs could be 32 bits wide in one frame and 64 on the frame above
6024 /* Copy a 32-bit single-precision value from the current frame
6025 into rare_buffer. */
6028 mips_read_fp_register_single (struct frame_info *frame, int regno,
6029 gdb_byte *rare_buffer)
6031 struct gdbarch *gdbarch = get_frame_arch (frame);
6032 int raw_size = register_size (gdbarch, regno);
6033 gdb_byte *raw_buffer = alloca (raw_size);
6035 if (!deprecated_frame_register_read (frame, regno, raw_buffer))
6036 error (_("can't read register %d (%s)"),
6037 regno, gdbarch_register_name (gdbarch, regno));
6040 /* We have a 64-bit value for this register. Find the low-order
6044 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6049 memcpy (rare_buffer, raw_buffer + offset, 4);
6053 memcpy (rare_buffer, raw_buffer, 4);
6057 /* Copy a 64-bit double-precision value from the current frame into
6058 rare_buffer. This may include getting half of it from the next
6062 mips_read_fp_register_double (struct frame_info *frame, int regno,
6063 gdb_byte *rare_buffer)
6065 struct gdbarch *gdbarch = get_frame_arch (frame);
6066 int raw_size = register_size (gdbarch, regno);
6068 if (raw_size == 8 && !mips2_fp_compat (frame))
6070 /* We have a 64-bit value for this register, and we should use
6072 if (!deprecated_frame_register_read (frame, regno, rare_buffer))
6073 error (_("can't read register %d (%s)"),
6074 regno, gdbarch_register_name (gdbarch, regno));
6078 int rawnum = regno % gdbarch_num_regs (gdbarch);
6080 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
6081 internal_error (__FILE__, __LINE__,
6082 _("mips_read_fp_register_double: bad access to "
6083 "odd-numbered FP register"));
6085 /* mips_read_fp_register_single will find the correct 32 bits from
6087 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6089 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
6090 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
6094 mips_read_fp_register_single (frame, regno, rare_buffer);
6095 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
6101 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
6103 { /* Do values for FP (float) regs. */
6104 struct gdbarch *gdbarch = get_frame_arch (frame);
6105 gdb_byte *raw_buffer;
6106 double doub, flt1; /* Doubles extracted from raw hex data. */
6109 raw_buffer = alloca (2 * register_size (gdbarch,
6110 mips_regnum (gdbarch)->fp0));
6112 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
6113 fprintf_filtered (file, "%*s",
6114 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
6117 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
6119 struct value_print_options opts;
6121 /* 4-byte registers: Print hex and floating. Also print even
6122 numbered registers as doubles. */
6123 mips_read_fp_register_single (frame, regnum, raw_buffer);
6124 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
6127 get_formatted_print_options (&opts, 'x');
6128 print_scalar_formatted (raw_buffer,
6129 builtin_type (gdbarch)->builtin_uint32,
6132 fprintf_filtered (file, " flt: ");
6134 fprintf_filtered (file, " <invalid float> ");
6136 fprintf_filtered (file, "%-17.9g", flt1);
6138 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
6140 mips_read_fp_register_double (frame, regnum, raw_buffer);
6141 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
6144 fprintf_filtered (file, " dbl: ");
6146 fprintf_filtered (file, "<invalid double>");
6148 fprintf_filtered (file, "%-24.17g", doub);
6153 struct value_print_options opts;
6155 /* Eight byte registers: print each one as hex, float and double. */
6156 mips_read_fp_register_single (frame, regnum, raw_buffer);
6157 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
6160 mips_read_fp_register_double (frame, regnum, raw_buffer);
6161 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
6164 get_formatted_print_options (&opts, 'x');
6165 print_scalar_formatted (raw_buffer,
6166 builtin_type (gdbarch)->builtin_uint64,
6169 fprintf_filtered (file, " flt: ");
6171 fprintf_filtered (file, "<invalid float>");
6173 fprintf_filtered (file, "%-17.9g", flt1);
6175 fprintf_filtered (file, " dbl: ");
6177 fprintf_filtered (file, "<invalid double>");
6179 fprintf_filtered (file, "%-24.17g", doub);
6184 mips_print_register (struct ui_file *file, struct frame_info *frame,
6187 struct gdbarch *gdbarch = get_frame_arch (frame);
6188 struct value_print_options opts;
6191 if (mips_float_register_p (gdbarch, regnum))
6193 mips_print_fp_register (file, frame, regnum);
6197 val = get_frame_register_value (frame, regnum);
6198 if (value_optimized_out (val))
6200 fprintf_filtered (file, "%s: [Invalid]",
6201 gdbarch_register_name (gdbarch, regnum));
6205 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
6207 /* The problem with printing numeric register names (r26, etc.) is that
6208 the user can't use them on input. Probably the best solution is to
6209 fix it so that either the numeric or the funky (a2, etc.) names
6210 are accepted on input. */
6211 if (regnum < MIPS_NUMREGS)
6212 fprintf_filtered (file, "(r%d): ", regnum);
6214 fprintf_filtered (file, ": ");
6216 get_formatted_print_options (&opts, 'x');
6217 val_print_scalar_formatted (value_type (val),
6218 value_contents_for_printing (val),
6219 value_embedded_offset (val),
6224 /* Replacement for generic do_registers_info.
6225 Print regs in pretty columns. */
6228 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
6231 fprintf_filtered (file, " ");
6232 mips_print_fp_register (file, frame, regnum);
6233 fprintf_filtered (file, "\n");
6238 /* Print a row's worth of GP (int) registers, with name labels above. */
6241 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
6244 struct gdbarch *gdbarch = get_frame_arch (frame);
6245 /* Do values for GP (int) regs. */
6246 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
6247 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols
6252 /* For GP registers, we print a separate row of names above the vals. */
6253 for (col = 0, regnum = start_regnum;
6254 col < ncols && regnum < gdbarch_num_regs (gdbarch)
6255 + gdbarch_num_pseudo_regs (gdbarch);
6258 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6259 continue; /* unused register */
6260 if (mips_float_register_p (gdbarch, regnum))
6261 break; /* End the row: reached FP register. */
6262 /* Large registers are handled separately. */
6263 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6266 break; /* End the row before this register. */
6268 /* Print this register on a row by itself. */
6269 mips_print_register (file, frame, regnum);
6270 fprintf_filtered (file, "\n");
6274 fprintf_filtered (file, " ");
6275 fprintf_filtered (file,
6276 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
6277 gdbarch_register_name (gdbarch, regnum));
6284 /* Print the R0 to R31 names. */
6285 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
6286 fprintf_filtered (file, "\n R%-4d",
6287 start_regnum % gdbarch_num_regs (gdbarch));
6289 fprintf_filtered (file, "\n ");
6291 /* Now print the values in hex, 4 or 8 to the row. */
6292 for (col = 0, regnum = start_regnum;
6293 col < ncols && regnum < gdbarch_num_regs (gdbarch)
6294 + gdbarch_num_pseudo_regs (gdbarch);
6297 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6298 continue; /* unused register */
6299 if (mips_float_register_p (gdbarch, regnum))
6300 break; /* End row: reached FP register. */
6301 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6302 break; /* End row: large register. */
6304 /* OK: get the data in raw format. */
6305 if (!deprecated_frame_register_read (frame, regnum, raw_buffer))
6306 error (_("can't read register %d (%s)"),
6307 regnum, gdbarch_register_name (gdbarch, regnum));
6308 /* pad small registers */
6310 byte < (mips_abi_regsize (gdbarch)
6311 - register_size (gdbarch, regnum)); byte++)
6312 printf_filtered (" ");
6313 /* Now print the register value in hex, endian order. */
6314 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6316 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
6317 byte < register_size (gdbarch, regnum); byte++)
6318 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6320 for (byte = register_size (gdbarch, regnum) - 1;
6322 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6323 fprintf_filtered (file, " ");
6326 if (col > 0) /* ie. if we actually printed anything... */
6327 fprintf_filtered (file, "\n");
6332 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6335 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
6336 struct frame_info *frame, int regnum, int all)
6338 if (regnum != -1) /* Do one specified register. */
6340 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
6341 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
6342 error (_("Not a valid register for the current processor type"));
6344 mips_print_register (file, frame, regnum);
6345 fprintf_filtered (file, "\n");
6348 /* Do all (or most) registers. */
6350 regnum = gdbarch_num_regs (gdbarch);
6351 while (regnum < gdbarch_num_regs (gdbarch)
6352 + gdbarch_num_pseudo_regs (gdbarch))
6354 if (mips_float_register_p (gdbarch, regnum))
6356 if (all) /* True for "INFO ALL-REGISTERS" command. */
6357 regnum = print_fp_register_row (file, frame, regnum);
6359 regnum += MIPS_NUMREGS; /* Skip floating point regs. */
6362 regnum = print_gp_register_row (file, frame, regnum);
6368 mips_single_step_through_delay (struct gdbarch *gdbarch,
6369 struct frame_info *frame)
6371 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6372 CORE_ADDR pc = get_frame_pc (frame);
6373 struct address_space *aspace;
6379 if ((mips_pc_is_mips (pc)
6380 && !mips32_instruction_has_delay_slot (gdbarch, pc))
6381 || (mips_pc_is_micromips (gdbarch, pc)
6382 && !micromips_instruction_has_delay_slot (gdbarch, pc, 0))
6383 || (mips_pc_is_mips16 (gdbarch, pc)
6384 && !mips16_instruction_has_delay_slot (gdbarch, pc, 0)))
6387 isa = mips_pc_isa (gdbarch, pc);
6388 /* _has_delay_slot above will have validated the read. */
6389 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL);
6390 size = mips_insn_size (isa, insn);
6391 aspace = get_frame_address_space (frame);
6392 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here;
6395 /* To skip prologues, I use this predicate. Returns either PC itself
6396 if the code at PC does not look like a function prologue; otherwise
6397 returns an address that (if we're lucky) follows the prologue. If
6398 LENIENT, then we must skip everything which is involved in setting
6399 up the frame (it's OK to skip more, just so long as we don't skip
6400 anything which might clobber the registers which are being saved.
6401 We must skip more in the case where part of the prologue is in the
6402 delay slot of a non-prologue instruction). */
6405 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
6408 CORE_ADDR func_addr;
6410 /* See if we can determine the end of the prologue via the symbol table.
6411 If so, then return either PC, or the PC after the prologue, whichever
6413 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
6415 CORE_ADDR post_prologue_pc
6416 = skip_prologue_using_sal (gdbarch, func_addr);
6417 if (post_prologue_pc != 0)
6418 return max (pc, post_prologue_pc);
6421 /* Can't determine prologue from the symbol table, need to examine
6424 /* Find an upper limit on the function prologue using the debug
6425 information. If the debug information could not be used to provide
6426 that bound, then use an arbitrary large number as the upper bound. */
6427 limit_pc = skip_prologue_using_sal (gdbarch, pc);
6429 limit_pc = pc + 100; /* Magic. */
6431 if (mips_pc_is_mips16 (gdbarch, pc))
6432 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6433 else if (mips_pc_is_micromips (gdbarch, pc))
6434 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6436 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6439 /* Check whether the PC is in a function epilogue (32-bit version).
6440 This is a helper function for mips_in_function_epilogue_p. */
6442 mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6444 CORE_ADDR func_addr = 0, func_end = 0;
6446 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6448 /* The MIPS epilogue is max. 12 bytes long. */
6449 CORE_ADDR addr = func_end - 12;
6451 if (addr < func_addr + 4)
6452 addr = func_addr + 4;
6456 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
6458 unsigned long high_word;
6461 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
6462 high_word = (inst >> 16) & 0xffff;
6464 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
6465 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
6466 && inst != 0x03e00008 /* jr $ra */
6467 && inst != 0x00000000) /* nop */
6477 /* Check whether the PC is in a function epilogue (microMIPS version).
6478 This is a helper function for mips_in_function_epilogue_p. */
6481 micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6483 CORE_ADDR func_addr = 0;
6484 CORE_ADDR func_end = 0;
6492 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6495 /* The microMIPS epilogue is max. 12 bytes long. */
6496 addr = func_end - 12;
6498 if (addr < func_addr + 2)
6499 addr = func_addr + 2;
6503 for (; pc < func_end; pc += loc)
6506 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
6507 loc += MIPS_INSN16_SIZE;
6508 switch (mips_insn_size (ISA_MICROMIPS, insn))
6510 /* 48-bit instructions. */
6511 case 3 * MIPS_INSN16_SIZE:
6512 /* No epilogue instructions in this category. */
6515 /* 32-bit instructions. */
6516 case 2 * MIPS_INSN16_SIZE:
6518 insn |= mips_fetch_instruction (gdbarch,
6519 ISA_MICROMIPS, pc + loc, NULL);
6520 loc += MIPS_INSN16_SIZE;
6521 switch (micromips_op (insn >> 16))
6523 case 0xc: /* ADDIU: bits 001100 */
6524 case 0x17: /* DADDIU: bits 010111 */
6525 sreg = b0s5_reg (insn >> 16);
6526 dreg = b5s5_reg (insn >> 16);
6527 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
6528 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
6529 /* (D)ADDIU $sp, imm */
6539 /* 16-bit instructions. */
6540 case MIPS_INSN16_SIZE:
6541 switch (micromips_op (insn))
6543 case 0x3: /* MOVE: bits 000011 */
6544 sreg = b0s5_reg (insn);
6545 dreg = b5s5_reg (insn);
6546 if (sreg == 0 && dreg == 0)
6547 /* MOVE $zero, $zero aka NOP */
6551 case 0x11: /* POOL16C: bits 010001 */
6552 if (b5s5_op (insn) == 0x18
6553 /* JRADDIUSP: bits 010011 11000 */
6554 || (b5s5_op (insn) == 0xd
6555 /* JRC: bits 010011 01101 */
6556 && b0s5_reg (insn) == MIPS_RA_REGNUM))
6561 case 0x13: /* POOL16D: bits 010011 */
6562 offset = micromips_decode_imm9 (b1s9_imm (insn));
6563 if ((insn & 0x1) == 0x1
6564 /* ADDIUSP: bits 010011 1 */
6578 /* Check whether the PC is in a function epilogue (16-bit version).
6579 This is a helper function for mips_in_function_epilogue_p. */
6581 mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6583 CORE_ADDR func_addr = 0, func_end = 0;
6585 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6587 /* The MIPS epilogue is max. 12 bytes long. */
6588 CORE_ADDR addr = func_end - 12;
6590 if (addr < func_addr + 4)
6591 addr = func_addr + 4;
6595 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
6597 unsigned short inst;
6599 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL);
6601 if ((inst & 0xf800) == 0xf000) /* extend */
6604 if (inst != 0x6300 /* addiu $sp,offset */
6605 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
6606 && inst != 0xe820 /* jr $ra */
6607 && inst != 0xe8a0 /* jrc $ra */
6608 && inst != 0x6500) /* nop */
6618 /* The epilogue is defined here as the area at the end of a function,
6619 after an instruction which destroys the function's stack frame. */
6621 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6623 if (mips_pc_is_mips16 (gdbarch, pc))
6624 return mips16_in_function_epilogue_p (gdbarch, pc);
6625 else if (mips_pc_is_micromips (gdbarch, pc))
6626 return micromips_in_function_epilogue_p (gdbarch, pc);
6628 return mips32_in_function_epilogue_p (gdbarch, pc);
6631 /* Root of all "set mips "/"show mips " commands. This will eventually be
6632 used for all MIPS-specific commands. */
6635 show_mips_command (char *args, int from_tty)
6637 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
6641 set_mips_command (char *args, int from_tty)
6644 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6645 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
6648 /* Commands to show/set the MIPS FPU type. */
6651 show_mipsfpu_command (char *args, int from_tty)
6655 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
6658 ("The MIPS floating-point coprocessor is unknown "
6659 "because the current architecture is not MIPS.\n");
6663 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6665 case MIPS_FPU_SINGLE:
6666 fpu = "single-precision";
6668 case MIPS_FPU_DOUBLE:
6669 fpu = "double-precision";
6672 fpu = "absent (none)";
6675 internal_error (__FILE__, __LINE__, _("bad switch"));
6677 if (mips_fpu_type_auto)
6678 printf_unfiltered ("The MIPS floating-point coprocessor "
6679 "is set automatically (currently %s)\n",
6683 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
6688 set_mipsfpu_command (char *args, int from_tty)
6690 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6691 "\"single\",\"none\" or \"auto\".\n");
6692 show_mipsfpu_command (args, from_tty);
6696 set_mipsfpu_single_command (char *args, int from_tty)
6698 struct gdbarch_info info;
6699 gdbarch_info_init (&info);
6700 mips_fpu_type = MIPS_FPU_SINGLE;
6701 mips_fpu_type_auto = 0;
6702 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6703 instead of relying on globals. Doing that would let generic code
6704 handle the search for this specific architecture. */
6705 if (!gdbarch_update_p (info))
6706 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6710 set_mipsfpu_double_command (char *args, int from_tty)
6712 struct gdbarch_info info;
6713 gdbarch_info_init (&info);
6714 mips_fpu_type = MIPS_FPU_DOUBLE;
6715 mips_fpu_type_auto = 0;
6716 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6717 instead of relying on globals. Doing that would let generic code
6718 handle the search for this specific architecture. */
6719 if (!gdbarch_update_p (info))
6720 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6724 set_mipsfpu_none_command (char *args, int from_tty)
6726 struct gdbarch_info info;
6727 gdbarch_info_init (&info);
6728 mips_fpu_type = MIPS_FPU_NONE;
6729 mips_fpu_type_auto = 0;
6730 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6731 instead of relying on globals. Doing that would let generic code
6732 handle the search for this specific architecture. */
6733 if (!gdbarch_update_p (info))
6734 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6738 set_mipsfpu_auto_command (char *args, int from_tty)
6740 mips_fpu_type_auto = 1;
6743 /* Attempt to identify the particular processor model by reading the
6744 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6745 the relevant processor still exists (it dates back to '94) and
6746 secondly this is not the way to do this. The processor type should
6747 be set by forcing an architecture change. */
6750 deprecated_mips_set_processor_regs_hack (void)
6752 struct regcache *regcache = get_current_regcache ();
6753 struct gdbarch *gdbarch = get_regcache_arch (regcache);
6754 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6757 regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid);
6758 if ((prid & ~0xf) == 0x700)
6759 tdep->mips_processor_reg_names = mips_r3041_reg_names;
6762 /* Just like reinit_frame_cache, but with the right arguments to be
6763 callable as an sfunc. */
6766 reinit_frame_cache_sfunc (char *args, int from_tty,
6767 struct cmd_list_element *c)
6769 reinit_frame_cache ();
6773 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
6775 struct gdbarch *gdbarch = info->application_data;
6777 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6778 disassembler needs to be able to locally determine the ISA, and
6779 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6781 if (mips_pc_is_mips16 (gdbarch, memaddr))
6782 info->mach = bfd_mach_mips16;
6783 else if (mips_pc_is_micromips (gdbarch, memaddr))
6784 info->mach = bfd_mach_mips_micromips;
6786 /* Round down the instruction address to the appropriate boundary. */
6787 memaddr &= (info->mach == bfd_mach_mips16
6788 || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3;
6790 /* Set the disassembler options. */
6791 if (!info->disassembler_options)
6792 /* This string is not recognized explicitly by the disassembler,
6793 but it tells the disassembler to not try to guess the ABI from
6794 the bfd elf headers, such that, if the user overrides the ABI
6795 of a program linked as NewABI, the disassembly will follow the
6796 register naming conventions specified by the user. */
6797 info->disassembler_options = "gpr-names=32";
6799 /* Call the appropriate disassembler based on the target endian-ness. */
6800 if (info->endian == BFD_ENDIAN_BIG)
6801 return print_insn_big_mips (memaddr, info);
6803 return print_insn_little_mips (memaddr, info);
6807 gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
6809 /* Set up the disassembler info, so that we get the right
6810 register names from libopcodes. */
6811 info->disassembler_options = "gpr-names=n32";
6812 info->flavour = bfd_target_elf_flavour;
6814 return gdb_print_insn_mips (memaddr, info);
6818 gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
6820 /* Set up the disassembler info, so that we get the right
6821 register names from libopcodes. */
6822 info->disassembler_options = "gpr-names=64";
6823 info->flavour = bfd_target_elf_flavour;
6825 return gdb_print_insn_mips (memaddr, info);
6828 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6829 program counter value to determine whether a 16- or 32-bit breakpoint
6830 should be used. It returns a pointer to a string of bytes that encode a
6831 breakpoint instruction, stores the length of the string to *lenptr, and
6832 adjusts pc (if necessary) to point to the actual memory location where
6833 the breakpoint should be inserted. */
6835 static const gdb_byte *
6836 mips_breakpoint_from_pc (struct gdbarch *gdbarch,
6837 CORE_ADDR *pcptr, int *lenptr)
6839 CORE_ADDR pc = *pcptr;
6841 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6843 if (mips_pc_is_mips16 (gdbarch, pc))
6845 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
6846 *pcptr = unmake_compact_addr (pc);
6847 *lenptr = sizeof (mips16_big_breakpoint);
6848 return mips16_big_breakpoint;
6850 else if (mips_pc_is_micromips (gdbarch, pc))
6852 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 };
6853 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 };
6858 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
6860 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
6861 *pcptr = unmake_compact_addr (pc);
6863 return (size == 2) ? micromips16_big_breakpoint
6864 : micromips32_big_breakpoint;
6868 /* The IDT board uses an unusual breakpoint value, and
6869 sometimes gets confused when it sees the usual MIPS
6870 breakpoint instruction. */
6871 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
6872 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
6873 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
6874 /* Likewise, IRIX appears to expect a different breakpoint,
6875 although this is not apparent until you try to use pthreads. */
6876 static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd };
6878 *lenptr = sizeof (big_breakpoint);
6880 if (strcmp (target_shortname, "mips") == 0)
6881 return idt_big_breakpoint;
6882 else if (strcmp (target_shortname, "ddb") == 0
6883 || strcmp (target_shortname, "pmon") == 0
6884 || strcmp (target_shortname, "lsi") == 0)
6885 return pmon_big_breakpoint;
6886 else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX)
6887 return irix_big_breakpoint;
6889 return big_breakpoint;
6894 if (mips_pc_is_mips16 (gdbarch, pc))
6896 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
6897 *pcptr = unmake_compact_addr (pc);
6898 *lenptr = sizeof (mips16_little_breakpoint);
6899 return mips16_little_breakpoint;
6901 else if (mips_pc_is_micromips (gdbarch, pc))
6903 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 };
6904 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 };
6909 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
6911 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
6912 *pcptr = unmake_compact_addr (pc);
6914 return (size == 2) ? micromips16_little_breakpoint
6915 : micromips32_little_breakpoint;
6919 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
6920 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
6921 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
6923 *lenptr = sizeof (little_breakpoint);
6925 if (strcmp (target_shortname, "mips") == 0)
6926 return idt_little_breakpoint;
6927 else if (strcmp (target_shortname, "ddb") == 0
6928 || strcmp (target_shortname, "pmon") == 0
6929 || strcmp (target_shortname, "lsi") == 0)
6930 return pmon_little_breakpoint;
6932 return little_breakpoint;
6937 /* Determine the remote breakpoint kind suitable for the PC. The following
6940 * 2 -- 16-bit MIPS16 mode breakpoint,
6942 * 3 -- 16-bit microMIPS mode breakpoint,
6944 * 4 -- 32-bit standard MIPS mode breakpoint,
6946 * 5 -- 32-bit microMIPS mode breakpoint. */
6949 mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
6952 CORE_ADDR pc = *pcptr;
6954 if (mips_pc_is_mips16 (gdbarch, pc))
6956 *pcptr = unmake_compact_addr (pc);
6959 else if (mips_pc_is_micromips (gdbarch, pc))
6965 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
6966 size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
6967 *pcptr = unmake_compact_addr (pc);
6968 *kindptr = size | 1;
6974 /* Return non-zero if the ADDR instruction has a branch delay slot
6975 (i.e. it is a jump or branch instruction). This function is based
6976 on mips32_next_pc. */
6979 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr)
6987 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status);
6991 op = itype_op (inst);
6992 if ((inst & 0xe0000000) != 0)
6994 rs = itype_rs (inst);
6995 rt = itype_rt (inst);
6996 return (is_octeon_bbit_op (op, gdbarch)
6997 || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
6998 || op == 29 /* JALX: bits 011101 */
7001 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7002 || (rs == 9 && (rt & 0x2) == 0)
7003 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7004 || (rs == 10 && (rt & 0x2) == 0))));
7005 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7008 switch (op & 0x07) /* extract bits 28,27,26 */
7010 case 0: /* SPECIAL */
7011 op = rtype_funct (inst);
7012 return (op == 8 /* JR */
7013 || op == 9); /* JALR */
7014 break; /* end SPECIAL */
7015 case 1: /* REGIMM */
7016 rs = itype_rs (inst);
7017 rt = itype_rt (inst); /* branch condition */
7018 return ((rt & 0xc) == 0
7019 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7020 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7021 || ((rt & 0x1e) == 0x1c && rs == 0));
7022 /* BPOSGE32, BPOSGE64: bits 1110x */
7023 break; /* end REGIMM */
7024 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7030 /* Return non-zero if the ADDR instruction, which must be a 32-bit
7031 instruction if MUSTBE32 is set or can be any instruction otherwise,
7032 has a branch delay slot (i.e. it is a non-compact jump instruction). */
7035 micromips_instruction_has_delay_slot (struct gdbarch *gdbarch,
7036 CORE_ADDR addr, int mustbe32)
7041 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7045 if (!mustbe32) /* 16-bit instructions. */
7046 return (micromips_op (insn) == 0x11
7047 /* POOL16C: bits 010001 */
7048 && (b5s5_op (insn) == 0xc
7049 /* JR16: bits 010001 01100 */
7050 || (b5s5_op (insn) & 0x1e) == 0xe))
7051 /* JALR16, JALRS16: bits 010001 0111x */
7052 || (micromips_op (insn) & 0x37) == 0x23
7053 /* BEQZ16, BNEZ16: bits 10x011 */
7054 || micromips_op (insn) == 0x33;
7055 /* B16: bits 110011 */
7057 /* 32-bit instructions. */
7058 if (micromips_op (insn) == 0x0)
7059 /* POOL32A: bits 000000 */
7062 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7065 return b0s6_op (insn) == 0x3c
7066 /* POOL32Axf: bits 000000 ... 111100 */
7067 && (b6s10_ext (insn) & 0x2bf) == 0x3c;
7068 /* JALR, JALR.HB: 000000 000x111100 111100 */
7069 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7072 return (micromips_op (insn) == 0x10
7073 /* POOL32I: bits 010000 */
7074 && ((b5s5_op (insn) & 0x1c) == 0x0
7075 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7076 || (b5s5_op (insn) & 0x1d) == 0x4
7077 /* BLEZ, BGTZ: bits 010000 001x0 */
7078 || (b5s5_op (insn) & 0x1d) == 0x11
7079 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7080 || ((b5s5_op (insn) & 0x1e) == 0x14
7081 && (insn & 0x3) == 0x0)
7082 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7083 || (b5s5_op (insn) & 0x1e) == 0x1a
7084 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7085 || ((b5s5_op (insn) & 0x1e) == 0x1c
7086 && (insn & 0x3) == 0x0)
7087 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7088 || ((b5s5_op (insn) & 0x1c) == 0x1c
7089 && (insn & 0x3) == 0x1)))
7090 /* BC1ANY*: bits 010000 111xx xxx01 */
7091 || (micromips_op (insn) & 0x1f) == 0x1d
7092 /* JALS, JAL: bits x11101 */
7093 || (micromips_op (insn) & 0x37) == 0x25
7094 /* BEQ, BNE: bits 10x101 */
7095 || micromips_op (insn) == 0x35
7096 /* J: bits 110101 */
7097 || micromips_op (insn) == 0x3c;
7098 /* JALX: bits 111100 */
7102 mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr,
7105 unsigned short inst;
7108 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status);
7113 return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
7114 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7117 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7118 This assumes KSSEG exists. */
7121 mips_segment_boundary (CORE_ADDR bpaddr)
7123 CORE_ADDR mask = CORE_ADDR_MAX;
7126 if (sizeof (CORE_ADDR) == 8)
7127 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7128 a compiler warning produced where CORE_ADDR is a 32-bit type even
7129 though in that case this is dead code). */
7130 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3)
7133 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr)
7134 segsize = 29; /* 32-bit compatibility segment */
7136 segsize = 62; /* xkseg */
7138 case 2: /* xkphys */
7141 default: /* xksseg (1), xkuseg/kuseg (0) */
7145 else if (bpaddr & 0x80000000) /* kernel segment */
7148 segsize = 31; /* user segment */
7150 return bpaddr & mask;
7153 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7154 it backwards if necessary. Return the address of the new location. */
7157 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
7159 CORE_ADDR prev_addr;
7161 CORE_ADDR func_addr;
7163 /* If a breakpoint is set on the instruction in a branch delay slot,
7164 GDB gets confused. When the breakpoint is hit, the PC isn't on
7165 the instruction in the branch delay slot, the PC will point to
7166 the branch instruction. Since the PC doesn't match any known
7167 breakpoints, GDB reports a trap exception.
7169 There are two possible fixes for this problem.
7171 1) When the breakpoint gets hit, see if the BD bit is set in the
7172 Cause register (which indicates the last exception occurred in a
7173 branch delay slot). If the BD bit is set, fix the PC to point to
7174 the instruction in the branch delay slot.
7176 2) When the user sets the breakpoint, don't allow him to set the
7177 breakpoint on the instruction in the branch delay slot. Instead
7178 move the breakpoint to the branch instruction (which will have
7181 The problem with the first solution is that if the user then
7182 single-steps the processor, the branch instruction will get
7183 skipped (since GDB thinks the PC is on the instruction in the
7186 So, we'll use the second solution. To do this we need to know if
7187 the instruction we're trying to set the breakpoint on is in the
7188 branch delay slot. */
7190 boundary = mips_segment_boundary (bpaddr);
7192 /* Make sure we don't scan back before the beginning of the current
7193 function, since we may fetch constant data or insns that look like
7194 a jump. Of course we might do that anyway if the compiler has
7195 moved constants inline. :-( */
7196 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL)
7197 && func_addr > boundary && func_addr <= bpaddr)
7198 boundary = func_addr;
7200 if (mips_pc_is_mips (bpaddr))
7202 if (bpaddr == boundary)
7205 /* If the previous instruction has a branch delay slot, we have
7206 to move the breakpoint to the branch instruction. */
7207 prev_addr = bpaddr - 4;
7208 if (mips32_instruction_has_delay_slot (gdbarch, prev_addr))
7213 int (*instruction_has_delay_slot) (struct gdbarch *, CORE_ADDR, int);
7214 CORE_ADDR addr, jmpaddr;
7217 boundary = unmake_compact_addr (boundary);
7219 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7220 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7221 so try for that first, then try the 2 byte JALR/JR.
7222 The microMIPS ASE has a whole range of jumps and branches
7223 with delay slots, some of which take 4 bytes and some take
7224 2 bytes, so the idea is the same.
7225 FIXME: We have to assume that bpaddr is not the second half
7226 of an extended instruction. */
7227 instruction_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr)
7228 ? micromips_instruction_has_delay_slot
7229 : mips16_instruction_has_delay_slot);
7233 for (i = 1; i < 4; i++)
7235 if (unmake_compact_addr (addr) == boundary)
7237 addr -= MIPS_INSN16_SIZE;
7238 if (i == 1 && instruction_has_delay_slot (gdbarch, addr, 0))
7239 /* Looks like a JR/JALR at [target-1], but it could be
7240 the second word of a previous JAL/JALX, so record it
7241 and check back one more. */
7243 else if (i > 1 && instruction_has_delay_slot (gdbarch, addr, 1))
7246 /* Looks like a JAL/JALX at [target-2], but it could also
7247 be the second word of a previous JAL/JALX, record it,
7248 and check back one more. */
7251 /* Looks like a JAL/JALX at [target-3], so any previously
7252 recorded JAL/JALX or JR/JALR must be wrong, because:
7255 -2: JAL-ext (can't be JAL/JALX)
7256 -1: bdslot (can't be JR/JALR)
7259 Of course it could be another JAL-ext which looks
7260 like a JAL, but in that case we'd have broken out
7261 of this loop at [target-2]:
7265 -2: bdslot (can't be jmp)
7272 /* Not a jump instruction: if we're at [target-1] this
7273 could be the second word of a JAL/JALX, so continue;
7274 otherwise we're done. */
7287 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7288 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7291 mips_is_stub_suffix (const char *suffix, int zero)
7296 return zero && suffix[1] == '\0';
7298 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0');
7303 return suffix[1] == '\0';
7309 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7310 call stubs, one of sf, df, sc, or dc. */
7313 mips_is_stub_mode (const char *mode)
7315 return ((mode[0] == 's' || mode[0] == 'd')
7316 && (mode[1] == 'f' || mode[1] == 'c'));
7319 /* Code at PC is a compiler-generated stub. Such a stub for a function
7320 bar might have a name like __fn_stub_bar, and might look like this:
7327 followed by (or interspersed with):
7334 addiu $25, $25, %lo(bar)
7337 ($1 may be used in old code; for robustness we accept any register)
7340 lui $28, %hi(_gp_disp)
7341 addiu $28, $28, %lo(_gp_disp)
7344 addiu $25, $25, %lo(bar)
7347 In the case of a __call_stub_bar stub, the sequence to set up
7348 arguments might look like this:
7355 followed by (or interspersed with) one of the jump sequences above.
7357 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7358 of J or JR, respectively, followed by:
7364 We are at the beginning of the stub here, and scan down and extract
7365 the target address from the jump immediate instruction or, if a jump
7366 register instruction is used, from the register referred. Return
7367 the value of PC calculated or 0 if inconclusive.
7369 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7372 mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc)
7374 struct gdbarch *gdbarch = get_frame_arch (frame);
7375 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7376 int addrreg = MIPS_ZERO_REGNUM;
7377 CORE_ADDR start_pc = pc;
7378 CORE_ADDR target_pc = 0;
7385 status == 0 && target_pc == 0 && i < 20;
7386 i++, pc += MIPS_INSN32_SIZE)
7388 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
7394 switch (itype_op (inst))
7396 case 0: /* SPECIAL */
7397 switch (rtype_funct (inst))
7401 rs = rtype_rs (inst);
7402 if (rs == MIPS_GP_REGNUM)
7403 target_pc = gp; /* Hmm... */
7404 else if (rs == addrreg)
7408 case 0x21: /* ADDU */
7409 rt = rtype_rt (inst);
7410 rs = rtype_rs (inst);
7411 rd = rtype_rd (inst);
7412 if (rd == MIPS_GP_REGNUM
7413 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM)
7414 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM)))
7422 target_pc = jtype_target (inst) << 2;
7423 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
7427 rt = itype_rt (inst);
7428 rs = itype_rs (inst);
7431 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7432 if (rt == MIPS_GP_REGNUM)
7434 else if (rt == addrreg)
7440 rt = itype_rt (inst);
7441 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16;
7442 if (rt == MIPS_GP_REGNUM)
7444 else if (rt != MIPS_ZERO_REGNUM)
7452 rt = itype_rt (inst);
7453 rs = itype_rs (inst);
7454 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7455 if (gp != 0 && rs == MIPS_GP_REGNUM)
7459 memset (buf, 0, sizeof (buf));
7460 status = target_read_memory (gp + imm, buf, sizeof (buf));
7462 addr = extract_signed_integer (buf, sizeof (buf), byte_order);
7471 /* If PC is in a MIPS16 call or return stub, return the address of the
7472 target PC, which is either the callee or the caller. There are several
7473 cases which must be handled:
7475 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7476 and the target PC is in $31 ($ra).
7477 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7478 and the target PC is in $2.
7479 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7480 i.e. before the JALR instruction, this is effectively a call stub
7481 and the target PC is in $2. Otherwise this is effectively
7482 a return stub and the target PC is in $18.
7483 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7484 JAL or JALR instruction, this is effectively a call stub and the
7485 target PC is buried in the instruction stream. Otherwise this
7486 is effectively a return stub and the target PC is in $18.
7487 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7488 stub and the target PC is buried in the instruction stream.
7490 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7491 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7495 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7497 struct gdbarch *gdbarch = get_frame_arch (frame);
7498 CORE_ADDR start_addr;
7502 /* Find the starting address and name of the function containing the PC. */
7503 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
7506 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7507 and the target PC is in $31 ($ra). */
7508 prefixlen = strlen (mips_str_mips16_ret_stub);
7509 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7510 && mips_is_stub_mode (name + prefixlen)
7511 && name[prefixlen + 2] == '\0')
7512 return get_frame_register_signed
7513 (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
7515 /* If the PC is in __mips16_call_stub_*, this is one of the call
7516 call/return stubs. */
7517 prefixlen = strlen (mips_str_mips16_call_stub);
7518 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0)
7520 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7521 and the target PC is in $2. */
7522 if (mips_is_stub_suffix (name + prefixlen, 0))
7523 return get_frame_register_signed
7524 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7526 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7527 i.e. before the JALR instruction, this is effectively a call stub
7528 and the target PC is in $2. Otherwise this is effectively
7529 a return stub and the target PC is in $18. */
7530 else if (mips_is_stub_mode (name + prefixlen)
7531 && name[prefixlen + 2] == '_'
7532 && mips_is_stub_suffix (name + prefixlen + 3, 0))
7534 if (pc == start_addr)
7535 /* This is the 'call' part of a call stub. The return
7536 address is in $2. */
7537 return get_frame_register_signed
7538 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7540 /* This is the 'return' part of a call stub. The return
7541 address is in $18. */
7542 return get_frame_register_signed
7543 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7546 return 0; /* Not a stub. */
7549 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7550 compiler-generated call or call/return stubs. */
7551 if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0
7552 || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0)
7554 if (pc == start_addr)
7555 /* This is the 'call' part of a call stub. Call this helper
7556 to scan through this code for interesting instructions
7557 and determine the final PC. */
7558 return mips_get_mips16_fn_stub_pc (frame, pc);
7560 /* This is the 'return' part of a call stub. The return address
7562 return get_frame_register_signed
7563 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7566 return 0; /* Not a stub. */
7569 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7570 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7573 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name)
7575 CORE_ADDR start_addr;
7578 /* Find the starting address of the function containing the PC. */
7579 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
7582 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7583 the start, i.e. after the JALR instruction, this is effectively
7585 prefixlen = strlen (mips_str_mips16_call_stub);
7586 if (pc != start_addr
7587 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0
7588 && mips_is_stub_mode (name + prefixlen)
7589 && name[prefixlen + 2] == '_'
7590 && mips_is_stub_suffix (name + prefixlen + 3, 1))
7593 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7594 the JAL or JALR instruction, this is effectively a return stub. */
7595 prefixlen = strlen (mips_str_call_fp_stub);
7596 if (pc != start_addr
7597 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0)
7600 /* Consume the .pic. prefix of any PIC stub, this function must return
7601 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7602 or the call stub path will trigger in handle_inferior_event causing
7604 prefixlen = strlen (mips_str_pic);
7605 if (strncmp (name, mips_str_pic, prefixlen) == 0)
7608 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7609 prefixlen = strlen (mips_str_mips16_ret_stub);
7610 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7611 && mips_is_stub_mode (name + prefixlen)
7612 && name[prefixlen + 2] == '\0')
7615 return 0; /* Not a stub. */
7618 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7619 PC of the stub target. The stub just loads $t9 and jumps to it,
7620 so that $t9 has the correct value at function entry. */
7623 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7625 struct gdbarch *gdbarch = get_frame_arch (frame);
7626 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7627 struct bound_minimal_symbol msym;
7629 gdb_byte stub_code[16];
7630 int32_t stub_words[4];
7632 /* The stub for foo is named ".pic.foo", and is either two
7633 instructions inserted before foo or a three instruction sequence
7634 which jumps to foo. */
7635 msym = lookup_minimal_symbol_by_pc (pc);
7636 if (msym.minsym == NULL
7637 || SYMBOL_VALUE_ADDRESS (msym.minsym) != pc
7638 || SYMBOL_LINKAGE_NAME (msym.minsym) == NULL
7639 || strncmp (SYMBOL_LINKAGE_NAME (msym.minsym), ".pic.", 5) != 0)
7642 /* A two-instruction header. */
7643 if (MSYMBOL_SIZE (msym.minsym) == 8)
7646 /* A three-instruction (plus delay slot) trampoline. */
7647 if (MSYMBOL_SIZE (msym.minsym) == 16)
7649 if (target_read_memory (pc, stub_code, 16) != 0)
7651 for (i = 0; i < 4; i++)
7652 stub_words[i] = extract_unsigned_integer (stub_code + i * 4,
7655 /* A stub contains these instructions:
7658 addiu t9, t9, %lo(target)
7661 This works even for N64, since stubs are only generated with
7663 if ((stub_words[0] & 0xffff0000U) == 0x3c190000
7664 && (stub_words[1] & 0xfc000000U) == 0x08000000
7665 && (stub_words[2] & 0xffff0000U) == 0x27390000
7666 && stub_words[3] == 0x00000000)
7667 return ((((stub_words[0] & 0x0000ffff) << 16)
7668 + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7671 /* Not a recognized stub. */
7676 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7678 CORE_ADDR requested_pc = pc;
7679 CORE_ADDR target_pc;
7686 new_pc = mips_skip_mips16_trampoline_code (frame, pc);
7690 if (is_compact_addr (pc))
7691 pc = unmake_compact_addr (pc);
7694 new_pc = find_solib_trampoline_target (frame, pc);
7698 if (is_compact_addr (pc))
7699 pc = unmake_compact_addr (pc);
7702 new_pc = mips_skip_pic_trampoline_code (frame, pc);
7706 if (is_compact_addr (pc))
7707 pc = unmake_compact_addr (pc);
7710 while (pc != target_pc);
7712 return pc != requested_pc ? pc : 0;
7715 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7716 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7719 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
7722 if (num >= 0 && num < 32)
7724 else if (num >= 38 && num < 70)
7725 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
7727 regnum = mips_regnum (gdbarch)->hi;
7729 regnum = mips_regnum (gdbarch)->lo;
7730 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78)
7731 regnum = num + mips_regnum (gdbarch)->dspacc - 72;
7733 /* This will hopefully (eventually) provoke a warning. Should
7734 we be calling complaint() here? */
7735 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
7736 return gdbarch_num_regs (gdbarch) + regnum;
7740 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7741 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7744 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
7747 if (num >= 0 && num < 32)
7749 else if (num >= 32 && num < 64)
7750 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
7752 regnum = mips_regnum (gdbarch)->hi;
7754 regnum = mips_regnum (gdbarch)->lo;
7755 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72)
7756 regnum = num + mips_regnum (gdbarch)->dspacc - 66;
7758 /* This will hopefully (eventually) provoke a warning. Should we
7759 be calling complaint() here? */
7760 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
7761 return gdbarch_num_regs (gdbarch) + regnum;
7765 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
7767 /* Only makes sense to supply raw registers. */
7768 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
7769 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7770 decide if it is valid. Should instead define a standard sim/gdb
7771 register numbering scheme. */
7772 if (gdbarch_register_name (gdbarch,
7773 gdbarch_num_regs (gdbarch) + regnum) != NULL
7774 && gdbarch_register_name (gdbarch,
7775 gdbarch_num_regs (gdbarch)
7776 + regnum)[0] != '\0')
7779 return LEGACY_SIM_REGNO_IGNORE;
7783 /* Convert an integer into an address. Extracting the value signed
7784 guarantees a correctly sign extended address. */
7787 mips_integer_to_address (struct gdbarch *gdbarch,
7788 struct type *type, const gdb_byte *buf)
7790 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7791 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
7794 /* Dummy virtual frame pointer method. This is no more or less accurate
7795 than most other architectures; we just need to be explicit about it,
7796 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7797 an assertion failure. */
7800 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
7801 CORE_ADDR pc, int *reg, LONGEST *offset)
7803 *reg = MIPS_SP_REGNUM;
7808 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
7810 enum mips_abi *abip = (enum mips_abi *) obj;
7811 const char *name = bfd_get_section_name (abfd, sect);
7813 if (*abip != MIPS_ABI_UNKNOWN)
7816 if (strncmp (name, ".mdebug.", 8) != 0)
7819 if (strcmp (name, ".mdebug.abi32") == 0)
7820 *abip = MIPS_ABI_O32;
7821 else if (strcmp (name, ".mdebug.abiN32") == 0)
7822 *abip = MIPS_ABI_N32;
7823 else if (strcmp (name, ".mdebug.abi64") == 0)
7824 *abip = MIPS_ABI_N64;
7825 else if (strcmp (name, ".mdebug.abiO64") == 0)
7826 *abip = MIPS_ABI_O64;
7827 else if (strcmp (name, ".mdebug.eabi32") == 0)
7828 *abip = MIPS_ABI_EABI32;
7829 else if (strcmp (name, ".mdebug.eabi64") == 0)
7830 *abip = MIPS_ABI_EABI64;
7832 warning (_("unsupported ABI %s."), name + 8);
7836 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
7838 int *lbp = (int *) obj;
7839 const char *name = bfd_get_section_name (abfd, sect);
7841 if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
7843 else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
7845 else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
7846 warning (_("unrecognized .gcc_compiled_longXX"));
7849 static enum mips_abi
7850 global_mips_abi (void)
7854 for (i = 0; mips_abi_strings[i] != NULL; i++)
7855 if (mips_abi_strings[i] == mips_abi_string)
7856 return (enum mips_abi) i;
7858 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
7861 /* Return the default compressed instruction set, either of MIPS16
7862 or microMIPS, selected when none could have been determined from
7863 the ELF header of the binary being executed (or no binary has been
7866 static enum mips_isa
7867 global_mips_compression (void)
7871 for (i = 0; mips_compression_strings[i] != NULL; i++)
7872 if (mips_compression_strings[i] == mips_compression_string)
7873 return (enum mips_isa) i;
7875 internal_error (__FILE__, __LINE__, _("unknown compressed ISA string"));
7879 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
7881 /* If the size matches the set of 32-bit or 64-bit integer registers,
7882 assume that's what we've got. */
7883 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
7884 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
7886 /* If the size matches the full set of registers GDB traditionally
7887 knows about, including floating point, for either 32-bit or
7888 64-bit, assume that's what we've got. */
7889 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
7890 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
7892 /* Otherwise we don't have a useful guess. */
7895 static struct value *
7896 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
7898 const int *reg_p = baton;
7899 return value_of_register (*reg_p, frame);
7902 static struct gdbarch *
7903 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7905 struct gdbarch *gdbarch;
7906 struct gdbarch_tdep *tdep;
7908 enum mips_abi mips_abi, found_abi, wanted_abi;
7910 enum mips_fpu_type fpu_type;
7911 struct tdesc_arch_data *tdesc_data = NULL;
7912 int elf_fpu_type = 0;
7913 const char **reg_names;
7914 struct mips_regnum mips_regnum, *regnum;
7915 enum mips_isa mips_isa;
7919 /* Fill in the OS dependent register numbers and names. */
7920 if (info.osabi == GDB_OSABI_IRIX)
7922 mips_regnum.fp0 = 32;
7923 mips_regnum.pc = 64;
7924 mips_regnum.cause = 65;
7925 mips_regnum.badvaddr = 66;
7926 mips_regnum.hi = 67;
7927 mips_regnum.lo = 68;
7928 mips_regnum.fp_control_status = 69;
7929 mips_regnum.fp_implementation_revision = 70;
7930 mips_regnum.dspacc = dspacc = -1;
7931 mips_regnum.dspctl = dspctl = -1;
7933 reg_names = mips_irix_reg_names;
7935 else if (info.osabi == GDB_OSABI_LINUX)
7937 mips_regnum.fp0 = 38;
7938 mips_regnum.pc = 37;
7939 mips_regnum.cause = 36;
7940 mips_regnum.badvaddr = 35;
7941 mips_regnum.hi = 34;
7942 mips_regnum.lo = 33;
7943 mips_regnum.fp_control_status = 70;
7944 mips_regnum.fp_implementation_revision = 71;
7945 mips_regnum.dspacc = -1;
7946 mips_regnum.dspctl = -1;
7950 reg_names = mips_linux_reg_names;
7954 mips_regnum.lo = MIPS_EMBED_LO_REGNUM;
7955 mips_regnum.hi = MIPS_EMBED_HI_REGNUM;
7956 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
7957 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM;
7958 mips_regnum.pc = MIPS_EMBED_PC_REGNUM;
7959 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM;
7960 mips_regnum.fp_control_status = 70;
7961 mips_regnum.fp_implementation_revision = 71;
7962 mips_regnum.dspacc = dspacc = -1;
7963 mips_regnum.dspctl = dspctl = -1;
7964 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
7965 if (info.bfd_arch_info != NULL
7966 && info.bfd_arch_info->mach == bfd_mach_mips3900)
7967 reg_names = mips_tx39_reg_names;
7969 reg_names = mips_generic_reg_names;
7972 /* Check any target description for validity. */
7973 if (tdesc_has_registers (info.target_desc))
7975 static const char *const mips_gprs[] = {
7976 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7977 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7978 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7979 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7981 static const char *const mips_fprs[] = {
7982 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7983 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7984 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7985 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
7988 const struct tdesc_feature *feature;
7991 feature = tdesc_find_feature (info.target_desc,
7992 "org.gnu.gdb.mips.cpu");
7993 if (feature == NULL)
7996 tdesc_data = tdesc_data_alloc ();
7999 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
8000 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8004 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8005 mips_regnum.lo, "lo");
8006 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8007 mips_regnum.hi, "hi");
8008 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8009 mips_regnum.pc, "pc");
8013 tdesc_data_cleanup (tdesc_data);
8017 feature = tdesc_find_feature (info.target_desc,
8018 "org.gnu.gdb.mips.cp0");
8019 if (feature == NULL)
8021 tdesc_data_cleanup (tdesc_data);
8026 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8027 mips_regnum.badvaddr, "badvaddr");
8028 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8029 MIPS_PS_REGNUM, "status");
8030 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8031 mips_regnum.cause, "cause");
8035 tdesc_data_cleanup (tdesc_data);
8039 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8040 backend is not prepared for that, though. */
8041 feature = tdesc_find_feature (info.target_desc,
8042 "org.gnu.gdb.mips.fpu");
8043 if (feature == NULL)
8045 tdesc_data_cleanup (tdesc_data);
8050 for (i = 0; i < 32; i++)
8051 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8052 i + mips_regnum.fp0, mips_fprs[i]);
8054 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8055 mips_regnum.fp_control_status,
8058 &= tdesc_numbered_register (feature, tdesc_data,
8059 mips_regnum.fp_implementation_revision,
8064 tdesc_data_cleanup (tdesc_data);
8070 feature = tdesc_find_feature (info.target_desc,
8071 "org.gnu.gdb.mips.dsp");
8072 /* The DSP registers are optional; it's OK if they are absent. */
8073 if (feature != NULL)
8077 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8078 dspacc + i++, "hi1");
8079 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8080 dspacc + i++, "lo1");
8081 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8082 dspacc + i++, "hi2");
8083 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8084 dspacc + i++, "lo2");
8085 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8086 dspacc + i++, "hi3");
8087 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8088 dspacc + i++, "lo3");
8090 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8095 tdesc_data_cleanup (tdesc_data);
8099 mips_regnum.dspacc = dspacc;
8100 mips_regnum.dspctl = dspctl;
8104 /* It would be nice to detect an attempt to use a 64-bit ABI
8105 when only 32-bit registers are provided. */
8109 /* First of all, extract the elf_flags, if available. */
8110 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8111 elf_flags = elf_elfheader (info.abfd)->e_flags;
8112 else if (arches != NULL)
8113 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
8117 fprintf_unfiltered (gdb_stdlog,
8118 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
8120 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8121 switch ((elf_flags & EF_MIPS_ABI))
8123 case E_MIPS_ABI_O32:
8124 found_abi = MIPS_ABI_O32;
8126 case E_MIPS_ABI_O64:
8127 found_abi = MIPS_ABI_O64;
8129 case E_MIPS_ABI_EABI32:
8130 found_abi = MIPS_ABI_EABI32;
8132 case E_MIPS_ABI_EABI64:
8133 found_abi = MIPS_ABI_EABI64;
8136 if ((elf_flags & EF_MIPS_ABI2))
8137 found_abi = MIPS_ABI_N32;
8139 found_abi = MIPS_ABI_UNKNOWN;
8143 /* GCC creates a pseudo-section whose name describes the ABI. */
8144 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
8145 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
8147 /* If we have no useful BFD information, use the ABI from the last
8148 MIPS architecture (if there is one). */
8149 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
8150 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
8152 /* Try the architecture for any hint of the correct ABI. */
8153 if (found_abi == MIPS_ABI_UNKNOWN
8154 && info.bfd_arch_info != NULL
8155 && info.bfd_arch_info->arch == bfd_arch_mips)
8157 switch (info.bfd_arch_info->mach)
8159 case bfd_mach_mips3900:
8160 found_abi = MIPS_ABI_EABI32;
8162 case bfd_mach_mips4100:
8163 case bfd_mach_mips5000:
8164 found_abi = MIPS_ABI_EABI64;
8166 case bfd_mach_mips8000:
8167 case bfd_mach_mips10000:
8168 /* On Irix, ELF64 executables use the N64 ABI. The
8169 pseudo-sections which describe the ABI aren't present
8170 on IRIX. (Even for executables created by gcc.) */
8171 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8172 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8173 found_abi = MIPS_ABI_N64;
8175 found_abi = MIPS_ABI_N32;
8180 /* Default 64-bit objects to N64 instead of O32. */
8181 if (found_abi == MIPS_ABI_UNKNOWN
8182 && info.abfd != NULL
8183 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8184 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8185 found_abi = MIPS_ABI_N64;
8188 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
8191 /* What has the user specified from the command line? */
8192 wanted_abi = global_mips_abi ();
8194 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
8197 /* Now that we have found what the ABI for this binary would be,
8198 check whether the user is overriding it. */
8199 if (wanted_abi != MIPS_ABI_UNKNOWN)
8200 mips_abi = wanted_abi;
8201 else if (found_abi != MIPS_ABI_UNKNOWN)
8202 mips_abi = found_abi;
8204 mips_abi = MIPS_ABI_O32;
8206 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
8209 /* Determine the default compressed ISA. */
8210 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0
8211 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0)
8212 mips_isa = ISA_MICROMIPS;
8213 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0
8214 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0)
8215 mips_isa = ISA_MIPS16;
8217 mips_isa = global_mips_compression ();
8218 mips_compression_string = mips_compression_strings[mips_isa];
8220 /* Also used when doing an architecture lookup. */
8222 fprintf_unfiltered (gdb_stdlog,
8223 "mips_gdbarch_init: "
8224 "mips64_transfers_32bit_regs_p = %d\n",
8225 mips64_transfers_32bit_regs_p);
8227 /* Determine the MIPS FPU type. */
8230 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8231 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
8232 Tag_GNU_MIPS_ABI_FP);
8233 #endif /* HAVE_ELF */
8235 if (!mips_fpu_type_auto)
8236 fpu_type = mips_fpu_type;
8237 else if (elf_fpu_type != 0)
8239 switch (elf_fpu_type)
8242 fpu_type = MIPS_FPU_DOUBLE;
8245 fpu_type = MIPS_FPU_SINGLE;
8249 /* Soft float or unknown. */
8250 fpu_type = MIPS_FPU_NONE;
8254 else if (info.bfd_arch_info != NULL
8255 && info.bfd_arch_info->arch == bfd_arch_mips)
8256 switch (info.bfd_arch_info->mach)
8258 case bfd_mach_mips3900:
8259 case bfd_mach_mips4100:
8260 case bfd_mach_mips4111:
8261 case bfd_mach_mips4120:
8262 fpu_type = MIPS_FPU_NONE;
8264 case bfd_mach_mips4650:
8265 fpu_type = MIPS_FPU_SINGLE;
8268 fpu_type = MIPS_FPU_DOUBLE;
8271 else if (arches != NULL)
8272 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
8274 fpu_type = MIPS_FPU_DOUBLE;
8276 fprintf_unfiltered (gdb_stdlog,
8277 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
8279 /* Check for blatant incompatibilities. */
8281 /* If we have only 32-bit registers, then we can't debug a 64-bit
8283 if (info.target_desc
8284 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
8285 && mips_abi != MIPS_ABI_EABI32
8286 && mips_abi != MIPS_ABI_O32)
8288 if (tdesc_data != NULL)
8289 tdesc_data_cleanup (tdesc_data);
8293 /* Try to find a pre-existing architecture. */
8294 for (arches = gdbarch_list_lookup_by_info (arches, &info);
8296 arches = gdbarch_list_lookup_by_info (arches->next, &info))
8298 /* MIPS needs to be pedantic about which ABI the object is
8300 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
8302 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
8304 /* Need to be pedantic about which register virtual size is
8306 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
8307 != mips64_transfers_32bit_regs_p)
8309 /* Be pedantic about which FPU is selected. */
8310 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
8313 if (tdesc_data != NULL)
8314 tdesc_data_cleanup (tdesc_data);
8315 return arches->gdbarch;
8318 /* Need a new architecture. Fill in a target specific vector. */
8319 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
8320 gdbarch = gdbarch_alloc (&info, tdep);
8321 tdep->elf_flags = elf_flags;
8322 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
8323 tdep->found_abi = found_abi;
8324 tdep->mips_abi = mips_abi;
8325 tdep->mips_isa = mips_isa;
8326 tdep->mips_fpu_type = fpu_type;
8327 tdep->register_size_valid_p = 0;
8328 tdep->register_size = 0;
8329 tdep->gregset = NULL;
8330 tdep->gregset64 = NULL;
8331 tdep->fpregset = NULL;
8332 tdep->fpregset64 = NULL;
8334 if (info.target_desc)
8336 /* Some useful properties can be inferred from the target. */
8337 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
8339 tdep->register_size_valid_p = 1;
8340 tdep->register_size = 4;
8342 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
8344 tdep->register_size_valid_p = 1;
8345 tdep->register_size = 8;
8349 /* Initially set everything according to the default ABI/ISA. */
8350 set_gdbarch_short_bit (gdbarch, 16);
8351 set_gdbarch_int_bit (gdbarch, 32);
8352 set_gdbarch_float_bit (gdbarch, 32);
8353 set_gdbarch_double_bit (gdbarch, 64);
8354 set_gdbarch_long_double_bit (gdbarch, 64);
8355 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
8356 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
8357 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
8359 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8360 mips_ax_pseudo_register_collect);
8361 set_gdbarch_ax_pseudo_register_push_stack
8362 (gdbarch, mips_ax_pseudo_register_push_stack);
8364 set_gdbarch_elf_make_msymbol_special (gdbarch,
8365 mips_elf_make_msymbol_special);
8367 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum);
8368 *regnum = mips_regnum;
8369 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
8370 set_gdbarch_num_regs (gdbarch, num_regs);
8371 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8372 set_gdbarch_register_name (gdbarch, mips_register_name);
8373 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
8374 tdep->mips_processor_reg_names = reg_names;
8375 tdep->regnum = regnum;
8380 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
8381 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
8382 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8383 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8384 tdep->default_mask_address_p = 0;
8385 set_gdbarch_long_bit (gdbarch, 32);
8386 set_gdbarch_ptr_bit (gdbarch, 32);
8387 set_gdbarch_long_long_bit (gdbarch, 64);
8390 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
8391 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
8392 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8393 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8394 tdep->default_mask_address_p = 0;
8395 set_gdbarch_long_bit (gdbarch, 32);
8396 set_gdbarch_ptr_bit (gdbarch, 32);
8397 set_gdbarch_long_long_bit (gdbarch, 64);
8399 case MIPS_ABI_EABI32:
8400 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8401 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8402 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8403 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8404 tdep->default_mask_address_p = 0;
8405 set_gdbarch_long_bit (gdbarch, 32);
8406 set_gdbarch_ptr_bit (gdbarch, 32);
8407 set_gdbarch_long_long_bit (gdbarch, 64);
8409 case MIPS_ABI_EABI64:
8410 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8411 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8412 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8413 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8414 tdep->default_mask_address_p = 0;
8415 set_gdbarch_long_bit (gdbarch, 64);
8416 set_gdbarch_ptr_bit (gdbarch, 64);
8417 set_gdbarch_long_long_bit (gdbarch, 64);
8420 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8421 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8422 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8423 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8424 tdep->default_mask_address_p = 0;
8425 set_gdbarch_long_bit (gdbarch, 32);
8426 set_gdbarch_ptr_bit (gdbarch, 32);
8427 set_gdbarch_long_long_bit (gdbarch, 64);
8428 set_gdbarch_long_double_bit (gdbarch, 128);
8429 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8432 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8433 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8434 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8435 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8436 tdep->default_mask_address_p = 0;
8437 set_gdbarch_long_bit (gdbarch, 64);
8438 set_gdbarch_ptr_bit (gdbarch, 64);
8439 set_gdbarch_long_long_bit (gdbarch, 64);
8440 set_gdbarch_long_double_bit (gdbarch, 128);
8441 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8444 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8447 /* GCC creates a pseudo-section whose name specifies the size of
8448 longs, since -mlong32 or -mlong64 may be used independent of
8449 other options. How those options affect pointer sizes is ABI and
8450 architecture dependent, so use them to override the default sizes
8451 set by the ABI. This table shows the relationship between ABI,
8452 -mlongXX, and size of pointers:
8454 ABI -mlongXX ptr bits
8455 --- -------- --------
8469 Note that for o32 and eabi32, pointers are always 32 bits
8470 regardless of any -mlongXX option. For all others, pointers and
8471 longs are the same, as set by -mlongXX or set by defaults. */
8473 if (info.abfd != NULL)
8477 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
8480 set_gdbarch_long_bit (gdbarch, long_bit);
8484 case MIPS_ABI_EABI32:
8489 case MIPS_ABI_EABI64:
8490 set_gdbarch_ptr_bit (gdbarch, long_bit);
8493 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8498 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8499 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8502 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8503 flag in object files because to do so would make it impossible to
8504 link with libraries compiled without "-gp32". This is
8505 unnecessarily restrictive.
8507 We could solve this problem by adding "-gp32" multilibs to gcc,
8508 but to set this flag before gcc is built with such multilibs will
8509 break too many systems.''
8511 But even more unhelpfully, the default linker output target for
8512 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8513 for 64-bit programs - you need to change the ABI to change this,
8514 and not all gcc targets support that currently. Therefore using
8515 this flag to detect 32-bit mode would do the wrong thing given
8516 the current gcc - it would make GDB treat these 64-bit programs
8517 as 32-bit programs by default. */
8519 set_gdbarch_read_pc (gdbarch, mips_read_pc);
8520 set_gdbarch_write_pc (gdbarch, mips_write_pc);
8522 /* Add/remove bits from an address. The MIPS needs be careful to
8523 ensure that all 32 bit addresses are sign extended to 64 bits. */
8524 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
8526 /* Unwind the frame. */
8527 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
8528 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
8529 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
8531 /* Map debug register numbers onto internal register numbers. */
8532 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
8533 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
8534 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8535 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
8536 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8537 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
8539 /* MIPS version of CALL_DUMMY. */
8541 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8542 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code);
8543 set_gdbarch_frame_align (gdbarch, mips_frame_align);
8545 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
8546 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
8547 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
8549 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8550 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
8551 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
8552 mips_remote_breakpoint_from_pc);
8553 set_gdbarch_adjust_breakpoint_address (gdbarch,
8554 mips_adjust_breakpoint_address);
8556 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
8558 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
8560 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
8561 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
8562 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
8564 set_gdbarch_register_type (gdbarch, mips_register_type);
8566 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
8568 if (mips_abi == MIPS_ABI_N32)
8569 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
8570 else if (mips_abi == MIPS_ABI_N64)
8571 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
8573 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
8575 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8576 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8577 need to all be folded into the target vector. Since they are
8578 being used as guards for target_stopped_by_watchpoint, why not have
8579 target_stopped_by_watchpoint return the type of watchpoint that the code
8581 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
8583 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
8585 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8586 to support MIPS16. This is a bad thing. Make sure not to do it
8587 if we have an OS ABI that actually supports shared libraries, since
8588 shared library support is more important. If we have an OS someday
8589 that supports both shared libraries and MIPS16, we'll have to find
8590 a better place for these.
8591 macro/2012-04-25: But that applies to return trampolines only and
8592 currently no MIPS OS ABI uses shared libraries that have them. */
8593 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
8595 set_gdbarch_single_step_through_delay (gdbarch,
8596 mips_single_step_through_delay);
8598 /* Virtual tables. */
8599 set_gdbarch_vbit_in_delta (gdbarch, 1);
8601 mips_register_g_packet_guesses (gdbarch);
8603 /* Hook in OS ABI-specific overrides, if they have been registered. */
8604 info.tdep_info = (void *) tdesc_data;
8605 gdbarch_init_osabi (info, gdbarch);
8607 /* The hook may have adjusted num_regs, fetch the final value and
8608 set pc_regnum and sp_regnum now that it has been fixed. */
8609 num_regs = gdbarch_num_regs (gdbarch);
8610 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
8611 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8613 /* Unwind the frame. */
8614 dwarf2_append_unwinders (gdbarch);
8615 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
8616 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
8617 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind);
8618 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
8619 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
8620 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
8621 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
8622 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer);
8623 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
8627 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
8628 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
8630 /* Override the normal target description methods to handle our
8631 dual real and pseudo registers. */
8632 set_gdbarch_register_name (gdbarch, mips_register_name);
8633 set_gdbarch_register_reggroup_p (gdbarch,
8634 mips_tdesc_register_reggroup_p);
8636 num_regs = gdbarch_num_regs (gdbarch);
8637 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8638 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
8639 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8642 /* Add ABI-specific aliases for the registers. */
8643 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
8644 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
8645 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
8646 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
8648 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
8649 user_reg_add (gdbarch, mips_o32_aliases[i].name,
8650 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
8652 /* Add some other standard aliases. */
8653 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
8654 user_reg_add (gdbarch, mips_register_aliases[i].name,
8655 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
8657 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)
8658 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,
8659 value_of_mips_user_reg,
8660 &mips_numeric_register_aliases[i].regnum);
8666 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
8668 struct gdbarch_info info;
8670 /* Force the architecture to update, and (if it's a MIPS architecture)
8671 mips_gdbarch_init will take care of the rest. */
8672 gdbarch_info_init (&info);
8673 gdbarch_update_p (info);
8676 /* Print out which MIPS ABI is in use. */
8679 show_mips_abi (struct ui_file *file,
8681 struct cmd_list_element *ignored_cmd,
8682 const char *ignored_value)
8684 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
8687 "The MIPS ABI is unknown because the current architecture "
8691 enum mips_abi global_abi = global_mips_abi ();
8692 enum mips_abi actual_abi = mips_abi (target_gdbarch ());
8693 const char *actual_abi_str = mips_abi_strings[actual_abi];
8695 if (global_abi == MIPS_ABI_UNKNOWN)
8698 "The MIPS ABI is set automatically (currently \"%s\").\n",
8700 else if (global_abi == actual_abi)
8703 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8707 /* Probably shouldn't happen... */
8708 fprintf_filtered (file,
8709 "The (auto detected) MIPS ABI \"%s\" is in use "
8710 "even though the user setting was \"%s\".\n",
8711 actual_abi_str, mips_abi_strings[global_abi]);
8716 /* Print out which MIPS compressed ISA encoding is used. */
8719 show_mips_compression (struct ui_file *file, int from_tty,
8720 struct cmd_list_element *c, const char *value)
8722 fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"),
8727 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
8729 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8733 int ef_mips_32bitmode;
8734 /* Determine the ISA. */
8735 switch (tdep->elf_flags & EF_MIPS_ARCH)
8753 /* Determine the size of a pointer. */
8754 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
8755 fprintf_unfiltered (file,
8756 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8758 fprintf_unfiltered (file,
8759 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8761 fprintf_unfiltered (file,
8762 "mips_dump_tdep: ef_mips_arch = %d\n",
8764 fprintf_unfiltered (file,
8765 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8766 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
8767 fprintf_unfiltered (file,
8769 "mips_mask_address_p() %d (default %d)\n",
8770 mips_mask_address_p (tdep),
8771 tdep->default_mask_address_p);
8773 fprintf_unfiltered (file,
8774 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8775 MIPS_DEFAULT_FPU_TYPE,
8776 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
8777 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
8778 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
8780 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
8781 MIPS_EABI (gdbarch));
8782 fprintf_unfiltered (file,
8783 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8784 MIPS_FPU_TYPE (gdbarch),
8785 (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none"
8786 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single"
8787 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double"
8791 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
8794 _initialize_mips_tdep (void)
8796 static struct cmd_list_element *mipsfpulist = NULL;
8797 struct cmd_list_element *c;
8799 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
8800 if (MIPS_ABI_LAST + 1
8801 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
8802 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
8804 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
8806 mips_pdr_data = register_objfile_data ();
8808 /* Create feature sets with the appropriate properties. The values
8809 are not important. */
8810 mips_tdesc_gp32 = allocate_target_description ();
8811 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
8813 mips_tdesc_gp64 = allocate_target_description ();
8814 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
8816 /* Add root prefix command for all "set mips"/"show mips" commands. */
8817 add_prefix_cmd ("mips", no_class, set_mips_command,
8818 _("Various MIPS specific commands."),
8819 &setmipscmdlist, "set mips ", 0, &setlist);
8821 add_prefix_cmd ("mips", no_class, show_mips_command,
8822 _("Various MIPS specific commands."),
8823 &showmipscmdlist, "show mips ", 0, &showlist);
8825 /* Allow the user to override the ABI. */
8826 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
8827 &mips_abi_string, _("\
8828 Set the MIPS ABI used by this program."), _("\
8829 Show the MIPS ABI used by this program."), _("\
8830 This option can be set to one of:\n\
8831 auto - the default ABI associated with the current binary\n\
8840 &setmipscmdlist, &showmipscmdlist);
8842 /* Allow the user to set the ISA to assume for compressed code if ELF
8843 file flags don't tell or there is no program file selected. This
8844 setting is updated whenever unambiguous ELF file flags are interpreted,
8845 and carried over to subsequent sessions. */
8846 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings,
8847 &mips_compression_string, _("\
8848 Set the compressed ISA encoding used by MIPS code."), _("\
8849 Show the compressed ISA encoding used by MIPS code."), _("\
8850 Select the compressed ISA encoding used in functions that have no symbol\n\
8851 information available. The encoding can be set to either of:\n\
8854 and is updated automatically from ELF file flags if available."),
8856 show_mips_compression,
8857 &setmipscmdlist, &showmipscmdlist);
8859 /* Let the user turn off floating point and set the fence post for
8860 heuristic_proc_start. */
8862 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
8863 _("Set use of MIPS floating-point coprocessor."),
8864 &mipsfpulist, "set mipsfpu ", 0, &setlist);
8865 add_cmd ("single", class_support, set_mipsfpu_single_command,
8866 _("Select single-precision MIPS floating-point coprocessor."),
8868 add_cmd ("double", class_support, set_mipsfpu_double_command,
8869 _("Select double-precision MIPS floating-point coprocessor."),
8871 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
8872 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
8873 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
8874 add_cmd ("none", class_support, set_mipsfpu_none_command,
8875 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
8876 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
8877 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
8878 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
8879 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
8880 _("Select MIPS floating-point coprocessor automatically."),
8882 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
8883 _("Show current use of MIPS floating-point coprocessor target."),
8886 /* We really would like to have both "0" and "unlimited" work, but
8887 command.c doesn't deal with that. So make it a var_zinteger
8888 because the user can always use "999999" or some such for unlimited. */
8889 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
8890 &heuristic_fence_post, _("\
8891 Set the distance searched for the start of a function."), _("\
8892 Show the distance searched for the start of a function."), _("\
8893 If you are debugging a stripped executable, GDB needs to search through the\n\
8894 program for the start of a function. This command sets the distance of the\n\
8895 search. The only need to set it is when debugging a stripped executable."),
8896 reinit_frame_cache_sfunc,
8897 NULL, /* FIXME: i18n: The distance searched for
8898 the start of a function is %s. */
8899 &setlist, &showlist);
8901 /* Allow the user to control whether the upper bits of 64-bit
8902 addresses should be zeroed. */
8903 add_setshow_auto_boolean_cmd ("mask-address", no_class,
8904 &mask_address_var, _("\
8905 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
8906 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
8907 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
8908 allow GDB to determine the correct value."),
8909 NULL, show_mask_address,
8910 &setmipscmdlist, &showmipscmdlist);
8912 /* Allow the user to control the size of 32 bit registers within the
8913 raw remote packet. */
8914 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
8915 &mips64_transfers_32bit_regs_p, _("\
8916 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8918 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8920 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
8921 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
8922 64 bits for others. Use \"off\" to disable compatibility mode"),
8923 set_mips64_transfers_32bit_regs,
8924 NULL, /* FIXME: i18n: Compatibility with 64-bit
8925 MIPS target that transfers 32-bit
8926 quantities is %s. */
8927 &setlist, &showlist);
8929 /* Debug this files internals. */
8930 add_setshow_zuinteger_cmd ("mips", class_maintenance,
8932 Set mips debugging."), _("\
8933 Show mips debugging."), _("\
8934 When non-zero, mips specific debugging is enabled."),
8936 NULL, /* FIXME: i18n: Mips debugging is
8938 &setdebuglist, &showdebuglist);