1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "opcode/mips.h"
47 /* A useful bit in the CP0 status register (PS_REGNUM). */
48 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
49 #define ST0_FR (1 << 26)
51 /* The sizes of floating point registers. */
55 MIPS_FPU_SINGLE_REGSIZE = 4,
56 MIPS_FPU_DOUBLE_REGSIZE = 8
59 /* All the possible MIPS ABIs. */
71 struct frame_extra_info
73 mips_extra_func_info_t proc_desc;
77 /* Various MIPS ISA options (related to stack analysis) can be
78 overridden dynamically. Establish an enum/array for managing
81 static const char size_auto[] = "auto";
82 static const char size_32[] = "32";
83 static const char size_64[] = "64";
85 static const char *size_enums[] = {
92 /* Some MIPS boards don't support floating point while others only
93 support single-precision floating-point operations. See also
94 FP_REGISTER_DOUBLE. */
98 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
99 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
100 MIPS_FPU_NONE /* No floating point. */
103 #ifndef MIPS_DEFAULT_FPU_TYPE
104 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
106 static int mips_fpu_type_auto = 1;
107 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
108 #define MIPS_FPU_TYPE mips_fpu_type
110 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
111 #ifndef FP_REGISTER_DOUBLE
112 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
115 static int mips_debug = 0;
117 /* MIPS specific per-architecture information */
120 /* from the elf header */
123 enum mips_abi mips_abi;
124 const char *mips_abi_string;
125 enum mips_fpu_type mips_fpu_type;
126 int mips_last_arg_regnum;
127 int mips_last_fp_arg_regnum;
128 int mips_default_saved_regsize;
129 int mips_fp_register_double;
130 int mips_regs_have_home_p;
131 int mips_default_stack_argsize;
132 int gdb_target_is_mips64;
133 int default_mask_address_p;
138 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
139 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
143 #undef MIPS_LAST_FP_ARG_REGNUM
144 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
148 #undef MIPS_LAST_ARG_REGNUM
149 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
154 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
160 #undef MIPS_DEFAULT_SAVED_REGSIZE
161 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
162 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
163 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
166 static const char *mips_saved_regsize_string = size_auto;
168 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
171 mips_saved_regsize (void)
173 if (mips_saved_regsize_string == size_auto)
174 return MIPS_DEFAULT_SAVED_REGSIZE;
175 else if (mips_saved_regsize_string == size_64)
177 else /* if (mips_saved_regsize_string == size_32) */
181 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
182 compatiblity mode. A return value of 1 means that we have
183 physical 64-bit registers, but should treat them as 32-bit registers. */
186 mips2_fp_compat (void)
188 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
190 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
194 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
195 in all the places we deal with FP registers. PR gdb/413. */
196 /* Otherwise check the FR bit in the status register - it controls
197 the FP compatiblity mode. If it is clear we are in compatibility
199 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
206 /* Indicate that the ABI makes use of double-precision registers
207 provided by the FPU (rather than combining pairs of registers to
208 form double-precision values). Do not use "TARGET_IS_MIPS64" to
209 determine if the ABI is using double-precision registers. See also
212 #undef FP_REGISTER_DOUBLE
213 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
216 /* Does the caller allocate a ``home'' for each register used in the
217 function call? The N32 ABI and MIPS_EABI do not, the others do. */
220 #undef MIPS_REGS_HAVE_HOME_P
221 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
222 #elif !defined (MIPS_REGS_HAVE_HOME_P)
223 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
226 /* The amount of space reserved on the stack for registers. This is
227 different to MIPS_SAVED_REGSIZE as it determines the alignment of
228 data allocated after the registers have run out. */
231 #undef MIPS_DEFAULT_STACK_ARGSIZE
232 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
233 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
234 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
237 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
239 static const char *mips_stack_argsize_string = size_auto;
242 mips_stack_argsize (void)
244 if (mips_stack_argsize_string == size_auto)
245 return MIPS_DEFAULT_STACK_ARGSIZE;
246 else if (mips_stack_argsize_string == size_64)
248 else /* if (mips_stack_argsize_string == size_32) */
253 #undef GDB_TARGET_IS_MIPS64
254 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
258 #undef MIPS_DEFAULT_MASK_ADDRESS_P
259 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
260 #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P)
261 #define MIPS_DEFAULT_MASK_ADDRESS_P (0)
264 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
266 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
268 static void mips_print_register (int, int);
270 static mips_extra_func_info_t
271 heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int);
273 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
275 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
277 int mips_set_processor_type (char *);
279 static void mips_show_processor_type_command (char *, int);
281 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
283 static mips_extra_func_info_t
284 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame);
286 static CORE_ADDR after_prologue (CORE_ADDR pc,
287 mips_extra_func_info_t proc_desc);
289 static void mips_read_fp_register_single (int regno, char *rare_buffer);
290 static void mips_read_fp_register_double (int regno, char *rare_buffer);
292 /* This value is the model of MIPS in use. It is derived from the value
293 of the PrID register. */
295 char *mips_processor_type;
297 char *tmp_mips_processor_type;
299 /* The list of available "set mips " and "show mips " commands */
301 static struct cmd_list_element *setmipscmdlist = NULL;
302 static struct cmd_list_element *showmipscmdlist = NULL;
304 /* A set of original names, to be used when restoring back to generic
305 registers from a specific set. */
307 char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
308 char **mips_processor_reg_names = mips_generic_reg_names;
311 mips_register_name (int i)
313 return mips_processor_reg_names[i];
316 /* Names of IDT R3041 registers. */
318 char *mips_r3041_reg_names[] = {
319 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
320 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
321 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
322 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
323 "sr", "lo", "hi", "bad", "cause","pc",
324 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
325 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
326 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
327 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
328 "fsr", "fir", "fp", "",
329 "", "", "bus", "ccfg", "", "", "", "",
330 "", "", "port", "cmp", "", "", "epc", "prid",
333 /* Names of IDT R3051 registers. */
335 char *mips_r3051_reg_names[] = {
336 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
337 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
338 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
339 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
340 "sr", "lo", "hi", "bad", "cause","pc",
341 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
342 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
343 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
344 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
345 "fsr", "fir", "fp", "",
346 "inx", "rand", "elo", "", "ctxt", "", "", "",
347 "", "", "ehi", "", "", "", "epc", "prid",
350 /* Names of IDT R3081 registers. */
352 char *mips_r3081_reg_names[] = {
353 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
354 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
355 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
356 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
357 "sr", "lo", "hi", "bad", "cause","pc",
358 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
359 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
360 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
361 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
362 "fsr", "fir", "fp", "",
363 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
364 "", "", "ehi", "", "", "", "epc", "prid",
367 /* Names of LSI 33k registers. */
369 char *mips_lsi33k_reg_names[] = {
370 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
371 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
372 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
373 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
374 "epc", "hi", "lo", "sr", "cause","badvaddr",
375 "dcic", "bpc", "bda", "", "", "", "", "",
376 "", "", "", "", "", "", "", "",
377 "", "", "", "", "", "", "", "",
378 "", "", "", "", "", "", "", "",
380 "", "", "", "", "", "", "", "",
381 "", "", "", "", "", "", "", "",
387 } mips_processor_type_table[] = {
388 { "generic", mips_generic_reg_names },
389 { "r3041", mips_r3041_reg_names },
390 { "r3051", mips_r3051_reg_names },
391 { "r3071", mips_r3081_reg_names },
392 { "r3081", mips_r3081_reg_names },
393 { "lsi33k", mips_lsi33k_reg_names },
401 /* Table to translate MIPS16 register field to actual register number. */
402 static int mips16_to_32_reg[8] =
403 {16, 17, 2, 3, 4, 5, 6, 7};
405 /* Heuristic_proc_start may hunt through the text section for a long
406 time across a 2400 baud serial line. Allows the user to limit this
409 static unsigned int heuristic_fence_post = 0;
411 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
412 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
413 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
414 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
415 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
416 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
417 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
418 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
419 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
420 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
421 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
422 #define _PROC_MAGIC_ 0x0F0F0F0F
423 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
424 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
426 struct linked_proc_info
428 struct mips_extra_func_info info;
429 struct linked_proc_info *next;
431 *linked_proc_desc_table = NULL;
434 mips_print_extra_frame_info (struct frame_info *fi)
438 && fi->extra_info->proc_desc
439 && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS)
440 printf_filtered (" frame pointer is at %s+%s\n",
441 REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg),
442 paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
445 /* Number of bytes of storage in the actual machine representation for
446 register N. NOTE: This indirectly defines the register size
447 transfered by the GDB protocol. */
449 static int mips64_transfers_32bit_regs_p = 0;
452 mips_register_raw_size (int reg_nr)
454 if (mips64_transfers_32bit_regs_p)
455 return REGISTER_VIRTUAL_SIZE (reg_nr);
456 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
457 && FP_REGISTER_DOUBLE)
458 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
465 /* Convert between RAW and VIRTUAL registers. The RAW register size
466 defines the remote-gdb packet. */
469 mips_register_convertible (int reg_nr)
471 if (mips64_transfers_32bit_regs_p)
474 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
478 mips_register_convert_to_virtual (int n, struct type *virtual_type,
479 char *raw_buf, char *virt_buf)
481 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
483 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
484 TYPE_LENGTH (virtual_type));
488 TYPE_LENGTH (virtual_type));
492 mips_register_convert_to_raw (struct type *virtual_type, int n,
493 char *virt_buf, char *raw_buf)
495 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
496 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
497 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
499 TYPE_LENGTH (virtual_type));
503 TYPE_LENGTH (virtual_type));
506 /* Should the upper word of 64-bit addresses be zeroed? */
507 enum cmd_auto_boolean mask_address_var = CMD_AUTO_BOOLEAN_AUTO;
510 mips_mask_address_p (void)
512 switch (mask_address_var)
514 case CMD_AUTO_BOOLEAN_TRUE:
516 case CMD_AUTO_BOOLEAN_FALSE:
519 case CMD_AUTO_BOOLEAN_AUTO:
520 return MIPS_DEFAULT_MASK_ADDRESS_P;
522 internal_error (__FILE__, __LINE__,
523 "mips_mask_address_p: bad switch");
529 show_mask_address (char *cmd, int from_tty)
531 switch (mask_address_var)
533 case CMD_AUTO_BOOLEAN_TRUE:
534 printf_filtered ("The 32 bit mips address mask is enabled\n");
536 case CMD_AUTO_BOOLEAN_FALSE:
537 printf_filtered ("The 32 bit mips address mask is disabled\n");
539 case CMD_AUTO_BOOLEAN_AUTO:
540 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
541 mips_mask_address_p () ? "enabled" : "disabled");
544 internal_error (__FILE__, __LINE__,
545 "show_mask_address: bad switch");
550 /* Should call_function allocate stack space for a struct return? */
552 mips_use_struct_convention (int gcc_p, struct type *type)
555 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
557 return 1; /* Structures are returned by ref in extra arg0 */
560 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
563 pc_is_mips16 (bfd_vma memaddr)
565 struct minimal_symbol *sym;
567 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
568 if (IS_MIPS16_ADDR (memaddr))
571 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
572 the high bit of the info field. Use this to decide if the function is
573 MIPS16 or normal MIPS. */
574 sym = lookup_minimal_symbol_by_pc (memaddr);
576 return MSYMBOL_IS_SPECIAL (sym);
581 /* MIPS believes that the PC has a sign extended value. Perhaphs the
582 all registers should be sign extended for simplicity? */
585 mips_read_pc (ptid_t ptid)
587 return read_signed_register_pid (PC_REGNUM, ptid);
590 /* This returns the PC of the first inst after the prologue. If we can't
591 find the prologue, then return 0. */
594 after_prologue (CORE_ADDR pc,
595 mips_extra_func_info_t proc_desc)
597 struct symtab_and_line sal;
598 CORE_ADDR func_addr, func_end;
600 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
601 to read the stack pointer from the current machine state, because
602 the current machine state has nothing to do with the information
603 we need from the proc_desc; and the process may or may not exist
606 proc_desc = find_proc_desc (pc, NULL, 0);
610 /* If function is frameless, then we need to do it the hard way. I
611 strongly suspect that frameless always means prologueless... */
612 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
613 && PROC_FRAME_OFFSET (proc_desc) == 0)
617 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
618 return 0; /* Unknown */
620 sal = find_pc_line (func_addr, 0);
622 if (sal.end < func_end)
625 /* The line after the prologue is after the end of the function. In this
626 case, tell the caller to find the prologue the hard way. */
631 /* Decode a MIPS32 instruction that saves a register in the stack, and
632 set the appropriate bit in the general register mask or float register mask
633 to indicate which register is saved. This is a helper function
634 for mips_find_saved_regs. */
637 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
638 unsigned long *float_mask)
642 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
643 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
644 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
646 /* It might be possible to use the instruction to
647 find the offset, rather than the code below which
648 is based on things being in a certain order in the
649 frame, but figuring out what the instruction's offset
650 is relative to might be a little tricky. */
651 reg = (inst & 0x001f0000) >> 16;
652 *gen_mask |= (1 << reg);
654 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
655 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
656 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
659 reg = ((inst & 0x001f0000) >> 16);
660 *float_mask |= (1 << reg);
664 /* Decode a MIPS16 instruction that saves a register in the stack, and
665 set the appropriate bit in the general register or float register mask
666 to indicate which register is saved. This is a helper function
667 for mips_find_saved_regs. */
670 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
672 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
674 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
675 *gen_mask |= (1 << reg);
677 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
679 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
680 *gen_mask |= (1 << reg);
682 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
683 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
684 *gen_mask |= (1 << RA_REGNUM);
688 /* Fetch and return instruction from the specified location. If the PC
689 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
692 mips_fetch_instruction (CORE_ADDR addr)
694 char buf[MIPS_INSTLEN];
698 if (pc_is_mips16 (addr))
700 instlen = MIPS16_INSTLEN;
701 addr = UNMAKE_MIPS16_ADDR (addr);
704 instlen = MIPS_INSTLEN;
705 status = read_memory_nobpt (addr, buf, instlen);
707 memory_error (status, addr);
708 return extract_unsigned_integer (buf, instlen);
712 /* These the fields of 32 bit mips instructions */
713 #define mips32_op(x) (x >> 26)
714 #define itype_op(x) (x >> 26)
715 #define itype_rs(x) ((x >> 21) & 0x1f)
716 #define itype_rt(x) ((x >> 16) & 0x1f)
717 #define itype_immediate(x) (x & 0xffff)
719 #define jtype_op(x) (x >> 26)
720 #define jtype_target(x) (x & 0x03ffffff)
722 #define rtype_op(x) (x >> 26)
723 #define rtype_rs(x) ((x >> 21) & 0x1f)
724 #define rtype_rt(x) ((x >> 16) & 0x1f)
725 #define rtype_rd(x) ((x >> 11) & 0x1f)
726 #define rtype_shamt(x) ((x >> 6) & 0x1f)
727 #define rtype_funct(x) (x & 0x3f)
730 mips32_relative_offset (unsigned long inst)
733 x = itype_immediate (inst);
734 if (x & 0x8000) /* sign bit set */
736 x |= 0xffff0000; /* sign extension */
742 /* Determine whate to set a single step breakpoint while considering
745 mips32_next_pc (CORE_ADDR pc)
749 inst = mips_fetch_instruction (pc);
750 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
752 if (itype_op (inst) >> 2 == 5)
753 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
755 op = (itype_op (inst) & 0x03);
770 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
771 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
773 int tf = itype_rt (inst) & 0x01;
774 int cnum = itype_rt (inst) >> 2;
775 int fcrcs = read_signed_register (FCRCS_REGNUM);
776 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
778 if (((cond >> cnum) & 0x01) == tf)
779 pc += mips32_relative_offset (inst) + 4;
784 pc += 4; /* Not a branch, next instruction is easy */
787 { /* This gets way messy */
789 /* Further subdivide into SPECIAL, REGIMM and other */
790 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
792 case 0: /* SPECIAL */
793 op = rtype_funct (inst);
798 /* Set PC to that address */
799 pc = read_signed_register (rtype_rs (inst));
805 break; /* end SPECIAL */
808 op = itype_rt (inst); /* branch condition */
813 case 16: /* BLTZAL */
814 case 18: /* BLTZALL */
816 if (read_signed_register (itype_rs (inst)) < 0)
817 pc += mips32_relative_offset (inst) + 4;
819 pc += 8; /* after the delay slot */
823 case 17: /* BGEZAL */
824 case 19: /* BGEZALL */
825 greater_equal_branch:
826 if (read_signed_register (itype_rs (inst)) >= 0)
827 pc += mips32_relative_offset (inst) + 4;
829 pc += 8; /* after the delay slot */
831 /* All of the other instructions in the REGIMM category */
836 break; /* end REGIMM */
841 reg = jtype_target (inst) << 2;
842 /* Upper four bits get never changed... */
843 pc = reg + ((pc + 4) & 0xf0000000);
846 /* FIXME case JALX : */
849 reg = jtype_target (inst) << 2;
850 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
851 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
853 break; /* The new PC will be alternate mode */
854 case 4: /* BEQ, BEQL */
856 if (read_signed_register (itype_rs (inst)) ==
857 read_signed_register (itype_rt (inst)))
858 pc += mips32_relative_offset (inst) + 4;
862 case 5: /* BNE, BNEL */
864 if (read_signed_register (itype_rs (inst)) !=
865 read_signed_register (itype_rt (inst)))
866 pc += mips32_relative_offset (inst) + 4;
870 case 6: /* BLEZ, BLEZL */
872 if (read_signed_register (itype_rs (inst) <= 0))
873 pc += mips32_relative_offset (inst) + 4;
879 greater_branch: /* BGTZ, BGTZL */
880 if (read_signed_register (itype_rs (inst) > 0))
881 pc += mips32_relative_offset (inst) + 4;
888 } /* mips32_next_pc */
890 /* Decoding the next place to set a breakpoint is irregular for the
891 mips 16 variant, but fortunately, there fewer instructions. We have to cope
892 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
893 We dont want to set a single step instruction on the extend instruction
897 /* Lots of mips16 instruction formats */
898 /* Predicting jumps requires itype,ritype,i8type
899 and their extensions extItype,extritype,extI8type
901 enum mips16_inst_fmts
903 itype, /* 0 immediate 5,10 */
904 ritype, /* 1 5,3,8 */
905 rrtype, /* 2 5,3,3,5 */
906 rritype, /* 3 5,3,3,5 */
907 rrrtype, /* 4 5,3,3,3,2 */
908 rriatype, /* 5 5,3,3,1,4 */
909 shifttype, /* 6 5,3,3,3,2 */
910 i8type, /* 7 5,3,8 */
911 i8movtype, /* 8 5,3,3,5 */
912 i8mov32rtype, /* 9 5,3,5,3 */
913 i64type, /* 10 5,3,8 */
914 ri64type, /* 11 5,3,3,5 */
915 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
916 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
917 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
918 extRRItype, /* 15 5,5,5,5,3,3,5 */
919 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
920 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
921 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
922 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
923 extRi64type, /* 20 5,6,5,5,3,3,5 */
924 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
926 /* I am heaping all the fields of the formats into one structure and
927 then, only the fields which are involved in instruction extension */
931 unsigned int regx; /* Function in i8 type */
936 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
937 for the bits which make up the immediatate extension. */
940 extended_offset (unsigned int extension)
943 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
945 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
947 value |= extension & 0x01f; /* extract 4:0 */
951 /* Only call this function if you know that this is an extendable
952 instruction, It wont malfunction, but why make excess remote memory references?
953 If the immediate operands get sign extended or somthing, do it after
954 the extension is performed.
956 /* FIXME: Every one of these cases needs to worry about sign extension
957 when the offset is to be used in relative addressing */
961 fetch_mips_16 (CORE_ADDR pc)
964 pc &= 0xfffffffe; /* clear the low order bit */
965 target_read_memory (pc, buf, 2);
966 return extract_unsigned_integer (buf, 2);
970 unpack_mips16 (CORE_ADDR pc,
971 unsigned int extension,
973 enum mips16_inst_fmts insn_format,
974 struct upk_mips16 *upk)
986 value = extended_offset (extension);
987 value = value << 11; /* rom for the original value */
988 value |= inst & 0x7ff; /* eleven bits from instruction */
992 value = inst & 0x7ff;
993 /* FIXME : Consider sign extension */
1002 { /* A register identifier and an offset */
1003 /* Most of the fields are the same as I type but the
1004 immediate value is of a different length */
1008 value = extended_offset (extension);
1009 value = value << 8; /* from the original instruction */
1010 value |= inst & 0xff; /* eleven bits from instruction */
1011 regx = (extension >> 8) & 0x07; /* or i8 funct */
1012 if (value & 0x4000) /* test the sign bit , bit 26 */
1014 value &= ~0x3fff; /* remove the sign bit */
1020 value = inst & 0xff; /* 8 bits */
1021 regx = (inst >> 8) & 0x07; /* or i8 funct */
1022 /* FIXME: Do sign extension , this format needs it */
1023 if (value & 0x80) /* THIS CONFUSES ME */
1025 value &= 0xef; /* remove the sign bit */
1035 unsigned long value;
1036 unsigned int nexthalf;
1037 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1038 value = value << 16;
1039 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1047 internal_error (__FILE__, __LINE__,
1050 upk->offset = offset;
1057 add_offset_16 (CORE_ADDR pc, int offset)
1059 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1064 extended_mips16_next_pc (CORE_ADDR pc,
1065 unsigned int extension,
1068 int op = (insn >> 11);
1071 case 2: /* Branch */
1074 struct upk_mips16 upk;
1075 unpack_mips16 (pc, extension, insn, itype, &upk);
1076 offset = upk.offset;
1082 pc += (offset << 1) + 2;
1085 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1087 struct upk_mips16 upk;
1088 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1089 pc = add_offset_16 (pc, upk.offset);
1090 if ((insn >> 10) & 0x01) /* Exchange mode */
1091 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1098 struct upk_mips16 upk;
1100 unpack_mips16 (pc, extension, insn, ritype, &upk);
1101 reg = read_signed_register (upk.regx);
1103 pc += (upk.offset << 1) + 2;
1110 struct upk_mips16 upk;
1112 unpack_mips16 (pc, extension, insn, ritype, &upk);
1113 reg = read_signed_register (upk.regx);
1115 pc += (upk.offset << 1) + 2;
1120 case 12: /* I8 Formats btez btnez */
1122 struct upk_mips16 upk;
1124 unpack_mips16 (pc, extension, insn, i8type, &upk);
1125 /* upk.regx contains the opcode */
1126 reg = read_signed_register (24); /* Test register is 24 */
1127 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1128 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1129 /* pc = add_offset_16(pc,upk.offset) ; */
1130 pc += (upk.offset << 1) + 2;
1135 case 29: /* RR Formats JR, JALR, JALR-RA */
1137 struct upk_mips16 upk;
1138 /* upk.fmt = rrtype; */
1143 upk.regx = (insn >> 8) & 0x07;
1144 upk.regy = (insn >> 5) & 0x07;
1152 break; /* Function return instruction */
1158 break; /* BOGUS Guess */
1160 pc = read_signed_register (reg);
1167 /* This is an instruction extension. Fetch the real instruction
1168 (which follows the extension) and decode things based on
1172 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1185 mips16_next_pc (CORE_ADDR pc)
1187 unsigned int insn = fetch_mips_16 (pc);
1188 return extended_mips16_next_pc (pc, 0, insn);
1191 /* The mips_next_pc function supports single_step when the remote
1192 target monitor or stub is not developed enough to do a single_step.
1193 It works by decoding the current instruction and predicting where a
1194 branch will go. This isnt hard because all the data is available.
1195 The MIPS32 and MIPS16 variants are quite different */
1197 mips_next_pc (CORE_ADDR pc)
1200 return mips16_next_pc (pc);
1202 return mips32_next_pc (pc);
1205 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1209 mips_find_saved_regs (struct frame_info *fci)
1212 CORE_ADDR reg_position;
1213 /* r0 bit means kernel trap */
1215 /* What registers have been saved? Bitmasks. */
1216 unsigned long gen_mask, float_mask;
1217 mips_extra_func_info_t proc_desc;
1220 frame_saved_regs_zalloc (fci);
1222 /* If it is the frame for sigtramp, the saved registers are located
1223 in a sigcontext structure somewhere on the stack.
1224 If the stack layout for sigtramp changes we might have to change these
1225 constants and the companion fixup_sigtramp in mdebugread.c */
1226 #ifndef SIGFRAME_BASE
1227 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1228 above the sigtramp frame. */
1229 #define SIGFRAME_BASE MIPS_REGSIZE
1230 /* FIXME! Are these correct?? */
1231 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1232 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1233 #define SIGFRAME_FPREGSAVE_OFF \
1234 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1236 #ifndef SIGFRAME_REG_SIZE
1237 /* FIXME! Is this correct?? */
1238 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1240 if (fci->signal_handler_caller)
1242 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1244 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
1245 + ireg * SIGFRAME_REG_SIZE;
1246 fci->saved_regs[ireg] = reg_position;
1248 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1250 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
1251 + ireg * SIGFRAME_REG_SIZE;
1252 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1254 fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
1258 proc_desc = fci->extra_info->proc_desc;
1259 if (proc_desc == NULL)
1260 /* I'm not sure how/whether this can happen. Normally when we can't
1261 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1262 and set the saved_regs right away. */
1265 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1266 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1267 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1269 if ( /* In any frame other than the innermost or a frame interrupted by
1270 a signal, we assume that all registers have been saved.
1271 This assumes that all register saves in a function happen before
1272 the first function call. */
1273 (fci->next == NULL || fci->next->signal_handler_caller)
1275 /* In a dummy frame we know exactly where things are saved. */
1276 && !PROC_DESC_IS_DUMMY (proc_desc)
1278 /* Don't bother unless we are inside a function prologue. Outside the
1279 prologue, we know where everything is. */
1281 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
1283 /* Not sure exactly what kernel_trap means, but if it means
1284 the kernel saves the registers without a prologue doing it,
1285 we better not examine the prologue to see whether registers
1286 have been saved yet. */
1289 /* We need to figure out whether the registers that the proc_desc
1290 claims are saved have been saved yet. */
1294 /* Bitmasks; set if we have found a save for the register. */
1295 unsigned long gen_save_found = 0;
1296 unsigned long float_save_found = 0;
1299 /* If the address is odd, assume this is MIPS16 code. */
1300 addr = PROC_LOW_ADDR (proc_desc);
1301 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1303 /* Scan through this function's instructions preceding the current
1304 PC, and look for those that save registers. */
1305 while (addr < fci->pc)
1307 inst = mips_fetch_instruction (addr);
1308 if (pc_is_mips16 (addr))
1309 mips16_decode_reg_save (inst, &gen_save_found);
1311 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1314 gen_mask = gen_save_found;
1315 float_mask = float_save_found;
1318 /* Fill in the offsets for the registers which gen_mask says
1320 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1321 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1322 if (gen_mask & 0x80000000)
1324 fci->saved_regs[ireg] = reg_position;
1325 reg_position -= MIPS_SAVED_REGSIZE;
1328 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1329 of that normally used by gcc. Therefore, we have to fetch the first
1330 instruction of the function, and if it's an entry instruction that
1331 saves $s0 or $s1, correct their saved addresses. */
1332 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1334 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1335 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1338 int sreg_count = (inst >> 6) & 3;
1340 /* Check if the ra register was pushed on the stack. */
1341 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1343 reg_position -= MIPS_SAVED_REGSIZE;
1345 /* Check if the s0 and s1 registers were pushed on the stack. */
1346 for (reg = 16; reg < sreg_count + 16; reg++)
1348 fci->saved_regs[reg] = reg_position;
1349 reg_position -= MIPS_SAVED_REGSIZE;
1354 /* Fill in the offsets for the registers which float_mask says
1356 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
1358 /* The freg_offset points to where the first *double* register
1359 is saved. So skip to the high-order word. */
1360 if (!GDB_TARGET_IS_MIPS64)
1361 reg_position += MIPS_SAVED_REGSIZE;
1363 /* Fill in the offsets for the float registers which float_mask says
1365 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1366 if (float_mask & 0x80000000)
1368 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1369 reg_position -= MIPS_SAVED_REGSIZE;
1372 fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM];
1376 read_next_frame_reg (struct frame_info *fi, int regno)
1378 for (; fi; fi = fi->next)
1380 /* We have to get the saved sp from the sigcontext
1381 if it is a signal handler frame. */
1382 if (regno == SP_REGNUM && !fi->signal_handler_caller)
1386 if (fi->saved_regs == NULL)
1387 mips_find_saved_regs (fi);
1388 if (fi->saved_regs[regno])
1389 return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE);
1392 return read_signed_register (regno);
1395 /* mips_addr_bits_remove - remove useless address bits */
1398 mips_addr_bits_remove (CORE_ADDR addr)
1400 if (GDB_TARGET_IS_MIPS64)
1402 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1404 /* This hack is a work-around for existing boards using
1405 PMON, the simulator, and any other 64-bit targets that
1406 doesn't have true 64-bit addressing. On these targets,
1407 the upper 32 bits of addresses are ignored by the
1408 hardware. Thus, the PC or SP are likely to have been
1409 sign extended to all 1s by instruction sequences that
1410 load 32-bit addresses. For example, a typical piece of
1411 code that loads an address is this:
1412 lui $r2, <upper 16 bits>
1413 ori $r2, <lower 16 bits>
1414 But the lui sign-extends the value such that the upper 32
1415 bits may be all 1s. The workaround is simply to mask off
1416 these bits. In the future, gcc may be changed to support
1417 true 64-bit addressing, and this masking will have to be
1419 addr &= (CORE_ADDR) 0xffffffff;
1422 else if (mips_mask_address_p ())
1424 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1425 masking off bits, instead, the actual target should be asking
1426 for the address to be converted to a valid pointer. */
1427 /* Even when GDB is configured for some 32-bit targets
1428 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1429 so CORE_ADDR is 64 bits. So we still have to mask off
1430 useless bits from addresses. */
1431 addr &= (CORE_ADDR) 0xffffffff;
1436 /* mips_software_single_step() is called just before we want to resume
1437 the inferior, if we want to single-step it but there is no hardware
1438 or kernel single-step support (MIPS on GNU/Linux for example). We find
1439 the target of the coming instruction and breakpoint it.
1441 single_step is also called just after the inferior stops. If we had
1442 set up a simulated single-step, we undo our damage. */
1445 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1447 static CORE_ADDR next_pc;
1448 typedef char binsn_quantum[BREAKPOINT_MAX];
1449 static binsn_quantum break_mem;
1452 if (insert_breakpoints_p)
1454 pc = read_register (PC_REGNUM);
1455 next_pc = mips_next_pc (pc);
1457 target_insert_breakpoint (next_pc, break_mem);
1460 target_remove_breakpoint (next_pc, break_mem);
1464 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1468 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
1469 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
1470 tmp = mips_skip_stub (pc);
1471 prev->pc = tmp ? tmp : pc;
1476 mips_frame_saved_pc (struct frame_info *frame)
1479 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
1480 /* We have to get the saved pc from the sigcontext
1481 if it is a signal handler frame. */
1482 int pcreg = frame->signal_handler_caller ? PC_REGNUM
1483 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1485 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1486 saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1488 saved_pc = read_next_frame_reg (frame, pcreg);
1490 return ADDR_BITS_REMOVE (saved_pc);
1493 static struct mips_extra_func_info temp_proc_desc;
1494 static CORE_ADDR temp_saved_regs[NUM_REGS];
1496 /* Set a register's saved stack address in temp_saved_regs. If an address
1497 has already been set for this register, do nothing; this way we will
1498 only recognize the first save of a given register in a function prologue.
1499 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1502 set_reg_offset (int regno, CORE_ADDR offset)
1504 if (temp_saved_regs[regno] == 0)
1505 temp_saved_regs[regno] = offset;
1509 /* Test whether the PC points to the return instruction at the
1510 end of a function. */
1513 mips_about_to_return (CORE_ADDR pc)
1515 if (pc_is_mips16 (pc))
1516 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1517 generates a "jr $ra"; other times it generates code to load
1518 the return address from the stack to an accessible register (such
1519 as $a3), then a "jr" using that register. This second case
1520 is almost impossible to distinguish from an indirect jump
1521 used for switch statements, so we don't even try. */
1522 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1524 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1528 /* This fencepost looks highly suspicious to me. Removing it also
1529 seems suspicious as it could affect remote debugging across serial
1533 heuristic_proc_start (CORE_ADDR pc)
1540 pc = ADDR_BITS_REMOVE (pc);
1542 fence = start_pc - heuristic_fence_post;
1546 if (heuristic_fence_post == UINT_MAX
1547 || fence < VM_MIN_ADDRESS)
1548 fence = VM_MIN_ADDRESS;
1550 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1552 /* search back for previous return */
1553 for (start_pc -= instlen;; start_pc -= instlen)
1554 if (start_pc < fence)
1556 /* It's not clear to me why we reach this point when
1557 stop_soon_quietly, but with this test, at least we
1558 don't print out warnings for every child forked (eg, on
1559 decstation). 22apr93 rich@cygnus.com. */
1560 if (!stop_soon_quietly)
1562 static int blurb_printed = 0;
1564 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1569 /* This actually happens frequently in embedded
1570 development, when you first connect to a board
1571 and your stack pointer and pc are nowhere in
1572 particular. This message needs to give people
1573 in that situation enough information to
1574 determine that it's no big deal. */
1575 printf_filtered ("\n\
1576 GDB is unable to find the start of the function at 0x%s\n\
1577 and thus can't determine the size of that function's stack frame.\n\
1578 This means that GDB may be unable to access that stack frame, or\n\
1579 the frames below it.\n\
1580 This problem is most likely caused by an invalid program counter or\n\
1582 However, if you think GDB should simply search farther back\n\
1583 from 0x%s for code which looks like the beginning of a\n\
1584 function, you can increase the range of the search using the `set\n\
1585 heuristic-fence-post' command.\n",
1586 paddr_nz (pc), paddr_nz (pc));
1593 else if (pc_is_mips16 (start_pc))
1595 unsigned short inst;
1597 /* On MIPS16, any one of the following is likely to be the
1598 start of a function:
1602 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1603 inst = mips_fetch_instruction (start_pc);
1604 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1605 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1606 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1607 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1609 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1610 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1615 else if (mips_about_to_return (start_pc))
1617 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1624 /* Fetch the immediate value from a MIPS16 instruction.
1625 If the previous instruction was an EXTEND, use it to extend
1626 the upper bits of the immediate value. This is a helper function
1627 for mips16_heuristic_proc_desc. */
1630 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1631 unsigned short inst, /* current instruction */
1632 int nbits, /* number of bits in imm field */
1633 int scale, /* scale factor to be applied to imm */
1634 int is_signed) /* is the imm field signed? */
1638 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1640 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1641 if (offset & 0x8000) /* check for negative extend */
1642 offset = 0 - (0x10000 - (offset & 0xffff));
1643 return offset | (inst & 0x1f);
1647 int max_imm = 1 << nbits;
1648 int mask = max_imm - 1;
1649 int sign_bit = max_imm >> 1;
1651 offset = inst & mask;
1652 if (is_signed && (offset & sign_bit))
1653 offset = 0 - (max_imm - offset);
1654 return offset * scale;
1659 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1660 stream from start_pc to limit_pc. */
1663 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1664 struct frame_info *next_frame, CORE_ADDR sp)
1667 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1668 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1669 unsigned inst = 0; /* current instruction */
1670 unsigned entry_inst = 0; /* the entry instruction */
1673 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1674 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1676 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1678 /* Save the previous instruction. If it's an EXTEND, we'll extract
1679 the immediate offset extension from it in mips16_get_imm. */
1682 /* Fetch and decode the instruction. */
1683 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1684 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1685 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1687 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1688 if (offset < 0) /* negative stack adjustment? */
1689 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
1691 /* Exit loop if a positive stack adjustment is found, which
1692 usually means that the stack cleanup code in the function
1693 epilogue is reached. */
1696 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1698 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1699 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1700 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1701 set_reg_offset (reg, sp + offset);
1703 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1705 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1706 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1707 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1708 set_reg_offset (reg, sp + offset);
1710 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1712 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1713 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1714 set_reg_offset (RA_REGNUM, sp + offset);
1716 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1718 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1719 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1720 set_reg_offset (RA_REGNUM, sp + offset);
1722 else if (inst == 0x673d) /* move $s1, $sp */
1725 PROC_FRAME_REG (&temp_proc_desc) = 17;
1727 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1729 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1730 frame_addr = sp + offset;
1731 PROC_FRAME_REG (&temp_proc_desc) = 17;
1732 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1734 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1736 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1737 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1738 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1739 set_reg_offset (reg, frame_addr + offset);
1741 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1743 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1744 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1745 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1746 set_reg_offset (reg, frame_addr + offset);
1748 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1749 entry_inst = inst; /* save for later processing */
1750 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1751 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
1754 /* The entry instruction is typically the first instruction in a function,
1755 and it stores registers at offsets relative to the value of the old SP
1756 (before the prologue). But the value of the sp parameter to this
1757 function is the new SP (after the prologue has been executed). So we
1758 can't calculate those offsets until we've seen the entire prologue,
1759 and can calculate what the old SP must have been. */
1760 if (entry_inst != 0)
1762 int areg_count = (entry_inst >> 8) & 7;
1763 int sreg_count = (entry_inst >> 6) & 3;
1765 /* The entry instruction always subtracts 32 from the SP. */
1766 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
1768 /* Now we can calculate what the SP must have been at the
1769 start of the function prologue. */
1770 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
1772 /* Check if a0-a3 were saved in the caller's argument save area. */
1773 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1775 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1776 set_reg_offset (reg, sp + offset);
1777 offset += MIPS_SAVED_REGSIZE;
1780 /* Check if the ra register was pushed on the stack. */
1782 if (entry_inst & 0x20)
1784 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
1785 set_reg_offset (RA_REGNUM, sp + offset);
1786 offset -= MIPS_SAVED_REGSIZE;
1789 /* Check if the s0 and s1 registers were pushed on the stack. */
1790 for (reg = 16; reg < sreg_count + 16; reg++)
1792 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1793 set_reg_offset (reg, sp + offset);
1794 offset -= MIPS_SAVED_REGSIZE;
1800 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1801 struct frame_info *next_frame, CORE_ADDR sp)
1804 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1806 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
1807 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
1808 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1809 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
1811 unsigned long inst, high_word, low_word;
1814 /* Fetch the instruction. */
1815 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1817 /* Save some code by pre-extracting some useful fields. */
1818 high_word = (inst >> 16) & 0xffff;
1819 low_word = inst & 0xffff;
1820 reg = high_word & 0x1f;
1822 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1823 || high_word == 0x23bd /* addi $sp,$sp,-i */
1824 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1826 if (low_word & 0x8000) /* negative stack adjustment? */
1827 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
1829 /* Exit loop if a positive stack adjustment is found, which
1830 usually means that the stack cleanup code in the function
1831 epilogue is reached. */
1834 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1836 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1837 set_reg_offset (reg, sp + low_word);
1839 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1841 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1842 but the register size used is only 32 bits. Make the address
1843 for the saved register point to the lower 32 bits. */
1844 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1845 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
1847 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1849 /* Old gcc frame, r30 is virtual frame pointer. */
1850 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
1851 frame_addr = sp + low_word;
1852 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1854 unsigned alloca_adjust;
1855 PROC_FRAME_REG (&temp_proc_desc) = 30;
1856 frame_addr = read_next_frame_reg (next_frame, 30);
1857 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1858 if (alloca_adjust > 0)
1860 /* FP > SP + frame_size. This may be because
1861 * of an alloca or somethings similar.
1862 * Fix sp to "pre-alloca" value, and try again.
1864 sp += alloca_adjust;
1869 /* move $30,$sp. With different versions of gas this will be either
1870 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1871 Accept any one of these. */
1872 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1874 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1875 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1877 unsigned alloca_adjust;
1878 PROC_FRAME_REG (&temp_proc_desc) = 30;
1879 frame_addr = read_next_frame_reg (next_frame, 30);
1880 alloca_adjust = (unsigned) (frame_addr - sp);
1881 if (alloca_adjust > 0)
1883 /* FP > SP + frame_size. This may be because
1884 * of an alloca or somethings similar.
1885 * Fix sp to "pre-alloca" value, and try again.
1887 sp += alloca_adjust;
1892 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1894 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1895 set_reg_offset (reg, frame_addr + low_word);
1900 static mips_extra_func_info_t
1901 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1902 struct frame_info *next_frame, int cur_frame)
1907 sp = read_next_frame_reg (next_frame, SP_REGNUM);
1913 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
1914 memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
1915 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
1916 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
1917 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
1919 if (start_pc + 200 < limit_pc)
1920 limit_pc = start_pc + 200;
1921 if (pc_is_mips16 (start_pc))
1922 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
1924 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
1925 return &temp_proc_desc;
1928 static mips_extra_func_info_t
1929 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
1931 CORE_ADDR startaddr;
1932 mips_extra_func_info_t proc_desc;
1933 struct block *b = block_for_pc (pc);
1936 find_pc_partial_function (pc, NULL, &startaddr, NULL);
1938 *addrptr = startaddr;
1939 if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0))
1943 if (startaddr > BLOCK_START (b))
1944 /* This is the "pathological" case referred to in a comment in
1945 print_frame_info. It might be better to move this check into
1949 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
1952 /* If we never found a PDR for this function in symbol reading, then
1953 examine prologues to find the information. */
1956 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
1957 if (PROC_FRAME_REG (proc_desc) == -1)
1967 static mips_extra_func_info_t
1968 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
1970 mips_extra_func_info_t proc_desc;
1971 CORE_ADDR startaddr;
1973 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
1977 /* IF this is the topmost frame AND
1978 * (this proc does not have debugging information OR
1979 * the PC is in the procedure prologue)
1980 * THEN create a "heuristic" proc_desc (by analyzing
1981 * the actual code) to replace the "official" proc_desc.
1983 if (next_frame == NULL)
1985 struct symtab_and_line val;
1986 struct symbol *proc_symbol =
1987 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
1991 val = find_pc_line (BLOCK_START
1992 (SYMBOL_BLOCK_VALUE (proc_symbol)),
1994 val.pc = val.end ? val.end : pc;
1996 if (!proc_symbol || pc < val.pc)
1998 mips_extra_func_info_t found_heuristic =
1999 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2000 pc, next_frame, cur_frame);
2001 if (found_heuristic)
2002 proc_desc = found_heuristic;
2008 /* Is linked_proc_desc_table really necessary? It only seems to be used
2009 by procedure call dummys. However, the procedures being called ought
2010 to have their own proc_descs, and even if they don't,
2011 heuristic_proc_desc knows how to create them! */
2013 register struct linked_proc_info *link;
2015 for (link = linked_proc_desc_table; link; link = link->next)
2016 if (PROC_LOW_ADDR (&link->info) <= pc
2017 && PROC_HIGH_ADDR (&link->info) > pc)
2021 startaddr = heuristic_proc_start (pc);
2024 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2030 get_frame_pointer (struct frame_info *frame,
2031 mips_extra_func_info_t proc_desc)
2033 return ADDR_BITS_REMOVE (
2034 read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) +
2035 PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
2038 mips_extra_func_info_t cached_proc_desc;
2041 mips_frame_chain (struct frame_info *frame)
2043 mips_extra_func_info_t proc_desc;
2045 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
2047 if (saved_pc == 0 || inside_entry_file (saved_pc))
2050 /* Check if the PC is inside a call stub. If it is, fetch the
2051 PC of the caller of that stub. */
2052 if ((tmp = mips_skip_stub (saved_pc)) != 0)
2055 /* Look up the procedure descriptor for this PC. */
2056 proc_desc = find_proc_desc (saved_pc, frame, 1);
2060 cached_proc_desc = proc_desc;
2062 /* If no frame pointer and frame size is zero, we must be at end
2063 of stack (or otherwise hosed). If we don't check frame size,
2064 we loop forever if we see a zero size frame. */
2065 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2066 && PROC_FRAME_OFFSET (proc_desc) == 0
2067 /* The previous frame from a sigtramp frame might be frameless
2068 and have frame size zero. */
2069 && !frame->signal_handler_caller)
2072 return get_frame_pointer (frame, proc_desc);
2076 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2080 /* Use proc_desc calculated in frame_chain */
2081 mips_extra_func_info_t proc_desc =
2082 fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1);
2084 fci->extra_info = (struct frame_extra_info *)
2085 frame_obstack_alloc (sizeof (struct frame_extra_info));
2087 fci->saved_regs = NULL;
2088 fci->extra_info->proc_desc =
2089 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2092 /* Fixup frame-pointer - only needed for top frame */
2093 /* This may not be quite right, if proc has a real frame register.
2094 Get the value of the frame relative sp, procedure might have been
2095 interrupted by a signal at it's very start. */
2096 if (fci->pc == PROC_LOW_ADDR (proc_desc)
2097 && !PROC_DESC_IS_DUMMY (proc_desc))
2098 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
2100 fci->frame = get_frame_pointer (fci->next, proc_desc);
2102 if (proc_desc == &temp_proc_desc)
2106 /* Do not set the saved registers for a sigtramp frame,
2107 mips_find_saved_registers will do that for us.
2108 We can't use fci->signal_handler_caller, it is not yet set. */
2109 find_pc_partial_function (fci->pc, &name,
2110 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2111 if (!IN_SIGTRAMP (fci->pc, name))
2113 frame_saved_regs_zalloc (fci);
2114 memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2115 fci->saved_regs[PC_REGNUM]
2116 = fci->saved_regs[RA_REGNUM];
2120 /* hack: if argument regs are saved, guess these contain args */
2121 /* assume we can't tell how many args for now */
2122 fci->extra_info->num_args = -1;
2123 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2125 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2127 fci->extra_info->num_args = regnum - A0_REGNUM + 1;
2134 /* MIPS stack frames are almost impenetrable. When execution stops,
2135 we basically have to look at symbol information for the function
2136 that we stopped in, which tells us *which* register (if any) is
2137 the base of the frame pointer, and what offset from that register
2138 the frame itself is at.
2140 This presents a problem when trying to examine a stack in memory
2141 (that isn't executing at the moment), using the "frame" command. We
2142 don't have a PC, nor do we have any registers except SP.
2144 This routine takes two arguments, SP and PC, and tries to make the
2145 cached frames look as if these two arguments defined a frame on the
2146 cache. This allows the rest of info frame to extract the important
2147 arguments without difficulty. */
2150 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2153 error ("MIPS frame specifications require two arguments: sp and pc");
2155 return create_new_frame (argv[0], argv[1]);
2158 /* According to the current ABI, should the type be passed in a
2159 floating-point register (assuming that there is space)? When there
2160 is no FPU, FP are not even considered as possibile candidates for
2161 FP registers and, consequently this returns false - forces FP
2162 arguments into integer registers. */
2165 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2167 return ((typecode == TYPE_CODE_FLT
2169 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2170 && TYPE_NFIELDS (arg_type) == 1
2171 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2172 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2175 /* On o32, argument passing in GPRs depends on the alignment of the type being
2176 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2179 mips_type_needs_double_align (struct type *type)
2181 enum type_code typecode = TYPE_CODE (type);
2183 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2185 else if (typecode == TYPE_CODE_STRUCT)
2187 if (TYPE_NFIELDS (type) < 1)
2189 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2191 else if (typecode == TYPE_CODE_UNION)
2195 n = TYPE_NFIELDS (type);
2196 for (i = 0; i < n; i++)
2197 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2205 mips_push_arguments (int nargs,
2206 struct value **args,
2209 CORE_ADDR struct_addr)
2215 int stack_offset = 0;
2217 /* Macros to round N up or down to the next A boundary; A must be
2219 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2220 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2222 /* First ensure that the stack and structure return address (if any)
2223 are properly aligned. The stack has to be at least 64-bit aligned
2224 even on 32-bit machines, because doubles must be 64-bit aligned.
2225 On at least one MIPS variant, stack frames need to be 128-bit
2226 aligned, so we round to this widest known alignment. */
2227 sp = ROUND_DOWN (sp, 16);
2228 struct_addr = ROUND_DOWN (struct_addr, 16);
2230 /* Now make space on the stack for the args. We allocate more
2231 than necessary for EABI, because the first few arguments are
2232 passed in registers, but that's OK. */
2233 for (argnum = 0; argnum < nargs; argnum++)
2234 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_STACK_ARGSIZE);
2235 sp -= ROUND_UP (len, 16);
2238 fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n",
2239 (long) sp, ROUND_UP (len, 16));
2241 /* Initialize the integer and float register pointers. */
2243 float_argreg = FPA0_REGNUM;
2245 /* the struct_return pointer occupies the first parameter-passing reg */
2249 fprintf_unfiltered (gdb_stdlog,
2250 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2251 argreg, (long) struct_addr);
2252 write_register (argreg++, struct_addr);
2253 if (MIPS_REGS_HAVE_HOME_P)
2254 stack_offset += MIPS_STACK_ARGSIZE;
2257 /* Now load as many as possible of the first arguments into
2258 registers, and push the rest onto the stack. Loop thru args
2259 from first to last. */
2260 for (argnum = 0; argnum < nargs; argnum++)
2263 char valbuf[MAX_REGISTER_RAW_SIZE];
2264 struct value *arg = args[argnum];
2265 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2266 int len = TYPE_LENGTH (arg_type);
2267 enum type_code typecode = TYPE_CODE (arg_type);
2270 fprintf_unfiltered (gdb_stdlog,
2271 "mips_push_arguments: %d len=%d type=%d",
2272 argnum + 1, len, (int) typecode);
2274 /* The EABI passes structures that do not fit in a register by
2275 reference. In all other cases, pass the structure by value. */
2277 && len > MIPS_SAVED_REGSIZE
2278 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2280 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2281 typecode = TYPE_CODE_PTR;
2282 len = MIPS_SAVED_REGSIZE;
2285 fprintf_unfiltered (gdb_stdlog, " push");
2288 val = (char *) VALUE_CONTENTS (arg);
2290 /* 32-bit ABIs always start floating point arguments in an
2291 even-numbered floating point register. Round the FP register
2292 up before the check to see if there are any FP registers
2293 left. Non MIPS_EABI targets also pass the FP in the integer
2294 registers so also round up normal registers. */
2295 if (!FP_REGISTER_DOUBLE
2296 && fp_register_arg_p (typecode, arg_type))
2298 if ((float_argreg & 1))
2302 /* Floating point arguments passed in registers have to be
2303 treated specially. On 32-bit architectures, doubles
2304 are passed in register pairs; the even register gets
2305 the low word, and the odd register gets the high word.
2306 On non-EABI processors, the first two floating point arguments are
2307 also copied to general registers, because MIPS16 functions
2308 don't use float registers for arguments. This duplication of
2309 arguments in general registers can't hurt non-MIPS16 functions
2310 because those registers are normally skipped. */
2311 /* MIPS_EABI squeezes a struct that contains a single floating
2312 point value into an FP register instead of pushing it onto the
2314 if (fp_register_arg_p (typecode, arg_type)
2315 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2317 if (!FP_REGISTER_DOUBLE && len == 8)
2319 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2320 unsigned long regval;
2322 /* Write the low word of the double to the even register(s). */
2323 regval = extract_unsigned_integer (val + low_offset, 4);
2325 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2326 float_argreg, phex (regval, 4));
2327 write_register (float_argreg++, regval);
2331 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2332 argreg, phex (regval, 4));
2333 write_register (argreg++, regval);
2336 /* Write the high word of the double to the odd register(s). */
2337 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2339 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2340 float_argreg, phex (regval, 4));
2341 write_register (float_argreg++, regval);
2345 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2346 argreg, phex (regval, 4));
2347 write_register (argreg++, regval);
2353 /* This is a floating point value that fits entirely
2354 in a single register. */
2355 /* On 32 bit ABI's the float_argreg is further adjusted
2356 above to ensure that it is even register aligned. */
2357 LONGEST regval = extract_unsigned_integer (val, len);
2359 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2360 float_argreg, phex (regval, len));
2361 write_register (float_argreg++, regval);
2364 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2365 registers for each argument. The below is (my
2366 guess) to ensure that the corresponding integer
2367 register has reserved the same space. */
2369 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2370 argreg, phex (regval, len));
2371 write_register (argreg, regval);
2372 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
2375 /* Reserve space for the FP register. */
2376 if (MIPS_REGS_HAVE_HOME_P)
2377 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
2381 /* Copy the argument to general registers or the stack in
2382 register-sized pieces. Large arguments are split between
2383 registers and stack. */
2384 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2385 are treated specially: Irix cc passes them in registers
2386 where gcc sometimes puts them on the stack. For maximum
2387 compatibility, we will put them in both places. */
2388 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2389 (len % MIPS_SAVED_REGSIZE != 0));
2390 /* Structures should be aligned to eight bytes (even arg registers)
2391 on MIPS_ABI_O32 if their first member has double precision. */
2392 if (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_O32
2393 && mips_type_needs_double_align (arg_type))
2398 /* Note: Floating-point values that didn't fit into an FP
2399 register are only written to memory. */
2402 /* Rememer if the argument was written to the stack. */
2403 int stack_used_p = 0;
2404 int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2407 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2410 /* Write this portion of the argument to the stack. */
2411 if (argreg > MIPS_LAST_ARG_REGNUM
2413 || fp_register_arg_p (typecode, arg_type))
2415 /* Should shorter than int integer values be
2416 promoted to int before being stored? */
2417 int longword_offset = 0;
2420 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2422 if (MIPS_STACK_ARGSIZE == 8 &&
2423 (typecode == TYPE_CODE_INT ||
2424 typecode == TYPE_CODE_PTR ||
2425 typecode == TYPE_CODE_FLT) && len <= 4)
2426 longword_offset = MIPS_STACK_ARGSIZE - len;
2427 else if ((typecode == TYPE_CODE_STRUCT ||
2428 typecode == TYPE_CODE_UNION) &&
2429 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2430 longword_offset = MIPS_STACK_ARGSIZE - len;
2435 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%lx",
2436 (long) stack_offset);
2437 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx",
2438 (long) longword_offset);
2441 addr = sp + stack_offset + longword_offset;
2446 fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr);
2447 for (i = 0; i < partial_len; i++)
2449 fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff);
2452 write_memory (addr, val, partial_len);
2455 /* Note!!! This is NOT an else clause. Odd sized
2456 structs may go thru BOTH paths. Floating point
2457 arguments will not. */
2458 /* Write this portion of the argument to a general
2459 purpose register. */
2460 if (argreg <= MIPS_LAST_ARG_REGNUM
2461 && !fp_register_arg_p (typecode, arg_type))
2463 LONGEST regval = extract_unsigned_integer (val, partial_len);
2465 /* A non-floating-point argument being passed in a
2466 general register. If a struct or union, and if
2467 the remaining length is smaller than the register
2468 size, we have to adjust the register value on
2471 It does not seem to be necessary to do the
2472 same for integral types.
2474 Also don't do this adjustment on EABI and O64
2477 cagney/2001-07-23: gdb/179: Also, GCC, when
2478 outputting LE O32 with sizeof (struct) <
2479 MIPS_SAVED_REGSIZE, generates a left shift as
2480 part of storing the argument in a register a
2481 register (the left shift isn't generated when
2482 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2483 is quite possible that this is GCC contradicting
2484 the LE/O32 ABI, GDB has not been adjusted to
2485 accommodate this. Either someone needs to
2486 demonstrate that the LE/O32 ABI specifies such a
2487 left shift OR this new ABI gets identified as
2488 such and GDB gets tweaked accordingly. */
2491 && MIPS_SAVED_REGSIZE < 8
2492 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2493 && partial_len < MIPS_SAVED_REGSIZE
2494 && (typecode == TYPE_CODE_STRUCT ||
2495 typecode == TYPE_CODE_UNION))
2496 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
2500 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2502 phex (regval, MIPS_SAVED_REGSIZE));
2503 write_register (argreg, regval);
2506 /* If this is the old ABI, prevent subsequent floating
2507 point arguments from being passed in floating point
2510 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
2516 /* Compute the the offset into the stack at which we
2517 will copy the next parameter.
2519 In older ABIs, the caller reserved space for
2520 registers that contained arguments. This was loosely
2521 refered to as their "home". Consequently, space is
2524 In the new EABI (and the NABI32), the stack_offset
2525 only needs to be adjusted when it has been used.. */
2527 if (MIPS_REGS_HAVE_HOME_P || stack_used_p)
2528 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2532 fprintf_unfiltered (gdb_stdlog, "\n");
2535 /* Return adjusted stack pointer. */
2540 mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2542 /* Set the return address register to point to the entry
2543 point of the program, where a breakpoint lies in wait. */
2544 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
2549 mips_push_register (CORE_ADDR * sp, int regno)
2551 char buffer[MAX_REGISTER_RAW_SIZE];
2554 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
2556 regsize = MIPS_SAVED_REGSIZE;
2557 offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2558 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
2563 regsize = REGISTER_RAW_SIZE (regno);
2567 read_register_gen (regno, buffer);
2568 write_memory (*sp, buffer + offset, regsize);
2571 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2572 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2575 mips_push_dummy_frame (void)
2578 struct linked_proc_info *link = (struct linked_proc_info *)
2579 xmalloc (sizeof (struct linked_proc_info));
2580 mips_extra_func_info_t proc_desc = &link->info;
2581 CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
2582 CORE_ADDR old_sp = sp;
2583 link->next = linked_proc_desc_table;
2584 linked_proc_desc_table = link;
2586 /* FIXME! are these correct ? */
2587 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2588 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2589 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2590 #define FLOAT_SINGLE_REG_SAVE_MASK \
2591 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2593 * The registers we must save are all those not preserved across
2594 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2595 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2596 * and FP Control/Status registers.
2599 * Dummy frame layout:
2602 * Saved MMHI, MMLO, FPC_CSR
2607 * Saved D18 (i.e. F19, F18)
2609 * Saved D0 (i.e. F1, F0)
2610 * Argument build area and stack arguments written via mips_push_arguments
2614 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2615 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
2616 PROC_FRAME_OFFSET (proc_desc) = 0;
2617 PROC_FRAME_ADJUST (proc_desc) = 0;
2618 mips_push_register (&sp, PC_REGNUM);
2619 mips_push_register (&sp, HI_REGNUM);
2620 mips_push_register (&sp, LO_REGNUM);
2621 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
2623 /* Save general CPU registers */
2624 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
2625 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2626 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
2627 for (ireg = 32; --ireg >= 0;)
2628 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
2629 mips_push_register (&sp, ireg);
2631 /* Save floating point registers starting with high order word */
2632 PROC_FREG_MASK (proc_desc) =
2633 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
2634 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
2635 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2637 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
2638 for (ireg = 32; --ireg >= 0;)
2639 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
2640 mips_push_register (&sp, ireg + FP0_REGNUM);
2642 /* Update the frame pointer for the call dummy and the stack pointer.
2643 Set the procedure's starting and ending addresses to point to the
2644 call dummy address at the entry point. */
2645 write_register (PUSH_FP_REGNUM, old_sp);
2646 write_register (SP_REGNUM, sp);
2647 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
2648 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
2649 SET_PROC_DESC_IS_DUMMY (proc_desc);
2650 PROC_PC_REG (proc_desc) = RA_REGNUM;
2654 mips_pop_frame (void)
2656 register int regnum;
2657 struct frame_info *frame = get_current_frame ();
2658 CORE_ADDR new_sp = FRAME_FP (frame);
2660 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
2662 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
2663 if (frame->saved_regs == NULL)
2664 mips_find_saved_regs (frame);
2665 for (regnum = 0; regnum < NUM_REGS; regnum++)
2667 if (regnum != SP_REGNUM && regnum != PC_REGNUM
2668 && frame->saved_regs[regnum])
2669 write_register (regnum,
2670 read_memory_integer (frame->saved_regs[regnum],
2671 MIPS_SAVED_REGSIZE));
2673 write_register (SP_REGNUM, new_sp);
2674 flush_cached_frames ();
2676 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
2678 struct linked_proc_info *pi_ptr, *prev_ptr;
2680 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
2682 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
2684 if (&pi_ptr->info == proc_desc)
2689 error ("Can't locate dummy extra frame info\n");
2691 if (prev_ptr != NULL)
2692 prev_ptr->next = pi_ptr->next;
2694 linked_proc_desc_table = pi_ptr->next;
2698 write_register (HI_REGNUM,
2699 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
2700 MIPS_SAVED_REGSIZE));
2701 write_register (LO_REGNUM,
2702 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
2703 MIPS_SAVED_REGSIZE));
2704 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
2705 write_register (FCRCS_REGNUM,
2706 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
2707 MIPS_SAVED_REGSIZE));
2711 /* Floating point register management.
2713 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2714 64bit operations, these early MIPS cpus treat fp register pairs
2715 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2716 registers and offer a compatibility mode that emulates the MIPS2 fp
2717 model. When operating in MIPS2 fp compat mode, later cpu's split
2718 double precision floats into two 32-bit chunks and store them in
2719 consecutive fp regs. To display 64-bit floats stored in this
2720 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2721 Throw in user-configurable endianness and you have a real mess.
2723 The way this works is:
2724 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2725 double-precision value will be split across two logical registers.
2726 The lower-numbered logical register will hold the low-order bits,
2727 regardless of the processor's endianness.
2728 - If we are on a 64-bit processor, and we are looking for a
2729 single-precision value, it will be in the low ordered bits
2730 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2731 save slot in memory.
2732 - If we are in 64-bit mode, everything is straightforward.
2734 Note that this code only deals with "live" registers at the top of the
2735 stack. We will attempt to deal with saved registers later, when
2736 the raw/cooked register interface is in place. (We need a general
2737 interface that can deal with dynamic saved register sizes -- fp
2738 regs could be 32 bits wide in one frame and 64 on the frame above
2741 /* Copy a 32-bit single-precision value from the current frame
2742 into rare_buffer. */
2745 mips_read_fp_register_single (int regno, char *rare_buffer)
2747 int raw_size = REGISTER_RAW_SIZE (regno);
2748 char *raw_buffer = alloca (raw_size);
2750 if (!frame_register_read (selected_frame, regno, raw_buffer))
2751 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
2754 /* We have a 64-bit value for this register. Find the low-order
2758 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2763 memcpy (rare_buffer, raw_buffer + offset, 4);
2767 memcpy (rare_buffer, raw_buffer, 4);
2771 /* Copy a 64-bit double-precision value from the current frame into
2772 rare_buffer. This may include getting half of it from the next
2776 mips_read_fp_register_double (int regno, char *rare_buffer)
2778 int raw_size = REGISTER_RAW_SIZE (regno);
2780 if (raw_size == 8 && !mips2_fp_compat ())
2782 /* We have a 64-bit value for this register, and we should use
2784 if (!frame_register_read (selected_frame, regno, rare_buffer))
2785 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
2789 if ((regno - FP0_REGNUM) & 1)
2790 internal_error (__FILE__, __LINE__,
2791 "mips_read_fp_register_double: bad access to "
2792 "odd-numbered FP register");
2794 /* mips_read_fp_register_single will find the correct 32 bits from
2796 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2798 mips_read_fp_register_single (regno, rare_buffer + 4);
2799 mips_read_fp_register_single (regno + 1, rare_buffer);
2803 mips_read_fp_register_single (regno, rare_buffer);
2804 mips_read_fp_register_single (regno + 1, rare_buffer + 4);
2810 mips_print_register (int regnum, int all)
2812 char raw_buffer[MAX_REGISTER_RAW_SIZE];
2814 /* Get the data in raw format. */
2815 if (!frame_register_read (selected_frame, regnum, raw_buffer))
2817 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
2821 /* If we have a actual 32-bit floating point register (or we are in
2822 32-bit compatibility mode), and the register is even-numbered,
2823 also print it as a double (spanning two registers). */
2824 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
2825 && (REGISTER_RAW_SIZE (regnum) == 4
2826 || mips2_fp_compat ())
2827 && !((regnum - FP0_REGNUM) & 1))
2829 char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
2831 mips_read_fp_register_double (regnum, dbuffer);
2833 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
2834 val_print (builtin_type_double, dbuffer, 0, 0,
2835 gdb_stdout, 0, 1, 0, Val_pretty_default);
2836 printf_filtered ("); ");
2838 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
2840 /* The problem with printing numeric register names (r26, etc.) is that
2841 the user can't use them on input. Probably the best solution is to
2842 fix it so that either the numeric or the funky (a2, etc.) names
2843 are accepted on input. */
2844 if (regnum < MIPS_NUMREGS)
2845 printf_filtered ("(r%d): ", regnum);
2847 printf_filtered (": ");
2849 /* If virtual format is floating, print it that way. */
2850 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2851 if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
2853 /* We have a meaningful 64-bit value in this register. Show
2854 it as a 32-bit float and a 64-bit double. */
2855 int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
2857 printf_filtered (" (float) ");
2858 val_print (builtin_type_float, raw_buffer + offset, 0, 0,
2859 gdb_stdout, 0, 1, 0, Val_pretty_default);
2860 printf_filtered (", (double) ");
2861 val_print (builtin_type_double, raw_buffer, 0, 0,
2862 gdb_stdout, 0, 1, 0, Val_pretty_default);
2865 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
2866 gdb_stdout, 0, 1, 0, Val_pretty_default);
2867 /* Else print as integer in hex. */
2872 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2873 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
2877 print_scalar_formatted (raw_buffer + offset,
2878 REGISTER_VIRTUAL_TYPE (regnum),
2879 'x', 0, gdb_stdout);
2883 /* Replacement for generic do_registers_info.
2884 Print regs in pretty columns. */
2887 do_fp_register_row (int regnum)
2888 { /* do values for FP (float) regs */
2890 double doub, flt1, flt2; /* doubles extracted from raw hex data */
2891 int inv1, inv2, inv3;
2893 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
2895 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
2897 /* 4-byte registers: we can fit two registers per row. */
2898 /* Also print every pair of 4-byte regs as an 8-byte double. */
2899 mips_read_fp_register_single (regnum, raw_buffer);
2900 flt1 = unpack_double (builtin_type_float, raw_buffer, &inv1);
2902 mips_read_fp_register_single (regnum + 1, raw_buffer);
2903 flt2 = unpack_double (builtin_type_float, raw_buffer, &inv2);
2905 mips_read_fp_register_double (regnum, raw_buffer);
2906 doub = unpack_double (builtin_type_double, raw_buffer, &inv3);
2908 printf_filtered (" %-5s", REGISTER_NAME (regnum));
2910 printf_filtered (": <invalid float>");
2912 printf_filtered ("%-17.9g", flt1);
2914 printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
2916 printf_filtered (": <invalid float>");
2918 printf_filtered ("%-17.9g", flt2);
2920 printf_filtered (" dbl: ");
2922 printf_filtered ("<invalid double>");
2924 printf_filtered ("%-24.17g", doub);
2925 printf_filtered ("\n");
2927 /* may want to do hex display here (future enhancement) */
2932 /* Eight byte registers: print each one as float AND as double. */
2933 mips_read_fp_register_single (regnum, raw_buffer);
2934 flt1 = unpack_double (builtin_type_double, raw_buffer, &inv1);
2936 mips_read_fp_register_double (regnum, raw_buffer);
2937 doub = unpack_double (builtin_type_double, raw_buffer, &inv3);
2939 printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
2941 printf_filtered ("<invalid float>");
2943 printf_filtered ("flt: %-17.9g", flt1);
2945 printf_filtered (" dbl: ");
2947 printf_filtered ("<invalid double>");
2949 printf_filtered ("%-24.17g", doub);
2951 printf_filtered ("\n");
2952 /* may want to do hex display here (future enhancement) */
2958 /* Print a row's worth of GP (int) registers, with name labels above */
2961 do_gp_register_row (int regnum)
2963 /* do values for GP (int) regs */
2964 char raw_buffer[MAX_REGISTER_RAW_SIZE];
2965 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
2967 int start_regnum = regnum;
2968 int numregs = NUM_REGS;
2971 /* For GP registers, we print a separate row of names above the vals */
2972 printf_filtered (" ");
2973 for (col = 0; col < ncols && regnum < numregs; regnum++)
2975 if (*REGISTER_NAME (regnum) == '\0')
2976 continue; /* unused register */
2977 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2978 break; /* end the row: reached FP register */
2979 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
2980 REGISTER_NAME (regnum));
2983 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
2984 start_regnum); /* print the R0 to R31 names */
2986 regnum = start_regnum; /* go back to start of row */
2987 /* now print the values in hex, 4 or 8 to the row */
2988 for (col = 0; col < ncols && regnum < numregs; regnum++)
2990 if (*REGISTER_NAME (regnum) == '\0')
2991 continue; /* unused register */
2992 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2993 break; /* end row: reached FP register */
2994 /* OK: get the data in raw format. */
2995 if (!frame_register_read (selected_frame, regnum, raw_buffer))
2996 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2997 /* pad small registers */
2998 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
2999 printf_filtered (" ");
3000 /* Now print the register value in hex, endian order. */
3001 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3002 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
3003 byte < REGISTER_RAW_SIZE (regnum);
3005 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
3007 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
3010 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
3011 printf_filtered (" ");
3014 if (col > 0) /* ie. if we actually printed anything... */
3015 printf_filtered ("\n");
3020 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3023 mips_do_registers_info (int regnum, int fpregs)
3025 if (regnum != -1) /* do one specified register */
3027 if (*(REGISTER_NAME (regnum)) == '\0')
3028 error ("Not a valid register for the current processor type");
3030 mips_print_register (regnum, 0);
3031 printf_filtered ("\n");
3034 /* do all (or most) registers */
3037 while (regnum < NUM_REGS)
3039 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3040 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
3041 regnum = do_fp_register_row (regnum); /* FP regs */
3043 regnum += MIPS_NUMREGS; /* skip floating point regs */
3045 regnum = do_gp_register_row (regnum); /* GP (int) regs */
3050 /* Return number of args passed to a frame. described by FIP.
3051 Can return -1, meaning no way to tell. */
3054 mips_frame_num_args (struct frame_info *frame)
3059 /* Is this a branch with a delay slot? */
3061 static int is_delayed (unsigned long);
3064 is_delayed (unsigned long insn)
3067 for (i = 0; i < NUMOPCODES; ++i)
3068 if (mips_opcodes[i].pinfo != INSN_MACRO
3069 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
3071 return (i < NUMOPCODES
3072 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
3073 | INSN_COND_BRANCH_DELAY
3074 | INSN_COND_BRANCH_LIKELY)));
3078 mips_step_skips_delay (CORE_ADDR pc)
3080 char buf[MIPS_INSTLEN];
3082 /* There is no branch delay slot on MIPS16. */
3083 if (pc_is_mips16 (pc))
3086 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
3087 /* If error reading memory, guess that it is not a delayed branch. */
3089 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
3093 /* Skip the PC past function prologue instructions (32-bit version).
3094 This is a helper function for mips_skip_prologue. */
3097 mips32_skip_prologue (CORE_ADDR pc)
3101 int seen_sp_adjust = 0;
3102 int load_immediate_bytes = 0;
3104 /* Skip the typical prologue instructions. These are the stack adjustment
3105 instruction and the instructions that save registers on the stack
3106 or in the gcc frame. */
3107 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
3109 unsigned long high_word;
3111 inst = mips_fetch_instruction (pc);
3112 high_word = (inst >> 16) & 0xffff;
3114 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
3115 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
3117 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
3118 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
3120 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3121 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3122 && (inst & 0x001F0000)) /* reg != $zero */
3125 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3127 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
3129 continue; /* reg != $zero */
3131 /* move $s8,$sp. With different versions of gas this will be either
3132 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3133 Accept any one of these. */
3134 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3137 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3139 else if (high_word == 0x3c1c) /* lui $gp,n */
3141 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
3143 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3144 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
3146 /* The following instructions load $at or $t0 with an immediate
3147 value in preparation for a stack adjustment via
3148 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3149 a local variable, so we accept them only before a stack adjustment
3150 instruction was seen. */
3151 else if (!seen_sp_adjust)
3153 if (high_word == 0x3c01 || /* lui $at,n */
3154 high_word == 0x3c08) /* lui $t0,n */
3156 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
3159 else if (high_word == 0x3421 || /* ori $at,$at,n */
3160 high_word == 0x3508 || /* ori $t0,$t0,n */
3161 high_word == 0x3401 || /* ori $at,$zero,n */
3162 high_word == 0x3408) /* ori $t0,$zero,n */
3164 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
3174 /* In a frameless function, we might have incorrectly
3175 skipped some load immediate instructions. Undo the skipping
3176 if the load immediate was not followed by a stack adjustment. */
3177 if (load_immediate_bytes && !seen_sp_adjust)
3178 pc -= load_immediate_bytes;
3182 /* Skip the PC past function prologue instructions (16-bit version).
3183 This is a helper function for mips_skip_prologue. */
3186 mips16_skip_prologue (CORE_ADDR pc)
3189 int extend_bytes = 0;
3190 int prev_extend_bytes;
3192 /* Table of instructions likely to be found in a function prologue. */
3195 unsigned short inst;
3196 unsigned short mask;
3203 , /* addiu $sp,offset */
3207 , /* daddiu $sp,offset */
3211 , /* sw reg,n($sp) */
3215 , /* sd reg,n($sp) */
3219 , /* sw $ra,n($sp) */
3223 , /* sd $ra,n($sp) */
3231 , /* sw $a0-$a3,n($s1) */
3235 , /* move reg,$a0-$a3 */
3239 , /* entry pseudo-op */
3243 , /* addiu $s1,$sp,n */
3246 } /* end of table marker */
3249 /* Skip the typical prologue instructions. These are the stack adjustment
3250 instruction and the instructions that save registers on the stack
3251 or in the gcc frame. */
3252 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
3254 unsigned short inst;
3257 inst = mips_fetch_instruction (pc);
3259 /* Normally we ignore an extend instruction. However, if it is
3260 not followed by a valid prologue instruction, we must adjust
3261 the pc back over the extend so that it won't be considered
3262 part of the prologue. */
3263 if ((inst & 0xf800) == 0xf000) /* extend */
3265 extend_bytes = MIPS16_INSTLEN;
3268 prev_extend_bytes = extend_bytes;
3271 /* Check for other valid prologue instructions besides extend. */
3272 for (i = 0; table[i].mask != 0; i++)
3273 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
3275 if (table[i].mask != 0) /* it was in table? */
3276 continue; /* ignore it */
3280 /* Return the current pc, adjusted backwards by 2 if
3281 the previous instruction was an extend. */
3282 return pc - prev_extend_bytes;
3288 /* To skip prologues, I use this predicate. Returns either PC itself
3289 if the code at PC does not look like a function prologue; otherwise
3290 returns an address that (if we're lucky) follows the prologue. If
3291 LENIENT, then we must skip everything which is involved in setting
3292 up the frame (it's OK to skip more, just so long as we don't skip
3293 anything which might clobber the registers which are being saved.
3294 We must skip more in the case where part of the prologue is in the
3295 delay slot of a non-prologue instruction). */
3298 mips_skip_prologue (CORE_ADDR pc)
3300 /* See if we can determine the end of the prologue via the symbol table.
3301 If so, then return either PC, or the PC after the prologue, whichever
3304 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
3306 if (post_prologue_pc != 0)
3307 return max (pc, post_prologue_pc);
3309 /* Can't determine prologue from the symbol table, need to examine
3312 if (pc_is_mips16 (pc))
3313 return mips16_skip_prologue (pc);
3315 return mips32_skip_prologue (pc);
3318 /* Determine how a return value is stored within the MIPS register
3319 file, given the return type `valtype'. */
3321 struct return_value_word
3330 return_value_location (struct type *valtype,
3331 struct return_value_word *hi,
3332 struct return_value_word *lo)
3334 int len = TYPE_LENGTH (valtype);
3336 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
3337 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
3338 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
3340 if (!FP_REGISTER_DOUBLE && len == 8)
3342 /* We need to break a 64bit float in two 32 bit halves and
3343 spread them across a floating-point register pair. */
3344 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3345 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
3346 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3347 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
3349 hi->reg_offset = lo->reg_offset;
3350 lo->reg = FP0_REGNUM + 0;
3351 hi->reg = FP0_REGNUM + 1;
3357 /* The floating point value fits in a single floating-point
3359 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3360 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
3363 lo->reg = FP0_REGNUM;
3374 /* Locate a result possibly spread across two registers. */
3376 lo->reg = regnum + 0;
3377 hi->reg = regnum + 1;
3378 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3379 && len < MIPS_SAVED_REGSIZE)
3381 /* "un-left-justify" the value in the low register */
3382 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
3387 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3388 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
3389 && len < MIPS_SAVED_REGSIZE * 2
3390 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
3391 TYPE_CODE (valtype) == TYPE_CODE_UNION))
3393 /* "un-left-justify" the value spread across two registers. */
3394 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
3395 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
3397 hi->len = len - lo->len;
3401 /* Only perform a partial copy of the second register. */
3404 if (len > MIPS_SAVED_REGSIZE)
3406 lo->len = MIPS_SAVED_REGSIZE;
3407 hi->len = len - MIPS_SAVED_REGSIZE;
3415 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3416 && REGISTER_RAW_SIZE (regnum) == 8
3417 && MIPS_SAVED_REGSIZE == 4)
3419 /* Account for the fact that only the least-signficant part
3420 of the register is being used */
3421 lo->reg_offset += 4;
3422 hi->reg_offset += 4;
3425 hi->buf_offset = lo->len;
3429 /* Given a return value in `regbuf' with a type `valtype', extract and
3430 copy its value into `valbuf'. */
3433 mips_extract_return_value (struct type *valtype,
3434 char regbuf[REGISTER_BYTES],
3437 struct return_value_word lo;
3438 struct return_value_word hi;
3439 return_value_location (valtype, &hi, &lo);
3441 memcpy (valbuf + lo.buf_offset,
3442 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
3446 memcpy (valbuf + hi.buf_offset,
3447 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
3451 /* Given a return value in `valbuf' with a type `valtype', write it's
3452 value into the appropriate register. */
3455 mips_store_return_value (struct type *valtype, char *valbuf)
3457 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3458 struct return_value_word lo;
3459 struct return_value_word hi;
3460 return_value_location (valtype, &hi, &lo);
3462 memset (raw_buffer, 0, sizeof (raw_buffer));
3463 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
3464 write_register_bytes (REGISTER_BYTE (lo.reg),
3466 REGISTER_RAW_SIZE (lo.reg));
3470 memset (raw_buffer, 0, sizeof (raw_buffer));
3471 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
3472 write_register_bytes (REGISTER_BYTE (hi.reg),
3474 REGISTER_RAW_SIZE (hi.reg));
3478 /* Exported procedure: Is PC in the signal trampoline code */
3481 in_sigtramp (CORE_ADDR pc, char *ignore)
3483 if (sigtramp_address == 0)
3485 return (pc >= sigtramp_address && pc < sigtramp_end);
3488 /* Root of all "set mips "/"show mips " commands. This will eventually be
3489 used for all MIPS-specific commands. */
3492 show_mips_command (char *args, int from_tty)
3494 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
3498 set_mips_command (char *args, int from_tty)
3500 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3501 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
3504 /* Commands to show/set the MIPS FPU type. */
3507 show_mipsfpu_command (char *args, int from_tty)
3510 switch (MIPS_FPU_TYPE)
3512 case MIPS_FPU_SINGLE:
3513 fpu = "single-precision";
3515 case MIPS_FPU_DOUBLE:
3516 fpu = "double-precision";
3519 fpu = "absent (none)";
3522 internal_error (__FILE__, __LINE__, "bad switch");
3524 if (mips_fpu_type_auto)
3525 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3528 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3534 set_mipsfpu_command (char *args, int from_tty)
3536 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3537 show_mipsfpu_command (args, from_tty);
3541 set_mipsfpu_single_command (char *args, int from_tty)
3543 mips_fpu_type = MIPS_FPU_SINGLE;
3544 mips_fpu_type_auto = 0;
3547 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
3552 set_mipsfpu_double_command (char *args, int from_tty)
3554 mips_fpu_type = MIPS_FPU_DOUBLE;
3555 mips_fpu_type_auto = 0;
3558 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
3563 set_mipsfpu_none_command (char *args, int from_tty)
3565 mips_fpu_type = MIPS_FPU_NONE;
3566 mips_fpu_type_auto = 0;
3569 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
3574 set_mipsfpu_auto_command (char *args, int from_tty)
3576 mips_fpu_type_auto = 1;
3579 /* Command to set the processor type. */
3582 mips_set_processor_type_command (char *args, int from_tty)
3586 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
3588 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3589 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3590 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
3592 /* Restore the value. */
3593 tmp_mips_processor_type = xstrdup (mips_processor_type);
3598 if (!mips_set_processor_type (tmp_mips_processor_type))
3600 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
3601 /* Restore its value. */
3602 tmp_mips_processor_type = xstrdup (mips_processor_type);
3607 mips_show_processor_type_command (char *args, int from_tty)
3611 /* Modify the actual processor type. */
3614 mips_set_processor_type (char *str)
3621 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3623 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
3625 mips_processor_type = str;
3626 mips_processor_reg_names = mips_processor_type_table[i].regnames;
3628 /* FIXME tweak fpu flag too */
3635 /* Attempt to identify the particular processor model by reading the
3639 mips_read_processor_type (void)
3643 prid = read_register (PRID_REGNUM);
3645 if ((prid & ~0xf) == 0x700)
3646 return savestring ("r3041", strlen ("r3041"));
3651 /* Just like reinit_frame_cache, but with the right arguments to be
3652 callable as an sfunc. */
3655 reinit_frame_cache_sfunc (char *args, int from_tty,
3656 struct cmd_list_element *c)
3658 reinit_frame_cache ();
3662 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
3664 mips_extra_func_info_t proc_desc;
3666 /* Search for the function containing this address. Set the low bit
3667 of the address when searching, in case we were given an even address
3668 that is the start of a 16-bit function. If we didn't do this,
3669 the search would fail because the symbol table says the function
3670 starts at an odd address, i.e. 1 byte past the given address. */
3671 memaddr = ADDR_BITS_REMOVE (memaddr);
3672 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
3674 /* Make an attempt to determine if this is a 16-bit function. If
3675 the procedure descriptor exists and the address therein is odd,
3676 it's definitely a 16-bit function. Otherwise, we have to just
3677 guess that if the address passed in is odd, it's 16-bits. */
3679 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
3680 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
3682 info->mach = pc_is_mips16 (memaddr) ?
3683 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
3685 /* Round down the instruction address to the appropriate boundary. */
3686 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
3688 /* Call the appropriate disassembler based on the target endian-ness. */
3689 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3690 return print_insn_big_mips (memaddr, info);
3692 return print_insn_little_mips (memaddr, info);
3695 /* Old-style breakpoint macros.
3696 The IDT board uses an unusual breakpoint value, and sometimes gets
3697 confused when it sees the usual MIPS breakpoint instruction. */
3699 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3700 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3701 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3702 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3703 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3704 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3705 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3706 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3708 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3709 counter value to determine whether a 16- or 32-bit breakpoint should be
3710 used. It returns a pointer to a string of bytes that encode a breakpoint
3711 instruction, stores the length of the string to *lenptr, and adjusts pc
3712 (if necessary) to point to the actual memory location where the
3713 breakpoint should be inserted. */
3715 const unsigned char *
3716 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
3718 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3720 if (pc_is_mips16 (*pcptr))
3722 static unsigned char mips16_big_breakpoint[] =
3723 MIPS16_BIG_BREAKPOINT;
3724 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
3725 *lenptr = sizeof (mips16_big_breakpoint);
3726 return mips16_big_breakpoint;
3730 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
3731 static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
3732 static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
3734 *lenptr = sizeof (big_breakpoint);
3736 if (strcmp (target_shortname, "mips") == 0)
3737 return idt_big_breakpoint;
3738 else if (strcmp (target_shortname, "ddb") == 0
3739 || strcmp (target_shortname, "pmon") == 0
3740 || strcmp (target_shortname, "lsi") == 0)
3741 return pmon_big_breakpoint;
3743 return big_breakpoint;
3748 if (pc_is_mips16 (*pcptr))
3750 static unsigned char mips16_little_breakpoint[] =
3751 MIPS16_LITTLE_BREAKPOINT;
3752 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
3753 *lenptr = sizeof (mips16_little_breakpoint);
3754 return mips16_little_breakpoint;
3758 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
3759 static unsigned char pmon_little_breakpoint[] =
3760 PMON_LITTLE_BREAKPOINT;
3761 static unsigned char idt_little_breakpoint[] =
3762 IDT_LITTLE_BREAKPOINT;
3764 *lenptr = sizeof (little_breakpoint);
3766 if (strcmp (target_shortname, "mips") == 0)
3767 return idt_little_breakpoint;
3768 else if (strcmp (target_shortname, "ddb") == 0
3769 || strcmp (target_shortname, "pmon") == 0
3770 || strcmp (target_shortname, "lsi") == 0)
3771 return pmon_little_breakpoint;
3773 return little_breakpoint;
3778 /* If PC is in a mips16 call or return stub, return the address of the target
3779 PC, which is either the callee or the caller. There are several
3780 cases which must be handled:
3782 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3783 target PC is in $31 ($ra).
3784 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3785 and the target PC is in $2.
3786 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3787 before the jal instruction, this is effectively a call stub
3788 and the the target PC is in $2. Otherwise this is effectively
3789 a return stub and the target PC is in $18.
3791 See the source code for the stubs in gcc/config/mips/mips16.S for
3794 This function implements the SKIP_TRAMPOLINE_CODE macro.
3798 mips_skip_stub (CORE_ADDR pc)
3801 CORE_ADDR start_addr;
3803 /* Find the starting address and name of the function containing the PC. */
3804 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
3807 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3808 target PC is in $31 ($ra). */
3809 if (strcmp (name, "__mips16_ret_sf") == 0
3810 || strcmp (name, "__mips16_ret_df") == 0)
3811 return read_signed_register (RA_REGNUM);
3813 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
3815 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3816 and the target PC is in $2. */
3817 if (name[19] >= '0' && name[19] <= '9')
3818 return read_signed_register (2);
3820 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3821 before the jal instruction, this is effectively a call stub
3822 and the the target PC is in $2. Otherwise this is effectively
3823 a return stub and the target PC is in $18. */
3824 else if (name[19] == 's' || name[19] == 'd')
3826 if (pc == start_addr)
3828 /* Check if the target of the stub is a compiler-generated
3829 stub. Such a stub for a function bar might have a name
3830 like __fn_stub_bar, and might look like this:
3835 la $1,bar (becomes a lui/addiu pair)
3837 So scan down to the lui/addi and extract the target
3838 address from those two instructions. */
3840 CORE_ADDR target_pc = read_signed_register (2);
3844 /* See if the name of the target function is __fn_stub_*. */
3845 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
3847 if (strncmp (name, "__fn_stub_", 10) != 0
3848 && strcmp (name, "etext") != 0
3849 && strcmp (name, "_etext") != 0)
3852 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3853 The limit on the search is arbitrarily set to 20
3854 instructions. FIXME. */
3855 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
3857 inst = mips_fetch_instruction (target_pc);
3858 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
3859 pc = (inst << 16) & 0xffff0000; /* high word */
3860 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
3861 return pc | (inst & 0xffff); /* low word */
3864 /* Couldn't find the lui/addui pair, so return stub address. */
3868 /* This is the 'return' part of a call stub. The return
3869 address is in $r18. */
3870 return read_signed_register (18);
3873 return 0; /* not a stub */
3877 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3878 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3881 mips_in_call_stub (CORE_ADDR pc, char *name)
3883 CORE_ADDR start_addr;
3885 /* Find the starting address of the function containing the PC. If the
3886 caller didn't give us a name, look it up at the same time. */
3887 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
3890 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
3892 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3893 if (name[19] >= '0' && name[19] <= '9')
3895 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3896 before the jal instruction, this is effectively a call stub. */
3897 else if (name[19] == 's' || name[19] == 'd')
3898 return pc == start_addr;
3901 return 0; /* not a stub */
3905 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3906 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3909 mips_in_return_stub (CORE_ADDR pc, char *name)
3911 CORE_ADDR start_addr;
3913 /* Find the starting address of the function containing the PC. */
3914 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
3917 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3918 if (strcmp (name, "__mips16_ret_sf") == 0
3919 || strcmp (name, "__mips16_ret_df") == 0)
3922 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3923 i.e. after the jal instruction, this is effectively a return stub. */
3924 if (strncmp (name, "__mips16_call_stub_", 19) == 0
3925 && (name[19] == 's' || name[19] == 'd')
3926 && pc != start_addr)
3929 return 0; /* not a stub */
3933 /* Return non-zero if the PC is in a library helper function that should
3934 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3937 mips_ignore_helper (CORE_ADDR pc)
3941 /* Find the starting address and name of the function containing the PC. */
3942 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
3945 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3946 that we want to ignore. */
3947 return (strcmp (name, "__mips16_ret_sf") == 0
3948 || strcmp (name, "__mips16_ret_df") == 0);
3952 /* Return a location where we can set a breakpoint that will be hit
3953 when an inferior function call returns. This is normally the
3954 program's entry point. Executables that don't have an entry
3955 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3956 whose address is the location where the breakpoint should be placed. */
3959 mips_call_dummy_address (void)
3961 struct minimal_symbol *sym;
3963 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
3965 return SYMBOL_VALUE_ADDRESS (sym);
3967 return entry_point_address ();
3971 /* If the current gcc for this target does not produce correct debugging
3972 information for float parameters, both prototyped and unprototyped, then
3973 define this macro. This forces gdb to always assume that floats are
3974 passed as doubles and then converted in the callee.
3976 For the mips chip, it appears that the debug info marks the parameters as
3977 floats regardless of whether the function is prototyped, but the actual
3978 values are passed as doubles for the non-prototyped case and floats for
3979 the prototyped case. Thus we choose to make the non-prototyped case work
3980 for C and break the prototyped case, since the non-prototyped case is
3981 probably much more common. (FIXME). */
3984 mips_coerce_float_to_double (struct type *formal, struct type *actual)
3986 return current_language->la_language == language_c;
3989 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3990 the register stored on the stack (32) is different to its real raw
3991 size (64). The below ensures that registers are fetched from the
3992 stack using their ABI size and then stored into the RAW_BUFFER
3993 using their raw size.
3995 The alternative to adding this function would be to add an ABI
3996 macro - REGISTER_STACK_SIZE(). */
3999 mips_get_saved_register (char *raw_buffer,
4002 struct frame_info *frame,
4004 enum lval_type *lval)
4008 if (!target_has_registers)
4009 error ("No registers.");
4011 /* Normal systems don't optimize out things with register numbers. */
4012 if (optimized != NULL)
4014 addr = find_saved_register (frame, regnum);
4018 *lval = lval_memory;
4019 if (regnum == SP_REGNUM)
4021 if (raw_buffer != NULL)
4023 /* Put it back in target format. */
4024 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
4031 if (raw_buffer != NULL)
4035 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4037 val = read_memory_integer (addr, MIPS_SAVED_REGSIZE);
4039 val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum));
4040 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
4046 *lval = lval_register;
4047 addr = REGISTER_BYTE (regnum);
4048 if (raw_buffer != NULL)
4049 read_register_gen (regnum, raw_buffer);
4055 /* Immediately after a function call, return the saved pc.
4056 Can't always go through the frames for this because on some machines
4057 the new frame is not set up until the new function executes
4058 some instructions. */
4061 mips_saved_pc_after_call (struct frame_info *frame)
4063 return read_signed_register (RA_REGNUM);
4067 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4071 mips_stab_reg_to_regnum (int num)
4076 return num + FP0_REGNUM - 38;
4079 /* Convert a ecoff register number to a gdb REGNUM */
4082 mips_ecoff_reg_to_regnum (int num)
4087 return num + FP0_REGNUM - 32;
4090 /* Convert an integer into an address. By first converting the value
4091 into a pointer and then extracting it signed, the address is
4092 guarenteed to be correctly sign extended. */
4095 mips_integer_to_address (struct type *type, void *buf)
4097 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
4098 LONGEST val = unpack_long (type, buf);
4099 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
4100 return extract_signed_integer (tmp,
4101 TYPE_LENGTH (builtin_type_void_data_ptr));
4104 static struct gdbarch *
4105 mips_gdbarch_init (struct gdbarch_info info,
4106 struct gdbarch_list *arches)
4108 static LONGEST mips_call_dummy_words[] =
4110 struct gdbarch *gdbarch;
4111 struct gdbarch_tdep *tdep;
4113 enum mips_abi mips_abi;
4115 /* Reset the disassembly info, in case it was set to something
4117 tm_print_insn_info.flavour = bfd_target_unknown_flavour;
4118 tm_print_insn_info.arch = bfd_arch_unknown;
4119 tm_print_insn_info.mach = 0;
4121 /* Extract the elf_flags if available */
4122 if (info.abfd != NULL
4123 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
4124 elf_flags = elf_elfheader (info.abfd)->e_flags;
4128 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4129 switch ((elf_flags & EF_MIPS_ABI))
4131 case E_MIPS_ABI_O32:
4132 mips_abi = MIPS_ABI_O32;
4134 case E_MIPS_ABI_O64:
4135 mips_abi = MIPS_ABI_O64;
4137 case E_MIPS_ABI_EABI32:
4138 mips_abi = MIPS_ABI_EABI32;
4140 case E_MIPS_ABI_EABI64:
4141 mips_abi = MIPS_ABI_EABI64;
4144 if ((elf_flags & EF_MIPS_ABI2))
4145 mips_abi = MIPS_ABI_N32;
4147 mips_abi = MIPS_ABI_UNKNOWN;
4151 /* Try the architecture for any hint of the corect ABI */
4152 if (mips_abi == MIPS_ABI_UNKNOWN
4153 && info.bfd_arch_info != NULL
4154 && info.bfd_arch_info->arch == bfd_arch_mips)
4156 switch (info.bfd_arch_info->mach)
4158 case bfd_mach_mips3900:
4159 mips_abi = MIPS_ABI_EABI32;
4161 case bfd_mach_mips4100:
4162 case bfd_mach_mips5000:
4163 mips_abi = MIPS_ABI_EABI64;
4165 case bfd_mach_mips8000:
4166 case bfd_mach_mips10000:
4167 mips_abi = MIPS_ABI_N32;
4171 #ifdef MIPS_DEFAULT_ABI
4172 if (mips_abi == MIPS_ABI_UNKNOWN)
4173 mips_abi = MIPS_DEFAULT_ABI;
4178 fprintf_unfiltered (gdb_stdlog,
4179 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4181 fprintf_unfiltered (gdb_stdlog,
4182 "mips_gdbarch_init: mips_abi = %d\n",
4186 /* try to find a pre-existing architecture */
4187 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4189 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4191 /* MIPS needs to be pedantic about which ABI the object is
4193 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
4195 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
4197 return arches->gdbarch;
4200 /* Need a new architecture. Fill in a target specific vector. */
4201 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4202 gdbarch = gdbarch_alloc (&info, tdep);
4203 tdep->elf_flags = elf_flags;
4205 /* Initially set everything according to the default ABI/ISA. */
4206 set_gdbarch_short_bit (gdbarch, 16);
4207 set_gdbarch_int_bit (gdbarch, 32);
4208 set_gdbarch_float_bit (gdbarch, 32);
4209 set_gdbarch_double_bit (gdbarch, 64);
4210 set_gdbarch_long_double_bit (gdbarch, 64);
4211 set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size);
4212 tdep->mips_abi = mips_abi;
4217 tdep->mips_abi_string = "o32";
4218 tdep->mips_default_saved_regsize = 4;
4219 tdep->mips_default_stack_argsize = 4;
4220 tdep->mips_fp_register_double = 0;
4221 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
4222 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
4223 tdep->mips_regs_have_home_p = 1;
4224 tdep->gdb_target_is_mips64 = 0;
4225 tdep->default_mask_address_p = 0;
4226 set_gdbarch_long_bit (gdbarch, 32);
4227 set_gdbarch_ptr_bit (gdbarch, 32);
4228 set_gdbarch_long_long_bit (gdbarch, 64);
4231 tdep->mips_abi_string = "o64";
4232 tdep->mips_default_saved_regsize = 8;
4233 tdep->mips_default_stack_argsize = 8;
4234 tdep->mips_fp_register_double = 1;
4235 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
4236 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
4237 tdep->mips_regs_have_home_p = 1;
4238 tdep->gdb_target_is_mips64 = 1;
4239 tdep->default_mask_address_p = 0;
4240 set_gdbarch_long_bit (gdbarch, 32);
4241 set_gdbarch_ptr_bit (gdbarch, 32);
4242 set_gdbarch_long_long_bit (gdbarch, 64);
4244 case MIPS_ABI_EABI32:
4245 tdep->mips_abi_string = "eabi32";
4246 tdep->mips_default_saved_regsize = 4;
4247 tdep->mips_default_stack_argsize = 4;
4248 tdep->mips_fp_register_double = 0;
4249 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4250 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4251 tdep->mips_regs_have_home_p = 0;
4252 tdep->gdb_target_is_mips64 = 0;
4253 tdep->default_mask_address_p = 0;
4254 set_gdbarch_long_bit (gdbarch, 32);
4255 set_gdbarch_ptr_bit (gdbarch, 32);
4256 set_gdbarch_long_long_bit (gdbarch, 64);
4258 case MIPS_ABI_EABI64:
4259 tdep->mips_abi_string = "eabi64";
4260 tdep->mips_default_saved_regsize = 8;
4261 tdep->mips_default_stack_argsize = 8;
4262 tdep->mips_fp_register_double = 1;
4263 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4264 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4265 tdep->mips_regs_have_home_p = 0;
4266 tdep->gdb_target_is_mips64 = 1;
4267 tdep->default_mask_address_p = 0;
4268 set_gdbarch_long_bit (gdbarch, 64);
4269 set_gdbarch_ptr_bit (gdbarch, 64);
4270 set_gdbarch_long_long_bit (gdbarch, 64);
4273 tdep->mips_abi_string = "n32";
4274 tdep->mips_default_saved_regsize = 4;
4275 tdep->mips_default_stack_argsize = 8;
4276 tdep->mips_fp_register_double = 1;
4277 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4278 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4279 tdep->mips_regs_have_home_p = 0;
4280 tdep->gdb_target_is_mips64 = 0;
4281 tdep->default_mask_address_p = 0;
4282 set_gdbarch_long_bit (gdbarch, 32);
4283 set_gdbarch_ptr_bit (gdbarch, 32);
4284 set_gdbarch_long_long_bit (gdbarch, 64);
4286 /* Set up the disassembler info, so that we get the right
4287 register names from libopcodes. */
4288 tm_print_insn_info.flavour = bfd_target_elf_flavour;
4289 tm_print_insn_info.arch = bfd_arch_mips;
4290 if (info.bfd_arch_info != NULL
4291 && info.bfd_arch_info->arch == bfd_arch_mips
4292 && info.bfd_arch_info->mach)
4293 tm_print_insn_info.mach = info.bfd_arch_info->mach;
4295 tm_print_insn_info.mach = bfd_mach_mips8000;
4298 tdep->mips_abi_string = "default";
4299 tdep->mips_default_saved_regsize = MIPS_REGSIZE;
4300 tdep->mips_default_stack_argsize = MIPS_REGSIZE;
4301 tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8);
4302 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4303 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4304 tdep->mips_regs_have_home_p = 1;
4305 tdep->gdb_target_is_mips64 = 0;
4306 tdep->default_mask_address_p = 0;
4307 set_gdbarch_long_bit (gdbarch, 32);
4308 set_gdbarch_ptr_bit (gdbarch, 32);
4309 set_gdbarch_long_long_bit (gdbarch, 64);
4313 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4314 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4317 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4318 flag in object files because to do so would make it impossible to
4319 link with libraries compiled without "-gp32". This is
4320 unnecessarily restrictive.
4322 We could solve this problem by adding "-gp32" multilibs to gcc,
4323 but to set this flag before gcc is built with such multilibs will
4324 break too many systems.''
4326 But even more unhelpfully, the default linker output target for
4327 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4328 for 64-bit programs - you need to change the ABI to change this,
4329 and not all gcc targets support that currently. Therefore using
4330 this flag to detect 32-bit mode would do the wrong thing given
4331 the current gcc - it would make GDB treat these 64-bit programs
4332 as 32-bit programs by default. */
4334 /* enable/disable the MIPS FPU */
4335 if (!mips_fpu_type_auto)
4336 tdep->mips_fpu_type = mips_fpu_type;
4337 else if (info.bfd_arch_info != NULL
4338 && info.bfd_arch_info->arch == bfd_arch_mips)
4339 switch (info.bfd_arch_info->mach)
4341 case bfd_mach_mips3900:
4342 case bfd_mach_mips4100:
4343 case bfd_mach_mips4111:
4344 tdep->mips_fpu_type = MIPS_FPU_NONE;
4346 case bfd_mach_mips4650:
4347 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
4350 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
4354 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
4356 /* MIPS version of register names. NOTE: At present the MIPS
4357 register name management is part way between the old -
4358 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4359 Further work on it is required. */
4360 set_gdbarch_register_name (gdbarch, mips_register_name);
4361 set_gdbarch_read_pc (gdbarch, mips_read_pc);
4362 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4363 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
4364 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4365 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4367 /* Add/remove bits from an address. The MIPS needs be careful to
4368 ensure that all 32 bit addresses are sign extended to 64 bits. */
4369 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
4371 /* There's a mess in stack frame creation. See comments in
4372 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4373 set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
4374 set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop);
4376 /* Map debug register numbers onto internal register numbers. */
4377 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
4378 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum);
4380 /* Initialize a frame */
4381 set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
4383 /* MIPS version of CALL_DUMMY */
4385 set_gdbarch_call_dummy_p (gdbarch, 1);
4386 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
4387 set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
4388 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
4389 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
4390 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
4391 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
4392 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4393 set_gdbarch_call_dummy_length (gdbarch, 0);
4394 set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
4395 set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
4396 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
4397 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
4398 set_gdbarch_push_arguments (gdbarch, mips_push_arguments);
4399 set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not);
4400 set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double);
4402 set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
4403 set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
4405 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4406 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
4407 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4409 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
4410 set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
4412 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
4413 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
4414 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
4419 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4421 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4425 int ef_mips_32bitmode;
4426 /* determine the ISA */
4427 switch (tdep->elf_flags & EF_MIPS_ARCH)
4445 /* determine the size of a pointer */
4446 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
4447 fprintf_unfiltered (file,
4448 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4450 fprintf_unfiltered (file,
4451 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4453 fprintf_unfiltered (file,
4454 "mips_dump_tdep: ef_mips_arch = %d\n",
4456 fprintf_unfiltered (file,
4457 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4459 tdep->mips_abi_string);
4460 fprintf_unfiltered (file,
4461 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4462 mips_mask_address_p (),
4463 tdep->default_mask_address_p);
4465 fprintf_unfiltered (file,
4466 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4467 FP_REGISTER_DOUBLE);
4468 fprintf_unfiltered (file,
4469 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4470 MIPS_DEFAULT_FPU_TYPE,
4471 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
4472 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
4473 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
4475 fprintf_unfiltered (file,
4476 "mips_dump_tdep: MIPS_EABI = %d\n",
4478 fprintf_unfiltered (file,
4479 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4480 MIPS_LAST_FP_ARG_REGNUM,
4481 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
4482 fprintf_unfiltered (file,
4483 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4485 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
4486 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
4487 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
4489 fprintf_unfiltered (file,
4490 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4491 MIPS_DEFAULT_SAVED_REGSIZE);
4492 fprintf_unfiltered (file,
4493 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4494 FP_REGISTER_DOUBLE);
4495 fprintf_unfiltered (file,
4496 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4497 MIPS_REGS_HAVE_HOME_P);
4498 fprintf_unfiltered (file,
4499 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4500 MIPS_DEFAULT_STACK_ARGSIZE);
4501 fprintf_unfiltered (file,
4502 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4503 MIPS_STACK_ARGSIZE);
4504 fprintf_unfiltered (file,
4505 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4507 fprintf_unfiltered (file,
4508 "mips_dump_tdep: A0_REGNUM = %d\n",
4510 fprintf_unfiltered (file,
4511 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4512 XSTRING (ADDR_BITS_REMOVE(ADDR)));
4513 fprintf_unfiltered (file,
4514 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4515 XSTRING (ATTACH_DETACH));
4516 fprintf_unfiltered (file,
4517 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4519 fprintf_unfiltered (file,
4520 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4521 fprintf_unfiltered (file,
4522 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4524 fprintf_unfiltered (file,
4525 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4527 fprintf_unfiltered (file,
4528 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4530 fprintf_unfiltered (file,
4531 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4532 XSTRING (DO_REGISTERS_INFO));
4533 fprintf_unfiltered (file,
4534 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4535 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
4536 fprintf_unfiltered (file,
4537 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4538 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
4539 fprintf_unfiltered (file,
4540 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4541 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM)));
4542 fprintf_unfiltered (file,
4543 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4545 fprintf_unfiltered (file,
4546 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4548 fprintf_unfiltered (file,
4549 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4550 FIRST_EMBED_REGNUM);
4551 fprintf_unfiltered (file,
4552 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4554 fprintf_unfiltered (file,
4555 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4556 GDB_TARGET_IS_MIPS64);
4557 fprintf_unfiltered (file,
4558 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4559 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC)));
4560 fprintf_unfiltered (file,
4561 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4562 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC)));
4563 fprintf_unfiltered (file,
4564 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4566 fprintf_unfiltered (file,
4567 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4568 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
4569 fprintf_unfiltered (file,
4570 "mips_dump_tdep: HI_REGNUM = %d\n",
4572 fprintf_unfiltered (file,
4573 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4574 fprintf_unfiltered (file,
4575 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4576 fprintf_unfiltered (file,
4577 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4578 XSTRING (IGNORE_HELPER_CALL (PC)));
4579 fprintf_unfiltered (file,
4580 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4581 XSTRING (IN_SIGTRAMP (PC, NAME)));
4582 fprintf_unfiltered (file,
4583 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4584 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
4585 fprintf_unfiltered (file,
4586 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4587 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
4588 fprintf_unfiltered (file,
4589 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4590 fprintf_unfiltered (file,
4591 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4593 fprintf_unfiltered (file,
4594 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4595 fprintf_unfiltered (file,
4596 "mips_dump_tdep: LO_REGNUM = %d\n",
4598 #ifdef MACHINE_CPROC_FP_OFFSET
4599 fprintf_unfiltered (file,
4600 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4601 MACHINE_CPROC_FP_OFFSET);
4603 #ifdef MACHINE_CPROC_PC_OFFSET
4604 fprintf_unfiltered (file,
4605 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4606 MACHINE_CPROC_PC_OFFSET);
4608 #ifdef MACHINE_CPROC_SP_OFFSET
4609 fprintf_unfiltered (file,
4610 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4611 MACHINE_CPROC_SP_OFFSET);
4613 fprintf_unfiltered (file,
4614 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4615 fprintf_unfiltered (file,
4616 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4617 fprintf_unfiltered (file,
4618 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4620 fprintf_unfiltered (file,
4621 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4622 fprintf_unfiltered (file,
4623 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4624 fprintf_unfiltered (file,
4625 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4626 fprintf_unfiltered (file,
4627 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4629 fprintf_unfiltered (file,
4630 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4631 MIPS_LAST_ARG_REGNUM,
4632 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
4633 fprintf_unfiltered (file,
4634 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4636 fprintf_unfiltered (file,
4637 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4638 fprintf_unfiltered (file,
4639 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4640 MIPS_SAVED_REGSIZE);
4641 fprintf_unfiltered (file,
4642 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4643 fprintf_unfiltered (file,
4644 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4645 XSTRING (MSYMBOL_SIZE (MSYM)));
4646 fprintf_unfiltered (file,
4647 "mips_dump_tdep: OP_LDFPR = used?\n");
4648 fprintf_unfiltered (file,
4649 "mips_dump_tdep: OP_LDGPR = used?\n");
4650 fprintf_unfiltered (file,
4651 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4652 fprintf_unfiltered (file,
4653 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4654 fprintf_unfiltered (file,
4655 "mips_dump_tdep: PRID_REGNUM = %d\n",
4657 fprintf_unfiltered (file,
4658 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4659 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
4660 fprintf_unfiltered (file,
4661 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4662 fprintf_unfiltered (file,
4663 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4664 fprintf_unfiltered (file,
4665 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4666 fprintf_unfiltered (file,
4667 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4668 fprintf_unfiltered (file,
4669 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4670 fprintf_unfiltered (file,
4671 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4672 fprintf_unfiltered (file,
4673 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4674 fprintf_unfiltered (file,
4675 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4676 fprintf_unfiltered (file,
4677 "mips_dump_tdep: PROC_PC_REG = function?\n");
4678 fprintf_unfiltered (file,
4679 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4680 fprintf_unfiltered (file,
4681 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4682 fprintf_unfiltered (file,
4683 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4684 fprintf_unfiltered (file,
4685 "mips_dump_tdep: PS_REGNUM = %d\n",
4687 fprintf_unfiltered (file,
4688 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4690 fprintf_unfiltered (file,
4691 "mips_dump_tdep: RA_REGNUM = %d\n",
4693 fprintf_unfiltered (file,
4694 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4695 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
4696 fprintf_unfiltered (file,
4697 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4698 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
4699 fprintf_unfiltered (file,
4700 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4701 fprintf_unfiltered (file,
4702 "mips_dump_tdep: ROUND_DOWN = function?\n");
4703 fprintf_unfiltered (file,
4704 "mips_dump_tdep: ROUND_UP = function?\n");
4706 fprintf_unfiltered (file,
4707 "mips_dump_tdep: SAVED_BYTES = %d\n",
4711 fprintf_unfiltered (file,
4712 "mips_dump_tdep: SAVED_FP = %d\n",
4716 fprintf_unfiltered (file,
4717 "mips_dump_tdep: SAVED_PC = %d\n",
4720 fprintf_unfiltered (file,
4721 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4722 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
4723 fprintf_unfiltered (file,
4724 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4725 fprintf_unfiltered (file,
4726 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4728 fprintf_unfiltered (file,
4729 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4730 SIGFRAME_FPREGSAVE_OFF);
4731 fprintf_unfiltered (file,
4732 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4734 fprintf_unfiltered (file,
4735 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4736 SIGFRAME_REGSAVE_OFF);
4737 fprintf_unfiltered (file,
4738 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4740 fprintf_unfiltered (file,
4741 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4742 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
4743 fprintf_unfiltered (file,
4744 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4745 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
4746 fprintf_unfiltered (file,
4747 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4748 SOFTWARE_SINGLE_STEP_P ());
4749 fprintf_unfiltered (file,
4750 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4751 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
4752 #ifdef STACK_END_ADDR
4753 fprintf_unfiltered (file,
4754 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4757 fprintf_unfiltered (file,
4758 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4759 XSTRING (STEP_SKIPS_DELAY (PC)));
4760 fprintf_unfiltered (file,
4761 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4762 STEP_SKIPS_DELAY_P);
4763 fprintf_unfiltered (file,
4764 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4765 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
4766 fprintf_unfiltered (file,
4767 "mips_dump_tdep: T9_REGNUM = %d\n",
4769 fprintf_unfiltered (file,
4770 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4771 fprintf_unfiltered (file,
4772 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4773 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
4774 fprintf_unfiltered (file,
4775 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4776 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
4777 fprintf_unfiltered (file,
4778 "mips_dump_tdep: TARGET_MIPS = used?\n");
4779 fprintf_unfiltered (file,
4780 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4781 XSTRING (TM_PRINT_INSN_MACH));
4783 fprintf_unfiltered (file,
4784 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4785 XSTRING (TRACE_CLEAR (THREAD, STATE)));
4788 fprintf_unfiltered (file,
4789 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4792 #ifdef TRACE_FLAVOR_SIZE
4793 fprintf_unfiltered (file,
4794 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4798 fprintf_unfiltered (file,
4799 "mips_dump_tdep: TRACE_SET # %s\n",
4800 XSTRING (TRACE_SET (X,STATE)));
4802 fprintf_unfiltered (file,
4803 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4804 #ifdef UNUSED_REGNUM
4805 fprintf_unfiltered (file,
4806 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4809 fprintf_unfiltered (file,
4810 "mips_dump_tdep: V0_REGNUM = %d\n",
4812 fprintf_unfiltered (file,
4813 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4814 (long) VM_MIN_ADDRESS);
4816 fprintf_unfiltered (file,
4817 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4820 fprintf_unfiltered (file,
4821 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4823 fprintf_unfiltered (file,
4824 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4829 _initialize_mips_tdep (void)
4831 static struct cmd_list_element *mipsfpulist = NULL;
4832 struct cmd_list_element *c;
4834 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
4835 if (!tm_print_insn) /* Someone may have already set it */
4836 tm_print_insn = gdb_print_insn_mips;
4838 /* Add root prefix command for all "set mips"/"show mips" commands */
4839 add_prefix_cmd ("mips", no_class, set_mips_command,
4840 "Various MIPS specific commands.",
4841 &setmipscmdlist, "set mips ", 0, &setlist);
4843 add_prefix_cmd ("mips", no_class, show_mips_command,
4844 "Various MIPS specific commands.",
4845 &showmipscmdlist, "show mips ", 0, &showlist);
4847 /* Allow the user to override the saved register size. */
4848 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4851 &mips_saved_regsize_string, "\
4852 Set size of general purpose registers saved on the stack.\n\
4853 This option can be set to one of:\n\
4854 32 - Force GDB to treat saved GP registers as 32-bit\n\
4855 64 - Force GDB to treat saved GP registers as 64-bit\n\
4856 auto - Allow GDB to use the target's default setting or autodetect the\n\
4857 saved GP register size from information contained in the executable.\n\
4862 /* Allow the user to override the argument stack size. */
4863 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4866 &mips_stack_argsize_string, "\
4867 Set the amount of stack space reserved for each argument.\n\
4868 This option can be set to one of:\n\
4869 32 - Force GDB to allocate 32-bit chunks per argument\n\
4870 64 - Force GDB to allocate 64-bit chunks per argument\n\
4871 auto - Allow GDB to determine the correct setting from the current\n\
4872 target and executable (default)",
4876 /* Let the user turn off floating point and set the fence post for
4877 heuristic_proc_start. */
4879 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
4880 "Set use of MIPS floating-point coprocessor.",
4881 &mipsfpulist, "set mipsfpu ", 0, &setlist);
4882 add_cmd ("single", class_support, set_mipsfpu_single_command,
4883 "Select single-precision MIPS floating-point coprocessor.",
4885 add_cmd ("double", class_support, set_mipsfpu_double_command,
4886 "Select double-precision MIPS floating-point coprocessor.",
4888 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
4889 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
4890 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
4891 add_cmd ("none", class_support, set_mipsfpu_none_command,
4892 "Select no MIPS floating-point coprocessor.",
4894 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
4895 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
4896 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
4897 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
4898 "Select MIPS floating-point coprocessor automatically.",
4900 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
4901 "Show current use of MIPS floating-point coprocessor target.",
4905 c = add_set_cmd ("processor", class_support, var_string_noescape,
4906 (char *) &tmp_mips_processor_type,
4907 "Set the type of MIPS processor in use.\n\
4908 Set this to be able to access processor-type-specific registers.\n\
4911 set_cmd_cfunc (c, mips_set_processor_type_command);
4912 c = add_show_from_set (c, &showlist);
4913 set_cmd_cfunc (c, mips_show_processor_type_command);
4915 tmp_mips_processor_type = xstrdup (DEFAULT_MIPS_TYPE);
4916 mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE), 0);
4919 /* We really would like to have both "0" and "unlimited" work, but
4920 command.c doesn't deal with that. So make it a var_zinteger
4921 because the user can always use "999999" or some such for unlimited. */
4922 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
4923 (char *) &heuristic_fence_post,
4925 Set the distance searched for the start of a function.\n\
4926 If you are debugging a stripped executable, GDB needs to search through the\n\
4927 program for the start of a function. This command sets the distance of the\n\
4928 search. The only need to set it is when debugging a stripped executable.",
4930 /* We need to throw away the frame cache when we set this, since it
4931 might change our ability to get backtraces. */
4932 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
4933 add_show_from_set (c, &showlist);
4935 /* Allow the user to control whether the upper bits of 64-bit
4936 addresses should be zeroed. */
4937 c = add_set_auto_boolean_cmd ("mask-address", no_class, &mask_address_var,
4938 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4939 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4940 the correct value.\n",
4942 add_cmd ("mask-address", no_class, show_mask_address,
4943 "Show current mask-address value", &showmipscmdlist);
4945 /* Allow the user to control the size of 32 bit registers within the
4946 raw remote packet. */
4947 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4950 (char *)&mips64_transfers_32bit_regs_p, "\
4951 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4952 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4953 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4954 64 bits for others. Use \"off\" to disable compatibility mode",
4958 /* Debug this files internals. */
4959 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
4960 &mips_debug, "Set mips debugging.\n\
4961 When non-zero, mips specific debugging is enabled.", &setdebuglist),