1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static const struct objfile_data *mips_pdr_data;
63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
65 static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch,
67 static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32);
68 static int mips16_instruction_has_delay_slot (unsigned short inst,
71 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
73 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
74 CORE_ADDR addr, int mustbe32);
75 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
76 CORE_ADDR addr, int mustbe32);
78 static void mips_print_float_info (struct gdbarch *, struct ui_file *,
79 struct frame_info *, const char *);
81 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
82 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
83 #define ST0_FR (1 << 26)
85 /* The sizes of floating point registers. */
89 MIPS_FPU_SINGLE_REGSIZE = 4,
90 MIPS_FPU_DOUBLE_REGSIZE = 8
99 static const char *mips_abi_string;
101 static const char *const mips_abi_strings[] = {
112 /* Enum describing the different kinds of breakpoints. */
114 enum mips_breakpoint_kind
116 /* 16-bit MIPS16 mode breakpoint. */
117 MIPS_BP_KIND_MIPS16 = 2,
119 /* 16-bit microMIPS mode breakpoint. */
120 MIPS_BP_KIND_MICROMIPS16 = 3,
122 /* 32-bit standard MIPS mode breakpoint. */
123 MIPS_BP_KIND_MIPS32 = 4,
125 /* 32-bit microMIPS mode breakpoint. */
126 MIPS_BP_KIND_MICROMIPS32 = 5,
129 /* For backwards compatibility we default to MIPS16. This flag is
130 overridden as soon as unambiguous ELF file flags tell us the
131 compressed ISA encoding used. */
132 static const char mips_compression_mips16[] = "mips16";
133 static const char mips_compression_micromips[] = "micromips";
134 static const char *const mips_compression_strings[] =
136 mips_compression_mips16,
137 mips_compression_micromips,
141 static const char *mips_compression_string = mips_compression_mips16;
143 /* The standard register names, and all the valid aliases for them. */
144 struct register_alias
150 /* Aliases for o32 and most other ABIs. */
151 const struct register_alias mips_o32_aliases[] = {
158 /* Aliases for n32 and n64. */
159 const struct register_alias mips_n32_n64_aliases[] = {
166 /* Aliases for ABI-independent registers. */
167 const struct register_alias mips_register_aliases[] = {
168 /* The architecture manuals specify these ABI-independent names for
170 #define R(n) { "r" #n, n }
171 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
172 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
173 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
174 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
177 /* k0 and k1 are sometimes called these instead (for "kernel
182 /* This is the traditional GDB name for the CP0 status register. */
183 { "sr", MIPS_PS_REGNUM },
185 /* This is the traditional GDB name for the CP0 BadVAddr register. */
186 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
188 /* This is the traditional GDB name for the FCSR. */
189 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
192 const struct register_alias mips_numeric_register_aliases[] = {
193 #define R(n) { #n, n }
194 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
195 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
196 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
197 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
201 #ifndef MIPS_DEFAULT_FPU_TYPE
202 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
204 static int mips_fpu_type_auto = 1;
205 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
207 static unsigned int mips_debug = 0;
209 /* Properties (for struct target_desc) describing the g/G packet
211 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
212 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
214 struct target_desc *mips_tdesc_gp32;
215 struct target_desc *mips_tdesc_gp64;
217 const struct mips_regnum *
218 mips_regnum (struct gdbarch *gdbarch)
220 return gdbarch_tdep (gdbarch)->regnum;
224 mips_fpa0_regnum (struct gdbarch *gdbarch)
226 return mips_regnum (gdbarch)->fp0 + 12;
229 /* Return 1 if REGNUM refers to a floating-point general register, raw
230 or cooked. Otherwise return 0. */
233 mips_float_register_p (struct gdbarch *gdbarch, int regnum)
235 int rawnum = regnum % gdbarch_num_regs (gdbarch);
237 return (rawnum >= mips_regnum (gdbarch)->fp0
238 && rawnum < mips_regnum (gdbarch)->fp0 + 32);
241 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
243 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
245 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
246 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
248 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
249 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
251 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
253 /* Return the MIPS ABI associated with GDBARCH. */
255 mips_abi (struct gdbarch *gdbarch)
257 return gdbarch_tdep (gdbarch)->mips_abi;
261 mips_isa_regsize (struct gdbarch *gdbarch)
263 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
265 /* If we know how big the registers are, use that size. */
266 if (tdep->register_size_valid_p)
267 return tdep->register_size;
269 /* Fall back to the previous behavior. */
270 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
271 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
274 /* Max saved register size. */
275 #define MAX_MIPS_ABI_REGSIZE 8
277 /* Return the currently configured (or set) saved register size. */
280 mips_abi_regsize (struct gdbarch *gdbarch)
282 switch (mips_abi (gdbarch))
284 case MIPS_ABI_EABI32:
290 case MIPS_ABI_EABI64:
292 case MIPS_ABI_UNKNOWN:
295 internal_error (__FILE__, __LINE__, _("bad switch"));
299 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
300 are some functions to handle addresses associated with compressed
301 code including but not limited to testing, setting, or clearing
302 bit 0 of such addresses. */
304 /* Return one iff compressed code is the MIPS16 instruction set. */
307 is_mips16_isa (struct gdbarch *gdbarch)
309 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16;
312 /* Return one iff compressed code is the microMIPS instruction set. */
315 is_micromips_isa (struct gdbarch *gdbarch)
317 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS;
320 /* Return one iff ADDR denotes compressed code. */
323 is_compact_addr (CORE_ADDR addr)
328 /* Return one iff ADDR denotes standard ISA code. */
331 is_mips_addr (CORE_ADDR addr)
333 return !is_compact_addr (addr);
336 /* Return one iff ADDR denotes MIPS16 code. */
339 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
341 return is_compact_addr (addr) && is_mips16_isa (gdbarch);
344 /* Return one iff ADDR denotes microMIPS code. */
347 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
349 return is_compact_addr (addr) && is_micromips_isa (gdbarch);
352 /* Strip the ISA (compression) bit off from ADDR. */
355 unmake_compact_addr (CORE_ADDR addr)
357 return ((addr) & ~(CORE_ADDR) 1);
360 /* Add the ISA (compression) bit to ADDR. */
363 make_compact_addr (CORE_ADDR addr)
365 return ((addr) | (CORE_ADDR) 1);
368 /* Extern version of unmake_compact_addr; we use a separate function
369 so that unmake_compact_addr can be inlined throughout this file. */
372 mips_unmake_compact_addr (CORE_ADDR addr)
374 return unmake_compact_addr (addr);
377 /* Functions for setting and testing a bit in a minimal symbol that
378 marks it as MIPS16 or microMIPS function. The MSB of the minimal
379 symbol's "info" field is used for this purpose.
381 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
382 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
383 one of the "special" bits in a minimal symbol to mark it accordingly.
384 The test checks an ELF-private flag that is valid for true function
385 symbols only; for synthetic symbols such as for PLT stubs that have
386 no ELF-private part at all the MIPS BFD backend arranges for this
387 information to be carried in the asymbol's udata field instead.
389 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
390 in a minimal symbol. */
393 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
395 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
396 unsigned char st_other;
398 if ((sym->flags & BSF_SYNTHETIC) == 0)
399 st_other = elfsym->internal_elf_sym.st_other;
400 else if ((sym->flags & BSF_FUNCTION) != 0)
401 st_other = sym->udata.i;
405 if (ELF_ST_IS_MICROMIPS (st_other))
407 MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1;
408 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
410 else if (ELF_ST_IS_MIPS16 (st_other))
412 MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1;
413 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
417 /* Return one iff MSYM refers to standard ISA code. */
420 msymbol_is_mips (struct minimal_symbol *msym)
422 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym)
423 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym));
426 /* Return one iff MSYM refers to MIPS16 code. */
429 msymbol_is_mips16 (struct minimal_symbol *msym)
431 return MSYMBOL_TARGET_FLAG_MIPS16 (msym);
434 /* Return one iff MSYM refers to microMIPS code. */
437 msymbol_is_micromips (struct minimal_symbol *msym)
439 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym);
442 /* Set the ISA bit in the main symbol too, complementing the corresponding
443 minimal symbol setting and reflecting the run-time value of the symbol.
444 The need for comes from the ISA bit having been cleared as code in
445 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
446 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
447 of symbols referring to compressed code different in GDB to the values
448 used by actual code. That in turn makes them evaluate incorrectly in
449 expressions, producing results different to what the same expressions
450 yield when compiled into the program being debugged. */
453 mips_make_symbol_special (struct symbol *sym, struct objfile *objfile)
455 if (SYMBOL_CLASS (sym) == LOC_BLOCK)
457 /* We are in symbol reading so it is OK to cast away constness. */
458 struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym);
459 CORE_ADDR compact_block_start;
460 struct bound_minimal_symbol msym;
462 compact_block_start = BLOCK_START (block) | 1;
463 msym = lookup_minimal_symbol_by_pc (compact_block_start);
464 if (msym.minsym && !msymbol_is_mips (msym.minsym))
466 BLOCK_START (block) = compact_block_start;
471 /* XFER a value from the big/little/left end of the register.
472 Depending on the size of the value it might occupy the entire
473 register or just part of it. Make an allowance for this, aligning
474 things accordingly. */
477 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
478 int reg_num, int length,
479 enum bfd_endian endian, gdb_byte *in,
480 const gdb_byte *out, int buf_offset)
484 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
485 /* Need to transfer the left or right part of the register, based on
486 the targets byte order. */
490 reg_offset = register_size (gdbarch, reg_num) - length;
492 case BFD_ENDIAN_LITTLE:
495 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
499 internal_error (__FILE__, __LINE__, _("bad switch"));
502 fprintf_unfiltered (gdb_stderr,
503 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
504 reg_num, reg_offset, buf_offset, length);
505 if (mips_debug && out != NULL)
508 fprintf_unfiltered (gdb_stdlog, "out ");
509 for (i = 0; i < length; i++)
510 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
513 regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset);
515 regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset);
516 if (mips_debug && in != NULL)
519 fprintf_unfiltered (gdb_stdlog, "in ");
520 for (i = 0; i < length; i++)
521 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
524 fprintf_unfiltered (gdb_stdlog, "\n");
527 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
528 compatiblity mode. A return value of 1 means that we have
529 physical 64-bit registers, but should treat them as 32-bit registers. */
532 mips2_fp_compat (struct frame_info *frame)
534 struct gdbarch *gdbarch = get_frame_arch (frame);
535 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
537 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
541 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
542 in all the places we deal with FP registers. PR gdb/413. */
543 /* Otherwise check the FR bit in the status register - it controls
544 the FP compatiblity mode. If it is clear we are in compatibility
546 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
553 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
555 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
557 /* The list of available "set mips " and "show mips " commands. */
559 static struct cmd_list_element *setmipscmdlist = NULL;
560 static struct cmd_list_element *showmipscmdlist = NULL;
562 /* Integer registers 0 thru 31 are handled explicitly by
563 mips_register_name(). Processor specific registers 32 and above
564 are listed in the following tables. */
567 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
571 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
572 "sr", "lo", "hi", "bad", "cause", "pc",
573 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
574 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
575 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
576 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
580 /* Names of tx39 registers. */
582 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
583 "sr", "lo", "hi", "bad", "cause", "pc",
584 "", "", "", "", "", "", "", "",
585 "", "", "", "", "", "", "", "",
586 "", "", "", "", "", "", "", "",
587 "", "", "", "", "", "", "", "",
589 "", "", "", "", "", "", "", "",
590 "", "", "config", "cache", "debug", "depc", "epc",
593 /* Names of registers with Linux kernels. */
594 static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
595 "sr", "lo", "hi", "bad", "cause", "pc",
596 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
597 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
598 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
599 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
604 /* Return the name of the register corresponding to REGNO. */
606 mips_register_name (struct gdbarch *gdbarch, int regno)
608 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
609 /* GPR names for all ABIs other than n32/n64. */
610 static const char *mips_gpr_names[] = {
611 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
612 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
613 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
614 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
617 /* GPR names for n32 and n64 ABIs. */
618 static const char *mips_n32_n64_gpr_names[] = {
619 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
620 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
621 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
622 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
625 enum mips_abi abi = mips_abi (gdbarch);
627 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
628 but then don't make the raw register names visible. This (upper)
629 range of user visible register numbers are the pseudo-registers.
631 This approach was adopted accommodate the following scenario:
632 It is possible to debug a 64-bit device using a 32-bit
633 programming model. In such instances, the raw registers are
634 configured to be 64-bits wide, while the pseudo registers are
635 configured to be 32-bits wide. The registers that the user
636 sees - the pseudo registers - match the users expectations
637 given the programming model being used. */
638 int rawnum = regno % gdbarch_num_regs (gdbarch);
639 if (regno < gdbarch_num_regs (gdbarch))
642 /* The MIPS integer registers are always mapped from 0 to 31. The
643 names of the registers (which reflects the conventions regarding
644 register use) vary depending on the ABI. */
645 if (0 <= rawnum && rawnum < 32)
647 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
648 return mips_n32_n64_gpr_names[rawnum];
650 return mips_gpr_names[rawnum];
652 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
653 return tdesc_register_name (gdbarch, rawnum);
654 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
656 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
657 if (tdep->mips_processor_reg_names[rawnum - 32])
658 return tdep->mips_processor_reg_names[rawnum - 32];
662 internal_error (__FILE__, __LINE__,
663 _("mips_register_name: bad register number %d"), rawnum);
666 /* Return the groups that a MIPS register can be categorised into. */
669 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
670 struct reggroup *reggroup)
675 int rawnum = regnum % gdbarch_num_regs (gdbarch);
676 int pseudo = regnum / gdbarch_num_regs (gdbarch);
677 if (reggroup == all_reggroup)
679 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
680 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
681 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
682 (gdbarch), as not all architectures are multi-arch. */
683 raw_p = rawnum < gdbarch_num_regs (gdbarch);
684 if (gdbarch_register_name (gdbarch, regnum) == NULL
685 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
687 if (reggroup == float_reggroup)
688 return float_p && pseudo;
689 if (reggroup == vector_reggroup)
690 return vector_p && pseudo;
691 if (reggroup == general_reggroup)
692 return (!vector_p && !float_p) && pseudo;
693 /* Save the pseudo registers. Need to make certain that any code
694 extracting register values from a saved register cache also uses
696 if (reggroup == save_reggroup)
697 return raw_p && pseudo;
698 /* Restore the same pseudo register. */
699 if (reggroup == restore_reggroup)
700 return raw_p && pseudo;
704 /* Return the groups that a MIPS register can be categorised into.
705 This version is only used if we have a target description which
706 describes real registers (and their groups). */
709 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
710 struct reggroup *reggroup)
712 int rawnum = regnum % gdbarch_num_regs (gdbarch);
713 int pseudo = regnum / gdbarch_num_regs (gdbarch);
716 /* Only save, restore, and display the pseudo registers. Need to
717 make certain that any code extracting register values from a
718 saved register cache also uses pseudo registers.
720 Note: saving and restoring the pseudo registers is slightly
721 strange; if we have 64 bits, we should save and restore all
722 64 bits. But this is hard and has little benefit. */
726 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
730 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
733 /* Map the symbol table registers which live in the range [1 *
734 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
735 registers. Take care of alignment and size problems. */
737 static enum register_status
738 mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache,
739 int cookednum, gdb_byte *buf)
741 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
742 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
743 && cookednum < 2 * gdbarch_num_regs (gdbarch));
744 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
745 return regcache->raw_read (rawnum, buf);
746 else if (register_size (gdbarch, rawnum) >
747 register_size (gdbarch, cookednum))
749 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
750 return regcache->raw_read_part (rawnum, 0, 4, buf);
753 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
755 enum register_status status;
757 status = regcache->raw_read (rawnum, ®val);
758 if (status == REG_VALID)
759 store_signed_integer (buf, 4, byte_order, regval);
764 internal_error (__FILE__, __LINE__, _("bad register size"));
768 mips_pseudo_register_write (struct gdbarch *gdbarch,
769 struct regcache *regcache, int cookednum,
772 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
773 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
774 && cookednum < 2 * gdbarch_num_regs (gdbarch));
775 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
776 regcache->raw_write (rawnum, buf);
777 else if (register_size (gdbarch, rawnum) >
778 register_size (gdbarch, cookednum))
780 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
781 regcache->raw_write_part (rawnum, 0, 4, buf);
784 /* Sign extend the shortened version of the register prior
785 to placing it in the raw register. This is required for
786 some mips64 parts in order to avoid unpredictable behavior. */
787 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
788 LONGEST regval = extract_signed_integer (buf, 4, byte_order);
789 regcache_raw_write_signed (regcache, rawnum, regval);
793 internal_error (__FILE__, __LINE__, _("bad register size"));
797 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch,
798 struct agent_expr *ax, int reg)
800 int rawnum = reg % gdbarch_num_regs (gdbarch);
801 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
802 && reg < 2 * gdbarch_num_regs (gdbarch));
804 ax_reg_mask (ax, rawnum);
810 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
811 struct agent_expr *ax, int reg)
813 int rawnum = reg % gdbarch_num_regs (gdbarch);
814 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
815 && reg < 2 * gdbarch_num_regs (gdbarch));
816 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg))
820 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg))
822 if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
823 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG)
826 ax_simple (ax, aop_lsh);
829 ax_simple (ax, aop_rsh_signed);
833 internal_error (__FILE__, __LINE__, _("bad register size"));
838 /* Table to translate 3-bit register field to actual register number. */
839 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
841 /* Heuristic_proc_start may hunt through the text section for a long
842 time across a 2400 baud serial line. Allows the user to limit this
845 static int heuristic_fence_post = 0;
847 /* Number of bytes of storage in the actual machine representation for
848 register N. NOTE: This defines the pseudo register type so need to
849 rebuild the architecture vector. */
851 static int mips64_transfers_32bit_regs_p = 0;
854 set_mips64_transfers_32bit_regs (const char *args, int from_tty,
855 struct cmd_list_element *c)
857 struct gdbarch_info info;
858 gdbarch_info_init (&info);
859 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
860 instead of relying on globals. Doing that would let generic code
861 handle the search for this specific architecture. */
862 if (!gdbarch_update_p (info))
864 mips64_transfers_32bit_regs_p = 0;
865 error (_("32-bit compatibility mode not supported"));
869 /* Convert to/from a register and the corresponding memory value. */
871 /* This predicate tests for the case of an 8 byte floating point
872 value that is being transferred to or from a pair of floating point
873 registers each of which are (or are considered to be) only 4 bytes
876 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum,
879 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
880 && register_size (gdbarch, regnum) == 4
881 && mips_float_register_p (gdbarch, regnum)
882 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
885 /* This predicate tests for the case of a value of less than 8
886 bytes in width that is being transfered to or from an 8 byte
887 general purpose register. */
889 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum,
892 int num_regs = gdbarch_num_regs (gdbarch);
894 return (register_size (gdbarch, regnum) == 8
895 && regnum % num_regs > 0 && regnum % num_regs < 32
896 && TYPE_LENGTH (type) < 8);
900 mips_convert_register_p (struct gdbarch *gdbarch,
901 int regnum, struct type *type)
903 return (mips_convert_register_float_case_p (gdbarch, regnum, type)
904 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type));
908 mips_register_to_value (struct frame_info *frame, int regnum,
909 struct type *type, gdb_byte *to,
910 int *optimizedp, int *unavailablep)
912 struct gdbarch *gdbarch = get_frame_arch (frame);
914 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
916 get_frame_register (frame, regnum + 0, to + 4);
917 get_frame_register (frame, regnum + 1, to + 0);
919 if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4,
920 optimizedp, unavailablep))
923 if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0,
924 optimizedp, unavailablep))
926 *optimizedp = *unavailablep = 0;
929 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
931 int len = TYPE_LENGTH (type);
934 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0;
935 if (!get_frame_register_bytes (frame, regnum, offset, len, to,
936 optimizedp, unavailablep))
939 *optimizedp = *unavailablep = 0;
944 internal_error (__FILE__, __LINE__,
945 _("mips_register_to_value: unrecognized case"));
950 mips_value_to_register (struct frame_info *frame, int regnum,
951 struct type *type, const gdb_byte *from)
953 struct gdbarch *gdbarch = get_frame_arch (frame);
955 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
957 put_frame_register (frame, regnum + 0, from + 4);
958 put_frame_register (frame, regnum + 1, from + 0);
960 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
963 int len = TYPE_LENGTH (type);
965 /* Sign extend values, irrespective of type, that are stored to
966 a 64-bit general purpose register. (32-bit unsigned values
967 are stored as signed quantities within a 64-bit register.
968 When performing an operation, in compiled code, that combines
969 a 32-bit unsigned value with a signed 64-bit value, a type
970 conversion is first performed that zeroes out the high 32 bits.) */
971 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
974 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1);
976 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0);
977 put_frame_register_bytes (frame, regnum, 0, 8 - len, fill);
978 put_frame_register_bytes (frame, regnum, 8 - len, len, from);
982 if (from[len-1] & 0x80)
983 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1);
985 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0);
986 put_frame_register_bytes (frame, regnum, 0, len, from);
987 put_frame_register_bytes (frame, regnum, len, 8 - len, fill);
992 internal_error (__FILE__, __LINE__,
993 _("mips_value_to_register: unrecognized case"));
997 /* Return the GDB type object for the "standard" data type of data in
1000 static struct type *
1001 mips_register_type (struct gdbarch *gdbarch, int regnum)
1003 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
1004 if (mips_float_register_p (gdbarch, regnum))
1006 /* The floating-point registers raw, or cooked, always match
1007 mips_isa_regsize(), and also map 1:1, byte for byte. */
1008 if (mips_isa_regsize (gdbarch) == 4)
1009 return builtin_type (gdbarch)->builtin_float;
1011 return builtin_type (gdbarch)->builtin_double;
1013 else if (regnum < gdbarch_num_regs (gdbarch))
1015 /* The raw or ISA registers. These are all sized according to
1017 if (mips_isa_regsize (gdbarch) == 4)
1018 return builtin_type (gdbarch)->builtin_int32;
1020 return builtin_type (gdbarch)->builtin_int64;
1024 int rawnum = regnum - gdbarch_num_regs (gdbarch);
1026 /* The cooked or ABI registers. These are sized according to
1027 the ABI (with a few complications). */
1028 if (rawnum == mips_regnum (gdbarch)->fp_control_status
1029 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision)
1030 return builtin_type (gdbarch)->builtin_int32;
1031 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
1032 && rawnum >= MIPS_FIRST_EMBED_REGNUM
1033 && rawnum <= MIPS_LAST_EMBED_REGNUM)
1034 /* The pseudo/cooked view of the embedded registers is always
1035 32-bit. The raw view is handled below. */
1036 return builtin_type (gdbarch)->builtin_int32;
1037 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
1038 /* The target, while possibly using a 64-bit register buffer,
1039 is only transfering 32-bits of each integer register.
1040 Reflect this in the cooked/pseudo (ABI) register value. */
1041 return builtin_type (gdbarch)->builtin_int32;
1042 else if (mips_abi_regsize (gdbarch) == 4)
1043 /* The ABI is restricted to 32-bit registers (the ISA could be
1045 return builtin_type (gdbarch)->builtin_int32;
1048 return builtin_type (gdbarch)->builtin_int64;
1052 /* Return the GDB type for the pseudo register REGNUM, which is the
1053 ABI-level view. This function is only called if there is a target
1054 description which includes registers, so we know precisely the
1055 types of hardware registers. */
1057 static struct type *
1058 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
1060 const int num_regs = gdbarch_num_regs (gdbarch);
1061 int rawnum = regnum % num_regs;
1062 struct type *rawtype;
1064 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
1066 /* Absent registers are still absent. */
1067 rawtype = gdbarch_register_type (gdbarch, rawnum);
1068 if (TYPE_LENGTH (rawtype) == 0)
1071 /* Present the floating point registers however the hardware did;
1072 do not try to convert between FPU layouts. */
1073 if (mips_float_register_p (gdbarch, rawnum))
1076 /* Floating-point control registers are always 32-bit even though for
1077 backwards compatibility reasons 64-bit targets will transfer them
1078 as 64-bit quantities even if using XML descriptions. */
1079 if (rawnum == mips_regnum (gdbarch)->fp_control_status
1080 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision)
1081 return builtin_type (gdbarch)->builtin_int32;
1083 /* Use pointer types for registers if we can. For n32 we can not,
1084 since we do not have a 64-bit pointer type. */
1085 if (mips_abi_regsize (gdbarch)
1086 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
1088 if (rawnum == MIPS_SP_REGNUM
1089 || rawnum == mips_regnum (gdbarch)->badvaddr)
1090 return builtin_type (gdbarch)->builtin_data_ptr;
1091 else if (rawnum == mips_regnum (gdbarch)->pc)
1092 return builtin_type (gdbarch)->builtin_func_ptr;
1095 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
1096 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM)
1097 || rawnum == mips_regnum (gdbarch)->lo
1098 || rawnum == mips_regnum (gdbarch)->hi
1099 || rawnum == mips_regnum (gdbarch)->badvaddr
1100 || rawnum == mips_regnum (gdbarch)->cause
1101 || rawnum == mips_regnum (gdbarch)->pc
1102 || (mips_regnum (gdbarch)->dspacc != -1
1103 && rawnum >= mips_regnum (gdbarch)->dspacc
1104 && rawnum < mips_regnum (gdbarch)->dspacc + 6)))
1105 return builtin_type (gdbarch)->builtin_int32;
1107 /* The pseudo/cooked view of embedded registers is always
1108 32-bit, even if the target transfers 64-bit values for them.
1109 New targets relying on XML descriptions should only transfer
1110 the necessary 32 bits, but older versions of GDB expected 64,
1111 so allow the target to provide 64 bits without interfering
1112 with the displayed type. */
1113 if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
1114 && rawnum >= MIPS_FIRST_EMBED_REGNUM
1115 && rawnum <= MIPS_LAST_EMBED_REGNUM)
1116 return builtin_type (gdbarch)->builtin_int32;
1118 /* For all other registers, pass through the hardware type. */
1122 /* Should the upper word of 64-bit addresses be zeroed? */
1123 static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
1126 mips_mask_address_p (struct gdbarch_tdep *tdep)
1128 switch (mask_address_var)
1130 case AUTO_BOOLEAN_TRUE:
1132 case AUTO_BOOLEAN_FALSE:
1135 case AUTO_BOOLEAN_AUTO:
1136 return tdep->default_mask_address_p;
1138 internal_error (__FILE__, __LINE__,
1139 _("mips_mask_address_p: bad switch"));
1145 show_mask_address (struct ui_file *file, int from_tty,
1146 struct cmd_list_element *c, const char *value)
1148 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
1150 deprecated_show_value_hack (file, from_tty, c, value);
1151 switch (mask_address_var)
1153 case AUTO_BOOLEAN_TRUE:
1154 printf_filtered ("The 32 bit mips address mask is enabled\n");
1156 case AUTO_BOOLEAN_FALSE:
1157 printf_filtered ("The 32 bit mips address mask is disabled\n");
1159 case AUTO_BOOLEAN_AUTO:
1161 ("The 32 bit address mask is set automatically. Currently %s\n",
1162 mips_mask_address_p (tdep) ? "enabled" : "disabled");
1165 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
1170 /* Tell if the program counter value in MEMADDR is in a standard ISA
1174 mips_pc_is_mips (CORE_ADDR memaddr)
1176 struct bound_minimal_symbol sym;
1178 /* Flags indicating that this is a MIPS16 or microMIPS function is
1179 stored by elfread.c in the high bit of the info field. Use this
1180 to decide if the function is standard MIPS. Otherwise if bit 0
1181 of the address is clear, then this is a standard MIPS function. */
1182 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1184 return msymbol_is_mips (sym.minsym);
1186 return is_mips_addr (memaddr);
1189 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1192 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1194 struct bound_minimal_symbol sym;
1196 /* A flag indicating that this is a MIPS16 function is stored by
1197 elfread.c in the high bit of the info field. Use this to decide
1198 if the function is MIPS16. Otherwise if bit 0 of the address is
1199 set, then ELF file flags will tell if this is a MIPS16 function. */
1200 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1202 return msymbol_is_mips16 (sym.minsym);
1204 return is_mips16_addr (gdbarch, memaddr);
1207 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1210 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1212 struct bound_minimal_symbol sym;
1214 /* A flag indicating that this is a microMIPS function is stored by
1215 elfread.c in the high bit of the info field. Use this to decide
1216 if the function is microMIPS. Otherwise if bit 0 of the address
1217 is set, then ELF file flags will tell if this is a microMIPS
1219 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1221 return msymbol_is_micromips (sym.minsym);
1223 return is_micromips_addr (gdbarch, memaddr);
1226 /* Tell the ISA type of the function the program counter value in MEMADDR
1229 static enum mips_isa
1230 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1232 struct bound_minimal_symbol sym;
1234 /* A flag indicating that this is a MIPS16 or a microMIPS function
1235 is stored by elfread.c in the high bit of the info field. Use
1236 this to decide if the function is MIPS16 or microMIPS or normal
1237 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1238 flags will tell if this is a MIPS16 or a microMIPS function. */
1239 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1242 if (msymbol_is_micromips (sym.minsym))
1243 return ISA_MICROMIPS;
1244 else if (msymbol_is_mips16 (sym.minsym))
1251 if (is_mips_addr (memaddr))
1253 else if (is_micromips_addr (gdbarch, memaddr))
1254 return ISA_MICROMIPS;
1260 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1261 The need for comes from the ISA bit having been cleared, making
1262 addresses in FDE, range records, etc. referring to compressed code
1263 different to those in line information, the symbol table and finally
1264 the PC register. That in turn confuses many operations. */
1267 mips_adjust_dwarf2_addr (CORE_ADDR pc)
1269 pc = unmake_compact_addr (pc);
1270 return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc);
1273 /* Recalculate the line record requested so that the resulting PC has
1274 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1275 this adjustment comes from some records associated with compressed
1276 code having the ISA bit cleared, most notably at function prologue
1277 ends. The ISA bit is in this context retrieved from the minimal
1278 symbol covering the address requested, which in turn has been
1279 constructed from the binary's symbol table rather than DWARF-2
1280 information. The correct setting of the ISA bit is required for
1281 breakpoint addresses to correctly match against the stop PC.
1283 As line entries can specify relative address adjustments we need to
1284 keep track of the absolute value of the last line address recorded
1285 in line information, so that we can calculate the actual address to
1286 apply the ISA bit adjustment to. We use PC for this tracking and
1287 keep the original address there.
1289 As such relative address adjustments can be odd within compressed
1290 code we need to keep track of the last line address with the ISA
1291 bit adjustment applied too, as the original address may or may not
1292 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1293 the adjusted address there.
1295 For relative address adjustments we then use these variables to
1296 calculate the address intended by line information, which will be
1297 PC-relative, and return an updated adjustment carrying ISA bit
1298 information, which will be ADJ_PC-relative. For absolute address
1299 adjustments we just return the same address that we store in ADJ_PC
1302 As the first line entry can be relative to an implied address value
1303 of 0 we need to have the initial address set up that we store in PC
1304 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1305 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1308 mips_adjust_dwarf2_line (CORE_ADDR addr, int rel)
1310 static CORE_ADDR adj_pc;
1311 static CORE_ADDR pc;
1314 pc = rel ? pc + addr : addr;
1315 isa_pc = mips_adjust_dwarf2_addr (pc);
1316 addr = rel ? isa_pc - adj_pc : isa_pc;
1321 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1323 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_";
1324 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_";
1325 static const char mips_str_call_fp_stub[] = "__call_stub_fp_";
1326 static const char mips_str_call_stub[] = "__call_stub_";
1327 static const char mips_str_fn_stub[] = "__fn_stub_";
1329 /* This is used as a PIC thunk prefix. */
1331 static const char mips_str_pic[] = ".pic.";
1333 /* Return non-zero if the PC is inside a call thunk (aka stub or
1334 trampoline) that should be treated as a temporary frame. */
1337 mips_in_frame_stub (CORE_ADDR pc)
1339 CORE_ADDR start_addr;
1342 /* Find the starting address of the function containing the PC. */
1343 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
1346 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1347 if (startswith (name, mips_str_mips16_call_stub))
1349 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1350 if (startswith (name, mips_str_call_stub))
1352 /* If the PC is in __fn_stub_*, this is a call stub. */
1353 if (startswith (name, mips_str_fn_stub))
1356 return 0; /* Not a stub. */
1359 /* MIPS believes that the PC has a sign extended value. Perhaps the
1360 all registers should be sign extended for simplicity? */
1363 mips_read_pc (readable_regcache *regcache)
1365 int regnum = gdbarch_pc_regnum (regcache->arch ());
1368 regcache->cooked_read (regnum, &pc);
1373 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1377 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch));
1378 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1379 intermediate frames. In this case we can get the caller's address
1380 from $ra, or if $ra contains an address within a thunk as well, then
1381 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1382 and thus the caller's address is in $s2. */
1383 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc))
1385 pc = frame_unwind_register_signed
1386 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
1387 if (mips_in_frame_stub (pc))
1388 pc = frame_unwind_register_signed
1389 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
1395 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1397 return frame_unwind_register_signed
1398 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
1401 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1402 dummy frame. The frame ID's base needs to match the TOS value
1403 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1406 static struct frame_id
1407 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1409 return frame_id_build
1410 (get_frame_register_signed (this_frame,
1411 gdbarch_num_regs (gdbarch)
1413 get_frame_pc (this_frame));
1416 /* Implement the "write_pc" gdbarch method. */
1419 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
1421 int regnum = gdbarch_pc_regnum (regcache->arch ());
1423 regcache_cooked_write_unsigned (regcache, regnum, pc);
1426 /* Fetch and return instruction from the specified location. Handle
1427 MIPS16/microMIPS as appropriate. */
1430 mips_fetch_instruction (struct gdbarch *gdbarch,
1431 enum mips_isa isa, CORE_ADDR addr, int *errp)
1433 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1434 gdb_byte buf[MIPS_INSN32_SIZE];
1442 instlen = MIPS_INSN16_SIZE;
1443 addr = unmake_compact_addr (addr);
1446 instlen = MIPS_INSN32_SIZE;
1449 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1452 err = target_read_memory (addr, buf, instlen);
1458 memory_error (TARGET_XFER_E_IO, addr);
1461 return extract_unsigned_integer (buf, instlen, byte_order);
1464 /* These are the fields of 32 bit mips instructions. */
1465 #define mips32_op(x) (x >> 26)
1466 #define itype_op(x) (x >> 26)
1467 #define itype_rs(x) ((x >> 21) & 0x1f)
1468 #define itype_rt(x) ((x >> 16) & 0x1f)
1469 #define itype_immediate(x) (x & 0xffff)
1471 #define jtype_op(x) (x >> 26)
1472 #define jtype_target(x) (x & 0x03ffffff)
1474 #define rtype_op(x) (x >> 26)
1475 #define rtype_rs(x) ((x >> 21) & 0x1f)
1476 #define rtype_rt(x) ((x >> 16) & 0x1f)
1477 #define rtype_rd(x) ((x >> 11) & 0x1f)
1478 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1479 #define rtype_funct(x) (x & 0x3f)
1481 /* MicroMIPS instruction fields. */
1482 #define micromips_op(x) ((x) >> 10)
1484 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1485 bit and the size respectively of the field extracted. */
1486 #define b0s4_imm(x) ((x) & 0xf)
1487 #define b0s5_imm(x) ((x) & 0x1f)
1488 #define b0s5_reg(x) ((x) & 0x1f)
1489 #define b0s7_imm(x) ((x) & 0x7f)
1490 #define b0s10_imm(x) ((x) & 0x3ff)
1491 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1492 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1493 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1494 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1495 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1496 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1497 #define b6s4_op(x) (((x) >> 6) & 0xf)
1498 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1500 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1501 respectively of the field extracted. */
1502 #define b0s6_op(x) ((x) & 0x3f)
1503 #define b0s11_op(x) ((x) & 0x7ff)
1504 #define b0s12_imm(x) ((x) & 0xfff)
1505 #define b0s16_imm(x) ((x) & 0xffff)
1506 #define b0s26_imm(x) ((x) & 0x3ffffff)
1507 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1508 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1509 #define b12s4_op(x) (((x) >> 12) & 0xf)
1511 /* Return the size in bytes of the instruction INSN encoded in the ISA
1515 mips_insn_size (enum mips_isa isa, ULONGEST insn)
1520 if ((micromips_op (insn) & 0x4) == 0x4
1521 || (micromips_op (insn) & 0x7) == 0x0)
1522 return 2 * MIPS_INSN16_SIZE;
1524 return MIPS_INSN16_SIZE;
1526 if ((insn & 0xf800) == 0xf000)
1527 return 2 * MIPS_INSN16_SIZE;
1529 return MIPS_INSN16_SIZE;
1531 return MIPS_INSN32_SIZE;
1533 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1537 mips32_relative_offset (ULONGEST inst)
1539 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
1542 /* Determine the address of the next instruction executed after the INST
1543 floating condition branch instruction at PC. COUNT specifies the
1544 number of the floating condition bits tested by the branch. */
1547 mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
1548 ULONGEST inst, CORE_ADDR pc, int count)
1550 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1551 int cnum = (itype_rt (inst) >> 2) & (count - 1);
1552 int tf = itype_rt (inst) & 1;
1553 int mask = (1 << count) - 1;
1558 /* No way to handle; it'll most likely trap anyway. */
1561 fcs = regcache_raw_get_unsigned (regcache, fcsr);
1562 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1564 if (((cond >> cnum) & mask) != mask * !tf)
1565 pc += mips32_relative_offset (inst);
1572 /* Return nonzero if the gdbarch is an Octeon series. */
1575 is_octeon (struct gdbarch *gdbarch)
1577 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
1579 return (info->mach == bfd_mach_mips_octeon
1580 || info->mach == bfd_mach_mips_octeonp
1581 || info->mach == bfd_mach_mips_octeon2);
1584 /* Return true if the OP represents the Octeon's BBIT instruction. */
1587 is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
1589 if (!is_octeon (gdbarch))
1591 /* BBIT0 is encoded as LWC2: 110 010. */
1592 /* BBIT032 is encoded as LDC2: 110 110. */
1593 /* BBIT1 is encoded as SWC2: 111 010. */
1594 /* BBIT132 is encoded as SDC2: 111 110. */
1595 if (op == 50 || op == 54 || op == 58 || op == 62)
1601 /* Determine where to set a single step breakpoint while considering
1602 branch prediction. */
1605 mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
1607 struct gdbarch *gdbarch = regcache->arch ();
1610 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
1611 op = itype_op (inst);
1612 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch
1616 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1627 goto greater_branch;
1632 else if (op == 17 && itype_rs (inst) == 8)
1633 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1634 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);
1635 else if (op == 17 && itype_rs (inst) == 9
1636 && (itype_rt (inst) & 2) == 0)
1637 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1638 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);
1639 else if (op == 17 && itype_rs (inst) == 10
1640 && (itype_rt (inst) & 2) == 0)
1641 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1642 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);
1645 /* The new PC will be alternate mode. */
1649 reg = jtype_target (inst) << 2;
1650 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1651 pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1;
1653 else if (is_octeon_bbit_op (op, gdbarch))
1657 branch_if = op == 58 || op == 62;
1658 bit = itype_rt (inst);
1660 /* Take into account the *32 instructions. */
1661 if (op == 54 || op == 62)
1664 if (((regcache_raw_get_signed (regcache,
1665 itype_rs (inst)) >> bit) & 1)
1667 pc += mips32_relative_offset (inst) + 4;
1669 pc += 8; /* After the delay slot. */
1673 pc += 4; /* Not a branch, next instruction is easy. */
1676 { /* This gets way messy. */
1678 /* Further subdivide into SPECIAL, REGIMM and other. */
1679 switch (op & 0x07) /* Extract bits 28,27,26. */
1681 case 0: /* SPECIAL */
1682 op = rtype_funct (inst);
1687 /* Set PC to that address. */
1688 pc = regcache_raw_get_signed (regcache, rtype_rs (inst));
1690 case 12: /* SYSCALL */
1692 struct gdbarch_tdep *tdep;
1694 tdep = gdbarch_tdep (gdbarch);
1695 if (tdep->syscall_next_pc != NULL)
1696 pc = tdep->syscall_next_pc (get_current_frame ());
1705 break; /* end SPECIAL */
1706 case 1: /* REGIMM */
1708 op = itype_rt (inst); /* branch condition */
1713 case 16: /* BLTZAL */
1714 case 18: /* BLTZALL */
1716 if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)
1717 pc += mips32_relative_offset (inst) + 4;
1719 pc += 8; /* after the delay slot */
1723 case 17: /* BGEZAL */
1724 case 19: /* BGEZALL */
1725 if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0)
1726 pc += mips32_relative_offset (inst) + 4;
1728 pc += 8; /* after the delay slot */
1730 case 0x1c: /* BPOSGE32 */
1731 case 0x1e: /* BPOSGE64 */
1733 if (itype_rs (inst) == 0)
1735 unsigned int pos = (op & 2) ? 64 : 32;
1736 int dspctl = mips_regnum (gdbarch)->dspctl;
1739 /* No way to handle; it'll most likely trap anyway. */
1742 if ((regcache_raw_get_unsigned (regcache,
1743 dspctl) & 0x7f) >= pos)
1744 pc += mips32_relative_offset (inst);
1749 /* All of the other instructions in the REGIMM category */
1754 break; /* end REGIMM */
1759 reg = jtype_target (inst) << 2;
1760 /* Upper four bits get never changed... */
1761 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1764 case 4: /* BEQ, BEQL */
1766 if (regcache_raw_get_signed (regcache, itype_rs (inst)) ==
1767 regcache_raw_get_signed (regcache, itype_rt (inst)))
1768 pc += mips32_relative_offset (inst) + 4;
1772 case 5: /* BNE, BNEL */
1774 if (regcache_raw_get_signed (regcache, itype_rs (inst)) !=
1775 regcache_raw_get_signed (regcache, itype_rt (inst)))
1776 pc += mips32_relative_offset (inst) + 4;
1780 case 6: /* BLEZ, BLEZL */
1781 if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0)
1782 pc += mips32_relative_offset (inst) + 4;
1788 greater_branch: /* BGTZ, BGTZL */
1789 if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)
1790 pc += mips32_relative_offset (inst) + 4;
1797 } /* mips32_next_pc */
1799 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1803 micromips_relative_offset7 (ULONGEST insn)
1805 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1;
1808 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1812 micromips_relative_offset10 (ULONGEST insn)
1814 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1;
1817 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1821 micromips_relative_offset16 (ULONGEST insn)
1823 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1;
1826 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1829 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc)
1833 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1834 return mips_insn_size (ISA_MICROMIPS, insn);
1837 /* Calculate the address of the next microMIPS instruction to execute
1838 after the INSN coprocessor 1 conditional branch instruction at the
1839 address PC. COUNT denotes the number of coprocessor condition bits
1840 examined by the branch. */
1843 micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
1844 ULONGEST insn, CORE_ADDR pc, int count)
1846 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1847 int cnum = b2s3_cc (insn >> 16) & (count - 1);
1848 int tf = b5s5_op (insn >> 16) & 1;
1849 int mask = (1 << count) - 1;
1854 /* No way to handle; it'll most likely trap anyway. */
1857 fcs = regcache_raw_get_unsigned (regcache, fcsr);
1858 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1860 if (((cond >> cnum) & mask) != mask * !tf)
1861 pc += micromips_relative_offset16 (insn);
1863 pc += micromips_pc_insn_size (gdbarch, pc);
1868 /* Calculate the address of the next microMIPS instruction to execute
1869 after the instruction at the address PC. */
1872 micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
1874 struct gdbarch *gdbarch = regcache->arch ();
1877 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1878 pc += MIPS_INSN16_SIZE;
1879 switch (mips_insn_size (ISA_MICROMIPS, insn))
1881 /* 32-bit instructions. */
1882 case 2 * MIPS_INSN16_SIZE:
1884 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1885 pc += MIPS_INSN16_SIZE;
1886 switch (micromips_op (insn >> 16))
1888 case 0x00: /* POOL32A: bits 000000 */
1889 if (b0s6_op (insn) == 0x3c
1890 /* POOL32Axf: bits 000000 ... 111100 */
1891 && (b6s10_ext (insn) & 0x2bf) == 0x3c)
1892 /* JALR, JALR.HB: 000000 000x111100 111100 */
1893 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1894 pc = regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16));
1897 case 0x10: /* POOL32I: bits 010000 */
1898 switch (b5s5_op (insn >> 16))
1900 case 0x00: /* BLTZ: bits 010000 00000 */
1901 case 0x01: /* BLTZAL: bits 010000 00001 */
1902 case 0x11: /* BLTZALS: bits 010000 10001 */
1903 if (regcache_raw_get_signed (regcache,
1904 b0s5_reg (insn >> 16)) < 0)
1905 pc += micromips_relative_offset16 (insn);
1907 pc += micromips_pc_insn_size (gdbarch, pc);
1910 case 0x02: /* BGEZ: bits 010000 00010 */
1911 case 0x03: /* BGEZAL: bits 010000 00011 */
1912 case 0x13: /* BGEZALS: bits 010000 10011 */
1913 if (regcache_raw_get_signed (regcache,
1914 b0s5_reg (insn >> 16)) >= 0)
1915 pc += micromips_relative_offset16 (insn);
1917 pc += micromips_pc_insn_size (gdbarch, pc);
1920 case 0x04: /* BLEZ: bits 010000 00100 */
1921 if (regcache_raw_get_signed (regcache,
1922 b0s5_reg (insn >> 16)) <= 0)
1923 pc += micromips_relative_offset16 (insn);
1925 pc += micromips_pc_insn_size (gdbarch, pc);
1928 case 0x05: /* BNEZC: bits 010000 00101 */
1929 if (regcache_raw_get_signed (regcache,
1930 b0s5_reg (insn >> 16)) != 0)
1931 pc += micromips_relative_offset16 (insn);
1934 case 0x06: /* BGTZ: bits 010000 00110 */
1935 if (regcache_raw_get_signed (regcache,
1936 b0s5_reg (insn >> 16)) > 0)
1937 pc += micromips_relative_offset16 (insn);
1939 pc += micromips_pc_insn_size (gdbarch, pc);
1942 case 0x07: /* BEQZC: bits 010000 00111 */
1943 if (regcache_raw_get_signed (regcache,
1944 b0s5_reg (insn >> 16)) == 0)
1945 pc += micromips_relative_offset16 (insn);
1948 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1949 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1950 if (((insn >> 16) & 0x3) == 0x0)
1951 /* BC2F, BC2T: don't know how to handle these. */
1955 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1956 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1958 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64;
1959 int dspctl = mips_regnum (gdbarch)->dspctl;
1962 /* No way to handle; it'll most likely trap anyway. */
1965 if ((regcache_raw_get_unsigned (regcache,
1966 dspctl) & 0x7f) >= pos)
1967 pc += micromips_relative_offset16 (insn);
1969 pc += micromips_pc_insn_size (gdbarch, pc);
1973 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1974 /* BC1ANY2F: bits 010000 11100 xxx01 */
1975 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1976 /* BC1ANY2T: bits 010000 11101 xxx01 */
1977 if (((insn >> 16) & 0x2) == 0x0)
1978 pc = micromips_bc1_pc (gdbarch, regcache, insn, pc,
1979 ((insn >> 16) & 0x1) + 1);
1982 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1983 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1984 if (((insn >> 16) & 0x3) == 0x1)
1985 pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4);
1990 case 0x1d: /* JALS: bits 011101 */
1991 case 0x35: /* J: bits 110101 */
1992 case 0x3d: /* JAL: bits 111101 */
1993 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1);
1996 case 0x25: /* BEQ: bits 100101 */
1997 if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
1998 == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
1999 pc += micromips_relative_offset16 (insn);
2001 pc += micromips_pc_insn_size (gdbarch, pc);
2004 case 0x2d: /* BNE: bits 101101 */
2005 if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
2006 != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
2007 pc += micromips_relative_offset16 (insn);
2009 pc += micromips_pc_insn_size (gdbarch, pc);
2012 case 0x3c: /* JALX: bits 111100 */
2013 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2);
2018 /* 16-bit instructions. */
2019 case MIPS_INSN16_SIZE:
2020 switch (micromips_op (insn))
2022 case 0x11: /* POOL16C: bits 010001 */
2023 if ((b5s5_op (insn) & 0x1c) == 0xc)
2024 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2025 pc = regcache_raw_get_signed (regcache, b0s5_reg (insn));
2026 else if (b5s5_op (insn) == 0x18)
2027 /* JRADDIUSP: bits 010001 11000 */
2028 pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM);
2031 case 0x23: /* BEQZ16: bits 100011 */
2033 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
2035 if (regcache_raw_get_signed (regcache, rs) == 0)
2036 pc += micromips_relative_offset7 (insn);
2038 pc += micromips_pc_insn_size (gdbarch, pc);
2042 case 0x2b: /* BNEZ16: bits 101011 */
2044 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
2046 if (regcache_raw_get_signed (regcache, rs) != 0)
2047 pc += micromips_relative_offset7 (insn);
2049 pc += micromips_pc_insn_size (gdbarch, pc);
2053 case 0x33: /* B16: bits 110011 */
2054 pc += micromips_relative_offset10 (insn);
2063 /* Decoding the next place to set a breakpoint is irregular for the
2064 mips 16 variant, but fortunately, there fewer instructions. We have
2065 to cope ith extensions for 16 bit instructions and a pair of actual
2066 32 bit instructions. We dont want to set a single step instruction
2067 on the extend instruction either. */
2069 /* Lots of mips16 instruction formats */
2070 /* Predicting jumps requires itype,ritype,i8type
2071 and their extensions extItype,extritype,extI8type. */
2072 enum mips16_inst_fmts
2074 itype, /* 0 immediate 5,10 */
2075 ritype, /* 1 5,3,8 */
2076 rrtype, /* 2 5,3,3,5 */
2077 rritype, /* 3 5,3,3,5 */
2078 rrrtype, /* 4 5,3,3,3,2 */
2079 rriatype, /* 5 5,3,3,1,4 */
2080 shifttype, /* 6 5,3,3,3,2 */
2081 i8type, /* 7 5,3,8 */
2082 i8movtype, /* 8 5,3,3,5 */
2083 i8mov32rtype, /* 9 5,3,5,3 */
2084 i64type, /* 10 5,3,8 */
2085 ri64type, /* 11 5,3,3,5 */
2086 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
2087 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2088 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
2089 extRRItype, /* 15 5,5,5,5,3,3,5 */
2090 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
2091 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2092 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
2093 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
2094 extRi64type, /* 20 5,6,5,5,3,3,5 */
2095 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2097 /* I am heaping all the fields of the formats into one structure and
2098 then, only the fields which are involved in instruction extension. */
2102 unsigned int regx; /* Function in i8 type. */
2107 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2108 for the bits which make up the immediate extension. */
2111 extended_offset (unsigned int extension)
2115 value = (extension >> 16) & 0x1f; /* Extract 15:11. */
2117 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */
2119 value |= extension & 0x1f; /* Extract 4:0. */
2124 /* Only call this function if you know that this is an extendable
2125 instruction. It won't malfunction, but why make excess remote memory
2126 references? If the immediate operands get sign extended or something,
2127 do it after the extension is performed. */
2128 /* FIXME: Every one of these cases needs to worry about sign extension
2129 when the offset is to be used in relative addressing. */
2132 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc)
2134 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2137 pc = unmake_compact_addr (pc); /* Clear the low order bit. */
2138 target_read_memory (pc, buf, 2);
2139 return extract_unsigned_integer (buf, 2, byte_order);
2143 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc,
2144 unsigned int extension,
2146 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
2151 switch (insn_format)
2158 value = extended_offset ((extension << 16) | inst);
2159 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2163 value = inst & 0x7ff;
2164 value = (value ^ 0x400) - 0x400; /* Sign-extend. */
2173 { /* A register identifier and an offset. */
2174 /* Most of the fields are the same as I type but the
2175 immediate value is of a different length. */
2179 value = extended_offset ((extension << 16) | inst);
2180 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2184 value = inst & 0xff; /* 8 bits */
2185 value = (value ^ 0x80) - 0x80; /* Sign-extend. */
2188 regx = (inst >> 8) & 0x07; /* i8 funct */
2194 unsigned long value;
2195 unsigned int nexthalf;
2196 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
2197 value = value << 16;
2198 nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL);
2199 /* Low bit still set. */
2207 internal_error (__FILE__, __LINE__, _("bad switch"));
2209 upk->offset = offset;
2215 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2216 and having a signed 16-bit OFFSET. */
2219 add_offset_16 (CORE_ADDR pc, int offset)
2221 return pc + (offset << 1) + 2;
2225 extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc,
2226 unsigned int extension, unsigned int insn)
2228 struct gdbarch *gdbarch = regcache->arch ();
2229 int op = (insn >> 11);
2232 case 2: /* Branch */
2234 struct upk_mips16 upk;
2235 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk);
2236 pc = add_offset_16 (pc, upk.offset);
2239 case 3: /* JAL , JALX - Watch out, these are 32 bit
2242 struct upk_mips16 upk;
2243 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk);
2244 pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2);
2245 if ((insn >> 10) & 0x01) /* Exchange mode */
2246 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */
2253 struct upk_mips16 upk;
2255 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2256 reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]);
2258 pc = add_offset_16 (pc, upk.offset);
2265 struct upk_mips16 upk;
2267 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2268 reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]);
2270 pc = add_offset_16 (pc, upk.offset);
2275 case 12: /* I8 Formats btez btnez */
2277 struct upk_mips16 upk;
2279 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
2280 /* upk.regx contains the opcode */
2281 /* Test register is 24 */
2282 reg = regcache_raw_get_signed (regcache, 24);
2283 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
2284 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
2285 pc = add_offset_16 (pc, upk.offset);
2290 case 29: /* RR Formats JR, JALR, JALR-RA */
2292 struct upk_mips16 upk;
2293 /* upk.fmt = rrtype; */
2298 upk.regx = (insn >> 8) & 0x07;
2299 upk.regy = (insn >> 5) & 0x07;
2300 if ((upk.regy & 1) == 0)
2301 reg = mips_reg3_to_reg[upk.regx];
2303 reg = 31; /* Function return instruction. */
2304 pc = regcache_raw_get_signed (regcache, reg);
2311 /* This is an instruction extension. Fetch the real instruction
2312 (which follows the extension) and decode things based on
2316 pc = extended_mips16_next_pc (regcache, pc, insn,
2317 fetch_mips_16 (gdbarch, pc));
2330 mips16_next_pc (struct regcache *regcache, CORE_ADDR pc)
2332 struct gdbarch *gdbarch = regcache->arch ();
2333 unsigned int insn = fetch_mips_16 (gdbarch, pc);
2334 return extended_mips16_next_pc (regcache, pc, 0, insn);
2337 /* The mips_next_pc function supports single_step when the remote
2338 target monitor or stub is not developed enough to do a single_step.
2339 It works by decoding the current instruction and predicting where a
2340 branch will go. This isn't hard because all the data is available.
2341 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2343 mips_next_pc (struct regcache *regcache, CORE_ADDR pc)
2345 struct gdbarch *gdbarch = regcache->arch ();
2347 if (mips_pc_is_mips16 (gdbarch, pc))
2348 return mips16_next_pc (regcache, pc);
2349 else if (mips_pc_is_micromips (gdbarch, pc))
2350 return micromips_next_pc (regcache, pc);
2352 return mips32_next_pc (regcache, pc);
2355 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2359 mips16_instruction_is_compact_branch (unsigned short insn)
2361 switch (insn & 0xf800)
2364 return (insn & 0x009f) == 0x80; /* JALRC/JRC */
2366 return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */
2367 case 0x2800: /* BNEZ */
2368 case 0x2000: /* BEQZ */
2369 case 0x1000: /* B */
2376 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2380 micromips_instruction_is_compact_branch (unsigned short insn)
2382 switch (micromips_op (insn))
2384 case 0x11: /* POOL16C: bits 010001 */
2385 return (b5s5_op (insn) == 0x18
2386 /* JRADDIUSP: bits 010001 11000 */
2387 || b5s5_op (insn) == 0xd);
2388 /* JRC: bits 010011 01101 */
2389 case 0x10: /* POOL32I: bits 010000 */
2390 return (b5s5_op (insn) & 0x1d) == 0x5;
2391 /* BEQZC/BNEZC: bits 010000 001x1 */
2397 struct mips_frame_cache
2400 struct trad_frame_saved_reg *saved_regs;
2403 /* Set a register's saved stack address in temp_saved_regs. If an
2404 address has already been set for this register, do nothing; this
2405 way we will only recognize the first save of a given register in a
2408 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2409 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2410 Strictly speaking, only the second range is used as it is only second
2411 range (the ABI instead of ISA registers) that comes into play when finding
2412 saved registers in a frame. */
2415 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
2416 int regnum, CORE_ADDR offset)
2418 if (this_cache != NULL
2419 && this_cache->saved_regs[regnum].addr == -1)
2421 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
2423 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
2429 /* Fetch the immediate value from a MIPS16 instruction.
2430 If the previous instruction was an EXTEND, use it to extend
2431 the upper bits of the immediate value. This is a helper function
2432 for mips16_scan_prologue. */
2435 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
2436 unsigned short inst, /* current instruction */
2437 int nbits, /* number of bits in imm field */
2438 int scale, /* scale factor to be applied to imm */
2439 int is_signed) /* is the imm field signed? */
2443 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2445 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
2446 if (offset & 0x8000) /* check for negative extend */
2447 offset = 0 - (0x10000 - (offset & 0xffff));
2448 return offset | (inst & 0x1f);
2452 int max_imm = 1 << nbits;
2453 int mask = max_imm - 1;
2454 int sign_bit = max_imm >> 1;
2456 offset = inst & mask;
2457 if (is_signed && (offset & sign_bit))
2458 offset = 0 - (max_imm - offset);
2459 return offset * scale;
2464 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2465 the associated FRAME_CACHE if not null.
2466 Return the address of the first instruction past the prologue. */
2469 mips16_scan_prologue (struct gdbarch *gdbarch,
2470 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2471 struct frame_info *this_frame,
2472 struct mips_frame_cache *this_cache)
2474 int prev_non_prologue_insn = 0;
2475 int this_non_prologue_insn;
2476 int non_prologue_insns = 0;
2479 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */
2481 long frame_offset = 0; /* Size of stack frame. */
2482 long frame_adjust = 0; /* Offset of FP from SP. */
2483 int frame_reg = MIPS_SP_REGNUM;
2484 unsigned short prev_inst = 0; /* saved copy of previous instruction. */
2485 unsigned inst = 0; /* current instruction */
2486 unsigned entry_inst = 0; /* the entry instruction */
2487 unsigned save_inst = 0; /* the save instruction */
2488 int prev_delay_slot = 0;
2492 int extend_bytes = 0;
2493 int prev_extend_bytes = 0;
2494 CORE_ADDR end_prologue_addr;
2496 /* Can be called when there's no process, and hence when there's no
2498 if (this_frame != NULL)
2499 sp = get_frame_register_signed (this_frame,
2500 gdbarch_num_regs (gdbarch)
2505 if (limit_pc > start_pc + 200)
2506 limit_pc = start_pc + 200;
2509 /* Permit at most one non-prologue non-control-transfer instruction
2510 in the middle which may have been reordered by the compiler for
2512 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
2514 this_non_prologue_insn = 0;
2517 /* Save the previous instruction. If it's an EXTEND, we'll extract
2518 the immediate offset extension from it in mips16_get_imm. */
2521 /* Fetch and decode the instruction. */
2522 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16,
2525 /* Normally we ignore extend instructions. However, if it is
2526 not followed by a valid prologue instruction, then this
2527 instruction is not part of the prologue either. We must
2528 remember in this case to adjust the end_prologue_addr back
2530 if ((inst & 0xf800) == 0xf000) /* extend */
2532 extend_bytes = MIPS_INSN16_SIZE;
2536 prev_extend_bytes = extend_bytes;
2539 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2540 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2542 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2543 if (offset < 0) /* Negative stack adjustment? */
2544 frame_offset -= offset;
2546 /* Exit loop if a positive stack adjustment is found, which
2547 usually means that the stack cleanup code in the function
2548 epilogue is reached. */
2551 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2553 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2554 reg = mips_reg3_to_reg[(inst & 0x700) >> 8];
2555 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2557 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2559 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2560 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2561 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2563 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2565 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2566 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2568 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2570 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2571 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2573 else if (inst == 0x673d) /* move $s1, $sp */
2578 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2580 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2581 frame_addr = sp + offset;
2583 frame_adjust = offset;
2585 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2587 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2588 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2589 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2591 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2593 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2594 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2595 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2597 else if ((inst & 0xf81f) == 0xe809
2598 && (inst & 0x700) != 0x700) /* entry */
2599 entry_inst = inst; /* Save for later processing. */
2600 else if ((inst & 0xff80) == 0x6480) /* save */
2602 save_inst = inst; /* Save for later processing. */
2603 if (prev_extend_bytes) /* extend */
2604 save_inst |= prev_inst << 16;
2606 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2608 /* This instruction is part of the prologue, but we don't
2609 need to do anything special to handle it. */
2611 else if (mips16_instruction_has_delay_slot (inst, 0))
2612 /* JAL/JALR/JALX/JR */
2614 /* The instruction in the delay slot can be a part
2615 of the prologue, so move forward once more. */
2617 if (mips16_instruction_has_delay_slot (inst, 1))
2620 prev_extend_bytes = MIPS_INSN16_SIZE;
2621 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
2626 this_non_prologue_insn = 1;
2629 non_prologue_insns += this_non_prologue_insn;
2631 /* A jump or branch, or enough non-prologue insns seen? If so,
2632 then we must have reached the end of the prologue by now. */
2633 if (prev_delay_slot || non_prologue_insns > 1
2634 || mips16_instruction_is_compact_branch (inst))
2637 prev_non_prologue_insn = this_non_prologue_insn;
2638 prev_delay_slot = in_delay_slot;
2639 prev_pc = cur_pc - prev_extend_bytes;
2642 /* The entry instruction is typically the first instruction in a function,
2643 and it stores registers at offsets relative to the value of the old SP
2644 (before the prologue). But the value of the sp parameter to this
2645 function is the new SP (after the prologue has been executed). So we
2646 can't calculate those offsets until we've seen the entire prologue,
2647 and can calculate what the old SP must have been. */
2648 if (entry_inst != 0)
2650 int areg_count = (entry_inst >> 8) & 7;
2651 int sreg_count = (entry_inst >> 6) & 3;
2653 /* The entry instruction always subtracts 32 from the SP. */
2656 /* Now we can calculate what the SP must have been at the
2657 start of the function prologue. */
2660 /* Check if a0-a3 were saved in the caller's argument save area. */
2661 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2663 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2664 offset += mips_abi_regsize (gdbarch);
2667 /* Check if the ra register was pushed on the stack. */
2669 if (entry_inst & 0x20)
2671 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2672 offset -= mips_abi_regsize (gdbarch);
2675 /* Check if the s0 and s1 registers were pushed on the stack. */
2676 for (reg = 16; reg < sreg_count + 16; reg++)
2678 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2679 offset -= mips_abi_regsize (gdbarch);
2683 /* The SAVE instruction is similar to ENTRY, except that defined by the
2684 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2685 size of the frame is specified as an immediate field of instruction
2686 and an extended variation exists which lets additional registers and
2687 frame space to be specified. The instruction always treats registers
2688 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2689 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
2691 static int args_table[16] = {
2692 0, 0, 0, 0, 1, 1, 1, 1,
2693 2, 2, 2, 0, 3, 3, 4, -1,
2695 static int astatic_table[16] = {
2696 0, 1, 2, 3, 0, 1, 2, 3,
2697 0, 1, 2, 4, 0, 1, 0, -1,
2699 int aregs = (save_inst >> 16) & 0xf;
2700 int xsregs = (save_inst >> 24) & 0x7;
2701 int args = args_table[aregs];
2702 int astatic = astatic_table[aregs];
2707 warning (_("Invalid number of argument registers encoded in SAVE."));
2712 warning (_("Invalid number of static registers encoded in SAVE."));
2716 /* For standard SAVE the frame size of 0 means 128. */
2717 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
2718 if (frame_size == 0 && (save_inst >> 16) == 0)
2721 frame_offset += frame_size;
2723 /* Now we can calculate what the SP must have been at the
2724 start of the function prologue. */
2727 /* Check if A0-A3 were saved in the caller's argument save area. */
2728 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
2730 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2731 offset += mips_abi_regsize (gdbarch);
2736 /* Check if the RA register was pushed on the stack. */
2737 if (save_inst & 0x40)
2739 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2740 offset -= mips_abi_regsize (gdbarch);
2743 /* Check if the S8 register was pushed on the stack. */
2746 set_reg_offset (gdbarch, this_cache, 30, sp + offset);
2747 offset -= mips_abi_regsize (gdbarch);
2750 /* Check if S2-S7 were pushed on the stack. */
2751 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
2753 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2754 offset -= mips_abi_regsize (gdbarch);
2757 /* Check if the S1 register was pushed on the stack. */
2758 if (save_inst & 0x10)
2760 set_reg_offset (gdbarch, this_cache, 17, sp + offset);
2761 offset -= mips_abi_regsize (gdbarch);
2763 /* Check if the S0 register was pushed on the stack. */
2764 if (save_inst & 0x20)
2766 set_reg_offset (gdbarch, this_cache, 16, sp + offset);
2767 offset -= mips_abi_regsize (gdbarch);
2770 /* Check if A0-A3 were pushed on the stack. */
2771 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
2773 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2774 offset -= mips_abi_regsize (gdbarch);
2778 if (this_cache != NULL)
2781 (get_frame_register_signed (this_frame,
2782 gdbarch_num_regs (gdbarch) + frame_reg)
2783 + frame_offset - frame_adjust);
2784 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2785 be able to get rid of the assignment below, evetually. But it's
2786 still needed for now. */
2787 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2788 + mips_regnum (gdbarch)->pc]
2789 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
2792 /* Set end_prologue_addr to the address of the instruction immediately
2793 after the last one we scanned. Unless the last one looked like a
2794 non-prologue instruction (and we looked ahead), in which case use
2795 its address instead. */
2796 end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot
2797 ? prev_pc : cur_pc - prev_extend_bytes);
2799 return end_prologue_addr;
2802 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2803 Procedures that use the 32-bit instruction set are handled by the
2804 mips_insn32 unwinder. */
2806 static struct mips_frame_cache *
2807 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
2809 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2810 struct mips_frame_cache *cache;
2812 if ((*this_cache) != NULL)
2813 return (struct mips_frame_cache *) (*this_cache);
2814 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2815 (*this_cache) = cache;
2816 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2818 /* Analyze the function prologue. */
2820 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2821 CORE_ADDR start_addr;
2823 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2824 if (start_addr == 0)
2825 start_addr = heuristic_proc_start (gdbarch, pc);
2826 /* We can't analyze the prologue if we couldn't find the begining
2828 if (start_addr == 0)
2831 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame,
2832 (struct mips_frame_cache *) *this_cache);
2835 /* gdbarch_sp_regnum contains the value and not the address. */
2836 trad_frame_set_value (cache->saved_regs,
2837 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
2840 return (struct mips_frame_cache *) (*this_cache);
2844 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
2845 struct frame_id *this_id)
2847 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2849 /* This marks the outermost frame. */
2850 if (info->base == 0)
2852 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2855 static struct value *
2856 mips_insn16_frame_prev_register (struct frame_info *this_frame,
2857 void **this_cache, int regnum)
2859 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2861 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2865 mips_insn16_frame_sniffer (const struct frame_unwind *self,
2866 struct frame_info *this_frame, void **this_cache)
2868 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2869 CORE_ADDR pc = get_frame_pc (this_frame);
2870 if (mips_pc_is_mips16 (gdbarch, pc))
2875 static const struct frame_unwind mips_insn16_frame_unwind =
2878 default_frame_unwind_stop_reason,
2879 mips_insn16_frame_this_id,
2880 mips_insn16_frame_prev_register,
2882 mips_insn16_frame_sniffer
2886 mips_insn16_frame_base_address (struct frame_info *this_frame,
2889 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2894 static const struct frame_base mips_insn16_frame_base =
2896 &mips_insn16_frame_unwind,
2897 mips_insn16_frame_base_address,
2898 mips_insn16_frame_base_address,
2899 mips_insn16_frame_base_address
2902 static const struct frame_base *
2903 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
2905 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2906 CORE_ADDR pc = get_frame_pc (this_frame);
2907 if (mips_pc_is_mips16 (gdbarch, pc))
2908 return &mips_insn16_frame_base;
2913 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2914 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2915 interpreted directly, and then multiplied by 4. */
2918 micromips_decode_imm9 (int imm)
2920 imm = (imm ^ 0x100) - 0x100;
2921 if (imm > -3 && imm < 2)
2926 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2927 the address of the first instruction past the prologue. */
2930 micromips_scan_prologue (struct gdbarch *gdbarch,
2931 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2932 struct frame_info *this_frame,
2933 struct mips_frame_cache *this_cache)
2935 CORE_ADDR end_prologue_addr;
2936 int prev_non_prologue_insn = 0;
2937 int frame_reg = MIPS_SP_REGNUM;
2938 int this_non_prologue_insn;
2939 int non_prologue_insns = 0;
2940 long frame_offset = 0; /* Size of stack frame. */
2941 long frame_adjust = 0; /* Offset of FP from SP. */
2942 int prev_delay_slot = 0;
2946 ULONGEST insn; /* current instruction */
2950 long v1_off = 0; /* The assumption is LUI will replace it. */
2961 /* Can be called when there's no process, and hence when there's no
2963 if (this_frame != NULL)
2964 sp = get_frame_register_signed (this_frame,
2965 gdbarch_num_regs (gdbarch)
2970 if (limit_pc > start_pc + 200)
2971 limit_pc = start_pc + 200;
2974 /* Permit at most one non-prologue non-control-transfer instruction
2975 in the middle which may have been reordered by the compiler for
2977 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc)
2979 this_non_prologue_insn = 0;
2983 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL);
2984 loc += MIPS_INSN16_SIZE;
2985 switch (mips_insn_size (ISA_MICROMIPS, insn))
2987 /* 32-bit instructions. */
2988 case 2 * MIPS_INSN16_SIZE:
2990 insn |= mips_fetch_instruction (gdbarch,
2991 ISA_MICROMIPS, cur_pc + loc, NULL);
2992 loc += MIPS_INSN16_SIZE;
2993 switch (micromips_op (insn >> 16))
2995 /* Record $sp/$fp adjustment. */
2996 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2997 case 0x0: /* POOL32A: bits 000000 */
2998 case 0x16: /* POOL32S: bits 010110 */
2999 op = b0s11_op (insn);
3000 sreg = b0s5_reg (insn >> 16);
3001 treg = b5s5_reg (insn >> 16);
3002 dreg = b11s5_reg (insn);
3004 /* SUBU: bits 000000 00111010000 */
3005 /* DSUBU: bits 010110 00111010000 */
3006 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM
3008 /* (D)SUBU $sp, $v1 */
3010 else if (op != 0x150
3011 /* ADDU: bits 000000 00101010000 */
3012 /* DADDU: bits 010110 00101010000 */
3013 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM)
3014 this_non_prologue_insn = 1;
3017 case 0x8: /* POOL32B: bits 001000 */
3018 op = b12s4_op (insn);
3019 breg = b0s5_reg (insn >> 16);
3020 reglist = sreg = b5s5_reg (insn >> 16);
3021 offset = (b0s12_imm (insn) ^ 0x800) - 0x800;
3022 if ((op == 0x9 || op == 0xc)
3023 /* SWP: bits 001000 1001 */
3024 /* SDP: bits 001000 1100 */
3025 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM)
3026 /* S[DW]P reg,offset($sp) */
3028 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4);
3029 set_reg_offset (gdbarch, this_cache,
3031 set_reg_offset (gdbarch, this_cache,
3032 sreg + 1, sp + offset + s);
3034 else if ((op == 0xd || op == 0xf)
3035 /* SWM: bits 001000 1101 */
3036 /* SDM: bits 001000 1111 */
3037 && breg == MIPS_SP_REGNUM
3038 /* SWM reglist,offset($sp) */
3039 && ((reglist >= 1 && reglist <= 9)
3040 || (reglist >= 16 && reglist <= 25)))
3042 int sreglist = std::min(reglist & 0xf, 8);
3044 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2);
3045 for (i = 0; i < sreglist; i++)
3046 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i);
3047 if ((reglist & 0xf) > 8)
3048 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++);
3049 if ((reglist & 0x10) == 0x10)
3050 set_reg_offset (gdbarch, this_cache,
3051 MIPS_RA_REGNUM, sp + s * i++);
3054 this_non_prologue_insn = 1;
3057 /* Record $sp/$fp adjustment. */
3058 /* Discard (D)ADDIU $gp used for PIC code. */
3059 case 0xc: /* ADDIU: bits 001100 */
3060 case 0x17: /* DADDIU: bits 010111 */
3061 sreg = b0s5_reg (insn >> 16);
3062 dreg = b5s5_reg (insn >> 16);
3063 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
3064 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM)
3065 /* (D)ADDIU $sp, imm */
3067 else if (sreg == MIPS_SP_REGNUM && dreg == 30)
3068 /* (D)ADDIU $fp, $sp, imm */
3070 frame_adjust = offset;
3073 else if (sreg != 28 || dreg != 28)
3074 /* (D)ADDIU $gp, imm */
3075 this_non_prologue_insn = 1;
3078 /* LUI $v1 is used for larger $sp adjustments. */
3079 /* Discard LUI $gp used for PIC code. */
3080 case 0x10: /* POOL32I: bits 010000 */
3081 if (b5s5_op (insn >> 16) == 0xd
3082 /* LUI: bits 010000 001101 */
3083 && b0s5_reg (insn >> 16) == 3)
3085 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000;
3086 else if (b5s5_op (insn >> 16) != 0xd
3087 /* LUI: bits 010000 001101 */
3088 || b0s5_reg (insn >> 16) != 28)
3090 this_non_prologue_insn = 1;
3093 /* ORI $v1 is used for larger $sp adjustments. */
3094 case 0x14: /* ORI: bits 010100 */
3095 sreg = b0s5_reg (insn >> 16);
3096 dreg = b5s5_reg (insn >> 16);
3097 if (sreg == 3 && dreg == 3)
3099 v1_off |= b0s16_imm (insn);
3101 this_non_prologue_insn = 1;
3104 case 0x26: /* SWC1: bits 100110 */
3105 case 0x2e: /* SDC1: bits 101110 */
3106 breg = b0s5_reg (insn >> 16);
3107 if (breg != MIPS_SP_REGNUM)
3108 /* S[DW]C1 reg,offset($sp) */
3109 this_non_prologue_insn = 1;
3112 case 0x36: /* SD: bits 110110 */
3113 case 0x3e: /* SW: bits 111110 */
3114 breg = b0s5_reg (insn >> 16);
3115 sreg = b5s5_reg (insn >> 16);
3116 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
3117 if (breg == MIPS_SP_REGNUM)
3118 /* S[DW] reg,offset($sp) */
3119 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
3121 this_non_prologue_insn = 1;
3125 /* The instruction in the delay slot can be a part
3126 of the prologue, so move forward once more. */
3127 if (micromips_instruction_has_delay_slot (insn, 0))
3130 this_non_prologue_insn = 1;
3136 /* 16-bit instructions. */
3137 case MIPS_INSN16_SIZE:
3138 switch (micromips_op (insn))
3140 case 0x3: /* MOVE: bits 000011 */
3141 sreg = b0s5_reg (insn);
3142 dreg = b5s5_reg (insn);
3143 if (sreg == MIPS_SP_REGNUM && dreg == 30)
3146 else if ((sreg & 0x1c) != 0x4)
3147 /* MOVE reg, $a0-$a3 */
3148 this_non_prologue_insn = 1;
3151 case 0x11: /* POOL16C: bits 010001 */
3152 if (b6s4_op (insn) == 0x5)
3153 /* SWM: bits 010001 0101 */
3155 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20;
3156 reglist = b4s2_regl (insn);
3157 for (i = 0; i <= reglist; i++)
3158 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i);
3159 set_reg_offset (gdbarch, this_cache,
3160 MIPS_RA_REGNUM, sp + 4 * i++);
3163 this_non_prologue_insn = 1;
3166 case 0x13: /* POOL16D: bits 010011 */
3167 if ((insn & 0x1) == 0x1)
3168 /* ADDIUSP: bits 010011 1 */
3169 sp_adj = micromips_decode_imm9 (b1s9_imm (insn));
3170 else if (b5s5_reg (insn) == MIPS_SP_REGNUM)
3171 /* ADDIUS5: bits 010011 0 */
3172 /* ADDIUS5 $sp, imm */
3173 sp_adj = (b1s4_imm (insn) ^ 8) - 8;
3175 this_non_prologue_insn = 1;
3178 case 0x32: /* SWSP: bits 110010 */
3179 offset = b0s5_imm (insn) << 2;
3180 sreg = b5s5_reg (insn);
3181 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
3185 /* The instruction in the delay slot can be a part
3186 of the prologue, so move forward once more. */
3187 if (micromips_instruction_has_delay_slot (insn << 16, 0))
3190 this_non_prologue_insn = 1;
3196 frame_offset -= sp_adj;
3198 non_prologue_insns += this_non_prologue_insn;
3200 /* A jump or branch, enough non-prologue insns seen or positive
3201 stack adjustment? If so, then we must have reached the end
3202 of the prologue by now. */
3203 if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0
3204 || micromips_instruction_is_compact_branch (insn))
3207 prev_non_prologue_insn = this_non_prologue_insn;
3208 prev_delay_slot = in_delay_slot;
3212 if (this_cache != NULL)
3215 (get_frame_register_signed (this_frame,
3216 gdbarch_num_regs (gdbarch) + frame_reg)
3217 + frame_offset - frame_adjust);
3218 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3219 be able to get rid of the assignment below, evetually. But it's
3220 still needed for now. */
3221 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3222 + mips_regnum (gdbarch)->pc]
3223 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
3226 /* Set end_prologue_addr to the address of the instruction immediately
3227 after the last one we scanned. Unless the last one looked like a
3228 non-prologue instruction (and we looked ahead), in which case use
3229 its address instead. */
3231 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc;
3233 return end_prologue_addr;
3236 /* Heuristic unwinder for procedures using microMIPS instructions.
3237 Procedures that use the 32-bit instruction set are handled by the
3238 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3240 static struct mips_frame_cache *
3241 mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache)
3243 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3244 struct mips_frame_cache *cache;
3246 if ((*this_cache) != NULL)
3247 return (struct mips_frame_cache *) (*this_cache);
3249 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3250 (*this_cache) = cache;
3251 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3253 /* Analyze the function prologue. */
3255 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3256 CORE_ADDR start_addr;
3258 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3259 if (start_addr == 0)
3260 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc);
3261 /* We can't analyze the prologue if we couldn't find the begining
3263 if (start_addr == 0)
3266 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame,
3267 (struct mips_frame_cache *) *this_cache);
3270 /* gdbarch_sp_regnum contains the value and not the address. */
3271 trad_frame_set_value (cache->saved_regs,
3272 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3275 return (struct mips_frame_cache *) (*this_cache);
3279 mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache,
3280 struct frame_id *this_id)
3282 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3284 /* This marks the outermost frame. */
3285 if (info->base == 0)
3287 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3290 static struct value *
3291 mips_micro_frame_prev_register (struct frame_info *this_frame,
3292 void **this_cache, int regnum)
3294 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3296 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3300 mips_micro_frame_sniffer (const struct frame_unwind *self,
3301 struct frame_info *this_frame, void **this_cache)
3303 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3304 CORE_ADDR pc = get_frame_pc (this_frame);
3306 if (mips_pc_is_micromips (gdbarch, pc))
3311 static const struct frame_unwind mips_micro_frame_unwind =
3314 default_frame_unwind_stop_reason,
3315 mips_micro_frame_this_id,
3316 mips_micro_frame_prev_register,
3318 mips_micro_frame_sniffer
3322 mips_micro_frame_base_address (struct frame_info *this_frame,
3325 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3330 static const struct frame_base mips_micro_frame_base =
3332 &mips_micro_frame_unwind,
3333 mips_micro_frame_base_address,
3334 mips_micro_frame_base_address,
3335 mips_micro_frame_base_address
3338 static const struct frame_base *
3339 mips_micro_frame_base_sniffer (struct frame_info *this_frame)
3341 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3342 CORE_ADDR pc = get_frame_pc (this_frame);
3344 if (mips_pc_is_micromips (gdbarch, pc))
3345 return &mips_micro_frame_base;
3350 /* Mark all the registers as unset in the saved_regs array
3351 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3354 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
3356 if (this_cache == NULL || this_cache->saved_regs == NULL)
3360 const int num_regs = gdbarch_num_regs (gdbarch);
3363 for (i = 0; i < num_regs; i++)
3365 this_cache->saved_regs[i].addr = -1;
3370 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3371 the associated FRAME_CACHE if not null.
3372 Return the address of the first instruction past the prologue. */
3375 mips32_scan_prologue (struct gdbarch *gdbarch,
3376 CORE_ADDR start_pc, CORE_ADDR limit_pc,
3377 struct frame_info *this_frame,
3378 struct mips_frame_cache *this_cache)
3380 int prev_non_prologue_insn;
3381 int this_non_prologue_insn;
3382 int non_prologue_insns;
3383 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for
3385 int prev_delay_slot;
3390 int frame_reg = MIPS_SP_REGNUM;
3392 CORE_ADDR end_prologue_addr;
3393 int seen_sp_adjust = 0;
3394 int load_immediate_bytes = 0;
3396 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
3398 /* Can be called when there's no process, and hence when there's no
3400 if (this_frame != NULL)
3401 sp = get_frame_register_signed (this_frame,
3402 gdbarch_num_regs (gdbarch)
3407 if (limit_pc > start_pc + 200)
3408 limit_pc = start_pc + 200;
3411 prev_non_prologue_insn = 0;
3412 non_prologue_insns = 0;
3413 prev_delay_slot = 0;
3416 /* Permit at most one non-prologue non-control-transfer instruction
3417 in the middle which may have been reordered by the compiler for
3420 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
3422 unsigned long inst, high_word;
3426 this_non_prologue_insn = 0;
3429 /* Fetch the instruction. */
3430 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS,
3433 /* Save some code by pre-extracting some useful fields. */
3434 high_word = (inst >> 16) & 0xffff;
3435 offset = ((inst & 0xffff) ^ 0x8000) - 0x8000;
3436 reg = high_word & 0x1f;
3438 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
3439 || high_word == 0x23bd /* addi $sp,$sp,-i */
3440 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
3442 if (offset < 0) /* Negative stack adjustment? */
3443 frame_offset -= offset;
3445 /* Exit loop if a positive stack adjustment is found, which
3446 usually means that the stack cleanup code in the function
3447 epilogue is reached. */
3451 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3452 && !regsize_is_64_bits)
3454 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
3456 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3457 && regsize_is_64_bits)
3459 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3460 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
3462 else if (high_word == 0x27be) /* addiu $30,$sp,size */
3464 /* Old gcc frame, r30 is virtual frame pointer. */
3465 if (offset != frame_offset)
3466 frame_addr = sp + offset;
3467 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
3469 unsigned alloca_adjust;
3472 frame_addr = get_frame_register_signed
3473 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3476 alloca_adjust = (unsigned) (frame_addr - (sp + offset));
3477 if (alloca_adjust > 0)
3479 /* FP > SP + frame_size. This may be because of
3480 an alloca or somethings similar. Fix sp to
3481 "pre-alloca" value, and try again. */
3482 sp += alloca_adjust;
3483 /* Need to reset the status of all registers. Otherwise,
3484 we will hit a guard that prevents the new address
3485 for each register to be recomputed during the second
3487 reset_saved_regs (gdbarch, this_cache);
3492 /* move $30,$sp. With different versions of gas this will be either
3493 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3494 Accept any one of these. */
3495 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3497 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3498 if (this_frame && frame_reg == MIPS_SP_REGNUM)
3500 unsigned alloca_adjust;
3503 frame_addr = get_frame_register_signed
3504 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3506 alloca_adjust = (unsigned) (frame_addr - sp);
3507 if (alloca_adjust > 0)
3509 /* FP > SP + frame_size. This may be because of
3510 an alloca or somethings similar. Fix sp to
3511 "pre-alloca" value, and try again. */
3513 /* Need to reset the status of all registers. Otherwise,
3514 we will hit a guard that prevents the new address
3515 for each register to be recomputed during the second
3517 reset_saved_regs (gdbarch, this_cache);
3522 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3523 && !regsize_is_64_bits)
3525 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
3527 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3528 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3529 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3530 || high_word == 0x3c1c /* lui $gp,n */
3531 || high_word == 0x279c /* addiu $gp,$gp,n */
3532 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3533 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
3536 /* These instructions are part of the prologue, but we don't
3537 need to do anything special to handle them. */
3539 /* The instructions below load $at or $t0 with an immediate
3540 value in preparation for a stack adjustment via
3541 subu $sp,$sp,[$at,$t0]. These instructions could also
3542 initialize a local variable, so we accept them only before
3543 a stack adjustment instruction was seen. */
3544 else if (!seen_sp_adjust
3546 && (high_word == 0x3c01 /* lui $at,n */
3547 || high_word == 0x3c08 /* lui $t0,n */
3548 || high_word == 0x3421 /* ori $at,$at,n */
3549 || high_word == 0x3508 /* ori $t0,$t0,n */
3550 || high_word == 0x3401 /* ori $at,$zero,n */
3551 || high_word == 0x3408 /* ori $t0,$zero,n */
3554 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
3556 /* Check for branches and jumps. The instruction in the delay
3557 slot can be a part of the prologue, so move forward once more. */
3558 else if (mips32_instruction_has_delay_slot (gdbarch, inst))
3562 /* This instruction is not an instruction typically found
3563 in a prologue, so we must have reached the end of the
3567 this_non_prologue_insn = 1;
3570 non_prologue_insns += this_non_prologue_insn;
3572 /* A jump or branch, or enough non-prologue insns seen? If so,
3573 then we must have reached the end of the prologue by now. */
3574 if (prev_delay_slot || non_prologue_insns > 1)
3577 prev_non_prologue_insn = this_non_prologue_insn;
3578 prev_delay_slot = in_delay_slot;
3582 if (this_cache != NULL)
3585 (get_frame_register_signed (this_frame,
3586 gdbarch_num_regs (gdbarch) + frame_reg)
3588 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3589 this assignment below, eventually. But it's still needed
3591 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3592 + mips_regnum (gdbarch)->pc]
3593 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3597 /* Set end_prologue_addr to the address of the instruction immediately
3598 after the last one we scanned. Unless the last one looked like a
3599 non-prologue instruction (and we looked ahead), in which case use
3600 its address instead. */
3602 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc;
3604 /* In a frameless function, we might have incorrectly
3605 skipped some load immediate instructions. Undo the skipping
3606 if the load immediate was not followed by a stack adjustment. */
3607 if (load_immediate_bytes && !seen_sp_adjust)
3608 end_prologue_addr -= load_immediate_bytes;
3610 return end_prologue_addr;
3613 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3614 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3615 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3616 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3618 static struct mips_frame_cache *
3619 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
3621 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3622 struct mips_frame_cache *cache;
3624 if ((*this_cache) != NULL)
3625 return (struct mips_frame_cache *) (*this_cache);
3627 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3628 (*this_cache) = cache;
3629 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3631 /* Analyze the function prologue. */
3633 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3634 CORE_ADDR start_addr;
3636 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3637 if (start_addr == 0)
3638 start_addr = heuristic_proc_start (gdbarch, pc);
3639 /* We can't analyze the prologue if we couldn't find the begining
3641 if (start_addr == 0)
3644 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame,
3645 (struct mips_frame_cache *) *this_cache);
3648 /* gdbarch_sp_regnum contains the value and not the address. */
3649 trad_frame_set_value (cache->saved_regs,
3650 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3653 return (struct mips_frame_cache *) (*this_cache);
3657 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
3658 struct frame_id *this_id)
3660 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3662 /* This marks the outermost frame. */
3663 if (info->base == 0)
3665 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3668 static struct value *
3669 mips_insn32_frame_prev_register (struct frame_info *this_frame,
3670 void **this_cache, int regnum)
3672 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3674 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3678 mips_insn32_frame_sniffer (const struct frame_unwind *self,
3679 struct frame_info *this_frame, void **this_cache)
3681 CORE_ADDR pc = get_frame_pc (this_frame);
3682 if (mips_pc_is_mips (pc))
3687 static const struct frame_unwind mips_insn32_frame_unwind =
3690 default_frame_unwind_stop_reason,
3691 mips_insn32_frame_this_id,
3692 mips_insn32_frame_prev_register,
3694 mips_insn32_frame_sniffer
3698 mips_insn32_frame_base_address (struct frame_info *this_frame,
3701 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3706 static const struct frame_base mips_insn32_frame_base =
3708 &mips_insn32_frame_unwind,
3709 mips_insn32_frame_base_address,
3710 mips_insn32_frame_base_address,
3711 mips_insn32_frame_base_address
3714 static const struct frame_base *
3715 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
3717 CORE_ADDR pc = get_frame_pc (this_frame);
3718 if (mips_pc_is_mips (pc))
3719 return &mips_insn32_frame_base;
3724 static struct trad_frame_cache *
3725 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
3728 CORE_ADDR start_addr;
3729 CORE_ADDR stack_addr;
3730 struct trad_frame_cache *this_trad_cache;
3731 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3732 int num_regs = gdbarch_num_regs (gdbarch);
3734 if ((*this_cache) != NULL)
3735 return (struct trad_frame_cache *) (*this_cache);
3736 this_trad_cache = trad_frame_cache_zalloc (this_frame);
3737 (*this_cache) = this_trad_cache;
3739 /* The return address is in the link register. */
3740 trad_frame_set_reg_realreg (this_trad_cache,
3741 gdbarch_pc_regnum (gdbarch),
3742 num_regs + MIPS_RA_REGNUM);
3744 /* Frame ID, since it's a frameless / stackless function, no stack
3745 space is allocated and SP on entry is the current SP. */
3746 pc = get_frame_pc (this_frame);
3747 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3748 stack_addr = get_frame_register_signed (this_frame,
3749 num_regs + MIPS_SP_REGNUM);
3750 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
3752 /* Assume that the frame's base is the same as the
3754 trad_frame_set_this_base (this_trad_cache, stack_addr);
3756 return this_trad_cache;
3760 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
3761 struct frame_id *this_id)
3763 struct trad_frame_cache *this_trad_cache
3764 = mips_stub_frame_cache (this_frame, this_cache);
3765 trad_frame_get_id (this_trad_cache, this_id);
3768 static struct value *
3769 mips_stub_frame_prev_register (struct frame_info *this_frame,
3770 void **this_cache, int regnum)
3772 struct trad_frame_cache *this_trad_cache
3773 = mips_stub_frame_cache (this_frame, this_cache);
3774 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
3778 mips_stub_frame_sniffer (const struct frame_unwind *self,
3779 struct frame_info *this_frame, void **this_cache)
3782 CORE_ADDR pc = get_frame_address_in_block (this_frame);
3783 struct bound_minimal_symbol msym;
3785 /* Use the stub unwinder for unreadable code. */
3786 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
3789 if (in_plt_section (pc) || in_mips_stubs_section (pc))
3792 /* Calling a PIC function from a non-PIC function passes through a
3793 stub. The stub for foo is named ".pic.foo". */
3794 msym = lookup_minimal_symbol_by_pc (pc);
3795 if (msym.minsym != NULL
3796 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL
3797 && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
3803 static const struct frame_unwind mips_stub_frame_unwind =
3806 default_frame_unwind_stop_reason,
3807 mips_stub_frame_this_id,
3808 mips_stub_frame_prev_register,
3810 mips_stub_frame_sniffer
3814 mips_stub_frame_base_address (struct frame_info *this_frame,
3817 struct trad_frame_cache *this_trad_cache
3818 = mips_stub_frame_cache (this_frame, this_cache);
3819 return trad_frame_get_this_base (this_trad_cache);
3822 static const struct frame_base mips_stub_frame_base =
3824 &mips_stub_frame_unwind,
3825 mips_stub_frame_base_address,
3826 mips_stub_frame_base_address,
3827 mips_stub_frame_base_address
3830 static const struct frame_base *
3831 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
3833 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
3834 return &mips_stub_frame_base;
3839 /* mips_addr_bits_remove - remove useless address bits */
3842 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
3844 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3846 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
3847 /* This hack is a work-around for existing boards using PMON, the
3848 simulator, and any other 64-bit targets that doesn't have true
3849 64-bit addressing. On these targets, the upper 32 bits of
3850 addresses are ignored by the hardware. Thus, the PC or SP are
3851 likely to have been sign extended to all 1s by instruction
3852 sequences that load 32-bit addresses. For example, a typical
3853 piece of code that loads an address is this:
3855 lui $r2, <upper 16 bits>
3856 ori $r2, <lower 16 bits>
3858 But the lui sign-extends the value such that the upper 32 bits
3859 may be all 1s. The workaround is simply to mask off these
3860 bits. In the future, gcc may be changed to support true 64-bit
3861 addressing, and this masking will have to be disabled. */
3862 return addr &= 0xffffffffUL;
3868 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3869 instruction and ending with a SC/SCD instruction. If such a sequence
3870 is found, attempt to step through it. A breakpoint is placed at the end of
3873 /* Instructions used during single-stepping of atomic sequences, standard
3875 #define LL_OPCODE 0x30
3876 #define LLD_OPCODE 0x34
3877 #define SC_OPCODE 0x38
3878 #define SCD_OPCODE 0x3c
3880 static std::vector<CORE_ADDR>
3881 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
3883 CORE_ADDR breaks[2] = {-1, -1};
3885 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
3889 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
3890 const int atomic_sequence_length = 16; /* Instruction sequence length. */
3892 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3893 /* Assume all atomic sequences start with a ll/lld instruction. */
3894 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
3897 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3899 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
3902 loc += MIPS_INSN32_SIZE;
3903 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3905 /* Assume that there is at most one branch in the atomic
3906 sequence. If a branch is found, put a breakpoint in its
3907 destination address. */
3908 switch (itype_op (insn))
3910 case 0: /* SPECIAL */
3911 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
3912 return {}; /* fallback to the standard single-step code. */
3914 case 1: /* REGIMM */
3915 is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */
3916 || ((itype_rt (insn) & 0x1e) == 0
3917 && itype_rs (insn) == 0)); /* BPOSGE* */
3921 return {}; /* fallback to the standard single-step code. */
3928 case 22: /* BLEZL */
3929 case 23: /* BGTTL */
3933 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10)
3934 && (itype_rt (insn) & 0x2) == 0);
3935 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3940 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3945 branch_bp = loc + mips32_relative_offset (insn) + 4;
3946 if (last_breakpoint >= 1)
3947 return {}; /* More than one branch found, fallback to the
3948 standard single-step code. */
3949 breaks[1] = branch_bp;
3953 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
3957 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3958 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
3961 loc += MIPS_INSN32_SIZE;
3963 /* Insert a breakpoint right after the end of the atomic sequence. */
3966 /* Check for duplicated breakpoints. Check also for a breakpoint
3967 placed (branch instruction's destination) in the atomic sequence. */
3968 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
3969 last_breakpoint = 0;
3971 std::vector<CORE_ADDR> next_pcs;
3973 /* Effectively inserts the breakpoints. */
3974 for (index = 0; index <= last_breakpoint; index++)
3975 next_pcs.push_back (breaks[index]);
3980 static std::vector<CORE_ADDR>
3981 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
3984 const int atomic_sequence_length = 16; /* Instruction sequence length. */
3985 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
3986 CORE_ADDR breaks[2] = {-1, -1};
3987 CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's
3995 /* Assume all atomic sequences start with a ll/lld instruction. */
3996 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
3997 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */
3999 loc += MIPS_INSN16_SIZE;
4001 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
4002 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4004 loc += MIPS_INSN16_SIZE;
4006 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4007 that no atomic sequence is longer than "atomic_sequence_length"
4009 for (insn_count = 0;
4010 !sc_found && insn_count < atomic_sequence_length;
4015 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
4016 loc += MIPS_INSN16_SIZE;
4018 /* Assume that there is at most one conditional branch in the
4019 atomic sequence. If a branch is found, put a breakpoint in
4020 its destination address. */
4021 switch (mips_insn_size (ISA_MICROMIPS, insn))
4023 /* 32-bit instructions. */
4024 case 2 * MIPS_INSN16_SIZE:
4025 switch (micromips_op (insn))
4027 case 0x10: /* POOL32I: bits 010000 */
4028 if ((b5s5_op (insn) & 0x18) != 0x0
4029 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4030 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4031 && (b5s5_op (insn) & 0x1d) != 0x11
4032 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4033 && ((b5s5_op (insn) & 0x1e) != 0x14
4034 || (insn & 0x3) != 0x0)
4035 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4036 && (b5s5_op (insn) & 0x1e) != 0x1a
4037 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4038 && ((b5s5_op (insn) & 0x1e) != 0x1c
4039 || (insn & 0x3) != 0x0)
4040 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4041 && ((b5s5_op (insn) & 0x1c) != 0x1c
4042 || (insn & 0x3) != 0x1))
4043 /* BC1ANY*: bits 010000 111xx xxx01 */
4047 case 0x25: /* BEQ: bits 100101 */
4048 case 0x2d: /* BNE: bits 101101 */
4050 insn |= mips_fetch_instruction (gdbarch,
4051 ISA_MICROMIPS, loc, NULL);
4052 branch_bp = (loc + MIPS_INSN16_SIZE
4053 + micromips_relative_offset16 (insn));
4057 case 0x00: /* POOL32A: bits 000000 */
4059 insn |= mips_fetch_instruction (gdbarch,
4060 ISA_MICROMIPS, loc, NULL);
4061 if (b0s6_op (insn) != 0x3c
4062 /* POOL32Axf: bits 000000 ... 111100 */
4063 || (b6s10_ext (insn) & 0x2bf) != 0x3c)
4064 /* JALR, JALR.HB: 000000 000x111100 111100 */
4065 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4069 case 0x1d: /* JALS: bits 011101 */
4070 case 0x35: /* J: bits 110101 */
4071 case 0x3d: /* JAL: bits 111101 */
4072 case 0x3c: /* JALX: bits 111100 */
4073 return {}; /* Fall back to the standard single-step code. */
4075 case 0x18: /* POOL32C: bits 011000 */
4076 if ((b12s4_op (insn) & 0xb) == 0xb)
4077 /* SC, SCD: bits 011000 1x11 */
4081 loc += MIPS_INSN16_SIZE;
4084 /* 16-bit instructions. */
4085 case MIPS_INSN16_SIZE:
4086 switch (micromips_op (insn))
4088 case 0x23: /* BEQZ16: bits 100011 */
4089 case 0x2b: /* BNEZ16: bits 101011 */
4090 branch_bp = loc + micromips_relative_offset7 (insn);
4094 case 0x11: /* POOL16C: bits 010001 */
4095 if ((b5s5_op (insn) & 0x1c) != 0xc
4096 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4097 && b5s5_op (insn) != 0x18)
4098 /* JRADDIUSP: bits 010001 11000 */
4100 return {}; /* Fall back to the standard single-step code. */
4102 case 0x33: /* B16: bits 110011 */
4103 return {}; /* Fall back to the standard single-step code. */
4109 if (last_breakpoint >= 1)
4110 return {}; /* More than one branch found, fallback to the
4111 standard single-step code. */
4112 breaks[1] = branch_bp;
4119 /* Insert a breakpoint right after the end of the atomic sequence. */
4122 /* Check for duplicated breakpoints. Check also for a breakpoint
4123 placed (branch instruction's destination) in the atomic sequence */
4124 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
4125 last_breakpoint = 0;
4127 std::vector<CORE_ADDR> next_pcs;
4129 /* Effectively inserts the breakpoints. */
4130 for (index = 0; index <= last_breakpoint; index++)
4131 next_pcs.push_back (breaks[index]);
4136 static std::vector<CORE_ADDR>
4137 deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
4139 if (mips_pc_is_mips (pc))
4140 return mips_deal_with_atomic_sequence (gdbarch, pc);
4141 else if (mips_pc_is_micromips (gdbarch, pc))
4142 return micromips_deal_with_atomic_sequence (gdbarch, pc);
4147 /* mips_software_single_step() is called just before we want to resume
4148 the inferior, if we want to single-step it but there is no hardware
4149 or kernel single-step support (MIPS on GNU/Linux for example). We find
4150 the target of the coming instruction and breakpoint it. */
4152 std::vector<CORE_ADDR>
4153 mips_software_single_step (struct regcache *regcache)
4155 struct gdbarch *gdbarch = regcache->arch ();
4156 CORE_ADDR pc, next_pc;
4158 pc = regcache_read_pc (regcache);
4159 std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc);
4161 if (!next_pcs.empty ())
4164 next_pc = mips_next_pc (regcache, pc);
4169 /* Test whether the PC points to the return instruction at the
4170 end of a function. */
4173 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
4178 /* This used to check for MIPS16, but this piece of code is never
4179 called for MIPS16 functions. And likewise microMIPS ones. */
4180 gdb_assert (mips_pc_is_mips (pc));
4182 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
4184 return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */
4188 /* This fencepost looks highly suspicious to me. Removing it also
4189 seems suspicious as it could affect remote debugging across serial
4193 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
4199 struct inferior *inf;
4201 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4203 fence = start_pc - heuristic_fence_post;
4207 if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS)
4208 fence = VM_MIN_ADDRESS;
4210 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE;
4212 inf = current_inferior ();
4214 /* Search back for previous return. */
4215 for (start_pc -= instlen;; start_pc -= instlen)
4216 if (start_pc < fence)
4218 /* It's not clear to me why we reach this point when
4219 stop_soon, but with this test, at least we
4220 don't print out warnings for every child forked (eg, on
4221 decstation). 22apr93 rich@cygnus.com. */
4222 if (inf->control.stop_soon == NO_STOP_QUIETLY)
4224 static int blurb_printed = 0;
4226 warning (_("GDB can't find the start of the function at %s."),
4227 paddress (gdbarch, pc));
4231 /* This actually happens frequently in embedded
4232 development, when you first connect to a board
4233 and your stack pointer and pc are nowhere in
4234 particular. This message needs to give people
4235 in that situation enough information to
4236 determine that it's no big deal. */
4237 printf_filtered ("\n\
4238 GDB is unable to find the start of the function at %s\n\
4239 and thus can't determine the size of that function's stack frame.\n\
4240 This means that GDB may be unable to access that stack frame, or\n\
4241 the frames below it.\n\
4242 This problem is most likely caused by an invalid program counter or\n\
4244 However, if you think GDB should simply search farther back\n\
4245 from %s for code which looks like the beginning of a\n\
4246 function, you can increase the range of the search using the `set\n\
4247 heuristic-fence-post' command.\n",
4248 paddress (gdbarch, pc), paddress (gdbarch, pc));
4255 else if (mips_pc_is_mips16 (gdbarch, start_pc))
4257 unsigned short inst;
4259 /* On MIPS16, any one of the following is likely to be the
4260 start of a function:
4266 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4267 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL);
4268 if ((inst & 0xff80) == 0x6480) /* save */
4270 if (start_pc - instlen >= fence)
4272 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16,
4273 start_pc - instlen, NULL);
4274 if ((inst & 0xf800) == 0xf000) /* extend */
4275 start_pc -= instlen;
4279 else if (((inst & 0xf81f) == 0xe809
4280 && (inst & 0x700) != 0x700) /* entry */
4281 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
4282 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
4283 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
4285 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
4286 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
4291 else if (mips_pc_is_micromips (gdbarch, start_pc))
4299 /* On microMIPS, any one of the following is likely to be the
4300 start of a function:
4304 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
4305 switch (micromips_op (insn))
4307 case 0xc: /* ADDIU: bits 001100 */
4308 case 0x17: /* DADDIU: bits 010111 */
4309 sreg = b0s5_reg (insn);
4310 dreg = b5s5_reg (insn);
4312 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS,
4313 pc + MIPS_INSN16_SIZE, NULL);
4314 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
4315 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
4316 /* (D)ADDIU $sp, imm */
4321 case 0x10: /* POOL32I: bits 010000 */
4322 if (b5s5_op (insn) == 0xd
4323 /* LUI: bits 010000 001101 */
4324 && b0s5_reg (insn >> 16) == 28)
4329 case 0x13: /* POOL16D: bits 010011 */
4330 if ((insn & 0x1) == 0x1)
4331 /* ADDIUSP: bits 010011 1 */
4333 offset = micromips_decode_imm9 (b1s9_imm (insn));
4339 /* ADDIUS5: bits 010011 0 */
4341 dreg = b5s5_reg (insn);
4342 offset = (b1s4_imm (insn) ^ 8) - 8;
4343 if (dreg == MIPS_SP_REGNUM && offset < 0)
4344 /* ADDIUS5 $sp, -imm */
4352 else if (mips_about_to_return (gdbarch, start_pc))
4354 /* Skip return and its delay slot. */
4355 start_pc += 2 * MIPS_INSN32_SIZE;
4362 struct mips_objfile_private
4368 /* According to the current ABI, should the type be passed in a
4369 floating-point register (assuming that there is space)? When there
4370 is no FPU, FP are not even considered as possible candidates for
4371 FP registers and, consequently this returns false - forces FP
4372 arguments into integer registers. */
4375 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
4376 struct type *arg_type)
4378 return ((typecode == TYPE_CODE_FLT
4379 || (MIPS_EABI (gdbarch)
4380 && (typecode == TYPE_CODE_STRUCT
4381 || typecode == TYPE_CODE_UNION)
4382 && TYPE_NFIELDS (arg_type) == 1
4383 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
4385 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
4388 /* On o32, argument passing in GPRs depends on the alignment of the type being
4389 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4392 mips_type_needs_double_align (struct type *type)
4394 enum type_code typecode = TYPE_CODE (type);
4396 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
4398 else if (typecode == TYPE_CODE_STRUCT)
4400 if (TYPE_NFIELDS (type) < 1)
4402 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
4404 else if (typecode == TYPE_CODE_UNION)
4408 n = TYPE_NFIELDS (type);
4409 for (i = 0; i < n; i++)
4410 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
4417 /* Adjust the address downward (direction of stack growth) so that it
4418 is correctly aligned for a new stack frame. */
4420 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
4422 return align_down (addr, 16);
4425 /* Implement the "push_dummy_code" gdbarch method. */
4428 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
4429 CORE_ADDR funaddr, struct value **args,
4430 int nargs, struct type *value_type,
4431 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
4432 struct regcache *regcache)
4434 static gdb_byte nop_insn[] = { 0, 0, 0, 0 };
4438 /* Reserve enough room on the stack for our breakpoint instruction. */
4439 bp_slot = sp - sizeof (nop_insn);
4441 /* Return to microMIPS mode if calling microMIPS code to avoid
4442 triggering an address error exception on processors that only
4443 support microMIPS execution. */
4444 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr)
4445 ? make_compact_addr (bp_slot) : bp_slot);
4447 /* The breakpoint layer automatically adjusts the address of
4448 breakpoints inserted in a branch delay slot. With enough
4449 bad luck, the 4 bytes located just before our breakpoint
4450 instruction could look like a branch instruction, and thus
4451 trigger the adjustement, and break the function call entirely.
4452 So, we reserve those 4 bytes and write a nop instruction
4453 to prevent that from happening. */
4454 nop_addr = bp_slot - sizeof (nop_insn);
4455 write_memory (nop_addr, nop_insn, sizeof (nop_insn));
4456 sp = mips_frame_align (gdbarch, nop_addr);
4458 /* Inferior resumes at the function entry point. */
4465 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4466 struct regcache *regcache, CORE_ADDR bp_addr,
4467 int nargs, struct value **args, CORE_ADDR sp,
4468 int struct_return, CORE_ADDR struct_addr)
4474 int stack_offset = 0;
4475 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4476 CORE_ADDR func_addr = find_function_addr (function, NULL);
4477 int abi_regsize = mips_abi_regsize (gdbarch);
4479 /* For shared libraries, "t9" needs to point at the function
4481 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4483 /* Set the return address register to point to the entry point of
4484 the program, where a breakpoint lies in wait. */
4485 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4487 /* First ensure that the stack and structure return address (if any)
4488 are properly aligned. The stack has to be at least 64-bit
4489 aligned even on 32-bit machines, because doubles must be 64-bit
4490 aligned. For n32 and n64, stack frames need to be 128-bit
4491 aligned, so we round to this widest known alignment. */
4493 sp = align_down (sp, 16);
4494 struct_addr = align_down (struct_addr, 16);
4496 /* Now make space on the stack for the args. We allocate more
4497 than necessary for EABI, because the first few arguments are
4498 passed in registers, but that's OK. */
4499 for (argnum = 0; argnum < nargs; argnum++)
4500 len += align_up (TYPE_LENGTH (value_type (args[argnum])), abi_regsize);
4501 sp -= align_up (len, 16);
4504 fprintf_unfiltered (gdb_stdlog,
4505 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4506 paddress (gdbarch, sp), (long) align_up (len, 16));
4508 /* Initialize the integer and float register pointers. */
4509 argreg = MIPS_A0_REGNUM;
4510 float_argreg = mips_fpa0_regnum (gdbarch);
4512 /* The struct_return pointer occupies the first parameter-passing reg. */
4516 fprintf_unfiltered (gdb_stdlog,
4517 "mips_eabi_push_dummy_call: "
4518 "struct_return reg=%d %s\n",
4519 argreg, paddress (gdbarch, struct_addr));
4520 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4523 /* Now load as many as possible of the first arguments into
4524 registers, and push the rest onto the stack. Loop thru args
4525 from first to last. */
4526 for (argnum = 0; argnum < nargs; argnum++)
4528 const gdb_byte *val;
4529 /* This holds the address of structures that are passed by
4531 gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE];
4532 struct value *arg = args[argnum];
4533 struct type *arg_type = check_typedef (value_type (arg));
4534 int len = TYPE_LENGTH (arg_type);
4535 enum type_code typecode = TYPE_CODE (arg_type);
4538 fprintf_unfiltered (gdb_stdlog,
4539 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4540 argnum + 1, len, (int) typecode);
4542 /* The EABI passes structures that do not fit in a register by
4544 if (len > abi_regsize
4545 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
4547 gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf));
4548 store_unsigned_integer (ref_valbuf, abi_regsize, byte_order,
4549 value_address (arg));
4550 typecode = TYPE_CODE_PTR;
4554 fprintf_unfiltered (gdb_stdlog, " push");
4557 val = value_contents (arg);
4559 /* 32-bit ABIs always start floating point arguments in an
4560 even-numbered floating point register. Round the FP register
4561 up before the check to see if there are any FP registers
4562 left. Non MIPS_EABI targets also pass the FP in the integer
4563 registers so also round up normal registers. */
4564 if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
4566 if ((float_argreg & 1))
4570 /* Floating point arguments passed in registers have to be
4571 treated specially. On 32-bit architectures, doubles
4572 are passed in register pairs; the even register gets
4573 the low word, and the odd register gets the high word.
4574 On non-EABI processors, the first two floating point arguments are
4575 also copied to general registers, because MIPS16 functions
4576 don't use float registers for arguments. This duplication of
4577 arguments in general registers can't hurt non-MIPS16 functions
4578 because those registers are normally skipped. */
4579 /* MIPS_EABI squeezes a struct that contains a single floating
4580 point value into an FP register instead of pushing it onto the
4582 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4583 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4585 /* EABI32 will pass doubles in consecutive registers, even on
4586 64-bit cores. At one time, we used to check the size of
4587 `float_argreg' to determine whether or not to pass doubles
4588 in consecutive registers, but this is not sufficient for
4589 making the ABI determination. */
4590 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
4592 int low_offset = gdbarch_byte_order (gdbarch)
4593 == BFD_ENDIAN_BIG ? 4 : 0;
4596 /* Write the low word of the double to the even register(s). */
4597 regval = extract_signed_integer (val + low_offset,
4600 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4601 float_argreg, phex (regval, 4));
4602 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4604 /* Write the high word of the double to the odd register(s). */
4605 regval = extract_signed_integer (val + 4 - low_offset,
4608 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4609 float_argreg, phex (regval, 4));
4610 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4614 /* This is a floating point value that fits entirely
4615 in a single register. */
4616 /* On 32 bit ABI's the float_argreg is further adjusted
4617 above to ensure that it is even register aligned. */
4618 LONGEST regval = extract_signed_integer (val, len, byte_order);
4620 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4621 float_argreg, phex (regval, len));
4622 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4627 /* Copy the argument to general registers or the stack in
4628 register-sized pieces. Large arguments are split between
4629 registers and stack. */
4630 /* Note: structs whose size is not a multiple of abi_regsize
4631 are treated specially: Irix cc passes
4632 them in registers where gcc sometimes puts them on the
4633 stack. For maximum compatibility, we will put them in
4635 int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0);
4637 /* Note: Floating-point values that didn't fit into an FP
4638 register are only written to memory. */
4641 /* Remember if the argument was written to the stack. */
4642 int stack_used_p = 0;
4643 int partial_len = (len < abi_regsize ? len : abi_regsize);
4646 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4649 /* Write this portion of the argument to the stack. */
4650 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4652 || fp_register_arg_p (gdbarch, typecode, arg_type))
4654 /* Should shorter than int integer values be
4655 promoted to int before being stored? */
4656 int longword_offset = 0;
4659 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4661 if (abi_regsize == 8
4662 && (typecode == TYPE_CODE_INT
4663 || typecode == TYPE_CODE_PTR
4664 || typecode == TYPE_CODE_FLT) && len <= 4)
4665 longword_offset = abi_regsize - len;
4666 else if ((typecode == TYPE_CODE_STRUCT
4667 || typecode == TYPE_CODE_UNION)
4668 && TYPE_LENGTH (arg_type) < abi_regsize)
4669 longword_offset = abi_regsize - len;
4674 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4675 paddress (gdbarch, stack_offset));
4676 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4677 paddress (gdbarch, longword_offset));
4680 addr = sp + stack_offset + longword_offset;
4685 fprintf_unfiltered (gdb_stdlog, " @%s ",
4686 paddress (gdbarch, addr));
4687 for (i = 0; i < partial_len; i++)
4689 fprintf_unfiltered (gdb_stdlog, "%02x",
4693 write_memory (addr, val, partial_len);
4696 /* Note!!! This is NOT an else clause. Odd sized
4697 structs may go thru BOTH paths. Floating point
4698 arguments will not. */
4699 /* Write this portion of the argument to a general
4700 purpose register. */
4701 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
4702 && !fp_register_arg_p (gdbarch, typecode, arg_type))
4705 extract_signed_integer (val, partial_len, byte_order);
4708 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4710 phex (regval, abi_regsize));
4711 regcache_cooked_write_signed (regcache, argreg, regval);
4718 /* Compute the offset into the stack at which we will
4719 copy the next parameter.
4721 In the new EABI (and the NABI32), the stack_offset
4722 only needs to be adjusted when it has been used. */
4725 stack_offset += align_up (partial_len, abi_regsize);
4729 fprintf_unfiltered (gdb_stdlog, "\n");
4732 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4734 /* Return adjusted stack pointer. */
4738 /* Determine the return value convention being used. */
4740 static enum return_value_convention
4741 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function,
4742 struct type *type, struct regcache *regcache,
4743 gdb_byte *readbuf, const gdb_byte *writebuf)
4745 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4746 int fp_return_type = 0;
4747 int offset, regnum, xfer;
4749 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
4750 return RETURN_VALUE_STRUCT_CONVENTION;
4752 /* Floating point type? */
4753 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
4755 if (TYPE_CODE (type) == TYPE_CODE_FLT)
4757 /* Structs with a single field of float type
4758 are returned in a floating point register. */
4759 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
4760 || TYPE_CODE (type) == TYPE_CODE_UNION)
4761 && TYPE_NFIELDS (type) == 1)
4763 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
4765 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
4772 /* A floating-point value belongs in the least significant part
4775 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4776 regnum = mips_regnum (gdbarch)->fp0;
4780 /* An integer value goes in V0/V1. */
4782 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
4783 regnum = MIPS_V0_REGNUM;
4786 offset < TYPE_LENGTH (type);
4787 offset += mips_abi_regsize (gdbarch), regnum++)
4789 xfer = mips_abi_regsize (gdbarch);
4790 if (offset + xfer > TYPE_LENGTH (type))
4791 xfer = TYPE_LENGTH (type) - offset;
4792 mips_xfer_register (gdbarch, regcache,
4793 gdbarch_num_regs (gdbarch) + regnum, xfer,
4794 gdbarch_byte_order (gdbarch), readbuf, writebuf,
4798 return RETURN_VALUE_REGISTER_CONVENTION;
4802 /* N32/N64 ABI stuff. */
4804 /* Search for a naturally aligned double at OFFSET inside a struct
4805 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4809 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
4814 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
4817 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
4820 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
4823 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
4826 struct type *field_type;
4828 /* We're only looking at normal fields. */
4829 if (field_is_static (&TYPE_FIELD (arg_type, i))
4830 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
4833 /* If we have gone past the offset, there is no double to pass. */
4834 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
4838 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
4840 /* If this field is entirely before the requested offset, go
4841 on to the next one. */
4842 if (pos + TYPE_LENGTH (field_type) <= offset)
4845 /* If this is our special aligned double, we can stop. */
4846 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
4847 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
4850 /* This field starts at or before the requested offset, and
4851 overlaps it. If it is a structure, recurse inwards. */
4852 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
4859 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4860 struct regcache *regcache, CORE_ADDR bp_addr,
4861 int nargs, struct value **args, CORE_ADDR sp,
4862 int struct_return, CORE_ADDR struct_addr)
4868 int stack_offset = 0;
4869 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4870 CORE_ADDR func_addr = find_function_addr (function, NULL);
4872 /* For shared libraries, "t9" needs to point at the function
4874 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4876 /* Set the return address register to point to the entry point of
4877 the program, where a breakpoint lies in wait. */
4878 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4880 /* First ensure that the stack and structure return address (if any)
4881 are properly aligned. The stack has to be at least 64-bit
4882 aligned even on 32-bit machines, because doubles must be 64-bit
4883 aligned. For n32 and n64, stack frames need to be 128-bit
4884 aligned, so we round to this widest known alignment. */
4886 sp = align_down (sp, 16);
4887 struct_addr = align_down (struct_addr, 16);
4889 /* Now make space on the stack for the args. */
4890 for (argnum = 0; argnum < nargs; argnum++)
4891 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
4892 sp -= align_up (len, 16);
4895 fprintf_unfiltered (gdb_stdlog,
4896 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4897 paddress (gdbarch, sp), (long) align_up (len, 16));
4899 /* Initialize the integer and float register pointers. */
4900 argreg = MIPS_A0_REGNUM;
4901 float_argreg = mips_fpa0_regnum (gdbarch);
4903 /* The struct_return pointer occupies the first parameter-passing reg. */
4907 fprintf_unfiltered (gdb_stdlog,
4908 "mips_n32n64_push_dummy_call: "
4909 "struct_return reg=%d %s\n",
4910 argreg, paddress (gdbarch, struct_addr));
4911 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4914 /* Now load as many as possible of the first arguments into
4915 registers, and push the rest onto the stack. Loop thru args
4916 from first to last. */
4917 for (argnum = 0; argnum < nargs; argnum++)
4919 const gdb_byte *val;
4920 struct value *arg = args[argnum];
4921 struct type *arg_type = check_typedef (value_type (arg));
4922 int len = TYPE_LENGTH (arg_type);
4923 enum type_code typecode = TYPE_CODE (arg_type);
4926 fprintf_unfiltered (gdb_stdlog,
4927 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4928 argnum + 1, len, (int) typecode);
4930 val = value_contents (arg);
4932 /* A 128-bit long double value requires an even-odd pair of
4933 floating-point registers. */
4935 && fp_register_arg_p (gdbarch, typecode, arg_type)
4936 && (float_argreg & 1))
4942 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4943 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4945 /* This is a floating point value that fits entirely
4946 in a single register or a pair of registers. */
4947 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4948 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
4950 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4951 float_argreg, phex (regval, reglen));
4952 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4955 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4956 argreg, phex (regval, reglen));
4957 regcache_cooked_write_unsigned (regcache, argreg, regval);
4962 regval = extract_unsigned_integer (val + reglen,
4963 reglen, byte_order);
4965 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4966 float_argreg, phex (regval, reglen));
4967 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4970 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4971 argreg, phex (regval, reglen));
4972 regcache_cooked_write_unsigned (regcache, argreg, regval);
4979 /* Copy the argument to general registers or the stack in
4980 register-sized pieces. Large arguments are split between
4981 registers and stack. */
4982 /* For N32/N64, structs, unions, or other composite types are
4983 treated as a sequence of doublewords, and are passed in integer
4984 or floating point registers as though they were simple scalar
4985 parameters to the extent that they fit, with any excess on the
4986 stack packed according to the normal memory layout of the
4988 The caller does not reserve space for the register arguments;
4989 the callee is responsible for reserving it if required. */
4990 /* Note: Floating-point values that didn't fit into an FP
4991 register are only written to memory. */
4994 /* Remember if the argument was written to the stack. */
4995 int stack_used_p = 0;
4996 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4999 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5002 if (fp_register_arg_p (gdbarch, typecode, arg_type))
5003 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
5005 /* Write this portion of the argument to the stack. */
5006 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
5008 /* Should shorter than int integer values be
5009 promoted to int before being stored? */
5010 int longword_offset = 0;
5013 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5015 if ((typecode == TYPE_CODE_INT
5016 || typecode == TYPE_CODE_PTR)
5018 longword_offset = MIPS64_REGSIZE - len;
5023 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5024 paddress (gdbarch, stack_offset));
5025 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5026 paddress (gdbarch, longword_offset));
5029 addr = sp + stack_offset + longword_offset;
5034 fprintf_unfiltered (gdb_stdlog, " @%s ",
5035 paddress (gdbarch, addr));
5036 for (i = 0; i < partial_len; i++)
5038 fprintf_unfiltered (gdb_stdlog, "%02x",
5042 write_memory (addr, val, partial_len);
5045 /* Note!!! This is NOT an else clause. Odd sized
5046 structs may go thru BOTH paths. */
5047 /* Write this portion of the argument to a general
5048 purpose register. */
5049 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5053 /* Sign extend pointers, 32-bit integers and signed
5054 16-bit and 8-bit integers; everything else is taken
5057 if ((partial_len == 4
5058 && (typecode == TYPE_CODE_PTR
5059 || typecode == TYPE_CODE_INT))
5061 && typecode == TYPE_CODE_INT
5062 && !TYPE_UNSIGNED (arg_type)))
5063 regval = extract_signed_integer (val, partial_len,
5066 regval = extract_unsigned_integer (val, partial_len,
5069 /* A non-floating-point argument being passed in a
5070 general register. If a struct or union, and if
5071 the remaining length is smaller than the register
5072 size, we have to adjust the register value on
5075 It does not seem to be necessary to do the
5076 same for integral types. */
5078 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5079 && partial_len < MIPS64_REGSIZE
5080 && (typecode == TYPE_CODE_STRUCT
5081 || typecode == TYPE_CODE_UNION))
5082 regval <<= ((MIPS64_REGSIZE - partial_len)
5086 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5088 phex (regval, MIPS64_REGSIZE));
5089 regcache_cooked_write_unsigned (regcache, argreg, regval);
5091 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
5092 TYPE_LENGTH (arg_type) - len))
5095 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
5097 phex (regval, MIPS64_REGSIZE));
5098 regcache_cooked_write_unsigned (regcache, float_argreg,
5109 /* Compute the offset into the stack at which we will
5110 copy the next parameter.
5112 In N32 (N64?), the stack_offset only needs to be
5113 adjusted when it has been used. */
5116 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
5120 fprintf_unfiltered (gdb_stdlog, "\n");
5123 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5125 /* Return adjusted stack pointer. */
5129 static enum return_value_convention
5130 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function,
5131 struct type *type, struct regcache *regcache,
5132 gdb_byte *readbuf, const gdb_byte *writebuf)
5134 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5136 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5138 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5139 if needed), as appropriate for the type. Composite results (struct,
5140 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5143 * A struct with only one or two floating point fields is returned in $f0
5144 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5147 * Any other composite results of at most 128 bits are returned in
5148 $2 (first 64 bits) and $3 (remainder, if necessary).
5150 * Larger composite results are handled by converting the function to a
5151 procedure with an implicit first parameter, which is a pointer to an area
5152 reserved by the caller to receive the result. [The o32-bit ABI requires
5153 that all composite results be handled by conversion to implicit first
5154 parameters. The MIPS/SGI Fortran implementation has always made a
5155 specific exception to return COMPLEX results in the floating point
5158 if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
5159 return RETURN_VALUE_STRUCT_CONVENTION;
5160 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5161 && TYPE_LENGTH (type) == 16
5162 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5164 /* A 128-bit floating-point value fills both $f0 and $f2. The
5165 two registers are used in the same as memory order, so the
5166 eight bytes with the lower memory address are in $f0. */
5168 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
5169 mips_xfer_register (gdbarch, regcache,
5170 (gdbarch_num_regs (gdbarch)
5171 + mips_regnum (gdbarch)->fp0),
5172 8, gdbarch_byte_order (gdbarch),
5173 readbuf, writebuf, 0);
5174 mips_xfer_register (gdbarch, regcache,
5175 (gdbarch_num_regs (gdbarch)
5176 + mips_regnum (gdbarch)->fp0 + 2),
5177 8, gdbarch_byte_order (gdbarch),
5178 readbuf ? readbuf + 8 : readbuf,
5179 writebuf ? writebuf + 8 : writebuf, 0);
5180 return RETURN_VALUE_REGISTER_CONVENTION;
5182 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5183 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5185 /* A single or double floating-point value that fits in FP0. */
5187 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5188 mips_xfer_register (gdbarch, regcache,
5189 (gdbarch_num_regs (gdbarch)
5190 + mips_regnum (gdbarch)->fp0),
5192 gdbarch_byte_order (gdbarch),
5193 readbuf, writebuf, 0);
5194 return RETURN_VALUE_REGISTER_CONVENTION;
5196 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5197 && TYPE_NFIELDS (type) <= 2
5198 && TYPE_NFIELDS (type) >= 1
5199 && ((TYPE_NFIELDS (type) == 1
5200 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5202 || (TYPE_NFIELDS (type) == 2
5203 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5205 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
5206 == TYPE_CODE_FLT))))
5208 /* A struct that contains one or two floats. Each value is part
5209 in the least significant part of their floating point
5210 register (or GPR, for soft float). */
5213 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
5214 ? mips_regnum (gdbarch)->fp0
5216 field < TYPE_NFIELDS (type); field++, regnum += 2)
5218 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5221 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5223 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
5225 /* A 16-byte long double field goes in two consecutive
5227 mips_xfer_register (gdbarch, regcache,
5228 gdbarch_num_regs (gdbarch) + regnum,
5230 gdbarch_byte_order (gdbarch),
5231 readbuf, writebuf, offset);
5232 mips_xfer_register (gdbarch, regcache,
5233 gdbarch_num_regs (gdbarch) + regnum + 1,
5235 gdbarch_byte_order (gdbarch),
5236 readbuf, writebuf, offset + 8);
5239 mips_xfer_register (gdbarch, regcache,
5240 gdbarch_num_regs (gdbarch) + regnum,
5241 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5242 gdbarch_byte_order (gdbarch),
5243 readbuf, writebuf, offset);
5245 return RETURN_VALUE_REGISTER_CONVENTION;
5247 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5248 || TYPE_CODE (type) == TYPE_CODE_UNION
5249 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5251 /* A composite type. Extract the left justified value,
5252 regardless of the byte order. I.e. DO NOT USE
5256 for (offset = 0, regnum = MIPS_V0_REGNUM;
5257 offset < TYPE_LENGTH (type);
5258 offset += register_size (gdbarch, regnum), regnum++)
5260 int xfer = register_size (gdbarch, regnum);
5261 if (offset + xfer > TYPE_LENGTH (type))
5262 xfer = TYPE_LENGTH (type) - offset;
5264 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5265 offset, xfer, regnum);
5266 mips_xfer_register (gdbarch, regcache,
5267 gdbarch_num_regs (gdbarch) + regnum,
5268 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
5271 return RETURN_VALUE_REGISTER_CONVENTION;
5275 /* A scalar extract each part but least-significant-byte
5279 for (offset = 0, regnum = MIPS_V0_REGNUM;
5280 offset < TYPE_LENGTH (type);
5281 offset += register_size (gdbarch, regnum), regnum++)
5283 int xfer = register_size (gdbarch, regnum);
5284 if (offset + xfer > TYPE_LENGTH (type))
5285 xfer = TYPE_LENGTH (type) - offset;
5287 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5288 offset, xfer, regnum);
5289 mips_xfer_register (gdbarch, regcache,
5290 gdbarch_num_regs (gdbarch) + regnum,
5291 xfer, gdbarch_byte_order (gdbarch),
5292 readbuf, writebuf, offset);
5294 return RETURN_VALUE_REGISTER_CONVENTION;
5298 /* Which registers to use for passing floating-point values between
5299 function calls, one of floating-point, general and both kinds of
5300 registers. O32 and O64 use different register kinds for standard
5301 MIPS and MIPS16 code; to make the handling of cases where we may
5302 not know what kind of code is being used (e.g. no debug information)
5303 easier we sometimes use both kinds. */
5312 /* O32 ABI stuff. */
5315 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5316 struct regcache *regcache, CORE_ADDR bp_addr,
5317 int nargs, struct value **args, CORE_ADDR sp,
5318 int struct_return, CORE_ADDR struct_addr)
5324 int stack_offset = 0;
5325 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5326 CORE_ADDR func_addr = find_function_addr (function, NULL);
5328 /* For shared libraries, "t9" needs to point at the function
5330 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5332 /* Set the return address register to point to the entry point of
5333 the program, where a breakpoint lies in wait. */
5334 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5336 /* First ensure that the stack and structure return address (if any)
5337 are properly aligned. The stack has to be at least 64-bit
5338 aligned even on 32-bit machines, because doubles must be 64-bit
5339 aligned. For n32 and n64, stack frames need to be 128-bit
5340 aligned, so we round to this widest known alignment. */
5342 sp = align_down (sp, 16);
5343 struct_addr = align_down (struct_addr, 16);
5345 /* Now make space on the stack for the args. */
5346 for (argnum = 0; argnum < nargs; argnum++)
5348 struct type *arg_type = check_typedef (value_type (args[argnum]));
5350 /* Align to double-word if necessary. */
5351 if (mips_type_needs_double_align (arg_type))
5352 len = align_up (len, MIPS32_REGSIZE * 2);
5353 /* Allocate space on the stack. */
5354 len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE);
5356 sp -= align_up (len, 16);
5359 fprintf_unfiltered (gdb_stdlog,
5360 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5361 paddress (gdbarch, sp), (long) align_up (len, 16));
5363 /* Initialize the integer and float register pointers. */
5364 argreg = MIPS_A0_REGNUM;
5365 float_argreg = mips_fpa0_regnum (gdbarch);
5367 /* The struct_return pointer occupies the first parameter-passing reg. */
5371 fprintf_unfiltered (gdb_stdlog,
5372 "mips_o32_push_dummy_call: "
5373 "struct_return reg=%d %s\n",
5374 argreg, paddress (gdbarch, struct_addr));
5375 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5376 stack_offset += MIPS32_REGSIZE;
5379 /* Now load as many as possible of the first arguments into
5380 registers, and push the rest onto the stack. Loop thru args
5381 from first to last. */
5382 for (argnum = 0; argnum < nargs; argnum++)
5384 const gdb_byte *val;
5385 struct value *arg = args[argnum];
5386 struct type *arg_type = check_typedef (value_type (arg));
5387 int len = TYPE_LENGTH (arg_type);
5388 enum type_code typecode = TYPE_CODE (arg_type);
5391 fprintf_unfiltered (gdb_stdlog,
5392 "mips_o32_push_dummy_call: %d len=%d type=%d",
5393 argnum + 1, len, (int) typecode);
5395 val = value_contents (arg);
5397 /* 32-bit ABIs always start floating point arguments in an
5398 even-numbered floating point register. Round the FP register
5399 up before the check to see if there are any FP registers
5400 left. O32 targets also pass the FP in the integer registers
5401 so also round up normal registers. */
5402 if (fp_register_arg_p (gdbarch, typecode, arg_type))
5404 if ((float_argreg & 1))
5408 /* Floating point arguments passed in registers have to be
5409 treated specially. On 32-bit architectures, doubles are
5410 passed in register pairs; the even FP register gets the
5411 low word, and the odd FP register gets the high word.
5412 On O32, the first two floating point arguments are also
5413 copied to general registers, following their memory order,
5414 because MIPS16 functions don't use float registers for
5415 arguments. This duplication of arguments in general
5416 registers can't hurt non-MIPS16 functions, because those
5417 registers are normally skipped. */
5419 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5420 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5422 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
5424 int freg_offset = gdbarch_byte_order (gdbarch)
5425 == BFD_ENDIAN_BIG ? 1 : 0;
5426 unsigned long regval;
5429 regval = extract_unsigned_integer (val, 4, byte_order);
5431 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5432 float_argreg + freg_offset,
5434 regcache_cooked_write_unsigned (regcache,
5435 float_argreg++ + freg_offset,
5438 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5439 argreg, phex (regval, 4));
5440 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5443 regval = extract_unsigned_integer (val + 4, 4, byte_order);
5445 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5446 float_argreg - freg_offset,
5448 regcache_cooked_write_unsigned (regcache,
5449 float_argreg++ - freg_offset,
5452 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5453 argreg, phex (regval, 4));
5454 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5458 /* This is a floating point value that fits entirely
5459 in a single register. */
5460 /* On 32 bit ABI's the float_argreg is further adjusted
5461 above to ensure that it is even register aligned. */
5462 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5464 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5465 float_argreg, phex (regval, len));
5466 regcache_cooked_write_unsigned (regcache,
5467 float_argreg++, regval);
5468 /* Although two FP registers are reserved for each
5469 argument, only one corresponding integer register is
5472 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5473 argreg, phex (regval, len));
5474 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5476 /* Reserve space for the FP register. */
5477 stack_offset += align_up (len, MIPS32_REGSIZE);
5481 /* Copy the argument to general registers or the stack in
5482 register-sized pieces. Large arguments are split between
5483 registers and stack. */
5484 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5485 are treated specially: Irix cc passes
5486 them in registers where gcc sometimes puts them on the
5487 stack. For maximum compatibility, we will put them in
5489 int odd_sized_struct = (len > MIPS32_REGSIZE
5490 && len % MIPS32_REGSIZE != 0);
5491 /* Structures should be aligned to eight bytes (even arg registers)
5492 on MIPS_ABI_O32, if their first member has double precision. */
5493 if (mips_type_needs_double_align (arg_type))
5498 stack_offset += MIPS32_REGSIZE;
5503 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
5506 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5509 /* Write this portion of the argument to the stack. */
5510 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5511 || odd_sized_struct)
5513 /* Should shorter than int integer values be
5514 promoted to int before being stored? */
5515 int longword_offset = 0;
5520 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5521 paddress (gdbarch, stack_offset));
5522 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5523 paddress (gdbarch, longword_offset));
5526 addr = sp + stack_offset + longword_offset;
5531 fprintf_unfiltered (gdb_stdlog, " @%s ",
5532 paddress (gdbarch, addr));
5533 for (i = 0; i < partial_len; i++)
5535 fprintf_unfiltered (gdb_stdlog, "%02x",
5539 write_memory (addr, val, partial_len);
5542 /* Note!!! This is NOT an else clause. Odd sized
5543 structs may go thru BOTH paths. */
5544 /* Write this portion of the argument to a general
5545 purpose register. */
5546 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5548 LONGEST regval = extract_signed_integer (val, partial_len,
5550 /* Value may need to be sign extended, because
5551 mips_isa_regsize() != mips_abi_regsize(). */
5553 /* A non-floating-point argument being passed in a
5554 general register. If a struct or union, and if
5555 the remaining length is smaller than the register
5556 size, we have to adjust the register value on
5559 It does not seem to be necessary to do the
5560 same for integral types.
5562 Also don't do this adjustment on O64 binaries.
5564 cagney/2001-07-23: gdb/179: Also, GCC, when
5565 outputting LE O32 with sizeof (struct) <
5566 mips_abi_regsize(), generates a left shift
5567 as part of storing the argument in a register
5568 (the left shift isn't generated when
5569 sizeof (struct) >= mips_abi_regsize()). Since
5570 it is quite possible that this is GCC
5571 contradicting the LE/O32 ABI, GDB has not been
5572 adjusted to accommodate this. Either someone
5573 needs to demonstrate that the LE/O32 ABI
5574 specifies such a left shift OR this new ABI gets
5575 identified as such and GDB gets tweaked
5578 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5579 && partial_len < MIPS32_REGSIZE
5580 && (typecode == TYPE_CODE_STRUCT
5581 || typecode == TYPE_CODE_UNION))
5582 regval <<= ((MIPS32_REGSIZE - partial_len)
5586 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5588 phex (regval, MIPS32_REGSIZE));
5589 regcache_cooked_write_unsigned (regcache, argreg, regval);
5592 /* Prevent subsequent floating point arguments from
5593 being passed in floating point registers. */
5594 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
5600 /* Compute the offset into the stack at which we will
5601 copy the next parameter.
5603 In older ABIs, the caller reserved space for
5604 registers that contained arguments. This was loosely
5605 refered to as their "home". Consequently, space is
5606 always allocated. */
5608 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
5612 fprintf_unfiltered (gdb_stdlog, "\n");
5615 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5617 /* Return adjusted stack pointer. */
5621 static enum return_value_convention
5622 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function,
5623 struct type *type, struct regcache *regcache,
5624 gdb_byte *readbuf, const gdb_byte *writebuf)
5626 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
5627 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
5628 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5629 enum mips_fval_reg fval_reg;
5631 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
5632 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5633 || TYPE_CODE (type) == TYPE_CODE_UNION
5634 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5635 return RETURN_VALUE_STRUCT_CONVENTION;
5636 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5637 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5639 /* A single-precision floating-point value. If reading in or copying,
5640 then we get it from/put it to FP0 for standard MIPS code or GPR2
5641 for MIPS16 code. If writing out only, then we put it to both FP0
5642 and GPR2. We do not support reading in with no function known, if
5643 this safety check ever triggers, then we'll have to try harder. */
5644 gdb_assert (function || !readbuf);
5649 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5652 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
5654 case mips_fval_both:
5655 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
5658 if (fval_reg != mips_fval_gpr)
5659 mips_xfer_register (gdbarch, regcache,
5660 (gdbarch_num_regs (gdbarch)
5661 + mips_regnum (gdbarch)->fp0),
5663 gdbarch_byte_order (gdbarch),
5664 readbuf, writebuf, 0);
5665 if (fval_reg != mips_fval_fpr)
5666 mips_xfer_register (gdbarch, regcache,
5667 gdbarch_num_regs (gdbarch) + 2,
5669 gdbarch_byte_order (gdbarch),
5670 readbuf, writebuf, 0);
5671 return RETURN_VALUE_REGISTER_CONVENTION;
5673 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5674 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5676 /* A double-precision floating-point value. If reading in or copying,
5677 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5678 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5679 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5680 no function known, if this safety check ever triggers, then we'll
5681 have to try harder. */
5682 gdb_assert (function || !readbuf);
5687 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
5690 fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n");
5692 case mips_fval_both:
5693 fprintf_unfiltered (gdb_stderr,
5694 "Return float in $fp1/$fp0 and $2/$3\n");
5697 if (fval_reg != mips_fval_gpr)
5699 /* The most significant part goes in FP1, and the least significant
5701 switch (gdbarch_byte_order (gdbarch))
5703 case BFD_ENDIAN_LITTLE:
5704 mips_xfer_register (gdbarch, regcache,
5705 (gdbarch_num_regs (gdbarch)
5706 + mips_regnum (gdbarch)->fp0 + 0),
5707 4, gdbarch_byte_order (gdbarch),
5708 readbuf, writebuf, 0);
5709 mips_xfer_register (gdbarch, regcache,
5710 (gdbarch_num_regs (gdbarch)
5711 + mips_regnum (gdbarch)->fp0 + 1),
5712 4, gdbarch_byte_order (gdbarch),
5713 readbuf, writebuf, 4);
5715 case BFD_ENDIAN_BIG:
5716 mips_xfer_register (gdbarch, regcache,
5717 (gdbarch_num_regs (gdbarch)
5718 + mips_regnum (gdbarch)->fp0 + 1),
5719 4, gdbarch_byte_order (gdbarch),
5720 readbuf, writebuf, 0);
5721 mips_xfer_register (gdbarch, regcache,
5722 (gdbarch_num_regs (gdbarch)
5723 + mips_regnum (gdbarch)->fp0 + 0),
5724 4, gdbarch_byte_order (gdbarch),
5725 readbuf, writebuf, 4);
5728 internal_error (__FILE__, __LINE__, _("bad switch"));
5731 if (fval_reg != mips_fval_fpr)
5733 /* The two 32-bit parts are always placed in GPR2 and GPR3
5734 following these registers' memory order. */
5735 mips_xfer_register (gdbarch, regcache,
5736 gdbarch_num_regs (gdbarch) + 2,
5737 4, gdbarch_byte_order (gdbarch),
5738 readbuf, writebuf, 0);
5739 mips_xfer_register (gdbarch, regcache,
5740 gdbarch_num_regs (gdbarch) + 3,
5741 4, gdbarch_byte_order (gdbarch),
5742 readbuf, writebuf, 4);
5744 return RETURN_VALUE_REGISTER_CONVENTION;
5747 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5748 && TYPE_NFIELDS (type) <= 2
5749 && TYPE_NFIELDS (type) >= 1
5750 && ((TYPE_NFIELDS (type) == 1
5751 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5753 || (TYPE_NFIELDS (type) == 2
5754 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5756 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
5758 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5760 /* A struct that contains one or two floats. Each value is part
5761 in the least significant part of their floating point
5765 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
5766 field < TYPE_NFIELDS (type); field++, regnum += 2)
5768 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5771 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5773 mips_xfer_register (gdbarch, regcache,
5774 gdbarch_num_regs (gdbarch) + regnum,
5775 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5776 gdbarch_byte_order (gdbarch),
5777 readbuf, writebuf, offset);
5779 return RETURN_VALUE_REGISTER_CONVENTION;
5783 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5784 || TYPE_CODE (type) == TYPE_CODE_UNION)
5786 /* A structure or union. Extract the left justified value,
5787 regardless of the byte order. I.e. DO NOT USE
5791 for (offset = 0, regnum = MIPS_V0_REGNUM;
5792 offset < TYPE_LENGTH (type);
5793 offset += register_size (gdbarch, regnum), regnum++)
5795 int xfer = register_size (gdbarch, regnum);
5796 if (offset + xfer > TYPE_LENGTH (type))
5797 xfer = TYPE_LENGTH (type) - offset;
5799 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5800 offset, xfer, regnum);
5801 mips_xfer_register (gdbarch, regcache,
5802 gdbarch_num_regs (gdbarch) + regnum, xfer,
5803 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
5805 return RETURN_VALUE_REGISTER_CONVENTION;
5810 /* A scalar extract each part but least-significant-byte
5811 justified. o32 thinks registers are 4 byte, regardless of
5815 for (offset = 0, regnum = MIPS_V0_REGNUM;
5816 offset < TYPE_LENGTH (type);
5817 offset += MIPS32_REGSIZE, regnum++)
5819 int xfer = MIPS32_REGSIZE;
5820 if (offset + xfer > TYPE_LENGTH (type))
5821 xfer = TYPE_LENGTH (type) - offset;
5823 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5824 offset, xfer, regnum);
5825 mips_xfer_register (gdbarch, regcache,
5826 gdbarch_num_regs (gdbarch) + regnum, xfer,
5827 gdbarch_byte_order (gdbarch),
5828 readbuf, writebuf, offset);
5830 return RETURN_VALUE_REGISTER_CONVENTION;
5834 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5838 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5839 struct regcache *regcache, CORE_ADDR bp_addr,
5841 struct value **args, CORE_ADDR sp,
5842 int struct_return, CORE_ADDR struct_addr)
5848 int stack_offset = 0;
5849 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5850 CORE_ADDR func_addr = find_function_addr (function, NULL);
5852 /* For shared libraries, "t9" needs to point at the function
5854 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5856 /* Set the return address register to point to the entry point of
5857 the program, where a breakpoint lies in wait. */
5858 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5860 /* First ensure that the stack and structure return address (if any)
5861 are properly aligned. The stack has to be at least 64-bit
5862 aligned even on 32-bit machines, because doubles must be 64-bit
5863 aligned. For n32 and n64, stack frames need to be 128-bit
5864 aligned, so we round to this widest known alignment. */
5866 sp = align_down (sp, 16);
5867 struct_addr = align_down (struct_addr, 16);
5869 /* Now make space on the stack for the args. */
5870 for (argnum = 0; argnum < nargs; argnum++)
5872 struct type *arg_type = check_typedef (value_type (args[argnum]));
5874 /* Allocate space on the stack. */
5875 len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE);
5877 sp -= align_up (len, 16);
5880 fprintf_unfiltered (gdb_stdlog,
5881 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5882 paddress (gdbarch, sp), (long) align_up (len, 16));
5884 /* Initialize the integer and float register pointers. */
5885 argreg = MIPS_A0_REGNUM;
5886 float_argreg = mips_fpa0_regnum (gdbarch);
5888 /* The struct_return pointer occupies the first parameter-passing reg. */
5892 fprintf_unfiltered (gdb_stdlog,
5893 "mips_o64_push_dummy_call: "
5894 "struct_return reg=%d %s\n",
5895 argreg, paddress (gdbarch, struct_addr));
5896 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5897 stack_offset += MIPS64_REGSIZE;
5900 /* Now load as many as possible of the first arguments into
5901 registers, and push the rest onto the stack. Loop thru args
5902 from first to last. */
5903 for (argnum = 0; argnum < nargs; argnum++)
5905 const gdb_byte *val;
5906 struct value *arg = args[argnum];
5907 struct type *arg_type = check_typedef (value_type (arg));
5908 int len = TYPE_LENGTH (arg_type);
5909 enum type_code typecode = TYPE_CODE (arg_type);
5912 fprintf_unfiltered (gdb_stdlog,
5913 "mips_o64_push_dummy_call: %d len=%d type=%d",
5914 argnum + 1, len, (int) typecode);
5916 val = value_contents (arg);
5918 /* Floating point arguments passed in registers have to be
5919 treated specially. On 32-bit architectures, doubles are
5920 passed in register pairs; the even FP register gets the
5921 low word, and the odd FP register gets the high word.
5922 On O64, the first two floating point arguments are also
5923 copied to general registers, because MIPS16 functions
5924 don't use float registers for arguments. This duplication
5925 of arguments in general registers can't hurt non-MIPS16
5926 functions because those registers are normally skipped. */
5928 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5929 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5931 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5933 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5934 float_argreg, phex (regval, len));
5935 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
5937 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5938 argreg, phex (regval, len));
5939 regcache_cooked_write_unsigned (regcache, argreg, regval);
5941 /* Reserve space for the FP register. */
5942 stack_offset += align_up (len, MIPS64_REGSIZE);
5946 /* Copy the argument to general registers or the stack in
5947 register-sized pieces. Large arguments are split between
5948 registers and stack. */
5949 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5950 are treated specially: Irix cc passes them in registers
5951 where gcc sometimes puts them on the stack. For maximum
5952 compatibility, we will put them in both places. */
5953 int odd_sized_struct = (len > MIPS64_REGSIZE
5954 && len % MIPS64_REGSIZE != 0);
5957 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
5960 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5963 /* Write this portion of the argument to the stack. */
5964 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5965 || odd_sized_struct)
5967 /* Should shorter than int integer values be
5968 promoted to int before being stored? */
5969 int longword_offset = 0;
5971 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5973 if ((typecode == TYPE_CODE_INT
5974 || typecode == TYPE_CODE_PTR
5975 || typecode == TYPE_CODE_FLT)
5977 longword_offset = MIPS64_REGSIZE - len;
5982 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5983 paddress (gdbarch, stack_offset));
5984 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5985 paddress (gdbarch, longword_offset));
5988 addr = sp + stack_offset + longword_offset;
5993 fprintf_unfiltered (gdb_stdlog, " @%s ",
5994 paddress (gdbarch, addr));
5995 for (i = 0; i < partial_len; i++)
5997 fprintf_unfiltered (gdb_stdlog, "%02x",
6001 write_memory (addr, val, partial_len);
6004 /* Note!!! This is NOT an else clause. Odd sized
6005 structs may go thru BOTH paths. */
6006 /* Write this portion of the argument to a general
6007 purpose register. */
6008 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
6010 LONGEST regval = extract_signed_integer (val, partial_len,
6012 /* Value may need to be sign extended, because
6013 mips_isa_regsize() != mips_abi_regsize(). */
6015 /* A non-floating-point argument being passed in a
6016 general register. If a struct or union, and if
6017 the remaining length is smaller than the register
6018 size, we have to adjust the register value on
6021 It does not seem to be necessary to do the
6022 same for integral types. */
6024 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
6025 && partial_len < MIPS64_REGSIZE
6026 && (typecode == TYPE_CODE_STRUCT
6027 || typecode == TYPE_CODE_UNION))
6028 regval <<= ((MIPS64_REGSIZE - partial_len)
6032 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
6034 phex (regval, MIPS64_REGSIZE));
6035 regcache_cooked_write_unsigned (regcache, argreg, regval);
6038 /* Prevent subsequent floating point arguments from
6039 being passed in floating point registers. */
6040 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
6046 /* Compute the offset into the stack at which we will
6047 copy the next parameter.
6049 In older ABIs, the caller reserved space for
6050 registers that contained arguments. This was loosely
6051 refered to as their "home". Consequently, space is
6052 always allocated. */
6054 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
6058 fprintf_unfiltered (gdb_stdlog, "\n");
6061 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
6063 /* Return adjusted stack pointer. */
6067 static enum return_value_convention
6068 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function,
6069 struct type *type, struct regcache *regcache,
6070 gdb_byte *readbuf, const gdb_byte *writebuf)
6072 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
6073 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
6074 enum mips_fval_reg fval_reg;
6076 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
6077 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
6078 || TYPE_CODE (type) == TYPE_CODE_UNION
6079 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
6080 return RETURN_VALUE_STRUCT_CONVENTION;
6081 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
6083 /* A floating-point value. If reading in or copying, then we get it
6084 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6085 If writing out only, then we put it to both FP0 and GPR2. We do
6086 not support reading in with no function known, if this safety
6087 check ever triggers, then we'll have to try harder. */
6088 gdb_assert (function || !readbuf);
6093 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
6096 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
6098 case mips_fval_both:
6099 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
6102 if (fval_reg != mips_fval_gpr)
6103 mips_xfer_register (gdbarch, regcache,
6104 (gdbarch_num_regs (gdbarch)
6105 + mips_regnum (gdbarch)->fp0),
6107 gdbarch_byte_order (gdbarch),
6108 readbuf, writebuf, 0);
6109 if (fval_reg != mips_fval_fpr)
6110 mips_xfer_register (gdbarch, regcache,
6111 gdbarch_num_regs (gdbarch) + 2,
6113 gdbarch_byte_order (gdbarch),
6114 readbuf, writebuf, 0);
6115 return RETURN_VALUE_REGISTER_CONVENTION;
6119 /* A scalar extract each part but least-significant-byte
6123 for (offset = 0, regnum = MIPS_V0_REGNUM;
6124 offset < TYPE_LENGTH (type);
6125 offset += MIPS64_REGSIZE, regnum++)
6127 int xfer = MIPS64_REGSIZE;
6128 if (offset + xfer > TYPE_LENGTH (type))
6129 xfer = TYPE_LENGTH (type) - offset;
6131 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
6132 offset, xfer, regnum);
6133 mips_xfer_register (gdbarch, regcache,
6134 gdbarch_num_regs (gdbarch) + regnum,
6135 xfer, gdbarch_byte_order (gdbarch),
6136 readbuf, writebuf, offset);
6138 return RETURN_VALUE_REGISTER_CONVENTION;
6142 /* Floating point register management.
6144 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6145 64bit operations, these early MIPS cpus treat fp register pairs
6146 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6147 registers and offer a compatibility mode that emulates the MIPS2 fp
6148 model. When operating in MIPS2 fp compat mode, later cpu's split
6149 double precision floats into two 32-bit chunks and store them in
6150 consecutive fp regs. To display 64-bit floats stored in this
6151 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6152 Throw in user-configurable endianness and you have a real mess.
6154 The way this works is:
6155 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6156 double-precision value will be split across two logical registers.
6157 The lower-numbered logical register will hold the low-order bits,
6158 regardless of the processor's endianness.
6159 - If we are on a 64-bit processor, and we are looking for a
6160 single-precision value, it will be in the low ordered bits
6161 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6162 save slot in memory.
6163 - If we are in 64-bit mode, everything is straightforward.
6165 Note that this code only deals with "live" registers at the top of the
6166 stack. We will attempt to deal with saved registers later, when
6167 the raw/cooked register interface is in place. (We need a general
6168 interface that can deal with dynamic saved register sizes -- fp
6169 regs could be 32 bits wide in one frame and 64 on the frame above
6172 /* Copy a 32-bit single-precision value from the current frame
6173 into rare_buffer. */
6176 mips_read_fp_register_single (struct frame_info *frame, int regno,
6177 gdb_byte *rare_buffer)
6179 struct gdbarch *gdbarch = get_frame_arch (frame);
6180 int raw_size = register_size (gdbarch, regno);
6181 gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size);
6183 if (!deprecated_frame_register_read (frame, regno, raw_buffer))
6184 error (_("can't read register %d (%s)"),
6185 regno, gdbarch_register_name (gdbarch, regno));
6188 /* We have a 64-bit value for this register. Find the low-order
6192 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6197 memcpy (rare_buffer, raw_buffer + offset, 4);
6201 memcpy (rare_buffer, raw_buffer, 4);
6205 /* Copy a 64-bit double-precision value from the current frame into
6206 rare_buffer. This may include getting half of it from the next
6210 mips_read_fp_register_double (struct frame_info *frame, int regno,
6211 gdb_byte *rare_buffer)
6213 struct gdbarch *gdbarch = get_frame_arch (frame);
6214 int raw_size = register_size (gdbarch, regno);
6216 if (raw_size == 8 && !mips2_fp_compat (frame))
6218 /* We have a 64-bit value for this register, and we should use
6220 if (!deprecated_frame_register_read (frame, regno, rare_buffer))
6221 error (_("can't read register %d (%s)"),
6222 regno, gdbarch_register_name (gdbarch, regno));
6226 int rawnum = regno % gdbarch_num_regs (gdbarch);
6228 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
6229 internal_error (__FILE__, __LINE__,
6230 _("mips_read_fp_register_double: bad access to "
6231 "odd-numbered FP register"));
6233 /* mips_read_fp_register_single will find the correct 32 bits from
6235 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6237 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
6238 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
6242 mips_read_fp_register_single (frame, regno, rare_buffer);
6243 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
6249 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
6251 { /* Do values for FP (float) regs. */
6252 struct gdbarch *gdbarch = get_frame_arch (frame);
6253 gdb_byte *raw_buffer;
6254 std::string flt_str, dbl_str;
6256 const struct type *flt_type = builtin_type (gdbarch)->builtin_float;
6257 const struct type *dbl_type = builtin_type (gdbarch)->builtin_double;
6261 alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)));
6263 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
6264 fprintf_filtered (file, "%*s",
6265 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
6268 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
6270 struct value_print_options opts;
6272 /* 4-byte registers: Print hex and floating. Also print even
6273 numbered registers as doubles. */
6274 mips_read_fp_register_single (frame, regnum, raw_buffer);
6275 flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g");
6277 get_formatted_print_options (&opts, 'x');
6278 print_scalar_formatted (raw_buffer,
6279 builtin_type (gdbarch)->builtin_uint32,
6282 fprintf_filtered (file, " flt: %s", flt_str.c_str ());
6284 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
6286 mips_read_fp_register_double (frame, regnum, raw_buffer);
6287 dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g");
6289 fprintf_filtered (file, " dbl: %s", dbl_str.c_str ());
6294 struct value_print_options opts;
6296 /* Eight byte registers: print each one as hex, float and double. */
6297 mips_read_fp_register_single (frame, regnum, raw_buffer);
6298 flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g");
6300 mips_read_fp_register_double (frame, regnum, raw_buffer);
6301 dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g");
6303 get_formatted_print_options (&opts, 'x');
6304 print_scalar_formatted (raw_buffer,
6305 builtin_type (gdbarch)->builtin_uint64,
6308 fprintf_filtered (file, " flt: %s", flt_str.c_str ());
6309 fprintf_filtered (file, " dbl: %s", dbl_str.c_str ());
6314 mips_print_register (struct ui_file *file, struct frame_info *frame,
6317 struct gdbarch *gdbarch = get_frame_arch (frame);
6318 struct value_print_options opts;
6321 if (mips_float_register_p (gdbarch, regnum))
6323 mips_print_fp_register (file, frame, regnum);
6327 val = get_frame_register_value (frame, regnum);
6329 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
6331 /* The problem with printing numeric register names (r26, etc.) is that
6332 the user can't use them on input. Probably the best solution is to
6333 fix it so that either the numeric or the funky (a2, etc.) names
6334 are accepted on input. */
6335 if (regnum < MIPS_NUMREGS)
6336 fprintf_filtered (file, "(r%d): ", regnum);
6338 fprintf_filtered (file, ": ");
6340 get_formatted_print_options (&opts, 'x');
6341 val_print_scalar_formatted (value_type (val),
6342 value_embedded_offset (val),
6347 /* Print IEEE exception condition bits in FLAGS. */
6350 print_fpu_flags (struct ui_file *file, int flags)
6352 if (flags & (1 << 0))
6353 fputs_filtered (" inexact", file);
6354 if (flags & (1 << 1))
6355 fputs_filtered (" uflow", file);
6356 if (flags & (1 << 2))
6357 fputs_filtered (" oflow", file);
6358 if (flags & (1 << 3))
6359 fputs_filtered (" div0", file);
6360 if (flags & (1 << 4))
6361 fputs_filtered (" inval", file);
6362 if (flags & (1 << 5))
6363 fputs_filtered (" unimp", file);
6364 fputc_filtered ('\n', file);
6367 /* Print interesting information about the floating point processor
6368 (if present) or emulator. */
6371 mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
6372 struct frame_info *frame, const char *args)
6374 int fcsr = mips_regnum (gdbarch)->fp_control_status;
6375 enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch);
6379 if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs))
6380 type = MIPS_FPU_NONE;
6382 fprintf_filtered (file, "fpu type: %s\n",
6383 type == MIPS_FPU_DOUBLE ? "double-precision"
6384 : type == MIPS_FPU_SINGLE ? "single-precision"
6387 if (type == MIPS_FPU_NONE)
6390 fprintf_filtered (file, "reg size: %d bits\n",
6391 register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8);
6393 fputs_filtered ("cond :", file);
6394 if (fcs & (1 << 23))
6395 fputs_filtered (" 0", file);
6396 for (i = 1; i <= 7; i++)
6397 if (fcs & (1 << (24 + i)))
6398 fprintf_filtered (file, " %d", i);
6399 fputc_filtered ('\n', file);
6401 fputs_filtered ("cause :", file);
6402 print_fpu_flags (file, (fcs >> 12) & 0x3f);
6403 fputs ("mask :", stdout);
6404 print_fpu_flags (file, (fcs >> 7) & 0x1f);
6405 fputs ("flags :", stdout);
6406 print_fpu_flags (file, (fcs >> 2) & 0x1f);
6408 fputs_filtered ("rounding: ", file);
6411 case 0: fputs_filtered ("nearest\n", file); break;
6412 case 1: fputs_filtered ("zero\n", file); break;
6413 case 2: fputs_filtered ("+inf\n", file); break;
6414 case 3: fputs_filtered ("-inf\n", file); break;
6417 fputs_filtered ("flush :", file);
6418 if (fcs & (1 << 21))
6419 fputs_filtered (" nearest", file);
6420 if (fcs & (1 << 22))
6421 fputs_filtered (" override", file);
6422 if (fcs & (1 << 24))
6423 fputs_filtered (" zero", file);
6424 if ((fcs & (0xb << 21)) == 0)
6425 fputs_filtered (" no", file);
6426 fputc_filtered ('\n', file);
6428 fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no");
6429 fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no");
6430 fputc_filtered ('\n', file);
6432 default_print_float_info (gdbarch, file, frame, args);
6435 /* Replacement for generic do_registers_info.
6436 Print regs in pretty columns. */
6439 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
6442 fprintf_filtered (file, " ");
6443 mips_print_fp_register (file, frame, regnum);
6444 fprintf_filtered (file, "\n");
6449 /* Print a row's worth of GP (int) registers, with name labels above. */
6452 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
6455 struct gdbarch *gdbarch = get_frame_arch (frame);
6456 /* Do values for GP (int) regs. */
6457 const gdb_byte *raw_buffer;
6458 struct value *value;
6459 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols
6464 /* For GP registers, we print a separate row of names above the vals. */
6465 for (col = 0, regnum = start_regnum;
6466 col < ncols && regnum < gdbarch_num_regs (gdbarch)
6467 + gdbarch_num_pseudo_regs (gdbarch);
6470 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6471 continue; /* unused register */
6472 if (mips_float_register_p (gdbarch, regnum))
6473 break; /* End the row: reached FP register. */
6474 /* Large registers are handled separately. */
6475 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6478 break; /* End the row before this register. */
6480 /* Print this register on a row by itself. */
6481 mips_print_register (file, frame, regnum);
6482 fprintf_filtered (file, "\n");
6486 fprintf_filtered (file, " ");
6487 fprintf_filtered (file,
6488 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
6489 gdbarch_register_name (gdbarch, regnum));
6496 /* Print the R0 to R31 names. */
6497 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
6498 fprintf_filtered (file, "\n R%-4d",
6499 start_regnum % gdbarch_num_regs (gdbarch));
6501 fprintf_filtered (file, "\n ");
6503 /* Now print the values in hex, 4 or 8 to the row. */
6504 for (col = 0, regnum = start_regnum;
6505 col < ncols && regnum < gdbarch_num_regs (gdbarch)
6506 + gdbarch_num_pseudo_regs (gdbarch);
6509 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6510 continue; /* unused register */
6511 if (mips_float_register_p (gdbarch, regnum))
6512 break; /* End row: reached FP register. */
6513 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6514 break; /* End row: large register. */
6516 /* OK: get the data in raw format. */
6517 value = get_frame_register_value (frame, regnum);
6518 if (value_optimized_out (value)
6519 || !value_entirely_available (value))
6521 fprintf_filtered (file, "%*s ",
6522 (int) mips_abi_regsize (gdbarch) * 2,
6523 (mips_abi_regsize (gdbarch) == 4 ? "<unavl>"
6524 : "<unavailable>"));
6528 raw_buffer = value_contents_all (value);
6529 /* pad small registers */
6531 byte < (mips_abi_regsize (gdbarch)
6532 - register_size (gdbarch, regnum)); byte++)
6533 fprintf_filtered (file, " ");
6534 /* Now print the register value in hex, endian order. */
6535 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6537 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
6538 byte < register_size (gdbarch, regnum); byte++)
6539 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6541 for (byte = register_size (gdbarch, regnum) - 1;
6543 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6544 fprintf_filtered (file, " ");
6547 if (col > 0) /* ie. if we actually printed anything... */
6548 fprintf_filtered (file, "\n");
6553 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6556 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
6557 struct frame_info *frame, int regnum, int all)
6559 if (regnum != -1) /* Do one specified register. */
6561 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
6562 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
6563 error (_("Not a valid register for the current processor type"));
6565 mips_print_register (file, frame, regnum);
6566 fprintf_filtered (file, "\n");
6569 /* Do all (or most) registers. */
6571 regnum = gdbarch_num_regs (gdbarch);
6572 while (regnum < gdbarch_num_regs (gdbarch)
6573 + gdbarch_num_pseudo_regs (gdbarch))
6575 if (mips_float_register_p (gdbarch, regnum))
6577 if (all) /* True for "INFO ALL-REGISTERS" command. */
6578 regnum = print_fp_register_row (file, frame, regnum);
6580 regnum += MIPS_NUMREGS; /* Skip floating point regs. */
6583 regnum = print_gp_register_row (file, frame, regnum);
6589 mips_single_step_through_delay (struct gdbarch *gdbarch,
6590 struct frame_info *frame)
6592 CORE_ADDR pc = get_frame_pc (frame);
6597 if ((mips_pc_is_mips (pc)
6598 && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc))
6599 || (mips_pc_is_micromips (gdbarch, pc)
6600 && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0))
6601 || (mips_pc_is_mips16 (gdbarch, pc)
6602 && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0)))
6605 isa = mips_pc_isa (gdbarch, pc);
6606 /* _has_delay_slot above will have validated the read. */
6607 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL);
6608 size = mips_insn_size (isa, insn);
6610 const address_space *aspace = get_frame_address_space (frame);
6612 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here;
6615 /* To skip prologues, I use this predicate. Returns either PC itself
6616 if the code at PC does not look like a function prologue; otherwise
6617 returns an address that (if we're lucky) follows the prologue. If
6618 LENIENT, then we must skip everything which is involved in setting
6619 up the frame (it's OK to skip more, just so long as we don't skip
6620 anything which might clobber the registers which are being saved.
6621 We must skip more in the case where part of the prologue is in the
6622 delay slot of a non-prologue instruction). */
6625 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
6628 CORE_ADDR func_addr;
6630 /* See if we can determine the end of the prologue via the symbol table.
6631 If so, then return either PC, or the PC after the prologue, whichever
6633 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
6635 CORE_ADDR post_prologue_pc
6636 = skip_prologue_using_sal (gdbarch, func_addr);
6637 if (post_prologue_pc != 0)
6638 return std::max (pc, post_prologue_pc);
6641 /* Can't determine prologue from the symbol table, need to examine
6644 /* Find an upper limit on the function prologue using the debug
6645 information. If the debug information could not be used to provide
6646 that bound, then use an arbitrary large number as the upper bound. */
6647 limit_pc = skip_prologue_using_sal (gdbarch, pc);
6649 limit_pc = pc + 100; /* Magic. */
6651 if (mips_pc_is_mips16 (gdbarch, pc))
6652 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6653 else if (mips_pc_is_micromips (gdbarch, pc))
6654 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6656 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6659 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6660 This is a helper function for mips_stack_frame_destroyed_p. */
6663 mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6665 CORE_ADDR func_addr = 0, func_end = 0;
6667 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6669 /* The MIPS epilogue is max. 12 bytes long. */
6670 CORE_ADDR addr = func_end - 12;
6672 if (addr < func_addr + 4)
6673 addr = func_addr + 4;
6677 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
6679 unsigned long high_word;
6682 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
6683 high_word = (inst >> 16) & 0xffff;
6685 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
6686 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
6687 && inst != 0x03e00008 /* jr $ra */
6688 && inst != 0x00000000) /* nop */
6698 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6699 This is a helper function for mips_stack_frame_destroyed_p. */
6702 micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6704 CORE_ADDR func_addr = 0;
6705 CORE_ADDR func_end = 0;
6713 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6716 /* The microMIPS epilogue is max. 12 bytes long. */
6717 addr = func_end - 12;
6719 if (addr < func_addr + 2)
6720 addr = func_addr + 2;
6724 for (; pc < func_end; pc += loc)
6727 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
6728 loc += MIPS_INSN16_SIZE;
6729 switch (mips_insn_size (ISA_MICROMIPS, insn))
6731 /* 32-bit instructions. */
6732 case 2 * MIPS_INSN16_SIZE:
6734 insn |= mips_fetch_instruction (gdbarch,
6735 ISA_MICROMIPS, pc + loc, NULL);
6736 loc += MIPS_INSN16_SIZE;
6737 switch (micromips_op (insn >> 16))
6739 case 0xc: /* ADDIU: bits 001100 */
6740 case 0x17: /* DADDIU: bits 010111 */
6741 sreg = b0s5_reg (insn >> 16);
6742 dreg = b5s5_reg (insn >> 16);
6743 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
6744 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
6745 /* (D)ADDIU $sp, imm */
6755 /* 16-bit instructions. */
6756 case MIPS_INSN16_SIZE:
6757 switch (micromips_op (insn))
6759 case 0x3: /* MOVE: bits 000011 */
6760 sreg = b0s5_reg (insn);
6761 dreg = b5s5_reg (insn);
6762 if (sreg == 0 && dreg == 0)
6763 /* MOVE $zero, $zero aka NOP */
6767 case 0x11: /* POOL16C: bits 010001 */
6768 if (b5s5_op (insn) == 0x18
6769 /* JRADDIUSP: bits 010011 11000 */
6770 || (b5s5_op (insn) == 0xd
6771 /* JRC: bits 010011 01101 */
6772 && b0s5_reg (insn) == MIPS_RA_REGNUM))
6777 case 0x13: /* POOL16D: bits 010011 */
6778 offset = micromips_decode_imm9 (b1s9_imm (insn));
6779 if ((insn & 0x1) == 0x1
6780 /* ADDIUSP: bits 010011 1 */
6794 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6795 This is a helper function for mips_stack_frame_destroyed_p. */
6798 mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6800 CORE_ADDR func_addr = 0, func_end = 0;
6802 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6804 /* The MIPS epilogue is max. 12 bytes long. */
6805 CORE_ADDR addr = func_end - 12;
6807 if (addr < func_addr + 4)
6808 addr = func_addr + 4;
6812 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
6814 unsigned short inst;
6816 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL);
6818 if ((inst & 0xf800) == 0xf000) /* extend */
6821 if (inst != 0x6300 /* addiu $sp,offset */
6822 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
6823 && inst != 0xe820 /* jr $ra */
6824 && inst != 0xe8a0 /* jrc $ra */
6825 && inst != 0x6500) /* nop */
6835 /* Implement the stack_frame_destroyed_p gdbarch method.
6837 The epilogue is defined here as the area at the end of a function,
6838 after an instruction which destroys the function's stack frame. */
6841 mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6843 if (mips_pc_is_mips16 (gdbarch, pc))
6844 return mips16_stack_frame_destroyed_p (gdbarch, pc);
6845 else if (mips_pc_is_micromips (gdbarch, pc))
6846 return micromips_stack_frame_destroyed_p (gdbarch, pc);
6848 return mips32_stack_frame_destroyed_p (gdbarch, pc);
6851 /* Root of all "set mips "/"show mips " commands. This will eventually be
6852 used for all MIPS-specific commands. */
6855 show_mips_command (const char *args, int from_tty)
6857 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
6861 set_mips_command (const char *args, int from_tty)
6864 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6865 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
6868 /* Commands to show/set the MIPS FPU type. */
6871 show_mipsfpu_command (const char *args, int from_tty)
6875 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
6878 ("The MIPS floating-point coprocessor is unknown "
6879 "because the current architecture is not MIPS.\n");
6883 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6885 case MIPS_FPU_SINGLE:
6886 fpu = "single-precision";
6888 case MIPS_FPU_DOUBLE:
6889 fpu = "double-precision";
6892 fpu = "absent (none)";
6895 internal_error (__FILE__, __LINE__, _("bad switch"));
6897 if (mips_fpu_type_auto)
6898 printf_unfiltered ("The MIPS floating-point coprocessor "
6899 "is set automatically (currently %s)\n",
6903 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
6908 set_mipsfpu_command (const char *args, int from_tty)
6910 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6911 "\"single\",\"none\" or \"auto\".\n");
6912 show_mipsfpu_command (args, from_tty);
6916 set_mipsfpu_single_command (const char *args, int from_tty)
6918 struct gdbarch_info info;
6919 gdbarch_info_init (&info);
6920 mips_fpu_type = MIPS_FPU_SINGLE;
6921 mips_fpu_type_auto = 0;
6922 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6923 instead of relying on globals. Doing that would let generic code
6924 handle the search for this specific architecture. */
6925 if (!gdbarch_update_p (info))
6926 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6930 set_mipsfpu_double_command (const char *args, int from_tty)
6932 struct gdbarch_info info;
6933 gdbarch_info_init (&info);
6934 mips_fpu_type = MIPS_FPU_DOUBLE;
6935 mips_fpu_type_auto = 0;
6936 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6937 instead of relying on globals. Doing that would let generic code
6938 handle the search for this specific architecture. */
6939 if (!gdbarch_update_p (info))
6940 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6944 set_mipsfpu_none_command (const char *args, int from_tty)
6946 struct gdbarch_info info;
6947 gdbarch_info_init (&info);
6948 mips_fpu_type = MIPS_FPU_NONE;
6949 mips_fpu_type_auto = 0;
6950 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6951 instead of relying on globals. Doing that would let generic code
6952 handle the search for this specific architecture. */
6953 if (!gdbarch_update_p (info))
6954 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6958 set_mipsfpu_auto_command (const char *args, int from_tty)
6960 mips_fpu_type_auto = 1;
6963 /* Just like reinit_frame_cache, but with the right arguments to be
6964 callable as an sfunc. */
6967 reinit_frame_cache_sfunc (const char *args, int from_tty,
6968 struct cmd_list_element *c)
6970 reinit_frame_cache ();
6974 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
6976 gdb_disassembler *di
6977 = static_cast<gdb_disassembler *>(info->application_data);
6978 struct gdbarch *gdbarch = di->arch ();
6980 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6981 disassembler needs to be able to locally determine the ISA, and
6982 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6984 if (mips_pc_is_mips16 (gdbarch, memaddr))
6985 info->mach = bfd_mach_mips16;
6986 else if (mips_pc_is_micromips (gdbarch, memaddr))
6987 info->mach = bfd_mach_mips_micromips;
6989 /* Round down the instruction address to the appropriate boundary. */
6990 memaddr &= (info->mach == bfd_mach_mips16
6991 || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3;
6993 /* Set the disassembler options. */
6994 if (!info->disassembler_options)
6995 /* This string is not recognized explicitly by the disassembler,
6996 but it tells the disassembler to not try to guess the ABI from
6997 the bfd elf headers, such that, if the user overrides the ABI
6998 of a program linked as NewABI, the disassembly will follow the
6999 register naming conventions specified by the user. */
7000 info->disassembler_options = "gpr-names=32";
7002 return default_print_insn (memaddr, info);
7006 gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
7008 /* Set up the disassembler info, so that we get the right
7009 register names from libopcodes. */
7010 info->disassembler_options = "gpr-names=n32";
7011 info->flavour = bfd_target_elf_flavour;
7013 return gdb_print_insn_mips (memaddr, info);
7017 gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
7019 /* Set up the disassembler info, so that we get the right
7020 register names from libopcodes. */
7021 info->disassembler_options = "gpr-names=64";
7022 info->flavour = bfd_target_elf_flavour;
7024 return gdb_print_insn_mips (memaddr, info);
7027 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7030 mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
7032 CORE_ADDR pc = *pcptr;
7034 if (mips_pc_is_mips16 (gdbarch, pc))
7036 *pcptr = unmake_compact_addr (pc);
7037 return MIPS_BP_KIND_MIPS16;
7039 else if (mips_pc_is_micromips (gdbarch, pc))
7044 *pcptr = unmake_compact_addr (pc);
7045 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
7046 if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2))
7047 return MIPS_BP_KIND_MICROMIPS16;
7049 return MIPS_BP_KIND_MICROMIPS32;
7052 return MIPS_BP_KIND_MIPS32;
7055 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7057 static const gdb_byte *
7058 mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
7060 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7064 case MIPS_BP_KIND_MIPS16:
7066 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
7067 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
7070 if (byte_order_for_code == BFD_ENDIAN_BIG)
7071 return mips16_big_breakpoint;
7073 return mips16_little_breakpoint;
7075 case MIPS_BP_KIND_MICROMIPS16:
7077 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 };
7078 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 };
7082 if (byte_order_for_code == BFD_ENDIAN_BIG)
7083 return micromips16_big_breakpoint;
7085 return micromips16_little_breakpoint;
7087 case MIPS_BP_KIND_MICROMIPS32:
7089 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 };
7090 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 };
7093 if (byte_order_for_code == BFD_ENDIAN_BIG)
7094 return micromips32_big_breakpoint;
7096 return micromips32_little_breakpoint;
7098 case MIPS_BP_KIND_MIPS32:
7100 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
7101 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
7104 if (byte_order_for_code == BFD_ENDIAN_BIG)
7105 return big_breakpoint;
7107 return little_breakpoint;
7110 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7114 /* Return non-zero if the standard MIPS instruction INST has a branch
7115 delay slot (i.e. it is a jump or branch instruction). This function
7116 is based on mips32_next_pc. */
7119 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst)
7125 op = itype_op (inst);
7126 if ((inst & 0xe0000000) != 0)
7128 rs = itype_rs (inst);
7129 rt = itype_rt (inst);
7130 return (is_octeon_bbit_op (op, gdbarch)
7131 || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7132 || op == 29 /* JALX: bits 011101 */
7135 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7136 || (rs == 9 && (rt & 0x2) == 0)
7137 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7138 || (rs == 10 && (rt & 0x2) == 0))));
7139 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7142 switch (op & 0x07) /* extract bits 28,27,26 */
7144 case 0: /* SPECIAL */
7145 op = rtype_funct (inst);
7146 return (op == 8 /* JR */
7147 || op == 9); /* JALR */
7148 break; /* end SPECIAL */
7149 case 1: /* REGIMM */
7150 rs = itype_rs (inst);
7151 rt = itype_rt (inst); /* branch condition */
7152 return ((rt & 0xc) == 0
7153 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7154 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7155 || ((rt & 0x1e) == 0x1c && rs == 0));
7156 /* BPOSGE32, BPOSGE64: bits 1110x */
7157 break; /* end REGIMM */
7158 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7164 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7165 delay slot (i.e. it is a jump or branch instruction). */
7168 mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr)
7173 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status);
7177 return mips32_instruction_has_delay_slot (gdbarch, insn);
7180 /* Return non-zero if the microMIPS instruction INSN, comprising the
7181 16-bit major opcode word in the high 16 bits and any second word
7182 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7183 jump or branch instruction). The instruction must be 32-bit if
7184 MUSTBE32 is set or can be any instruction otherwise. */
7187 micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32)
7189 ULONGEST major = insn >> 16;
7191 switch (micromips_op (major))
7193 /* 16-bit instructions. */
7194 case 0x33: /* B16: bits 110011 */
7195 case 0x2b: /* BNEZ16: bits 101011 */
7196 case 0x23: /* BEQZ16: bits 100011 */
7198 case 0x11: /* POOL16C: bits 010001 */
7200 && ((b5s5_op (major) == 0xc
7201 /* JR16: bits 010001 01100 */
7202 || (b5s5_op (major) & 0x1e) == 0xe)));
7203 /* JALR16, JALRS16: bits 010001 0111x */
7204 /* 32-bit instructions. */
7205 case 0x3d: /* JAL: bits 111101 */
7206 case 0x3c: /* JALX: bits 111100 */
7207 case 0x35: /* J: bits 110101 */
7208 case 0x2d: /* BNE: bits 101101 */
7209 case 0x25: /* BEQ: bits 100101 */
7210 case 0x1d: /* JALS: bits 011101 */
7212 case 0x10: /* POOL32I: bits 010000 */
7213 return ((b5s5_op (major) & 0x1c) == 0x0
7214 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7215 || (b5s5_op (major) & 0x1d) == 0x4
7216 /* BLEZ, BGTZ: bits 010000 001x0 */
7217 || (b5s5_op (major) & 0x1d) == 0x11
7218 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7219 || ((b5s5_op (major) & 0x1e) == 0x14
7220 && (major & 0x3) == 0x0)
7221 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7222 || (b5s5_op (major) & 0x1e) == 0x1a
7223 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7224 || ((b5s5_op (major) & 0x1e) == 0x1c
7225 && (major & 0x3) == 0x0)
7226 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7227 || ((b5s5_op (major) & 0x1c) == 0x1c
7228 && (major & 0x3) == 0x1));
7229 /* BC1ANY*: bits 010000 111xx xxx01 */
7230 case 0x0: /* POOL32A: bits 000000 */
7231 return (b0s6_op (insn) == 0x3c
7232 /* POOL32Axf: bits 000000 ... 111100 */
7233 && (b6s10_ext (insn) & 0x2bf) == 0x3c);
7234 /* JALR, JALR.HB: 000000 000x111100 111100 */
7235 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7241 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7242 slot (i.e. it is a non-compact jump instruction). The instruction
7243 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7246 micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
7247 CORE_ADDR addr, int mustbe32)
7253 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7256 size = mips_insn_size (ISA_MICROMIPS, insn);
7258 if (size == 2 * MIPS_INSN16_SIZE)
7260 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7265 return micromips_instruction_has_delay_slot (insn, mustbe32);
7268 /* Return non-zero if the MIPS16 instruction INST, which must be
7269 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7270 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7271 instruction). This function is based on mips16_next_pc. */
7274 mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32)
7276 if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7278 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7281 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7282 slot (i.e. it is a non-compact jump instruction). The instruction
7283 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7286 mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
7287 CORE_ADDR addr, int mustbe32)
7289 unsigned short insn;
7292 insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status);
7296 return mips16_instruction_has_delay_slot (insn, mustbe32);
7299 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7300 This assumes KSSEG exists. */
7303 mips_segment_boundary (CORE_ADDR bpaddr)
7305 CORE_ADDR mask = CORE_ADDR_MAX;
7308 if (sizeof (CORE_ADDR) == 8)
7309 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7310 a compiler warning produced where CORE_ADDR is a 32-bit type even
7311 though in that case this is dead code). */
7312 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3)
7315 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr)
7316 segsize = 29; /* 32-bit compatibility segment */
7318 segsize = 62; /* xkseg */
7320 case 2: /* xkphys */
7323 default: /* xksseg (1), xkuseg/kuseg (0) */
7327 else if (bpaddr & 0x80000000) /* kernel segment */
7330 segsize = 31; /* user segment */
7332 return bpaddr & mask;
7335 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7336 it backwards if necessary. Return the address of the new location. */
7339 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
7341 CORE_ADDR prev_addr;
7343 CORE_ADDR func_addr;
7345 /* If a breakpoint is set on the instruction in a branch delay slot,
7346 GDB gets confused. When the breakpoint is hit, the PC isn't on
7347 the instruction in the branch delay slot, the PC will point to
7348 the branch instruction. Since the PC doesn't match any known
7349 breakpoints, GDB reports a trap exception.
7351 There are two possible fixes for this problem.
7353 1) When the breakpoint gets hit, see if the BD bit is set in the
7354 Cause register (which indicates the last exception occurred in a
7355 branch delay slot). If the BD bit is set, fix the PC to point to
7356 the instruction in the branch delay slot.
7358 2) When the user sets the breakpoint, don't allow him to set the
7359 breakpoint on the instruction in the branch delay slot. Instead
7360 move the breakpoint to the branch instruction (which will have
7363 The problem with the first solution is that if the user then
7364 single-steps the processor, the branch instruction will get
7365 skipped (since GDB thinks the PC is on the instruction in the
7368 So, we'll use the second solution. To do this we need to know if
7369 the instruction we're trying to set the breakpoint on is in the
7370 branch delay slot. */
7372 boundary = mips_segment_boundary (bpaddr);
7374 /* Make sure we don't scan back before the beginning of the current
7375 function, since we may fetch constant data or insns that look like
7376 a jump. Of course we might do that anyway if the compiler has
7377 moved constants inline. :-( */
7378 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL)
7379 && func_addr > boundary && func_addr <= bpaddr)
7380 boundary = func_addr;
7382 if (mips_pc_is_mips (bpaddr))
7384 if (bpaddr == boundary)
7387 /* If the previous instruction has a branch delay slot, we have
7388 to move the breakpoint to the branch instruction. */
7389 prev_addr = bpaddr - 4;
7390 if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr))
7395 int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int);
7396 CORE_ADDR addr, jmpaddr;
7399 boundary = unmake_compact_addr (boundary);
7401 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7402 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7403 so try for that first, then try the 2 byte JALR/JR.
7404 The microMIPS ASE has a whole range of jumps and branches
7405 with delay slots, some of which take 4 bytes and some take
7406 2 bytes, so the idea is the same.
7407 FIXME: We have to assume that bpaddr is not the second half
7408 of an extended instruction. */
7409 insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr)
7410 ? micromips_insn_at_pc_has_delay_slot
7411 : mips16_insn_at_pc_has_delay_slot);
7415 for (i = 1; i < 4; i++)
7417 if (unmake_compact_addr (addr) == boundary)
7419 addr -= MIPS_INSN16_SIZE;
7420 if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0))
7421 /* Looks like a JR/JALR at [target-1], but it could be
7422 the second word of a previous JAL/JALX, so record it
7423 and check back one more. */
7425 else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1))
7428 /* Looks like a JAL/JALX at [target-2], but it could also
7429 be the second word of a previous JAL/JALX, record it,
7430 and check back one more. */
7433 /* Looks like a JAL/JALX at [target-3], so any previously
7434 recorded JAL/JALX or JR/JALR must be wrong, because:
7437 -2: JAL-ext (can't be JAL/JALX)
7438 -1: bdslot (can't be JR/JALR)
7441 Of course it could be another JAL-ext which looks
7442 like a JAL, but in that case we'd have broken out
7443 of this loop at [target-2]:
7447 -2: bdslot (can't be jmp)
7454 /* Not a jump instruction: if we're at [target-1] this
7455 could be the second word of a JAL/JALX, so continue;
7456 otherwise we're done. */
7469 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7470 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7473 mips_is_stub_suffix (const char *suffix, int zero)
7478 return zero && suffix[1] == '\0';
7480 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0');
7485 return suffix[1] == '\0';
7491 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7492 call stubs, one of sf, df, sc, or dc. */
7495 mips_is_stub_mode (const char *mode)
7497 return ((mode[0] == 's' || mode[0] == 'd')
7498 && (mode[1] == 'f' || mode[1] == 'c'));
7501 /* Code at PC is a compiler-generated stub. Such a stub for a function
7502 bar might have a name like __fn_stub_bar, and might look like this:
7509 followed by (or interspersed with):
7516 addiu $25, $25, %lo(bar)
7519 ($1 may be used in old code; for robustness we accept any register)
7522 lui $28, %hi(_gp_disp)
7523 addiu $28, $28, %lo(_gp_disp)
7526 addiu $25, $25, %lo(bar)
7529 In the case of a __call_stub_bar stub, the sequence to set up
7530 arguments might look like this:
7537 followed by (or interspersed with) one of the jump sequences above.
7539 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7540 of J or JR, respectively, followed by:
7546 We are at the beginning of the stub here, and scan down and extract
7547 the target address from the jump immediate instruction or, if a jump
7548 register instruction is used, from the register referred. Return
7549 the value of PC calculated or 0 if inconclusive.
7551 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7554 mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc)
7556 struct gdbarch *gdbarch = get_frame_arch (frame);
7557 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7558 int addrreg = MIPS_ZERO_REGNUM;
7559 CORE_ADDR start_pc = pc;
7560 CORE_ADDR target_pc = 0;
7567 status == 0 && target_pc == 0 && i < 20;
7568 i++, pc += MIPS_INSN32_SIZE)
7570 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
7576 switch (itype_op (inst))
7578 case 0: /* SPECIAL */
7579 switch (rtype_funct (inst))
7583 rs = rtype_rs (inst);
7584 if (rs == MIPS_GP_REGNUM)
7585 target_pc = gp; /* Hmm... */
7586 else if (rs == addrreg)
7590 case 0x21: /* ADDU */
7591 rt = rtype_rt (inst);
7592 rs = rtype_rs (inst);
7593 rd = rtype_rd (inst);
7594 if (rd == MIPS_GP_REGNUM
7595 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM)
7596 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM)))
7604 target_pc = jtype_target (inst) << 2;
7605 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
7609 rt = itype_rt (inst);
7610 rs = itype_rs (inst);
7613 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7614 if (rt == MIPS_GP_REGNUM)
7616 else if (rt == addrreg)
7622 rt = itype_rt (inst);
7623 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16;
7624 if (rt == MIPS_GP_REGNUM)
7626 else if (rt != MIPS_ZERO_REGNUM)
7634 rt = itype_rt (inst);
7635 rs = itype_rs (inst);
7636 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7637 if (gp != 0 && rs == MIPS_GP_REGNUM)
7641 memset (buf, 0, sizeof (buf));
7642 status = target_read_memory (gp + imm, buf, sizeof (buf));
7644 addr = extract_signed_integer (buf, sizeof (buf), byte_order);
7653 /* If PC is in a MIPS16 call or return stub, return the address of the
7654 target PC, which is either the callee or the caller. There are several
7655 cases which must be handled:
7657 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7658 and the target PC is in $31 ($ra).
7659 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7660 and the target PC is in $2.
7661 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7662 i.e. before the JALR instruction, this is effectively a call stub
7663 and the target PC is in $2. Otherwise this is effectively
7664 a return stub and the target PC is in $18.
7665 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7666 JAL or JALR instruction, this is effectively a call stub and the
7667 target PC is buried in the instruction stream. Otherwise this
7668 is effectively a return stub and the target PC is in $18.
7669 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7670 stub and the target PC is buried in the instruction stream.
7672 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7673 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7677 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7679 struct gdbarch *gdbarch = get_frame_arch (frame);
7680 CORE_ADDR start_addr;
7684 /* Find the starting address and name of the function containing the PC. */
7685 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
7688 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7689 and the target PC is in $31 ($ra). */
7690 prefixlen = strlen (mips_str_mips16_ret_stub);
7691 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7692 && mips_is_stub_mode (name + prefixlen)
7693 && name[prefixlen + 2] == '\0')
7694 return get_frame_register_signed
7695 (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
7697 /* If the PC is in __mips16_call_stub_*, this is one of the call
7698 call/return stubs. */
7699 prefixlen = strlen (mips_str_mips16_call_stub);
7700 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0)
7702 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7703 and the target PC is in $2. */
7704 if (mips_is_stub_suffix (name + prefixlen, 0))
7705 return get_frame_register_signed
7706 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7708 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7709 i.e. before the JALR instruction, this is effectively a call stub
7710 and the target PC is in $2. Otherwise this is effectively
7711 a return stub and the target PC is in $18. */
7712 else if (mips_is_stub_mode (name + prefixlen)
7713 && name[prefixlen + 2] == '_'
7714 && mips_is_stub_suffix (name + prefixlen + 3, 0))
7716 if (pc == start_addr)
7717 /* This is the 'call' part of a call stub. The return
7718 address is in $2. */
7719 return get_frame_register_signed
7720 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7722 /* This is the 'return' part of a call stub. The return
7723 address is in $18. */
7724 return get_frame_register_signed
7725 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7728 return 0; /* Not a stub. */
7731 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7732 compiler-generated call or call/return stubs. */
7733 if (startswith (name, mips_str_fn_stub)
7734 || startswith (name, mips_str_call_stub))
7736 if (pc == start_addr)
7737 /* This is the 'call' part of a call stub. Call this helper
7738 to scan through this code for interesting instructions
7739 and determine the final PC. */
7740 return mips_get_mips16_fn_stub_pc (frame, pc);
7742 /* This is the 'return' part of a call stub. The return address
7744 return get_frame_register_signed
7745 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7748 return 0; /* Not a stub. */
7751 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7752 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7755 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name)
7757 CORE_ADDR start_addr;
7760 /* Find the starting address of the function containing the PC. */
7761 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
7764 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7765 the start, i.e. after the JALR instruction, this is effectively
7767 prefixlen = strlen (mips_str_mips16_call_stub);
7768 if (pc != start_addr
7769 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0
7770 && mips_is_stub_mode (name + prefixlen)
7771 && name[prefixlen + 2] == '_'
7772 && mips_is_stub_suffix (name + prefixlen + 3, 1))
7775 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7776 the JAL or JALR instruction, this is effectively a return stub. */
7777 prefixlen = strlen (mips_str_call_fp_stub);
7778 if (pc != start_addr
7779 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0)
7782 /* Consume the .pic. prefix of any PIC stub, this function must return
7783 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7784 or the call stub path will trigger in handle_inferior_event causing
7786 prefixlen = strlen (mips_str_pic);
7787 if (strncmp (name, mips_str_pic, prefixlen) == 0)
7790 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7791 prefixlen = strlen (mips_str_mips16_ret_stub);
7792 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7793 && mips_is_stub_mode (name + prefixlen)
7794 && name[prefixlen + 2] == '\0')
7797 return 0; /* Not a stub. */
7800 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7801 PC of the stub target. The stub just loads $t9 and jumps to it,
7802 so that $t9 has the correct value at function entry. */
7805 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7807 struct gdbarch *gdbarch = get_frame_arch (frame);
7808 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7809 struct bound_minimal_symbol msym;
7811 gdb_byte stub_code[16];
7812 int32_t stub_words[4];
7814 /* The stub for foo is named ".pic.foo", and is either two
7815 instructions inserted before foo or a three instruction sequence
7816 which jumps to foo. */
7817 msym = lookup_minimal_symbol_by_pc (pc);
7818 if (msym.minsym == NULL
7819 || BMSYMBOL_VALUE_ADDRESS (msym) != pc
7820 || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL
7821 || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
7824 /* A two-instruction header. */
7825 if (MSYMBOL_SIZE (msym.minsym) == 8)
7828 /* A three-instruction (plus delay slot) trampoline. */
7829 if (MSYMBOL_SIZE (msym.minsym) == 16)
7831 if (target_read_memory (pc, stub_code, 16) != 0)
7833 for (i = 0; i < 4; i++)
7834 stub_words[i] = extract_unsigned_integer (stub_code + i * 4,
7837 /* A stub contains these instructions:
7840 addiu t9, t9, %lo(target)
7843 This works even for N64, since stubs are only generated with
7845 if ((stub_words[0] & 0xffff0000U) == 0x3c190000
7846 && (stub_words[1] & 0xfc000000U) == 0x08000000
7847 && (stub_words[2] & 0xffff0000U) == 0x27390000
7848 && stub_words[3] == 0x00000000)
7849 return ((((stub_words[0] & 0x0000ffff) << 16)
7850 + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7853 /* Not a recognized stub. */
7858 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7860 CORE_ADDR requested_pc = pc;
7861 CORE_ADDR target_pc;
7868 new_pc = mips_skip_mips16_trampoline_code (frame, pc);
7872 new_pc = find_solib_trampoline_target (frame, pc);
7876 new_pc = mips_skip_pic_trampoline_code (frame, pc);
7880 while (pc != target_pc);
7882 return pc != requested_pc ? pc : 0;
7885 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7886 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7889 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
7892 if (num >= 0 && num < 32)
7894 else if (num >= 38 && num < 70)
7895 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
7897 regnum = mips_regnum (gdbarch)->hi;
7899 regnum = mips_regnum (gdbarch)->lo;
7900 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78)
7901 regnum = num + mips_regnum (gdbarch)->dspacc - 72;
7904 return gdbarch_num_regs (gdbarch) + regnum;
7908 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7909 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7912 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
7915 if (num >= 0 && num < 32)
7917 else if (num >= 32 && num < 64)
7918 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
7920 regnum = mips_regnum (gdbarch)->hi;
7922 regnum = mips_regnum (gdbarch)->lo;
7923 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72)
7924 regnum = num + mips_regnum (gdbarch)->dspacc - 66;
7927 return gdbarch_num_regs (gdbarch) + regnum;
7931 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
7933 /* Only makes sense to supply raw registers. */
7934 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
7935 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7936 decide if it is valid. Should instead define a standard sim/gdb
7937 register numbering scheme. */
7938 if (gdbarch_register_name (gdbarch,
7939 gdbarch_num_regs (gdbarch) + regnum) != NULL
7940 && gdbarch_register_name (gdbarch,
7941 gdbarch_num_regs (gdbarch)
7942 + regnum)[0] != '\0')
7945 return LEGACY_SIM_REGNO_IGNORE;
7949 /* Convert an integer into an address. Extracting the value signed
7950 guarantees a correctly sign extended address. */
7953 mips_integer_to_address (struct gdbarch *gdbarch,
7954 struct type *type, const gdb_byte *buf)
7956 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7957 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
7960 /* Dummy virtual frame pointer method. This is no more or less accurate
7961 than most other architectures; we just need to be explicit about it,
7962 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7963 an assertion failure. */
7966 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
7967 CORE_ADDR pc, int *reg, LONGEST *offset)
7969 *reg = MIPS_SP_REGNUM;
7974 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
7976 enum mips_abi *abip = (enum mips_abi *) obj;
7977 const char *name = bfd_get_section_name (abfd, sect);
7979 if (*abip != MIPS_ABI_UNKNOWN)
7982 if (!startswith (name, ".mdebug."))
7985 if (strcmp (name, ".mdebug.abi32") == 0)
7986 *abip = MIPS_ABI_O32;
7987 else if (strcmp (name, ".mdebug.abiN32") == 0)
7988 *abip = MIPS_ABI_N32;
7989 else if (strcmp (name, ".mdebug.abi64") == 0)
7990 *abip = MIPS_ABI_N64;
7991 else if (strcmp (name, ".mdebug.abiO64") == 0)
7992 *abip = MIPS_ABI_O64;
7993 else if (strcmp (name, ".mdebug.eabi32") == 0)
7994 *abip = MIPS_ABI_EABI32;
7995 else if (strcmp (name, ".mdebug.eabi64") == 0)
7996 *abip = MIPS_ABI_EABI64;
7998 warning (_("unsupported ABI %s."), name + 8);
8002 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
8004 int *lbp = (int *) obj;
8005 const char *name = bfd_get_section_name (abfd, sect);
8007 if (startswith (name, ".gcc_compiled_long32"))
8009 else if (startswith (name, ".gcc_compiled_long64"))
8011 else if (startswith (name, ".gcc_compiled_long"))
8012 warning (_("unrecognized .gcc_compiled_longXX"));
8015 static enum mips_abi
8016 global_mips_abi (void)
8020 for (i = 0; mips_abi_strings[i] != NULL; i++)
8021 if (mips_abi_strings[i] == mips_abi_string)
8022 return (enum mips_abi) i;
8024 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
8027 /* Return the default compressed instruction set, either of MIPS16
8028 or microMIPS, selected when none could have been determined from
8029 the ELF header of the binary being executed (or no binary has been
8032 static enum mips_isa
8033 global_mips_compression (void)
8037 for (i = 0; mips_compression_strings[i] != NULL; i++)
8038 if (mips_compression_strings[i] == mips_compression_string)
8039 return (enum mips_isa) i;
8041 internal_error (__FILE__, __LINE__, _("unknown compressed ISA string"));
8045 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
8047 /* If the size matches the set of 32-bit or 64-bit integer registers,
8048 assume that's what we've got. */
8049 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
8050 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
8052 /* If the size matches the full set of registers GDB traditionally
8053 knows about, including floating point, for either 32-bit or
8054 64-bit, assume that's what we've got. */
8055 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
8056 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
8058 /* Otherwise we don't have a useful guess. */
8061 static struct value *
8062 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
8064 const int *reg_p = (const int *) baton;
8065 return value_of_register (*reg_p, frame);
8068 static struct gdbarch *
8069 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8071 struct gdbarch *gdbarch;
8072 struct gdbarch_tdep *tdep;
8074 enum mips_abi mips_abi, found_abi, wanted_abi;
8076 enum mips_fpu_type fpu_type;
8077 struct tdesc_arch_data *tdesc_data = NULL;
8078 int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY;
8079 const char **reg_names;
8080 struct mips_regnum mips_regnum, *regnum;
8081 enum mips_isa mips_isa;
8085 /* First of all, extract the elf_flags, if available. */
8086 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8087 elf_flags = elf_elfheader (info.abfd)->e_flags;
8088 else if (arches != NULL)
8089 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
8093 fprintf_unfiltered (gdb_stdlog,
8094 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
8096 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8097 switch ((elf_flags & EF_MIPS_ABI))
8099 case E_MIPS_ABI_O32:
8100 found_abi = MIPS_ABI_O32;
8102 case E_MIPS_ABI_O64:
8103 found_abi = MIPS_ABI_O64;
8105 case E_MIPS_ABI_EABI32:
8106 found_abi = MIPS_ABI_EABI32;
8108 case E_MIPS_ABI_EABI64:
8109 found_abi = MIPS_ABI_EABI64;
8112 if ((elf_flags & EF_MIPS_ABI2))
8113 found_abi = MIPS_ABI_N32;
8115 found_abi = MIPS_ABI_UNKNOWN;
8119 /* GCC creates a pseudo-section whose name describes the ABI. */
8120 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
8121 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
8123 /* If we have no useful BFD information, use the ABI from the last
8124 MIPS architecture (if there is one). */
8125 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
8126 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
8128 /* Try the architecture for any hint of the correct ABI. */
8129 if (found_abi == MIPS_ABI_UNKNOWN
8130 && info.bfd_arch_info != NULL
8131 && info.bfd_arch_info->arch == bfd_arch_mips)
8133 switch (info.bfd_arch_info->mach)
8135 case bfd_mach_mips3900:
8136 found_abi = MIPS_ABI_EABI32;
8138 case bfd_mach_mips4100:
8139 case bfd_mach_mips5000:
8140 found_abi = MIPS_ABI_EABI64;
8142 case bfd_mach_mips8000:
8143 case bfd_mach_mips10000:
8144 /* On Irix, ELF64 executables use the N64 ABI. The
8145 pseudo-sections which describe the ABI aren't present
8146 on IRIX. (Even for executables created by gcc.) */
8147 if (info.abfd != NULL
8148 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8149 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8150 found_abi = MIPS_ABI_N64;
8152 found_abi = MIPS_ABI_N32;
8157 /* Default 64-bit objects to N64 instead of O32. */
8158 if (found_abi == MIPS_ABI_UNKNOWN
8159 && info.abfd != NULL
8160 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8161 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8162 found_abi = MIPS_ABI_N64;
8165 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
8168 /* What has the user specified from the command line? */
8169 wanted_abi = global_mips_abi ();
8171 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
8174 /* Now that we have found what the ABI for this binary would be,
8175 check whether the user is overriding it. */
8176 if (wanted_abi != MIPS_ABI_UNKNOWN)
8177 mips_abi = wanted_abi;
8178 else if (found_abi != MIPS_ABI_UNKNOWN)
8179 mips_abi = found_abi;
8181 mips_abi = MIPS_ABI_O32;
8183 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
8186 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8187 if (mips_abi != MIPS_ABI_EABI32
8188 && mips_abi != MIPS_ABI_O32
8189 && info.bfd_arch_info != NULL
8190 && info.bfd_arch_info->arch == bfd_arch_mips
8191 && info.bfd_arch_info->bits_per_word < 64)
8192 info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000);
8194 /* Determine the default compressed ISA. */
8195 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0
8196 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0)
8197 mips_isa = ISA_MICROMIPS;
8198 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0
8199 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0)
8200 mips_isa = ISA_MIPS16;
8202 mips_isa = global_mips_compression ();
8203 mips_compression_string = mips_compression_strings[mips_isa];
8205 /* Also used when doing an architecture lookup. */
8207 fprintf_unfiltered (gdb_stdlog,
8208 "mips_gdbarch_init: "
8209 "mips64_transfers_32bit_regs_p = %d\n",
8210 mips64_transfers_32bit_regs_p);
8212 /* Determine the MIPS FPU type. */
8215 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8216 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
8217 Tag_GNU_MIPS_ABI_FP);
8218 #endif /* HAVE_ELF */
8220 if (!mips_fpu_type_auto)
8221 fpu_type = mips_fpu_type;
8222 else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY)
8224 switch (elf_fpu_type)
8226 case Val_GNU_MIPS_ABI_FP_DOUBLE:
8227 fpu_type = MIPS_FPU_DOUBLE;
8229 case Val_GNU_MIPS_ABI_FP_SINGLE:
8230 fpu_type = MIPS_FPU_SINGLE;
8232 case Val_GNU_MIPS_ABI_FP_SOFT:
8234 /* Soft float or unknown. */
8235 fpu_type = MIPS_FPU_NONE;
8239 else if (info.bfd_arch_info != NULL
8240 && info.bfd_arch_info->arch == bfd_arch_mips)
8241 switch (info.bfd_arch_info->mach)
8243 case bfd_mach_mips3900:
8244 case bfd_mach_mips4100:
8245 case bfd_mach_mips4111:
8246 case bfd_mach_mips4120:
8247 fpu_type = MIPS_FPU_NONE;
8249 case bfd_mach_mips4650:
8250 fpu_type = MIPS_FPU_SINGLE;
8253 fpu_type = MIPS_FPU_DOUBLE;
8256 else if (arches != NULL)
8257 fpu_type = MIPS_FPU_TYPE (arches->gdbarch);
8259 fpu_type = MIPS_FPU_DOUBLE;
8261 fprintf_unfiltered (gdb_stdlog,
8262 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
8264 /* Check for blatant incompatibilities. */
8266 /* If we have only 32-bit registers, then we can't debug a 64-bit
8268 if (info.target_desc
8269 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
8270 && mips_abi != MIPS_ABI_EABI32
8271 && mips_abi != MIPS_ABI_O32)
8274 /* Fill in the OS dependent register numbers and names. */
8275 if (info.osabi == GDB_OSABI_LINUX)
8277 mips_regnum.fp0 = 38;
8278 mips_regnum.pc = 37;
8279 mips_regnum.cause = 36;
8280 mips_regnum.badvaddr = 35;
8281 mips_regnum.hi = 34;
8282 mips_regnum.lo = 33;
8283 mips_regnum.fp_control_status = 70;
8284 mips_regnum.fp_implementation_revision = 71;
8285 mips_regnum.dspacc = -1;
8286 mips_regnum.dspctl = -1;
8290 reg_names = mips_linux_reg_names;
8294 mips_regnum.lo = MIPS_EMBED_LO_REGNUM;
8295 mips_regnum.hi = MIPS_EMBED_HI_REGNUM;
8296 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
8297 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM;
8298 mips_regnum.pc = MIPS_EMBED_PC_REGNUM;
8299 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM;
8300 mips_regnum.fp_control_status = 70;
8301 mips_regnum.fp_implementation_revision = 71;
8302 mips_regnum.dspacc = dspacc = -1;
8303 mips_regnum.dspctl = dspctl = -1;
8304 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
8305 if (info.bfd_arch_info != NULL
8306 && info.bfd_arch_info->mach == bfd_mach_mips3900)
8307 reg_names = mips_tx39_reg_names;
8309 reg_names = mips_generic_reg_names;
8312 /* Check any target description for validity. */
8313 if (tdesc_has_registers (info.target_desc))
8315 static const char *const mips_gprs[] = {
8316 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8317 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8318 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8319 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8321 static const char *const mips_fprs[] = {
8322 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8323 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8324 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8325 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8328 const struct tdesc_feature *feature;
8331 feature = tdesc_find_feature (info.target_desc,
8332 "org.gnu.gdb.mips.cpu");
8333 if (feature == NULL)
8336 tdesc_data = tdesc_data_alloc ();
8339 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
8340 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8344 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8345 mips_regnum.lo, "lo");
8346 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8347 mips_regnum.hi, "hi");
8348 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8349 mips_regnum.pc, "pc");
8353 tdesc_data_cleanup (tdesc_data);
8357 feature = tdesc_find_feature (info.target_desc,
8358 "org.gnu.gdb.mips.cp0");
8359 if (feature == NULL)
8361 tdesc_data_cleanup (tdesc_data);
8366 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8367 mips_regnum.badvaddr, "badvaddr");
8368 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8369 MIPS_PS_REGNUM, "status");
8370 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8371 mips_regnum.cause, "cause");
8375 tdesc_data_cleanup (tdesc_data);
8379 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8380 backend is not prepared for that, though. */
8381 feature = tdesc_find_feature (info.target_desc,
8382 "org.gnu.gdb.mips.fpu");
8383 if (feature == NULL)
8385 tdesc_data_cleanup (tdesc_data);
8390 for (i = 0; i < 32; i++)
8391 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8392 i + mips_regnum.fp0, mips_fprs[i]);
8394 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8395 mips_regnum.fp_control_status,
8398 &= tdesc_numbered_register (feature, tdesc_data,
8399 mips_regnum.fp_implementation_revision,
8404 tdesc_data_cleanup (tdesc_data);
8408 num_regs = mips_regnum.fp_implementation_revision + 1;
8412 feature = tdesc_find_feature (info.target_desc,
8413 "org.gnu.gdb.mips.dsp");
8414 /* The DSP registers are optional; it's OK if they are absent. */
8415 if (feature != NULL)
8419 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8420 dspacc + i++, "hi1");
8421 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8422 dspacc + i++, "lo1");
8423 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8424 dspacc + i++, "hi2");
8425 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8426 dspacc + i++, "lo2");
8427 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8428 dspacc + i++, "hi3");
8429 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8430 dspacc + i++, "lo3");
8432 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8437 tdesc_data_cleanup (tdesc_data);
8441 mips_regnum.dspacc = dspacc;
8442 mips_regnum.dspctl = dspctl;
8444 num_regs = mips_regnum.dspctl + 1;
8448 /* It would be nice to detect an attempt to use a 64-bit ABI
8449 when only 32-bit registers are provided. */
8453 /* Try to find a pre-existing architecture. */
8454 for (arches = gdbarch_list_lookup_by_info (arches, &info);
8456 arches = gdbarch_list_lookup_by_info (arches->next, &info))
8458 /* MIPS needs to be pedantic about which ABI and the compressed
8459 ISA variation the object is using. */
8460 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
8462 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
8464 if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa)
8466 /* Need to be pedantic about which register virtual size is
8468 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
8469 != mips64_transfers_32bit_regs_p)
8471 /* Be pedantic about which FPU is selected. */
8472 if (MIPS_FPU_TYPE (arches->gdbarch) != fpu_type)
8475 if (tdesc_data != NULL)
8476 tdesc_data_cleanup (tdesc_data);
8477 return arches->gdbarch;
8480 /* Need a new architecture. Fill in a target specific vector. */
8481 tdep = XCNEW (struct gdbarch_tdep);
8482 gdbarch = gdbarch_alloc (&info, tdep);
8483 tdep->elf_flags = elf_flags;
8484 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
8485 tdep->found_abi = found_abi;
8486 tdep->mips_abi = mips_abi;
8487 tdep->mips_isa = mips_isa;
8488 tdep->mips_fpu_type = fpu_type;
8489 tdep->register_size_valid_p = 0;
8490 tdep->register_size = 0;
8492 if (info.target_desc)
8494 /* Some useful properties can be inferred from the target. */
8495 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
8497 tdep->register_size_valid_p = 1;
8498 tdep->register_size = 4;
8500 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
8502 tdep->register_size_valid_p = 1;
8503 tdep->register_size = 8;
8507 /* Initially set everything according to the default ABI/ISA. */
8508 set_gdbarch_short_bit (gdbarch, 16);
8509 set_gdbarch_int_bit (gdbarch, 32);
8510 set_gdbarch_float_bit (gdbarch, 32);
8511 set_gdbarch_double_bit (gdbarch, 64);
8512 set_gdbarch_long_double_bit (gdbarch, 64);
8513 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
8514 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
8515 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
8517 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8518 mips_ax_pseudo_register_collect);
8519 set_gdbarch_ax_pseudo_register_push_stack
8520 (gdbarch, mips_ax_pseudo_register_push_stack);
8522 set_gdbarch_elf_make_msymbol_special (gdbarch,
8523 mips_elf_make_msymbol_special);
8524 set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special);
8525 set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr);
8526 set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line);
8528 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum);
8529 *regnum = mips_regnum;
8530 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
8531 set_gdbarch_num_regs (gdbarch, num_regs);
8532 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8533 set_gdbarch_register_name (gdbarch, mips_register_name);
8534 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
8535 tdep->mips_processor_reg_names = reg_names;
8536 tdep->regnum = regnum;
8541 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
8542 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
8543 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8544 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8545 tdep->default_mask_address_p = 0;
8546 set_gdbarch_long_bit (gdbarch, 32);
8547 set_gdbarch_ptr_bit (gdbarch, 32);
8548 set_gdbarch_long_long_bit (gdbarch, 64);
8551 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
8552 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
8553 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8554 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8555 tdep->default_mask_address_p = 0;
8556 set_gdbarch_long_bit (gdbarch, 32);
8557 set_gdbarch_ptr_bit (gdbarch, 32);
8558 set_gdbarch_long_long_bit (gdbarch, 64);
8560 case MIPS_ABI_EABI32:
8561 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8562 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8563 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8564 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8565 tdep->default_mask_address_p = 0;
8566 set_gdbarch_long_bit (gdbarch, 32);
8567 set_gdbarch_ptr_bit (gdbarch, 32);
8568 set_gdbarch_long_long_bit (gdbarch, 64);
8570 case MIPS_ABI_EABI64:
8571 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8572 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8573 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8574 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8575 tdep->default_mask_address_p = 0;
8576 set_gdbarch_long_bit (gdbarch, 64);
8577 set_gdbarch_ptr_bit (gdbarch, 64);
8578 set_gdbarch_long_long_bit (gdbarch, 64);
8581 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8582 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8583 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8584 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8585 tdep->default_mask_address_p = 0;
8586 set_gdbarch_long_bit (gdbarch, 32);
8587 set_gdbarch_ptr_bit (gdbarch, 32);
8588 set_gdbarch_long_long_bit (gdbarch, 64);
8589 set_gdbarch_long_double_bit (gdbarch, 128);
8590 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8593 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8594 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8595 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8596 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8597 tdep->default_mask_address_p = 0;
8598 set_gdbarch_long_bit (gdbarch, 64);
8599 set_gdbarch_ptr_bit (gdbarch, 64);
8600 set_gdbarch_long_long_bit (gdbarch, 64);
8601 set_gdbarch_long_double_bit (gdbarch, 128);
8602 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8605 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8608 /* GCC creates a pseudo-section whose name specifies the size of
8609 longs, since -mlong32 or -mlong64 may be used independent of
8610 other options. How those options affect pointer sizes is ABI and
8611 architecture dependent, so use them to override the default sizes
8612 set by the ABI. This table shows the relationship between ABI,
8613 -mlongXX, and size of pointers:
8615 ABI -mlongXX ptr bits
8616 --- -------- --------
8630 Note that for o32 and eabi32, pointers are always 32 bits
8631 regardless of any -mlongXX option. For all others, pointers and
8632 longs are the same, as set by -mlongXX or set by defaults. */
8634 if (info.abfd != NULL)
8638 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
8641 set_gdbarch_long_bit (gdbarch, long_bit);
8645 case MIPS_ABI_EABI32:
8650 case MIPS_ABI_EABI64:
8651 set_gdbarch_ptr_bit (gdbarch, long_bit);
8654 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8659 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8660 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8663 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8664 flag in object files because to do so would make it impossible to
8665 link with libraries compiled without "-gp32". This is
8666 unnecessarily restrictive.
8668 We could solve this problem by adding "-gp32" multilibs to gcc,
8669 but to set this flag before gcc is built with such multilibs will
8670 break too many systems.''
8672 But even more unhelpfully, the default linker output target for
8673 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8674 for 64-bit programs - you need to change the ABI to change this,
8675 and not all gcc targets support that currently. Therefore using
8676 this flag to detect 32-bit mode would do the wrong thing given
8677 the current gcc - it would make GDB treat these 64-bit programs
8678 as 32-bit programs by default. */
8680 set_gdbarch_read_pc (gdbarch, mips_read_pc);
8681 set_gdbarch_write_pc (gdbarch, mips_write_pc);
8683 /* Add/remove bits from an address. The MIPS needs be careful to
8684 ensure that all 32 bit addresses are sign extended to 64 bits. */
8685 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
8687 /* Unwind the frame. */
8688 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
8689 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
8690 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
8692 /* Map debug register numbers onto internal register numbers. */
8693 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
8694 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
8695 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8696 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
8697 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8698 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
8700 /* MIPS version of CALL_DUMMY. */
8702 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8703 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code);
8704 set_gdbarch_frame_align (gdbarch, mips_frame_align);
8706 set_gdbarch_print_float_info (gdbarch, mips_print_float_info);
8708 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
8709 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
8710 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
8712 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8713 set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc);
8714 set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind);
8715 set_gdbarch_adjust_breakpoint_address (gdbarch,
8716 mips_adjust_breakpoint_address);
8718 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
8720 set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p);
8722 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
8723 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
8724 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
8726 set_gdbarch_register_type (gdbarch, mips_register_type);
8728 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
8730 if (mips_abi == MIPS_ABI_N32)
8731 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
8732 else if (mips_abi == MIPS_ABI_N64)
8733 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
8735 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
8737 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8738 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8739 need to all be folded into the target vector. Since they are
8740 being used as guards for target_stopped_by_watchpoint, why not have
8741 target_stopped_by_watchpoint return the type of watchpoint that the code
8743 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
8745 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
8747 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8748 to support MIPS16. This is a bad thing. Make sure not to do it
8749 if we have an OS ABI that actually supports shared libraries, since
8750 shared library support is more important. If we have an OS someday
8751 that supports both shared libraries and MIPS16, we'll have to find
8752 a better place for these.
8753 macro/2012-04-25: But that applies to return trampolines only and
8754 currently no MIPS OS ABI uses shared libraries that have them. */
8755 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
8757 set_gdbarch_single_step_through_delay (gdbarch,
8758 mips_single_step_through_delay);
8760 /* Virtual tables. */
8761 set_gdbarch_vbit_in_delta (gdbarch, 1);
8763 mips_register_g_packet_guesses (gdbarch);
8765 /* Hook in OS ABI-specific overrides, if they have been registered. */
8766 info.tdesc_data = tdesc_data;
8767 gdbarch_init_osabi (info, gdbarch);
8769 /* The hook may have adjusted num_regs, fetch the final value and
8770 set pc_regnum and sp_regnum now that it has been fixed. */
8771 num_regs = gdbarch_num_regs (gdbarch);
8772 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
8773 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8775 /* Unwind the frame. */
8776 dwarf2_append_unwinders (gdbarch);
8777 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
8778 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
8779 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind);
8780 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
8781 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
8782 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
8783 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
8784 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer);
8785 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
8789 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
8790 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
8792 /* Override the normal target description methods to handle our
8793 dual real and pseudo registers. */
8794 set_gdbarch_register_name (gdbarch, mips_register_name);
8795 set_gdbarch_register_reggroup_p (gdbarch,
8796 mips_tdesc_register_reggroup_p);
8798 num_regs = gdbarch_num_regs (gdbarch);
8799 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8800 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
8801 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8804 /* Add ABI-specific aliases for the registers. */
8805 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
8806 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
8807 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
8808 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
8810 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
8811 user_reg_add (gdbarch, mips_o32_aliases[i].name,
8812 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
8814 /* Add some other standard aliases. */
8815 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
8816 user_reg_add (gdbarch, mips_register_aliases[i].name,
8817 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
8819 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)
8820 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,
8821 value_of_mips_user_reg,
8822 &mips_numeric_register_aliases[i].regnum);
8828 mips_abi_update (const char *ignore_args,
8829 int from_tty, struct cmd_list_element *c)
8831 struct gdbarch_info info;
8833 /* Force the architecture to update, and (if it's a MIPS architecture)
8834 mips_gdbarch_init will take care of the rest. */
8835 gdbarch_info_init (&info);
8836 gdbarch_update_p (info);
8839 /* Print out which MIPS ABI is in use. */
8842 show_mips_abi (struct ui_file *file,
8844 struct cmd_list_element *ignored_cmd,
8845 const char *ignored_value)
8847 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
8850 "The MIPS ABI is unknown because the current architecture "
8854 enum mips_abi global_abi = global_mips_abi ();
8855 enum mips_abi actual_abi = mips_abi (target_gdbarch ());
8856 const char *actual_abi_str = mips_abi_strings[actual_abi];
8858 if (global_abi == MIPS_ABI_UNKNOWN)
8861 "The MIPS ABI is set automatically (currently \"%s\").\n",
8863 else if (global_abi == actual_abi)
8866 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8870 /* Probably shouldn't happen... */
8871 fprintf_filtered (file,
8872 "The (auto detected) MIPS ABI \"%s\" is in use "
8873 "even though the user setting was \"%s\".\n",
8874 actual_abi_str, mips_abi_strings[global_abi]);
8879 /* Print out which MIPS compressed ISA encoding is used. */
8882 show_mips_compression (struct ui_file *file, int from_tty,
8883 struct cmd_list_element *c, const char *value)
8885 fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"),
8889 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8892 mips_fpu_type_str (enum mips_fpu_type fpu_type)
8898 case MIPS_FPU_SINGLE:
8900 case MIPS_FPU_DOUBLE:
8908 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
8910 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8914 int ef_mips_32bitmode;
8915 /* Determine the ISA. */
8916 switch (tdep->elf_flags & EF_MIPS_ARCH)
8934 /* Determine the size of a pointer. */
8935 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
8936 fprintf_unfiltered (file,
8937 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8939 fprintf_unfiltered (file,
8940 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8942 fprintf_unfiltered (file,
8943 "mips_dump_tdep: ef_mips_arch = %d\n",
8945 fprintf_unfiltered (file,
8946 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8947 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
8948 fprintf_unfiltered (file,
8950 "mips_mask_address_p() %d (default %d)\n",
8951 mips_mask_address_p (tdep),
8952 tdep->default_mask_address_p);
8954 fprintf_unfiltered (file,
8955 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8956 MIPS_DEFAULT_FPU_TYPE,
8957 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE));
8958 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
8959 MIPS_EABI (gdbarch));
8960 fprintf_unfiltered (file,
8961 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8962 MIPS_FPU_TYPE (gdbarch),
8963 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch)));
8967 _initialize_mips_tdep (void)
8969 static struct cmd_list_element *mipsfpulist = NULL;
8971 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
8972 if (MIPS_ABI_LAST + 1
8973 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
8974 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
8976 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
8978 mips_pdr_data = register_objfile_data ();
8980 /* Create feature sets with the appropriate properties. The values
8981 are not important. */
8982 mips_tdesc_gp32 = allocate_target_description ();
8983 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
8985 mips_tdesc_gp64 = allocate_target_description ();
8986 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
8988 /* Add root prefix command for all "set mips"/"show mips" commands. */
8989 add_prefix_cmd ("mips", no_class, set_mips_command,
8990 _("Various MIPS specific commands."),
8991 &setmipscmdlist, "set mips ", 0, &setlist);
8993 add_prefix_cmd ("mips", no_class, show_mips_command,
8994 _("Various MIPS specific commands."),
8995 &showmipscmdlist, "show mips ", 0, &showlist);
8997 /* Allow the user to override the ABI. */
8998 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
8999 &mips_abi_string, _("\
9000 Set the MIPS ABI used by this program."), _("\
9001 Show the MIPS ABI used by this program."), _("\
9002 This option can be set to one of:\n\
9003 auto - the default ABI associated with the current binary\n\
9012 &setmipscmdlist, &showmipscmdlist);
9014 /* Allow the user to set the ISA to assume for compressed code if ELF
9015 file flags don't tell or there is no program file selected. This
9016 setting is updated whenever unambiguous ELF file flags are interpreted,
9017 and carried over to subsequent sessions. */
9018 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings,
9019 &mips_compression_string, _("\
9020 Set the compressed ISA encoding used by MIPS code."), _("\
9021 Show the compressed ISA encoding used by MIPS code."), _("\
9022 Select the compressed ISA encoding used in functions that have no symbol\n\
9023 information available. The encoding can be set to either of:\n\
9026 and is updated automatically from ELF file flags if available."),
9028 show_mips_compression,
9029 &setmipscmdlist, &showmipscmdlist);
9031 /* Let the user turn off floating point and set the fence post for
9032 heuristic_proc_start. */
9034 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
9035 _("Set use of MIPS floating-point coprocessor."),
9036 &mipsfpulist, "set mipsfpu ", 0, &setlist);
9037 add_cmd ("single", class_support, set_mipsfpu_single_command,
9038 _("Select single-precision MIPS floating-point coprocessor."),
9040 add_cmd ("double", class_support, set_mipsfpu_double_command,
9041 _("Select double-precision MIPS floating-point coprocessor."),
9043 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
9044 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
9045 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
9046 add_cmd ("none", class_support, set_mipsfpu_none_command,
9047 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
9048 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
9049 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
9050 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
9051 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
9052 _("Select MIPS floating-point coprocessor automatically."),
9054 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
9055 _("Show current use of MIPS floating-point coprocessor target."),
9058 /* We really would like to have both "0" and "unlimited" work, but
9059 command.c doesn't deal with that. So make it a var_zinteger
9060 because the user can always use "999999" or some such for unlimited. */
9061 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
9062 &heuristic_fence_post, _("\
9063 Set the distance searched for the start of a function."), _("\
9064 Show the distance searched for the start of a function."), _("\
9065 If you are debugging a stripped executable, GDB needs to search through the\n\
9066 program for the start of a function. This command sets the distance of the\n\
9067 search. The only need to set it is when debugging a stripped executable."),
9068 reinit_frame_cache_sfunc,
9069 NULL, /* FIXME: i18n: The distance searched for
9070 the start of a function is %s. */
9071 &setlist, &showlist);
9073 /* Allow the user to control whether the upper bits of 64-bit
9074 addresses should be zeroed. */
9075 add_setshow_auto_boolean_cmd ("mask-address", no_class,
9076 &mask_address_var, _("\
9077 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9078 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9079 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9080 allow GDB to determine the correct value."),
9081 NULL, show_mask_address,
9082 &setmipscmdlist, &showmipscmdlist);
9084 /* Allow the user to control the size of 32 bit registers within the
9085 raw remote packet. */
9086 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
9087 &mips64_transfers_32bit_regs_p, _("\
9088 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9090 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9092 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9093 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9094 64 bits for others. Use \"off\" to disable compatibility mode"),
9095 set_mips64_transfers_32bit_regs,
9096 NULL, /* FIXME: i18n: Compatibility with 64-bit
9097 MIPS target that transfers 32-bit
9098 quantities is %s. */
9099 &setlist, &showlist);
9101 /* Debug this files internals. */
9102 add_setshow_zuinteger_cmd ("mips", class_maintenance,
9104 Set mips debugging."), _("\
9105 Show mips debugging."), _("\
9106 When non-zero, mips specific debugging is enabled."),
9108 NULL, /* FIXME: i18n: Mips debugging is
9110 &setdebuglist, &showdebuglist);