1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static const struct objfile_data *mips_pdr_data;
63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
65 static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch,
67 static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32);
68 static int mips16_instruction_has_delay_slot (unsigned short inst,
71 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
73 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
74 CORE_ADDR addr, int mustbe32);
75 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
76 CORE_ADDR addr, int mustbe32);
78 static void mips_print_float_info (struct gdbarch *, struct ui_file *,
79 struct frame_info *, const char *);
81 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
82 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
83 #define ST0_FR (1 << 26)
85 /* The sizes of floating point registers. */
89 MIPS_FPU_SINGLE_REGSIZE = 4,
90 MIPS_FPU_DOUBLE_REGSIZE = 8
99 static const char *mips_abi_string;
101 static const char *const mips_abi_strings[] = {
112 /* Enum describing the different kinds of breakpoints. */
114 enum mips_breakpoint_kind
116 /* 16-bit MIPS16 mode breakpoint. */
117 MIPS_BP_KIND_MIPS16 = 2,
119 /* 16-bit microMIPS mode breakpoint. */
120 MIPS_BP_KIND_MICROMIPS16 = 3,
122 /* 32-bit standard MIPS mode breakpoint. */
123 MIPS_BP_KIND_MIPS32 = 4,
125 /* 32-bit microMIPS mode breakpoint. */
126 MIPS_BP_KIND_MICROMIPS32 = 5,
129 /* For backwards compatibility we default to MIPS16. This flag is
130 overridden as soon as unambiguous ELF file flags tell us the
131 compressed ISA encoding used. */
132 static const char mips_compression_mips16[] = "mips16";
133 static const char mips_compression_micromips[] = "micromips";
134 static const char *const mips_compression_strings[] =
136 mips_compression_mips16,
137 mips_compression_micromips,
141 static const char *mips_compression_string = mips_compression_mips16;
143 /* The standard register names, and all the valid aliases for them. */
144 struct register_alias
150 /* Aliases for o32 and most other ABIs. */
151 const struct register_alias mips_o32_aliases[] = {
158 /* Aliases for n32 and n64. */
159 const struct register_alias mips_n32_n64_aliases[] = {
166 /* Aliases for ABI-independent registers. */
167 const struct register_alias mips_register_aliases[] = {
168 /* The architecture manuals specify these ABI-independent names for
170 #define R(n) { "r" #n, n }
171 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
172 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
173 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
174 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
177 /* k0 and k1 are sometimes called these instead (for "kernel
182 /* This is the traditional GDB name for the CP0 status register. */
183 { "sr", MIPS_PS_REGNUM },
185 /* This is the traditional GDB name for the CP0 BadVAddr register. */
186 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
188 /* This is the traditional GDB name for the FCSR. */
189 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
192 const struct register_alias mips_numeric_register_aliases[] = {
193 #define R(n) { #n, n }
194 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
195 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
196 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
197 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
201 #ifndef MIPS_DEFAULT_FPU_TYPE
202 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
204 static int mips_fpu_type_auto = 1;
205 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
207 static unsigned int mips_debug = 0;
209 /* Properties (for struct target_desc) describing the g/G packet
211 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
212 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
214 struct target_desc *mips_tdesc_gp32;
215 struct target_desc *mips_tdesc_gp64;
217 /* The current set of options to be passed to the disassembler. */
218 static char *mips_disassembler_options;
220 /* Implicit disassembler options for individual ABIs. These tell
221 libopcodes to use general-purpose register names corresponding
222 to the ABI we have selected, perhaps via a `set mips abi ...'
223 override, rather than ones inferred from the ABI set in the ELF
224 headers of the binary file selected for debugging. */
225 static const char mips_disassembler_options_o32[] = "gpr-names=32";
226 static const char mips_disassembler_options_n32[] = "gpr-names=n32";
227 static const char mips_disassembler_options_n64[] = "gpr-names=64";
229 const struct mips_regnum *
230 mips_regnum (struct gdbarch *gdbarch)
232 return gdbarch_tdep (gdbarch)->regnum;
236 mips_fpa0_regnum (struct gdbarch *gdbarch)
238 return mips_regnum (gdbarch)->fp0 + 12;
241 /* Return 1 if REGNUM refers to a floating-point general register, raw
242 or cooked. Otherwise return 0. */
245 mips_float_register_p (struct gdbarch *gdbarch, int regnum)
247 int rawnum = regnum % gdbarch_num_regs (gdbarch);
249 return (rawnum >= mips_regnum (gdbarch)->fp0
250 && rawnum < mips_regnum (gdbarch)->fp0 + 32);
253 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
255 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
257 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
258 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
260 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
261 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
263 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
265 /* Return the MIPS ABI associated with GDBARCH. */
267 mips_abi (struct gdbarch *gdbarch)
269 return gdbarch_tdep (gdbarch)->mips_abi;
273 mips_isa_regsize (struct gdbarch *gdbarch)
275 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
277 /* If we know how big the registers are, use that size. */
278 if (tdep->register_size_valid_p)
279 return tdep->register_size;
281 /* Fall back to the previous behavior. */
282 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
283 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
286 /* Max saved register size. */
287 #define MAX_MIPS_ABI_REGSIZE 8
289 /* Return the currently configured (or set) saved register size. */
292 mips_abi_regsize (struct gdbarch *gdbarch)
294 switch (mips_abi (gdbarch))
296 case MIPS_ABI_EABI32:
302 case MIPS_ABI_EABI64:
304 case MIPS_ABI_UNKNOWN:
307 internal_error (__FILE__, __LINE__, _("bad switch"));
311 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
312 are some functions to handle addresses associated with compressed
313 code including but not limited to testing, setting, or clearing
314 bit 0 of such addresses. */
316 /* Return one iff compressed code is the MIPS16 instruction set. */
319 is_mips16_isa (struct gdbarch *gdbarch)
321 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16;
324 /* Return one iff compressed code is the microMIPS instruction set. */
327 is_micromips_isa (struct gdbarch *gdbarch)
329 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS;
332 /* Return one iff ADDR denotes compressed code. */
335 is_compact_addr (CORE_ADDR addr)
340 /* Return one iff ADDR denotes standard ISA code. */
343 is_mips_addr (CORE_ADDR addr)
345 return !is_compact_addr (addr);
348 /* Return one iff ADDR denotes MIPS16 code. */
351 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
353 return is_compact_addr (addr) && is_mips16_isa (gdbarch);
356 /* Return one iff ADDR denotes microMIPS code. */
359 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
361 return is_compact_addr (addr) && is_micromips_isa (gdbarch);
364 /* Strip the ISA (compression) bit off from ADDR. */
367 unmake_compact_addr (CORE_ADDR addr)
369 return ((addr) & ~(CORE_ADDR) 1);
372 /* Add the ISA (compression) bit to ADDR. */
375 make_compact_addr (CORE_ADDR addr)
377 return ((addr) | (CORE_ADDR) 1);
380 /* Extern version of unmake_compact_addr; we use a separate function
381 so that unmake_compact_addr can be inlined throughout this file. */
384 mips_unmake_compact_addr (CORE_ADDR addr)
386 return unmake_compact_addr (addr);
389 /* Functions for setting and testing a bit in a minimal symbol that
390 marks it as MIPS16 or microMIPS function. The MSB of the minimal
391 symbol's "info" field is used for this purpose.
393 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
394 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
395 one of the "special" bits in a minimal symbol to mark it accordingly.
396 The test checks an ELF-private flag that is valid for true function
397 symbols only; for synthetic symbols such as for PLT stubs that have
398 no ELF-private part at all the MIPS BFD backend arranges for this
399 information to be carried in the asymbol's udata field instead.
401 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
402 in a minimal symbol. */
405 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
407 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
408 unsigned char st_other;
410 if ((sym->flags & BSF_SYNTHETIC) == 0)
411 st_other = elfsym->internal_elf_sym.st_other;
412 else if ((sym->flags & BSF_FUNCTION) != 0)
413 st_other = sym->udata.i;
417 if (ELF_ST_IS_MICROMIPS (st_other))
419 MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1;
420 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
422 else if (ELF_ST_IS_MIPS16 (st_other))
424 MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1;
425 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
429 /* Return one iff MSYM refers to standard ISA code. */
432 msymbol_is_mips (struct minimal_symbol *msym)
434 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym)
435 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym));
438 /* Return one iff MSYM refers to MIPS16 code. */
441 msymbol_is_mips16 (struct minimal_symbol *msym)
443 return MSYMBOL_TARGET_FLAG_MIPS16 (msym);
446 /* Return one iff MSYM refers to microMIPS code. */
449 msymbol_is_micromips (struct minimal_symbol *msym)
451 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym);
454 /* Set the ISA bit in the main symbol too, complementing the corresponding
455 minimal symbol setting and reflecting the run-time value of the symbol.
456 The need for comes from the ISA bit having been cleared as code in
457 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
458 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
459 of symbols referring to compressed code different in GDB to the values
460 used by actual code. That in turn makes them evaluate incorrectly in
461 expressions, producing results different to what the same expressions
462 yield when compiled into the program being debugged. */
465 mips_make_symbol_special (struct symbol *sym, struct objfile *objfile)
467 if (SYMBOL_CLASS (sym) == LOC_BLOCK)
469 /* We are in symbol reading so it is OK to cast away constness. */
470 struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym);
471 CORE_ADDR compact_block_start;
472 struct bound_minimal_symbol msym;
474 compact_block_start = BLOCK_START (block) | 1;
475 msym = lookup_minimal_symbol_by_pc (compact_block_start);
476 if (msym.minsym && !msymbol_is_mips (msym.minsym))
478 BLOCK_START (block) = compact_block_start;
483 /* XFER a value from the big/little/left end of the register.
484 Depending on the size of the value it might occupy the entire
485 register or just part of it. Make an allowance for this, aligning
486 things accordingly. */
489 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
490 int reg_num, int length,
491 enum bfd_endian endian, gdb_byte *in,
492 const gdb_byte *out, int buf_offset)
496 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
497 /* Need to transfer the left or right part of the register, based on
498 the targets byte order. */
502 reg_offset = register_size (gdbarch, reg_num) - length;
504 case BFD_ENDIAN_LITTLE:
507 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
511 internal_error (__FILE__, __LINE__, _("bad switch"));
514 fprintf_unfiltered (gdb_stderr,
515 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
516 reg_num, reg_offset, buf_offset, length);
517 if (mips_debug && out != NULL)
520 fprintf_unfiltered (gdb_stdlog, "out ");
521 for (i = 0; i < length; i++)
522 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
525 regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset);
527 regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset);
528 if (mips_debug && in != NULL)
531 fprintf_unfiltered (gdb_stdlog, "in ");
532 for (i = 0; i < length; i++)
533 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
536 fprintf_unfiltered (gdb_stdlog, "\n");
539 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
540 compatiblity mode. A return value of 1 means that we have
541 physical 64-bit registers, but should treat them as 32-bit registers. */
544 mips2_fp_compat (struct frame_info *frame)
546 struct gdbarch *gdbarch = get_frame_arch (frame);
547 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
549 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
553 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
554 in all the places we deal with FP registers. PR gdb/413. */
555 /* Otherwise check the FR bit in the status register - it controls
556 the FP compatiblity mode. If it is clear we are in compatibility
558 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
565 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
567 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
569 /* The list of available "set mips " and "show mips " commands. */
571 static struct cmd_list_element *setmipscmdlist = NULL;
572 static struct cmd_list_element *showmipscmdlist = NULL;
574 /* Integer registers 0 thru 31 are handled explicitly by
575 mips_register_name(). Processor specific registers 32 and above
576 are listed in the following tables. */
579 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
583 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
584 "sr", "lo", "hi", "bad", "cause", "pc",
585 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
586 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
587 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
588 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
592 /* Names of tx39 registers. */
594 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
595 "sr", "lo", "hi", "bad", "cause", "pc",
596 "", "", "", "", "", "", "", "",
597 "", "", "", "", "", "", "", "",
598 "", "", "", "", "", "", "", "",
599 "", "", "", "", "", "", "", "",
601 "", "", "", "", "", "", "", "",
602 "", "", "config", "cache", "debug", "depc", "epc",
605 /* Names of registers with Linux kernels. */
606 static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
607 "sr", "lo", "hi", "bad", "cause", "pc",
608 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
609 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
610 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
611 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
616 /* Return the name of the register corresponding to REGNO. */
618 mips_register_name (struct gdbarch *gdbarch, int regno)
620 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
621 /* GPR names for all ABIs other than n32/n64. */
622 static const char *mips_gpr_names[] = {
623 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
624 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
625 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
626 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
629 /* GPR names for n32 and n64 ABIs. */
630 static const char *mips_n32_n64_gpr_names[] = {
631 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
632 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
633 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
634 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
637 enum mips_abi abi = mips_abi (gdbarch);
639 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
640 but then don't make the raw register names visible. This (upper)
641 range of user visible register numbers are the pseudo-registers.
643 This approach was adopted accommodate the following scenario:
644 It is possible to debug a 64-bit device using a 32-bit
645 programming model. In such instances, the raw registers are
646 configured to be 64-bits wide, while the pseudo registers are
647 configured to be 32-bits wide. The registers that the user
648 sees - the pseudo registers - match the users expectations
649 given the programming model being used. */
650 int rawnum = regno % gdbarch_num_regs (gdbarch);
651 if (regno < gdbarch_num_regs (gdbarch))
654 /* The MIPS integer registers are always mapped from 0 to 31. The
655 names of the registers (which reflects the conventions regarding
656 register use) vary depending on the ABI. */
657 if (0 <= rawnum && rawnum < 32)
659 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
660 return mips_n32_n64_gpr_names[rawnum];
662 return mips_gpr_names[rawnum];
664 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
665 return tdesc_register_name (gdbarch, rawnum);
666 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
668 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
669 if (tdep->mips_processor_reg_names[rawnum - 32])
670 return tdep->mips_processor_reg_names[rawnum - 32];
674 internal_error (__FILE__, __LINE__,
675 _("mips_register_name: bad register number %d"), rawnum);
678 /* Return the groups that a MIPS register can be categorised into. */
681 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
682 struct reggroup *reggroup)
687 int rawnum = regnum % gdbarch_num_regs (gdbarch);
688 int pseudo = regnum / gdbarch_num_regs (gdbarch);
689 if (reggroup == all_reggroup)
691 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
692 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
693 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
694 (gdbarch), as not all architectures are multi-arch. */
695 raw_p = rawnum < gdbarch_num_regs (gdbarch);
696 if (gdbarch_register_name (gdbarch, regnum) == NULL
697 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
699 if (reggroup == float_reggroup)
700 return float_p && pseudo;
701 if (reggroup == vector_reggroup)
702 return vector_p && pseudo;
703 if (reggroup == general_reggroup)
704 return (!vector_p && !float_p) && pseudo;
705 /* Save the pseudo registers. Need to make certain that any code
706 extracting register values from a saved register cache also uses
708 if (reggroup == save_reggroup)
709 return raw_p && pseudo;
710 /* Restore the same pseudo register. */
711 if (reggroup == restore_reggroup)
712 return raw_p && pseudo;
716 /* Return the groups that a MIPS register can be categorised into.
717 This version is only used if we have a target description which
718 describes real registers (and their groups). */
721 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
722 struct reggroup *reggroup)
724 int rawnum = regnum % gdbarch_num_regs (gdbarch);
725 int pseudo = regnum / gdbarch_num_regs (gdbarch);
728 /* Only save, restore, and display the pseudo registers. Need to
729 make certain that any code extracting register values from a
730 saved register cache also uses pseudo registers.
732 Note: saving and restoring the pseudo registers is slightly
733 strange; if we have 64 bits, we should save and restore all
734 64 bits. But this is hard and has little benefit. */
738 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
742 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
745 /* Map the symbol table registers which live in the range [1 *
746 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
747 registers. Take care of alignment and size problems. */
749 static enum register_status
750 mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache,
751 int cookednum, gdb_byte *buf)
753 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
754 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
755 && cookednum < 2 * gdbarch_num_regs (gdbarch));
756 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
757 return regcache->raw_read (rawnum, buf);
758 else if (register_size (gdbarch, rawnum) >
759 register_size (gdbarch, cookednum))
761 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
762 return regcache->raw_read_part (rawnum, 0, 4, buf);
765 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
767 enum register_status status;
769 status = regcache->raw_read (rawnum, ®val);
770 if (status == REG_VALID)
771 store_signed_integer (buf, 4, byte_order, regval);
776 internal_error (__FILE__, __LINE__, _("bad register size"));
780 mips_pseudo_register_write (struct gdbarch *gdbarch,
781 struct regcache *regcache, int cookednum,
784 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
785 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
786 && cookednum < 2 * gdbarch_num_regs (gdbarch));
787 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
788 regcache->raw_write (rawnum, buf);
789 else if (register_size (gdbarch, rawnum) >
790 register_size (gdbarch, cookednum))
792 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
793 regcache->raw_write_part (rawnum, 0, 4, buf);
796 /* Sign extend the shortened version of the register prior
797 to placing it in the raw register. This is required for
798 some mips64 parts in order to avoid unpredictable behavior. */
799 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
800 LONGEST regval = extract_signed_integer (buf, 4, byte_order);
801 regcache_raw_write_signed (regcache, rawnum, regval);
805 internal_error (__FILE__, __LINE__, _("bad register size"));
809 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch,
810 struct agent_expr *ax, int reg)
812 int rawnum = reg % gdbarch_num_regs (gdbarch);
813 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
814 && reg < 2 * gdbarch_num_regs (gdbarch));
816 ax_reg_mask (ax, rawnum);
822 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
823 struct agent_expr *ax, int reg)
825 int rawnum = reg % gdbarch_num_regs (gdbarch);
826 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
827 && reg < 2 * gdbarch_num_regs (gdbarch));
828 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg))
832 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg))
834 if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
835 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG)
838 ax_simple (ax, aop_lsh);
841 ax_simple (ax, aop_rsh_signed);
845 internal_error (__FILE__, __LINE__, _("bad register size"));
850 /* Table to translate 3-bit register field to actual register number. */
851 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
853 /* Heuristic_proc_start may hunt through the text section for a long
854 time across a 2400 baud serial line. Allows the user to limit this
857 static int heuristic_fence_post = 0;
859 /* Number of bytes of storage in the actual machine representation for
860 register N. NOTE: This defines the pseudo register type so need to
861 rebuild the architecture vector. */
863 static int mips64_transfers_32bit_regs_p = 0;
866 set_mips64_transfers_32bit_regs (const char *args, int from_tty,
867 struct cmd_list_element *c)
869 struct gdbarch_info info;
870 gdbarch_info_init (&info);
871 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
872 instead of relying on globals. Doing that would let generic code
873 handle the search for this specific architecture. */
874 if (!gdbarch_update_p (info))
876 mips64_transfers_32bit_regs_p = 0;
877 error (_("32-bit compatibility mode not supported"));
881 /* Convert to/from a register and the corresponding memory value. */
883 /* This predicate tests for the case of an 8 byte floating point
884 value that is being transferred to or from a pair of floating point
885 registers each of which are (or are considered to be) only 4 bytes
888 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum,
891 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
892 && register_size (gdbarch, regnum) == 4
893 && mips_float_register_p (gdbarch, regnum)
894 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
897 /* This predicate tests for the case of a value of less than 8
898 bytes in width that is being transfered to or from an 8 byte
899 general purpose register. */
901 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum,
904 int num_regs = gdbarch_num_regs (gdbarch);
906 return (register_size (gdbarch, regnum) == 8
907 && regnum % num_regs > 0 && regnum % num_regs < 32
908 && TYPE_LENGTH (type) < 8);
912 mips_convert_register_p (struct gdbarch *gdbarch,
913 int regnum, struct type *type)
915 return (mips_convert_register_float_case_p (gdbarch, regnum, type)
916 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type));
920 mips_register_to_value (struct frame_info *frame, int regnum,
921 struct type *type, gdb_byte *to,
922 int *optimizedp, int *unavailablep)
924 struct gdbarch *gdbarch = get_frame_arch (frame);
926 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
928 get_frame_register (frame, regnum + 0, to + 4);
929 get_frame_register (frame, regnum + 1, to + 0);
931 if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4,
932 optimizedp, unavailablep))
935 if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0,
936 optimizedp, unavailablep))
938 *optimizedp = *unavailablep = 0;
941 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
943 int len = TYPE_LENGTH (type);
946 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0;
947 if (!get_frame_register_bytes (frame, regnum, offset, len, to,
948 optimizedp, unavailablep))
951 *optimizedp = *unavailablep = 0;
956 internal_error (__FILE__, __LINE__,
957 _("mips_register_to_value: unrecognized case"));
962 mips_value_to_register (struct frame_info *frame, int regnum,
963 struct type *type, const gdb_byte *from)
965 struct gdbarch *gdbarch = get_frame_arch (frame);
967 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
969 put_frame_register (frame, regnum + 0, from + 4);
970 put_frame_register (frame, regnum + 1, from + 0);
972 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
975 int len = TYPE_LENGTH (type);
977 /* Sign extend values, irrespective of type, that are stored to
978 a 64-bit general purpose register. (32-bit unsigned values
979 are stored as signed quantities within a 64-bit register.
980 When performing an operation, in compiled code, that combines
981 a 32-bit unsigned value with a signed 64-bit value, a type
982 conversion is first performed that zeroes out the high 32 bits.) */
983 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
986 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1);
988 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0);
989 put_frame_register_bytes (frame, regnum, 0, 8 - len, fill);
990 put_frame_register_bytes (frame, regnum, 8 - len, len, from);
994 if (from[len-1] & 0x80)
995 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1);
997 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0);
998 put_frame_register_bytes (frame, regnum, 0, len, from);
999 put_frame_register_bytes (frame, regnum, len, 8 - len, fill);
1004 internal_error (__FILE__, __LINE__,
1005 _("mips_value_to_register: unrecognized case"));
1009 /* Return the GDB type object for the "standard" data type of data in
1012 static struct type *
1013 mips_register_type (struct gdbarch *gdbarch, int regnum)
1015 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
1016 if (mips_float_register_p (gdbarch, regnum))
1018 /* The floating-point registers raw, or cooked, always match
1019 mips_isa_regsize(), and also map 1:1, byte for byte. */
1020 if (mips_isa_regsize (gdbarch) == 4)
1021 return builtin_type (gdbarch)->builtin_float;
1023 return builtin_type (gdbarch)->builtin_double;
1025 else if (regnum < gdbarch_num_regs (gdbarch))
1027 /* The raw or ISA registers. These are all sized according to
1029 if (mips_isa_regsize (gdbarch) == 4)
1030 return builtin_type (gdbarch)->builtin_int32;
1032 return builtin_type (gdbarch)->builtin_int64;
1036 int rawnum = regnum - gdbarch_num_regs (gdbarch);
1038 /* The cooked or ABI registers. These are sized according to
1039 the ABI (with a few complications). */
1040 if (rawnum == mips_regnum (gdbarch)->fp_control_status
1041 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision)
1042 return builtin_type (gdbarch)->builtin_int32;
1043 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
1044 && rawnum >= MIPS_FIRST_EMBED_REGNUM
1045 && rawnum <= MIPS_LAST_EMBED_REGNUM)
1046 /* The pseudo/cooked view of the embedded registers is always
1047 32-bit. The raw view is handled below. */
1048 return builtin_type (gdbarch)->builtin_int32;
1049 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
1050 /* The target, while possibly using a 64-bit register buffer,
1051 is only transfering 32-bits of each integer register.
1052 Reflect this in the cooked/pseudo (ABI) register value. */
1053 return builtin_type (gdbarch)->builtin_int32;
1054 else if (mips_abi_regsize (gdbarch) == 4)
1055 /* The ABI is restricted to 32-bit registers (the ISA could be
1057 return builtin_type (gdbarch)->builtin_int32;
1060 return builtin_type (gdbarch)->builtin_int64;
1064 /* Return the GDB type for the pseudo register REGNUM, which is the
1065 ABI-level view. This function is only called if there is a target
1066 description which includes registers, so we know precisely the
1067 types of hardware registers. */
1069 static struct type *
1070 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
1072 const int num_regs = gdbarch_num_regs (gdbarch);
1073 int rawnum = regnum % num_regs;
1074 struct type *rawtype;
1076 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
1078 /* Absent registers are still absent. */
1079 rawtype = gdbarch_register_type (gdbarch, rawnum);
1080 if (TYPE_LENGTH (rawtype) == 0)
1083 /* Present the floating point registers however the hardware did;
1084 do not try to convert between FPU layouts. */
1085 if (mips_float_register_p (gdbarch, rawnum))
1088 /* Floating-point control registers are always 32-bit even though for
1089 backwards compatibility reasons 64-bit targets will transfer them
1090 as 64-bit quantities even if using XML descriptions. */
1091 if (rawnum == mips_regnum (gdbarch)->fp_control_status
1092 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision)
1093 return builtin_type (gdbarch)->builtin_int32;
1095 /* Use pointer types for registers if we can. For n32 we can not,
1096 since we do not have a 64-bit pointer type. */
1097 if (mips_abi_regsize (gdbarch)
1098 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
1100 if (rawnum == MIPS_SP_REGNUM
1101 || rawnum == mips_regnum (gdbarch)->badvaddr)
1102 return builtin_type (gdbarch)->builtin_data_ptr;
1103 else if (rawnum == mips_regnum (gdbarch)->pc)
1104 return builtin_type (gdbarch)->builtin_func_ptr;
1107 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
1108 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM)
1109 || rawnum == mips_regnum (gdbarch)->lo
1110 || rawnum == mips_regnum (gdbarch)->hi
1111 || rawnum == mips_regnum (gdbarch)->badvaddr
1112 || rawnum == mips_regnum (gdbarch)->cause
1113 || rawnum == mips_regnum (gdbarch)->pc
1114 || (mips_regnum (gdbarch)->dspacc != -1
1115 && rawnum >= mips_regnum (gdbarch)->dspacc
1116 && rawnum < mips_regnum (gdbarch)->dspacc + 6)))
1117 return builtin_type (gdbarch)->builtin_int32;
1119 /* The pseudo/cooked view of embedded registers is always
1120 32-bit, even if the target transfers 64-bit values for them.
1121 New targets relying on XML descriptions should only transfer
1122 the necessary 32 bits, but older versions of GDB expected 64,
1123 so allow the target to provide 64 bits without interfering
1124 with the displayed type. */
1125 if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
1126 && rawnum >= MIPS_FIRST_EMBED_REGNUM
1127 && rawnum <= MIPS_LAST_EMBED_REGNUM)
1128 return builtin_type (gdbarch)->builtin_int32;
1130 /* For all other registers, pass through the hardware type. */
1134 /* Should the upper word of 64-bit addresses be zeroed? */
1135 static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
1138 mips_mask_address_p (struct gdbarch_tdep *tdep)
1140 switch (mask_address_var)
1142 case AUTO_BOOLEAN_TRUE:
1144 case AUTO_BOOLEAN_FALSE:
1147 case AUTO_BOOLEAN_AUTO:
1148 return tdep->default_mask_address_p;
1150 internal_error (__FILE__, __LINE__,
1151 _("mips_mask_address_p: bad switch"));
1157 show_mask_address (struct ui_file *file, int from_tty,
1158 struct cmd_list_element *c, const char *value)
1160 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
1162 deprecated_show_value_hack (file, from_tty, c, value);
1163 switch (mask_address_var)
1165 case AUTO_BOOLEAN_TRUE:
1166 printf_filtered ("The 32 bit mips address mask is enabled\n");
1168 case AUTO_BOOLEAN_FALSE:
1169 printf_filtered ("The 32 bit mips address mask is disabled\n");
1171 case AUTO_BOOLEAN_AUTO:
1173 ("The 32 bit address mask is set automatically. Currently %s\n",
1174 mips_mask_address_p (tdep) ? "enabled" : "disabled");
1177 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
1182 /* Tell if the program counter value in MEMADDR is in a standard ISA
1186 mips_pc_is_mips (CORE_ADDR memaddr)
1188 struct bound_minimal_symbol sym;
1190 /* Flags indicating that this is a MIPS16 or microMIPS function is
1191 stored by elfread.c in the high bit of the info field. Use this
1192 to decide if the function is standard MIPS. Otherwise if bit 0
1193 of the address is clear, then this is a standard MIPS function. */
1194 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1196 return msymbol_is_mips (sym.minsym);
1198 return is_mips_addr (memaddr);
1201 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1204 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1206 struct bound_minimal_symbol sym;
1208 /* A flag indicating that this is a MIPS16 function is stored by
1209 elfread.c in the high bit of the info field. Use this to decide
1210 if the function is MIPS16. Otherwise if bit 0 of the address is
1211 set, then ELF file flags will tell if this is a MIPS16 function. */
1212 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1214 return msymbol_is_mips16 (sym.minsym);
1216 return is_mips16_addr (gdbarch, memaddr);
1219 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1222 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1224 struct bound_minimal_symbol sym;
1226 /* A flag indicating that this is a microMIPS function is stored by
1227 elfread.c in the high bit of the info field. Use this to decide
1228 if the function is microMIPS. Otherwise if bit 0 of the address
1229 is set, then ELF file flags will tell if this is a microMIPS
1231 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1233 return msymbol_is_micromips (sym.minsym);
1235 return is_micromips_addr (gdbarch, memaddr);
1238 /* Tell the ISA type of the function the program counter value in MEMADDR
1241 static enum mips_isa
1242 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1244 struct bound_minimal_symbol sym;
1246 /* A flag indicating that this is a MIPS16 or a microMIPS function
1247 is stored by elfread.c in the high bit of the info field. Use
1248 this to decide if the function is MIPS16 or microMIPS or normal
1249 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1250 flags will tell if this is a MIPS16 or a microMIPS function. */
1251 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1254 if (msymbol_is_micromips (sym.minsym))
1255 return ISA_MICROMIPS;
1256 else if (msymbol_is_mips16 (sym.minsym))
1263 if (is_mips_addr (memaddr))
1265 else if (is_micromips_addr (gdbarch, memaddr))
1266 return ISA_MICROMIPS;
1272 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1273 The need for comes from the ISA bit having been cleared, making
1274 addresses in FDE, range records, etc. referring to compressed code
1275 different to those in line information, the symbol table and finally
1276 the PC register. That in turn confuses many operations. */
1279 mips_adjust_dwarf2_addr (CORE_ADDR pc)
1281 pc = unmake_compact_addr (pc);
1282 return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc);
1285 /* Recalculate the line record requested so that the resulting PC has
1286 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1287 this adjustment comes from some records associated with compressed
1288 code having the ISA bit cleared, most notably at function prologue
1289 ends. The ISA bit is in this context retrieved from the minimal
1290 symbol covering the address requested, which in turn has been
1291 constructed from the binary's symbol table rather than DWARF-2
1292 information. The correct setting of the ISA bit is required for
1293 breakpoint addresses to correctly match against the stop PC.
1295 As line entries can specify relative address adjustments we need to
1296 keep track of the absolute value of the last line address recorded
1297 in line information, so that we can calculate the actual address to
1298 apply the ISA bit adjustment to. We use PC for this tracking and
1299 keep the original address there.
1301 As such relative address adjustments can be odd within compressed
1302 code we need to keep track of the last line address with the ISA
1303 bit adjustment applied too, as the original address may or may not
1304 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1305 the adjusted address there.
1307 For relative address adjustments we then use these variables to
1308 calculate the address intended by line information, which will be
1309 PC-relative, and return an updated adjustment carrying ISA bit
1310 information, which will be ADJ_PC-relative. For absolute address
1311 adjustments we just return the same address that we store in ADJ_PC
1314 As the first line entry can be relative to an implied address value
1315 of 0 we need to have the initial address set up that we store in PC
1316 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1317 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1320 mips_adjust_dwarf2_line (CORE_ADDR addr, int rel)
1322 static CORE_ADDR adj_pc;
1323 static CORE_ADDR pc;
1326 pc = rel ? pc + addr : addr;
1327 isa_pc = mips_adjust_dwarf2_addr (pc);
1328 addr = rel ? isa_pc - adj_pc : isa_pc;
1333 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1335 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_";
1336 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_";
1337 static const char mips_str_call_fp_stub[] = "__call_stub_fp_";
1338 static const char mips_str_call_stub[] = "__call_stub_";
1339 static const char mips_str_fn_stub[] = "__fn_stub_";
1341 /* This is used as a PIC thunk prefix. */
1343 static const char mips_str_pic[] = ".pic.";
1345 /* Return non-zero if the PC is inside a call thunk (aka stub or
1346 trampoline) that should be treated as a temporary frame. */
1349 mips_in_frame_stub (CORE_ADDR pc)
1351 CORE_ADDR start_addr;
1354 /* Find the starting address of the function containing the PC. */
1355 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
1358 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1359 if (startswith (name, mips_str_mips16_call_stub))
1361 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1362 if (startswith (name, mips_str_call_stub))
1364 /* If the PC is in __fn_stub_*, this is a call stub. */
1365 if (startswith (name, mips_str_fn_stub))
1368 return 0; /* Not a stub. */
1371 /* MIPS believes that the PC has a sign extended value. Perhaps the
1372 all registers should be sign extended for simplicity? */
1375 mips_read_pc (readable_regcache *regcache)
1377 int regnum = gdbarch_pc_regnum (regcache->arch ());
1380 regcache->cooked_read (regnum, &pc);
1385 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1389 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch));
1390 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1391 intermediate frames. In this case we can get the caller's address
1392 from $ra, or if $ra contains an address within a thunk as well, then
1393 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1394 and thus the caller's address is in $s2. */
1395 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc))
1397 pc = frame_unwind_register_signed
1398 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
1399 if (mips_in_frame_stub (pc))
1400 pc = frame_unwind_register_signed
1401 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
1407 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1409 return frame_unwind_register_signed
1410 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
1413 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1414 dummy frame. The frame ID's base needs to match the TOS value
1415 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1418 static struct frame_id
1419 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1421 return frame_id_build
1422 (get_frame_register_signed (this_frame,
1423 gdbarch_num_regs (gdbarch)
1425 get_frame_pc (this_frame));
1428 /* Implement the "write_pc" gdbarch method. */
1431 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
1433 int regnum = gdbarch_pc_regnum (regcache->arch ());
1435 regcache_cooked_write_unsigned (regcache, regnum, pc);
1438 /* Fetch and return instruction from the specified location. Handle
1439 MIPS16/microMIPS as appropriate. */
1442 mips_fetch_instruction (struct gdbarch *gdbarch,
1443 enum mips_isa isa, CORE_ADDR addr, int *errp)
1445 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1446 gdb_byte buf[MIPS_INSN32_SIZE];
1454 instlen = MIPS_INSN16_SIZE;
1455 addr = unmake_compact_addr (addr);
1458 instlen = MIPS_INSN32_SIZE;
1461 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1464 err = target_read_memory (addr, buf, instlen);
1470 memory_error (TARGET_XFER_E_IO, addr);
1473 return extract_unsigned_integer (buf, instlen, byte_order);
1476 /* These are the fields of 32 bit mips instructions. */
1477 #define mips32_op(x) (x >> 26)
1478 #define itype_op(x) (x >> 26)
1479 #define itype_rs(x) ((x >> 21) & 0x1f)
1480 #define itype_rt(x) ((x >> 16) & 0x1f)
1481 #define itype_immediate(x) (x & 0xffff)
1483 #define jtype_op(x) (x >> 26)
1484 #define jtype_target(x) (x & 0x03ffffff)
1486 #define rtype_op(x) (x >> 26)
1487 #define rtype_rs(x) ((x >> 21) & 0x1f)
1488 #define rtype_rt(x) ((x >> 16) & 0x1f)
1489 #define rtype_rd(x) ((x >> 11) & 0x1f)
1490 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1491 #define rtype_funct(x) (x & 0x3f)
1493 /* MicroMIPS instruction fields. */
1494 #define micromips_op(x) ((x) >> 10)
1496 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1497 bit and the size respectively of the field extracted. */
1498 #define b0s4_imm(x) ((x) & 0xf)
1499 #define b0s5_imm(x) ((x) & 0x1f)
1500 #define b0s5_reg(x) ((x) & 0x1f)
1501 #define b0s7_imm(x) ((x) & 0x7f)
1502 #define b0s10_imm(x) ((x) & 0x3ff)
1503 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1504 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1505 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1506 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1507 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1508 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1509 #define b6s4_op(x) (((x) >> 6) & 0xf)
1510 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1512 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1513 respectively of the field extracted. */
1514 #define b0s6_op(x) ((x) & 0x3f)
1515 #define b0s11_op(x) ((x) & 0x7ff)
1516 #define b0s12_imm(x) ((x) & 0xfff)
1517 #define b0s16_imm(x) ((x) & 0xffff)
1518 #define b0s26_imm(x) ((x) & 0x3ffffff)
1519 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1520 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1521 #define b12s4_op(x) (((x) >> 12) & 0xf)
1523 /* Return the size in bytes of the instruction INSN encoded in the ISA
1527 mips_insn_size (enum mips_isa isa, ULONGEST insn)
1532 if ((micromips_op (insn) & 0x4) == 0x4
1533 || (micromips_op (insn) & 0x7) == 0x0)
1534 return 2 * MIPS_INSN16_SIZE;
1536 return MIPS_INSN16_SIZE;
1538 if ((insn & 0xf800) == 0xf000)
1539 return 2 * MIPS_INSN16_SIZE;
1541 return MIPS_INSN16_SIZE;
1543 return MIPS_INSN32_SIZE;
1545 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1549 mips32_relative_offset (ULONGEST inst)
1551 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
1554 /* Determine the address of the next instruction executed after the INST
1555 floating condition branch instruction at PC. COUNT specifies the
1556 number of the floating condition bits tested by the branch. */
1559 mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
1560 ULONGEST inst, CORE_ADDR pc, int count)
1562 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1563 int cnum = (itype_rt (inst) >> 2) & (count - 1);
1564 int tf = itype_rt (inst) & 1;
1565 int mask = (1 << count) - 1;
1570 /* No way to handle; it'll most likely trap anyway. */
1573 fcs = regcache_raw_get_unsigned (regcache, fcsr);
1574 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1576 if (((cond >> cnum) & mask) != mask * !tf)
1577 pc += mips32_relative_offset (inst);
1584 /* Return nonzero if the gdbarch is an Octeon series. */
1587 is_octeon (struct gdbarch *gdbarch)
1589 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
1591 return (info->mach == bfd_mach_mips_octeon
1592 || info->mach == bfd_mach_mips_octeonp
1593 || info->mach == bfd_mach_mips_octeon2);
1596 /* Return true if the OP represents the Octeon's BBIT instruction. */
1599 is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
1601 if (!is_octeon (gdbarch))
1603 /* BBIT0 is encoded as LWC2: 110 010. */
1604 /* BBIT032 is encoded as LDC2: 110 110. */
1605 /* BBIT1 is encoded as SWC2: 111 010. */
1606 /* BBIT132 is encoded as SDC2: 111 110. */
1607 if (op == 50 || op == 54 || op == 58 || op == 62)
1613 /* Determine where to set a single step breakpoint while considering
1614 branch prediction. */
1617 mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
1619 struct gdbarch *gdbarch = regcache->arch ();
1622 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
1623 op = itype_op (inst);
1624 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch
1628 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1639 goto greater_branch;
1644 else if (op == 17 && itype_rs (inst) == 8)
1645 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1646 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);
1647 else if (op == 17 && itype_rs (inst) == 9
1648 && (itype_rt (inst) & 2) == 0)
1649 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1650 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);
1651 else if (op == 17 && itype_rs (inst) == 10
1652 && (itype_rt (inst) & 2) == 0)
1653 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1654 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);
1657 /* The new PC will be alternate mode. */
1661 reg = jtype_target (inst) << 2;
1662 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1663 pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1;
1665 else if (is_octeon_bbit_op (op, gdbarch))
1669 branch_if = op == 58 || op == 62;
1670 bit = itype_rt (inst);
1672 /* Take into account the *32 instructions. */
1673 if (op == 54 || op == 62)
1676 if (((regcache_raw_get_signed (regcache,
1677 itype_rs (inst)) >> bit) & 1)
1679 pc += mips32_relative_offset (inst) + 4;
1681 pc += 8; /* After the delay slot. */
1685 pc += 4; /* Not a branch, next instruction is easy. */
1688 { /* This gets way messy. */
1690 /* Further subdivide into SPECIAL, REGIMM and other. */
1691 switch (op & 0x07) /* Extract bits 28,27,26. */
1693 case 0: /* SPECIAL */
1694 op = rtype_funct (inst);
1699 /* Set PC to that address. */
1700 pc = regcache_raw_get_signed (regcache, rtype_rs (inst));
1702 case 12: /* SYSCALL */
1704 struct gdbarch_tdep *tdep;
1706 tdep = gdbarch_tdep (gdbarch);
1707 if (tdep->syscall_next_pc != NULL)
1708 pc = tdep->syscall_next_pc (get_current_frame ());
1717 break; /* end SPECIAL */
1718 case 1: /* REGIMM */
1720 op = itype_rt (inst); /* branch condition */
1725 case 16: /* BLTZAL */
1726 case 18: /* BLTZALL */
1728 if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)
1729 pc += mips32_relative_offset (inst) + 4;
1731 pc += 8; /* after the delay slot */
1735 case 17: /* BGEZAL */
1736 case 19: /* BGEZALL */
1737 if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0)
1738 pc += mips32_relative_offset (inst) + 4;
1740 pc += 8; /* after the delay slot */
1742 case 0x1c: /* BPOSGE32 */
1743 case 0x1e: /* BPOSGE64 */
1745 if (itype_rs (inst) == 0)
1747 unsigned int pos = (op & 2) ? 64 : 32;
1748 int dspctl = mips_regnum (gdbarch)->dspctl;
1751 /* No way to handle; it'll most likely trap anyway. */
1754 if ((regcache_raw_get_unsigned (regcache,
1755 dspctl) & 0x7f) >= pos)
1756 pc += mips32_relative_offset (inst);
1761 /* All of the other instructions in the REGIMM category */
1766 break; /* end REGIMM */
1771 reg = jtype_target (inst) << 2;
1772 /* Upper four bits get never changed... */
1773 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1776 case 4: /* BEQ, BEQL */
1778 if (regcache_raw_get_signed (regcache, itype_rs (inst)) ==
1779 regcache_raw_get_signed (regcache, itype_rt (inst)))
1780 pc += mips32_relative_offset (inst) + 4;
1784 case 5: /* BNE, BNEL */
1786 if (regcache_raw_get_signed (regcache, itype_rs (inst)) !=
1787 regcache_raw_get_signed (regcache, itype_rt (inst)))
1788 pc += mips32_relative_offset (inst) + 4;
1792 case 6: /* BLEZ, BLEZL */
1793 if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0)
1794 pc += mips32_relative_offset (inst) + 4;
1800 greater_branch: /* BGTZ, BGTZL */
1801 if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)
1802 pc += mips32_relative_offset (inst) + 4;
1809 } /* mips32_next_pc */
1811 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1815 micromips_relative_offset7 (ULONGEST insn)
1817 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1;
1820 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1824 micromips_relative_offset10 (ULONGEST insn)
1826 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1;
1829 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1833 micromips_relative_offset16 (ULONGEST insn)
1835 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1;
1838 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1841 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc)
1845 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1846 return mips_insn_size (ISA_MICROMIPS, insn);
1849 /* Calculate the address of the next microMIPS instruction to execute
1850 after the INSN coprocessor 1 conditional branch instruction at the
1851 address PC. COUNT denotes the number of coprocessor condition bits
1852 examined by the branch. */
1855 micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
1856 ULONGEST insn, CORE_ADDR pc, int count)
1858 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1859 int cnum = b2s3_cc (insn >> 16) & (count - 1);
1860 int tf = b5s5_op (insn >> 16) & 1;
1861 int mask = (1 << count) - 1;
1866 /* No way to handle; it'll most likely trap anyway. */
1869 fcs = regcache_raw_get_unsigned (regcache, fcsr);
1870 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1872 if (((cond >> cnum) & mask) != mask * !tf)
1873 pc += micromips_relative_offset16 (insn);
1875 pc += micromips_pc_insn_size (gdbarch, pc);
1880 /* Calculate the address of the next microMIPS instruction to execute
1881 after the instruction at the address PC. */
1884 micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
1886 struct gdbarch *gdbarch = regcache->arch ();
1889 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1890 pc += MIPS_INSN16_SIZE;
1891 switch (mips_insn_size (ISA_MICROMIPS, insn))
1893 /* 32-bit instructions. */
1894 case 2 * MIPS_INSN16_SIZE:
1896 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1897 pc += MIPS_INSN16_SIZE;
1898 switch (micromips_op (insn >> 16))
1900 case 0x00: /* POOL32A: bits 000000 */
1901 switch (b0s6_op (insn))
1903 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1904 switch (b6s10_ext (insn))
1906 case 0x3c: /* JALR: 000000 0000111100 111100 */
1907 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1908 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1909 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1910 pc = regcache_raw_get_signed (regcache,
1911 b0s5_reg (insn >> 16));
1913 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1915 struct gdbarch_tdep *tdep;
1917 tdep = gdbarch_tdep (gdbarch);
1918 if (tdep->syscall_next_pc != NULL)
1919 pc = tdep->syscall_next_pc (get_current_frame ());
1927 case 0x10: /* POOL32I: bits 010000 */
1928 switch (b5s5_op (insn >> 16))
1930 case 0x00: /* BLTZ: bits 010000 00000 */
1931 case 0x01: /* BLTZAL: bits 010000 00001 */
1932 case 0x11: /* BLTZALS: bits 010000 10001 */
1933 if (regcache_raw_get_signed (regcache,
1934 b0s5_reg (insn >> 16)) < 0)
1935 pc += micromips_relative_offset16 (insn);
1937 pc += micromips_pc_insn_size (gdbarch, pc);
1940 case 0x02: /* BGEZ: bits 010000 00010 */
1941 case 0x03: /* BGEZAL: bits 010000 00011 */
1942 case 0x13: /* BGEZALS: bits 010000 10011 */
1943 if (regcache_raw_get_signed (regcache,
1944 b0s5_reg (insn >> 16)) >= 0)
1945 pc += micromips_relative_offset16 (insn);
1947 pc += micromips_pc_insn_size (gdbarch, pc);
1950 case 0x04: /* BLEZ: bits 010000 00100 */
1951 if (regcache_raw_get_signed (regcache,
1952 b0s5_reg (insn >> 16)) <= 0)
1953 pc += micromips_relative_offset16 (insn);
1955 pc += micromips_pc_insn_size (gdbarch, pc);
1958 case 0x05: /* BNEZC: bits 010000 00101 */
1959 if (regcache_raw_get_signed (regcache,
1960 b0s5_reg (insn >> 16)) != 0)
1961 pc += micromips_relative_offset16 (insn);
1964 case 0x06: /* BGTZ: bits 010000 00110 */
1965 if (regcache_raw_get_signed (regcache,
1966 b0s5_reg (insn >> 16)) > 0)
1967 pc += micromips_relative_offset16 (insn);
1969 pc += micromips_pc_insn_size (gdbarch, pc);
1972 case 0x07: /* BEQZC: bits 010000 00111 */
1973 if (regcache_raw_get_signed (regcache,
1974 b0s5_reg (insn >> 16)) == 0)
1975 pc += micromips_relative_offset16 (insn);
1978 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1979 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1980 if (((insn >> 16) & 0x3) == 0x0)
1981 /* BC2F, BC2T: don't know how to handle these. */
1985 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1986 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1988 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64;
1989 int dspctl = mips_regnum (gdbarch)->dspctl;
1992 /* No way to handle; it'll most likely trap anyway. */
1995 if ((regcache_raw_get_unsigned (regcache,
1996 dspctl) & 0x7f) >= pos)
1997 pc += micromips_relative_offset16 (insn);
1999 pc += micromips_pc_insn_size (gdbarch, pc);
2003 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2004 /* BC1ANY2F: bits 010000 11100 xxx01 */
2005 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2006 /* BC1ANY2T: bits 010000 11101 xxx01 */
2007 if (((insn >> 16) & 0x2) == 0x0)
2008 pc = micromips_bc1_pc (gdbarch, regcache, insn, pc,
2009 ((insn >> 16) & 0x1) + 1);
2012 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2013 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2014 if (((insn >> 16) & 0x3) == 0x1)
2015 pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4);
2020 case 0x1d: /* JALS: bits 011101 */
2021 case 0x35: /* J: bits 110101 */
2022 case 0x3d: /* JAL: bits 111101 */
2023 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1);
2026 case 0x25: /* BEQ: bits 100101 */
2027 if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
2028 == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
2029 pc += micromips_relative_offset16 (insn);
2031 pc += micromips_pc_insn_size (gdbarch, pc);
2034 case 0x2d: /* BNE: bits 101101 */
2035 if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
2036 != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
2037 pc += micromips_relative_offset16 (insn);
2039 pc += micromips_pc_insn_size (gdbarch, pc);
2042 case 0x3c: /* JALX: bits 111100 */
2043 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2);
2048 /* 16-bit instructions. */
2049 case MIPS_INSN16_SIZE:
2050 switch (micromips_op (insn))
2052 case 0x11: /* POOL16C: bits 010001 */
2053 if ((b5s5_op (insn) & 0x1c) == 0xc)
2054 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2055 pc = regcache_raw_get_signed (regcache, b0s5_reg (insn));
2056 else if (b5s5_op (insn) == 0x18)
2057 /* JRADDIUSP: bits 010001 11000 */
2058 pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM);
2061 case 0x23: /* BEQZ16: bits 100011 */
2063 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
2065 if (regcache_raw_get_signed (regcache, rs) == 0)
2066 pc += micromips_relative_offset7 (insn);
2068 pc += micromips_pc_insn_size (gdbarch, pc);
2072 case 0x2b: /* BNEZ16: bits 101011 */
2074 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
2076 if (regcache_raw_get_signed (regcache, rs) != 0)
2077 pc += micromips_relative_offset7 (insn);
2079 pc += micromips_pc_insn_size (gdbarch, pc);
2083 case 0x33: /* B16: bits 110011 */
2084 pc += micromips_relative_offset10 (insn);
2093 /* Decoding the next place to set a breakpoint is irregular for the
2094 mips 16 variant, but fortunately, there fewer instructions. We have
2095 to cope ith extensions for 16 bit instructions and a pair of actual
2096 32 bit instructions. We dont want to set a single step instruction
2097 on the extend instruction either. */
2099 /* Lots of mips16 instruction formats */
2100 /* Predicting jumps requires itype,ritype,i8type
2101 and their extensions extItype,extritype,extI8type. */
2102 enum mips16_inst_fmts
2104 itype, /* 0 immediate 5,10 */
2105 ritype, /* 1 5,3,8 */
2106 rrtype, /* 2 5,3,3,5 */
2107 rritype, /* 3 5,3,3,5 */
2108 rrrtype, /* 4 5,3,3,3,2 */
2109 rriatype, /* 5 5,3,3,1,4 */
2110 shifttype, /* 6 5,3,3,3,2 */
2111 i8type, /* 7 5,3,8 */
2112 i8movtype, /* 8 5,3,3,5 */
2113 i8mov32rtype, /* 9 5,3,5,3 */
2114 i64type, /* 10 5,3,8 */
2115 ri64type, /* 11 5,3,3,5 */
2116 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
2117 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2118 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
2119 extRRItype, /* 15 5,5,5,5,3,3,5 */
2120 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
2121 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2122 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
2123 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
2124 extRi64type, /* 20 5,6,5,5,3,3,5 */
2125 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2127 /* I am heaping all the fields of the formats into one structure and
2128 then, only the fields which are involved in instruction extension. */
2132 unsigned int regx; /* Function in i8 type. */
2137 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2138 for the bits which make up the immediate extension. */
2141 extended_offset (unsigned int extension)
2145 value = (extension >> 16) & 0x1f; /* Extract 15:11. */
2147 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */
2149 value |= extension & 0x1f; /* Extract 4:0. */
2154 /* Only call this function if you know that this is an extendable
2155 instruction. It won't malfunction, but why make excess remote memory
2156 references? If the immediate operands get sign extended or something,
2157 do it after the extension is performed. */
2158 /* FIXME: Every one of these cases needs to worry about sign extension
2159 when the offset is to be used in relative addressing. */
2162 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc)
2164 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2167 pc = unmake_compact_addr (pc); /* Clear the low order bit. */
2168 target_read_memory (pc, buf, 2);
2169 return extract_unsigned_integer (buf, 2, byte_order);
2173 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc,
2174 unsigned int extension,
2176 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
2181 switch (insn_format)
2188 value = extended_offset ((extension << 16) | inst);
2189 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2193 value = inst & 0x7ff;
2194 value = (value ^ 0x400) - 0x400; /* Sign-extend. */
2203 { /* A register identifier and an offset. */
2204 /* Most of the fields are the same as I type but the
2205 immediate value is of a different length. */
2209 value = extended_offset ((extension << 16) | inst);
2210 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2214 value = inst & 0xff; /* 8 bits */
2215 value = (value ^ 0x80) - 0x80; /* Sign-extend. */
2218 regx = (inst >> 8) & 0x07; /* i8 funct */
2224 unsigned long value;
2225 unsigned int nexthalf;
2226 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
2227 value = value << 16;
2228 nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL);
2229 /* Low bit still set. */
2237 internal_error (__FILE__, __LINE__, _("bad switch"));
2239 upk->offset = offset;
2245 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2246 and having a signed 16-bit OFFSET. */
2249 add_offset_16 (CORE_ADDR pc, int offset)
2251 return pc + (offset << 1) + 2;
2255 extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc,
2256 unsigned int extension, unsigned int insn)
2258 struct gdbarch *gdbarch = regcache->arch ();
2259 int op = (insn >> 11);
2262 case 2: /* Branch */
2264 struct upk_mips16 upk;
2265 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk);
2266 pc = add_offset_16 (pc, upk.offset);
2269 case 3: /* JAL , JALX - Watch out, these are 32 bit
2272 struct upk_mips16 upk;
2273 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk);
2274 pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2);
2275 if ((insn >> 10) & 0x01) /* Exchange mode */
2276 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */
2283 struct upk_mips16 upk;
2285 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2286 reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]);
2288 pc = add_offset_16 (pc, upk.offset);
2295 struct upk_mips16 upk;
2297 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2298 reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]);
2300 pc = add_offset_16 (pc, upk.offset);
2305 case 12: /* I8 Formats btez btnez */
2307 struct upk_mips16 upk;
2309 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
2310 /* upk.regx contains the opcode */
2311 /* Test register is 24 */
2312 reg = regcache_raw_get_signed (regcache, 24);
2313 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
2314 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
2315 pc = add_offset_16 (pc, upk.offset);
2320 case 29: /* RR Formats JR, JALR, JALR-RA */
2322 struct upk_mips16 upk;
2323 /* upk.fmt = rrtype; */
2328 upk.regx = (insn >> 8) & 0x07;
2329 upk.regy = (insn >> 5) & 0x07;
2330 if ((upk.regy & 1) == 0)
2331 reg = mips_reg3_to_reg[upk.regx];
2333 reg = 31; /* Function return instruction. */
2334 pc = regcache_raw_get_signed (regcache, reg);
2341 /* This is an instruction extension. Fetch the real instruction
2342 (which follows the extension) and decode things based on
2346 pc = extended_mips16_next_pc (regcache, pc, insn,
2347 fetch_mips_16 (gdbarch, pc));
2360 mips16_next_pc (struct regcache *regcache, CORE_ADDR pc)
2362 struct gdbarch *gdbarch = regcache->arch ();
2363 unsigned int insn = fetch_mips_16 (gdbarch, pc);
2364 return extended_mips16_next_pc (regcache, pc, 0, insn);
2367 /* The mips_next_pc function supports single_step when the remote
2368 target monitor or stub is not developed enough to do a single_step.
2369 It works by decoding the current instruction and predicting where a
2370 branch will go. This isn't hard because all the data is available.
2371 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2373 mips_next_pc (struct regcache *regcache, CORE_ADDR pc)
2375 struct gdbarch *gdbarch = regcache->arch ();
2377 if (mips_pc_is_mips16 (gdbarch, pc))
2378 return mips16_next_pc (regcache, pc);
2379 else if (mips_pc_is_micromips (gdbarch, pc))
2380 return micromips_next_pc (regcache, pc);
2382 return mips32_next_pc (regcache, pc);
2385 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2389 mips16_instruction_is_compact_branch (unsigned short insn)
2391 switch (insn & 0xf800)
2394 return (insn & 0x009f) == 0x80; /* JALRC/JRC */
2396 return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */
2397 case 0x2800: /* BNEZ */
2398 case 0x2000: /* BEQZ */
2399 case 0x1000: /* B */
2406 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2410 micromips_instruction_is_compact_branch (unsigned short insn)
2412 switch (micromips_op (insn))
2414 case 0x11: /* POOL16C: bits 010001 */
2415 return (b5s5_op (insn) == 0x18
2416 /* JRADDIUSP: bits 010001 11000 */
2417 || b5s5_op (insn) == 0xd);
2418 /* JRC: bits 010011 01101 */
2419 case 0x10: /* POOL32I: bits 010000 */
2420 return (b5s5_op (insn) & 0x1d) == 0x5;
2421 /* BEQZC/BNEZC: bits 010000 001x1 */
2427 struct mips_frame_cache
2430 struct trad_frame_saved_reg *saved_regs;
2433 /* Set a register's saved stack address in temp_saved_regs. If an
2434 address has already been set for this register, do nothing; this
2435 way we will only recognize the first save of a given register in a
2438 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2439 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2440 Strictly speaking, only the second range is used as it is only second
2441 range (the ABI instead of ISA registers) that comes into play when finding
2442 saved registers in a frame. */
2445 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
2446 int regnum, CORE_ADDR offset)
2448 if (this_cache != NULL
2449 && this_cache->saved_regs[regnum].addr == -1)
2451 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
2453 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
2459 /* Fetch the immediate value from a MIPS16 instruction.
2460 If the previous instruction was an EXTEND, use it to extend
2461 the upper bits of the immediate value. This is a helper function
2462 for mips16_scan_prologue. */
2465 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
2466 unsigned short inst, /* current instruction */
2467 int nbits, /* number of bits in imm field */
2468 int scale, /* scale factor to be applied to imm */
2469 int is_signed) /* is the imm field signed? */
2473 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2475 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
2476 if (offset & 0x8000) /* check for negative extend */
2477 offset = 0 - (0x10000 - (offset & 0xffff));
2478 return offset | (inst & 0x1f);
2482 int max_imm = 1 << nbits;
2483 int mask = max_imm - 1;
2484 int sign_bit = max_imm >> 1;
2486 offset = inst & mask;
2487 if (is_signed && (offset & sign_bit))
2488 offset = 0 - (max_imm - offset);
2489 return offset * scale;
2494 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2495 the associated FRAME_CACHE if not null.
2496 Return the address of the first instruction past the prologue. */
2499 mips16_scan_prologue (struct gdbarch *gdbarch,
2500 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2501 struct frame_info *this_frame,
2502 struct mips_frame_cache *this_cache)
2504 int prev_non_prologue_insn = 0;
2505 int this_non_prologue_insn;
2506 int non_prologue_insns = 0;
2509 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */
2511 long frame_offset = 0; /* Size of stack frame. */
2512 long frame_adjust = 0; /* Offset of FP from SP. */
2513 int frame_reg = MIPS_SP_REGNUM;
2514 unsigned short prev_inst = 0; /* saved copy of previous instruction. */
2515 unsigned inst = 0; /* current instruction */
2516 unsigned entry_inst = 0; /* the entry instruction */
2517 unsigned save_inst = 0; /* the save instruction */
2518 int prev_delay_slot = 0;
2522 int extend_bytes = 0;
2523 int prev_extend_bytes = 0;
2524 CORE_ADDR end_prologue_addr;
2526 /* Can be called when there's no process, and hence when there's no
2528 if (this_frame != NULL)
2529 sp = get_frame_register_signed (this_frame,
2530 gdbarch_num_regs (gdbarch)
2535 if (limit_pc > start_pc + 200)
2536 limit_pc = start_pc + 200;
2539 /* Permit at most one non-prologue non-control-transfer instruction
2540 in the middle which may have been reordered by the compiler for
2542 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
2544 this_non_prologue_insn = 0;
2547 /* Save the previous instruction. If it's an EXTEND, we'll extract
2548 the immediate offset extension from it in mips16_get_imm. */
2551 /* Fetch and decode the instruction. */
2552 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16,
2555 /* Normally we ignore extend instructions. However, if it is
2556 not followed by a valid prologue instruction, then this
2557 instruction is not part of the prologue either. We must
2558 remember in this case to adjust the end_prologue_addr back
2560 if ((inst & 0xf800) == 0xf000) /* extend */
2562 extend_bytes = MIPS_INSN16_SIZE;
2566 prev_extend_bytes = extend_bytes;
2569 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2570 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2572 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2573 if (offset < 0) /* Negative stack adjustment? */
2574 frame_offset -= offset;
2576 /* Exit loop if a positive stack adjustment is found, which
2577 usually means that the stack cleanup code in the function
2578 epilogue is reached. */
2581 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2583 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2584 reg = mips_reg3_to_reg[(inst & 0x700) >> 8];
2585 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2587 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2589 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2590 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2591 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2593 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2595 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2596 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2598 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2600 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2601 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2603 else if (inst == 0x673d) /* move $s1, $sp */
2608 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2610 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2611 frame_addr = sp + offset;
2613 frame_adjust = offset;
2615 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2617 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2618 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2619 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2621 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2623 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2624 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2625 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2627 else if ((inst & 0xf81f) == 0xe809
2628 && (inst & 0x700) != 0x700) /* entry */
2629 entry_inst = inst; /* Save for later processing. */
2630 else if ((inst & 0xff80) == 0x6480) /* save */
2632 save_inst = inst; /* Save for later processing. */
2633 if (prev_extend_bytes) /* extend */
2634 save_inst |= prev_inst << 16;
2636 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2638 /* This instruction is part of the prologue, but we don't
2639 need to do anything special to handle it. */
2641 else if (mips16_instruction_has_delay_slot (inst, 0))
2642 /* JAL/JALR/JALX/JR */
2644 /* The instruction in the delay slot can be a part
2645 of the prologue, so move forward once more. */
2647 if (mips16_instruction_has_delay_slot (inst, 1))
2650 prev_extend_bytes = MIPS_INSN16_SIZE;
2651 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
2656 this_non_prologue_insn = 1;
2659 non_prologue_insns += this_non_prologue_insn;
2661 /* A jump or branch, or enough non-prologue insns seen? If so,
2662 then we must have reached the end of the prologue by now. */
2663 if (prev_delay_slot || non_prologue_insns > 1
2664 || mips16_instruction_is_compact_branch (inst))
2667 prev_non_prologue_insn = this_non_prologue_insn;
2668 prev_delay_slot = in_delay_slot;
2669 prev_pc = cur_pc - prev_extend_bytes;
2672 /* The entry instruction is typically the first instruction in a function,
2673 and it stores registers at offsets relative to the value of the old SP
2674 (before the prologue). But the value of the sp parameter to this
2675 function is the new SP (after the prologue has been executed). So we
2676 can't calculate those offsets until we've seen the entire prologue,
2677 and can calculate what the old SP must have been. */
2678 if (entry_inst != 0)
2680 int areg_count = (entry_inst >> 8) & 7;
2681 int sreg_count = (entry_inst >> 6) & 3;
2683 /* The entry instruction always subtracts 32 from the SP. */
2686 /* Now we can calculate what the SP must have been at the
2687 start of the function prologue. */
2690 /* Check if a0-a3 were saved in the caller's argument save area. */
2691 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2693 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2694 offset += mips_abi_regsize (gdbarch);
2697 /* Check if the ra register was pushed on the stack. */
2699 if (entry_inst & 0x20)
2701 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2702 offset -= mips_abi_regsize (gdbarch);
2705 /* Check if the s0 and s1 registers were pushed on the stack. */
2706 for (reg = 16; reg < sreg_count + 16; reg++)
2708 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2709 offset -= mips_abi_regsize (gdbarch);
2713 /* The SAVE instruction is similar to ENTRY, except that defined by the
2714 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2715 size of the frame is specified as an immediate field of instruction
2716 and an extended variation exists which lets additional registers and
2717 frame space to be specified. The instruction always treats registers
2718 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2719 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
2721 static int args_table[16] = {
2722 0, 0, 0, 0, 1, 1, 1, 1,
2723 2, 2, 2, 0, 3, 3, 4, -1,
2725 static int astatic_table[16] = {
2726 0, 1, 2, 3, 0, 1, 2, 3,
2727 0, 1, 2, 4, 0, 1, 0, -1,
2729 int aregs = (save_inst >> 16) & 0xf;
2730 int xsregs = (save_inst >> 24) & 0x7;
2731 int args = args_table[aregs];
2732 int astatic = astatic_table[aregs];
2737 warning (_("Invalid number of argument registers encoded in SAVE."));
2742 warning (_("Invalid number of static registers encoded in SAVE."));
2746 /* For standard SAVE the frame size of 0 means 128. */
2747 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
2748 if (frame_size == 0 && (save_inst >> 16) == 0)
2751 frame_offset += frame_size;
2753 /* Now we can calculate what the SP must have been at the
2754 start of the function prologue. */
2757 /* Check if A0-A3 were saved in the caller's argument save area. */
2758 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
2760 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2761 offset += mips_abi_regsize (gdbarch);
2766 /* Check if the RA register was pushed on the stack. */
2767 if (save_inst & 0x40)
2769 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2770 offset -= mips_abi_regsize (gdbarch);
2773 /* Check if the S8 register was pushed on the stack. */
2776 set_reg_offset (gdbarch, this_cache, 30, sp + offset);
2777 offset -= mips_abi_regsize (gdbarch);
2780 /* Check if S2-S7 were pushed on the stack. */
2781 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
2783 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2784 offset -= mips_abi_regsize (gdbarch);
2787 /* Check if the S1 register was pushed on the stack. */
2788 if (save_inst & 0x10)
2790 set_reg_offset (gdbarch, this_cache, 17, sp + offset);
2791 offset -= mips_abi_regsize (gdbarch);
2793 /* Check if the S0 register was pushed on the stack. */
2794 if (save_inst & 0x20)
2796 set_reg_offset (gdbarch, this_cache, 16, sp + offset);
2797 offset -= mips_abi_regsize (gdbarch);
2800 /* Check if A0-A3 were pushed on the stack. */
2801 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
2803 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2804 offset -= mips_abi_regsize (gdbarch);
2808 if (this_cache != NULL)
2811 (get_frame_register_signed (this_frame,
2812 gdbarch_num_regs (gdbarch) + frame_reg)
2813 + frame_offset - frame_adjust);
2814 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2815 be able to get rid of the assignment below, evetually. But it's
2816 still needed for now. */
2817 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2818 + mips_regnum (gdbarch)->pc]
2819 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
2822 /* Set end_prologue_addr to the address of the instruction immediately
2823 after the last one we scanned. Unless the last one looked like a
2824 non-prologue instruction (and we looked ahead), in which case use
2825 its address instead. */
2826 end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot
2827 ? prev_pc : cur_pc - prev_extend_bytes);
2829 return end_prologue_addr;
2832 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2833 Procedures that use the 32-bit instruction set are handled by the
2834 mips_insn32 unwinder. */
2836 static struct mips_frame_cache *
2837 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
2839 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2840 struct mips_frame_cache *cache;
2842 if ((*this_cache) != NULL)
2843 return (struct mips_frame_cache *) (*this_cache);
2844 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2845 (*this_cache) = cache;
2846 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2848 /* Analyze the function prologue. */
2850 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2851 CORE_ADDR start_addr;
2853 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2854 if (start_addr == 0)
2855 start_addr = heuristic_proc_start (gdbarch, pc);
2856 /* We can't analyze the prologue if we couldn't find the begining
2858 if (start_addr == 0)
2861 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame,
2862 (struct mips_frame_cache *) *this_cache);
2865 /* gdbarch_sp_regnum contains the value and not the address. */
2866 trad_frame_set_value (cache->saved_regs,
2867 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
2870 return (struct mips_frame_cache *) (*this_cache);
2874 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
2875 struct frame_id *this_id)
2877 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2879 /* This marks the outermost frame. */
2880 if (info->base == 0)
2882 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2885 static struct value *
2886 mips_insn16_frame_prev_register (struct frame_info *this_frame,
2887 void **this_cache, int regnum)
2889 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2891 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2895 mips_insn16_frame_sniffer (const struct frame_unwind *self,
2896 struct frame_info *this_frame, void **this_cache)
2898 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2899 CORE_ADDR pc = get_frame_pc (this_frame);
2900 if (mips_pc_is_mips16 (gdbarch, pc))
2905 static const struct frame_unwind mips_insn16_frame_unwind =
2908 default_frame_unwind_stop_reason,
2909 mips_insn16_frame_this_id,
2910 mips_insn16_frame_prev_register,
2912 mips_insn16_frame_sniffer
2916 mips_insn16_frame_base_address (struct frame_info *this_frame,
2919 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2924 static const struct frame_base mips_insn16_frame_base =
2926 &mips_insn16_frame_unwind,
2927 mips_insn16_frame_base_address,
2928 mips_insn16_frame_base_address,
2929 mips_insn16_frame_base_address
2932 static const struct frame_base *
2933 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
2935 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2936 CORE_ADDR pc = get_frame_pc (this_frame);
2937 if (mips_pc_is_mips16 (gdbarch, pc))
2938 return &mips_insn16_frame_base;
2943 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2944 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2945 interpreted directly, and then multiplied by 4. */
2948 micromips_decode_imm9 (int imm)
2950 imm = (imm ^ 0x100) - 0x100;
2951 if (imm > -3 && imm < 2)
2956 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2957 the address of the first instruction past the prologue. */
2960 micromips_scan_prologue (struct gdbarch *gdbarch,
2961 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2962 struct frame_info *this_frame,
2963 struct mips_frame_cache *this_cache)
2965 CORE_ADDR end_prologue_addr;
2966 int prev_non_prologue_insn = 0;
2967 int frame_reg = MIPS_SP_REGNUM;
2968 int this_non_prologue_insn;
2969 int non_prologue_insns = 0;
2970 long frame_offset = 0; /* Size of stack frame. */
2971 long frame_adjust = 0; /* Offset of FP from SP. */
2972 int prev_delay_slot = 0;
2976 ULONGEST insn; /* current instruction */
2980 long v1_off = 0; /* The assumption is LUI will replace it. */
2991 /* Can be called when there's no process, and hence when there's no
2993 if (this_frame != NULL)
2994 sp = get_frame_register_signed (this_frame,
2995 gdbarch_num_regs (gdbarch)
3000 if (limit_pc > start_pc + 200)
3001 limit_pc = start_pc + 200;
3004 /* Permit at most one non-prologue non-control-transfer instruction
3005 in the middle which may have been reordered by the compiler for
3007 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc)
3009 this_non_prologue_insn = 0;
3013 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL);
3014 loc += MIPS_INSN16_SIZE;
3015 switch (mips_insn_size (ISA_MICROMIPS, insn))
3017 /* 32-bit instructions. */
3018 case 2 * MIPS_INSN16_SIZE:
3020 insn |= mips_fetch_instruction (gdbarch,
3021 ISA_MICROMIPS, cur_pc + loc, NULL);
3022 loc += MIPS_INSN16_SIZE;
3023 switch (micromips_op (insn >> 16))
3025 /* Record $sp/$fp adjustment. */
3026 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3027 case 0x0: /* POOL32A: bits 000000 */
3028 case 0x16: /* POOL32S: bits 010110 */
3029 op = b0s11_op (insn);
3030 sreg = b0s5_reg (insn >> 16);
3031 treg = b5s5_reg (insn >> 16);
3032 dreg = b11s5_reg (insn);
3034 /* SUBU: bits 000000 00111010000 */
3035 /* DSUBU: bits 010110 00111010000 */
3036 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM
3038 /* (D)SUBU $sp, $v1 */
3040 else if (op != 0x150
3041 /* ADDU: bits 000000 00101010000 */
3042 /* DADDU: bits 010110 00101010000 */
3043 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM)
3044 this_non_prologue_insn = 1;
3047 case 0x8: /* POOL32B: bits 001000 */
3048 op = b12s4_op (insn);
3049 breg = b0s5_reg (insn >> 16);
3050 reglist = sreg = b5s5_reg (insn >> 16);
3051 offset = (b0s12_imm (insn) ^ 0x800) - 0x800;
3052 if ((op == 0x9 || op == 0xc)
3053 /* SWP: bits 001000 1001 */
3054 /* SDP: bits 001000 1100 */
3055 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM)
3056 /* S[DW]P reg,offset($sp) */
3058 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4);
3059 set_reg_offset (gdbarch, this_cache,
3061 set_reg_offset (gdbarch, this_cache,
3062 sreg + 1, sp + offset + s);
3064 else if ((op == 0xd || op == 0xf)
3065 /* SWM: bits 001000 1101 */
3066 /* SDM: bits 001000 1111 */
3067 && breg == MIPS_SP_REGNUM
3068 /* SWM reglist,offset($sp) */
3069 && ((reglist >= 1 && reglist <= 9)
3070 || (reglist >= 16 && reglist <= 25)))
3072 int sreglist = std::min(reglist & 0xf, 8);
3074 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2);
3075 for (i = 0; i < sreglist; i++)
3076 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i);
3077 if ((reglist & 0xf) > 8)
3078 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++);
3079 if ((reglist & 0x10) == 0x10)
3080 set_reg_offset (gdbarch, this_cache,
3081 MIPS_RA_REGNUM, sp + s * i++);
3084 this_non_prologue_insn = 1;
3087 /* Record $sp/$fp adjustment. */
3088 /* Discard (D)ADDIU $gp used for PIC code. */
3089 case 0xc: /* ADDIU: bits 001100 */
3090 case 0x17: /* DADDIU: bits 010111 */
3091 sreg = b0s5_reg (insn >> 16);
3092 dreg = b5s5_reg (insn >> 16);
3093 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
3094 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM)
3095 /* (D)ADDIU $sp, imm */
3097 else if (sreg == MIPS_SP_REGNUM && dreg == 30)
3098 /* (D)ADDIU $fp, $sp, imm */
3100 frame_adjust = offset;
3103 else if (sreg != 28 || dreg != 28)
3104 /* (D)ADDIU $gp, imm */
3105 this_non_prologue_insn = 1;
3108 /* LUI $v1 is used for larger $sp adjustments. */
3109 /* Discard LUI $gp used for PIC code. */
3110 case 0x10: /* POOL32I: bits 010000 */
3111 if (b5s5_op (insn >> 16) == 0xd
3112 /* LUI: bits 010000 001101 */
3113 && b0s5_reg (insn >> 16) == 3)
3115 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000;
3116 else if (b5s5_op (insn >> 16) != 0xd
3117 /* LUI: bits 010000 001101 */
3118 || b0s5_reg (insn >> 16) != 28)
3120 this_non_prologue_insn = 1;
3123 /* ORI $v1 is used for larger $sp adjustments. */
3124 case 0x14: /* ORI: bits 010100 */
3125 sreg = b0s5_reg (insn >> 16);
3126 dreg = b5s5_reg (insn >> 16);
3127 if (sreg == 3 && dreg == 3)
3129 v1_off |= b0s16_imm (insn);
3131 this_non_prologue_insn = 1;
3134 case 0x26: /* SWC1: bits 100110 */
3135 case 0x2e: /* SDC1: bits 101110 */
3136 breg = b0s5_reg (insn >> 16);
3137 if (breg != MIPS_SP_REGNUM)
3138 /* S[DW]C1 reg,offset($sp) */
3139 this_non_prologue_insn = 1;
3142 case 0x36: /* SD: bits 110110 */
3143 case 0x3e: /* SW: bits 111110 */
3144 breg = b0s5_reg (insn >> 16);
3145 sreg = b5s5_reg (insn >> 16);
3146 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
3147 if (breg == MIPS_SP_REGNUM)
3148 /* S[DW] reg,offset($sp) */
3149 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
3151 this_non_prologue_insn = 1;
3155 /* The instruction in the delay slot can be a part
3156 of the prologue, so move forward once more. */
3157 if (micromips_instruction_has_delay_slot (insn, 0))
3160 this_non_prologue_insn = 1;
3166 /* 16-bit instructions. */
3167 case MIPS_INSN16_SIZE:
3168 switch (micromips_op (insn))
3170 case 0x3: /* MOVE: bits 000011 */
3171 sreg = b0s5_reg (insn);
3172 dreg = b5s5_reg (insn);
3173 if (sreg == MIPS_SP_REGNUM && dreg == 30)
3176 else if ((sreg & 0x1c) != 0x4)
3177 /* MOVE reg, $a0-$a3 */
3178 this_non_prologue_insn = 1;
3181 case 0x11: /* POOL16C: bits 010001 */
3182 if (b6s4_op (insn) == 0x5)
3183 /* SWM: bits 010001 0101 */
3185 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20;
3186 reglist = b4s2_regl (insn);
3187 for (i = 0; i <= reglist; i++)
3188 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i);
3189 set_reg_offset (gdbarch, this_cache,
3190 MIPS_RA_REGNUM, sp + 4 * i++);
3193 this_non_prologue_insn = 1;
3196 case 0x13: /* POOL16D: bits 010011 */
3197 if ((insn & 0x1) == 0x1)
3198 /* ADDIUSP: bits 010011 1 */
3199 sp_adj = micromips_decode_imm9 (b1s9_imm (insn));
3200 else if (b5s5_reg (insn) == MIPS_SP_REGNUM)
3201 /* ADDIUS5: bits 010011 0 */
3202 /* ADDIUS5 $sp, imm */
3203 sp_adj = (b1s4_imm (insn) ^ 8) - 8;
3205 this_non_prologue_insn = 1;
3208 case 0x32: /* SWSP: bits 110010 */
3209 offset = b0s5_imm (insn) << 2;
3210 sreg = b5s5_reg (insn);
3211 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
3215 /* The instruction in the delay slot can be a part
3216 of the prologue, so move forward once more. */
3217 if (micromips_instruction_has_delay_slot (insn << 16, 0))
3220 this_non_prologue_insn = 1;
3226 frame_offset -= sp_adj;
3228 non_prologue_insns += this_non_prologue_insn;
3230 /* A jump or branch, enough non-prologue insns seen or positive
3231 stack adjustment? If so, then we must have reached the end
3232 of the prologue by now. */
3233 if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0
3234 || micromips_instruction_is_compact_branch (insn))
3237 prev_non_prologue_insn = this_non_prologue_insn;
3238 prev_delay_slot = in_delay_slot;
3242 if (this_cache != NULL)
3245 (get_frame_register_signed (this_frame,
3246 gdbarch_num_regs (gdbarch) + frame_reg)
3247 + frame_offset - frame_adjust);
3248 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3249 be able to get rid of the assignment below, evetually. But it's
3250 still needed for now. */
3251 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3252 + mips_regnum (gdbarch)->pc]
3253 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
3256 /* Set end_prologue_addr to the address of the instruction immediately
3257 after the last one we scanned. Unless the last one looked like a
3258 non-prologue instruction (and we looked ahead), in which case use
3259 its address instead. */
3261 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc;
3263 return end_prologue_addr;
3266 /* Heuristic unwinder for procedures using microMIPS instructions.
3267 Procedures that use the 32-bit instruction set are handled by the
3268 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3270 static struct mips_frame_cache *
3271 mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache)
3273 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3274 struct mips_frame_cache *cache;
3276 if ((*this_cache) != NULL)
3277 return (struct mips_frame_cache *) (*this_cache);
3279 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3280 (*this_cache) = cache;
3281 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3283 /* Analyze the function prologue. */
3285 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3286 CORE_ADDR start_addr;
3288 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3289 if (start_addr == 0)
3290 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc);
3291 /* We can't analyze the prologue if we couldn't find the begining
3293 if (start_addr == 0)
3296 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame,
3297 (struct mips_frame_cache *) *this_cache);
3300 /* gdbarch_sp_regnum contains the value and not the address. */
3301 trad_frame_set_value (cache->saved_regs,
3302 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3305 return (struct mips_frame_cache *) (*this_cache);
3309 mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache,
3310 struct frame_id *this_id)
3312 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3314 /* This marks the outermost frame. */
3315 if (info->base == 0)
3317 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3320 static struct value *
3321 mips_micro_frame_prev_register (struct frame_info *this_frame,
3322 void **this_cache, int regnum)
3324 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3326 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3330 mips_micro_frame_sniffer (const struct frame_unwind *self,
3331 struct frame_info *this_frame, void **this_cache)
3333 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3334 CORE_ADDR pc = get_frame_pc (this_frame);
3336 if (mips_pc_is_micromips (gdbarch, pc))
3341 static const struct frame_unwind mips_micro_frame_unwind =
3344 default_frame_unwind_stop_reason,
3345 mips_micro_frame_this_id,
3346 mips_micro_frame_prev_register,
3348 mips_micro_frame_sniffer
3352 mips_micro_frame_base_address (struct frame_info *this_frame,
3355 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3360 static const struct frame_base mips_micro_frame_base =
3362 &mips_micro_frame_unwind,
3363 mips_micro_frame_base_address,
3364 mips_micro_frame_base_address,
3365 mips_micro_frame_base_address
3368 static const struct frame_base *
3369 mips_micro_frame_base_sniffer (struct frame_info *this_frame)
3371 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3372 CORE_ADDR pc = get_frame_pc (this_frame);
3374 if (mips_pc_is_micromips (gdbarch, pc))
3375 return &mips_micro_frame_base;
3380 /* Mark all the registers as unset in the saved_regs array
3381 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3384 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
3386 if (this_cache == NULL || this_cache->saved_regs == NULL)
3390 const int num_regs = gdbarch_num_regs (gdbarch);
3393 for (i = 0; i < num_regs; i++)
3395 this_cache->saved_regs[i].addr = -1;
3400 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3401 the associated FRAME_CACHE if not null.
3402 Return the address of the first instruction past the prologue. */
3405 mips32_scan_prologue (struct gdbarch *gdbarch,
3406 CORE_ADDR start_pc, CORE_ADDR limit_pc,
3407 struct frame_info *this_frame,
3408 struct mips_frame_cache *this_cache)
3410 int prev_non_prologue_insn;
3411 int this_non_prologue_insn;
3412 int non_prologue_insns;
3413 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for
3415 int prev_delay_slot;
3420 int frame_reg = MIPS_SP_REGNUM;
3422 CORE_ADDR end_prologue_addr;
3423 int seen_sp_adjust = 0;
3424 int load_immediate_bytes = 0;
3426 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
3428 /* Can be called when there's no process, and hence when there's no
3430 if (this_frame != NULL)
3431 sp = get_frame_register_signed (this_frame,
3432 gdbarch_num_regs (gdbarch)
3437 if (limit_pc > start_pc + 200)
3438 limit_pc = start_pc + 200;
3441 prev_non_prologue_insn = 0;
3442 non_prologue_insns = 0;
3443 prev_delay_slot = 0;
3446 /* Permit at most one non-prologue non-control-transfer instruction
3447 in the middle which may have been reordered by the compiler for
3450 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
3452 unsigned long inst, high_word;
3456 this_non_prologue_insn = 0;
3459 /* Fetch the instruction. */
3460 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS,
3463 /* Save some code by pre-extracting some useful fields. */
3464 high_word = (inst >> 16) & 0xffff;
3465 offset = ((inst & 0xffff) ^ 0x8000) - 0x8000;
3466 reg = high_word & 0x1f;
3468 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
3469 || high_word == 0x23bd /* addi $sp,$sp,-i */
3470 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
3472 if (offset < 0) /* Negative stack adjustment? */
3473 frame_offset -= offset;
3475 /* Exit loop if a positive stack adjustment is found, which
3476 usually means that the stack cleanup code in the function
3477 epilogue is reached. */
3481 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3482 && !regsize_is_64_bits)
3484 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
3486 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3487 && regsize_is_64_bits)
3489 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3490 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
3492 else if (high_word == 0x27be) /* addiu $30,$sp,size */
3494 /* Old gcc frame, r30 is virtual frame pointer. */
3495 if (offset != frame_offset)
3496 frame_addr = sp + offset;
3497 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
3499 unsigned alloca_adjust;
3502 frame_addr = get_frame_register_signed
3503 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3506 alloca_adjust = (unsigned) (frame_addr - (sp + offset));
3507 if (alloca_adjust > 0)
3509 /* FP > SP + frame_size. This may be because of
3510 an alloca or somethings similar. Fix sp to
3511 "pre-alloca" value, and try again. */
3512 sp += alloca_adjust;
3513 /* Need to reset the status of all registers. Otherwise,
3514 we will hit a guard that prevents the new address
3515 for each register to be recomputed during the second
3517 reset_saved_regs (gdbarch, this_cache);
3522 /* move $30,$sp. With different versions of gas this will be either
3523 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3524 Accept any one of these. */
3525 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3527 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3528 if (this_frame && frame_reg == MIPS_SP_REGNUM)
3530 unsigned alloca_adjust;
3533 frame_addr = get_frame_register_signed
3534 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3536 alloca_adjust = (unsigned) (frame_addr - sp);
3537 if (alloca_adjust > 0)
3539 /* FP > SP + frame_size. This may be because of
3540 an alloca or somethings similar. Fix sp to
3541 "pre-alloca" value, and try again. */
3543 /* Need to reset the status of all registers. Otherwise,
3544 we will hit a guard that prevents the new address
3545 for each register to be recomputed during the second
3547 reset_saved_regs (gdbarch, this_cache);
3552 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3553 && !regsize_is_64_bits)
3555 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
3557 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3558 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3559 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3560 || high_word == 0x3c1c /* lui $gp,n */
3561 || high_word == 0x279c /* addiu $gp,$gp,n */
3562 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3563 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
3566 /* These instructions are part of the prologue, but we don't
3567 need to do anything special to handle them. */
3569 /* The instructions below load $at or $t0 with an immediate
3570 value in preparation for a stack adjustment via
3571 subu $sp,$sp,[$at,$t0]. These instructions could also
3572 initialize a local variable, so we accept them only before
3573 a stack adjustment instruction was seen. */
3574 else if (!seen_sp_adjust
3576 && (high_word == 0x3c01 /* lui $at,n */
3577 || high_word == 0x3c08 /* lui $t0,n */
3578 || high_word == 0x3421 /* ori $at,$at,n */
3579 || high_word == 0x3508 /* ori $t0,$t0,n */
3580 || high_word == 0x3401 /* ori $at,$zero,n */
3581 || high_word == 0x3408 /* ori $t0,$zero,n */
3584 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
3586 /* Check for branches and jumps. The instruction in the delay
3587 slot can be a part of the prologue, so move forward once more. */
3588 else if (mips32_instruction_has_delay_slot (gdbarch, inst))
3592 /* This instruction is not an instruction typically found
3593 in a prologue, so we must have reached the end of the
3597 this_non_prologue_insn = 1;
3600 non_prologue_insns += this_non_prologue_insn;
3602 /* A jump or branch, or enough non-prologue insns seen? If so,
3603 then we must have reached the end of the prologue by now. */
3604 if (prev_delay_slot || non_prologue_insns > 1)
3607 prev_non_prologue_insn = this_non_prologue_insn;
3608 prev_delay_slot = in_delay_slot;
3612 if (this_cache != NULL)
3615 (get_frame_register_signed (this_frame,
3616 gdbarch_num_regs (gdbarch) + frame_reg)
3618 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3619 this assignment below, eventually. But it's still needed
3621 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3622 + mips_regnum (gdbarch)->pc]
3623 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3627 /* Set end_prologue_addr to the address of the instruction immediately
3628 after the last one we scanned. Unless the last one looked like a
3629 non-prologue instruction (and we looked ahead), in which case use
3630 its address instead. */
3632 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc;
3634 /* In a frameless function, we might have incorrectly
3635 skipped some load immediate instructions. Undo the skipping
3636 if the load immediate was not followed by a stack adjustment. */
3637 if (load_immediate_bytes && !seen_sp_adjust)
3638 end_prologue_addr -= load_immediate_bytes;
3640 return end_prologue_addr;
3643 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3644 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3645 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3646 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3648 static struct mips_frame_cache *
3649 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
3651 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3652 struct mips_frame_cache *cache;
3654 if ((*this_cache) != NULL)
3655 return (struct mips_frame_cache *) (*this_cache);
3657 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3658 (*this_cache) = cache;
3659 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3661 /* Analyze the function prologue. */
3663 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3664 CORE_ADDR start_addr;
3666 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3667 if (start_addr == 0)
3668 start_addr = heuristic_proc_start (gdbarch, pc);
3669 /* We can't analyze the prologue if we couldn't find the begining
3671 if (start_addr == 0)
3674 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame,
3675 (struct mips_frame_cache *) *this_cache);
3678 /* gdbarch_sp_regnum contains the value and not the address. */
3679 trad_frame_set_value (cache->saved_regs,
3680 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3683 return (struct mips_frame_cache *) (*this_cache);
3687 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
3688 struct frame_id *this_id)
3690 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3692 /* This marks the outermost frame. */
3693 if (info->base == 0)
3695 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3698 static struct value *
3699 mips_insn32_frame_prev_register (struct frame_info *this_frame,
3700 void **this_cache, int regnum)
3702 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3704 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3708 mips_insn32_frame_sniffer (const struct frame_unwind *self,
3709 struct frame_info *this_frame, void **this_cache)
3711 CORE_ADDR pc = get_frame_pc (this_frame);
3712 if (mips_pc_is_mips (pc))
3717 static const struct frame_unwind mips_insn32_frame_unwind =
3720 default_frame_unwind_stop_reason,
3721 mips_insn32_frame_this_id,
3722 mips_insn32_frame_prev_register,
3724 mips_insn32_frame_sniffer
3728 mips_insn32_frame_base_address (struct frame_info *this_frame,
3731 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3736 static const struct frame_base mips_insn32_frame_base =
3738 &mips_insn32_frame_unwind,
3739 mips_insn32_frame_base_address,
3740 mips_insn32_frame_base_address,
3741 mips_insn32_frame_base_address
3744 static const struct frame_base *
3745 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
3747 CORE_ADDR pc = get_frame_pc (this_frame);
3748 if (mips_pc_is_mips (pc))
3749 return &mips_insn32_frame_base;
3754 static struct trad_frame_cache *
3755 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
3758 CORE_ADDR start_addr;
3759 CORE_ADDR stack_addr;
3760 struct trad_frame_cache *this_trad_cache;
3761 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3762 int num_regs = gdbarch_num_regs (gdbarch);
3764 if ((*this_cache) != NULL)
3765 return (struct trad_frame_cache *) (*this_cache);
3766 this_trad_cache = trad_frame_cache_zalloc (this_frame);
3767 (*this_cache) = this_trad_cache;
3769 /* The return address is in the link register. */
3770 trad_frame_set_reg_realreg (this_trad_cache,
3771 gdbarch_pc_regnum (gdbarch),
3772 num_regs + MIPS_RA_REGNUM);
3774 /* Frame ID, since it's a frameless / stackless function, no stack
3775 space is allocated and SP on entry is the current SP. */
3776 pc = get_frame_pc (this_frame);
3777 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3778 stack_addr = get_frame_register_signed (this_frame,
3779 num_regs + MIPS_SP_REGNUM);
3780 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
3782 /* Assume that the frame's base is the same as the
3784 trad_frame_set_this_base (this_trad_cache, stack_addr);
3786 return this_trad_cache;
3790 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
3791 struct frame_id *this_id)
3793 struct trad_frame_cache *this_trad_cache
3794 = mips_stub_frame_cache (this_frame, this_cache);
3795 trad_frame_get_id (this_trad_cache, this_id);
3798 static struct value *
3799 mips_stub_frame_prev_register (struct frame_info *this_frame,
3800 void **this_cache, int regnum)
3802 struct trad_frame_cache *this_trad_cache
3803 = mips_stub_frame_cache (this_frame, this_cache);
3804 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
3808 mips_stub_frame_sniffer (const struct frame_unwind *self,
3809 struct frame_info *this_frame, void **this_cache)
3812 CORE_ADDR pc = get_frame_address_in_block (this_frame);
3813 struct bound_minimal_symbol msym;
3815 /* Use the stub unwinder for unreadable code. */
3816 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
3819 if (in_plt_section (pc) || in_mips_stubs_section (pc))
3822 /* Calling a PIC function from a non-PIC function passes through a
3823 stub. The stub for foo is named ".pic.foo". */
3824 msym = lookup_minimal_symbol_by_pc (pc);
3825 if (msym.minsym != NULL
3826 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL
3827 && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
3833 static const struct frame_unwind mips_stub_frame_unwind =
3836 default_frame_unwind_stop_reason,
3837 mips_stub_frame_this_id,
3838 mips_stub_frame_prev_register,
3840 mips_stub_frame_sniffer
3844 mips_stub_frame_base_address (struct frame_info *this_frame,
3847 struct trad_frame_cache *this_trad_cache
3848 = mips_stub_frame_cache (this_frame, this_cache);
3849 return trad_frame_get_this_base (this_trad_cache);
3852 static const struct frame_base mips_stub_frame_base =
3854 &mips_stub_frame_unwind,
3855 mips_stub_frame_base_address,
3856 mips_stub_frame_base_address,
3857 mips_stub_frame_base_address
3860 static const struct frame_base *
3861 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
3863 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
3864 return &mips_stub_frame_base;
3869 /* mips_addr_bits_remove - remove useless address bits */
3872 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
3874 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3876 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
3877 /* This hack is a work-around for existing boards using PMON, the
3878 simulator, and any other 64-bit targets that doesn't have true
3879 64-bit addressing. On these targets, the upper 32 bits of
3880 addresses are ignored by the hardware. Thus, the PC or SP are
3881 likely to have been sign extended to all 1s by instruction
3882 sequences that load 32-bit addresses. For example, a typical
3883 piece of code that loads an address is this:
3885 lui $r2, <upper 16 bits>
3886 ori $r2, <lower 16 bits>
3888 But the lui sign-extends the value such that the upper 32 bits
3889 may be all 1s. The workaround is simply to mask off these
3890 bits. In the future, gcc may be changed to support true 64-bit
3891 addressing, and this masking will have to be disabled. */
3892 return addr &= 0xffffffffUL;
3898 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3899 instruction and ending with a SC/SCD instruction. If such a sequence
3900 is found, attempt to step through it. A breakpoint is placed at the end of
3903 /* Instructions used during single-stepping of atomic sequences, standard
3905 #define LL_OPCODE 0x30
3906 #define LLD_OPCODE 0x34
3907 #define SC_OPCODE 0x38
3908 #define SCD_OPCODE 0x3c
3910 static std::vector<CORE_ADDR>
3911 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
3913 CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
3915 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
3919 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
3920 const int atomic_sequence_length = 16; /* Instruction sequence length. */
3922 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3923 /* Assume all atomic sequences start with a ll/lld instruction. */
3924 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
3927 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3929 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
3932 loc += MIPS_INSN32_SIZE;
3933 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3935 /* Assume that there is at most one branch in the atomic
3936 sequence. If a branch is found, put a breakpoint in its
3937 destination address. */
3938 switch (itype_op (insn))
3940 case 0: /* SPECIAL */
3941 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
3942 return {}; /* fallback to the standard single-step code. */
3944 case 1: /* REGIMM */
3945 is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */
3946 || ((itype_rt (insn) & 0x1e) == 0
3947 && itype_rs (insn) == 0)); /* BPOSGE* */
3951 return {}; /* fallback to the standard single-step code. */
3958 case 22: /* BLEZL */
3959 case 23: /* BGTTL */
3963 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10)
3964 && (itype_rt (insn) & 0x2) == 0);
3965 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3970 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3975 branch_bp = loc + mips32_relative_offset (insn) + 4;
3976 if (last_breakpoint >= 1)
3977 return {}; /* More than one branch found, fallback to the
3978 standard single-step code. */
3979 breaks[1] = branch_bp;
3983 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
3987 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3988 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
3991 loc += MIPS_INSN32_SIZE;
3993 /* Insert a breakpoint right after the end of the atomic sequence. */
3996 /* Check for duplicated breakpoints. Check also for a breakpoint
3997 placed (branch instruction's destination) in the atomic sequence. */
3998 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
3999 last_breakpoint = 0;
4001 std::vector<CORE_ADDR> next_pcs;
4003 /* Effectively inserts the breakpoints. */
4004 for (index = 0; index <= last_breakpoint; index++)
4005 next_pcs.push_back (breaks[index]);
4010 static std::vector<CORE_ADDR>
4011 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
4014 const int atomic_sequence_length = 16; /* Instruction sequence length. */
4015 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
4016 CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
4017 CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's
4025 /* Assume all atomic sequences start with a ll/lld instruction. */
4026 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
4027 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */
4029 loc += MIPS_INSN16_SIZE;
4031 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
4032 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4034 loc += MIPS_INSN16_SIZE;
4036 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4037 that no atomic sequence is longer than "atomic_sequence_length"
4039 for (insn_count = 0;
4040 !sc_found && insn_count < atomic_sequence_length;
4045 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
4046 loc += MIPS_INSN16_SIZE;
4048 /* Assume that there is at most one conditional branch in the
4049 atomic sequence. If a branch is found, put a breakpoint in
4050 its destination address. */
4051 switch (mips_insn_size (ISA_MICROMIPS, insn))
4053 /* 32-bit instructions. */
4054 case 2 * MIPS_INSN16_SIZE:
4055 switch (micromips_op (insn))
4057 case 0x10: /* POOL32I: bits 010000 */
4058 if ((b5s5_op (insn) & 0x18) != 0x0
4059 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4060 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4061 && (b5s5_op (insn) & 0x1d) != 0x11
4062 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4063 && ((b5s5_op (insn) & 0x1e) != 0x14
4064 || (insn & 0x3) != 0x0)
4065 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4066 && (b5s5_op (insn) & 0x1e) != 0x1a
4067 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4068 && ((b5s5_op (insn) & 0x1e) != 0x1c
4069 || (insn & 0x3) != 0x0)
4070 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4071 && ((b5s5_op (insn) & 0x1c) != 0x1c
4072 || (insn & 0x3) != 0x1))
4073 /* BC1ANY*: bits 010000 111xx xxx01 */
4077 case 0x25: /* BEQ: bits 100101 */
4078 case 0x2d: /* BNE: bits 101101 */
4080 insn |= mips_fetch_instruction (gdbarch,
4081 ISA_MICROMIPS, loc, NULL);
4082 branch_bp = (loc + MIPS_INSN16_SIZE
4083 + micromips_relative_offset16 (insn));
4087 case 0x00: /* POOL32A: bits 000000 */
4089 insn |= mips_fetch_instruction (gdbarch,
4090 ISA_MICROMIPS, loc, NULL);
4091 if (b0s6_op (insn) != 0x3c
4092 /* POOL32Axf: bits 000000 ... 111100 */
4093 || (b6s10_ext (insn) & 0x2bf) != 0x3c)
4094 /* JALR, JALR.HB: 000000 000x111100 111100 */
4095 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4099 case 0x1d: /* JALS: bits 011101 */
4100 case 0x35: /* J: bits 110101 */
4101 case 0x3d: /* JAL: bits 111101 */
4102 case 0x3c: /* JALX: bits 111100 */
4103 return {}; /* Fall back to the standard single-step code. */
4105 case 0x18: /* POOL32C: bits 011000 */
4106 if ((b12s4_op (insn) & 0xb) == 0xb)
4107 /* SC, SCD: bits 011000 1x11 */
4111 loc += MIPS_INSN16_SIZE;
4114 /* 16-bit instructions. */
4115 case MIPS_INSN16_SIZE:
4116 switch (micromips_op (insn))
4118 case 0x23: /* BEQZ16: bits 100011 */
4119 case 0x2b: /* BNEZ16: bits 101011 */
4120 branch_bp = loc + micromips_relative_offset7 (insn);
4124 case 0x11: /* POOL16C: bits 010001 */
4125 if ((b5s5_op (insn) & 0x1c) != 0xc
4126 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4127 && b5s5_op (insn) != 0x18)
4128 /* JRADDIUSP: bits 010001 11000 */
4130 return {}; /* Fall back to the standard single-step code. */
4132 case 0x33: /* B16: bits 110011 */
4133 return {}; /* Fall back to the standard single-step code. */
4139 if (last_breakpoint >= 1)
4140 return {}; /* More than one branch found, fallback to the
4141 standard single-step code. */
4142 breaks[1] = branch_bp;
4149 /* Insert a breakpoint right after the end of the atomic sequence. */
4152 /* Check for duplicated breakpoints. Check also for a breakpoint
4153 placed (branch instruction's destination) in the atomic sequence */
4154 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
4155 last_breakpoint = 0;
4157 std::vector<CORE_ADDR> next_pcs;
4159 /* Effectively inserts the breakpoints. */
4160 for (index = 0; index <= last_breakpoint; index++)
4161 next_pcs.push_back (breaks[index]);
4166 static std::vector<CORE_ADDR>
4167 deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
4169 if (mips_pc_is_mips (pc))
4170 return mips_deal_with_atomic_sequence (gdbarch, pc);
4171 else if (mips_pc_is_micromips (gdbarch, pc))
4172 return micromips_deal_with_atomic_sequence (gdbarch, pc);
4177 /* mips_software_single_step() is called just before we want to resume
4178 the inferior, if we want to single-step it but there is no hardware
4179 or kernel single-step support (MIPS on GNU/Linux for example). We find
4180 the target of the coming instruction and breakpoint it. */
4182 std::vector<CORE_ADDR>
4183 mips_software_single_step (struct regcache *regcache)
4185 struct gdbarch *gdbarch = regcache->arch ();
4186 CORE_ADDR pc, next_pc;
4188 pc = regcache_read_pc (regcache);
4189 std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc);
4191 if (!next_pcs.empty ())
4194 next_pc = mips_next_pc (regcache, pc);
4199 /* Test whether the PC points to the return instruction at the
4200 end of a function. */
4203 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
4208 /* This used to check for MIPS16, but this piece of code is never
4209 called for MIPS16 functions. And likewise microMIPS ones. */
4210 gdb_assert (mips_pc_is_mips (pc));
4212 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
4214 return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */
4218 /* This fencepost looks highly suspicious to me. Removing it also
4219 seems suspicious as it could affect remote debugging across serial
4223 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
4229 struct inferior *inf;
4231 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4233 fence = start_pc - heuristic_fence_post;
4237 if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS)
4238 fence = VM_MIN_ADDRESS;
4240 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE;
4242 inf = current_inferior ();
4244 /* Search back for previous return. */
4245 for (start_pc -= instlen;; start_pc -= instlen)
4246 if (start_pc < fence)
4248 /* It's not clear to me why we reach this point when
4249 stop_soon, but with this test, at least we
4250 don't print out warnings for every child forked (eg, on
4251 decstation). 22apr93 rich@cygnus.com. */
4252 if (inf->control.stop_soon == NO_STOP_QUIETLY)
4254 static int blurb_printed = 0;
4256 warning (_("GDB can't find the start of the function at %s."),
4257 paddress (gdbarch, pc));
4261 /* This actually happens frequently in embedded
4262 development, when you first connect to a board
4263 and your stack pointer and pc are nowhere in
4264 particular. This message needs to give people
4265 in that situation enough information to
4266 determine that it's no big deal. */
4267 printf_filtered ("\n\
4268 GDB is unable to find the start of the function at %s\n\
4269 and thus can't determine the size of that function's stack frame.\n\
4270 This means that GDB may be unable to access that stack frame, or\n\
4271 the frames below it.\n\
4272 This problem is most likely caused by an invalid program counter or\n\
4274 However, if you think GDB should simply search farther back\n\
4275 from %s for code which looks like the beginning of a\n\
4276 function, you can increase the range of the search using the `set\n\
4277 heuristic-fence-post' command.\n",
4278 paddress (gdbarch, pc), paddress (gdbarch, pc));
4285 else if (mips_pc_is_mips16 (gdbarch, start_pc))
4287 unsigned short inst;
4289 /* On MIPS16, any one of the following is likely to be the
4290 start of a function:
4296 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4297 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL);
4298 if ((inst & 0xff80) == 0x6480) /* save */
4300 if (start_pc - instlen >= fence)
4302 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16,
4303 start_pc - instlen, NULL);
4304 if ((inst & 0xf800) == 0xf000) /* extend */
4305 start_pc -= instlen;
4309 else if (((inst & 0xf81f) == 0xe809
4310 && (inst & 0x700) != 0x700) /* entry */
4311 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
4312 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
4313 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
4315 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
4316 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
4321 else if (mips_pc_is_micromips (gdbarch, start_pc))
4329 /* On microMIPS, any one of the following is likely to be the
4330 start of a function:
4334 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
4335 switch (micromips_op (insn))
4337 case 0xc: /* ADDIU: bits 001100 */
4338 case 0x17: /* DADDIU: bits 010111 */
4339 sreg = b0s5_reg (insn);
4340 dreg = b5s5_reg (insn);
4342 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS,
4343 pc + MIPS_INSN16_SIZE, NULL);
4344 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
4345 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
4346 /* (D)ADDIU $sp, imm */
4351 case 0x10: /* POOL32I: bits 010000 */
4352 if (b5s5_op (insn) == 0xd
4353 /* LUI: bits 010000 001101 */
4354 && b0s5_reg (insn >> 16) == 28)
4359 case 0x13: /* POOL16D: bits 010011 */
4360 if ((insn & 0x1) == 0x1)
4361 /* ADDIUSP: bits 010011 1 */
4363 offset = micromips_decode_imm9 (b1s9_imm (insn));
4369 /* ADDIUS5: bits 010011 0 */
4371 dreg = b5s5_reg (insn);
4372 offset = (b1s4_imm (insn) ^ 8) - 8;
4373 if (dreg == MIPS_SP_REGNUM && offset < 0)
4374 /* ADDIUS5 $sp, -imm */
4382 else if (mips_about_to_return (gdbarch, start_pc))
4384 /* Skip return and its delay slot. */
4385 start_pc += 2 * MIPS_INSN32_SIZE;
4392 struct mips_objfile_private
4398 /* According to the current ABI, should the type be passed in a
4399 floating-point register (assuming that there is space)? When there
4400 is no FPU, FP are not even considered as possible candidates for
4401 FP registers and, consequently this returns false - forces FP
4402 arguments into integer registers. */
4405 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
4406 struct type *arg_type)
4408 return ((typecode == TYPE_CODE_FLT
4409 || (MIPS_EABI (gdbarch)
4410 && (typecode == TYPE_CODE_STRUCT
4411 || typecode == TYPE_CODE_UNION)
4412 && TYPE_NFIELDS (arg_type) == 1
4413 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
4415 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
4418 /* On o32, argument passing in GPRs depends on the alignment of the type being
4419 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4422 mips_type_needs_double_align (struct type *type)
4424 enum type_code typecode = TYPE_CODE (type);
4426 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
4428 else if (typecode == TYPE_CODE_STRUCT)
4430 if (TYPE_NFIELDS (type) < 1)
4432 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
4434 else if (typecode == TYPE_CODE_UNION)
4438 n = TYPE_NFIELDS (type);
4439 for (i = 0; i < n; i++)
4440 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
4447 /* Adjust the address downward (direction of stack growth) so that it
4448 is correctly aligned for a new stack frame. */
4450 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
4452 return align_down (addr, 16);
4455 /* Implement the "push_dummy_code" gdbarch method. */
4458 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
4459 CORE_ADDR funaddr, struct value **args,
4460 int nargs, struct type *value_type,
4461 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
4462 struct regcache *regcache)
4464 static gdb_byte nop_insn[] = { 0, 0, 0, 0 };
4468 /* Reserve enough room on the stack for our breakpoint instruction. */
4469 bp_slot = sp - sizeof (nop_insn);
4471 /* Return to microMIPS mode if calling microMIPS code to avoid
4472 triggering an address error exception on processors that only
4473 support microMIPS execution. */
4474 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr)
4475 ? make_compact_addr (bp_slot) : bp_slot);
4477 /* The breakpoint layer automatically adjusts the address of
4478 breakpoints inserted in a branch delay slot. With enough
4479 bad luck, the 4 bytes located just before our breakpoint
4480 instruction could look like a branch instruction, and thus
4481 trigger the adjustement, and break the function call entirely.
4482 So, we reserve those 4 bytes and write a nop instruction
4483 to prevent that from happening. */
4484 nop_addr = bp_slot - sizeof (nop_insn);
4485 write_memory (nop_addr, nop_insn, sizeof (nop_insn));
4486 sp = mips_frame_align (gdbarch, nop_addr);
4488 /* Inferior resumes at the function entry point. */
4495 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4496 struct regcache *regcache, CORE_ADDR bp_addr,
4497 int nargs, struct value **args, CORE_ADDR sp,
4498 int struct_return, CORE_ADDR struct_addr)
4504 int stack_offset = 0;
4505 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4506 CORE_ADDR func_addr = find_function_addr (function, NULL);
4507 int abi_regsize = mips_abi_regsize (gdbarch);
4509 /* For shared libraries, "t9" needs to point at the function
4511 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4513 /* Set the return address register to point to the entry point of
4514 the program, where a breakpoint lies in wait. */
4515 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4517 /* First ensure that the stack and structure return address (if any)
4518 are properly aligned. The stack has to be at least 64-bit
4519 aligned even on 32-bit machines, because doubles must be 64-bit
4520 aligned. For n32 and n64, stack frames need to be 128-bit
4521 aligned, so we round to this widest known alignment. */
4523 sp = align_down (sp, 16);
4524 struct_addr = align_down (struct_addr, 16);
4526 /* Now make space on the stack for the args. We allocate more
4527 than necessary for EABI, because the first few arguments are
4528 passed in registers, but that's OK. */
4529 for (argnum = 0; argnum < nargs; argnum++)
4530 arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), abi_regsize);
4531 sp -= align_up (arg_space, 16);
4534 fprintf_unfiltered (gdb_stdlog,
4535 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4536 paddress (gdbarch, sp),
4537 (long) align_up (arg_space, 16));
4539 /* Initialize the integer and float register pointers. */
4540 argreg = MIPS_A0_REGNUM;
4541 float_argreg = mips_fpa0_regnum (gdbarch);
4543 /* The struct_return pointer occupies the first parameter-passing reg. */
4547 fprintf_unfiltered (gdb_stdlog,
4548 "mips_eabi_push_dummy_call: "
4549 "struct_return reg=%d %s\n",
4550 argreg, paddress (gdbarch, struct_addr));
4551 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4554 /* Now load as many as possible of the first arguments into
4555 registers, and push the rest onto the stack. Loop thru args
4556 from first to last. */
4557 for (argnum = 0; argnum < nargs; argnum++)
4559 const gdb_byte *val;
4560 /* This holds the address of structures that are passed by
4562 gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE];
4563 struct value *arg = args[argnum];
4564 struct type *arg_type = check_typedef (value_type (arg));
4565 int len = TYPE_LENGTH (arg_type);
4566 enum type_code typecode = TYPE_CODE (arg_type);
4569 fprintf_unfiltered (gdb_stdlog,
4570 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4571 argnum + 1, len, (int) typecode);
4573 /* The EABI passes structures that do not fit in a register by
4575 if (len > abi_regsize
4576 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
4578 gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf));
4579 store_unsigned_integer (ref_valbuf, abi_regsize, byte_order,
4580 value_address (arg));
4581 typecode = TYPE_CODE_PTR;
4585 fprintf_unfiltered (gdb_stdlog, " push");
4588 val = value_contents (arg);
4590 /* 32-bit ABIs always start floating point arguments in an
4591 even-numbered floating point register. Round the FP register
4592 up before the check to see if there are any FP registers
4593 left. Non MIPS_EABI targets also pass the FP in the integer
4594 registers so also round up normal registers. */
4595 if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
4597 if ((float_argreg & 1))
4601 /* Floating point arguments passed in registers have to be
4602 treated specially. On 32-bit architectures, doubles
4603 are passed in register pairs; the even register gets
4604 the low word, and the odd register gets the high word.
4605 On non-EABI processors, the first two floating point arguments are
4606 also copied to general registers, because MIPS16 functions
4607 don't use float registers for arguments. This duplication of
4608 arguments in general registers can't hurt non-MIPS16 functions
4609 because those registers are normally skipped. */
4610 /* MIPS_EABI squeezes a struct that contains a single floating
4611 point value into an FP register instead of pushing it onto the
4613 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4614 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4616 /* EABI32 will pass doubles in consecutive registers, even on
4617 64-bit cores. At one time, we used to check the size of
4618 `float_argreg' to determine whether or not to pass doubles
4619 in consecutive registers, but this is not sufficient for
4620 making the ABI determination. */
4621 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
4623 int low_offset = gdbarch_byte_order (gdbarch)
4624 == BFD_ENDIAN_BIG ? 4 : 0;
4627 /* Write the low word of the double to the even register(s). */
4628 regval = extract_signed_integer (val + low_offset,
4631 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4632 float_argreg, phex (regval, 4));
4633 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4635 /* Write the high word of the double to the odd register(s). */
4636 regval = extract_signed_integer (val + 4 - low_offset,
4639 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4640 float_argreg, phex (regval, 4));
4641 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4645 /* This is a floating point value that fits entirely
4646 in a single register. */
4647 /* On 32 bit ABI's the float_argreg is further adjusted
4648 above to ensure that it is even register aligned. */
4649 LONGEST regval = extract_signed_integer (val, len, byte_order);
4651 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4652 float_argreg, phex (regval, len));
4653 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4658 /* Copy the argument to general registers or the stack in
4659 register-sized pieces. Large arguments are split between
4660 registers and stack. */
4661 /* Note: structs whose size is not a multiple of abi_regsize
4662 are treated specially: Irix cc passes
4663 them in registers where gcc sometimes puts them on the
4664 stack. For maximum compatibility, we will put them in
4666 int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0);
4668 /* Note: Floating-point values that didn't fit into an FP
4669 register are only written to memory. */
4672 /* Remember if the argument was written to the stack. */
4673 int stack_used_p = 0;
4674 int partial_len = (len < abi_regsize ? len : abi_regsize);
4677 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4680 /* Write this portion of the argument to the stack. */
4681 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4683 || fp_register_arg_p (gdbarch, typecode, arg_type))
4685 /* Should shorter than int integer values be
4686 promoted to int before being stored? */
4687 int longword_offset = 0;
4690 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4692 if (abi_regsize == 8
4693 && (typecode == TYPE_CODE_INT
4694 || typecode == TYPE_CODE_PTR
4695 || typecode == TYPE_CODE_FLT) && len <= 4)
4696 longword_offset = abi_regsize - len;
4697 else if ((typecode == TYPE_CODE_STRUCT
4698 || typecode == TYPE_CODE_UNION)
4699 && TYPE_LENGTH (arg_type) < abi_regsize)
4700 longword_offset = abi_regsize - len;
4705 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4706 paddress (gdbarch, stack_offset));
4707 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4708 paddress (gdbarch, longword_offset));
4711 addr = sp + stack_offset + longword_offset;
4716 fprintf_unfiltered (gdb_stdlog, " @%s ",
4717 paddress (gdbarch, addr));
4718 for (i = 0; i < partial_len; i++)
4720 fprintf_unfiltered (gdb_stdlog, "%02x",
4724 write_memory (addr, val, partial_len);
4727 /* Note!!! This is NOT an else clause. Odd sized
4728 structs may go thru BOTH paths. Floating point
4729 arguments will not. */
4730 /* Write this portion of the argument to a general
4731 purpose register. */
4732 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
4733 && !fp_register_arg_p (gdbarch, typecode, arg_type))
4736 extract_signed_integer (val, partial_len, byte_order);
4739 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4741 phex (regval, abi_regsize));
4742 regcache_cooked_write_signed (regcache, argreg, regval);
4749 /* Compute the offset into the stack at which we will
4750 copy the next parameter.
4752 In the new EABI (and the NABI32), the stack_offset
4753 only needs to be adjusted when it has been used. */
4756 stack_offset += align_up (partial_len, abi_regsize);
4760 fprintf_unfiltered (gdb_stdlog, "\n");
4763 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4765 /* Return adjusted stack pointer. */
4769 /* Determine the return value convention being used. */
4771 static enum return_value_convention
4772 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function,
4773 struct type *type, struct regcache *regcache,
4774 gdb_byte *readbuf, const gdb_byte *writebuf)
4776 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4777 int fp_return_type = 0;
4778 int offset, regnum, xfer;
4780 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
4781 return RETURN_VALUE_STRUCT_CONVENTION;
4783 /* Floating point type? */
4784 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
4786 if (TYPE_CODE (type) == TYPE_CODE_FLT)
4788 /* Structs with a single field of float type
4789 are returned in a floating point register. */
4790 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
4791 || TYPE_CODE (type) == TYPE_CODE_UNION)
4792 && TYPE_NFIELDS (type) == 1)
4794 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
4796 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
4803 /* A floating-point value belongs in the least significant part
4806 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4807 regnum = mips_regnum (gdbarch)->fp0;
4811 /* An integer value goes in V0/V1. */
4813 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
4814 regnum = MIPS_V0_REGNUM;
4817 offset < TYPE_LENGTH (type);
4818 offset += mips_abi_regsize (gdbarch), regnum++)
4820 xfer = mips_abi_regsize (gdbarch);
4821 if (offset + xfer > TYPE_LENGTH (type))
4822 xfer = TYPE_LENGTH (type) - offset;
4823 mips_xfer_register (gdbarch, regcache,
4824 gdbarch_num_regs (gdbarch) + regnum, xfer,
4825 gdbarch_byte_order (gdbarch), readbuf, writebuf,
4829 return RETURN_VALUE_REGISTER_CONVENTION;
4833 /* N32/N64 ABI stuff. */
4835 /* Search for a naturally aligned double at OFFSET inside a struct
4836 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4840 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
4845 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
4848 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
4851 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
4854 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
4857 struct type *field_type;
4859 /* We're only looking at normal fields. */
4860 if (field_is_static (&TYPE_FIELD (arg_type, i))
4861 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
4864 /* If we have gone past the offset, there is no double to pass. */
4865 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
4869 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
4871 /* If this field is entirely before the requested offset, go
4872 on to the next one. */
4873 if (pos + TYPE_LENGTH (field_type) <= offset)
4876 /* If this is our special aligned double, we can stop. */
4877 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
4878 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
4881 /* This field starts at or before the requested offset, and
4882 overlaps it. If it is a structure, recurse inwards. */
4883 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
4890 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4891 struct regcache *regcache, CORE_ADDR bp_addr,
4892 int nargs, struct value **args, CORE_ADDR sp,
4893 int struct_return, CORE_ADDR struct_addr)
4899 int stack_offset = 0;
4900 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4901 CORE_ADDR func_addr = find_function_addr (function, NULL);
4903 /* For shared libraries, "t9" needs to point at the function
4905 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4907 /* Set the return address register to point to the entry point of
4908 the program, where a breakpoint lies in wait. */
4909 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4911 /* First ensure that the stack and structure return address (if any)
4912 are properly aligned. The stack has to be at least 64-bit
4913 aligned even on 32-bit machines, because doubles must be 64-bit
4914 aligned. For n32 and n64, stack frames need to be 128-bit
4915 aligned, so we round to this widest known alignment. */
4917 sp = align_down (sp, 16);
4918 struct_addr = align_down (struct_addr, 16);
4920 /* Now make space on the stack for the args. */
4921 for (argnum = 0; argnum < nargs; argnum++)
4922 arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
4923 sp -= align_up (arg_space, 16);
4926 fprintf_unfiltered (gdb_stdlog,
4927 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4928 paddress (gdbarch, sp),
4929 (long) align_up (arg_space, 16));
4931 /* Initialize the integer and float register pointers. */
4932 argreg = MIPS_A0_REGNUM;
4933 float_argreg = mips_fpa0_regnum (gdbarch);
4935 /* The struct_return pointer occupies the first parameter-passing reg. */
4939 fprintf_unfiltered (gdb_stdlog,
4940 "mips_n32n64_push_dummy_call: "
4941 "struct_return reg=%d %s\n",
4942 argreg, paddress (gdbarch, struct_addr));
4943 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4946 /* Now load as many as possible of the first arguments into
4947 registers, and push the rest onto the stack. Loop thru args
4948 from first to last. */
4949 for (argnum = 0; argnum < nargs; argnum++)
4951 const gdb_byte *val;
4952 struct value *arg = args[argnum];
4953 struct type *arg_type = check_typedef (value_type (arg));
4954 int len = TYPE_LENGTH (arg_type);
4955 enum type_code typecode = TYPE_CODE (arg_type);
4958 fprintf_unfiltered (gdb_stdlog,
4959 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4960 argnum + 1, len, (int) typecode);
4962 val = value_contents (arg);
4964 /* A 128-bit long double value requires an even-odd pair of
4965 floating-point registers. */
4967 && fp_register_arg_p (gdbarch, typecode, arg_type)
4968 && (float_argreg & 1))
4974 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4975 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4977 /* This is a floating point value that fits entirely
4978 in a single register or a pair of registers. */
4979 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4980 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
4982 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4983 float_argreg, phex (regval, reglen));
4984 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4987 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4988 argreg, phex (regval, reglen));
4989 regcache_cooked_write_unsigned (regcache, argreg, regval);
4994 regval = extract_unsigned_integer (val + reglen,
4995 reglen, byte_order);
4997 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4998 float_argreg, phex (regval, reglen));
4999 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
5002 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5003 argreg, phex (regval, reglen));
5004 regcache_cooked_write_unsigned (regcache, argreg, regval);
5011 /* Copy the argument to general registers or the stack in
5012 register-sized pieces. Large arguments are split between
5013 registers and stack. */
5014 /* For N32/N64, structs, unions, or other composite types are
5015 treated as a sequence of doublewords, and are passed in integer
5016 or floating point registers as though they were simple scalar
5017 parameters to the extent that they fit, with any excess on the
5018 stack packed according to the normal memory layout of the
5020 The caller does not reserve space for the register arguments;
5021 the callee is responsible for reserving it if required. */
5022 /* Note: Floating-point values that didn't fit into an FP
5023 register are only written to memory. */
5026 /* Remember if the argument was written to the stack. */
5027 int stack_used_p = 0;
5028 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
5031 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5034 if (fp_register_arg_p (gdbarch, typecode, arg_type))
5035 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
5037 /* Write this portion of the argument to the stack. */
5038 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
5040 /* Should shorter than int integer values be
5041 promoted to int before being stored? */
5042 int longword_offset = 0;
5045 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5047 if ((typecode == TYPE_CODE_INT
5048 || typecode == TYPE_CODE_PTR)
5050 longword_offset = MIPS64_REGSIZE - len;
5055 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5056 paddress (gdbarch, stack_offset));
5057 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5058 paddress (gdbarch, longword_offset));
5061 addr = sp + stack_offset + longword_offset;
5066 fprintf_unfiltered (gdb_stdlog, " @%s ",
5067 paddress (gdbarch, addr));
5068 for (i = 0; i < partial_len; i++)
5070 fprintf_unfiltered (gdb_stdlog, "%02x",
5074 write_memory (addr, val, partial_len);
5077 /* Note!!! This is NOT an else clause. Odd sized
5078 structs may go thru BOTH paths. */
5079 /* Write this portion of the argument to a general
5080 purpose register. */
5081 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5085 /* Sign extend pointers, 32-bit integers and signed
5086 16-bit and 8-bit integers; everything else is taken
5089 if ((partial_len == 4
5090 && (typecode == TYPE_CODE_PTR
5091 || typecode == TYPE_CODE_INT))
5093 && typecode == TYPE_CODE_INT
5094 && !TYPE_UNSIGNED (arg_type)))
5095 regval = extract_signed_integer (val, partial_len,
5098 regval = extract_unsigned_integer (val, partial_len,
5101 /* A non-floating-point argument being passed in a
5102 general register. If a struct or union, and if
5103 the remaining length is smaller than the register
5104 size, we have to adjust the register value on
5107 It does not seem to be necessary to do the
5108 same for integral types. */
5110 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5111 && partial_len < MIPS64_REGSIZE
5112 && (typecode == TYPE_CODE_STRUCT
5113 || typecode == TYPE_CODE_UNION))
5114 regval <<= ((MIPS64_REGSIZE - partial_len)
5118 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5120 phex (regval, MIPS64_REGSIZE));
5121 regcache_cooked_write_unsigned (regcache, argreg, regval);
5123 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
5124 TYPE_LENGTH (arg_type) - len))
5127 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
5129 phex (regval, MIPS64_REGSIZE));
5130 regcache_cooked_write_unsigned (regcache, float_argreg,
5141 /* Compute the offset into the stack at which we will
5142 copy the next parameter.
5144 In N32 (N64?), the stack_offset only needs to be
5145 adjusted when it has been used. */
5148 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
5152 fprintf_unfiltered (gdb_stdlog, "\n");
5155 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5157 /* Return adjusted stack pointer. */
5161 static enum return_value_convention
5162 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function,
5163 struct type *type, struct regcache *regcache,
5164 gdb_byte *readbuf, const gdb_byte *writebuf)
5166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5168 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5170 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5171 if needed), as appropriate for the type. Composite results (struct,
5172 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5175 * A struct with only one or two floating point fields is returned in $f0
5176 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5179 * Any other composite results of at most 128 bits are returned in
5180 $2 (first 64 bits) and $3 (remainder, if necessary).
5182 * Larger composite results are handled by converting the function to a
5183 procedure with an implicit first parameter, which is a pointer to an area
5184 reserved by the caller to receive the result. [The o32-bit ABI requires
5185 that all composite results be handled by conversion to implicit first
5186 parameters. The MIPS/SGI Fortran implementation has always made a
5187 specific exception to return COMPLEX results in the floating point
5190 if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
5191 return RETURN_VALUE_STRUCT_CONVENTION;
5192 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5193 && TYPE_LENGTH (type) == 16
5194 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5196 /* A 128-bit floating-point value fills both $f0 and $f2. The
5197 two registers are used in the same as memory order, so the
5198 eight bytes with the lower memory address are in $f0. */
5200 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
5201 mips_xfer_register (gdbarch, regcache,
5202 (gdbarch_num_regs (gdbarch)
5203 + mips_regnum (gdbarch)->fp0),
5204 8, gdbarch_byte_order (gdbarch),
5205 readbuf, writebuf, 0);
5206 mips_xfer_register (gdbarch, regcache,
5207 (gdbarch_num_regs (gdbarch)
5208 + mips_regnum (gdbarch)->fp0 + 2),
5209 8, gdbarch_byte_order (gdbarch),
5210 readbuf ? readbuf + 8 : readbuf,
5211 writebuf ? writebuf + 8 : writebuf, 0);
5212 return RETURN_VALUE_REGISTER_CONVENTION;
5214 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5215 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5217 /* A single or double floating-point value that fits in FP0. */
5219 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5220 mips_xfer_register (gdbarch, regcache,
5221 (gdbarch_num_regs (gdbarch)
5222 + mips_regnum (gdbarch)->fp0),
5224 gdbarch_byte_order (gdbarch),
5225 readbuf, writebuf, 0);
5226 return RETURN_VALUE_REGISTER_CONVENTION;
5228 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5229 && TYPE_NFIELDS (type) <= 2
5230 && TYPE_NFIELDS (type) >= 1
5231 && ((TYPE_NFIELDS (type) == 1
5232 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5234 || (TYPE_NFIELDS (type) == 2
5235 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5237 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
5238 == TYPE_CODE_FLT))))
5240 /* A struct that contains one or two floats. Each value is part
5241 in the least significant part of their floating point
5242 register (or GPR, for soft float). */
5245 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
5246 ? mips_regnum (gdbarch)->fp0
5248 field < TYPE_NFIELDS (type); field++, regnum += 2)
5250 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5253 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5255 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
5257 /* A 16-byte long double field goes in two consecutive
5259 mips_xfer_register (gdbarch, regcache,
5260 gdbarch_num_regs (gdbarch) + regnum,
5262 gdbarch_byte_order (gdbarch),
5263 readbuf, writebuf, offset);
5264 mips_xfer_register (gdbarch, regcache,
5265 gdbarch_num_regs (gdbarch) + regnum + 1,
5267 gdbarch_byte_order (gdbarch),
5268 readbuf, writebuf, offset + 8);
5271 mips_xfer_register (gdbarch, regcache,
5272 gdbarch_num_regs (gdbarch) + regnum,
5273 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5274 gdbarch_byte_order (gdbarch),
5275 readbuf, writebuf, offset);
5277 return RETURN_VALUE_REGISTER_CONVENTION;
5279 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5280 || TYPE_CODE (type) == TYPE_CODE_UNION
5281 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5283 /* A composite type. Extract the left justified value,
5284 regardless of the byte order. I.e. DO NOT USE
5288 for (offset = 0, regnum = MIPS_V0_REGNUM;
5289 offset < TYPE_LENGTH (type);
5290 offset += register_size (gdbarch, regnum), regnum++)
5292 int xfer = register_size (gdbarch, regnum);
5293 if (offset + xfer > TYPE_LENGTH (type))
5294 xfer = TYPE_LENGTH (type) - offset;
5296 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5297 offset, xfer, regnum);
5298 mips_xfer_register (gdbarch, regcache,
5299 gdbarch_num_regs (gdbarch) + regnum,
5300 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
5303 return RETURN_VALUE_REGISTER_CONVENTION;
5307 /* A scalar extract each part but least-significant-byte
5311 for (offset = 0, regnum = MIPS_V0_REGNUM;
5312 offset < TYPE_LENGTH (type);
5313 offset += register_size (gdbarch, regnum), regnum++)
5315 int xfer = register_size (gdbarch, regnum);
5316 if (offset + xfer > TYPE_LENGTH (type))
5317 xfer = TYPE_LENGTH (type) - offset;
5319 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5320 offset, xfer, regnum);
5321 mips_xfer_register (gdbarch, regcache,
5322 gdbarch_num_regs (gdbarch) + regnum,
5323 xfer, gdbarch_byte_order (gdbarch),
5324 readbuf, writebuf, offset);
5326 return RETURN_VALUE_REGISTER_CONVENTION;
5330 /* Which registers to use for passing floating-point values between
5331 function calls, one of floating-point, general and both kinds of
5332 registers. O32 and O64 use different register kinds for standard
5333 MIPS and MIPS16 code; to make the handling of cases where we may
5334 not know what kind of code is being used (e.g. no debug information)
5335 easier we sometimes use both kinds. */
5344 /* O32 ABI stuff. */
5347 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5348 struct regcache *regcache, CORE_ADDR bp_addr,
5349 int nargs, struct value **args, CORE_ADDR sp,
5350 int struct_return, CORE_ADDR struct_addr)
5356 int stack_offset = 0;
5357 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5358 CORE_ADDR func_addr = find_function_addr (function, NULL);
5360 /* For shared libraries, "t9" needs to point at the function
5362 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5364 /* Set the return address register to point to the entry point of
5365 the program, where a breakpoint lies in wait. */
5366 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5368 /* First ensure that the stack and structure return address (if any)
5369 are properly aligned. The stack has to be at least 64-bit
5370 aligned even on 32-bit machines, because doubles must be 64-bit
5371 aligned. For n32 and n64, stack frames need to be 128-bit
5372 aligned, so we round to this widest known alignment. */
5374 sp = align_down (sp, 16);
5375 struct_addr = align_down (struct_addr, 16);
5377 /* Now make space on the stack for the args. */
5378 for (argnum = 0; argnum < nargs; argnum++)
5380 struct type *arg_type = check_typedef (value_type (args[argnum]));
5382 /* Align to double-word if necessary. */
5383 if (mips_type_needs_double_align (arg_type))
5384 arg_space = align_up (arg_space, MIPS32_REGSIZE * 2);
5385 /* Allocate space on the stack. */
5386 arg_space += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE);
5388 sp -= align_up (arg_space, 16);
5391 fprintf_unfiltered (gdb_stdlog,
5392 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5393 paddress (gdbarch, sp),
5394 (long) align_up (arg_space, 16));
5396 /* Initialize the integer and float register pointers. */
5397 argreg = MIPS_A0_REGNUM;
5398 float_argreg = mips_fpa0_regnum (gdbarch);
5400 /* The struct_return pointer occupies the first parameter-passing reg. */
5404 fprintf_unfiltered (gdb_stdlog,
5405 "mips_o32_push_dummy_call: "
5406 "struct_return reg=%d %s\n",
5407 argreg, paddress (gdbarch, struct_addr));
5408 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5409 stack_offset += MIPS32_REGSIZE;
5412 /* Now load as many as possible of the first arguments into
5413 registers, and push the rest onto the stack. Loop thru args
5414 from first to last. */
5415 for (argnum = 0; argnum < nargs; argnum++)
5417 const gdb_byte *val;
5418 struct value *arg = args[argnum];
5419 struct type *arg_type = check_typedef (value_type (arg));
5420 int len = TYPE_LENGTH (arg_type);
5421 enum type_code typecode = TYPE_CODE (arg_type);
5424 fprintf_unfiltered (gdb_stdlog,
5425 "mips_o32_push_dummy_call: %d len=%d type=%d",
5426 argnum + 1, len, (int) typecode);
5428 val = value_contents (arg);
5430 /* 32-bit ABIs always start floating point arguments in an
5431 even-numbered floating point register. Round the FP register
5432 up before the check to see if there are any FP registers
5433 left. O32 targets also pass the FP in the integer registers
5434 so also round up normal registers. */
5435 if (fp_register_arg_p (gdbarch, typecode, arg_type))
5437 if ((float_argreg & 1))
5441 /* Floating point arguments passed in registers have to be
5442 treated specially. On 32-bit architectures, doubles are
5443 passed in register pairs; the even FP register gets the
5444 low word, and the odd FP register gets the high word.
5445 On O32, the first two floating point arguments are also
5446 copied to general registers, following their memory order,
5447 because MIPS16 functions don't use float registers for
5448 arguments. This duplication of arguments in general
5449 registers can't hurt non-MIPS16 functions, because those
5450 registers are normally skipped. */
5452 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5453 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5455 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
5457 int freg_offset = gdbarch_byte_order (gdbarch)
5458 == BFD_ENDIAN_BIG ? 1 : 0;
5459 unsigned long regval;
5462 regval = extract_unsigned_integer (val, 4, byte_order);
5464 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5465 float_argreg + freg_offset,
5467 regcache_cooked_write_unsigned (regcache,
5468 float_argreg++ + freg_offset,
5471 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5472 argreg, phex (regval, 4));
5473 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5476 regval = extract_unsigned_integer (val + 4, 4, byte_order);
5478 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5479 float_argreg - freg_offset,
5481 regcache_cooked_write_unsigned (regcache,
5482 float_argreg++ - freg_offset,
5485 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5486 argreg, phex (regval, 4));
5487 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5491 /* This is a floating point value that fits entirely
5492 in a single register. */
5493 /* On 32 bit ABI's the float_argreg is further adjusted
5494 above to ensure that it is even register aligned. */
5495 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5497 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5498 float_argreg, phex (regval, len));
5499 regcache_cooked_write_unsigned (regcache,
5500 float_argreg++, regval);
5501 /* Although two FP registers are reserved for each
5502 argument, only one corresponding integer register is
5505 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5506 argreg, phex (regval, len));
5507 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5509 /* Reserve space for the FP register. */
5510 stack_offset += align_up (len, MIPS32_REGSIZE);
5514 /* Copy the argument to general registers or the stack in
5515 register-sized pieces. Large arguments are split between
5516 registers and stack. */
5517 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5518 are treated specially: Irix cc passes
5519 them in registers where gcc sometimes puts them on the
5520 stack. For maximum compatibility, we will put them in
5522 int odd_sized_struct = (len > MIPS32_REGSIZE
5523 && len % MIPS32_REGSIZE != 0);
5524 /* Structures should be aligned to eight bytes (even arg registers)
5525 on MIPS_ABI_O32, if their first member has double precision. */
5526 if (mips_type_needs_double_align (arg_type))
5531 stack_offset += MIPS32_REGSIZE;
5536 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
5539 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5542 /* Write this portion of the argument to the stack. */
5543 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5544 || odd_sized_struct)
5546 /* Should shorter than int integer values be
5547 promoted to int before being stored? */
5548 int longword_offset = 0;
5553 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5554 paddress (gdbarch, stack_offset));
5555 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5556 paddress (gdbarch, longword_offset));
5559 addr = sp + stack_offset + longword_offset;
5564 fprintf_unfiltered (gdb_stdlog, " @%s ",
5565 paddress (gdbarch, addr));
5566 for (i = 0; i < partial_len; i++)
5568 fprintf_unfiltered (gdb_stdlog, "%02x",
5572 write_memory (addr, val, partial_len);
5575 /* Note!!! This is NOT an else clause. Odd sized
5576 structs may go thru BOTH paths. */
5577 /* Write this portion of the argument to a general
5578 purpose register. */
5579 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5581 LONGEST regval = extract_signed_integer (val, partial_len,
5583 /* Value may need to be sign extended, because
5584 mips_isa_regsize() != mips_abi_regsize(). */
5586 /* A non-floating-point argument being passed in a
5587 general register. If a struct or union, and if
5588 the remaining length is smaller than the register
5589 size, we have to adjust the register value on
5592 It does not seem to be necessary to do the
5593 same for integral types.
5595 Also don't do this adjustment on O64 binaries.
5597 cagney/2001-07-23: gdb/179: Also, GCC, when
5598 outputting LE O32 with sizeof (struct) <
5599 mips_abi_regsize(), generates a left shift
5600 as part of storing the argument in a register
5601 (the left shift isn't generated when
5602 sizeof (struct) >= mips_abi_regsize()). Since
5603 it is quite possible that this is GCC
5604 contradicting the LE/O32 ABI, GDB has not been
5605 adjusted to accommodate this. Either someone
5606 needs to demonstrate that the LE/O32 ABI
5607 specifies such a left shift OR this new ABI gets
5608 identified as such and GDB gets tweaked
5611 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5612 && partial_len < MIPS32_REGSIZE
5613 && (typecode == TYPE_CODE_STRUCT
5614 || typecode == TYPE_CODE_UNION))
5615 regval <<= ((MIPS32_REGSIZE - partial_len)
5619 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5621 phex (regval, MIPS32_REGSIZE));
5622 regcache_cooked_write_unsigned (regcache, argreg, regval);
5625 /* Prevent subsequent floating point arguments from
5626 being passed in floating point registers. */
5627 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
5633 /* Compute the offset into the stack at which we will
5634 copy the next parameter.
5636 In older ABIs, the caller reserved space for
5637 registers that contained arguments. This was loosely
5638 refered to as their "home". Consequently, space is
5639 always allocated. */
5641 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
5645 fprintf_unfiltered (gdb_stdlog, "\n");
5648 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5650 /* Return adjusted stack pointer. */
5654 static enum return_value_convention
5655 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function,
5656 struct type *type, struct regcache *regcache,
5657 gdb_byte *readbuf, const gdb_byte *writebuf)
5659 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
5660 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
5661 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5662 enum mips_fval_reg fval_reg;
5664 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
5665 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5666 || TYPE_CODE (type) == TYPE_CODE_UNION
5667 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5668 return RETURN_VALUE_STRUCT_CONVENTION;
5669 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5670 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5672 /* A single-precision floating-point value. If reading in or copying,
5673 then we get it from/put it to FP0 for standard MIPS code or GPR2
5674 for MIPS16 code. If writing out only, then we put it to both FP0
5675 and GPR2. We do not support reading in with no function known, if
5676 this safety check ever triggers, then we'll have to try harder. */
5677 gdb_assert (function || !readbuf);
5682 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5685 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
5687 case mips_fval_both:
5688 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
5691 if (fval_reg != mips_fval_gpr)
5692 mips_xfer_register (gdbarch, regcache,
5693 (gdbarch_num_regs (gdbarch)
5694 + mips_regnum (gdbarch)->fp0),
5696 gdbarch_byte_order (gdbarch),
5697 readbuf, writebuf, 0);
5698 if (fval_reg != mips_fval_fpr)
5699 mips_xfer_register (gdbarch, regcache,
5700 gdbarch_num_regs (gdbarch) + 2,
5702 gdbarch_byte_order (gdbarch),
5703 readbuf, writebuf, 0);
5704 return RETURN_VALUE_REGISTER_CONVENTION;
5706 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5707 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5709 /* A double-precision floating-point value. If reading in or copying,
5710 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5711 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5712 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5713 no function known, if this safety check ever triggers, then we'll
5714 have to try harder. */
5715 gdb_assert (function || !readbuf);
5720 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
5723 fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n");
5725 case mips_fval_both:
5726 fprintf_unfiltered (gdb_stderr,
5727 "Return float in $fp1/$fp0 and $2/$3\n");
5730 if (fval_reg != mips_fval_gpr)
5732 /* The most significant part goes in FP1, and the least significant
5734 switch (gdbarch_byte_order (gdbarch))
5736 case BFD_ENDIAN_LITTLE:
5737 mips_xfer_register (gdbarch, regcache,
5738 (gdbarch_num_regs (gdbarch)
5739 + mips_regnum (gdbarch)->fp0 + 0),
5740 4, gdbarch_byte_order (gdbarch),
5741 readbuf, writebuf, 0);
5742 mips_xfer_register (gdbarch, regcache,
5743 (gdbarch_num_regs (gdbarch)
5744 + mips_regnum (gdbarch)->fp0 + 1),
5745 4, gdbarch_byte_order (gdbarch),
5746 readbuf, writebuf, 4);
5748 case BFD_ENDIAN_BIG:
5749 mips_xfer_register (gdbarch, regcache,
5750 (gdbarch_num_regs (gdbarch)
5751 + mips_regnum (gdbarch)->fp0 + 1),
5752 4, gdbarch_byte_order (gdbarch),
5753 readbuf, writebuf, 0);
5754 mips_xfer_register (gdbarch, regcache,
5755 (gdbarch_num_regs (gdbarch)
5756 + mips_regnum (gdbarch)->fp0 + 0),
5757 4, gdbarch_byte_order (gdbarch),
5758 readbuf, writebuf, 4);
5761 internal_error (__FILE__, __LINE__, _("bad switch"));
5764 if (fval_reg != mips_fval_fpr)
5766 /* The two 32-bit parts are always placed in GPR2 and GPR3
5767 following these registers' memory order. */
5768 mips_xfer_register (gdbarch, regcache,
5769 gdbarch_num_regs (gdbarch) + 2,
5770 4, gdbarch_byte_order (gdbarch),
5771 readbuf, writebuf, 0);
5772 mips_xfer_register (gdbarch, regcache,
5773 gdbarch_num_regs (gdbarch) + 3,
5774 4, gdbarch_byte_order (gdbarch),
5775 readbuf, writebuf, 4);
5777 return RETURN_VALUE_REGISTER_CONVENTION;
5780 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5781 && TYPE_NFIELDS (type) <= 2
5782 && TYPE_NFIELDS (type) >= 1
5783 && ((TYPE_NFIELDS (type) == 1
5784 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5786 || (TYPE_NFIELDS (type) == 2
5787 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5789 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
5791 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5793 /* A struct that contains one or two floats. Each value is part
5794 in the least significant part of their floating point
5798 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
5799 field < TYPE_NFIELDS (type); field++, regnum += 2)
5801 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5804 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5806 mips_xfer_register (gdbarch, regcache,
5807 gdbarch_num_regs (gdbarch) + regnum,
5808 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5809 gdbarch_byte_order (gdbarch),
5810 readbuf, writebuf, offset);
5812 return RETURN_VALUE_REGISTER_CONVENTION;
5816 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5817 || TYPE_CODE (type) == TYPE_CODE_UNION)
5819 /* A structure or union. Extract the left justified value,
5820 regardless of the byte order. I.e. DO NOT USE
5824 for (offset = 0, regnum = MIPS_V0_REGNUM;
5825 offset < TYPE_LENGTH (type);
5826 offset += register_size (gdbarch, regnum), regnum++)
5828 int xfer = register_size (gdbarch, regnum);
5829 if (offset + xfer > TYPE_LENGTH (type))
5830 xfer = TYPE_LENGTH (type) - offset;
5832 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5833 offset, xfer, regnum);
5834 mips_xfer_register (gdbarch, regcache,
5835 gdbarch_num_regs (gdbarch) + regnum, xfer,
5836 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
5838 return RETURN_VALUE_REGISTER_CONVENTION;
5843 /* A scalar extract each part but least-significant-byte
5844 justified. o32 thinks registers are 4 byte, regardless of
5848 for (offset = 0, regnum = MIPS_V0_REGNUM;
5849 offset < TYPE_LENGTH (type);
5850 offset += MIPS32_REGSIZE, regnum++)
5852 int xfer = MIPS32_REGSIZE;
5853 if (offset + xfer > TYPE_LENGTH (type))
5854 xfer = TYPE_LENGTH (type) - offset;
5856 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5857 offset, xfer, regnum);
5858 mips_xfer_register (gdbarch, regcache,
5859 gdbarch_num_regs (gdbarch) + regnum, xfer,
5860 gdbarch_byte_order (gdbarch),
5861 readbuf, writebuf, offset);
5863 return RETURN_VALUE_REGISTER_CONVENTION;
5867 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5871 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5872 struct regcache *regcache, CORE_ADDR bp_addr,
5874 struct value **args, CORE_ADDR sp,
5875 int struct_return, CORE_ADDR struct_addr)
5881 int stack_offset = 0;
5882 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5883 CORE_ADDR func_addr = find_function_addr (function, NULL);
5885 /* For shared libraries, "t9" needs to point at the function
5887 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5889 /* Set the return address register to point to the entry point of
5890 the program, where a breakpoint lies in wait. */
5891 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5893 /* First ensure that the stack and structure return address (if any)
5894 are properly aligned. The stack has to be at least 64-bit
5895 aligned even on 32-bit machines, because doubles must be 64-bit
5896 aligned. For n32 and n64, stack frames need to be 128-bit
5897 aligned, so we round to this widest known alignment. */
5899 sp = align_down (sp, 16);
5900 struct_addr = align_down (struct_addr, 16);
5902 /* Now make space on the stack for the args. */
5903 for (argnum = 0; argnum < nargs; argnum++)
5905 struct type *arg_type = check_typedef (value_type (args[argnum]));
5907 /* Allocate space on the stack. */
5908 arg_space += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE);
5910 sp -= align_up (arg_space, 16);
5913 fprintf_unfiltered (gdb_stdlog,
5914 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5915 paddress (gdbarch, sp),
5916 (long) align_up (arg_space, 16));
5918 /* Initialize the integer and float register pointers. */
5919 argreg = MIPS_A0_REGNUM;
5920 float_argreg = mips_fpa0_regnum (gdbarch);
5922 /* The struct_return pointer occupies the first parameter-passing reg. */
5926 fprintf_unfiltered (gdb_stdlog,
5927 "mips_o64_push_dummy_call: "
5928 "struct_return reg=%d %s\n",
5929 argreg, paddress (gdbarch, struct_addr));
5930 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5931 stack_offset += MIPS64_REGSIZE;
5934 /* Now load as many as possible of the first arguments into
5935 registers, and push the rest onto the stack. Loop thru args
5936 from first to last. */
5937 for (argnum = 0; argnum < nargs; argnum++)
5939 const gdb_byte *val;
5940 struct value *arg = args[argnum];
5941 struct type *arg_type = check_typedef (value_type (arg));
5942 int len = TYPE_LENGTH (arg_type);
5943 enum type_code typecode = TYPE_CODE (arg_type);
5946 fprintf_unfiltered (gdb_stdlog,
5947 "mips_o64_push_dummy_call: %d len=%d type=%d",
5948 argnum + 1, len, (int) typecode);
5950 val = value_contents (arg);
5952 /* Floating point arguments passed in registers have to be
5953 treated specially. On 32-bit architectures, doubles are
5954 passed in register pairs; the even FP register gets the
5955 low word, and the odd FP register gets the high word.
5956 On O64, the first two floating point arguments are also
5957 copied to general registers, because MIPS16 functions
5958 don't use float registers for arguments. This duplication
5959 of arguments in general registers can't hurt non-MIPS16
5960 functions because those registers are normally skipped. */
5962 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5963 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5965 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5967 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5968 float_argreg, phex (regval, len));
5969 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
5971 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5972 argreg, phex (regval, len));
5973 regcache_cooked_write_unsigned (regcache, argreg, regval);
5975 /* Reserve space for the FP register. */
5976 stack_offset += align_up (len, MIPS64_REGSIZE);
5980 /* Copy the argument to general registers or the stack in
5981 register-sized pieces. Large arguments are split between
5982 registers and stack. */
5983 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5984 are treated specially: Irix cc passes them in registers
5985 where gcc sometimes puts them on the stack. For maximum
5986 compatibility, we will put them in both places. */
5987 int odd_sized_struct = (len > MIPS64_REGSIZE
5988 && len % MIPS64_REGSIZE != 0);
5991 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
5994 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5997 /* Write this portion of the argument to the stack. */
5998 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5999 || odd_sized_struct)
6001 /* Should shorter than int integer values be
6002 promoted to int before being stored? */
6003 int longword_offset = 0;
6005 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6007 if ((typecode == TYPE_CODE_INT
6008 || typecode == TYPE_CODE_PTR
6009 || typecode == TYPE_CODE_FLT)
6011 longword_offset = MIPS64_REGSIZE - len;
6016 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
6017 paddress (gdbarch, stack_offset));
6018 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
6019 paddress (gdbarch, longword_offset));
6022 addr = sp + stack_offset + longword_offset;
6027 fprintf_unfiltered (gdb_stdlog, " @%s ",
6028 paddress (gdbarch, addr));
6029 for (i = 0; i < partial_len; i++)
6031 fprintf_unfiltered (gdb_stdlog, "%02x",
6035 write_memory (addr, val, partial_len);
6038 /* Note!!! This is NOT an else clause. Odd sized
6039 structs may go thru BOTH paths. */
6040 /* Write this portion of the argument to a general
6041 purpose register. */
6042 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
6044 LONGEST regval = extract_signed_integer (val, partial_len,
6046 /* Value may need to be sign extended, because
6047 mips_isa_regsize() != mips_abi_regsize(). */
6049 /* A non-floating-point argument being passed in a
6050 general register. If a struct or union, and if
6051 the remaining length is smaller than the register
6052 size, we have to adjust the register value on
6055 It does not seem to be necessary to do the
6056 same for integral types. */
6058 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
6059 && partial_len < MIPS64_REGSIZE
6060 && (typecode == TYPE_CODE_STRUCT
6061 || typecode == TYPE_CODE_UNION))
6062 regval <<= ((MIPS64_REGSIZE - partial_len)
6066 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
6068 phex (regval, MIPS64_REGSIZE));
6069 regcache_cooked_write_unsigned (regcache, argreg, regval);
6072 /* Prevent subsequent floating point arguments from
6073 being passed in floating point registers. */
6074 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
6080 /* Compute the offset into the stack at which we will
6081 copy the next parameter.
6083 In older ABIs, the caller reserved space for
6084 registers that contained arguments. This was loosely
6085 refered to as their "home". Consequently, space is
6086 always allocated. */
6088 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
6092 fprintf_unfiltered (gdb_stdlog, "\n");
6095 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
6097 /* Return adjusted stack pointer. */
6101 static enum return_value_convention
6102 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function,
6103 struct type *type, struct regcache *regcache,
6104 gdb_byte *readbuf, const gdb_byte *writebuf)
6106 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
6107 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
6108 enum mips_fval_reg fval_reg;
6110 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
6111 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
6112 || TYPE_CODE (type) == TYPE_CODE_UNION
6113 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
6114 return RETURN_VALUE_STRUCT_CONVENTION;
6115 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
6117 /* A floating-point value. If reading in or copying, then we get it
6118 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6119 If writing out only, then we put it to both FP0 and GPR2. We do
6120 not support reading in with no function known, if this safety
6121 check ever triggers, then we'll have to try harder. */
6122 gdb_assert (function || !readbuf);
6127 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
6130 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
6132 case mips_fval_both:
6133 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
6136 if (fval_reg != mips_fval_gpr)
6137 mips_xfer_register (gdbarch, regcache,
6138 (gdbarch_num_regs (gdbarch)
6139 + mips_regnum (gdbarch)->fp0),
6141 gdbarch_byte_order (gdbarch),
6142 readbuf, writebuf, 0);
6143 if (fval_reg != mips_fval_fpr)
6144 mips_xfer_register (gdbarch, regcache,
6145 gdbarch_num_regs (gdbarch) + 2,
6147 gdbarch_byte_order (gdbarch),
6148 readbuf, writebuf, 0);
6149 return RETURN_VALUE_REGISTER_CONVENTION;
6153 /* A scalar extract each part but least-significant-byte
6157 for (offset = 0, regnum = MIPS_V0_REGNUM;
6158 offset < TYPE_LENGTH (type);
6159 offset += MIPS64_REGSIZE, regnum++)
6161 int xfer = MIPS64_REGSIZE;
6162 if (offset + xfer > TYPE_LENGTH (type))
6163 xfer = TYPE_LENGTH (type) - offset;
6165 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
6166 offset, xfer, regnum);
6167 mips_xfer_register (gdbarch, regcache,
6168 gdbarch_num_regs (gdbarch) + regnum,
6169 xfer, gdbarch_byte_order (gdbarch),
6170 readbuf, writebuf, offset);
6172 return RETURN_VALUE_REGISTER_CONVENTION;
6176 /* Floating point register management.
6178 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6179 64bit operations, these early MIPS cpus treat fp register pairs
6180 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6181 registers and offer a compatibility mode that emulates the MIPS2 fp
6182 model. When operating in MIPS2 fp compat mode, later cpu's split
6183 double precision floats into two 32-bit chunks and store them in
6184 consecutive fp regs. To display 64-bit floats stored in this
6185 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6186 Throw in user-configurable endianness and you have a real mess.
6188 The way this works is:
6189 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6190 double-precision value will be split across two logical registers.
6191 The lower-numbered logical register will hold the low-order bits,
6192 regardless of the processor's endianness.
6193 - If we are on a 64-bit processor, and we are looking for a
6194 single-precision value, it will be in the low ordered bits
6195 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6196 save slot in memory.
6197 - If we are in 64-bit mode, everything is straightforward.
6199 Note that this code only deals with "live" registers at the top of the
6200 stack. We will attempt to deal with saved registers later, when
6201 the raw/cooked register interface is in place. (We need a general
6202 interface that can deal with dynamic saved register sizes -- fp
6203 regs could be 32 bits wide in one frame and 64 on the frame above
6206 /* Copy a 32-bit single-precision value from the current frame
6207 into rare_buffer. */
6210 mips_read_fp_register_single (struct frame_info *frame, int regno,
6211 gdb_byte *rare_buffer)
6213 struct gdbarch *gdbarch = get_frame_arch (frame);
6214 int raw_size = register_size (gdbarch, regno);
6215 gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size);
6217 if (!deprecated_frame_register_read (frame, regno, raw_buffer))
6218 error (_("can't read register %d (%s)"),
6219 regno, gdbarch_register_name (gdbarch, regno));
6222 /* We have a 64-bit value for this register. Find the low-order
6226 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6231 memcpy (rare_buffer, raw_buffer + offset, 4);
6235 memcpy (rare_buffer, raw_buffer, 4);
6239 /* Copy a 64-bit double-precision value from the current frame into
6240 rare_buffer. This may include getting half of it from the next
6244 mips_read_fp_register_double (struct frame_info *frame, int regno,
6245 gdb_byte *rare_buffer)
6247 struct gdbarch *gdbarch = get_frame_arch (frame);
6248 int raw_size = register_size (gdbarch, regno);
6250 if (raw_size == 8 && !mips2_fp_compat (frame))
6252 /* We have a 64-bit value for this register, and we should use
6254 if (!deprecated_frame_register_read (frame, regno, rare_buffer))
6255 error (_("can't read register %d (%s)"),
6256 regno, gdbarch_register_name (gdbarch, regno));
6260 int rawnum = regno % gdbarch_num_regs (gdbarch);
6262 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
6263 internal_error (__FILE__, __LINE__,
6264 _("mips_read_fp_register_double: bad access to "
6265 "odd-numbered FP register"));
6267 /* mips_read_fp_register_single will find the correct 32 bits from
6269 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6271 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
6272 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
6276 mips_read_fp_register_single (frame, regno, rare_buffer);
6277 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
6283 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
6285 { /* Do values for FP (float) regs. */
6286 struct gdbarch *gdbarch = get_frame_arch (frame);
6287 gdb_byte *raw_buffer;
6288 std::string flt_str, dbl_str;
6290 const struct type *flt_type = builtin_type (gdbarch)->builtin_float;
6291 const struct type *dbl_type = builtin_type (gdbarch)->builtin_double;
6295 alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)));
6297 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
6298 fprintf_filtered (file, "%*s",
6299 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
6302 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
6304 struct value_print_options opts;
6306 /* 4-byte registers: Print hex and floating. Also print even
6307 numbered registers as doubles. */
6308 mips_read_fp_register_single (frame, regnum, raw_buffer);
6309 flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g");
6311 get_formatted_print_options (&opts, 'x');
6312 print_scalar_formatted (raw_buffer,
6313 builtin_type (gdbarch)->builtin_uint32,
6316 fprintf_filtered (file, " flt: %s", flt_str.c_str ());
6318 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
6320 mips_read_fp_register_double (frame, regnum, raw_buffer);
6321 dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g");
6323 fprintf_filtered (file, " dbl: %s", dbl_str.c_str ());
6328 struct value_print_options opts;
6330 /* Eight byte registers: print each one as hex, float and double. */
6331 mips_read_fp_register_single (frame, regnum, raw_buffer);
6332 flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g");
6334 mips_read_fp_register_double (frame, regnum, raw_buffer);
6335 dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g");
6337 get_formatted_print_options (&opts, 'x');
6338 print_scalar_formatted (raw_buffer,
6339 builtin_type (gdbarch)->builtin_uint64,
6342 fprintf_filtered (file, " flt: %s", flt_str.c_str ());
6343 fprintf_filtered (file, " dbl: %s", dbl_str.c_str ());
6348 mips_print_register (struct ui_file *file, struct frame_info *frame,
6351 struct gdbarch *gdbarch = get_frame_arch (frame);
6352 struct value_print_options opts;
6355 if (mips_float_register_p (gdbarch, regnum))
6357 mips_print_fp_register (file, frame, regnum);
6361 val = get_frame_register_value (frame, regnum);
6363 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
6365 /* The problem with printing numeric register names (r26, etc.) is that
6366 the user can't use them on input. Probably the best solution is to
6367 fix it so that either the numeric or the funky (a2, etc.) names
6368 are accepted on input. */
6369 if (regnum < MIPS_NUMREGS)
6370 fprintf_filtered (file, "(r%d): ", regnum);
6372 fprintf_filtered (file, ": ");
6374 get_formatted_print_options (&opts, 'x');
6375 val_print_scalar_formatted (value_type (val),
6376 value_embedded_offset (val),
6381 /* Print IEEE exception condition bits in FLAGS. */
6384 print_fpu_flags (struct ui_file *file, int flags)
6386 if (flags & (1 << 0))
6387 fputs_filtered (" inexact", file);
6388 if (flags & (1 << 1))
6389 fputs_filtered (" uflow", file);
6390 if (flags & (1 << 2))
6391 fputs_filtered (" oflow", file);
6392 if (flags & (1 << 3))
6393 fputs_filtered (" div0", file);
6394 if (flags & (1 << 4))
6395 fputs_filtered (" inval", file);
6396 if (flags & (1 << 5))
6397 fputs_filtered (" unimp", file);
6398 fputc_filtered ('\n', file);
6401 /* Print interesting information about the floating point processor
6402 (if present) or emulator. */
6405 mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
6406 struct frame_info *frame, const char *args)
6408 int fcsr = mips_regnum (gdbarch)->fp_control_status;
6409 enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch);
6413 if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs))
6414 type = MIPS_FPU_NONE;
6416 fprintf_filtered (file, "fpu type: %s\n",
6417 type == MIPS_FPU_DOUBLE ? "double-precision"
6418 : type == MIPS_FPU_SINGLE ? "single-precision"
6421 if (type == MIPS_FPU_NONE)
6424 fprintf_filtered (file, "reg size: %d bits\n",
6425 register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8);
6427 fputs_filtered ("cond :", file);
6428 if (fcs & (1 << 23))
6429 fputs_filtered (" 0", file);
6430 for (i = 1; i <= 7; i++)
6431 if (fcs & (1 << (24 + i)))
6432 fprintf_filtered (file, " %d", i);
6433 fputc_filtered ('\n', file);
6435 fputs_filtered ("cause :", file);
6436 print_fpu_flags (file, (fcs >> 12) & 0x3f);
6437 fputs ("mask :", stdout);
6438 print_fpu_flags (file, (fcs >> 7) & 0x1f);
6439 fputs ("flags :", stdout);
6440 print_fpu_flags (file, (fcs >> 2) & 0x1f);
6442 fputs_filtered ("rounding: ", file);
6445 case 0: fputs_filtered ("nearest\n", file); break;
6446 case 1: fputs_filtered ("zero\n", file); break;
6447 case 2: fputs_filtered ("+inf\n", file); break;
6448 case 3: fputs_filtered ("-inf\n", file); break;
6451 fputs_filtered ("flush :", file);
6452 if (fcs & (1 << 21))
6453 fputs_filtered (" nearest", file);
6454 if (fcs & (1 << 22))
6455 fputs_filtered (" override", file);
6456 if (fcs & (1 << 24))
6457 fputs_filtered (" zero", file);
6458 if ((fcs & (0xb << 21)) == 0)
6459 fputs_filtered (" no", file);
6460 fputc_filtered ('\n', file);
6462 fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no");
6463 fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no");
6464 fputc_filtered ('\n', file);
6466 default_print_float_info (gdbarch, file, frame, args);
6469 /* Replacement for generic do_registers_info.
6470 Print regs in pretty columns. */
6473 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
6476 fprintf_filtered (file, " ");
6477 mips_print_fp_register (file, frame, regnum);
6478 fprintf_filtered (file, "\n");
6483 /* Print a row's worth of GP (int) registers, with name labels above. */
6486 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
6489 struct gdbarch *gdbarch = get_frame_arch (frame);
6490 /* Do values for GP (int) regs. */
6491 const gdb_byte *raw_buffer;
6492 struct value *value;
6493 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols
6498 /* For GP registers, we print a separate row of names above the vals. */
6499 for (col = 0, regnum = start_regnum;
6500 col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch);
6503 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6504 continue; /* unused register */
6505 if (mips_float_register_p (gdbarch, regnum))
6506 break; /* End the row: reached FP register. */
6507 /* Large registers are handled separately. */
6508 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6511 break; /* End the row before this register. */
6513 /* Print this register on a row by itself. */
6514 mips_print_register (file, frame, regnum);
6515 fprintf_filtered (file, "\n");
6519 fprintf_filtered (file, " ");
6520 fprintf_filtered (file,
6521 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
6522 gdbarch_register_name (gdbarch, regnum));
6529 /* Print the R0 to R31 names. */
6530 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
6531 fprintf_filtered (file, "\n R%-4d",
6532 start_regnum % gdbarch_num_regs (gdbarch));
6534 fprintf_filtered (file, "\n ");
6536 /* Now print the values in hex, 4 or 8 to the row. */
6537 for (col = 0, regnum = start_regnum;
6538 col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch);
6541 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6542 continue; /* unused register */
6543 if (mips_float_register_p (gdbarch, regnum))
6544 break; /* End row: reached FP register. */
6545 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6546 break; /* End row: large register. */
6548 /* OK: get the data in raw format. */
6549 value = get_frame_register_value (frame, regnum);
6550 if (value_optimized_out (value)
6551 || !value_entirely_available (value))
6553 fprintf_filtered (file, "%*s ",
6554 (int) mips_abi_regsize (gdbarch) * 2,
6555 (mips_abi_regsize (gdbarch) == 4 ? "<unavl>"
6556 : "<unavailable>"));
6560 raw_buffer = value_contents_all (value);
6561 /* pad small registers */
6563 byte < (mips_abi_regsize (gdbarch)
6564 - register_size (gdbarch, regnum)); byte++)
6565 fprintf_filtered (file, " ");
6566 /* Now print the register value in hex, endian order. */
6567 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6569 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
6570 byte < register_size (gdbarch, regnum); byte++)
6571 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6573 for (byte = register_size (gdbarch, regnum) - 1;
6575 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6576 fprintf_filtered (file, " ");
6579 if (col > 0) /* ie. if we actually printed anything... */
6580 fprintf_filtered (file, "\n");
6585 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6588 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
6589 struct frame_info *frame, int regnum, int all)
6591 if (regnum != -1) /* Do one specified register. */
6593 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
6594 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
6595 error (_("Not a valid register for the current processor type"));
6597 mips_print_register (file, frame, regnum);
6598 fprintf_filtered (file, "\n");
6601 /* Do all (or most) registers. */
6603 regnum = gdbarch_num_regs (gdbarch);
6604 while (regnum < gdbarch_num_cooked_regs (gdbarch))
6606 if (mips_float_register_p (gdbarch, regnum))
6608 if (all) /* True for "INFO ALL-REGISTERS" command. */
6609 regnum = print_fp_register_row (file, frame, regnum);
6611 regnum += MIPS_NUMREGS; /* Skip floating point regs. */
6614 regnum = print_gp_register_row (file, frame, regnum);
6620 mips_single_step_through_delay (struct gdbarch *gdbarch,
6621 struct frame_info *frame)
6623 CORE_ADDR pc = get_frame_pc (frame);
6628 if ((mips_pc_is_mips (pc)
6629 && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc))
6630 || (mips_pc_is_micromips (gdbarch, pc)
6631 && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0))
6632 || (mips_pc_is_mips16 (gdbarch, pc)
6633 && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0)))
6636 isa = mips_pc_isa (gdbarch, pc);
6637 /* _has_delay_slot above will have validated the read. */
6638 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL);
6639 size = mips_insn_size (isa, insn);
6641 const address_space *aspace = get_frame_address_space (frame);
6643 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here;
6646 /* To skip prologues, I use this predicate. Returns either PC itself
6647 if the code at PC does not look like a function prologue; otherwise
6648 returns an address that (if we're lucky) follows the prologue. If
6649 LENIENT, then we must skip everything which is involved in setting
6650 up the frame (it's OK to skip more, just so long as we don't skip
6651 anything which might clobber the registers which are being saved.
6652 We must skip more in the case where part of the prologue is in the
6653 delay slot of a non-prologue instruction). */
6656 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
6659 CORE_ADDR func_addr;
6661 /* See if we can determine the end of the prologue via the symbol table.
6662 If so, then return either PC, or the PC after the prologue, whichever
6664 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
6666 CORE_ADDR post_prologue_pc
6667 = skip_prologue_using_sal (gdbarch, func_addr);
6668 if (post_prologue_pc != 0)
6669 return std::max (pc, post_prologue_pc);
6672 /* Can't determine prologue from the symbol table, need to examine
6675 /* Find an upper limit on the function prologue using the debug
6676 information. If the debug information could not be used to provide
6677 that bound, then use an arbitrary large number as the upper bound. */
6678 limit_pc = skip_prologue_using_sal (gdbarch, pc);
6680 limit_pc = pc + 100; /* Magic. */
6682 if (mips_pc_is_mips16 (gdbarch, pc))
6683 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6684 else if (mips_pc_is_micromips (gdbarch, pc))
6685 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6687 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6690 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6691 This is a helper function for mips_stack_frame_destroyed_p. */
6694 mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6696 CORE_ADDR func_addr = 0, func_end = 0;
6698 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6700 /* The MIPS epilogue is max. 12 bytes long. */
6701 CORE_ADDR addr = func_end - 12;
6703 if (addr < func_addr + 4)
6704 addr = func_addr + 4;
6708 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
6710 unsigned long high_word;
6713 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
6714 high_word = (inst >> 16) & 0xffff;
6716 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
6717 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
6718 && inst != 0x03e00008 /* jr $ra */
6719 && inst != 0x00000000) /* nop */
6729 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6730 This is a helper function for mips_stack_frame_destroyed_p. */
6733 micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6735 CORE_ADDR func_addr = 0;
6736 CORE_ADDR func_end = 0;
6744 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6747 /* The microMIPS epilogue is max. 12 bytes long. */
6748 addr = func_end - 12;
6750 if (addr < func_addr + 2)
6751 addr = func_addr + 2;
6755 for (; pc < func_end; pc += loc)
6758 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
6759 loc += MIPS_INSN16_SIZE;
6760 switch (mips_insn_size (ISA_MICROMIPS, insn))
6762 /* 32-bit instructions. */
6763 case 2 * MIPS_INSN16_SIZE:
6765 insn |= mips_fetch_instruction (gdbarch,
6766 ISA_MICROMIPS, pc + loc, NULL);
6767 loc += MIPS_INSN16_SIZE;
6768 switch (micromips_op (insn >> 16))
6770 case 0xc: /* ADDIU: bits 001100 */
6771 case 0x17: /* DADDIU: bits 010111 */
6772 sreg = b0s5_reg (insn >> 16);
6773 dreg = b5s5_reg (insn >> 16);
6774 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
6775 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
6776 /* (D)ADDIU $sp, imm */
6786 /* 16-bit instructions. */
6787 case MIPS_INSN16_SIZE:
6788 switch (micromips_op (insn))
6790 case 0x3: /* MOVE: bits 000011 */
6791 sreg = b0s5_reg (insn);
6792 dreg = b5s5_reg (insn);
6793 if (sreg == 0 && dreg == 0)
6794 /* MOVE $zero, $zero aka NOP */
6798 case 0x11: /* POOL16C: bits 010001 */
6799 if (b5s5_op (insn) == 0x18
6800 /* JRADDIUSP: bits 010011 11000 */
6801 || (b5s5_op (insn) == 0xd
6802 /* JRC: bits 010011 01101 */
6803 && b0s5_reg (insn) == MIPS_RA_REGNUM))
6808 case 0x13: /* POOL16D: bits 010011 */
6809 offset = micromips_decode_imm9 (b1s9_imm (insn));
6810 if ((insn & 0x1) == 0x1
6811 /* ADDIUSP: bits 010011 1 */
6825 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6826 This is a helper function for mips_stack_frame_destroyed_p. */
6829 mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6831 CORE_ADDR func_addr = 0, func_end = 0;
6833 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6835 /* The MIPS epilogue is max. 12 bytes long. */
6836 CORE_ADDR addr = func_end - 12;
6838 if (addr < func_addr + 4)
6839 addr = func_addr + 4;
6843 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
6845 unsigned short inst;
6847 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL);
6849 if ((inst & 0xf800) == 0xf000) /* extend */
6852 if (inst != 0x6300 /* addiu $sp,offset */
6853 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
6854 && inst != 0xe820 /* jr $ra */
6855 && inst != 0xe8a0 /* jrc $ra */
6856 && inst != 0x6500) /* nop */
6866 /* Implement the stack_frame_destroyed_p gdbarch method.
6868 The epilogue is defined here as the area at the end of a function,
6869 after an instruction which destroys the function's stack frame. */
6872 mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6874 if (mips_pc_is_mips16 (gdbarch, pc))
6875 return mips16_stack_frame_destroyed_p (gdbarch, pc);
6876 else if (mips_pc_is_micromips (gdbarch, pc))
6877 return micromips_stack_frame_destroyed_p (gdbarch, pc);
6879 return mips32_stack_frame_destroyed_p (gdbarch, pc);
6882 /* Root of all "set mips "/"show mips " commands. This will eventually be
6883 used for all MIPS-specific commands. */
6886 show_mips_command (const char *args, int from_tty)
6888 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
6892 set_mips_command (const char *args, int from_tty)
6895 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6896 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
6899 /* Commands to show/set the MIPS FPU type. */
6902 show_mipsfpu_command (const char *args, int from_tty)
6906 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
6909 ("The MIPS floating-point coprocessor is unknown "
6910 "because the current architecture is not MIPS.\n");
6914 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6916 case MIPS_FPU_SINGLE:
6917 fpu = "single-precision";
6919 case MIPS_FPU_DOUBLE:
6920 fpu = "double-precision";
6923 fpu = "absent (none)";
6926 internal_error (__FILE__, __LINE__, _("bad switch"));
6928 if (mips_fpu_type_auto)
6929 printf_unfiltered ("The MIPS floating-point coprocessor "
6930 "is set automatically (currently %s)\n",
6934 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
6939 set_mipsfpu_command (const char *args, int from_tty)
6941 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6942 "\"single\",\"none\" or \"auto\".\n");
6943 show_mipsfpu_command (args, from_tty);
6947 set_mipsfpu_single_command (const char *args, int from_tty)
6949 struct gdbarch_info info;
6950 gdbarch_info_init (&info);
6951 mips_fpu_type = MIPS_FPU_SINGLE;
6952 mips_fpu_type_auto = 0;
6953 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6954 instead of relying on globals. Doing that would let generic code
6955 handle the search for this specific architecture. */
6956 if (!gdbarch_update_p (info))
6957 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6961 set_mipsfpu_double_command (const char *args, int from_tty)
6963 struct gdbarch_info info;
6964 gdbarch_info_init (&info);
6965 mips_fpu_type = MIPS_FPU_DOUBLE;
6966 mips_fpu_type_auto = 0;
6967 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6968 instead of relying on globals. Doing that would let generic code
6969 handle the search for this specific architecture. */
6970 if (!gdbarch_update_p (info))
6971 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6975 set_mipsfpu_none_command (const char *args, int from_tty)
6977 struct gdbarch_info info;
6978 gdbarch_info_init (&info);
6979 mips_fpu_type = MIPS_FPU_NONE;
6980 mips_fpu_type_auto = 0;
6981 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6982 instead of relying on globals. Doing that would let generic code
6983 handle the search for this specific architecture. */
6984 if (!gdbarch_update_p (info))
6985 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6989 set_mipsfpu_auto_command (const char *args, int from_tty)
6991 mips_fpu_type_auto = 1;
6994 /* Just like reinit_frame_cache, but with the right arguments to be
6995 callable as an sfunc. */
6998 reinit_frame_cache_sfunc (const char *args, int from_tty,
6999 struct cmd_list_element *c)
7001 reinit_frame_cache ();
7005 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
7007 gdb_disassembler *di
7008 = static_cast<gdb_disassembler *>(info->application_data);
7009 struct gdbarch *gdbarch = di->arch ();
7011 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7012 disassembler needs to be able to locally determine the ISA, and
7013 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7015 if (mips_pc_is_mips16 (gdbarch, memaddr))
7016 info->mach = bfd_mach_mips16;
7017 else if (mips_pc_is_micromips (gdbarch, memaddr))
7018 info->mach = bfd_mach_mips_micromips;
7020 /* Round down the instruction address to the appropriate boundary. */
7021 memaddr &= (info->mach == bfd_mach_mips16
7022 || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3;
7024 return default_print_insn (memaddr, info);
7027 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7030 mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
7032 CORE_ADDR pc = *pcptr;
7034 if (mips_pc_is_mips16 (gdbarch, pc))
7036 *pcptr = unmake_compact_addr (pc);
7037 return MIPS_BP_KIND_MIPS16;
7039 else if (mips_pc_is_micromips (gdbarch, pc))
7044 *pcptr = unmake_compact_addr (pc);
7045 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
7046 if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2))
7047 return MIPS_BP_KIND_MICROMIPS16;
7049 return MIPS_BP_KIND_MICROMIPS32;
7052 return MIPS_BP_KIND_MIPS32;
7055 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7057 static const gdb_byte *
7058 mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
7060 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
7064 case MIPS_BP_KIND_MIPS16:
7066 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
7067 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
7070 if (byte_order_for_code == BFD_ENDIAN_BIG)
7071 return mips16_big_breakpoint;
7073 return mips16_little_breakpoint;
7075 case MIPS_BP_KIND_MICROMIPS16:
7077 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 };
7078 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 };
7082 if (byte_order_for_code == BFD_ENDIAN_BIG)
7083 return micromips16_big_breakpoint;
7085 return micromips16_little_breakpoint;
7087 case MIPS_BP_KIND_MICROMIPS32:
7089 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 };
7090 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 };
7093 if (byte_order_for_code == BFD_ENDIAN_BIG)
7094 return micromips32_big_breakpoint;
7096 return micromips32_little_breakpoint;
7098 case MIPS_BP_KIND_MIPS32:
7100 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
7101 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
7104 if (byte_order_for_code == BFD_ENDIAN_BIG)
7105 return big_breakpoint;
7107 return little_breakpoint;
7110 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7114 /* Return non-zero if the standard MIPS instruction INST has a branch
7115 delay slot (i.e. it is a jump or branch instruction). This function
7116 is based on mips32_next_pc. */
7119 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst)
7125 op = itype_op (inst);
7126 if ((inst & 0xe0000000) != 0)
7128 rs = itype_rs (inst);
7129 rt = itype_rt (inst);
7130 return (is_octeon_bbit_op (op, gdbarch)
7131 || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7132 || op == 29 /* JALX: bits 011101 */
7135 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7136 || (rs == 9 && (rt & 0x2) == 0)
7137 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7138 || (rs == 10 && (rt & 0x2) == 0))));
7139 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7142 switch (op & 0x07) /* extract bits 28,27,26 */
7144 case 0: /* SPECIAL */
7145 op = rtype_funct (inst);
7146 return (op == 8 /* JR */
7147 || op == 9); /* JALR */
7148 break; /* end SPECIAL */
7149 case 1: /* REGIMM */
7150 rs = itype_rs (inst);
7151 rt = itype_rt (inst); /* branch condition */
7152 return ((rt & 0xc) == 0
7153 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7154 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7155 || ((rt & 0x1e) == 0x1c && rs == 0));
7156 /* BPOSGE32, BPOSGE64: bits 1110x */
7157 break; /* end REGIMM */
7158 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7164 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7165 delay slot (i.e. it is a jump or branch instruction). */
7168 mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr)
7173 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status);
7177 return mips32_instruction_has_delay_slot (gdbarch, insn);
7180 /* Return non-zero if the microMIPS instruction INSN, comprising the
7181 16-bit major opcode word in the high 16 bits and any second word
7182 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7183 jump or branch instruction). The instruction must be 32-bit if
7184 MUSTBE32 is set or can be any instruction otherwise. */
7187 micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32)
7189 ULONGEST major = insn >> 16;
7191 switch (micromips_op (major))
7193 /* 16-bit instructions. */
7194 case 0x33: /* B16: bits 110011 */
7195 case 0x2b: /* BNEZ16: bits 101011 */
7196 case 0x23: /* BEQZ16: bits 100011 */
7198 case 0x11: /* POOL16C: bits 010001 */
7200 && ((b5s5_op (major) == 0xc
7201 /* JR16: bits 010001 01100 */
7202 || (b5s5_op (major) & 0x1e) == 0xe)));
7203 /* JALR16, JALRS16: bits 010001 0111x */
7204 /* 32-bit instructions. */
7205 case 0x3d: /* JAL: bits 111101 */
7206 case 0x3c: /* JALX: bits 111100 */
7207 case 0x35: /* J: bits 110101 */
7208 case 0x2d: /* BNE: bits 101101 */
7209 case 0x25: /* BEQ: bits 100101 */
7210 case 0x1d: /* JALS: bits 011101 */
7212 case 0x10: /* POOL32I: bits 010000 */
7213 return ((b5s5_op (major) & 0x1c) == 0x0
7214 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7215 || (b5s5_op (major) & 0x1d) == 0x4
7216 /* BLEZ, BGTZ: bits 010000 001x0 */
7217 || (b5s5_op (major) & 0x1d) == 0x11
7218 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7219 || ((b5s5_op (major) & 0x1e) == 0x14
7220 && (major & 0x3) == 0x0)
7221 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7222 || (b5s5_op (major) & 0x1e) == 0x1a
7223 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7224 || ((b5s5_op (major) & 0x1e) == 0x1c
7225 && (major & 0x3) == 0x0)
7226 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7227 || ((b5s5_op (major) & 0x1c) == 0x1c
7228 && (major & 0x3) == 0x1));
7229 /* BC1ANY*: bits 010000 111xx xxx01 */
7230 case 0x0: /* POOL32A: bits 000000 */
7231 return (b0s6_op (insn) == 0x3c
7232 /* POOL32Axf: bits 000000 ... 111100 */
7233 && (b6s10_ext (insn) & 0x2bf) == 0x3c);
7234 /* JALR, JALR.HB: 000000 000x111100 111100 */
7235 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7241 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7242 slot (i.e. it is a non-compact jump instruction). The instruction
7243 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7246 micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
7247 CORE_ADDR addr, int mustbe32)
7253 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7256 size = mips_insn_size (ISA_MICROMIPS, insn);
7258 if (size == 2 * MIPS_INSN16_SIZE)
7260 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7265 return micromips_instruction_has_delay_slot (insn, mustbe32);
7268 /* Return non-zero if the MIPS16 instruction INST, which must be
7269 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7270 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7271 instruction). This function is based on mips16_next_pc. */
7274 mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32)
7276 if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7278 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7281 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7282 slot (i.e. it is a non-compact jump instruction). The instruction
7283 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7286 mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
7287 CORE_ADDR addr, int mustbe32)
7289 unsigned short insn;
7292 insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status);
7296 return mips16_instruction_has_delay_slot (insn, mustbe32);
7299 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7300 This assumes KSSEG exists. */
7303 mips_segment_boundary (CORE_ADDR bpaddr)
7305 CORE_ADDR mask = CORE_ADDR_MAX;
7308 if (sizeof (CORE_ADDR) == 8)
7309 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7310 a compiler warning produced where CORE_ADDR is a 32-bit type even
7311 though in that case this is dead code). */
7312 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3)
7315 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr)
7316 segsize = 29; /* 32-bit compatibility segment */
7318 segsize = 62; /* xkseg */
7320 case 2: /* xkphys */
7323 default: /* xksseg (1), xkuseg/kuseg (0) */
7327 else if (bpaddr & 0x80000000) /* kernel segment */
7330 segsize = 31; /* user segment */
7332 return bpaddr & mask;
7335 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7336 it backwards if necessary. Return the address of the new location. */
7339 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
7341 CORE_ADDR prev_addr;
7343 CORE_ADDR func_addr;
7345 /* If a breakpoint is set on the instruction in a branch delay slot,
7346 GDB gets confused. When the breakpoint is hit, the PC isn't on
7347 the instruction in the branch delay slot, the PC will point to
7348 the branch instruction. Since the PC doesn't match any known
7349 breakpoints, GDB reports a trap exception.
7351 There are two possible fixes for this problem.
7353 1) When the breakpoint gets hit, see if the BD bit is set in the
7354 Cause register (which indicates the last exception occurred in a
7355 branch delay slot). If the BD bit is set, fix the PC to point to
7356 the instruction in the branch delay slot.
7358 2) When the user sets the breakpoint, don't allow him to set the
7359 breakpoint on the instruction in the branch delay slot. Instead
7360 move the breakpoint to the branch instruction (which will have
7363 The problem with the first solution is that if the user then
7364 single-steps the processor, the branch instruction will get
7365 skipped (since GDB thinks the PC is on the instruction in the
7368 So, we'll use the second solution. To do this we need to know if
7369 the instruction we're trying to set the breakpoint on is in the
7370 branch delay slot. */
7372 boundary = mips_segment_boundary (bpaddr);
7374 /* Make sure we don't scan back before the beginning of the current
7375 function, since we may fetch constant data or insns that look like
7376 a jump. Of course we might do that anyway if the compiler has
7377 moved constants inline. :-( */
7378 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL)
7379 && func_addr > boundary && func_addr <= bpaddr)
7380 boundary = func_addr;
7382 if (mips_pc_is_mips (bpaddr))
7384 if (bpaddr == boundary)
7387 /* If the previous instruction has a branch delay slot, we have
7388 to move the breakpoint to the branch instruction. */
7389 prev_addr = bpaddr - 4;
7390 if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr))
7395 int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int);
7396 CORE_ADDR addr, jmpaddr;
7399 boundary = unmake_compact_addr (boundary);
7401 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7402 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7403 so try for that first, then try the 2 byte JALR/JR.
7404 The microMIPS ASE has a whole range of jumps and branches
7405 with delay slots, some of which take 4 bytes and some take
7406 2 bytes, so the idea is the same.
7407 FIXME: We have to assume that bpaddr is not the second half
7408 of an extended instruction. */
7409 insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr)
7410 ? micromips_insn_at_pc_has_delay_slot
7411 : mips16_insn_at_pc_has_delay_slot);
7415 for (i = 1; i < 4; i++)
7417 if (unmake_compact_addr (addr) == boundary)
7419 addr -= MIPS_INSN16_SIZE;
7420 if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0))
7421 /* Looks like a JR/JALR at [target-1], but it could be
7422 the second word of a previous JAL/JALX, so record it
7423 and check back one more. */
7425 else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1))
7428 /* Looks like a JAL/JALX at [target-2], but it could also
7429 be the second word of a previous JAL/JALX, record it,
7430 and check back one more. */
7433 /* Looks like a JAL/JALX at [target-3], so any previously
7434 recorded JAL/JALX or JR/JALR must be wrong, because:
7437 -2: JAL-ext (can't be JAL/JALX)
7438 -1: bdslot (can't be JR/JALR)
7441 Of course it could be another JAL-ext which looks
7442 like a JAL, but in that case we'd have broken out
7443 of this loop at [target-2]:
7447 -2: bdslot (can't be jmp)
7454 /* Not a jump instruction: if we're at [target-1] this
7455 could be the second word of a JAL/JALX, so continue;
7456 otherwise we're done. */
7469 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7470 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7473 mips_is_stub_suffix (const char *suffix, int zero)
7478 return zero && suffix[1] == '\0';
7480 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0');
7485 return suffix[1] == '\0';
7491 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7492 call stubs, one of sf, df, sc, or dc. */
7495 mips_is_stub_mode (const char *mode)
7497 return ((mode[0] == 's' || mode[0] == 'd')
7498 && (mode[1] == 'f' || mode[1] == 'c'));
7501 /* Code at PC is a compiler-generated stub. Such a stub for a function
7502 bar might have a name like __fn_stub_bar, and might look like this:
7509 followed by (or interspersed with):
7516 addiu $25, $25, %lo(bar)
7519 ($1 may be used in old code; for robustness we accept any register)
7522 lui $28, %hi(_gp_disp)
7523 addiu $28, $28, %lo(_gp_disp)
7526 addiu $25, $25, %lo(bar)
7529 In the case of a __call_stub_bar stub, the sequence to set up
7530 arguments might look like this:
7537 followed by (or interspersed with) one of the jump sequences above.
7539 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7540 of J or JR, respectively, followed by:
7546 We are at the beginning of the stub here, and scan down and extract
7547 the target address from the jump immediate instruction or, if a jump
7548 register instruction is used, from the register referred. Return
7549 the value of PC calculated or 0 if inconclusive.
7551 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7554 mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc)
7556 struct gdbarch *gdbarch = get_frame_arch (frame);
7557 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7558 int addrreg = MIPS_ZERO_REGNUM;
7559 CORE_ADDR start_pc = pc;
7560 CORE_ADDR target_pc = 0;
7567 status == 0 && target_pc == 0 && i < 20;
7568 i++, pc += MIPS_INSN32_SIZE)
7570 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
7576 switch (itype_op (inst))
7578 case 0: /* SPECIAL */
7579 switch (rtype_funct (inst))
7583 rs = rtype_rs (inst);
7584 if (rs == MIPS_GP_REGNUM)
7585 target_pc = gp; /* Hmm... */
7586 else if (rs == addrreg)
7590 case 0x21: /* ADDU */
7591 rt = rtype_rt (inst);
7592 rs = rtype_rs (inst);
7593 rd = rtype_rd (inst);
7594 if (rd == MIPS_GP_REGNUM
7595 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM)
7596 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM)))
7604 target_pc = jtype_target (inst) << 2;
7605 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
7609 rt = itype_rt (inst);
7610 rs = itype_rs (inst);
7613 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7614 if (rt == MIPS_GP_REGNUM)
7616 else if (rt == addrreg)
7622 rt = itype_rt (inst);
7623 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16;
7624 if (rt == MIPS_GP_REGNUM)
7626 else if (rt != MIPS_ZERO_REGNUM)
7634 rt = itype_rt (inst);
7635 rs = itype_rs (inst);
7636 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7637 if (gp != 0 && rs == MIPS_GP_REGNUM)
7641 memset (buf, 0, sizeof (buf));
7642 status = target_read_memory (gp + imm, buf, sizeof (buf));
7644 addr = extract_signed_integer (buf, sizeof (buf), byte_order);
7653 /* If PC is in a MIPS16 call or return stub, return the address of the
7654 target PC, which is either the callee or the caller. There are several
7655 cases which must be handled:
7657 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7658 and the target PC is in $31 ($ra).
7659 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7660 and the target PC is in $2.
7661 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7662 i.e. before the JALR instruction, this is effectively a call stub
7663 and the target PC is in $2. Otherwise this is effectively
7664 a return stub and the target PC is in $18.
7665 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7666 JAL or JALR instruction, this is effectively a call stub and the
7667 target PC is buried in the instruction stream. Otherwise this
7668 is effectively a return stub and the target PC is in $18.
7669 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7670 stub and the target PC is buried in the instruction stream.
7672 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7673 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7677 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7679 struct gdbarch *gdbarch = get_frame_arch (frame);
7680 CORE_ADDR start_addr;
7684 /* Find the starting address and name of the function containing the PC. */
7685 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
7688 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7689 and the target PC is in $31 ($ra). */
7690 prefixlen = strlen (mips_str_mips16_ret_stub);
7691 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7692 && mips_is_stub_mode (name + prefixlen)
7693 && name[prefixlen + 2] == '\0')
7694 return get_frame_register_signed
7695 (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
7697 /* If the PC is in __mips16_call_stub_*, this is one of the call
7698 call/return stubs. */
7699 prefixlen = strlen (mips_str_mips16_call_stub);
7700 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0)
7702 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7703 and the target PC is in $2. */
7704 if (mips_is_stub_suffix (name + prefixlen, 0))
7705 return get_frame_register_signed
7706 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7708 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7709 i.e. before the JALR instruction, this is effectively a call stub
7710 and the target PC is in $2. Otherwise this is effectively
7711 a return stub and the target PC is in $18. */
7712 else if (mips_is_stub_mode (name + prefixlen)
7713 && name[prefixlen + 2] == '_'
7714 && mips_is_stub_suffix (name + prefixlen + 3, 0))
7716 if (pc == start_addr)
7717 /* This is the 'call' part of a call stub. The return
7718 address is in $2. */
7719 return get_frame_register_signed
7720 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7722 /* This is the 'return' part of a call stub. The return
7723 address is in $18. */
7724 return get_frame_register_signed
7725 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7728 return 0; /* Not a stub. */
7731 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7732 compiler-generated call or call/return stubs. */
7733 if (startswith (name, mips_str_fn_stub)
7734 || startswith (name, mips_str_call_stub))
7736 if (pc == start_addr)
7737 /* This is the 'call' part of a call stub. Call this helper
7738 to scan through this code for interesting instructions
7739 and determine the final PC. */
7740 return mips_get_mips16_fn_stub_pc (frame, pc);
7742 /* This is the 'return' part of a call stub. The return address
7744 return get_frame_register_signed
7745 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7748 return 0; /* Not a stub. */
7751 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7752 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7755 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name)
7757 CORE_ADDR start_addr;
7760 /* Find the starting address of the function containing the PC. */
7761 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
7764 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7765 the start, i.e. after the JALR instruction, this is effectively
7767 prefixlen = strlen (mips_str_mips16_call_stub);
7768 if (pc != start_addr
7769 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0
7770 && mips_is_stub_mode (name + prefixlen)
7771 && name[prefixlen + 2] == '_'
7772 && mips_is_stub_suffix (name + prefixlen + 3, 1))
7775 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7776 the JAL or JALR instruction, this is effectively a return stub. */
7777 prefixlen = strlen (mips_str_call_fp_stub);
7778 if (pc != start_addr
7779 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0)
7782 /* Consume the .pic. prefix of any PIC stub, this function must return
7783 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7784 or the call stub path will trigger in handle_inferior_event causing
7786 prefixlen = strlen (mips_str_pic);
7787 if (strncmp (name, mips_str_pic, prefixlen) == 0)
7790 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7791 prefixlen = strlen (mips_str_mips16_ret_stub);
7792 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7793 && mips_is_stub_mode (name + prefixlen)
7794 && name[prefixlen + 2] == '\0')
7797 return 0; /* Not a stub. */
7800 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7801 PC of the stub target. The stub just loads $t9 and jumps to it,
7802 so that $t9 has the correct value at function entry. */
7805 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7807 struct gdbarch *gdbarch = get_frame_arch (frame);
7808 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7809 struct bound_minimal_symbol msym;
7811 gdb_byte stub_code[16];
7812 int32_t stub_words[4];
7814 /* The stub for foo is named ".pic.foo", and is either two
7815 instructions inserted before foo or a three instruction sequence
7816 which jumps to foo. */
7817 msym = lookup_minimal_symbol_by_pc (pc);
7818 if (msym.minsym == NULL
7819 || BMSYMBOL_VALUE_ADDRESS (msym) != pc
7820 || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL
7821 || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
7824 /* A two-instruction header. */
7825 if (MSYMBOL_SIZE (msym.minsym) == 8)
7828 /* A three-instruction (plus delay slot) trampoline. */
7829 if (MSYMBOL_SIZE (msym.minsym) == 16)
7831 if (target_read_memory (pc, stub_code, 16) != 0)
7833 for (i = 0; i < 4; i++)
7834 stub_words[i] = extract_unsigned_integer (stub_code + i * 4,
7837 /* A stub contains these instructions:
7840 addiu t9, t9, %lo(target)
7843 This works even for N64, since stubs are only generated with
7845 if ((stub_words[0] & 0xffff0000U) == 0x3c190000
7846 && (stub_words[1] & 0xfc000000U) == 0x08000000
7847 && (stub_words[2] & 0xffff0000U) == 0x27390000
7848 && stub_words[3] == 0x00000000)
7849 return ((((stub_words[0] & 0x0000ffff) << 16)
7850 + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7853 /* Not a recognized stub. */
7858 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7860 CORE_ADDR requested_pc = pc;
7861 CORE_ADDR target_pc;
7868 new_pc = mips_skip_mips16_trampoline_code (frame, pc);
7872 new_pc = find_solib_trampoline_target (frame, pc);
7876 new_pc = mips_skip_pic_trampoline_code (frame, pc);
7880 while (pc != target_pc);
7882 return pc != requested_pc ? pc : 0;
7885 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7886 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7889 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
7892 if (num >= 0 && num < 32)
7894 else if (num >= 38 && num < 70)
7895 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
7897 regnum = mips_regnum (gdbarch)->hi;
7899 regnum = mips_regnum (gdbarch)->lo;
7900 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78)
7901 regnum = num + mips_regnum (gdbarch)->dspacc - 72;
7904 return gdbarch_num_regs (gdbarch) + regnum;
7908 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7909 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7912 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
7915 if (num >= 0 && num < 32)
7917 else if (num >= 32 && num < 64)
7918 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
7920 regnum = mips_regnum (gdbarch)->hi;
7922 regnum = mips_regnum (gdbarch)->lo;
7923 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72)
7924 regnum = num + mips_regnum (gdbarch)->dspacc - 66;
7927 return gdbarch_num_regs (gdbarch) + regnum;
7931 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
7933 /* Only makes sense to supply raw registers. */
7934 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
7935 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7936 decide if it is valid. Should instead define a standard sim/gdb
7937 register numbering scheme. */
7938 if (gdbarch_register_name (gdbarch,
7939 gdbarch_num_regs (gdbarch) + regnum) != NULL
7940 && gdbarch_register_name (gdbarch,
7941 gdbarch_num_regs (gdbarch)
7942 + regnum)[0] != '\0')
7945 return LEGACY_SIM_REGNO_IGNORE;
7949 /* Convert an integer into an address. Extracting the value signed
7950 guarantees a correctly sign extended address. */
7953 mips_integer_to_address (struct gdbarch *gdbarch,
7954 struct type *type, const gdb_byte *buf)
7956 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7957 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
7960 /* Dummy virtual frame pointer method. This is no more or less accurate
7961 than most other architectures; we just need to be explicit about it,
7962 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7963 an assertion failure. */
7966 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
7967 CORE_ADDR pc, int *reg, LONGEST *offset)
7969 *reg = MIPS_SP_REGNUM;
7974 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
7976 enum mips_abi *abip = (enum mips_abi *) obj;
7977 const char *name = bfd_get_section_name (abfd, sect);
7979 if (*abip != MIPS_ABI_UNKNOWN)
7982 if (!startswith (name, ".mdebug."))
7985 if (strcmp (name, ".mdebug.abi32") == 0)
7986 *abip = MIPS_ABI_O32;
7987 else if (strcmp (name, ".mdebug.abiN32") == 0)
7988 *abip = MIPS_ABI_N32;
7989 else if (strcmp (name, ".mdebug.abi64") == 0)
7990 *abip = MIPS_ABI_N64;
7991 else if (strcmp (name, ".mdebug.abiO64") == 0)
7992 *abip = MIPS_ABI_O64;
7993 else if (strcmp (name, ".mdebug.eabi32") == 0)
7994 *abip = MIPS_ABI_EABI32;
7995 else if (strcmp (name, ".mdebug.eabi64") == 0)
7996 *abip = MIPS_ABI_EABI64;
7998 warning (_("unsupported ABI %s."), name + 8);
8002 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
8004 int *lbp = (int *) obj;
8005 const char *name = bfd_get_section_name (abfd, sect);
8007 if (startswith (name, ".gcc_compiled_long32"))
8009 else if (startswith (name, ".gcc_compiled_long64"))
8011 else if (startswith (name, ".gcc_compiled_long"))
8012 warning (_("unrecognized .gcc_compiled_longXX"));
8015 static enum mips_abi
8016 global_mips_abi (void)
8020 for (i = 0; mips_abi_strings[i] != NULL; i++)
8021 if (mips_abi_strings[i] == mips_abi_string)
8022 return (enum mips_abi) i;
8024 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
8027 /* Return the default compressed instruction set, either of MIPS16
8028 or microMIPS, selected when none could have been determined from
8029 the ELF header of the binary being executed (or no binary has been
8032 static enum mips_isa
8033 global_mips_compression (void)
8037 for (i = 0; mips_compression_strings[i] != NULL; i++)
8038 if (mips_compression_strings[i] == mips_compression_string)
8039 return (enum mips_isa) i;
8041 internal_error (__FILE__, __LINE__, _("unknown compressed ISA string"));
8045 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
8047 /* If the size matches the set of 32-bit or 64-bit integer registers,
8048 assume that's what we've got. */
8049 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
8050 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
8052 /* If the size matches the full set of registers GDB traditionally
8053 knows about, including floating point, for either 32-bit or
8054 64-bit, assume that's what we've got. */
8055 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
8056 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
8058 /* Otherwise we don't have a useful guess. */
8061 static struct value *
8062 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
8064 const int *reg_p = (const int *) baton;
8065 return value_of_register (*reg_p, frame);
8068 static struct gdbarch *
8069 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8071 struct gdbarch *gdbarch;
8072 struct gdbarch_tdep *tdep;
8074 enum mips_abi mips_abi, found_abi, wanted_abi;
8076 enum mips_fpu_type fpu_type;
8077 struct tdesc_arch_data *tdesc_data = NULL;
8078 int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY;
8079 const char **reg_names;
8080 struct mips_regnum mips_regnum, *regnum;
8081 enum mips_isa mips_isa;
8085 /* First of all, extract the elf_flags, if available. */
8086 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8087 elf_flags = elf_elfheader (info.abfd)->e_flags;
8088 else if (arches != NULL)
8089 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
8093 fprintf_unfiltered (gdb_stdlog,
8094 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
8096 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8097 switch ((elf_flags & EF_MIPS_ABI))
8099 case E_MIPS_ABI_O32:
8100 found_abi = MIPS_ABI_O32;
8102 case E_MIPS_ABI_O64:
8103 found_abi = MIPS_ABI_O64;
8105 case E_MIPS_ABI_EABI32:
8106 found_abi = MIPS_ABI_EABI32;
8108 case E_MIPS_ABI_EABI64:
8109 found_abi = MIPS_ABI_EABI64;
8112 if ((elf_flags & EF_MIPS_ABI2))
8113 found_abi = MIPS_ABI_N32;
8115 found_abi = MIPS_ABI_UNKNOWN;
8119 /* GCC creates a pseudo-section whose name describes the ABI. */
8120 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
8121 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
8123 /* If we have no useful BFD information, use the ABI from the last
8124 MIPS architecture (if there is one). */
8125 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
8126 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
8128 /* Try the architecture for any hint of the correct ABI. */
8129 if (found_abi == MIPS_ABI_UNKNOWN
8130 && info.bfd_arch_info != NULL
8131 && info.bfd_arch_info->arch == bfd_arch_mips)
8133 switch (info.bfd_arch_info->mach)
8135 case bfd_mach_mips3900:
8136 found_abi = MIPS_ABI_EABI32;
8138 case bfd_mach_mips4100:
8139 case bfd_mach_mips5000:
8140 found_abi = MIPS_ABI_EABI64;
8142 case bfd_mach_mips8000:
8143 case bfd_mach_mips10000:
8144 /* On Irix, ELF64 executables use the N64 ABI. The
8145 pseudo-sections which describe the ABI aren't present
8146 on IRIX. (Even for executables created by gcc.) */
8147 if (info.abfd != NULL
8148 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8149 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8150 found_abi = MIPS_ABI_N64;
8152 found_abi = MIPS_ABI_N32;
8157 /* Default 64-bit objects to N64 instead of O32. */
8158 if (found_abi == MIPS_ABI_UNKNOWN
8159 && info.abfd != NULL
8160 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8161 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8162 found_abi = MIPS_ABI_N64;
8165 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
8168 /* What has the user specified from the command line? */
8169 wanted_abi = global_mips_abi ();
8171 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
8174 /* Now that we have found what the ABI for this binary would be,
8175 check whether the user is overriding it. */
8176 if (wanted_abi != MIPS_ABI_UNKNOWN)
8177 mips_abi = wanted_abi;
8178 else if (found_abi != MIPS_ABI_UNKNOWN)
8179 mips_abi = found_abi;
8181 mips_abi = MIPS_ABI_O32;
8183 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
8186 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8187 if (mips_abi != MIPS_ABI_EABI32
8188 && mips_abi != MIPS_ABI_O32
8189 && info.bfd_arch_info != NULL
8190 && info.bfd_arch_info->arch == bfd_arch_mips
8191 && info.bfd_arch_info->bits_per_word < 64)
8192 info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000);
8194 /* Determine the default compressed ISA. */
8195 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0
8196 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0)
8197 mips_isa = ISA_MICROMIPS;
8198 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0
8199 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0)
8200 mips_isa = ISA_MIPS16;
8202 mips_isa = global_mips_compression ();
8203 mips_compression_string = mips_compression_strings[mips_isa];
8205 /* Also used when doing an architecture lookup. */
8207 fprintf_unfiltered (gdb_stdlog,
8208 "mips_gdbarch_init: "
8209 "mips64_transfers_32bit_regs_p = %d\n",
8210 mips64_transfers_32bit_regs_p);
8212 /* Determine the MIPS FPU type. */
8215 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8216 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
8217 Tag_GNU_MIPS_ABI_FP);
8218 #endif /* HAVE_ELF */
8220 if (!mips_fpu_type_auto)
8221 fpu_type = mips_fpu_type;
8222 else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY)
8224 switch (elf_fpu_type)
8226 case Val_GNU_MIPS_ABI_FP_DOUBLE:
8227 fpu_type = MIPS_FPU_DOUBLE;
8229 case Val_GNU_MIPS_ABI_FP_SINGLE:
8230 fpu_type = MIPS_FPU_SINGLE;
8232 case Val_GNU_MIPS_ABI_FP_SOFT:
8234 /* Soft float or unknown. */
8235 fpu_type = MIPS_FPU_NONE;
8239 else if (info.bfd_arch_info != NULL
8240 && info.bfd_arch_info->arch == bfd_arch_mips)
8241 switch (info.bfd_arch_info->mach)
8243 case bfd_mach_mips3900:
8244 case bfd_mach_mips4100:
8245 case bfd_mach_mips4111:
8246 case bfd_mach_mips4120:
8247 fpu_type = MIPS_FPU_NONE;
8249 case bfd_mach_mips4650:
8250 fpu_type = MIPS_FPU_SINGLE;
8253 fpu_type = MIPS_FPU_DOUBLE;
8256 else if (arches != NULL)
8257 fpu_type = MIPS_FPU_TYPE (arches->gdbarch);
8259 fpu_type = MIPS_FPU_DOUBLE;
8261 fprintf_unfiltered (gdb_stdlog,
8262 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
8264 /* Check for blatant incompatibilities. */
8266 /* If we have only 32-bit registers, then we can't debug a 64-bit
8268 if (info.target_desc
8269 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
8270 && mips_abi != MIPS_ABI_EABI32
8271 && mips_abi != MIPS_ABI_O32)
8274 /* Fill in the OS dependent register numbers and names. */
8275 if (info.osabi == GDB_OSABI_LINUX)
8277 mips_regnum.fp0 = 38;
8278 mips_regnum.pc = 37;
8279 mips_regnum.cause = 36;
8280 mips_regnum.badvaddr = 35;
8281 mips_regnum.hi = 34;
8282 mips_regnum.lo = 33;
8283 mips_regnum.fp_control_status = 70;
8284 mips_regnum.fp_implementation_revision = 71;
8285 mips_regnum.dspacc = -1;
8286 mips_regnum.dspctl = -1;
8290 reg_names = mips_linux_reg_names;
8294 mips_regnum.lo = MIPS_EMBED_LO_REGNUM;
8295 mips_regnum.hi = MIPS_EMBED_HI_REGNUM;
8296 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
8297 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM;
8298 mips_regnum.pc = MIPS_EMBED_PC_REGNUM;
8299 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM;
8300 mips_regnum.fp_control_status = 70;
8301 mips_regnum.fp_implementation_revision = 71;
8302 mips_regnum.dspacc = dspacc = -1;
8303 mips_regnum.dspctl = dspctl = -1;
8304 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
8305 if (info.bfd_arch_info != NULL
8306 && info.bfd_arch_info->mach == bfd_mach_mips3900)
8307 reg_names = mips_tx39_reg_names;
8309 reg_names = mips_generic_reg_names;
8312 /* Check any target description for validity. */
8313 if (tdesc_has_registers (info.target_desc))
8315 static const char *const mips_gprs[] = {
8316 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8317 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8318 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8319 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8321 static const char *const mips_fprs[] = {
8322 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8323 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8324 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8325 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8328 const struct tdesc_feature *feature;
8331 feature = tdesc_find_feature (info.target_desc,
8332 "org.gnu.gdb.mips.cpu");
8333 if (feature == NULL)
8336 tdesc_data = tdesc_data_alloc ();
8339 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
8340 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8344 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8345 mips_regnum.lo, "lo");
8346 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8347 mips_regnum.hi, "hi");
8348 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8349 mips_regnum.pc, "pc");
8353 tdesc_data_cleanup (tdesc_data);
8357 feature = tdesc_find_feature (info.target_desc,
8358 "org.gnu.gdb.mips.cp0");
8359 if (feature == NULL)
8361 tdesc_data_cleanup (tdesc_data);
8366 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8367 mips_regnum.badvaddr, "badvaddr");
8368 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8369 MIPS_PS_REGNUM, "status");
8370 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8371 mips_regnum.cause, "cause");
8375 tdesc_data_cleanup (tdesc_data);
8379 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8380 backend is not prepared for that, though. */
8381 feature = tdesc_find_feature (info.target_desc,
8382 "org.gnu.gdb.mips.fpu");
8383 if (feature == NULL)
8385 tdesc_data_cleanup (tdesc_data);
8390 for (i = 0; i < 32; i++)
8391 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8392 i + mips_regnum.fp0, mips_fprs[i]);
8394 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8395 mips_regnum.fp_control_status,
8398 &= tdesc_numbered_register (feature, tdesc_data,
8399 mips_regnum.fp_implementation_revision,
8404 tdesc_data_cleanup (tdesc_data);
8408 num_regs = mips_regnum.fp_implementation_revision + 1;
8412 feature = tdesc_find_feature (info.target_desc,
8413 "org.gnu.gdb.mips.dsp");
8414 /* The DSP registers are optional; it's OK if they are absent. */
8415 if (feature != NULL)
8419 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8420 dspacc + i++, "hi1");
8421 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8422 dspacc + i++, "lo1");
8423 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8424 dspacc + i++, "hi2");
8425 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8426 dspacc + i++, "lo2");
8427 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8428 dspacc + i++, "hi3");
8429 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8430 dspacc + i++, "lo3");
8432 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8437 tdesc_data_cleanup (tdesc_data);
8441 mips_regnum.dspacc = dspacc;
8442 mips_regnum.dspctl = dspctl;
8444 num_regs = mips_regnum.dspctl + 1;
8448 /* It would be nice to detect an attempt to use a 64-bit ABI
8449 when only 32-bit registers are provided. */
8453 /* Try to find a pre-existing architecture. */
8454 for (arches = gdbarch_list_lookup_by_info (arches, &info);
8456 arches = gdbarch_list_lookup_by_info (arches->next, &info))
8458 /* MIPS needs to be pedantic about which ABI and the compressed
8459 ISA variation the object is using. */
8460 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
8462 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
8464 if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa)
8466 /* Need to be pedantic about which register virtual size is
8468 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
8469 != mips64_transfers_32bit_regs_p)
8471 /* Be pedantic about which FPU is selected. */
8472 if (MIPS_FPU_TYPE (arches->gdbarch) != fpu_type)
8475 if (tdesc_data != NULL)
8476 tdesc_data_cleanup (tdesc_data);
8477 return arches->gdbarch;
8480 /* Need a new architecture. Fill in a target specific vector. */
8481 tdep = XCNEW (struct gdbarch_tdep);
8482 gdbarch = gdbarch_alloc (&info, tdep);
8483 tdep->elf_flags = elf_flags;
8484 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
8485 tdep->found_abi = found_abi;
8486 tdep->mips_abi = mips_abi;
8487 tdep->mips_isa = mips_isa;
8488 tdep->mips_fpu_type = fpu_type;
8489 tdep->register_size_valid_p = 0;
8490 tdep->register_size = 0;
8492 if (info.target_desc)
8494 /* Some useful properties can be inferred from the target. */
8495 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
8497 tdep->register_size_valid_p = 1;
8498 tdep->register_size = 4;
8500 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
8502 tdep->register_size_valid_p = 1;
8503 tdep->register_size = 8;
8507 /* Initially set everything according to the default ABI/ISA. */
8508 set_gdbarch_short_bit (gdbarch, 16);
8509 set_gdbarch_int_bit (gdbarch, 32);
8510 set_gdbarch_float_bit (gdbarch, 32);
8511 set_gdbarch_double_bit (gdbarch, 64);
8512 set_gdbarch_long_double_bit (gdbarch, 64);
8513 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
8514 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
8515 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
8517 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8518 mips_ax_pseudo_register_collect);
8519 set_gdbarch_ax_pseudo_register_push_stack
8520 (gdbarch, mips_ax_pseudo_register_push_stack);
8522 set_gdbarch_elf_make_msymbol_special (gdbarch,
8523 mips_elf_make_msymbol_special);
8524 set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special);
8525 set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr);
8526 set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line);
8528 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum);
8529 *regnum = mips_regnum;
8530 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
8531 set_gdbarch_num_regs (gdbarch, num_regs);
8532 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8533 set_gdbarch_register_name (gdbarch, mips_register_name);
8534 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
8535 tdep->mips_processor_reg_names = reg_names;
8536 tdep->regnum = regnum;
8541 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
8542 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
8543 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8544 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8545 tdep->default_mask_address_p = 0;
8546 set_gdbarch_long_bit (gdbarch, 32);
8547 set_gdbarch_ptr_bit (gdbarch, 32);
8548 set_gdbarch_long_long_bit (gdbarch, 64);
8551 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
8552 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
8553 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8554 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8555 tdep->default_mask_address_p = 0;
8556 set_gdbarch_long_bit (gdbarch, 32);
8557 set_gdbarch_ptr_bit (gdbarch, 32);
8558 set_gdbarch_long_long_bit (gdbarch, 64);
8560 case MIPS_ABI_EABI32:
8561 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8562 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8563 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8564 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8565 tdep->default_mask_address_p = 0;
8566 set_gdbarch_long_bit (gdbarch, 32);
8567 set_gdbarch_ptr_bit (gdbarch, 32);
8568 set_gdbarch_long_long_bit (gdbarch, 64);
8570 case MIPS_ABI_EABI64:
8571 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8572 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8573 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8574 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8575 tdep->default_mask_address_p = 0;
8576 set_gdbarch_long_bit (gdbarch, 64);
8577 set_gdbarch_ptr_bit (gdbarch, 64);
8578 set_gdbarch_long_long_bit (gdbarch, 64);
8581 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8582 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8583 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8584 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8585 tdep->default_mask_address_p = 0;
8586 set_gdbarch_long_bit (gdbarch, 32);
8587 set_gdbarch_ptr_bit (gdbarch, 32);
8588 set_gdbarch_long_long_bit (gdbarch, 64);
8589 set_gdbarch_long_double_bit (gdbarch, 128);
8590 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8593 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8594 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8595 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8596 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8597 tdep->default_mask_address_p = 0;
8598 set_gdbarch_long_bit (gdbarch, 64);
8599 set_gdbarch_ptr_bit (gdbarch, 64);
8600 set_gdbarch_long_long_bit (gdbarch, 64);
8601 set_gdbarch_long_double_bit (gdbarch, 128);
8602 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8605 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8608 /* GCC creates a pseudo-section whose name specifies the size of
8609 longs, since -mlong32 or -mlong64 may be used independent of
8610 other options. How those options affect pointer sizes is ABI and
8611 architecture dependent, so use them to override the default sizes
8612 set by the ABI. This table shows the relationship between ABI,
8613 -mlongXX, and size of pointers:
8615 ABI -mlongXX ptr bits
8616 --- -------- --------
8630 Note that for o32 and eabi32, pointers are always 32 bits
8631 regardless of any -mlongXX option. For all others, pointers and
8632 longs are the same, as set by -mlongXX or set by defaults. */
8634 if (info.abfd != NULL)
8638 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
8641 set_gdbarch_long_bit (gdbarch, long_bit);
8645 case MIPS_ABI_EABI32:
8650 case MIPS_ABI_EABI64:
8651 set_gdbarch_ptr_bit (gdbarch, long_bit);
8654 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8659 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8660 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8663 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8664 flag in object files because to do so would make it impossible to
8665 link with libraries compiled without "-gp32". This is
8666 unnecessarily restrictive.
8668 We could solve this problem by adding "-gp32" multilibs to gcc,
8669 but to set this flag before gcc is built with such multilibs will
8670 break too many systems.''
8672 But even more unhelpfully, the default linker output target for
8673 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8674 for 64-bit programs - you need to change the ABI to change this,
8675 and not all gcc targets support that currently. Therefore using
8676 this flag to detect 32-bit mode would do the wrong thing given
8677 the current gcc - it would make GDB treat these 64-bit programs
8678 as 32-bit programs by default. */
8680 set_gdbarch_read_pc (gdbarch, mips_read_pc);
8681 set_gdbarch_write_pc (gdbarch, mips_write_pc);
8683 /* Add/remove bits from an address. The MIPS needs be careful to
8684 ensure that all 32 bit addresses are sign extended to 64 bits. */
8685 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
8687 /* Unwind the frame. */
8688 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
8689 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
8690 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
8692 /* Map debug register numbers onto internal register numbers. */
8693 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
8694 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
8695 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8696 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
8697 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8698 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
8700 /* MIPS version of CALL_DUMMY. */
8702 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8703 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code);
8704 set_gdbarch_frame_align (gdbarch, mips_frame_align);
8706 set_gdbarch_print_float_info (gdbarch, mips_print_float_info);
8708 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
8709 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
8710 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
8712 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8713 set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc);
8714 set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind);
8715 set_gdbarch_adjust_breakpoint_address (gdbarch,
8716 mips_adjust_breakpoint_address);
8718 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
8720 set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p);
8722 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
8723 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
8724 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
8726 set_gdbarch_register_type (gdbarch, mips_register_type);
8728 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
8730 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
8731 if (mips_abi == MIPS_ABI_N64)
8732 set_gdbarch_disassembler_options_implicit
8733 (gdbarch, (const char *) mips_disassembler_options_n64);
8734 else if (mips_abi == MIPS_ABI_N32)
8735 set_gdbarch_disassembler_options_implicit
8736 (gdbarch, (const char *) mips_disassembler_options_n32);
8738 set_gdbarch_disassembler_options_implicit
8739 (gdbarch, (const char *) mips_disassembler_options_o32);
8740 set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options);
8741 set_gdbarch_valid_disassembler_options (gdbarch,
8742 disassembler_options_mips ());
8744 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8745 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8746 need to all be folded into the target vector. Since they are
8747 being used as guards for target_stopped_by_watchpoint, why not have
8748 target_stopped_by_watchpoint return the type of watchpoint that the code
8750 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
8752 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
8754 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8755 to support MIPS16. This is a bad thing. Make sure not to do it
8756 if we have an OS ABI that actually supports shared libraries, since
8757 shared library support is more important. If we have an OS someday
8758 that supports both shared libraries and MIPS16, we'll have to find
8759 a better place for these.
8760 macro/2012-04-25: But that applies to return trampolines only and
8761 currently no MIPS OS ABI uses shared libraries that have them. */
8762 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
8764 set_gdbarch_single_step_through_delay (gdbarch,
8765 mips_single_step_through_delay);
8767 /* Virtual tables. */
8768 set_gdbarch_vbit_in_delta (gdbarch, 1);
8770 mips_register_g_packet_guesses (gdbarch);
8772 /* Hook in OS ABI-specific overrides, if they have been registered. */
8773 info.tdesc_data = tdesc_data;
8774 gdbarch_init_osabi (info, gdbarch);
8776 /* The hook may have adjusted num_regs, fetch the final value and
8777 set pc_regnum and sp_regnum now that it has been fixed. */
8778 num_regs = gdbarch_num_regs (gdbarch);
8779 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
8780 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8782 /* Unwind the frame. */
8783 dwarf2_append_unwinders (gdbarch);
8784 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
8785 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
8786 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind);
8787 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
8788 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
8789 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
8790 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
8791 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer);
8792 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
8796 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
8797 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
8799 /* Override the normal target description methods to handle our
8800 dual real and pseudo registers. */
8801 set_gdbarch_register_name (gdbarch, mips_register_name);
8802 set_gdbarch_register_reggroup_p (gdbarch,
8803 mips_tdesc_register_reggroup_p);
8805 num_regs = gdbarch_num_regs (gdbarch);
8806 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8807 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
8808 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8811 /* Add ABI-specific aliases for the registers. */
8812 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
8813 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
8814 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
8815 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
8817 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
8818 user_reg_add (gdbarch, mips_o32_aliases[i].name,
8819 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
8821 /* Add some other standard aliases. */
8822 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
8823 user_reg_add (gdbarch, mips_register_aliases[i].name,
8824 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
8826 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)
8827 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,
8828 value_of_mips_user_reg,
8829 &mips_numeric_register_aliases[i].regnum);
8835 mips_abi_update (const char *ignore_args,
8836 int from_tty, struct cmd_list_element *c)
8838 struct gdbarch_info info;
8840 /* Force the architecture to update, and (if it's a MIPS architecture)
8841 mips_gdbarch_init will take care of the rest. */
8842 gdbarch_info_init (&info);
8843 gdbarch_update_p (info);
8846 /* Print out which MIPS ABI is in use. */
8849 show_mips_abi (struct ui_file *file,
8851 struct cmd_list_element *ignored_cmd,
8852 const char *ignored_value)
8854 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
8857 "The MIPS ABI is unknown because the current architecture "
8861 enum mips_abi global_abi = global_mips_abi ();
8862 enum mips_abi actual_abi = mips_abi (target_gdbarch ());
8863 const char *actual_abi_str = mips_abi_strings[actual_abi];
8865 if (global_abi == MIPS_ABI_UNKNOWN)
8868 "The MIPS ABI is set automatically (currently \"%s\").\n",
8870 else if (global_abi == actual_abi)
8873 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8877 /* Probably shouldn't happen... */
8878 fprintf_filtered (file,
8879 "The (auto detected) MIPS ABI \"%s\" is in use "
8880 "even though the user setting was \"%s\".\n",
8881 actual_abi_str, mips_abi_strings[global_abi]);
8886 /* Print out which MIPS compressed ISA encoding is used. */
8889 show_mips_compression (struct ui_file *file, int from_tty,
8890 struct cmd_list_element *c, const char *value)
8892 fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"),
8896 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8899 mips_fpu_type_str (enum mips_fpu_type fpu_type)
8905 case MIPS_FPU_SINGLE:
8907 case MIPS_FPU_DOUBLE:
8915 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
8917 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8921 int ef_mips_32bitmode;
8922 /* Determine the ISA. */
8923 switch (tdep->elf_flags & EF_MIPS_ARCH)
8941 /* Determine the size of a pointer. */
8942 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
8943 fprintf_unfiltered (file,
8944 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8946 fprintf_unfiltered (file,
8947 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8949 fprintf_unfiltered (file,
8950 "mips_dump_tdep: ef_mips_arch = %d\n",
8952 fprintf_unfiltered (file,
8953 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8954 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
8955 fprintf_unfiltered (file,
8957 "mips_mask_address_p() %d (default %d)\n",
8958 mips_mask_address_p (tdep),
8959 tdep->default_mask_address_p);
8961 fprintf_unfiltered (file,
8962 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8963 MIPS_DEFAULT_FPU_TYPE,
8964 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE));
8965 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
8966 MIPS_EABI (gdbarch));
8967 fprintf_unfiltered (file,
8968 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8969 MIPS_FPU_TYPE (gdbarch),
8970 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch)));
8974 _initialize_mips_tdep (void)
8976 static struct cmd_list_element *mipsfpulist = NULL;
8978 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
8979 if (MIPS_ABI_LAST + 1
8980 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
8981 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
8983 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
8985 mips_pdr_data = register_objfile_data ();
8987 /* Create feature sets with the appropriate properties. The values
8988 are not important. */
8989 mips_tdesc_gp32 = allocate_target_description ();
8990 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
8992 mips_tdesc_gp64 = allocate_target_description ();
8993 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
8995 /* Add root prefix command for all "set mips"/"show mips" commands. */
8996 add_prefix_cmd ("mips", no_class, set_mips_command,
8997 _("Various MIPS specific commands."),
8998 &setmipscmdlist, "set mips ", 0, &setlist);
9000 add_prefix_cmd ("mips", no_class, show_mips_command,
9001 _("Various MIPS specific commands."),
9002 &showmipscmdlist, "show mips ", 0, &showlist);
9004 /* Allow the user to override the ABI. */
9005 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
9006 &mips_abi_string, _("\
9007 Set the MIPS ABI used by this program."), _("\
9008 Show the MIPS ABI used by this program."), _("\
9009 This option can be set to one of:\n\
9010 auto - the default ABI associated with the current binary\n\
9019 &setmipscmdlist, &showmipscmdlist);
9021 /* Allow the user to set the ISA to assume for compressed code if ELF
9022 file flags don't tell or there is no program file selected. This
9023 setting is updated whenever unambiguous ELF file flags are interpreted,
9024 and carried over to subsequent sessions. */
9025 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings,
9026 &mips_compression_string, _("\
9027 Set the compressed ISA encoding used by MIPS code."), _("\
9028 Show the compressed ISA encoding used by MIPS code."), _("\
9029 Select the compressed ISA encoding used in functions that have no symbol\n\
9030 information available. The encoding can be set to either of:\n\
9033 and is updated automatically from ELF file flags if available."),
9035 show_mips_compression,
9036 &setmipscmdlist, &showmipscmdlist);
9038 /* Let the user turn off floating point and set the fence post for
9039 heuristic_proc_start. */
9041 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
9042 _("Set use of MIPS floating-point coprocessor."),
9043 &mipsfpulist, "set mipsfpu ", 0, &setlist);
9044 add_cmd ("single", class_support, set_mipsfpu_single_command,
9045 _("Select single-precision MIPS floating-point coprocessor."),
9047 add_cmd ("double", class_support, set_mipsfpu_double_command,
9048 _("Select double-precision MIPS floating-point coprocessor."),
9050 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
9051 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
9052 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
9053 add_cmd ("none", class_support, set_mipsfpu_none_command,
9054 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
9055 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
9056 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
9057 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
9058 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
9059 _("Select MIPS floating-point coprocessor automatically."),
9061 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
9062 _("Show current use of MIPS floating-point coprocessor target."),
9065 /* We really would like to have both "0" and "unlimited" work, but
9066 command.c doesn't deal with that. So make it a var_zinteger
9067 because the user can always use "999999" or some such for unlimited. */
9068 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
9069 &heuristic_fence_post, _("\
9070 Set the distance searched for the start of a function."), _("\
9071 Show the distance searched for the start of a function."), _("\
9072 If you are debugging a stripped executable, GDB needs to search through the\n\
9073 program for the start of a function. This command sets the distance of the\n\
9074 search. The only need to set it is when debugging a stripped executable."),
9075 reinit_frame_cache_sfunc,
9076 NULL, /* FIXME: i18n: The distance searched for
9077 the start of a function is %s. */
9078 &setlist, &showlist);
9080 /* Allow the user to control whether the upper bits of 64-bit
9081 addresses should be zeroed. */
9082 add_setshow_auto_boolean_cmd ("mask-address", no_class,
9083 &mask_address_var, _("\
9084 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9085 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9086 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9087 allow GDB to determine the correct value."),
9088 NULL, show_mask_address,
9089 &setmipscmdlist, &showmipscmdlist);
9091 /* Allow the user to control the size of 32 bit registers within the
9092 raw remote packet. */
9093 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
9094 &mips64_transfers_32bit_regs_p, _("\
9095 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9097 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9099 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9100 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9101 64 bits for others. Use \"off\" to disable compatibility mode"),
9102 set_mips64_transfers_32bit_regs,
9103 NULL, /* FIXME: i18n: Compatibility with 64-bit
9104 MIPS target that transfers 32-bit
9105 quantities is %s. */
9106 &setlist, &showlist);
9108 /* Debug this files internals. */
9109 add_setshow_zuinteger_cmd ("mips", class_maintenance,
9111 Set mips debugging."), _("\
9112 Show mips debugging."), _("\
9113 When non-zero, mips specific debugging is enabled."),
9115 NULL, /* FIXME: i18n: Mips debugging is
9117 &setdebuglist, &showdebuglist);