1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE = 4,
57 MIPS_FPU_DOUBLE_REGSIZE = 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string;
76 static const char *mips_abi_strings[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto[] = "auto";
98 static const char size_32[] = "32";
99 static const char size_64[] = "64";
101 static const char *size_enums[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE /* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto = 1;
123 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
125 static int mips_debug = 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi;
135 enum mips_abi found_abi;
136 enum mips_fpu_type mips_fpu_type;
137 int mips_last_arg_regnum;
138 int mips_last_fp_arg_regnum;
139 int mips_default_saved_regsize;
140 int mips_fp_register_double;
141 int mips_default_stack_argsize;
142 int gdb_target_is_mips64;
143 int default_mask_address_p;
145 enum gdb_osabi osabi;
148 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
149 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
151 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
153 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
155 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
159 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
161 static const char *mips_saved_regsize_string = size_auto;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string == size_auto)
169 return MIPS_DEFAULT_SAVED_REGSIZE;
170 else if (mips_saved_regsize_string == size_64)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* Macros for setting and testing a bit in a minimal symbol that
177 marks it as 16-bit function. The MSB of the minimal symbol's
178 "info" field is used for this purpose. This field is already
179 being used to store the symbol size, so the assumption is
180 that the symbol size cannot exceed 2^31.
182 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
183 i.e. refers to a 16-bit function, and sets a "special" bit in a
184 minimal symbol to mark it as a 16-bit function
186 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
187 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
188 the "info" field with the "special" bit masked out */
190 #define MSYMBOL_IS_SPECIAL(msym) \
191 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
192 #define MSYMBOL_SIZE(msym) \
193 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
196 mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
198 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16)
200 MSYMBOL_INFO (msym) = (char *)
201 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
202 SYMBOL_VALUE_ADDRESS (msym) |= 1;
206 /* XFER a value from the big/little/left end of the register.
207 Depending on the size of the value it might occupy the entire
208 register or just part of it. Make an allowance for this, aligning
209 things accordingly. */
212 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
213 enum bfd_endian endian, bfd_byte *in, const bfd_byte *out,
216 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
218 /* Need to transfer the left or right part of the register, based on
219 the targets byte order. */
223 reg_offset = REGISTER_RAW_SIZE (reg_num) - length;
225 case BFD_ENDIAN_LITTLE:
228 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
232 internal_error (__FILE__, __LINE__, "bad switch");
235 fprintf_unfiltered (gdb_stderr,
236 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
237 reg_num, reg_offset, buf_offset, length);
238 if (mips_debug && out != NULL)
241 fprintf_unfiltered (gdb_stdlog, "out ");
242 for (i = 0; i < length; i++)
243 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
246 regcache_raw_read_part (regcache, reg_num, reg_offset, length, in + buf_offset);
248 regcache_raw_write_part (regcache, reg_num, reg_offset, length, out + buf_offset);
249 if (mips_debug && in != NULL)
252 fprintf_unfiltered (gdb_stdlog, "in ");
253 for (i = 0; i < length; i++)
254 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
257 fprintf_unfiltered (gdb_stdlog, "\n");
260 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
261 compatiblity mode. A return value of 1 means that we have
262 physical 64-bit registers, but should treat them as 32-bit registers. */
265 mips2_fp_compat (void)
267 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
269 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
273 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
274 in all the places we deal with FP registers. PR gdb/413. */
275 /* Otherwise check the FR bit in the status register - it controls
276 the FP compatiblity mode. If it is clear we are in compatibility
278 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
285 /* Indicate that the ABI makes use of double-precision registers
286 provided by the FPU (rather than combining pairs of registers to
287 form double-precision values). Do not use "TARGET_IS_MIPS64" to
288 determine if the ABI is using double-precision registers. See also
290 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
292 /* The amount of space reserved on the stack for registers. This is
293 different to MIPS_SAVED_REGSIZE as it determines the alignment of
294 data allocated after the registers have run out. */
296 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
298 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
300 static const char *mips_stack_argsize_string = size_auto;
303 mips_stack_argsize (void)
305 if (mips_stack_argsize_string == size_auto)
306 return MIPS_DEFAULT_STACK_ARGSIZE;
307 else if (mips_stack_argsize_string == size_64)
309 else /* if (mips_stack_argsize_string == size_32) */
313 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
315 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
317 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
319 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
321 static void mips_print_register (int, int);
323 static mips_extra_func_info_t
324 heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int);
326 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
328 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
330 static int mips_set_processor_type (char *);
332 static void mips_show_processor_type_command (char *, int);
334 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
336 static mips_extra_func_info_t
337 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame);
339 static CORE_ADDR after_prologue (CORE_ADDR pc,
340 mips_extra_func_info_t proc_desc);
342 static void mips_read_fp_register_single (int regno, char *rare_buffer);
343 static void mips_read_fp_register_double (int regno, char *rare_buffer);
345 static struct type *mips_float_register_type (void);
346 static struct type *mips_double_register_type (void);
348 /* This value is the model of MIPS in use. It is derived from the value
349 of the PrID register. */
351 char *mips_processor_type;
353 char *tmp_mips_processor_type;
355 /* The list of available "set mips " and "show mips " commands */
357 static struct cmd_list_element *setmipscmdlist = NULL;
358 static struct cmd_list_element *showmipscmdlist = NULL;
360 /* A set of original names, to be used when restoring back to generic
361 registers from a specific set. */
363 char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
364 char **mips_processor_reg_names = mips_generic_reg_names;
367 mips_register_name (int i)
369 return mips_processor_reg_names[i];
372 /* Names of IDT R3041 registers. */
374 char *mips_r3041_reg_names[] = {
375 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
376 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
377 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
378 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
379 "sr", "lo", "hi", "bad", "cause","pc",
380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
384 "fsr", "fir", "fp", "",
385 "", "", "bus", "ccfg", "", "", "", "",
386 "", "", "port", "cmp", "", "", "epc", "prid",
389 /* Names of IDT R3051 registers. */
391 char *mips_r3051_reg_names[] = {
392 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
393 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
394 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
395 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
396 "sr", "lo", "hi", "bad", "cause","pc",
397 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
398 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
399 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
400 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
401 "fsr", "fir", "fp", "",
402 "inx", "rand", "elo", "", "ctxt", "", "", "",
403 "", "", "ehi", "", "", "", "epc", "prid",
406 /* Names of IDT R3081 registers. */
408 char *mips_r3081_reg_names[] = {
409 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
410 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
411 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
412 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
413 "sr", "lo", "hi", "bad", "cause","pc",
414 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
415 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
416 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
417 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
418 "fsr", "fir", "fp", "",
419 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
420 "", "", "ehi", "", "", "", "epc", "prid",
423 /* Names of LSI 33k registers. */
425 char *mips_lsi33k_reg_names[] = {
426 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
427 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
428 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
429 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
430 "epc", "hi", "lo", "sr", "cause","badvaddr",
431 "dcic", "bpc", "bda", "", "", "", "", "",
432 "", "", "", "", "", "", "", "",
433 "", "", "", "", "", "", "", "",
434 "", "", "", "", "", "", "", "",
436 "", "", "", "", "", "", "", "",
437 "", "", "", "", "", "", "", "",
443 } mips_processor_type_table[] = {
444 { "generic", mips_generic_reg_names },
445 { "r3041", mips_r3041_reg_names },
446 { "r3051", mips_r3051_reg_names },
447 { "r3071", mips_r3081_reg_names },
448 { "r3081", mips_r3081_reg_names },
449 { "lsi33k", mips_lsi33k_reg_names },
457 /* Table to translate MIPS16 register field to actual register number. */
458 static int mips16_to_32_reg[8] =
459 {16, 17, 2, 3, 4, 5, 6, 7};
461 /* Heuristic_proc_start may hunt through the text section for a long
462 time across a 2400 baud serial line. Allows the user to limit this
465 static unsigned int heuristic_fence_post = 0;
467 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
468 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
469 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
470 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
471 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
472 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
473 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
474 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
475 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
476 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
477 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
478 this will corrupt pdr.iline. Fortunately we don't use it. */
479 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
480 #define _PROC_MAGIC_ 0x0F0F0F0F
481 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
482 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
484 struct linked_proc_info
486 struct mips_extra_func_info info;
487 struct linked_proc_info *next;
489 *linked_proc_desc_table = NULL;
492 mips_print_extra_frame_info (struct frame_info *fi)
496 && fi->extra_info->proc_desc
497 && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS)
498 printf_filtered (" frame pointer is at %s+%s\n",
499 REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg),
500 paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
503 /* Number of bytes of storage in the actual machine representation for
504 register N. NOTE: This indirectly defines the register size
505 transfered by the GDB protocol. */
507 static int mips64_transfers_32bit_regs_p = 0;
510 mips_register_raw_size (int reg_nr)
512 if (mips64_transfers_32bit_regs_p)
513 return REGISTER_VIRTUAL_SIZE (reg_nr);
514 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
515 && FP_REGISTER_DOUBLE)
516 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
523 /* Convert between RAW and VIRTUAL registers. The RAW register size
524 defines the remote-gdb packet. */
527 mips_register_convertible (int reg_nr)
529 if (mips64_transfers_32bit_regs_p)
532 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
536 mips_register_convert_to_virtual (int n, struct type *virtual_type,
537 char *raw_buf, char *virt_buf)
539 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
541 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
542 TYPE_LENGTH (virtual_type));
546 TYPE_LENGTH (virtual_type));
550 mips_register_convert_to_raw (struct type *virtual_type, int n,
551 char *virt_buf, char *raw_buf)
553 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
554 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
555 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
557 TYPE_LENGTH (virtual_type));
561 TYPE_LENGTH (virtual_type));
565 mips_register_convert_to_type (int regnum, struct type *type, char *buffer)
567 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
568 && REGISTER_RAW_SIZE (regnum) == 4
569 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
570 && TYPE_CODE(type) == TYPE_CODE_FLT
571 && TYPE_LENGTH(type) == 8)
574 memcpy (temp, ((char *)(buffer))+4, 4);
575 memcpy (((char *)(buffer))+4, (buffer), 4);
576 memcpy (((char *)(buffer)), temp, 4);
581 mips_register_convert_from_type (int regnum, struct type *type, char *buffer)
583 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
584 && REGISTER_RAW_SIZE (regnum) == 4
585 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
586 && TYPE_CODE(type) == TYPE_CODE_FLT
587 && TYPE_LENGTH(type) == 8)
590 memcpy (temp, ((char *)(buffer))+4, 4);
591 memcpy (((char *)(buffer))+4, (buffer), 4);
592 memcpy (((char *)(buffer)), temp, 4);
596 /* Return the GDB type object for the "standard" data type
597 of data in register REG.
599 Note: kevinb/2002-08-01: The definition below should faithfully
600 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
601 definitions found in config/mips/tm-*.h. I'm concerned about
602 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
603 though. In some cases FP_REGNUM is in this range, and I doubt
604 that this code is correct for the 64-bit case. */
607 mips_register_virtual_type (int reg)
609 if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32)
611 /* Floating point registers... */
612 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
613 return builtin_type_ieee_double_big;
615 return builtin_type_ieee_double_little;
617 else if (reg == PS_REGNUM /* CR */)
618 return builtin_type_uint32;
619 else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM)
620 return builtin_type_uint32;
623 /* Everything else...
624 Return type appropriate for width of register. */
625 if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64))
626 return builtin_type_uint64;
628 return builtin_type_uint32;
632 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
637 return ADDR_BITS_REMOVE (read_register (SP_REGNUM));
640 /* Should the upper word of 64-bit addresses be zeroed? */
641 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
644 mips_mask_address_p (void)
646 switch (mask_address_var)
648 case AUTO_BOOLEAN_TRUE:
650 case AUTO_BOOLEAN_FALSE:
653 case AUTO_BOOLEAN_AUTO:
654 return MIPS_DEFAULT_MASK_ADDRESS_P;
656 internal_error (__FILE__, __LINE__,
657 "mips_mask_address_p: bad switch");
663 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
665 switch (mask_address_var)
667 case AUTO_BOOLEAN_TRUE:
668 printf_filtered ("The 32 bit mips address mask is enabled\n");
670 case AUTO_BOOLEAN_FALSE:
671 printf_filtered ("The 32 bit mips address mask is disabled\n");
673 case AUTO_BOOLEAN_AUTO:
674 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
675 mips_mask_address_p () ? "enabled" : "disabled");
678 internal_error (__FILE__, __LINE__,
679 "show_mask_address: bad switch");
684 /* Should call_function allocate stack space for a struct return? */
687 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
689 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
693 mips_n32n64_use_struct_convention (int gcc_p, struct type *type)
695 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
699 mips_o32_use_struct_convention (int gcc_p, struct type *type)
701 return 1; /* Structures are returned by ref in extra arg0. */
704 /* Should call_function pass struct by reference?
705 For each architecture, structs are passed either by
706 value or by reference, depending on their size. */
709 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
711 enum type_code typecode = TYPE_CODE (check_typedef (type));
712 int len = TYPE_LENGTH (check_typedef (type));
714 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
715 return (len > MIPS_SAVED_REGSIZE);
721 mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type)
723 return 0; /* Assumption: N32/N64 never passes struct by ref. */
727 mips_o32_reg_struct_has_addr (int gcc_p, struct type *type)
729 return 0; /* Assumption: O32/O64 never passes struct by ref. */
732 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
735 pc_is_mips16 (bfd_vma memaddr)
737 struct minimal_symbol *sym;
739 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
740 if (IS_MIPS16_ADDR (memaddr))
743 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
744 the high bit of the info field. Use this to decide if the function is
745 MIPS16 or normal MIPS. */
746 sym = lookup_minimal_symbol_by_pc (memaddr);
748 return MSYMBOL_IS_SPECIAL (sym);
753 /* MIPS believes that the PC has a sign extended value. Perhaphs the
754 all registers should be sign extended for simplicity? */
757 mips_read_pc (ptid_t ptid)
759 return read_signed_register_pid (PC_REGNUM, ptid);
762 /* This returns the PC of the first inst after the prologue. If we can't
763 find the prologue, then return 0. */
766 after_prologue (CORE_ADDR pc,
767 mips_extra_func_info_t proc_desc)
769 struct symtab_and_line sal;
770 CORE_ADDR func_addr, func_end;
772 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
773 to read the stack pointer from the current machine state, because
774 the current machine state has nothing to do with the information
775 we need from the proc_desc; and the process may or may not exist
778 proc_desc = find_proc_desc (pc, NULL, 0);
782 /* If function is frameless, then we need to do it the hard way. I
783 strongly suspect that frameless always means prologueless... */
784 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
785 && PROC_FRAME_OFFSET (proc_desc) == 0)
789 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
790 return 0; /* Unknown */
792 sal = find_pc_line (func_addr, 0);
794 if (sal.end < func_end)
797 /* The line after the prologue is after the end of the function. In this
798 case, tell the caller to find the prologue the hard way. */
803 /* Decode a MIPS32 instruction that saves a register in the stack, and
804 set the appropriate bit in the general register mask or float register mask
805 to indicate which register is saved. This is a helper function
806 for mips_find_saved_regs. */
809 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
810 unsigned long *float_mask)
814 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
815 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
816 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
818 /* It might be possible to use the instruction to
819 find the offset, rather than the code below which
820 is based on things being in a certain order in the
821 frame, but figuring out what the instruction's offset
822 is relative to might be a little tricky. */
823 reg = (inst & 0x001f0000) >> 16;
824 *gen_mask |= (1 << reg);
826 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
827 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
828 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
831 reg = ((inst & 0x001f0000) >> 16);
832 *float_mask |= (1 << reg);
836 /* Decode a MIPS16 instruction that saves a register in the stack, and
837 set the appropriate bit in the general register or float register mask
838 to indicate which register is saved. This is a helper function
839 for mips_find_saved_regs. */
842 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
844 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
846 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
847 *gen_mask |= (1 << reg);
849 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
851 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
852 *gen_mask |= (1 << reg);
854 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
855 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
856 *gen_mask |= (1 << RA_REGNUM);
860 /* Fetch and return instruction from the specified location. If the PC
861 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
864 mips_fetch_instruction (CORE_ADDR addr)
866 char buf[MIPS_INSTLEN];
870 if (pc_is_mips16 (addr))
872 instlen = MIPS16_INSTLEN;
873 addr = UNMAKE_MIPS16_ADDR (addr);
876 instlen = MIPS_INSTLEN;
877 status = read_memory_nobpt (addr, buf, instlen);
879 memory_error (status, addr);
880 return extract_unsigned_integer (buf, instlen);
884 /* These the fields of 32 bit mips instructions */
885 #define mips32_op(x) (x >> 26)
886 #define itype_op(x) (x >> 26)
887 #define itype_rs(x) ((x >> 21) & 0x1f)
888 #define itype_rt(x) ((x >> 16) & 0x1f)
889 #define itype_immediate(x) (x & 0xffff)
891 #define jtype_op(x) (x >> 26)
892 #define jtype_target(x) (x & 0x03ffffff)
894 #define rtype_op(x) (x >> 26)
895 #define rtype_rs(x) ((x >> 21) & 0x1f)
896 #define rtype_rt(x) ((x >> 16) & 0x1f)
897 #define rtype_rd(x) ((x >> 11) & 0x1f)
898 #define rtype_shamt(x) ((x >> 6) & 0x1f)
899 #define rtype_funct(x) (x & 0x3f)
902 mips32_relative_offset (unsigned long inst)
905 x = itype_immediate (inst);
906 if (x & 0x8000) /* sign bit set */
908 x |= 0xffff0000; /* sign extension */
914 /* Determine whate to set a single step breakpoint while considering
917 mips32_next_pc (CORE_ADDR pc)
921 inst = mips_fetch_instruction (pc);
922 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
924 if (itype_op (inst) >> 2 == 5)
925 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
927 op = (itype_op (inst) & 0x03);
942 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
943 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
945 int tf = itype_rt (inst) & 0x01;
946 int cnum = itype_rt (inst) >> 2;
947 int fcrcs = read_signed_register (FCRCS_REGNUM);
948 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
950 if (((cond >> cnum) & 0x01) == tf)
951 pc += mips32_relative_offset (inst) + 4;
956 pc += 4; /* Not a branch, next instruction is easy */
959 { /* This gets way messy */
961 /* Further subdivide into SPECIAL, REGIMM and other */
962 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
964 case 0: /* SPECIAL */
965 op = rtype_funct (inst);
970 /* Set PC to that address */
971 pc = read_signed_register (rtype_rs (inst));
977 break; /* end SPECIAL */
980 op = itype_rt (inst); /* branch condition */
985 case 16: /* BLTZAL */
986 case 18: /* BLTZALL */
988 if (read_signed_register (itype_rs (inst)) < 0)
989 pc += mips32_relative_offset (inst) + 4;
991 pc += 8; /* after the delay slot */
995 case 17: /* BGEZAL */
996 case 19: /* BGEZALL */
997 greater_equal_branch:
998 if (read_signed_register (itype_rs (inst)) >= 0)
999 pc += mips32_relative_offset (inst) + 4;
1001 pc += 8; /* after the delay slot */
1003 /* All of the other instructions in the REGIMM category */
1008 break; /* end REGIMM */
1013 reg = jtype_target (inst) << 2;
1014 /* Upper four bits get never changed... */
1015 pc = reg + ((pc + 4) & 0xf0000000);
1018 /* FIXME case JALX : */
1021 reg = jtype_target (inst) << 2;
1022 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
1023 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1025 break; /* The new PC will be alternate mode */
1026 case 4: /* BEQ, BEQL */
1028 if (read_signed_register (itype_rs (inst)) ==
1029 read_signed_register (itype_rt (inst)))
1030 pc += mips32_relative_offset (inst) + 4;
1034 case 5: /* BNE, BNEL */
1036 if (read_signed_register (itype_rs (inst)) !=
1037 read_signed_register (itype_rt (inst)))
1038 pc += mips32_relative_offset (inst) + 4;
1042 case 6: /* BLEZ, BLEZL */
1044 if (read_signed_register (itype_rs (inst) <= 0))
1045 pc += mips32_relative_offset (inst) + 4;
1051 greater_branch: /* BGTZ, BGTZL */
1052 if (read_signed_register (itype_rs (inst) > 0))
1053 pc += mips32_relative_offset (inst) + 4;
1060 } /* mips32_next_pc */
1062 /* Decoding the next place to set a breakpoint is irregular for the
1063 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1064 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1065 We dont want to set a single step instruction on the extend instruction
1069 /* Lots of mips16 instruction formats */
1070 /* Predicting jumps requires itype,ritype,i8type
1071 and their extensions extItype,extritype,extI8type
1073 enum mips16_inst_fmts
1075 itype, /* 0 immediate 5,10 */
1076 ritype, /* 1 5,3,8 */
1077 rrtype, /* 2 5,3,3,5 */
1078 rritype, /* 3 5,3,3,5 */
1079 rrrtype, /* 4 5,3,3,3,2 */
1080 rriatype, /* 5 5,3,3,1,4 */
1081 shifttype, /* 6 5,3,3,3,2 */
1082 i8type, /* 7 5,3,8 */
1083 i8movtype, /* 8 5,3,3,5 */
1084 i8mov32rtype, /* 9 5,3,5,3 */
1085 i64type, /* 10 5,3,8 */
1086 ri64type, /* 11 5,3,3,5 */
1087 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1088 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1089 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1090 extRRItype, /* 15 5,5,5,5,3,3,5 */
1091 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1092 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1093 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1094 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1095 extRi64type, /* 20 5,6,5,5,3,3,5 */
1096 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1098 /* I am heaping all the fields of the formats into one structure and
1099 then, only the fields which are involved in instruction extension */
1103 unsigned int regx; /* Function in i8 type */
1108 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1109 for the bits which make up the immediatate extension. */
1112 extended_offset (unsigned int extension)
1115 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1117 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1119 value |= extension & 0x01f; /* extract 4:0 */
1123 /* Only call this function if you know that this is an extendable
1124 instruction, It wont malfunction, but why make excess remote memory references?
1125 If the immediate operands get sign extended or somthing, do it after
1126 the extension is performed.
1128 /* FIXME: Every one of these cases needs to worry about sign extension
1129 when the offset is to be used in relative addressing */
1133 fetch_mips_16 (CORE_ADDR pc)
1136 pc &= 0xfffffffe; /* clear the low order bit */
1137 target_read_memory (pc, buf, 2);
1138 return extract_unsigned_integer (buf, 2);
1142 unpack_mips16 (CORE_ADDR pc,
1143 unsigned int extension,
1145 enum mips16_inst_fmts insn_format,
1146 struct upk_mips16 *upk)
1151 switch (insn_format)
1158 value = extended_offset (extension);
1159 value = value << 11; /* rom for the original value */
1160 value |= inst & 0x7ff; /* eleven bits from instruction */
1164 value = inst & 0x7ff;
1165 /* FIXME : Consider sign extension */
1174 { /* A register identifier and an offset */
1175 /* Most of the fields are the same as I type but the
1176 immediate value is of a different length */
1180 value = extended_offset (extension);
1181 value = value << 8; /* from the original instruction */
1182 value |= inst & 0xff; /* eleven bits from instruction */
1183 regx = (extension >> 8) & 0x07; /* or i8 funct */
1184 if (value & 0x4000) /* test the sign bit , bit 26 */
1186 value &= ~0x3fff; /* remove the sign bit */
1192 value = inst & 0xff; /* 8 bits */
1193 regx = (inst >> 8) & 0x07; /* or i8 funct */
1194 /* FIXME: Do sign extension , this format needs it */
1195 if (value & 0x80) /* THIS CONFUSES ME */
1197 value &= 0xef; /* remove the sign bit */
1207 unsigned long value;
1208 unsigned int nexthalf;
1209 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1210 value = value << 16;
1211 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1219 internal_error (__FILE__, __LINE__,
1222 upk->offset = offset;
1229 add_offset_16 (CORE_ADDR pc, int offset)
1231 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1235 extended_mips16_next_pc (CORE_ADDR pc,
1236 unsigned int extension,
1239 int op = (insn >> 11);
1242 case 2: /* Branch */
1245 struct upk_mips16 upk;
1246 unpack_mips16 (pc, extension, insn, itype, &upk);
1247 offset = upk.offset;
1253 pc += (offset << 1) + 2;
1256 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1258 struct upk_mips16 upk;
1259 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1260 pc = add_offset_16 (pc, upk.offset);
1261 if ((insn >> 10) & 0x01) /* Exchange mode */
1262 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1269 struct upk_mips16 upk;
1271 unpack_mips16 (pc, extension, insn, ritype, &upk);
1272 reg = read_signed_register (upk.regx);
1274 pc += (upk.offset << 1) + 2;
1281 struct upk_mips16 upk;
1283 unpack_mips16 (pc, extension, insn, ritype, &upk);
1284 reg = read_signed_register (upk.regx);
1286 pc += (upk.offset << 1) + 2;
1291 case 12: /* I8 Formats btez btnez */
1293 struct upk_mips16 upk;
1295 unpack_mips16 (pc, extension, insn, i8type, &upk);
1296 /* upk.regx contains the opcode */
1297 reg = read_signed_register (24); /* Test register is 24 */
1298 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1299 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1300 /* pc = add_offset_16(pc,upk.offset) ; */
1301 pc += (upk.offset << 1) + 2;
1306 case 29: /* RR Formats JR, JALR, JALR-RA */
1308 struct upk_mips16 upk;
1309 /* upk.fmt = rrtype; */
1314 upk.regx = (insn >> 8) & 0x07;
1315 upk.regy = (insn >> 5) & 0x07;
1323 break; /* Function return instruction */
1329 break; /* BOGUS Guess */
1331 pc = read_signed_register (reg);
1338 /* This is an instruction extension. Fetch the real instruction
1339 (which follows the extension) and decode things based on
1343 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1356 mips16_next_pc (CORE_ADDR pc)
1358 unsigned int insn = fetch_mips_16 (pc);
1359 return extended_mips16_next_pc (pc, 0, insn);
1362 /* The mips_next_pc function supports single_step when the remote
1363 target monitor or stub is not developed enough to do a single_step.
1364 It works by decoding the current instruction and predicting where a
1365 branch will go. This isnt hard because all the data is available.
1366 The MIPS32 and MIPS16 variants are quite different */
1368 mips_next_pc (CORE_ADDR pc)
1371 return mips16_next_pc (pc);
1373 return mips32_next_pc (pc);
1376 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1379 Note: kevinb/2002-08-09: The only caller of this function is (and
1380 should remain) mips_frame_init_saved_regs(). In fact,
1381 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1382 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1383 functions should really be combined and now that there is only one
1384 caller, it should be straightforward. (Watch out for multiple returns
1388 mips_find_saved_regs (struct frame_info *fci)
1391 CORE_ADDR reg_position;
1392 /* r0 bit means kernel trap */
1394 /* What registers have been saved? Bitmasks. */
1395 unsigned long gen_mask, float_mask;
1396 mips_extra_func_info_t proc_desc;
1399 frame_saved_regs_zalloc (fci);
1401 /* If it is the frame for sigtramp, the saved registers are located
1402 in a sigcontext structure somewhere on the stack.
1403 If the stack layout for sigtramp changes we might have to change these
1404 constants and the companion fixup_sigtramp in mdebugread.c */
1405 #ifndef SIGFRAME_BASE
1406 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1407 above the sigtramp frame. */
1408 #define SIGFRAME_BASE MIPS_REGSIZE
1409 /* FIXME! Are these correct?? */
1410 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1411 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1412 #define SIGFRAME_FPREGSAVE_OFF \
1413 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1415 #ifndef SIGFRAME_REG_SIZE
1416 /* FIXME! Is this correct?? */
1417 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1419 if (fci->signal_handler_caller)
1421 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1423 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
1424 + ireg * SIGFRAME_REG_SIZE;
1425 fci->saved_regs[ireg] = reg_position;
1427 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1429 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
1430 + ireg * SIGFRAME_REG_SIZE;
1431 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1433 fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
1437 proc_desc = fci->extra_info->proc_desc;
1438 if (proc_desc == NULL)
1439 /* I'm not sure how/whether this can happen. Normally when we can't
1440 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1441 and set the saved_regs right away. */
1444 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1445 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1446 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1448 if ( /* In any frame other than the innermost or a frame interrupted by
1449 a signal, we assume that all registers have been saved.
1450 This assumes that all register saves in a function happen before
1451 the first function call. */
1452 (fci->next == NULL || fci->next->signal_handler_caller)
1454 /* In a dummy frame we know exactly where things are saved. */
1455 && !PROC_DESC_IS_DUMMY (proc_desc)
1457 /* Don't bother unless we are inside a function prologue. Outside the
1458 prologue, we know where everything is. */
1460 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
1462 /* Not sure exactly what kernel_trap means, but if it means
1463 the kernel saves the registers without a prologue doing it,
1464 we better not examine the prologue to see whether registers
1465 have been saved yet. */
1468 /* We need to figure out whether the registers that the proc_desc
1469 claims are saved have been saved yet. */
1473 /* Bitmasks; set if we have found a save for the register. */
1474 unsigned long gen_save_found = 0;
1475 unsigned long float_save_found = 0;
1478 /* If the address is odd, assume this is MIPS16 code. */
1479 addr = PROC_LOW_ADDR (proc_desc);
1480 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1482 /* Scan through this function's instructions preceding the current
1483 PC, and look for those that save registers. */
1484 while (addr < fci->pc)
1486 inst = mips_fetch_instruction (addr);
1487 if (pc_is_mips16 (addr))
1488 mips16_decode_reg_save (inst, &gen_save_found);
1490 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1493 gen_mask = gen_save_found;
1494 float_mask = float_save_found;
1497 /* Fill in the offsets for the registers which gen_mask says
1499 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1500 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1501 if (gen_mask & 0x80000000)
1503 fci->saved_regs[ireg] = reg_position;
1504 reg_position -= MIPS_SAVED_REGSIZE;
1507 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1508 of that normally used by gcc. Therefore, we have to fetch the first
1509 instruction of the function, and if it's an entry instruction that
1510 saves $s0 or $s1, correct their saved addresses. */
1511 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1513 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1514 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1517 int sreg_count = (inst >> 6) & 3;
1519 /* Check if the ra register was pushed on the stack. */
1520 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1522 reg_position -= MIPS_SAVED_REGSIZE;
1524 /* Check if the s0 and s1 registers were pushed on the stack. */
1525 for (reg = 16; reg < sreg_count + 16; reg++)
1527 fci->saved_regs[reg] = reg_position;
1528 reg_position -= MIPS_SAVED_REGSIZE;
1533 /* Fill in the offsets for the registers which float_mask says
1535 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
1537 /* Apparently, the freg_offset gives the offset to the first 64 bit
1540 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1541 designates the first saved 64 bit register.
1543 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1544 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1545 FREG_OFFSET, designates the address of the lower register of the
1546 register pair. Adjust the offset so that it designates the upper
1547 register of the pair -- i.e., the address of the first saved 32
1550 if (MIPS_SAVED_REGSIZE == 4)
1551 reg_position += MIPS_SAVED_REGSIZE;
1553 /* Fill in the offsets for the float registers which float_mask says
1555 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1556 if (float_mask & 0x80000000)
1558 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1559 reg_position -= MIPS_SAVED_REGSIZE;
1562 fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM];
1565 /* Set up the 'saved_regs' array. This is a data structure containing
1566 the addresses on the stack where each register has been saved, for
1567 each stack frame. Registers that have not been saved will have
1568 zero here. The stack pointer register is special: rather than the
1569 address where the stack register has been saved, saved_regs[SP_REGNUM]
1570 will have the actual value of the previous frame's stack register. */
1573 mips_frame_init_saved_regs (struct frame_info *frame)
1575 if (frame->saved_regs == NULL)
1577 mips_find_saved_regs (frame);
1579 frame->saved_regs[SP_REGNUM] = frame->frame;
1583 read_next_frame_reg (struct frame_info *fi, int regno)
1585 for (; fi; fi = fi->next)
1587 /* We have to get the saved sp from the sigcontext
1588 if it is a signal handler frame. */
1589 if (regno == SP_REGNUM && !fi->signal_handler_caller)
1593 if (fi->saved_regs == NULL)
1594 FRAME_INIT_SAVED_REGS (fi);
1595 if (fi->saved_regs[regno])
1596 return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE);
1599 return read_signed_register (regno);
1602 /* mips_addr_bits_remove - remove useless address bits */
1605 mips_addr_bits_remove (CORE_ADDR addr)
1607 if (GDB_TARGET_IS_MIPS64)
1609 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1611 /* This hack is a work-around for existing boards using
1612 PMON, the simulator, and any other 64-bit targets that
1613 doesn't have true 64-bit addressing. On these targets,
1614 the upper 32 bits of addresses are ignored by the
1615 hardware. Thus, the PC or SP are likely to have been
1616 sign extended to all 1s by instruction sequences that
1617 load 32-bit addresses. For example, a typical piece of
1618 code that loads an address is this:
1619 lui $r2, <upper 16 bits>
1620 ori $r2, <lower 16 bits>
1621 But the lui sign-extends the value such that the upper 32
1622 bits may be all 1s. The workaround is simply to mask off
1623 these bits. In the future, gcc may be changed to support
1624 true 64-bit addressing, and this masking will have to be
1626 addr &= (CORE_ADDR) 0xffffffff;
1629 else if (mips_mask_address_p ())
1631 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1632 masking off bits, instead, the actual target should be asking
1633 for the address to be converted to a valid pointer. */
1634 /* Even when GDB is configured for some 32-bit targets
1635 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1636 so CORE_ADDR is 64 bits. So we still have to mask off
1637 useless bits from addresses. */
1638 addr &= (CORE_ADDR) 0xffffffff;
1643 /* mips_software_single_step() is called just before we want to resume
1644 the inferior, if we want to single-step it but there is no hardware
1645 or kernel single-step support (MIPS on GNU/Linux for example). We find
1646 the target of the coming instruction and breakpoint it.
1648 single_step is also called just after the inferior stops. If we had
1649 set up a simulated single-step, we undo our damage. */
1652 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1654 static CORE_ADDR next_pc;
1655 typedef char binsn_quantum[BREAKPOINT_MAX];
1656 static binsn_quantum break_mem;
1659 if (insert_breakpoints_p)
1661 pc = read_register (PC_REGNUM);
1662 next_pc = mips_next_pc (pc);
1664 target_insert_breakpoint (next_pc, break_mem);
1667 target_remove_breakpoint (next_pc, break_mem);
1671 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1675 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
1676 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
1677 tmp = SKIP_TRAMPOLINE_CODE (pc);
1678 prev->pc = tmp ? tmp : pc;
1683 mips_frame_saved_pc (struct frame_info *frame)
1686 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
1687 /* We have to get the saved pc from the sigcontext
1688 if it is a signal handler frame. */
1689 int pcreg = frame->signal_handler_caller ? PC_REGNUM
1690 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1692 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1693 saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1695 saved_pc = read_next_frame_reg (frame, pcreg);
1697 return ADDR_BITS_REMOVE (saved_pc);
1700 static struct mips_extra_func_info temp_proc_desc;
1701 static CORE_ADDR temp_saved_regs[NUM_REGS];
1703 /* Set a register's saved stack address in temp_saved_regs. If an address
1704 has already been set for this register, do nothing; this way we will
1705 only recognize the first save of a given register in a function prologue.
1706 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1709 set_reg_offset (int regno, CORE_ADDR offset)
1711 if (temp_saved_regs[regno] == 0)
1712 temp_saved_regs[regno] = offset;
1716 /* Test whether the PC points to the return instruction at the
1717 end of a function. */
1720 mips_about_to_return (CORE_ADDR pc)
1722 if (pc_is_mips16 (pc))
1723 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1724 generates a "jr $ra"; other times it generates code to load
1725 the return address from the stack to an accessible register (such
1726 as $a3), then a "jr" using that register. This second case
1727 is almost impossible to distinguish from an indirect jump
1728 used for switch statements, so we don't even try. */
1729 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1731 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1735 /* This fencepost looks highly suspicious to me. Removing it also
1736 seems suspicious as it could affect remote debugging across serial
1740 heuristic_proc_start (CORE_ADDR pc)
1747 pc = ADDR_BITS_REMOVE (pc);
1749 fence = start_pc - heuristic_fence_post;
1753 if (heuristic_fence_post == UINT_MAX
1754 || fence < VM_MIN_ADDRESS)
1755 fence = VM_MIN_ADDRESS;
1757 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1759 /* search back for previous return */
1760 for (start_pc -= instlen;; start_pc -= instlen)
1761 if (start_pc < fence)
1763 /* It's not clear to me why we reach this point when
1764 stop_soon_quietly, but with this test, at least we
1765 don't print out warnings for every child forked (eg, on
1766 decstation). 22apr93 rich@cygnus.com. */
1767 if (!stop_soon_quietly)
1769 static int blurb_printed = 0;
1771 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1776 /* This actually happens frequently in embedded
1777 development, when you first connect to a board
1778 and your stack pointer and pc are nowhere in
1779 particular. This message needs to give people
1780 in that situation enough information to
1781 determine that it's no big deal. */
1782 printf_filtered ("\n\
1783 GDB is unable to find the start of the function at 0x%s\n\
1784 and thus can't determine the size of that function's stack frame.\n\
1785 This means that GDB may be unable to access that stack frame, or\n\
1786 the frames below it.\n\
1787 This problem is most likely caused by an invalid program counter or\n\
1789 However, if you think GDB should simply search farther back\n\
1790 from 0x%s for code which looks like the beginning of a\n\
1791 function, you can increase the range of the search using the `set\n\
1792 heuristic-fence-post' command.\n",
1793 paddr_nz (pc), paddr_nz (pc));
1800 else if (pc_is_mips16 (start_pc))
1802 unsigned short inst;
1804 /* On MIPS16, any one of the following is likely to be the
1805 start of a function:
1809 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1810 inst = mips_fetch_instruction (start_pc);
1811 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1812 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1813 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1814 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1816 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1817 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1822 else if (mips_about_to_return (start_pc))
1824 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1831 /* Fetch the immediate value from a MIPS16 instruction.
1832 If the previous instruction was an EXTEND, use it to extend
1833 the upper bits of the immediate value. This is a helper function
1834 for mips16_heuristic_proc_desc. */
1837 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1838 unsigned short inst, /* current instruction */
1839 int nbits, /* number of bits in imm field */
1840 int scale, /* scale factor to be applied to imm */
1841 int is_signed) /* is the imm field signed? */
1845 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1847 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1848 if (offset & 0x8000) /* check for negative extend */
1849 offset = 0 - (0x10000 - (offset & 0xffff));
1850 return offset | (inst & 0x1f);
1854 int max_imm = 1 << nbits;
1855 int mask = max_imm - 1;
1856 int sign_bit = max_imm >> 1;
1858 offset = inst & mask;
1859 if (is_signed && (offset & sign_bit))
1860 offset = 0 - (max_imm - offset);
1861 return offset * scale;
1866 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1867 stream from start_pc to limit_pc. */
1870 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1871 struct frame_info *next_frame, CORE_ADDR sp)
1874 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1875 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1876 unsigned inst = 0; /* current instruction */
1877 unsigned entry_inst = 0; /* the entry instruction */
1880 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1881 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1883 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1885 /* Save the previous instruction. If it's an EXTEND, we'll extract
1886 the immediate offset extension from it in mips16_get_imm. */
1889 /* Fetch and decode the instruction. */
1890 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1891 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1892 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1894 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1895 if (offset < 0) /* negative stack adjustment? */
1896 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
1898 /* Exit loop if a positive stack adjustment is found, which
1899 usually means that the stack cleanup code in the function
1900 epilogue is reached. */
1903 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1905 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1906 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1907 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1908 set_reg_offset (reg, sp + offset);
1910 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1912 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1913 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1914 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1915 set_reg_offset (reg, sp + offset);
1917 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1919 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1920 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1921 set_reg_offset (RA_REGNUM, sp + offset);
1923 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1925 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1926 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1927 set_reg_offset (RA_REGNUM, sp + offset);
1929 else if (inst == 0x673d) /* move $s1, $sp */
1932 PROC_FRAME_REG (&temp_proc_desc) = 17;
1934 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1936 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1937 frame_addr = sp + offset;
1938 PROC_FRAME_REG (&temp_proc_desc) = 17;
1939 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1941 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1943 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1944 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1945 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1946 set_reg_offset (reg, frame_addr + offset);
1948 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1950 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1951 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1952 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1953 set_reg_offset (reg, frame_addr + offset);
1955 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1956 entry_inst = inst; /* save for later processing */
1957 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1958 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
1961 /* The entry instruction is typically the first instruction in a function,
1962 and it stores registers at offsets relative to the value of the old SP
1963 (before the prologue). But the value of the sp parameter to this
1964 function is the new SP (after the prologue has been executed). So we
1965 can't calculate those offsets until we've seen the entire prologue,
1966 and can calculate what the old SP must have been. */
1967 if (entry_inst != 0)
1969 int areg_count = (entry_inst >> 8) & 7;
1970 int sreg_count = (entry_inst >> 6) & 3;
1972 /* The entry instruction always subtracts 32 from the SP. */
1973 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
1975 /* Now we can calculate what the SP must have been at the
1976 start of the function prologue. */
1977 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
1979 /* Check if a0-a3 were saved in the caller's argument save area. */
1980 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1982 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1983 set_reg_offset (reg, sp + offset);
1984 offset += MIPS_SAVED_REGSIZE;
1987 /* Check if the ra register was pushed on the stack. */
1989 if (entry_inst & 0x20)
1991 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
1992 set_reg_offset (RA_REGNUM, sp + offset);
1993 offset -= MIPS_SAVED_REGSIZE;
1996 /* Check if the s0 and s1 registers were pushed on the stack. */
1997 for (reg = 16; reg < sreg_count + 16; reg++)
1999 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2000 set_reg_offset (reg, sp + offset);
2001 offset -= MIPS_SAVED_REGSIZE;
2007 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2008 struct frame_info *next_frame, CORE_ADDR sp)
2011 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
2013 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2014 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
2015 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2016 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2018 unsigned long inst, high_word, low_word;
2021 /* Fetch the instruction. */
2022 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2024 /* Save some code by pre-extracting some useful fields. */
2025 high_word = (inst >> 16) & 0xffff;
2026 low_word = inst & 0xffff;
2027 reg = high_word & 0x1f;
2029 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2030 || high_word == 0x23bd /* addi $sp,$sp,-i */
2031 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2033 if (low_word & 0x8000) /* negative stack adjustment? */
2034 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
2036 /* Exit loop if a positive stack adjustment is found, which
2037 usually means that the stack cleanup code in the function
2038 epilogue is reached. */
2041 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2043 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2044 set_reg_offset (reg, sp + low_word);
2046 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2048 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2049 but the register size used is only 32 bits. Make the address
2050 for the saved register point to the lower 32 bits. */
2051 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2052 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
2054 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2056 /* Old gcc frame, r30 is virtual frame pointer. */
2057 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2058 frame_addr = sp + low_word;
2059 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2061 unsigned alloca_adjust;
2062 PROC_FRAME_REG (&temp_proc_desc) = 30;
2063 frame_addr = read_next_frame_reg (next_frame, 30);
2064 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2065 if (alloca_adjust > 0)
2067 /* FP > SP + frame_size. This may be because
2068 * of an alloca or somethings similar.
2069 * Fix sp to "pre-alloca" value, and try again.
2071 sp += alloca_adjust;
2076 /* move $30,$sp. With different versions of gas this will be either
2077 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2078 Accept any one of these. */
2079 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2081 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2082 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2084 unsigned alloca_adjust;
2085 PROC_FRAME_REG (&temp_proc_desc) = 30;
2086 frame_addr = read_next_frame_reg (next_frame, 30);
2087 alloca_adjust = (unsigned) (frame_addr - sp);
2088 if (alloca_adjust > 0)
2090 /* FP > SP + frame_size. This may be because
2091 * of an alloca or somethings similar.
2092 * Fix sp to "pre-alloca" value, and try again.
2094 sp += alloca_adjust;
2099 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2101 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2102 set_reg_offset (reg, frame_addr + low_word);
2107 static mips_extra_func_info_t
2108 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2109 struct frame_info *next_frame, int cur_frame)
2114 sp = read_next_frame_reg (next_frame, SP_REGNUM);
2120 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2121 memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2122 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2123 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2124 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2126 if (start_pc + 200 < limit_pc)
2127 limit_pc = start_pc + 200;
2128 if (pc_is_mips16 (start_pc))
2129 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2131 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2132 return &temp_proc_desc;
2135 struct mips_objfile_private
2141 /* Global used to communicate between non_heuristic_proc_desc and
2142 compare_pdr_entries within qsort (). */
2143 static bfd *the_bfd;
2146 compare_pdr_entries (const void *a, const void *b)
2148 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2149 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2153 else if (lhs == rhs)
2159 static mips_extra_func_info_t
2160 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2162 CORE_ADDR startaddr;
2163 mips_extra_func_info_t proc_desc;
2164 struct block *b = block_for_pc (pc);
2166 struct obj_section *sec;
2167 struct mips_objfile_private *priv;
2169 if (PC_IN_CALL_DUMMY (pc, 0, 0))
2172 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2174 *addrptr = startaddr;
2178 sec = find_pc_section (pc);
2181 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2183 /* Search the ".pdr" section generated by GAS. This includes most of
2184 the information normally found in ECOFF PDRs. */
2186 the_bfd = sec->objfile->obfd;
2188 && (the_bfd->format == bfd_object
2189 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2190 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2192 /* Right now GAS only outputs the address as a four-byte sequence.
2193 This means that we should not bother with this method on 64-bit
2194 targets (until that is fixed). */
2196 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2197 sizeof (struct mips_objfile_private));
2199 sec->objfile->obj_private = priv;
2201 else if (priv == NULL)
2205 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2206 sizeof (struct mips_objfile_private));
2208 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2211 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2212 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2214 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2215 priv->contents, 0, priv->size);
2217 /* In general, the .pdr section is sorted. However, in the
2218 presence of multiple code sections (and other corner cases)
2219 it can become unsorted. Sort it so that we can use a faster
2221 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2226 sec->objfile->obj_private = priv;
2230 if (priv->size != 0)
2236 high = priv->size / 32;
2242 mid = (low + high) / 2;
2244 ptr = priv->contents + mid * 32;
2245 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2246 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2247 SECT_OFF_TEXT (sec->objfile));
2248 if (pdr_pc == startaddr)
2250 if (pdr_pc > startaddr)
2255 while (low != high);
2259 struct symbol *sym = find_pc_function (pc);
2261 /* Fill in what we need of the proc_desc. */
2262 proc_desc = (mips_extra_func_info_t)
2263 obstack_alloc (&sec->objfile->psymbol_obstack,
2264 sizeof (struct mips_extra_func_info));
2265 PROC_LOW_ADDR (proc_desc) = startaddr;
2267 /* Only used for dummy frames. */
2268 PROC_HIGH_ADDR (proc_desc) = 0;
2270 PROC_FRAME_OFFSET (proc_desc)
2271 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2272 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2274 PROC_FRAME_ADJUST (proc_desc) = 0;
2275 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2277 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2279 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2281 PROC_FREG_OFFSET (proc_desc)
2282 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2283 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2285 proc_desc->pdr.isym = (long) sym;
2295 if (startaddr > BLOCK_START (b))
2297 /* This is the "pathological" case referred to in a comment in
2298 print_frame_info. It might be better to move this check into
2303 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
2305 /* If we never found a PDR for this function in symbol reading, then
2306 examine prologues to find the information. */
2309 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2310 if (PROC_FRAME_REG (proc_desc) == -1)
2320 static mips_extra_func_info_t
2321 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2323 mips_extra_func_info_t proc_desc;
2324 CORE_ADDR startaddr;
2326 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2330 /* IF this is the topmost frame AND
2331 * (this proc does not have debugging information OR
2332 * the PC is in the procedure prologue)
2333 * THEN create a "heuristic" proc_desc (by analyzing
2334 * the actual code) to replace the "official" proc_desc.
2336 if (next_frame == NULL)
2338 struct symtab_and_line val;
2339 struct symbol *proc_symbol =
2340 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2344 val = find_pc_line (BLOCK_START
2345 (SYMBOL_BLOCK_VALUE (proc_symbol)),
2347 val.pc = val.end ? val.end : pc;
2349 if (!proc_symbol || pc < val.pc)
2351 mips_extra_func_info_t found_heuristic =
2352 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2353 pc, next_frame, cur_frame);
2354 if (found_heuristic)
2355 proc_desc = found_heuristic;
2361 /* Is linked_proc_desc_table really necessary? It only seems to be used
2362 by procedure call dummys. However, the procedures being called ought
2363 to have their own proc_descs, and even if they don't,
2364 heuristic_proc_desc knows how to create them! */
2366 register struct linked_proc_info *link;
2368 for (link = linked_proc_desc_table; link; link = link->next)
2369 if (PROC_LOW_ADDR (&link->info) <= pc
2370 && PROC_HIGH_ADDR (&link->info) > pc)
2374 startaddr = heuristic_proc_start (pc);
2377 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2383 get_frame_pointer (struct frame_info *frame,
2384 mips_extra_func_info_t proc_desc)
2386 return ADDR_BITS_REMOVE (read_next_frame_reg (frame,
2387 PROC_FRAME_REG (proc_desc)) +
2388 PROC_FRAME_OFFSET (proc_desc) -
2389 PROC_FRAME_ADJUST (proc_desc));
2392 static mips_extra_func_info_t cached_proc_desc;
2395 mips_frame_chain (struct frame_info *frame)
2397 mips_extra_func_info_t proc_desc;
2399 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
2401 if (saved_pc == 0 || inside_entry_file (saved_pc))
2404 /* Check if the PC is inside a call stub. If it is, fetch the
2405 PC of the caller of that stub. */
2406 if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0)
2409 /* Look up the procedure descriptor for this PC. */
2410 proc_desc = find_proc_desc (saved_pc, frame, 1);
2414 cached_proc_desc = proc_desc;
2416 /* If no frame pointer and frame size is zero, we must be at end
2417 of stack (or otherwise hosed). If we don't check frame size,
2418 we loop forever if we see a zero size frame. */
2419 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2420 && PROC_FRAME_OFFSET (proc_desc) == 0
2421 /* The previous frame from a sigtramp frame might be frameless
2422 and have frame size zero. */
2423 && !frame->signal_handler_caller
2424 /* Check if this is a call dummy frame. */
2425 && frame->pc != CALL_DUMMY_ADDRESS ())
2428 return get_frame_pointer (frame, proc_desc);
2432 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2436 /* Use proc_desc calculated in frame_chain */
2437 mips_extra_func_info_t proc_desc =
2438 fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1);
2440 fci->extra_info = (struct frame_extra_info *)
2441 frame_obstack_alloc (sizeof (struct frame_extra_info));
2443 fci->saved_regs = NULL;
2444 fci->extra_info->proc_desc =
2445 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2448 /* Fixup frame-pointer - only needed for top frame */
2449 /* This may not be quite right, if proc has a real frame register.
2450 Get the value of the frame relative sp, procedure might have been
2451 interrupted by a signal at it's very start. */
2452 if (fci->pc == PROC_LOW_ADDR (proc_desc)
2453 && !PROC_DESC_IS_DUMMY (proc_desc))
2454 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
2456 fci->frame = get_frame_pointer (fci->next, proc_desc);
2458 if (proc_desc == &temp_proc_desc)
2462 /* Do not set the saved registers for a sigtramp frame,
2463 mips_find_saved_registers will do that for us.
2464 We can't use fci->signal_handler_caller, it is not yet set. */
2465 find_pc_partial_function (fci->pc, &name,
2466 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2467 if (!PC_IN_SIGTRAMP (fci->pc, name))
2469 frame_saved_regs_zalloc (fci);
2470 memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2471 fci->saved_regs[PC_REGNUM]
2472 = fci->saved_regs[RA_REGNUM];
2473 /* Set value of previous frame's stack pointer. Remember that
2474 saved_regs[SP_REGNUM] is special in that it contains the
2475 value of the stack pointer register. The other saved_regs
2476 values are addresses (in the inferior) at which a given
2477 register's value may be found. */
2478 fci->saved_regs[SP_REGNUM] = fci->frame;
2482 /* hack: if argument regs are saved, guess these contain args */
2483 /* assume we can't tell how many args for now */
2484 fci->extra_info->num_args = -1;
2485 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2487 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2489 fci->extra_info->num_args = regnum - A0_REGNUM + 1;
2496 /* MIPS stack frames are almost impenetrable. When execution stops,
2497 we basically have to look at symbol information for the function
2498 that we stopped in, which tells us *which* register (if any) is
2499 the base of the frame pointer, and what offset from that register
2500 the frame itself is at.
2502 This presents a problem when trying to examine a stack in memory
2503 (that isn't executing at the moment), using the "frame" command. We
2504 don't have a PC, nor do we have any registers except SP.
2506 This routine takes two arguments, SP and PC, and tries to make the
2507 cached frames look as if these two arguments defined a frame on the
2508 cache. This allows the rest of info frame to extract the important
2509 arguments without difficulty. */
2512 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2515 error ("MIPS frame specifications require two arguments: sp and pc");
2517 return create_new_frame (argv[0], argv[1]);
2520 /* According to the current ABI, should the type be passed in a
2521 floating-point register (assuming that there is space)? When there
2522 is no FPU, FP are not even considered as possibile candidates for
2523 FP registers and, consequently this returns false - forces FP
2524 arguments into integer registers. */
2527 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2529 return ((typecode == TYPE_CODE_FLT
2531 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2532 && TYPE_NFIELDS (arg_type) == 1
2533 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2534 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2537 /* On o32, argument passing in GPRs depends on the alignment of the type being
2538 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2541 mips_type_needs_double_align (struct type *type)
2543 enum type_code typecode = TYPE_CODE (type);
2545 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2547 else if (typecode == TYPE_CODE_STRUCT)
2549 if (TYPE_NFIELDS (type) < 1)
2551 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2553 else if (typecode == TYPE_CODE_UNION)
2557 n = TYPE_NFIELDS (type);
2558 for (i = 0; i < n; i++)
2559 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2566 /* Macros to round N up or down to the next A boundary;
2567 A must be a power of two. */
2569 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2570 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2573 mips_eabi_push_arguments (int nargs,
2574 struct value **args,
2577 CORE_ADDR struct_addr)
2583 int stack_offset = 0;
2585 /* First ensure that the stack and structure return address (if any)
2586 are properly aligned. The stack has to be at least 64-bit
2587 aligned even on 32-bit machines, because doubles must be 64-bit
2588 aligned. For n32 and n64, stack frames need to be 128-bit
2589 aligned, so we round to this widest known alignment. */
2591 sp = ROUND_DOWN (sp, 16);
2592 struct_addr = ROUND_DOWN (struct_addr, 16);
2594 /* Now make space on the stack for the args. We allocate more
2595 than necessary for EABI, because the first few arguments are
2596 passed in registers, but that's OK. */
2597 for (argnum = 0; argnum < nargs; argnum++)
2598 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2599 MIPS_STACK_ARGSIZE);
2600 sp -= ROUND_UP (len, 16);
2603 fprintf_unfiltered (gdb_stdlog,
2604 "mips_eabi_push_arguments: sp=0x%s allocated %d\n",
2605 paddr_nz (sp), ROUND_UP (len, 16));
2607 /* Initialize the integer and float register pointers. */
2609 float_argreg = FPA0_REGNUM;
2611 /* The struct_return pointer occupies the first parameter-passing reg. */
2615 fprintf_unfiltered (gdb_stdlog,
2616 "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n",
2617 argreg, paddr_nz (struct_addr));
2618 write_register (argreg++, struct_addr);
2621 /* Now load as many as possible of the first arguments into
2622 registers, and push the rest onto the stack. Loop thru args
2623 from first to last. */
2624 for (argnum = 0; argnum < nargs; argnum++)
2627 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2628 struct value *arg = args[argnum];
2629 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2630 int len = TYPE_LENGTH (arg_type);
2631 enum type_code typecode = TYPE_CODE (arg_type);
2634 fprintf_unfiltered (gdb_stdlog,
2635 "mips_eabi_push_arguments: %d len=%d type=%d",
2636 argnum + 1, len, (int) typecode);
2638 /* The EABI passes structures that do not fit in a register by
2640 if (len > MIPS_SAVED_REGSIZE
2641 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2643 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2644 typecode = TYPE_CODE_PTR;
2645 len = MIPS_SAVED_REGSIZE;
2648 fprintf_unfiltered (gdb_stdlog, " push");
2651 val = (char *) VALUE_CONTENTS (arg);
2653 /* 32-bit ABIs always start floating point arguments in an
2654 even-numbered floating point register. Round the FP register
2655 up before the check to see if there are any FP registers
2656 left. Non MIPS_EABI targets also pass the FP in the integer
2657 registers so also round up normal registers. */
2658 if (!FP_REGISTER_DOUBLE
2659 && fp_register_arg_p (typecode, arg_type))
2661 if ((float_argreg & 1))
2665 /* Floating point arguments passed in registers have to be
2666 treated specially. On 32-bit architectures, doubles
2667 are passed in register pairs; the even register gets
2668 the low word, and the odd register gets the high word.
2669 On non-EABI processors, the first two floating point arguments are
2670 also copied to general registers, because MIPS16 functions
2671 don't use float registers for arguments. This duplication of
2672 arguments in general registers can't hurt non-MIPS16 functions
2673 because those registers are normally skipped. */
2674 /* MIPS_EABI squeezes a struct that contains a single floating
2675 point value into an FP register instead of pushing it onto the
2677 if (fp_register_arg_p (typecode, arg_type)
2678 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2680 if (!FP_REGISTER_DOUBLE && len == 8)
2682 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2683 unsigned long regval;
2685 /* Write the low word of the double to the even register(s). */
2686 regval = extract_unsigned_integer (val + low_offset, 4);
2688 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2689 float_argreg, phex (regval, 4));
2690 write_register (float_argreg++, regval);
2692 /* Write the high word of the double to the odd register(s). */
2693 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2695 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2696 float_argreg, phex (regval, 4));
2697 write_register (float_argreg++, regval);
2701 /* This is a floating point value that fits entirely
2702 in a single register. */
2703 /* On 32 bit ABI's the float_argreg is further adjusted
2704 above to ensure that it is even register aligned. */
2705 LONGEST regval = extract_unsigned_integer (val, len);
2707 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2708 float_argreg, phex (regval, len));
2709 write_register (float_argreg++, regval);
2714 /* Copy the argument to general registers or the stack in
2715 register-sized pieces. Large arguments are split between
2716 registers and stack. */
2717 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2718 are treated specially: Irix cc passes them in registers
2719 where gcc sometimes puts them on the stack. For maximum
2720 compatibility, we will put them in both places. */
2721 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2722 (len % MIPS_SAVED_REGSIZE != 0));
2724 /* Note: Floating-point values that didn't fit into an FP
2725 register are only written to memory. */
2728 /* Remember if the argument was written to the stack. */
2729 int stack_used_p = 0;
2731 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2734 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2737 /* Write this portion of the argument to the stack. */
2738 if (argreg > MIPS_LAST_ARG_REGNUM
2740 || fp_register_arg_p (typecode, arg_type))
2742 /* Should shorter than int integer values be
2743 promoted to int before being stored? */
2744 int longword_offset = 0;
2747 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2749 if (MIPS_STACK_ARGSIZE == 8 &&
2750 (typecode == TYPE_CODE_INT ||
2751 typecode == TYPE_CODE_PTR ||
2752 typecode == TYPE_CODE_FLT) && len <= 4)
2753 longword_offset = MIPS_STACK_ARGSIZE - len;
2754 else if ((typecode == TYPE_CODE_STRUCT ||
2755 typecode == TYPE_CODE_UNION) &&
2756 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2757 longword_offset = MIPS_STACK_ARGSIZE - len;
2762 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2763 paddr_nz (stack_offset));
2764 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2765 paddr_nz (longword_offset));
2768 addr = sp + stack_offset + longword_offset;
2773 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2775 for (i = 0; i < partial_len; i++)
2777 fprintf_unfiltered (gdb_stdlog, "%02x",
2781 write_memory (addr, val, partial_len);
2784 /* Note!!! This is NOT an else clause. Odd sized
2785 structs may go thru BOTH paths. Floating point
2786 arguments will not. */
2787 /* Write this portion of the argument to a general
2788 purpose register. */
2789 if (argreg <= MIPS_LAST_ARG_REGNUM
2790 && !fp_register_arg_p (typecode, arg_type))
2792 LONGEST regval = extract_unsigned_integer (val, partial_len);
2795 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2797 phex (regval, MIPS_SAVED_REGSIZE));
2798 write_register (argreg, regval);
2805 /* Compute the the offset into the stack at which we
2806 will copy the next parameter.
2808 In the new EABI (and the NABI32), the stack_offset
2809 only needs to be adjusted when it has been used. */
2812 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2816 fprintf_unfiltered (gdb_stdlog, "\n");
2819 /* Return adjusted stack pointer. */
2823 /* N32/N64 version of push_arguments. */
2826 mips_n32n64_push_arguments (int nargs,
2827 struct value **args,
2830 CORE_ADDR struct_addr)
2836 int stack_offset = 0;
2838 /* First ensure that the stack and structure return address (if any)
2839 are properly aligned. The stack has to be at least 64-bit
2840 aligned even on 32-bit machines, because doubles must be 64-bit
2841 aligned. For n32 and n64, stack frames need to be 128-bit
2842 aligned, so we round to this widest known alignment. */
2844 sp = ROUND_DOWN (sp, 16);
2845 struct_addr = ROUND_DOWN (struct_addr, 16);
2847 /* Now make space on the stack for the args. */
2848 for (argnum = 0; argnum < nargs; argnum++)
2849 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2850 MIPS_STACK_ARGSIZE);
2851 sp -= ROUND_UP (len, 16);
2854 fprintf_unfiltered (gdb_stdlog,
2855 "mips_n32n64_push_arguments: sp=0x%s allocated %d\n",
2856 paddr_nz (sp), ROUND_UP (len, 16));
2858 /* Initialize the integer and float register pointers. */
2860 float_argreg = FPA0_REGNUM;
2862 /* The struct_return pointer occupies the first parameter-passing reg. */
2866 fprintf_unfiltered (gdb_stdlog,
2867 "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n",
2868 argreg, paddr_nz (struct_addr));
2869 write_register (argreg++, struct_addr);
2872 /* Now load as many as possible of the first arguments into
2873 registers, and push the rest onto the stack. Loop thru args
2874 from first to last. */
2875 for (argnum = 0; argnum < nargs; argnum++)
2878 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
2879 struct value *arg = args[argnum];
2880 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2881 int len = TYPE_LENGTH (arg_type);
2882 enum type_code typecode = TYPE_CODE (arg_type);
2885 fprintf_unfiltered (gdb_stdlog,
2886 "mips_n32n64_push_arguments: %d len=%d type=%d",
2887 argnum + 1, len, (int) typecode);
2889 val = (char *) VALUE_CONTENTS (arg);
2891 if (fp_register_arg_p (typecode, arg_type)
2892 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2894 /* This is a floating point value that fits entirely
2895 in a single register. */
2896 /* On 32 bit ABI's the float_argreg is further adjusted
2897 above to ensure that it is even register aligned. */
2898 LONGEST regval = extract_unsigned_integer (val, len);
2900 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2901 float_argreg, phex (regval, len));
2902 write_register (float_argreg++, regval);
2905 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2906 argreg, phex (regval, len));
2907 write_register (argreg, regval);
2912 /* Copy the argument to general registers or the stack in
2913 register-sized pieces. Large arguments are split between
2914 registers and stack. */
2915 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2916 are treated specially: Irix cc passes them in registers
2917 where gcc sometimes puts them on the stack. For maximum
2918 compatibility, we will put them in both places. */
2919 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2920 (len % MIPS_SAVED_REGSIZE != 0));
2921 /* Note: Floating-point values that didn't fit into an FP
2922 register are only written to memory. */
2925 /* Rememer if the argument was written to the stack. */
2926 int stack_used_p = 0;
2927 int partial_len = len < MIPS_SAVED_REGSIZE ?
2928 len : MIPS_SAVED_REGSIZE;
2931 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2934 /* Write this portion of the argument to the stack. */
2935 if (argreg > MIPS_LAST_ARG_REGNUM
2937 || fp_register_arg_p (typecode, arg_type))
2939 /* Should shorter than int integer values be
2940 promoted to int before being stored? */
2941 int longword_offset = 0;
2944 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2946 if (MIPS_STACK_ARGSIZE == 8 &&
2947 (typecode == TYPE_CODE_INT ||
2948 typecode == TYPE_CODE_PTR ||
2949 typecode == TYPE_CODE_FLT) && len <= 4)
2950 longword_offset = MIPS_STACK_ARGSIZE - len;
2951 else if ((typecode == TYPE_CODE_STRUCT ||
2952 typecode == TYPE_CODE_UNION) &&
2953 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2954 longword_offset = MIPS_STACK_ARGSIZE - len;
2959 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2960 paddr_nz (stack_offset));
2961 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2962 paddr_nz (longword_offset));
2965 addr = sp + stack_offset + longword_offset;
2970 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2972 for (i = 0; i < partial_len; i++)
2974 fprintf_unfiltered (gdb_stdlog, "%02x",
2978 write_memory (addr, val, partial_len);
2981 /* Note!!! This is NOT an else clause. Odd sized
2982 structs may go thru BOTH paths. Floating point
2983 arguments will not. */
2984 /* Write this portion of the argument to a general
2985 purpose register. */
2986 if (argreg <= MIPS_LAST_ARG_REGNUM
2987 && !fp_register_arg_p (typecode, arg_type))
2989 LONGEST regval = extract_unsigned_integer (val, partial_len);
2991 /* A non-floating-point argument being passed in a
2992 general register. If a struct or union, and if
2993 the remaining length is smaller than the register
2994 size, we have to adjust the register value on
2997 It does not seem to be necessary to do the
2998 same for integral types.
3000 cagney/2001-07-23: gdb/179: Also, GCC, when
3001 outputting LE O32 with sizeof (struct) <
3002 MIPS_SAVED_REGSIZE, generates a left shift as
3003 part of storing the argument in a register a
3004 register (the left shift isn't generated when
3005 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3006 is quite possible that this is GCC contradicting
3007 the LE/O32 ABI, GDB has not been adjusted to
3008 accommodate this. Either someone needs to
3009 demonstrate that the LE/O32 ABI specifies such a
3010 left shift OR this new ABI gets identified as
3011 such and GDB gets tweaked accordingly. */
3013 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3014 && partial_len < MIPS_SAVED_REGSIZE
3015 && (typecode == TYPE_CODE_STRUCT ||
3016 typecode == TYPE_CODE_UNION))
3017 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3021 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3023 phex (regval, MIPS_SAVED_REGSIZE));
3024 write_register (argreg, regval);
3031 /* Compute the the offset into the stack at which we
3032 will copy the next parameter.
3034 In N32 (N64?), the stack_offset only needs to be
3035 adjusted when it has been used. */
3038 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3042 fprintf_unfiltered (gdb_stdlog, "\n");
3045 /* Return adjusted stack pointer. */
3049 /* O32 version of push_arguments. */
3052 mips_o32_push_arguments (int nargs,
3053 struct value **args,
3056 CORE_ADDR struct_addr)
3062 int stack_offset = 0;
3064 /* First ensure that the stack and structure return address (if any)
3065 are properly aligned. The stack has to be at least 64-bit
3066 aligned even on 32-bit machines, because doubles must be 64-bit
3067 aligned. For n32 and n64, stack frames need to be 128-bit
3068 aligned, so we round to this widest known alignment. */
3070 sp = ROUND_DOWN (sp, 16);
3071 struct_addr = ROUND_DOWN (struct_addr, 16);
3073 /* Now make space on the stack for the args. */
3074 for (argnum = 0; argnum < nargs; argnum++)
3075 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3076 MIPS_STACK_ARGSIZE);
3077 sp -= ROUND_UP (len, 16);
3080 fprintf_unfiltered (gdb_stdlog,
3081 "mips_o32_push_arguments: sp=0x%s allocated %d\n",
3082 paddr_nz (sp), ROUND_UP (len, 16));
3084 /* Initialize the integer and float register pointers. */
3086 float_argreg = FPA0_REGNUM;
3088 /* The struct_return pointer occupies the first parameter-passing reg. */
3092 fprintf_unfiltered (gdb_stdlog,
3093 "mips_o32_push_arguments: struct_return reg=%d 0x%s\n",
3094 argreg, paddr_nz (struct_addr));
3095 write_register (argreg++, struct_addr);
3096 stack_offset += MIPS_STACK_ARGSIZE;
3099 /* Now load as many as possible of the first arguments into
3100 registers, and push the rest onto the stack. Loop thru args
3101 from first to last. */
3102 for (argnum = 0; argnum < nargs; argnum++)
3105 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
3106 struct value *arg = args[argnum];
3107 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3108 int len = TYPE_LENGTH (arg_type);
3109 enum type_code typecode = TYPE_CODE (arg_type);
3112 fprintf_unfiltered (gdb_stdlog,
3113 "mips_o32_push_arguments: %d len=%d type=%d",
3114 argnum + 1, len, (int) typecode);
3116 val = (char *) VALUE_CONTENTS (arg);
3118 /* 32-bit ABIs always start floating point arguments in an
3119 even-numbered floating point register. Round the FP register
3120 up before the check to see if there are any FP registers
3121 left. O32/O64 targets also pass the FP in the integer
3122 registers so also round up normal registers. */
3123 if (!FP_REGISTER_DOUBLE
3124 && fp_register_arg_p (typecode, arg_type))
3126 if ((float_argreg & 1))
3130 /* Floating point arguments passed in registers have to be
3131 treated specially. On 32-bit architectures, doubles
3132 are passed in register pairs; the even register gets
3133 the low word, and the odd register gets the high word.
3134 On O32/O64, the first two floating point arguments are
3135 also copied to general registers, because MIPS16 functions
3136 don't use float registers for arguments. This duplication of
3137 arguments in general registers can't hurt non-MIPS16 functions
3138 because those registers are normally skipped. */
3140 if (fp_register_arg_p (typecode, arg_type)
3141 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3143 if (!FP_REGISTER_DOUBLE && len == 8)
3145 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3146 unsigned long regval;
3148 /* Write the low word of the double to the even register(s). */
3149 regval = extract_unsigned_integer (val + low_offset, 4);
3151 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3152 float_argreg, phex (regval, 4));
3153 write_register (float_argreg++, regval);
3155 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3156 argreg, phex (regval, 4));
3157 write_register (argreg++, regval);
3159 /* Write the high word of the double to the odd register(s). */
3160 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3162 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3163 float_argreg, phex (regval, 4));
3164 write_register (float_argreg++, regval);
3167 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3168 argreg, phex (regval, 4));
3169 write_register (argreg++, regval);
3173 /* This is a floating point value that fits entirely
3174 in a single register. */
3175 /* On 32 bit ABI's the float_argreg is further adjusted
3176 above to ensure that it is even register aligned. */
3177 LONGEST regval = extract_unsigned_integer (val, len);
3179 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3180 float_argreg, phex (regval, len));
3181 write_register (float_argreg++, regval);
3182 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3183 registers for each argument. The below is (my
3184 guess) to ensure that the corresponding integer
3185 register has reserved the same space. */
3187 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3188 argreg, phex (regval, len));
3189 write_register (argreg, regval);
3190 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3192 /* Reserve space for the FP register. */
3193 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3197 /* Copy the argument to general registers or the stack in
3198 register-sized pieces. Large arguments are split between
3199 registers and stack. */
3200 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3201 are treated specially: Irix cc passes them in registers
3202 where gcc sometimes puts them on the stack. For maximum
3203 compatibility, we will put them in both places. */
3204 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3205 (len % MIPS_SAVED_REGSIZE != 0));
3206 /* Structures should be aligned to eight bytes (even arg registers)
3207 on MIPS_ABI_O32, if their first member has double precision. */
3208 if (MIPS_SAVED_REGSIZE < 8
3209 && mips_type_needs_double_align (arg_type))
3214 /* Note: Floating-point values that didn't fit into an FP
3215 register are only written to memory. */
3218 /* Remember if the argument was written to the stack. */
3219 int stack_used_p = 0;
3221 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3224 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3227 /* Write this portion of the argument to the stack. */
3228 if (argreg > MIPS_LAST_ARG_REGNUM
3230 || fp_register_arg_p (typecode, arg_type))
3232 /* Should shorter than int integer values be
3233 promoted to int before being stored? */
3234 int longword_offset = 0;
3237 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3239 if (MIPS_STACK_ARGSIZE == 8 &&
3240 (typecode == TYPE_CODE_INT ||
3241 typecode == TYPE_CODE_PTR ||
3242 typecode == TYPE_CODE_FLT) && len <= 4)
3243 longword_offset = MIPS_STACK_ARGSIZE - len;
3248 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3249 paddr_nz (stack_offset));
3250 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3251 paddr_nz (longword_offset));
3254 addr = sp + stack_offset + longword_offset;
3259 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3261 for (i = 0; i < partial_len; i++)
3263 fprintf_unfiltered (gdb_stdlog, "%02x",
3267 write_memory (addr, val, partial_len);
3270 /* Note!!! This is NOT an else clause. Odd sized
3271 structs may go thru BOTH paths. Floating point
3272 arguments will not. */
3273 /* Write this portion of the argument to a general
3274 purpose register. */
3275 if (argreg <= MIPS_LAST_ARG_REGNUM
3276 && !fp_register_arg_p (typecode, arg_type))
3278 LONGEST regval = extract_signed_integer (val, partial_len);
3279 /* Value may need to be sign extended, because
3280 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3282 /* A non-floating-point argument being passed in a
3283 general register. If a struct or union, and if
3284 the remaining length is smaller than the register
3285 size, we have to adjust the register value on
3288 It does not seem to be necessary to do the
3289 same for integral types.
3291 Also don't do this adjustment on O64 binaries.
3293 cagney/2001-07-23: gdb/179: Also, GCC, when
3294 outputting LE O32 with sizeof (struct) <
3295 MIPS_SAVED_REGSIZE, generates a left shift as
3296 part of storing the argument in a register a
3297 register (the left shift isn't generated when
3298 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3299 is quite possible that this is GCC contradicting
3300 the LE/O32 ABI, GDB has not been adjusted to
3301 accommodate this. Either someone needs to
3302 demonstrate that the LE/O32 ABI specifies such a
3303 left shift OR this new ABI gets identified as
3304 such and GDB gets tweaked accordingly. */
3306 if (MIPS_SAVED_REGSIZE < 8
3307 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3308 && partial_len < MIPS_SAVED_REGSIZE
3309 && (typecode == TYPE_CODE_STRUCT ||
3310 typecode == TYPE_CODE_UNION))
3311 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3315 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3317 phex (regval, MIPS_SAVED_REGSIZE));
3318 write_register (argreg, regval);
3321 /* Prevent subsequent floating point arguments from
3322 being passed in floating point registers. */
3323 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3329 /* Compute the the offset into the stack at which we
3330 will copy the next parameter.
3332 In older ABIs, the caller reserved space for
3333 registers that contained arguments. This was loosely
3334 refered to as their "home". Consequently, space is
3335 always allocated. */
3337 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3341 fprintf_unfiltered (gdb_stdlog, "\n");
3344 /* Return adjusted stack pointer. */
3348 /* O64 version of push_arguments. */
3351 mips_o64_push_arguments (int nargs,
3352 struct value **args,
3355 CORE_ADDR struct_addr)
3361 int stack_offset = 0;
3363 /* First ensure that the stack and structure return address (if any)
3364 are properly aligned. The stack has to be at least 64-bit
3365 aligned even on 32-bit machines, because doubles must be 64-bit
3366 aligned. For n32 and n64, stack frames need to be 128-bit
3367 aligned, so we round to this widest known alignment. */
3369 sp = ROUND_DOWN (sp, 16);
3370 struct_addr = ROUND_DOWN (struct_addr, 16);
3372 /* Now make space on the stack for the args. */
3373 for (argnum = 0; argnum < nargs; argnum++)
3374 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3375 MIPS_STACK_ARGSIZE);
3376 sp -= ROUND_UP (len, 16);
3379 fprintf_unfiltered (gdb_stdlog,
3380 "mips_o64_push_arguments: sp=0x%s allocated %d\n",
3381 paddr_nz (sp), ROUND_UP (len, 16));
3383 /* Initialize the integer and float register pointers. */
3385 float_argreg = FPA0_REGNUM;
3387 /* The struct_return pointer occupies the first parameter-passing reg. */
3391 fprintf_unfiltered (gdb_stdlog,
3392 "mips_o64_push_arguments: struct_return reg=%d 0x%s\n",
3393 argreg, paddr_nz (struct_addr));
3394 write_register (argreg++, struct_addr);
3395 stack_offset += MIPS_STACK_ARGSIZE;
3398 /* Now load as many as possible of the first arguments into
3399 registers, and push the rest onto the stack. Loop thru args
3400 from first to last. */
3401 for (argnum = 0; argnum < nargs; argnum++)
3404 char *valbuf = alloca (MAX_REGISTER_RAW_SIZE);
3405 struct value *arg = args[argnum];
3406 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3407 int len = TYPE_LENGTH (arg_type);
3408 enum type_code typecode = TYPE_CODE (arg_type);
3411 fprintf_unfiltered (gdb_stdlog,
3412 "mips_o64_push_arguments: %d len=%d type=%d",
3413 argnum + 1, len, (int) typecode);
3415 val = (char *) VALUE_CONTENTS (arg);
3417 /* 32-bit ABIs always start floating point arguments in an
3418 even-numbered floating point register. Round the FP register
3419 up before the check to see if there are any FP registers
3420 left. O32/O64 targets also pass the FP in the integer
3421 registers so also round up normal registers. */
3422 if (!FP_REGISTER_DOUBLE
3423 && fp_register_arg_p (typecode, arg_type))
3425 if ((float_argreg & 1))
3429 /* Floating point arguments passed in registers have to be
3430 treated specially. On 32-bit architectures, doubles
3431 are passed in register pairs; the even register gets
3432 the low word, and the odd register gets the high word.
3433 On O32/O64, the first two floating point arguments are
3434 also copied to general registers, because MIPS16 functions
3435 don't use float registers for arguments. This duplication of
3436 arguments in general registers can't hurt non-MIPS16 functions
3437 because those registers are normally skipped. */
3439 if (fp_register_arg_p (typecode, arg_type)
3440 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3442 if (!FP_REGISTER_DOUBLE && len == 8)
3444 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3445 unsigned long regval;
3447 /* Write the low word of the double to the even register(s). */
3448 regval = extract_unsigned_integer (val + low_offset, 4);
3450 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3451 float_argreg, phex (regval, 4));
3452 write_register (float_argreg++, regval);
3454 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3455 argreg, phex (regval, 4));
3456 write_register (argreg++, regval);
3458 /* Write the high word of the double to the odd register(s). */
3459 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3461 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3462 float_argreg, phex (regval, 4));
3463 write_register (float_argreg++, regval);
3466 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3467 argreg, phex (regval, 4));
3468 write_register (argreg++, regval);
3472 /* This is a floating point value that fits entirely
3473 in a single register. */
3474 /* On 32 bit ABI's the float_argreg is further adjusted
3475 above to ensure that it is even register aligned. */
3476 LONGEST regval = extract_unsigned_integer (val, len);
3478 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3479 float_argreg, phex (regval, len));
3480 write_register (float_argreg++, regval);
3481 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3482 registers for each argument. The below is (my
3483 guess) to ensure that the corresponding integer
3484 register has reserved the same space. */
3486 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3487 argreg, phex (regval, len));
3488 write_register (argreg, regval);
3489 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3491 /* Reserve space for the FP register. */
3492 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
3496 /* Copy the argument to general registers or the stack in
3497 register-sized pieces. Large arguments are split between
3498 registers and stack. */
3499 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3500 are treated specially: Irix cc passes them in registers
3501 where gcc sometimes puts them on the stack. For maximum
3502 compatibility, we will put them in both places. */
3503 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3504 (len % MIPS_SAVED_REGSIZE != 0));
3505 /* Structures should be aligned to eight bytes (even arg registers)
3506 on MIPS_ABI_O32, if their first member has double precision. */
3507 if (MIPS_SAVED_REGSIZE < 8
3508 && mips_type_needs_double_align (arg_type))
3513 /* Note: Floating-point values that didn't fit into an FP
3514 register are only written to memory. */
3517 /* Remember if the argument was written to the stack. */
3518 int stack_used_p = 0;
3520 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3523 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3526 /* Write this portion of the argument to the stack. */
3527 if (argreg > MIPS_LAST_ARG_REGNUM
3529 || fp_register_arg_p (typecode, arg_type))
3531 /* Should shorter than int integer values be
3532 promoted to int before being stored? */
3533 int longword_offset = 0;
3536 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3538 if (MIPS_STACK_ARGSIZE == 8 &&
3539 (typecode == TYPE_CODE_INT ||
3540 typecode == TYPE_CODE_PTR ||
3541 typecode == TYPE_CODE_FLT) && len <= 4)
3542 longword_offset = MIPS_STACK_ARGSIZE - len;
3547 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3548 paddr_nz (stack_offset));
3549 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3550 paddr_nz (longword_offset));
3553 addr = sp + stack_offset + longword_offset;
3558 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3560 for (i = 0; i < partial_len; i++)
3562 fprintf_unfiltered (gdb_stdlog, "%02x",
3566 write_memory (addr, val, partial_len);
3569 /* Note!!! This is NOT an else clause. Odd sized
3570 structs may go thru BOTH paths. Floating point
3571 arguments will not. */
3572 /* Write this portion of the argument to a general
3573 purpose register. */
3574 if (argreg <= MIPS_LAST_ARG_REGNUM
3575 && !fp_register_arg_p (typecode, arg_type))
3577 LONGEST regval = extract_signed_integer (val, partial_len);
3578 /* Value may need to be sign extended, because
3579 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3581 /* A non-floating-point argument being passed in a
3582 general register. If a struct or union, and if
3583 the remaining length is smaller than the register
3584 size, we have to adjust the register value on
3587 It does not seem to be necessary to do the
3588 same for integral types.
3590 Also don't do this adjustment on O64 binaries.
3592 cagney/2001-07-23: gdb/179: Also, GCC, when
3593 outputting LE O32 with sizeof (struct) <
3594 MIPS_SAVED_REGSIZE, generates a left shift as
3595 part of storing the argument in a register a
3596 register (the left shift isn't generated when
3597 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3598 is quite possible that this is GCC contradicting
3599 the LE/O32 ABI, GDB has not been adjusted to
3600 accommodate this. Either someone needs to
3601 demonstrate that the LE/O32 ABI specifies such a
3602 left shift OR this new ABI gets identified as
3603 such and GDB gets tweaked accordingly. */
3605 if (MIPS_SAVED_REGSIZE < 8
3606 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3607 && partial_len < MIPS_SAVED_REGSIZE
3608 && (typecode == TYPE_CODE_STRUCT ||
3609 typecode == TYPE_CODE_UNION))
3610 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3614 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3616 phex (regval, MIPS_SAVED_REGSIZE));
3617 write_register (argreg, regval);
3620 /* Prevent subsequent floating point arguments from
3621 being passed in floating point registers. */
3622 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3628 /* Compute the the offset into the stack at which we
3629 will copy the next parameter.
3631 In older ABIs, the caller reserved space for
3632 registers that contained arguments. This was loosely
3633 refered to as their "home". Consequently, space is
3634 always allocated. */
3636 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
3640 fprintf_unfiltered (gdb_stdlog, "\n");
3643 /* Return adjusted stack pointer. */
3648 mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
3650 /* Set the return address register to point to the entry
3651 point of the program, where a breakpoint lies in wait. */
3652 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
3657 mips_push_register (CORE_ADDR * sp, int regno)
3659 char *buffer = alloca (MAX_REGISTER_RAW_SIZE);
3662 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
3664 regsize = MIPS_SAVED_REGSIZE;
3665 offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3666 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
3671 regsize = REGISTER_RAW_SIZE (regno);
3675 read_register_gen (regno, buffer);
3676 write_memory (*sp, buffer + offset, regsize);
3679 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
3680 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
3683 mips_push_dummy_frame (void)
3686 struct linked_proc_info *link = (struct linked_proc_info *)
3687 xmalloc (sizeof (struct linked_proc_info));
3688 mips_extra_func_info_t proc_desc = &link->info;
3689 CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
3690 CORE_ADDR old_sp = sp;
3691 link->next = linked_proc_desc_table;
3692 linked_proc_desc_table = link;
3694 /* FIXME! are these correct ? */
3695 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
3696 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
3697 #define FLOAT_REG_SAVE_MASK MASK(0,19)
3698 #define FLOAT_SINGLE_REG_SAVE_MASK \
3699 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
3701 * The registers we must save are all those not preserved across
3702 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
3703 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
3704 * and FP Control/Status registers.
3707 * Dummy frame layout:
3710 * Saved MMHI, MMLO, FPC_CSR
3715 * Saved D18 (i.e. F19, F18)
3717 * Saved D0 (i.e. F1, F0)
3718 * Argument build area and stack arguments written via mips_push_arguments
3722 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
3723 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
3724 PROC_FRAME_OFFSET (proc_desc) = 0;
3725 PROC_FRAME_ADJUST (proc_desc) = 0;
3726 mips_push_register (&sp, PC_REGNUM);
3727 mips_push_register (&sp, HI_REGNUM);
3728 mips_push_register (&sp, LO_REGNUM);
3729 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
3731 /* Save general CPU registers */
3732 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
3733 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
3734 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
3735 for (ireg = 32; --ireg >= 0;)
3736 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
3737 mips_push_register (&sp, ireg);
3739 /* Save floating point registers starting with high order word */
3740 PROC_FREG_MASK (proc_desc) =
3741 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
3742 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
3743 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
3745 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
3746 for (ireg = 32; --ireg >= 0;)
3747 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
3748 mips_push_register (&sp, ireg + FP0_REGNUM);
3750 /* Update the frame pointer for the call dummy and the stack pointer.
3751 Set the procedure's starting and ending addresses to point to the
3752 call dummy address at the entry point. */
3753 write_register (PUSH_FP_REGNUM, old_sp);
3754 write_register (SP_REGNUM, sp);
3755 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
3756 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
3757 SET_PROC_DESC_IS_DUMMY (proc_desc);
3758 PROC_PC_REG (proc_desc) = RA_REGNUM;
3762 mips_pop_frame (void)
3764 register int regnum;
3765 struct frame_info *frame = get_current_frame ();
3766 CORE_ADDR new_sp = FRAME_FP (frame);
3768 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
3770 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
3771 if (frame->saved_regs == NULL)
3772 FRAME_INIT_SAVED_REGS (frame);
3773 for (regnum = 0; regnum < NUM_REGS; regnum++)
3775 if (regnum != SP_REGNUM && regnum != PC_REGNUM
3776 && frame->saved_regs[regnum])
3777 write_register (regnum,
3778 read_memory_integer (frame->saved_regs[regnum],
3779 MIPS_SAVED_REGSIZE));
3782 write_register (SP_REGNUM, new_sp);
3783 flush_cached_frames ();
3785 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
3787 struct linked_proc_info *pi_ptr, *prev_ptr;
3789 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
3791 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
3793 if (&pi_ptr->info == proc_desc)
3798 error ("Can't locate dummy extra frame info\n");
3800 if (prev_ptr != NULL)
3801 prev_ptr->next = pi_ptr->next;
3803 linked_proc_desc_table = pi_ptr->next;
3807 write_register (HI_REGNUM,
3808 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
3809 MIPS_SAVED_REGSIZE));
3810 write_register (LO_REGNUM,
3811 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
3812 MIPS_SAVED_REGSIZE));
3813 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
3814 write_register (FCRCS_REGNUM,
3815 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
3816 MIPS_SAVED_REGSIZE));
3821 mips_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
3822 struct value **args, struct type *type, int gcc_p)
3824 write_register(T9_REGNUM, fun);
3827 /* Floating point register management.
3829 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3830 64bit operations, these early MIPS cpus treat fp register pairs
3831 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3832 registers and offer a compatibility mode that emulates the MIPS2 fp
3833 model. When operating in MIPS2 fp compat mode, later cpu's split
3834 double precision floats into two 32-bit chunks and store them in
3835 consecutive fp regs. To display 64-bit floats stored in this
3836 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3837 Throw in user-configurable endianness and you have a real mess.
3839 The way this works is:
3840 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3841 double-precision value will be split across two logical registers.
3842 The lower-numbered logical register will hold the low-order bits,
3843 regardless of the processor's endianness.
3844 - If we are on a 64-bit processor, and we are looking for a
3845 single-precision value, it will be in the low ordered bits
3846 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3847 save slot in memory.
3848 - If we are in 64-bit mode, everything is straightforward.
3850 Note that this code only deals with "live" registers at the top of the
3851 stack. We will attempt to deal with saved registers later, when
3852 the raw/cooked register interface is in place. (We need a general
3853 interface that can deal with dynamic saved register sizes -- fp
3854 regs could be 32 bits wide in one frame and 64 on the frame above
3857 static struct type *
3858 mips_float_register_type (void)
3860 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3861 return builtin_type_ieee_single_big;
3863 return builtin_type_ieee_single_little;
3866 static struct type *
3867 mips_double_register_type (void)
3869 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3870 return builtin_type_ieee_double_big;
3872 return builtin_type_ieee_double_little;
3875 /* Copy a 32-bit single-precision value from the current frame
3876 into rare_buffer. */
3879 mips_read_fp_register_single (int regno, char *rare_buffer)
3881 int raw_size = REGISTER_RAW_SIZE (regno);
3882 char *raw_buffer = alloca (raw_size);
3884 if (!frame_register_read (selected_frame, regno, raw_buffer))
3885 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3888 /* We have a 64-bit value for this register. Find the low-order
3892 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3897 memcpy (rare_buffer, raw_buffer + offset, 4);
3901 memcpy (rare_buffer, raw_buffer, 4);
3905 /* Copy a 64-bit double-precision value from the current frame into
3906 rare_buffer. This may include getting half of it from the next
3910 mips_read_fp_register_double (int regno, char *rare_buffer)
3912 int raw_size = REGISTER_RAW_SIZE (regno);
3914 if (raw_size == 8 && !mips2_fp_compat ())
3916 /* We have a 64-bit value for this register, and we should use
3918 if (!frame_register_read (selected_frame, regno, rare_buffer))
3919 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
3923 if ((regno - FP0_REGNUM) & 1)
3924 internal_error (__FILE__, __LINE__,
3925 "mips_read_fp_register_double: bad access to "
3926 "odd-numbered FP register");
3928 /* mips_read_fp_register_single will find the correct 32 bits from
3930 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3932 mips_read_fp_register_single (regno, rare_buffer + 4);
3933 mips_read_fp_register_single (regno + 1, rare_buffer);
3937 mips_read_fp_register_single (regno, rare_buffer);
3938 mips_read_fp_register_single (regno + 1, rare_buffer + 4);
3944 mips_print_register (int regnum, int all)
3946 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
3948 /* Get the data in raw format. */
3949 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3951 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
3955 /* If we have a actual 32-bit floating point register (or we are in
3956 32-bit compatibility mode), and the register is even-numbered,
3957 also print it as a double (spanning two registers). */
3958 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
3959 && (REGISTER_RAW_SIZE (regnum) == 4
3960 || mips2_fp_compat ())
3961 && !((regnum - FP0_REGNUM) & 1))
3963 char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE);
3965 mips_read_fp_register_double (regnum, dbuffer);
3967 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
3968 val_print (mips_double_register_type (), dbuffer, 0, 0,
3969 gdb_stdout, 0, 1, 0, Val_pretty_default);
3970 printf_filtered ("); ");
3972 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3974 /* The problem with printing numeric register names (r26, etc.) is that
3975 the user can't use them on input. Probably the best solution is to
3976 fix it so that either the numeric or the funky (a2, etc.) names
3977 are accepted on input. */
3978 if (regnum < MIPS_NUMREGS)
3979 printf_filtered ("(r%d): ", regnum);
3981 printf_filtered (": ");
3983 /* If virtual format is floating, print it that way. */
3984 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
3985 if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
3987 /* We have a meaningful 64-bit value in this register. Show
3988 it as a 32-bit float and a 64-bit double. */
3989 int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
3991 printf_filtered (" (float) ");
3992 val_print (mips_float_register_type (), raw_buffer + offset, 0, 0,
3993 gdb_stdout, 0, 1, 0, Val_pretty_default);
3994 printf_filtered (", (double) ");
3995 val_print (mips_double_register_type (), raw_buffer, 0, 0,
3996 gdb_stdout, 0, 1, 0, Val_pretty_default);
3999 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4000 gdb_stdout, 0, 1, 0, Val_pretty_default);
4001 /* Else print as integer in hex. */
4006 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4007 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4011 print_scalar_formatted (raw_buffer + offset,
4012 REGISTER_VIRTUAL_TYPE (regnum),
4013 'x', 0, gdb_stdout);
4017 /* Replacement for generic do_registers_info.
4018 Print regs in pretty columns. */
4021 do_fp_register_row (int regnum)
4022 { /* do values for FP (float) regs */
4024 double doub, flt1, flt2; /* doubles extracted from raw hex data */
4025 int inv1, inv2, inv3;
4027 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
4029 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
4031 /* 4-byte registers: we can fit two registers per row. */
4032 /* Also print every pair of 4-byte regs as an 8-byte double. */
4033 mips_read_fp_register_single (regnum, raw_buffer);
4034 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4036 mips_read_fp_register_single (regnum + 1, raw_buffer);
4037 flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2);
4039 mips_read_fp_register_double (regnum, raw_buffer);
4040 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
4042 printf_filtered (" %-5s", REGISTER_NAME (regnum));
4044 printf_filtered (": <invalid float>");
4046 printf_filtered ("%-17.9g", flt1);
4048 printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
4050 printf_filtered (": <invalid float>");
4052 printf_filtered ("%-17.9g", flt2);
4054 printf_filtered (" dbl: ");
4056 printf_filtered ("<invalid double>");
4058 printf_filtered ("%-24.17g", doub);
4059 printf_filtered ("\n");
4061 /* may want to do hex display here (future enhancement) */
4066 /* Eight byte registers: print each one as float AND as double. */
4067 mips_read_fp_register_single (regnum, raw_buffer);
4068 flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1);
4070 mips_read_fp_register_double (regnum, raw_buffer);
4071 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
4073 printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
4075 printf_filtered ("<invalid float>");
4077 printf_filtered ("flt: %-17.9g", flt1);
4079 printf_filtered (" dbl: ");
4081 printf_filtered ("<invalid double>");
4083 printf_filtered ("%-24.17g", doub);
4085 printf_filtered ("\n");
4086 /* may want to do hex display here (future enhancement) */
4092 /* Print a row's worth of GP (int) registers, with name labels above */
4095 do_gp_register_row (int regnum)
4097 /* do values for GP (int) regs */
4098 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4099 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
4101 int start_regnum = regnum;
4102 int numregs = NUM_REGS;
4105 /* For GP registers, we print a separate row of names above the vals */
4106 printf_filtered (" ");
4107 for (col = 0; col < ncols && regnum < numregs; regnum++)
4109 if (*REGISTER_NAME (regnum) == '\0')
4110 continue; /* unused register */
4111 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4112 break; /* end the row: reached FP register */
4113 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
4114 REGISTER_NAME (regnum));
4117 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
4118 start_regnum); /* print the R0 to R31 names */
4120 regnum = start_regnum; /* go back to start of row */
4121 /* now print the values in hex, 4 or 8 to the row */
4122 for (col = 0; col < ncols && regnum < numregs; regnum++)
4124 if (*REGISTER_NAME (regnum) == '\0')
4125 continue; /* unused register */
4126 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4127 break; /* end row: reached FP register */
4128 /* OK: get the data in raw format. */
4129 if (!frame_register_read (selected_frame, regnum, raw_buffer))
4130 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4131 /* pad small registers */
4132 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
4133 printf_filtered (" ");
4134 /* Now print the register value in hex, endian order. */
4135 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4136 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4137 byte < REGISTER_RAW_SIZE (regnum);
4139 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
4141 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
4144 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
4145 printf_filtered (" ");
4148 if (col > 0) /* ie. if we actually printed anything... */
4149 printf_filtered ("\n");
4154 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4157 mips_do_registers_info (int regnum, int fpregs)
4159 if (regnum != -1) /* do one specified register */
4161 if (*(REGISTER_NAME (regnum)) == '\0')
4162 error ("Not a valid register for the current processor type");
4164 mips_print_register (regnum, 0);
4165 printf_filtered ("\n");
4168 /* do all (or most) registers */
4171 while (regnum < NUM_REGS)
4173 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4174 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
4175 regnum = do_fp_register_row (regnum); /* FP regs */
4177 regnum += MIPS_NUMREGS; /* skip floating point regs */
4179 regnum = do_gp_register_row (regnum); /* GP (int) regs */
4184 /* Is this a branch with a delay slot? */
4186 static int is_delayed (unsigned long);
4189 is_delayed (unsigned long insn)
4192 for (i = 0; i < NUMOPCODES; ++i)
4193 if (mips_opcodes[i].pinfo != INSN_MACRO
4194 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4196 return (i < NUMOPCODES
4197 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4198 | INSN_COND_BRANCH_DELAY
4199 | INSN_COND_BRANCH_LIKELY)));
4203 mips_step_skips_delay (CORE_ADDR pc)
4205 char buf[MIPS_INSTLEN];
4207 /* There is no branch delay slot on MIPS16. */
4208 if (pc_is_mips16 (pc))
4211 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4212 /* If error reading memory, guess that it is not a delayed branch. */
4214 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
4218 /* Skip the PC past function prologue instructions (32-bit version).
4219 This is a helper function for mips_skip_prologue. */
4222 mips32_skip_prologue (CORE_ADDR pc)
4226 int seen_sp_adjust = 0;
4227 int load_immediate_bytes = 0;
4229 /* Skip the typical prologue instructions. These are the stack adjustment
4230 instruction and the instructions that save registers on the stack
4231 or in the gcc frame. */
4232 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
4234 unsigned long high_word;
4236 inst = mips_fetch_instruction (pc);
4237 high_word = (inst >> 16) & 0xffff;
4239 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4240 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4242 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4243 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4245 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4246 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4247 && (inst & 0x001F0000)) /* reg != $zero */
4250 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4252 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4254 continue; /* reg != $zero */
4256 /* move $s8,$sp. With different versions of gas this will be either
4257 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4258 Accept any one of these. */
4259 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4262 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4264 else if (high_word == 0x3c1c) /* lui $gp,n */
4266 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4268 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4269 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4271 /* The following instructions load $at or $t0 with an immediate
4272 value in preparation for a stack adjustment via
4273 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4274 a local variable, so we accept them only before a stack adjustment
4275 instruction was seen. */
4276 else if (!seen_sp_adjust)
4278 if (high_word == 0x3c01 || /* lui $at,n */
4279 high_word == 0x3c08) /* lui $t0,n */
4281 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4284 else if (high_word == 0x3421 || /* ori $at,$at,n */
4285 high_word == 0x3508 || /* ori $t0,$t0,n */
4286 high_word == 0x3401 || /* ori $at,$zero,n */
4287 high_word == 0x3408) /* ori $t0,$zero,n */
4289 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4299 /* In a frameless function, we might have incorrectly
4300 skipped some load immediate instructions. Undo the skipping
4301 if the load immediate was not followed by a stack adjustment. */
4302 if (load_immediate_bytes && !seen_sp_adjust)
4303 pc -= load_immediate_bytes;
4307 /* Skip the PC past function prologue instructions (16-bit version).
4308 This is a helper function for mips_skip_prologue. */
4311 mips16_skip_prologue (CORE_ADDR pc)
4314 int extend_bytes = 0;
4315 int prev_extend_bytes;
4317 /* Table of instructions likely to be found in a function prologue. */
4320 unsigned short inst;
4321 unsigned short mask;
4328 , /* addiu $sp,offset */
4332 , /* daddiu $sp,offset */
4336 , /* sw reg,n($sp) */
4340 , /* sd reg,n($sp) */
4344 , /* sw $ra,n($sp) */
4348 , /* sd $ra,n($sp) */
4356 , /* sw $a0-$a3,n($s1) */
4360 , /* move reg,$a0-$a3 */
4364 , /* entry pseudo-op */
4368 , /* addiu $s1,$sp,n */
4371 } /* end of table marker */
4374 /* Skip the typical prologue instructions. These are the stack adjustment
4375 instruction and the instructions that save registers on the stack
4376 or in the gcc frame. */
4377 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
4379 unsigned short inst;
4382 inst = mips_fetch_instruction (pc);
4384 /* Normally we ignore an extend instruction. However, if it is
4385 not followed by a valid prologue instruction, we must adjust
4386 the pc back over the extend so that it won't be considered
4387 part of the prologue. */
4388 if ((inst & 0xf800) == 0xf000) /* extend */
4390 extend_bytes = MIPS16_INSTLEN;
4393 prev_extend_bytes = extend_bytes;
4396 /* Check for other valid prologue instructions besides extend. */
4397 for (i = 0; table[i].mask != 0; i++)
4398 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4400 if (table[i].mask != 0) /* it was in table? */
4401 continue; /* ignore it */
4405 /* Return the current pc, adjusted backwards by 2 if
4406 the previous instruction was an extend. */
4407 return pc - prev_extend_bytes;
4413 /* To skip prologues, I use this predicate. Returns either PC itself
4414 if the code at PC does not look like a function prologue; otherwise
4415 returns an address that (if we're lucky) follows the prologue. If
4416 LENIENT, then we must skip everything which is involved in setting
4417 up the frame (it's OK to skip more, just so long as we don't skip
4418 anything which might clobber the registers which are being saved.
4419 We must skip more in the case where part of the prologue is in the
4420 delay slot of a non-prologue instruction). */
4423 mips_skip_prologue (CORE_ADDR pc)
4425 /* See if we can determine the end of the prologue via the symbol table.
4426 If so, then return either PC, or the PC after the prologue, whichever
4429 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4431 if (post_prologue_pc != 0)
4432 return max (pc, post_prologue_pc);
4434 /* Can't determine prologue from the symbol table, need to examine
4437 if (pc_is_mips16 (pc))
4438 return mips16_skip_prologue (pc);
4440 return mips32_skip_prologue (pc);
4443 /* Determine how a return value is stored within the MIPS register
4444 file, given the return type `valtype'. */
4446 struct return_value_word
4455 return_value_location (struct type *valtype,
4456 struct return_value_word *hi,
4457 struct return_value_word *lo)
4459 int len = TYPE_LENGTH (valtype);
4461 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
4462 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
4463 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
4465 if (!FP_REGISTER_DOUBLE && len == 8)
4467 /* We need to break a 64bit float in two 32 bit halves and
4468 spread them across a floating-point register pair. */
4469 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
4470 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
4471 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4472 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
4474 hi->reg_offset = lo->reg_offset;
4475 lo->reg = FP0_REGNUM + 0;
4476 hi->reg = FP0_REGNUM + 1;
4482 /* The floating point value fits in a single floating-point
4484 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4485 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
4488 lo->reg = FP0_REGNUM;
4499 /* Locate a result possibly spread across two registers. */
4501 lo->reg = regnum + 0;
4502 hi->reg = regnum + 1;
4503 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4504 && len < MIPS_SAVED_REGSIZE)
4506 /* "un-left-justify" the value in the low register */
4507 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
4512 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4513 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
4514 && len < MIPS_SAVED_REGSIZE * 2
4515 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
4516 TYPE_CODE (valtype) == TYPE_CODE_UNION))
4518 /* "un-left-justify" the value spread across two registers. */
4519 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
4520 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
4522 hi->len = len - lo->len;
4526 /* Only perform a partial copy of the second register. */
4529 if (len > MIPS_SAVED_REGSIZE)
4531 lo->len = MIPS_SAVED_REGSIZE;
4532 hi->len = len - MIPS_SAVED_REGSIZE;
4540 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4541 && REGISTER_RAW_SIZE (regnum) == 8
4542 && MIPS_SAVED_REGSIZE == 4)
4544 /* Account for the fact that only the least-signficant part
4545 of the register is being used */
4546 lo->reg_offset += 4;
4547 hi->reg_offset += 4;
4550 hi->buf_offset = lo->len;
4554 /* Given a return value in `regbuf' with a type `valtype', extract and
4555 copy its value into `valbuf'. */
4558 mips_eabi_extract_return_value (struct type *valtype,
4559 char regbuf[REGISTER_BYTES],
4562 struct return_value_word lo;
4563 struct return_value_word hi;
4564 return_value_location (valtype, &hi, &lo);
4566 memcpy (valbuf + lo.buf_offset,
4567 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4571 memcpy (valbuf + hi.buf_offset,
4572 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4577 mips_o64_extract_return_value (struct type *valtype,
4578 char regbuf[REGISTER_BYTES],
4581 struct return_value_word lo;
4582 struct return_value_word hi;
4583 return_value_location (valtype, &hi, &lo);
4585 memcpy (valbuf + lo.buf_offset,
4586 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
4590 memcpy (valbuf + hi.buf_offset,
4591 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
4595 /* Given a return value in `valbuf' with a type `valtype', write it's
4596 value into the appropriate register. */
4599 mips_eabi_store_return_value (struct type *valtype, char *valbuf)
4601 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4602 struct return_value_word lo;
4603 struct return_value_word hi;
4604 return_value_location (valtype, &hi, &lo);
4606 memset (raw_buffer, 0, sizeof (raw_buffer));
4607 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4608 write_register_bytes (REGISTER_BYTE (lo.reg),
4610 REGISTER_RAW_SIZE (lo.reg));
4614 memset (raw_buffer, 0, sizeof (raw_buffer));
4615 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4616 write_register_bytes (REGISTER_BYTE (hi.reg),
4618 REGISTER_RAW_SIZE (hi.reg));
4623 mips_o64_store_return_value (struct type *valtype, char *valbuf)
4625 char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
4626 struct return_value_word lo;
4627 struct return_value_word hi;
4628 return_value_location (valtype, &hi, &lo);
4630 memset (raw_buffer, 0, sizeof (raw_buffer));
4631 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4632 write_register_bytes (REGISTER_BYTE (lo.reg),
4634 REGISTER_RAW_SIZE (lo.reg));
4638 memset (raw_buffer, 0, sizeof (raw_buffer));
4639 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4640 write_register_bytes (REGISTER_BYTE (hi.reg),
4642 REGISTER_RAW_SIZE (hi.reg));
4646 /* O32 ABI stuff. */
4649 mips_o32_xfer_return_value (struct type *type,
4650 struct regcache *regcache,
4651 bfd_byte *in, const bfd_byte *out)
4653 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4654 if (TYPE_CODE (type) == TYPE_CODE_FLT
4655 && TYPE_LENGTH (type) == 4
4656 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4658 /* A single-precision floating-point value. It fits in the
4659 least significant part of FP0. */
4661 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4662 mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type),
4663 TARGET_BYTE_ORDER, in, out, 0);
4665 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4666 && TYPE_LENGTH (type) == 8
4667 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4669 /* A double-precision floating-point value. It fits in the
4670 least significant part of FP0/FP1 but with byte ordering
4671 based on the target (???). */
4673 fprintf_unfiltered (gdb_stderr, "Return float in $fp0/$fp1\n");
4674 switch (TARGET_BYTE_ORDER)
4676 case BFD_ENDIAN_LITTLE:
4677 mips_xfer_register (regcache, FP0_REGNUM + 0, 4,
4678 TARGET_BYTE_ORDER, in, out, 0);
4679 mips_xfer_register (regcache, FP0_REGNUM + 1, 4,
4680 TARGET_BYTE_ORDER, in, out, 4);
4682 case BFD_ENDIAN_BIG:
4683 mips_xfer_register (regcache, FP0_REGNUM + 1, 4,
4684 TARGET_BYTE_ORDER, in, out, 0);
4685 mips_xfer_register (regcache, FP0_REGNUM + 0, 4,
4686 TARGET_BYTE_ORDER, in, out, 4);
4689 internal_error (__FILE__, __LINE__, "bad switch");
4693 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4694 && TYPE_NFIELDS (type) <= 2
4695 && TYPE_NFIELDS (type) >= 1
4696 && ((TYPE_NFIELDS (type) == 1
4697 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4699 || (TYPE_NFIELDS (type) == 2
4700 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4702 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4704 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4706 /* A struct that contains one or two floats. Each value is part
4707 in the least significant part of their floating point
4709 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
4712 for (field = 0, regnum = FP0_REGNUM;
4713 field < TYPE_NFIELDS (type);
4714 field++, regnum += 2)
4716 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4719 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4720 mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4721 TARGET_BYTE_ORDER, in, out, offset);
4726 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4727 || TYPE_CODE (type) == TYPE_CODE_UNION)
4729 /* A structure or union. Extract the left justified value,
4730 regardless of the byte order. I.e. DO NOT USE
4734 for (offset = 0, regnum = V0_REGNUM;
4735 offset < TYPE_LENGTH (type);
4736 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4738 int xfer = REGISTER_RAW_SIZE (regnum);
4739 if (offset + xfer > TYPE_LENGTH (type))
4740 xfer = TYPE_LENGTH (type) - offset;
4742 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4743 offset, xfer, regnum);
4744 mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN,
4751 /* A scalar extract each part but least-significant-byte
4752 justified. o32 thinks registers are 4 byte, regardless of
4753 the ISA. mips_stack_argsize controls this. */
4756 for (offset = 0, regnum = V0_REGNUM;
4757 offset < TYPE_LENGTH (type);
4758 offset += mips_stack_argsize (), regnum++)
4760 int xfer = mips_stack_argsize ();
4762 if (offset + xfer > TYPE_LENGTH (type))
4763 xfer = TYPE_LENGTH (type) - offset;
4765 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4766 offset, xfer, regnum);
4767 mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER,
4774 mips_o32_extract_return_value (struct type *type,
4775 struct regcache *regcache,
4778 mips_o32_xfer_return_value (type, regcache, valbuf, NULL);
4782 mips_o32_store_return_value (struct type *type, char *valbuf)
4784 mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf);
4787 /* N32/N44 ABI stuff. */
4790 mips_n32n64_xfer_return_value (struct type *type,
4791 struct regcache *regcache,
4792 bfd_byte *in, const bfd_byte *out)
4794 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4795 if (TYPE_CODE (type) == TYPE_CODE_FLT
4796 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4798 /* A floating-point value belongs in the least significant part
4801 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4802 mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type),
4803 TARGET_BYTE_ORDER, in, out, 0);
4805 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4806 && TYPE_NFIELDS (type) <= 2
4807 && TYPE_NFIELDS (type) >= 1
4808 && ((TYPE_NFIELDS (type) == 1
4809 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4811 || (TYPE_NFIELDS (type) == 2
4812 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4814 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4816 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4818 /* A struct that contains one or two floats. Each value is part
4819 in the least significant part of their floating point
4821 bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE);
4824 for (field = 0, regnum = FP0_REGNUM;
4825 field < TYPE_NFIELDS (type);
4826 field++, regnum += 2)
4828 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4831 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4832 mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4833 TARGET_BYTE_ORDER, in, out, offset);
4836 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4837 || TYPE_CODE (type) == TYPE_CODE_UNION)
4839 /* A structure or union. Extract the left justified value,
4840 regardless of the byte order. I.e. DO NOT USE
4844 for (offset = 0, regnum = V0_REGNUM;
4845 offset < TYPE_LENGTH (type);
4846 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4848 int xfer = REGISTER_RAW_SIZE (regnum);
4849 if (offset + xfer > TYPE_LENGTH (type))
4850 xfer = TYPE_LENGTH (type) - offset;
4852 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4853 offset, xfer, regnum);
4854 mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN,
4860 /* A scalar extract each part but least-significant-byte
4864 for (offset = 0, regnum = V0_REGNUM;
4865 offset < TYPE_LENGTH (type);
4866 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4868 int xfer = REGISTER_RAW_SIZE (regnum);
4870 if (offset + xfer > TYPE_LENGTH (type))
4871 xfer = TYPE_LENGTH (type) - offset;
4873 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4874 offset, xfer, regnum);
4875 mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER,
4882 mips_n32n64_extract_return_value (struct type *type,
4883 struct regcache *regcache,
4886 mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL);
4890 mips_n32n64_store_return_value (struct type *type, char *valbuf)
4892 mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf);
4896 mips_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
4898 /* Nothing to do -- push_arguments does all the work. */
4902 mips_extract_struct_value_address (struct regcache *ignore)
4904 /* FIXME: This will only work at random. The caller passes the
4905 struct_return address in V0, but it is not preserved. It may
4906 still be there, or this may be a random value. */
4907 return read_register (V0_REGNUM);
4910 /* Exported procedure: Is PC in the signal trampoline code */
4913 mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore)
4915 if (sigtramp_address == 0)
4917 return (pc >= sigtramp_address && pc < sigtramp_end);
4920 /* Root of all "set mips "/"show mips " commands. This will eventually be
4921 used for all MIPS-specific commands. */
4924 show_mips_command (char *args, int from_tty)
4926 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4930 set_mips_command (char *args, int from_tty)
4932 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4933 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4936 /* Commands to show/set the MIPS FPU type. */
4939 show_mipsfpu_command (char *args, int from_tty)
4942 switch (MIPS_FPU_TYPE)
4944 case MIPS_FPU_SINGLE:
4945 fpu = "single-precision";
4947 case MIPS_FPU_DOUBLE:
4948 fpu = "double-precision";
4951 fpu = "absent (none)";
4954 internal_error (__FILE__, __LINE__, "bad switch");
4956 if (mips_fpu_type_auto)
4957 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4960 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
4966 set_mipsfpu_command (char *args, int from_tty)
4968 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4969 show_mipsfpu_command (args, from_tty);
4973 set_mipsfpu_single_command (char *args, int from_tty)
4975 mips_fpu_type = MIPS_FPU_SINGLE;
4976 mips_fpu_type_auto = 0;
4977 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
4981 set_mipsfpu_double_command (char *args, int from_tty)
4983 mips_fpu_type = MIPS_FPU_DOUBLE;
4984 mips_fpu_type_auto = 0;
4985 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
4989 set_mipsfpu_none_command (char *args, int from_tty)
4991 mips_fpu_type = MIPS_FPU_NONE;
4992 mips_fpu_type_auto = 0;
4993 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
4997 set_mipsfpu_auto_command (char *args, int from_tty)
4999 mips_fpu_type_auto = 1;
5002 /* Command to set the processor type. */
5005 mips_set_processor_type_command (char *args, int from_tty)
5009 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
5011 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5012 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5013 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
5015 /* Restore the value. */
5016 tmp_mips_processor_type = xstrdup (mips_processor_type);
5021 if (!mips_set_processor_type (tmp_mips_processor_type))
5023 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
5024 /* Restore its value. */
5025 tmp_mips_processor_type = xstrdup (mips_processor_type);
5030 mips_show_processor_type_command (char *args, int from_tty)
5034 /* Modify the actual processor type. */
5037 mips_set_processor_type (char *str)
5044 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5046 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
5048 mips_processor_type = str;
5049 mips_processor_reg_names = mips_processor_type_table[i].regnames;
5051 /* FIXME tweak fpu flag too */
5058 /* Attempt to identify the particular processor model by reading the
5062 mips_read_processor_type (void)
5066 prid = read_register (PRID_REGNUM);
5068 if ((prid & ~0xf) == 0x700)
5069 return savestring ("r3041", strlen ("r3041"));
5074 /* Just like reinit_frame_cache, but with the right arguments to be
5075 callable as an sfunc. */
5078 reinit_frame_cache_sfunc (char *args, int from_tty,
5079 struct cmd_list_element *c)
5081 reinit_frame_cache ();
5085 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
5087 mips_extra_func_info_t proc_desc;
5089 /* Search for the function containing this address. Set the low bit
5090 of the address when searching, in case we were given an even address
5091 that is the start of a 16-bit function. If we didn't do this,
5092 the search would fail because the symbol table says the function
5093 starts at an odd address, i.e. 1 byte past the given address. */
5094 memaddr = ADDR_BITS_REMOVE (memaddr);
5095 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
5097 /* Make an attempt to determine if this is a 16-bit function. If
5098 the procedure descriptor exists and the address therein is odd,
5099 it's definitely a 16-bit function. Otherwise, we have to just
5100 guess that if the address passed in is odd, it's 16-bits. */
5102 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
5103 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
5105 info->mach = pc_is_mips16 (memaddr) ?
5106 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
5108 /* Round down the instruction address to the appropriate boundary. */
5109 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
5111 /* Call the appropriate disassembler based on the target endian-ness. */
5112 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5113 return print_insn_big_mips (memaddr, info);
5115 return print_insn_little_mips (memaddr, info);
5118 /* Old-style breakpoint macros.
5119 The IDT board uses an unusual breakpoint value, and sometimes gets
5120 confused when it sees the usual MIPS breakpoint instruction. */
5122 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
5123 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
5124 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
5125 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
5126 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
5127 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
5128 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
5129 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
5131 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5132 counter value to determine whether a 16- or 32-bit breakpoint should be
5133 used. It returns a pointer to a string of bytes that encode a breakpoint
5134 instruction, stores the length of the string to *lenptr, and adjusts pc
5135 (if necessary) to point to the actual memory location where the
5136 breakpoint should be inserted. */
5138 static const unsigned char *
5139 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
5141 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5143 if (pc_is_mips16 (*pcptr))
5145 static unsigned char mips16_big_breakpoint[] =
5146 MIPS16_BIG_BREAKPOINT;
5147 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
5148 *lenptr = sizeof (mips16_big_breakpoint);
5149 return mips16_big_breakpoint;
5153 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
5154 static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
5155 static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
5157 *lenptr = sizeof (big_breakpoint);
5159 if (strcmp (target_shortname, "mips") == 0)
5160 return idt_big_breakpoint;
5161 else if (strcmp (target_shortname, "ddb") == 0
5162 || strcmp (target_shortname, "pmon") == 0
5163 || strcmp (target_shortname, "lsi") == 0)
5164 return pmon_big_breakpoint;
5166 return big_breakpoint;
5171 if (pc_is_mips16 (*pcptr))
5173 static unsigned char mips16_little_breakpoint[] =
5174 MIPS16_LITTLE_BREAKPOINT;
5175 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
5176 *lenptr = sizeof (mips16_little_breakpoint);
5177 return mips16_little_breakpoint;
5181 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
5182 static unsigned char pmon_little_breakpoint[] =
5183 PMON_LITTLE_BREAKPOINT;
5184 static unsigned char idt_little_breakpoint[] =
5185 IDT_LITTLE_BREAKPOINT;
5187 *lenptr = sizeof (little_breakpoint);
5189 if (strcmp (target_shortname, "mips") == 0)
5190 return idt_little_breakpoint;
5191 else if (strcmp (target_shortname, "ddb") == 0
5192 || strcmp (target_shortname, "pmon") == 0
5193 || strcmp (target_shortname, "lsi") == 0)
5194 return pmon_little_breakpoint;
5196 return little_breakpoint;
5201 /* If PC is in a mips16 call or return stub, return the address of the target
5202 PC, which is either the callee or the caller. There are several
5203 cases which must be handled:
5205 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5206 target PC is in $31 ($ra).
5207 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5208 and the target PC is in $2.
5209 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5210 before the jal instruction, this is effectively a call stub
5211 and the the target PC is in $2. Otherwise this is effectively
5212 a return stub and the target PC is in $18.
5214 See the source code for the stubs in gcc/config/mips/mips16.S for
5217 This function implements the SKIP_TRAMPOLINE_CODE macro.
5221 mips_skip_stub (CORE_ADDR pc)
5224 CORE_ADDR start_addr;
5226 /* Find the starting address and name of the function containing the PC. */
5227 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5230 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5231 target PC is in $31 ($ra). */
5232 if (strcmp (name, "__mips16_ret_sf") == 0
5233 || strcmp (name, "__mips16_ret_df") == 0)
5234 return read_signed_register (RA_REGNUM);
5236 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5238 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5239 and the target PC is in $2. */
5240 if (name[19] >= '0' && name[19] <= '9')
5241 return read_signed_register (2);
5243 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5244 before the jal instruction, this is effectively a call stub
5245 and the the target PC is in $2. Otherwise this is effectively
5246 a return stub and the target PC is in $18. */
5247 else if (name[19] == 's' || name[19] == 'd')
5249 if (pc == start_addr)
5251 /* Check if the target of the stub is a compiler-generated
5252 stub. Such a stub for a function bar might have a name
5253 like __fn_stub_bar, and might look like this:
5258 la $1,bar (becomes a lui/addiu pair)
5260 So scan down to the lui/addi and extract the target
5261 address from those two instructions. */
5263 CORE_ADDR target_pc = read_signed_register (2);
5267 /* See if the name of the target function is __fn_stub_*. */
5268 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
5270 if (strncmp (name, "__fn_stub_", 10) != 0
5271 && strcmp (name, "etext") != 0
5272 && strcmp (name, "_etext") != 0)
5275 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5276 The limit on the search is arbitrarily set to 20
5277 instructions. FIXME. */
5278 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5280 inst = mips_fetch_instruction (target_pc);
5281 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5282 pc = (inst << 16) & 0xffff0000; /* high word */
5283 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5284 return pc | (inst & 0xffff); /* low word */
5287 /* Couldn't find the lui/addui pair, so return stub address. */
5291 /* This is the 'return' part of a call stub. The return
5292 address is in $r18. */
5293 return read_signed_register (18);
5296 return 0; /* not a stub */
5300 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5301 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5304 mips_in_call_stub (CORE_ADDR pc, char *name)
5306 CORE_ADDR start_addr;
5308 /* Find the starting address of the function containing the PC. If the
5309 caller didn't give us a name, look it up at the same time. */
5310 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
5313 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5315 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5316 if (name[19] >= '0' && name[19] <= '9')
5318 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5319 before the jal instruction, this is effectively a call stub. */
5320 else if (name[19] == 's' || name[19] == 'd')
5321 return pc == start_addr;
5324 return 0; /* not a stub */
5328 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5329 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5332 mips_in_return_stub (CORE_ADDR pc, char *name)
5334 CORE_ADDR start_addr;
5336 /* Find the starting address of the function containing the PC. */
5337 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5340 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5341 if (strcmp (name, "__mips16_ret_sf") == 0
5342 || strcmp (name, "__mips16_ret_df") == 0)
5345 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5346 i.e. after the jal instruction, this is effectively a return stub. */
5347 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5348 && (name[19] == 's' || name[19] == 'd')
5349 && pc != start_addr)
5352 return 0; /* not a stub */
5356 /* Return non-zero if the PC is in a library helper function that should
5357 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5360 mips_ignore_helper (CORE_ADDR pc)
5364 /* Find the starting address and name of the function containing the PC. */
5365 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5368 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5369 that we want to ignore. */
5370 return (strcmp (name, "__mips16_ret_sf") == 0
5371 || strcmp (name, "__mips16_ret_df") == 0);
5375 /* Return a location where we can set a breakpoint that will be hit
5376 when an inferior function call returns. This is normally the
5377 program's entry point. Executables that don't have an entry
5378 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
5379 whose address is the location where the breakpoint should be placed. */
5382 mips_call_dummy_address (void)
5384 struct minimal_symbol *sym;
5386 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
5388 return SYMBOL_VALUE_ADDRESS (sym);
5390 return entry_point_address ();
5394 /* If the current gcc for this target does not produce correct debugging
5395 information for float parameters, both prototyped and unprototyped, then
5396 define this macro. This forces gdb to always assume that floats are
5397 passed as doubles and then converted in the callee.
5399 For the mips chip, it appears that the debug info marks the parameters as
5400 floats regardless of whether the function is prototyped, but the actual
5401 values are passed as doubles for the non-prototyped case and floats for
5402 the prototyped case. Thus we choose to make the non-prototyped case work
5403 for C and break the prototyped case, since the non-prototyped case is
5404 probably much more common. (FIXME). */
5407 mips_coerce_float_to_double (struct type *formal, struct type *actual)
5409 return current_language->la_language == language_c;
5412 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5413 the register stored on the stack (32) is different to its real raw
5414 size (64). The below ensures that registers are fetched from the
5415 stack using their ABI size and then stored into the RAW_BUFFER
5416 using their raw size.
5418 The alternative to adding this function would be to add an ABI
5419 macro - REGISTER_STACK_SIZE(). */
5422 mips_get_saved_register (char *raw_buffer,
5425 struct frame_info *frame,
5427 enum lval_type *lval)
5431 if (!target_has_registers)
5432 error ("No registers.");
5434 /* Normal systems don't optimize out things with register numbers. */
5435 if (optimized != NULL)
5437 addr = find_saved_register (frame, regnum);
5441 *lval = lval_memory;
5442 if (regnum == SP_REGNUM)
5444 if (raw_buffer != NULL)
5446 /* Put it back in target format. */
5447 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
5454 if (raw_buffer != NULL)
5458 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
5460 val = read_memory_integer (addr, MIPS_SAVED_REGSIZE);
5462 val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum));
5463 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
5469 *lval = lval_register;
5470 addr = REGISTER_BYTE (regnum);
5471 if (raw_buffer != NULL)
5472 read_register_gen (regnum, raw_buffer);
5478 /* Immediately after a function call, return the saved pc.
5479 Can't always go through the frames for this because on some machines
5480 the new frame is not set up until the new function executes
5481 some instructions. */
5484 mips_saved_pc_after_call (struct frame_info *frame)
5486 return read_signed_register (RA_REGNUM);
5490 /* Convert a dbx stab register number (from `r' declaration) to a gdb
5494 mips_stab_reg_to_regnum (int num)
5499 return num + FP0_REGNUM - 38;
5502 /* Convert a ecoff register number to a gdb REGNUM */
5505 mips_ecoff_reg_to_regnum (int num)
5510 return num + FP0_REGNUM - 32;
5513 /* Convert an integer into an address. By first converting the value
5514 into a pointer and then extracting it signed, the address is
5515 guarenteed to be correctly sign extended. */
5518 mips_integer_to_address (struct type *type, void *buf)
5520 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5521 LONGEST val = unpack_long (type, buf);
5522 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5523 return extract_signed_integer (tmp,
5524 TYPE_LENGTH (builtin_type_void_data_ptr));
5528 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5530 enum mips_abi *abip = (enum mips_abi *) obj;
5531 const char *name = bfd_get_section_name (abfd, sect);
5533 if (*abip != MIPS_ABI_UNKNOWN)
5536 if (strncmp (name, ".mdebug.", 8) != 0)
5539 if (strcmp (name, ".mdebug.abi32") == 0)
5540 *abip = MIPS_ABI_O32;
5541 else if (strcmp (name, ".mdebug.abiN32") == 0)
5542 *abip = MIPS_ABI_N32;
5543 else if (strcmp (name, ".mdebug.abiN64") == 0)
5544 *abip = MIPS_ABI_N64;
5545 else if (strcmp (name, ".mdebug.abiO64") == 0)
5546 *abip = MIPS_ABI_O64;
5547 else if (strcmp (name, ".mdebug.eabi32") == 0)
5548 *abip = MIPS_ABI_EABI32;
5549 else if (strcmp (name, ".mdebug.eabi64") == 0)
5550 *abip = MIPS_ABI_EABI64;
5552 warning ("unsupported ABI %s.", name + 8);
5555 static enum mips_abi
5556 global_mips_abi (void)
5560 for (i = 0; mips_abi_strings[i] != NULL; i++)
5561 if (mips_abi_strings[i] == mips_abi_string)
5562 return (enum mips_abi) i;
5564 internal_error (__FILE__, __LINE__,
5565 "unknown ABI string");
5568 static struct gdbarch *
5569 mips_gdbarch_init (struct gdbarch_info info,
5570 struct gdbarch_list *arches)
5572 static LONGEST mips_call_dummy_words[] =
5574 struct gdbarch *gdbarch;
5575 struct gdbarch_tdep *tdep;
5577 enum mips_abi mips_abi, found_abi, wanted_abi;
5578 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
5580 /* Reset the disassembly info, in case it was set to something
5582 tm_print_insn_info.flavour = bfd_target_unknown_flavour;
5583 tm_print_insn_info.arch = bfd_arch_unknown;
5584 tm_print_insn_info.mach = 0;
5590 /* First of all, extract the elf_flags, if available. */
5591 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5592 elf_flags = elf_elfheader (info.abfd)->e_flags;
5594 /* Try to determine the OS ABI of the object we are loading. If
5595 we end up with `unknown', just leave it that way. */
5596 osabi = gdbarch_lookup_osabi (info.abfd);
5599 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5600 switch ((elf_flags & EF_MIPS_ABI))
5602 case E_MIPS_ABI_O32:
5603 mips_abi = MIPS_ABI_O32;
5605 case E_MIPS_ABI_O64:
5606 mips_abi = MIPS_ABI_O64;
5608 case E_MIPS_ABI_EABI32:
5609 mips_abi = MIPS_ABI_EABI32;
5611 case E_MIPS_ABI_EABI64:
5612 mips_abi = MIPS_ABI_EABI64;
5615 if ((elf_flags & EF_MIPS_ABI2))
5616 mips_abi = MIPS_ABI_N32;
5618 mips_abi = MIPS_ABI_UNKNOWN;
5622 /* GCC creates a pseudo-section whose name describes the ABI. */
5623 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5624 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
5626 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5627 Use the ABI from the last architecture if there is one. */
5628 if (info.abfd == NULL && arches != NULL)
5629 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5631 /* Try the architecture for any hint of the correct ABI. */
5632 if (mips_abi == MIPS_ABI_UNKNOWN
5633 && info.bfd_arch_info != NULL
5634 && info.bfd_arch_info->arch == bfd_arch_mips)
5636 switch (info.bfd_arch_info->mach)
5638 case bfd_mach_mips3900:
5639 mips_abi = MIPS_ABI_EABI32;
5641 case bfd_mach_mips4100:
5642 case bfd_mach_mips5000:
5643 mips_abi = MIPS_ABI_EABI64;
5645 case bfd_mach_mips8000:
5646 case bfd_mach_mips10000:
5647 /* On Irix, ELF64 executables use the N64 ABI. The
5648 pseudo-sections which describe the ABI aren't present
5649 on IRIX. (Even for executables created by gcc.) */
5650 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5651 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5652 mips_abi = MIPS_ABI_N64;
5654 mips_abi = MIPS_ABI_N32;
5659 if (mips_abi == MIPS_ABI_UNKNOWN)
5660 mips_abi = MIPS_ABI_O32;
5662 /* Now that we have found what the ABI for this binary would be,
5663 check whether the user is overriding it. */
5664 found_abi = mips_abi;
5665 wanted_abi = global_mips_abi ();
5666 if (wanted_abi != MIPS_ABI_UNKNOWN)
5667 mips_abi = wanted_abi;
5671 fprintf_unfiltered (gdb_stdlog,
5672 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5674 fprintf_unfiltered (gdb_stdlog,
5675 "mips_gdbarch_init: mips_abi = %d\n",
5677 fprintf_unfiltered (gdb_stdlog,
5678 "mips_gdbarch_init: found_mips_abi = %d\n",
5682 /* try to find a pre-existing architecture */
5683 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5685 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5687 /* MIPS needs to be pedantic about which ABI the object is
5689 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5691 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5693 if (gdbarch_tdep (arches->gdbarch)->osabi == osabi)
5694 return arches->gdbarch;
5697 /* Need a new architecture. Fill in a target specific vector. */
5698 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5699 gdbarch = gdbarch_alloc (&info, tdep);
5700 tdep->elf_flags = elf_flags;
5701 tdep->osabi = osabi;
5703 /* Initially set everything according to the default ABI/ISA. */
5704 set_gdbarch_short_bit (gdbarch, 16);
5705 set_gdbarch_int_bit (gdbarch, 32);
5706 set_gdbarch_float_bit (gdbarch, 32);
5707 set_gdbarch_double_bit (gdbarch, 64);
5708 set_gdbarch_long_double_bit (gdbarch, 64);
5709 set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size);
5710 set_gdbarch_max_register_raw_size (gdbarch, 8);
5711 set_gdbarch_max_register_virtual_size (gdbarch, 8);
5712 tdep->found_abi = found_abi;
5713 tdep->mips_abi = mips_abi;
5715 set_gdbarch_elf_make_msymbol_special (gdbarch,
5716 mips_elf_make_msymbol_special);
5721 set_gdbarch_push_arguments (gdbarch, mips_o32_push_arguments);
5722 set_gdbarch_store_return_value (gdbarch, mips_o32_store_return_value);
5723 set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value);
5724 tdep->mips_default_saved_regsize = 4;
5725 tdep->mips_default_stack_argsize = 4;
5726 tdep->mips_fp_register_double = 0;
5727 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5728 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5729 tdep->gdb_target_is_mips64 = 0;
5730 tdep->default_mask_address_p = 0;
5731 set_gdbarch_long_bit (gdbarch, 32);
5732 set_gdbarch_ptr_bit (gdbarch, 32);
5733 set_gdbarch_long_long_bit (gdbarch, 64);
5734 set_gdbarch_reg_struct_has_addr (gdbarch,
5735 mips_o32_reg_struct_has_addr);
5736 set_gdbarch_use_struct_convention (gdbarch,
5737 mips_o32_use_struct_convention);
5740 set_gdbarch_push_arguments (gdbarch, mips_o64_push_arguments);
5741 set_gdbarch_store_return_value (gdbarch, mips_o64_store_return_value);
5742 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value);
5743 tdep->mips_default_saved_regsize = 8;
5744 tdep->mips_default_stack_argsize = 8;
5745 tdep->mips_fp_register_double = 1;
5746 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5747 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5748 tdep->gdb_target_is_mips64 = 1;
5749 tdep->default_mask_address_p = 0;
5750 set_gdbarch_long_bit (gdbarch, 32);
5751 set_gdbarch_ptr_bit (gdbarch, 32);
5752 set_gdbarch_long_long_bit (gdbarch, 64);
5753 set_gdbarch_reg_struct_has_addr (gdbarch,
5754 mips_o32_reg_struct_has_addr);
5755 set_gdbarch_use_struct_convention (gdbarch,
5756 mips_o32_use_struct_convention);
5758 case MIPS_ABI_EABI32:
5759 set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments);
5760 set_gdbarch_store_return_value (gdbarch, mips_eabi_store_return_value);
5761 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5762 tdep->mips_default_saved_regsize = 4;
5763 tdep->mips_default_stack_argsize = 4;
5764 tdep->mips_fp_register_double = 0;
5765 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5766 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5767 tdep->gdb_target_is_mips64 = 0;
5768 tdep->default_mask_address_p = 0;
5769 set_gdbarch_long_bit (gdbarch, 32);
5770 set_gdbarch_ptr_bit (gdbarch, 32);
5771 set_gdbarch_long_long_bit (gdbarch, 64);
5772 set_gdbarch_reg_struct_has_addr (gdbarch,
5773 mips_eabi_reg_struct_has_addr);
5774 set_gdbarch_use_struct_convention (gdbarch,
5775 mips_eabi_use_struct_convention);
5777 case MIPS_ABI_EABI64:
5778 set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments);
5779 set_gdbarch_store_return_value (gdbarch, mips_eabi_store_return_value);
5780 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5781 tdep->mips_default_saved_regsize = 8;
5782 tdep->mips_default_stack_argsize = 8;
5783 tdep->mips_fp_register_double = 1;
5784 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5785 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5786 tdep->gdb_target_is_mips64 = 1;
5787 tdep->default_mask_address_p = 0;
5788 set_gdbarch_long_bit (gdbarch, 64);
5789 set_gdbarch_ptr_bit (gdbarch, 64);
5790 set_gdbarch_long_long_bit (gdbarch, 64);
5791 set_gdbarch_reg_struct_has_addr (gdbarch,
5792 mips_eabi_reg_struct_has_addr);
5793 set_gdbarch_use_struct_convention (gdbarch,
5794 mips_eabi_use_struct_convention);
5797 set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments);
5798 set_gdbarch_store_return_value (gdbarch, mips_n32n64_store_return_value);
5799 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5800 tdep->mips_default_saved_regsize = 8;
5801 tdep->mips_default_stack_argsize = 8;
5802 tdep->mips_fp_register_double = 1;
5803 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5804 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5805 tdep->gdb_target_is_mips64 = 1;
5806 tdep->default_mask_address_p = 0;
5807 set_gdbarch_long_bit (gdbarch, 32);
5808 set_gdbarch_ptr_bit (gdbarch, 32);
5809 set_gdbarch_long_long_bit (gdbarch, 64);
5811 /* Set up the disassembler info, so that we get the right
5812 register names from libopcodes. */
5813 tm_print_insn_info.flavour = bfd_target_elf_flavour;
5814 tm_print_insn_info.arch = bfd_arch_mips;
5815 if (info.bfd_arch_info != NULL
5816 && info.bfd_arch_info->arch == bfd_arch_mips
5817 && info.bfd_arch_info->mach)
5818 tm_print_insn_info.mach = info.bfd_arch_info->mach;
5820 tm_print_insn_info.mach = bfd_mach_mips8000;
5822 set_gdbarch_use_struct_convention (gdbarch,
5823 mips_n32n64_use_struct_convention);
5824 set_gdbarch_reg_struct_has_addr (gdbarch,
5825 mips_n32n64_reg_struct_has_addr);
5828 set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments);
5829 set_gdbarch_store_return_value (gdbarch, mips_n32n64_store_return_value);
5830 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5831 tdep->mips_default_saved_regsize = 8;
5832 tdep->mips_default_stack_argsize = 8;
5833 tdep->mips_fp_register_double = 1;
5834 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5835 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5836 tdep->gdb_target_is_mips64 = 1;
5837 tdep->default_mask_address_p = 0;
5838 set_gdbarch_long_bit (gdbarch, 64);
5839 set_gdbarch_ptr_bit (gdbarch, 64);
5840 set_gdbarch_long_long_bit (gdbarch, 64);
5842 /* Set up the disassembler info, so that we get the right
5843 register names from libopcodes. */
5844 tm_print_insn_info.flavour = bfd_target_elf_flavour;
5845 tm_print_insn_info.arch = bfd_arch_mips;
5846 if (info.bfd_arch_info != NULL
5847 && info.bfd_arch_info->arch == bfd_arch_mips
5848 && info.bfd_arch_info->mach)
5849 tm_print_insn_info.mach = info.bfd_arch_info->mach;
5851 tm_print_insn_info.mach = bfd_mach_mips8000;
5853 set_gdbarch_use_struct_convention (gdbarch,
5854 mips_n32n64_use_struct_convention);
5855 set_gdbarch_reg_struct_has_addr (gdbarch,
5856 mips_n32n64_reg_struct_has_addr);
5859 internal_error (__FILE__, __LINE__,
5860 "unknown ABI in switch");
5863 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5864 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5867 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5868 flag in object files because to do so would make it impossible to
5869 link with libraries compiled without "-gp32". This is
5870 unnecessarily restrictive.
5872 We could solve this problem by adding "-gp32" multilibs to gcc,
5873 but to set this flag before gcc is built with such multilibs will
5874 break too many systems.''
5876 But even more unhelpfully, the default linker output target for
5877 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5878 for 64-bit programs - you need to change the ABI to change this,
5879 and not all gcc targets support that currently. Therefore using
5880 this flag to detect 32-bit mode would do the wrong thing given
5881 the current gcc - it would make GDB treat these 64-bit programs
5882 as 32-bit programs by default. */
5884 /* enable/disable the MIPS FPU */
5885 if (!mips_fpu_type_auto)
5886 tdep->mips_fpu_type = mips_fpu_type;
5887 else if (info.bfd_arch_info != NULL
5888 && info.bfd_arch_info->arch == bfd_arch_mips)
5889 switch (info.bfd_arch_info->mach)
5891 case bfd_mach_mips3900:
5892 case bfd_mach_mips4100:
5893 case bfd_mach_mips4111:
5894 tdep->mips_fpu_type = MIPS_FPU_NONE;
5896 case bfd_mach_mips4650:
5897 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
5900 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5904 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5906 /* MIPS version of register names. NOTE: At present the MIPS
5907 register name management is part way between the old -
5908 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5909 Further work on it is required. */
5910 set_gdbarch_register_name (gdbarch, mips_register_name);
5911 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5912 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
5913 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
5914 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5915 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
5917 /* Add/remove bits from an address. The MIPS needs be careful to
5918 ensure that all 32 bit addresses are sign extended to 64 bits. */
5919 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5921 /* There's a mess in stack frame creation. See comments in
5922 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
5923 set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
5924 set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop);
5926 /* Map debug register numbers onto internal register numbers. */
5927 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5928 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum);
5930 /* Initialize a frame */
5931 set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
5932 set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs);
5934 /* MIPS version of CALL_DUMMY */
5936 set_gdbarch_call_dummy_p (gdbarch, 1);
5937 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
5938 set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
5939 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
5940 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
5941 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
5942 set_gdbarch_push_dummy_frame (gdbarch, mips_push_dummy_frame);
5943 set_gdbarch_pop_frame (gdbarch, mips_pop_frame);
5944 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
5945 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
5946 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
5947 set_gdbarch_call_dummy_length (gdbarch, 0);
5948 set_gdbarch_fix_call_dummy (gdbarch, mips_fix_call_dummy);
5949 set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
5950 set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
5951 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
5952 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
5953 set_gdbarch_register_convertible (gdbarch, mips_register_convertible);
5954 set_gdbarch_register_convert_to_virtual (gdbarch,
5955 mips_register_convert_to_virtual);
5956 set_gdbarch_register_convert_to_raw (gdbarch,
5957 mips_register_convert_to_raw);
5959 set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double);
5961 set_gdbarch_frame_chain (gdbarch, mips_frame_chain);
5962 set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
5963 set_gdbarch_frameless_function_invocation (gdbarch,
5964 generic_frameless_function_invocation_not);
5965 set_gdbarch_frame_saved_pc (gdbarch, mips_frame_saved_pc);
5966 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
5967 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
5968 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
5969 set_gdbarch_frame_args_skip (gdbarch, 0);
5971 set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
5973 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5974 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5975 set_gdbarch_decr_pc_after_break (gdbarch, 0);
5977 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5978 set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
5980 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5981 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5982 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5984 set_gdbarch_function_start_offset (gdbarch, 0);
5986 /* There are MIPS targets which do not yet use this since they still
5987 define REGISTER_VIRTUAL_TYPE. */
5988 set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type);
5989 set_gdbarch_register_virtual_size (gdbarch, generic_register_size);
5991 set_gdbarch_do_registers_info (gdbarch, mips_do_registers_info);
5992 set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp);
5994 /* Hook in OS ABI-specific overrides, if they have been registered. */
5995 gdbarch_init_osabi (info, gdbarch, osabi);
5997 set_gdbarch_store_struct_return (gdbarch, mips_store_struct_return);
5998 set_gdbarch_extract_struct_value_address (gdbarch,
5999 mips_extract_struct_value_address);
6001 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
6003 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
6004 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
6010 mips_abi_update (char *ignore_args, int from_tty,
6011 struct cmd_list_element *c)
6013 struct gdbarch_info info;
6015 /* Force the architecture to update, and (if it's a MIPS architecture)
6016 mips_gdbarch_init will take care of the rest. */
6017 gdbarch_info_init (&info);
6018 gdbarch_update_p (info);
6022 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
6024 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
6028 int ef_mips_32bitmode;
6029 /* determine the ISA */
6030 switch (tdep->elf_flags & EF_MIPS_ARCH)
6048 /* determine the size of a pointer */
6049 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6050 fprintf_unfiltered (file,
6051 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6053 fprintf_unfiltered (file,
6054 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6056 fprintf_unfiltered (file,
6057 "mips_dump_tdep: ef_mips_arch = %d\n",
6059 fprintf_unfiltered (file,
6060 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6062 mips_abi_strings[tdep->mips_abi]);
6063 fprintf_unfiltered (file,
6064 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6065 mips_mask_address_p (),
6066 tdep->default_mask_address_p);
6068 fprintf_unfiltered (file,
6069 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6070 FP_REGISTER_DOUBLE);
6071 fprintf_unfiltered (file,
6072 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6073 MIPS_DEFAULT_FPU_TYPE,
6074 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6075 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6076 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6078 fprintf_unfiltered (file,
6079 "mips_dump_tdep: MIPS_EABI = %d\n",
6081 fprintf_unfiltered (file,
6082 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6083 MIPS_LAST_FP_ARG_REGNUM,
6084 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
6085 fprintf_unfiltered (file,
6086 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6088 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
6089 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6090 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6092 fprintf_unfiltered (file,
6093 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6094 MIPS_DEFAULT_SAVED_REGSIZE);
6095 fprintf_unfiltered (file,
6096 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6097 FP_REGISTER_DOUBLE);
6098 fprintf_unfiltered (file,
6099 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6100 MIPS_DEFAULT_STACK_ARGSIZE);
6101 fprintf_unfiltered (file,
6102 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6103 MIPS_STACK_ARGSIZE);
6104 fprintf_unfiltered (file,
6105 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
6107 fprintf_unfiltered (file,
6108 "mips_dump_tdep: A0_REGNUM = %d\n",
6110 fprintf_unfiltered (file,
6111 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6112 XSTRING (ADDR_BITS_REMOVE(ADDR)));
6113 fprintf_unfiltered (file,
6114 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6115 XSTRING (ATTACH_DETACH));
6116 fprintf_unfiltered (file,
6117 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6119 fprintf_unfiltered (file,
6120 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
6121 fprintf_unfiltered (file,
6122 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6124 fprintf_unfiltered (file,
6125 "mips_dump_tdep: CPLUS_MARKER = %c\n",
6127 fprintf_unfiltered (file,
6128 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
6130 fprintf_unfiltered (file,
6131 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
6132 XSTRING (DO_REGISTERS_INFO));
6133 fprintf_unfiltered (file,
6134 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6135 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
6136 fprintf_unfiltered (file,
6137 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6138 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
6139 fprintf_unfiltered (file,
6140 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
6141 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM)));
6142 fprintf_unfiltered (file,
6143 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6145 fprintf_unfiltered (file,
6146 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6148 fprintf_unfiltered (file,
6149 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6150 FIRST_EMBED_REGNUM);
6151 fprintf_unfiltered (file,
6152 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6154 fprintf_unfiltered (file,
6155 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6156 GDB_TARGET_IS_MIPS64);
6157 fprintf_unfiltered (file,
6158 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
6159 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC)));
6160 fprintf_unfiltered (file,
6161 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
6162 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC)));
6163 fprintf_unfiltered (file,
6164 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
6166 fprintf_unfiltered (file,
6167 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
6168 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
6169 fprintf_unfiltered (file,
6170 "mips_dump_tdep: HI_REGNUM = %d\n",
6172 fprintf_unfiltered (file,
6173 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
6174 fprintf_unfiltered (file,
6175 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
6176 fprintf_unfiltered (file,
6177 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6178 XSTRING (IGNORE_HELPER_CALL (PC)));
6179 fprintf_unfiltered (file,
6180 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6181 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
6182 fprintf_unfiltered (file,
6183 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6184 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
6185 fprintf_unfiltered (file,
6186 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
6187 fprintf_unfiltered (file,
6188 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6190 fprintf_unfiltered (file,
6191 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
6192 fprintf_unfiltered (file,
6193 "mips_dump_tdep: LO_REGNUM = %d\n",
6195 #ifdef MACHINE_CPROC_FP_OFFSET
6196 fprintf_unfiltered (file,
6197 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6198 MACHINE_CPROC_FP_OFFSET);
6200 #ifdef MACHINE_CPROC_PC_OFFSET
6201 fprintf_unfiltered (file,
6202 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6203 MACHINE_CPROC_PC_OFFSET);
6205 #ifdef MACHINE_CPROC_SP_OFFSET
6206 fprintf_unfiltered (file,
6207 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6208 MACHINE_CPROC_SP_OFFSET);
6210 fprintf_unfiltered (file,
6211 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
6212 fprintf_unfiltered (file,
6213 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
6214 fprintf_unfiltered (file,
6215 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6217 fprintf_unfiltered (file,
6218 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
6219 fprintf_unfiltered (file,
6220 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6221 fprintf_unfiltered (file,
6222 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6223 fprintf_unfiltered (file,
6224 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6226 fprintf_unfiltered (file,
6227 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6228 MIPS_LAST_ARG_REGNUM,
6229 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
6230 fprintf_unfiltered (file,
6231 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6233 fprintf_unfiltered (file,
6234 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6235 fprintf_unfiltered (file,
6236 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6237 MIPS_SAVED_REGSIZE);
6238 fprintf_unfiltered (file,
6239 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
6240 fprintf_unfiltered (file,
6241 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
6242 XSTRING (MSYMBOL_SIZE (MSYM)));
6243 fprintf_unfiltered (file,
6244 "mips_dump_tdep: OP_LDFPR = used?\n");
6245 fprintf_unfiltered (file,
6246 "mips_dump_tdep: OP_LDGPR = used?\n");
6247 fprintf_unfiltered (file,
6248 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
6249 fprintf_unfiltered (file,
6250 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
6251 fprintf_unfiltered (file,
6252 "mips_dump_tdep: PRID_REGNUM = %d\n",
6254 fprintf_unfiltered (file,
6255 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
6256 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
6257 fprintf_unfiltered (file,
6258 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6259 fprintf_unfiltered (file,
6260 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6261 fprintf_unfiltered (file,
6262 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6263 fprintf_unfiltered (file,
6264 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6265 fprintf_unfiltered (file,
6266 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6267 fprintf_unfiltered (file,
6268 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6269 fprintf_unfiltered (file,
6270 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6271 fprintf_unfiltered (file,
6272 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6273 fprintf_unfiltered (file,
6274 "mips_dump_tdep: PROC_PC_REG = function?\n");
6275 fprintf_unfiltered (file,
6276 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6277 fprintf_unfiltered (file,
6278 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6279 fprintf_unfiltered (file,
6280 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6281 fprintf_unfiltered (file,
6282 "mips_dump_tdep: PS_REGNUM = %d\n",
6284 fprintf_unfiltered (file,
6285 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
6287 fprintf_unfiltered (file,
6288 "mips_dump_tdep: RA_REGNUM = %d\n",
6290 fprintf_unfiltered (file,
6291 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
6292 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
6293 fprintf_unfiltered (file,
6294 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
6295 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
6296 fprintf_unfiltered (file,
6297 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
6298 fprintf_unfiltered (file,
6299 "mips_dump_tdep: ROUND_DOWN = function?\n");
6300 fprintf_unfiltered (file,
6301 "mips_dump_tdep: ROUND_UP = function?\n");
6303 fprintf_unfiltered (file,
6304 "mips_dump_tdep: SAVED_BYTES = %d\n",
6308 fprintf_unfiltered (file,
6309 "mips_dump_tdep: SAVED_FP = %d\n",
6313 fprintf_unfiltered (file,
6314 "mips_dump_tdep: SAVED_PC = %d\n",
6317 fprintf_unfiltered (file,
6318 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6319 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
6320 fprintf_unfiltered (file,
6321 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6322 fprintf_unfiltered (file,
6323 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6325 fprintf_unfiltered (file,
6326 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6327 SIGFRAME_FPREGSAVE_OFF);
6328 fprintf_unfiltered (file,
6329 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6331 fprintf_unfiltered (file,
6332 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6333 SIGFRAME_REGSAVE_OFF);
6334 fprintf_unfiltered (file,
6335 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6337 fprintf_unfiltered (file,
6338 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6339 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
6340 fprintf_unfiltered (file,
6341 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6342 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
6343 fprintf_unfiltered (file,
6344 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6345 SOFTWARE_SINGLE_STEP_P ());
6346 fprintf_unfiltered (file,
6347 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6348 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6349 #ifdef STACK_END_ADDR
6350 fprintf_unfiltered (file,
6351 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6354 fprintf_unfiltered (file,
6355 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6356 XSTRING (STEP_SKIPS_DELAY (PC)));
6357 fprintf_unfiltered (file,
6358 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6359 STEP_SKIPS_DELAY_P);
6360 fprintf_unfiltered (file,
6361 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6362 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6363 fprintf_unfiltered (file,
6364 "mips_dump_tdep: T9_REGNUM = %d\n",
6366 fprintf_unfiltered (file,
6367 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6368 fprintf_unfiltered (file,
6369 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6370 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
6371 fprintf_unfiltered (file,
6372 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6373 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
6374 fprintf_unfiltered (file,
6375 "mips_dump_tdep: TARGET_MIPS = used?\n");
6376 fprintf_unfiltered (file,
6377 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
6378 XSTRING (TM_PRINT_INSN_MACH));
6380 fprintf_unfiltered (file,
6381 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6382 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6385 fprintf_unfiltered (file,
6386 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6389 #ifdef TRACE_FLAVOR_SIZE
6390 fprintf_unfiltered (file,
6391 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6395 fprintf_unfiltered (file,
6396 "mips_dump_tdep: TRACE_SET # %s\n",
6397 XSTRING (TRACE_SET (X,STATE)));
6399 fprintf_unfiltered (file,
6400 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
6401 #ifdef UNUSED_REGNUM
6402 fprintf_unfiltered (file,
6403 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6406 fprintf_unfiltered (file,
6407 "mips_dump_tdep: V0_REGNUM = %d\n",
6409 fprintf_unfiltered (file,
6410 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6411 (long) VM_MIN_ADDRESS);
6413 fprintf_unfiltered (file,
6414 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
6417 fprintf_unfiltered (file,
6418 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6420 fprintf_unfiltered (file,
6421 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6424 fprintf_unfiltered (file,
6425 "mips_dump_tdep: OS ABI = %s\n",
6426 gdbarch_osabi_name (tdep->osabi));
6430 _initialize_mips_tdep (void)
6432 static struct cmd_list_element *mipsfpulist = NULL;
6433 struct cmd_list_element *c;
6435 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
6436 if (MIPS_ABI_LAST + 1
6437 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6438 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6440 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6441 if (!tm_print_insn) /* Someone may have already set it */
6442 tm_print_insn = gdb_print_insn_mips;
6444 /* Add root prefix command for all "set mips"/"show mips" commands */
6445 add_prefix_cmd ("mips", no_class, set_mips_command,
6446 "Various MIPS specific commands.",
6447 &setmipscmdlist, "set mips ", 0, &setlist);
6449 add_prefix_cmd ("mips", no_class, show_mips_command,
6450 "Various MIPS specific commands.",
6451 &showmipscmdlist, "show mips ", 0, &showlist);
6453 /* Allow the user to override the saved register size. */
6454 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6457 &mips_saved_regsize_string, "\
6458 Set size of general purpose registers saved on the stack.\n\
6459 This option can be set to one of:\n\
6460 32 - Force GDB to treat saved GP registers as 32-bit\n\
6461 64 - Force GDB to treat saved GP registers as 64-bit\n\
6462 auto - Allow GDB to use the target's default setting or autodetect the\n\
6463 saved GP register size from information contained in the executable.\n\
6468 /* Allow the user to override the argument stack size. */
6469 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6472 &mips_stack_argsize_string, "\
6473 Set the amount of stack space reserved for each argument.\n\
6474 This option can be set to one of:\n\
6475 32 - Force GDB to allocate 32-bit chunks per argument\n\
6476 64 - Force GDB to allocate 64-bit chunks per argument\n\
6477 auto - Allow GDB to determine the correct setting from the current\n\
6478 target and executable (default)",
6482 /* Allow the user to override the ABI. */
6483 c = add_set_enum_cmd
6484 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6485 "Set the ABI used by this program.\n"
6486 "This option can be set to one of:\n"
6487 " auto - the default ABI associated with the current binary\n"
6495 add_show_from_set (c, &showmipscmdlist);
6496 set_cmd_sfunc (c, mips_abi_update);
6498 /* Let the user turn off floating point and set the fence post for
6499 heuristic_proc_start. */
6501 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6502 "Set use of MIPS floating-point coprocessor.",
6503 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6504 add_cmd ("single", class_support, set_mipsfpu_single_command,
6505 "Select single-precision MIPS floating-point coprocessor.",
6507 add_cmd ("double", class_support, set_mipsfpu_double_command,
6508 "Select double-precision MIPS floating-point coprocessor.",
6510 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6511 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6512 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6513 add_cmd ("none", class_support, set_mipsfpu_none_command,
6514 "Select no MIPS floating-point coprocessor.",
6516 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6517 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6518 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6519 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6520 "Select MIPS floating-point coprocessor automatically.",
6522 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6523 "Show current use of MIPS floating-point coprocessor target.",
6526 /* We really would like to have both "0" and "unlimited" work, but
6527 command.c doesn't deal with that. So make it a var_zinteger
6528 because the user can always use "999999" or some such for unlimited. */
6529 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6530 (char *) &heuristic_fence_post,
6532 Set the distance searched for the start of a function.\n\
6533 If you are debugging a stripped executable, GDB needs to search through the\n\
6534 program for the start of a function. This command sets the distance of the\n\
6535 search. The only need to set it is when debugging a stripped executable.",
6537 /* We need to throw away the frame cache when we set this, since it
6538 might change our ability to get backtraces. */
6539 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
6540 add_show_from_set (c, &showlist);
6542 /* Allow the user to control whether the upper bits of 64-bit
6543 addresses should be zeroed. */
6544 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6545 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6546 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6547 allow GDB to determine the correct value.\n", "\
6548 Show zeroing of upper 32 bits of 64-bit addresses.",
6549 NULL, show_mask_address,
6550 &setmipscmdlist, &showmipscmdlist);
6552 /* Allow the user to control the size of 32 bit registers within the
6553 raw remote packet. */
6554 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6557 (char *)&mips64_transfers_32bit_regs_p, "\
6558 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6559 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6560 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6561 64 bits for others. Use \"off\" to disable compatibility mode",
6565 /* Debug this files internals. */
6566 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6567 &mips_debug, "Set mips debugging.\n\
6568 When non-zero, mips specific debugging is enabled.", &setdebuglist),