1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
63 static const struct objfile_data *mips_pdr_data;
65 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
67 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
68 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
69 #define ST0_FR (1 << 26)
71 /* The sizes of floating point registers. */
75 MIPS_FPU_SINGLE_REGSIZE = 4,
76 MIPS_FPU_DOUBLE_REGSIZE = 8
85 static const char *mips_abi_string;
87 static const char *mips_abi_strings[] = {
98 /* The standard register names, and all the valid aliases for them. */
105 /* Aliases for o32 and most other ABIs. */
106 const struct register_alias mips_o32_aliases[] = {
113 /* Aliases for n32 and n64. */
114 const struct register_alias mips_n32_n64_aliases[] = {
121 /* Aliases for ABI-independent registers. */
122 const struct register_alias mips_register_aliases[] = {
123 /* The architecture manuals specify these ABI-independent names for
125 #define R(n) { "r" #n, n }
126 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
127 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
128 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
129 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
132 /* k0 and k1 are sometimes called these instead (for "kernel
137 /* This is the traditional GDB name for the CP0 status register. */
138 { "sr", MIPS_PS_REGNUM },
140 /* This is the traditional GDB name for the CP0 BadVAddr register. */
141 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
143 /* This is the traditional GDB name for the FCSR. */
144 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
147 const struct register_alias mips_numeric_register_aliases[] = {
148 #define R(n) { #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
156 #ifndef MIPS_DEFAULT_FPU_TYPE
157 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
159 static int mips_fpu_type_auto = 1;
160 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
162 static int mips_debug = 0;
164 /* Properties (for struct target_desc) describing the g/G packet
166 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
167 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
169 struct target_desc *mips_tdesc_gp32;
170 struct target_desc *mips_tdesc_gp64;
172 const struct mips_regnum *
173 mips_regnum (struct gdbarch *gdbarch)
175 return gdbarch_tdep (gdbarch)->regnum;
179 mips_fpa0_regnum (struct gdbarch *gdbarch)
181 return mips_regnum (gdbarch)->fp0 + 12;
184 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
186 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
188 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
189 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
191 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
192 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
194 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
196 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
197 functions to test, set, or clear bit 0 of addresses. */
200 is_mips16_addr (CORE_ADDR addr)
206 unmake_mips16_addr (CORE_ADDR addr)
208 return ((addr) & ~(CORE_ADDR) 1);
212 make_mips16_addr (CORE_ADDR addr)
214 return ((addr) | (CORE_ADDR) 1);
217 /* Return the MIPS ABI associated with GDBARCH. */
219 mips_abi (struct gdbarch *gdbarch)
221 return gdbarch_tdep (gdbarch)->mips_abi;
225 mips_isa_regsize (struct gdbarch *gdbarch)
227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 /* If we know how big the registers are, use that size. */
230 if (tdep->register_size_valid_p)
231 return tdep->register_size;
233 /* Fall back to the previous behavior. */
234 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
235 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
238 /* Return the currently configured (or set) saved register size. */
241 mips_abi_regsize (struct gdbarch *gdbarch)
243 switch (mips_abi (gdbarch))
245 case MIPS_ABI_EABI32:
251 case MIPS_ABI_EABI64:
253 case MIPS_ABI_UNKNOWN:
256 internal_error (__FILE__, __LINE__, _("bad switch"));
260 /* Functions for setting and testing a bit in a minimal symbol that
261 marks it as 16-bit function. The MSB of the minimal symbol's
262 "info" field is used for this purpose.
264 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
265 i.e. refers to a 16-bit function, and sets a "special" bit in a
266 minimal symbol to mark it as a 16-bit function
268 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
271 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
273 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
275 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
280 msymbol_is_special (struct minimal_symbol *msym)
282 return MSYMBOL_TARGET_FLAG_1 (msym);
285 /* XFER a value from the big/little/left end of the register.
286 Depending on the size of the value it might occupy the entire
287 register or just part of it. Make an allowance for this, aligning
288 things accordingly. */
291 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
292 int reg_num, int length,
293 enum bfd_endian endian, gdb_byte *in,
294 const gdb_byte *out, int buf_offset)
298 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
299 /* Need to transfer the left or right part of the register, based on
300 the targets byte order. */
304 reg_offset = register_size (gdbarch, reg_num) - length;
306 case BFD_ENDIAN_LITTLE:
309 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
313 internal_error (__FILE__, __LINE__, _("bad switch"));
316 fprintf_unfiltered (gdb_stderr,
317 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
318 reg_num, reg_offset, buf_offset, length);
319 if (mips_debug && out != NULL)
322 fprintf_unfiltered (gdb_stdlog, "out ");
323 for (i = 0; i < length; i++)
324 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
327 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
330 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
332 if (mips_debug && in != NULL)
335 fprintf_unfiltered (gdb_stdlog, "in ");
336 for (i = 0; i < length; i++)
337 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
340 fprintf_unfiltered (gdb_stdlog, "\n");
343 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
344 compatiblity mode. A return value of 1 means that we have
345 physical 64-bit registers, but should treat them as 32-bit registers. */
348 mips2_fp_compat (struct frame_info *frame)
350 struct gdbarch *gdbarch = get_frame_arch (frame);
351 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
353 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
357 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
358 in all the places we deal with FP registers. PR gdb/413. */
359 /* Otherwise check the FR bit in the status register - it controls
360 the FP compatiblity mode. If it is clear we are in compatibility
362 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
369 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
371 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
373 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
375 /* The list of available "set mips " and "show mips " commands. */
377 static struct cmd_list_element *setmipscmdlist = NULL;
378 static struct cmd_list_element *showmipscmdlist = NULL;
380 /* Integer registers 0 thru 31 are handled explicitly by
381 mips_register_name(). Processor specific registers 32 and above
382 are listed in the following tables. */
385 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
389 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
390 "sr", "lo", "hi", "bad", "cause", "pc",
391 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
392 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
393 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
394 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
395 "fsr", "fir", "" /*"fp" */ , "",
396 "", "", "", "", "", "", "", "",
397 "", "", "", "", "", "", "", "",
400 /* Names of IDT R3041 registers. */
402 static const char *mips_r3041_reg_names[] = {
403 "sr", "lo", "hi", "bad", "cause", "pc",
404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
408 "fsr", "fir", "", /*"fp" */ "",
409 "", "", "bus", "ccfg", "", "", "", "",
410 "", "", "port", "cmp", "", "", "epc", "prid",
413 /* Names of tx39 registers. */
415 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
420 "", "", "", "", "", "", "", "",
422 "", "", "", "", "", "", "", "",
423 "", "", "config", "cache", "debug", "depc", "epc", ""
426 /* Names of IRIX registers. */
427 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
432 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
436 /* Return the name of the register corresponding to REGNO. */
438 mips_register_name (struct gdbarch *gdbarch, int regno)
440 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
441 /* GPR names for all ABIs other than n32/n64. */
442 static char *mips_gpr_names[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
449 /* GPR names for n32 and n64 ABIs. */
450 static char *mips_n32_n64_gpr_names[] = {
451 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
452 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
453 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
454 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
457 enum mips_abi abi = mips_abi (gdbarch);
459 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
460 but then don't make the raw register names visible. This (upper)
461 range of user visible register numbers are the pseudo-registers.
463 This approach was adopted accommodate the following scenario:
464 It is possible to debug a 64-bit device using a 32-bit
465 programming model. In such instances, the raw registers are
466 configured to be 64-bits wide, while the pseudo registers are
467 configured to be 32-bits wide. The registers that the user
468 sees - the pseudo registers - match the users expectations
469 given the programming model being used. */
470 int rawnum = regno % gdbarch_num_regs (gdbarch);
471 if (regno < gdbarch_num_regs (gdbarch))
474 /* The MIPS integer registers are always mapped from 0 to 31. The
475 names of the registers (which reflects the conventions regarding
476 register use) vary depending on the ABI. */
477 if (0 <= rawnum && rawnum < 32)
479 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
480 return mips_n32_n64_gpr_names[rawnum];
482 return mips_gpr_names[rawnum];
484 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
485 return tdesc_register_name (gdbarch, rawnum);
486 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
488 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
489 return tdep->mips_processor_reg_names[rawnum - 32];
492 internal_error (__FILE__, __LINE__,
493 _("mips_register_name: bad register number %d"), rawnum);
496 /* Return the groups that a MIPS register can be categorised into. */
499 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
500 struct reggroup *reggroup)
505 int rawnum = regnum % gdbarch_num_regs (gdbarch);
506 int pseudo = regnum / gdbarch_num_regs (gdbarch);
507 if (reggroup == all_reggroup)
509 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
510 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
511 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
512 (gdbarch), as not all architectures are multi-arch. */
513 raw_p = rawnum < gdbarch_num_regs (gdbarch);
514 if (gdbarch_register_name (gdbarch, regnum) == NULL
515 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
517 if (reggroup == float_reggroup)
518 return float_p && pseudo;
519 if (reggroup == vector_reggroup)
520 return vector_p && pseudo;
521 if (reggroup == general_reggroup)
522 return (!vector_p && !float_p) && pseudo;
523 /* Save the pseudo registers. Need to make certain that any code
524 extracting register values from a saved register cache also uses
526 if (reggroup == save_reggroup)
527 return raw_p && pseudo;
528 /* Restore the same pseudo register. */
529 if (reggroup == restore_reggroup)
530 return raw_p && pseudo;
534 /* Return the groups that a MIPS register can be categorised into.
535 This version is only used if we have a target description which
536 describes real registers (and their groups). */
539 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
540 struct reggroup *reggroup)
542 int rawnum = regnum % gdbarch_num_regs (gdbarch);
543 int pseudo = regnum / gdbarch_num_regs (gdbarch);
546 /* Only save, restore, and display the pseudo registers. Need to
547 make certain that any code extracting register values from a
548 saved register cache also uses pseudo registers.
550 Note: saving and restoring the pseudo registers is slightly
551 strange; if we have 64 bits, we should save and restore all
552 64 bits. But this is hard and has little benefit. */
556 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
560 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
563 /* Map the symbol table registers which live in the range [1 *
564 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
565 registers. Take care of alignment and size problems. */
567 static enum register_status
568 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
569 int cookednum, gdb_byte *buf)
571 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
572 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
573 && cookednum < 2 * gdbarch_num_regs (gdbarch));
574 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
575 return regcache_raw_read (regcache, rawnum, buf);
576 else if (register_size (gdbarch, rawnum) >
577 register_size (gdbarch, cookednum))
579 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
580 return regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
583 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
585 enum register_status status;
587 status = regcache_raw_read_signed (regcache, rawnum, ®val);
588 if (status == REG_VALID)
589 store_signed_integer (buf, 4, byte_order, regval);
594 internal_error (__FILE__, __LINE__, _("bad register size"));
598 mips_pseudo_register_write (struct gdbarch *gdbarch,
599 struct regcache *regcache, int cookednum,
602 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
603 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
604 && cookednum < 2 * gdbarch_num_regs (gdbarch));
605 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
606 regcache_raw_write (regcache, rawnum, buf);
607 else if (register_size (gdbarch, rawnum) >
608 register_size (gdbarch, cookednum))
610 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
611 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
614 /* Sign extend the shortened version of the register prior
615 to placing it in the raw register. This is required for
616 some mips64 parts in order to avoid unpredictable behavior. */
617 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
618 LONGEST regval = extract_signed_integer (buf, 4, byte_order);
619 regcache_raw_write_signed (regcache, rawnum, regval);
623 internal_error (__FILE__, __LINE__, _("bad register size"));
627 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch,
628 struct agent_expr *ax, int reg)
630 int rawnum = reg % gdbarch_num_regs (gdbarch);
631 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
632 && reg < 2 * gdbarch_num_regs (gdbarch));
634 ax_reg_mask (ax, rawnum);
640 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
641 struct agent_expr *ax, int reg)
643 int rawnum = reg % gdbarch_num_regs (gdbarch);
644 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
645 && reg < 2 * gdbarch_num_regs (gdbarch));
646 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg))
650 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg))
652 if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
653 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG)
656 ax_simple (ax, aop_lsh);
659 ax_simple (ax, aop_rsh_signed);
663 internal_error (__FILE__, __LINE__, _("bad register size"));
668 /* Table to translate MIPS16 register field to actual register number. */
669 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
671 /* Heuristic_proc_start may hunt through the text section for a long
672 time across a 2400 baud serial line. Allows the user to limit this
675 static unsigned int heuristic_fence_post = 0;
677 /* Number of bytes of storage in the actual machine representation for
678 register N. NOTE: This defines the pseudo register type so need to
679 rebuild the architecture vector. */
681 static int mips64_transfers_32bit_regs_p = 0;
684 set_mips64_transfers_32bit_regs (char *args, int from_tty,
685 struct cmd_list_element *c)
687 struct gdbarch_info info;
688 gdbarch_info_init (&info);
689 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
690 instead of relying on globals. Doing that would let generic code
691 handle the search for this specific architecture. */
692 if (!gdbarch_update_p (info))
694 mips64_transfers_32bit_regs_p = 0;
695 error (_("32-bit compatibility mode not supported"));
699 /* Convert to/from a register and the corresponding memory value. */
701 /* This predicate tests for the case of an 8 byte floating point
702 value that is being transferred to or from a pair of floating point
703 registers each of which are (or are considered to be) only 4 bytes
706 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum,
709 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
710 && register_size (gdbarch, regnum) == 4
711 && (regnum % gdbarch_num_regs (gdbarch))
712 >= mips_regnum (gdbarch)->fp0
713 && (regnum % gdbarch_num_regs (gdbarch))
714 < mips_regnum (gdbarch)->fp0 + 32
715 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
718 /* This predicate tests for the case of a value of less than 8
719 bytes in width that is being transfered to or from an 8 byte
720 general purpose register. */
722 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum,
725 int num_regs = gdbarch_num_regs (gdbarch);
727 return (register_size (gdbarch, regnum) == 8
728 && regnum % num_regs > 0 && regnum % num_regs < 32
729 && TYPE_LENGTH (type) < 8);
733 mips_convert_register_p (struct gdbarch *gdbarch,
734 int regnum, struct type *type)
736 return mips_convert_register_float_case_p (gdbarch, regnum, type)
737 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type);
741 mips_register_to_value (struct frame_info *frame, int regnum,
742 struct type *type, gdb_byte *to,
743 int *optimizedp, int *unavailablep)
745 struct gdbarch *gdbarch = get_frame_arch (frame);
747 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
749 get_frame_register (frame, regnum + 0, to + 4);
750 get_frame_register (frame, regnum + 1, to + 0);
752 if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4,
753 optimizedp, unavailablep))
756 if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0,
757 optimizedp, unavailablep))
759 *optimizedp = *unavailablep = 0;
762 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
764 int len = TYPE_LENGTH (type);
767 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0;
768 if (!get_frame_register_bytes (frame, regnum, offset, len, to,
769 optimizedp, unavailablep))
772 *optimizedp = *unavailablep = 0;
777 internal_error (__FILE__, __LINE__,
778 _("mips_register_to_value: unrecognized case"));
783 mips_value_to_register (struct frame_info *frame, int regnum,
784 struct type *type, const gdb_byte *from)
786 struct gdbarch *gdbarch = get_frame_arch (frame);
788 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
790 put_frame_register (frame, regnum + 0, from + 4);
791 put_frame_register (frame, regnum + 1, from + 0);
793 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
796 int len = TYPE_LENGTH (type);
798 /* Sign extend values, irrespective of type, that are stored to
799 a 64-bit general purpose register. (32-bit unsigned values
800 are stored as signed quantities within a 64-bit register.
801 When performing an operation, in compiled code, that combines
802 a 32-bit unsigned value with a signed 64-bit value, a type
803 conversion is first performed that zeroes out the high 32 bits.) */
804 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
807 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1);
809 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0);
810 put_frame_register_bytes (frame, regnum, 0, 8 - len, fill);
811 put_frame_register_bytes (frame, regnum, 8 - len, len, from);
815 if (from[len-1] & 0x80)
816 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1);
818 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0);
819 put_frame_register_bytes (frame, regnum, 0, len, from);
820 put_frame_register_bytes (frame, regnum, len, 8 - len, fill);
825 internal_error (__FILE__, __LINE__,
826 _("mips_value_to_register: unrecognized case"));
830 /* Return the GDB type object for the "standard" data type of data in
834 mips_register_type (struct gdbarch *gdbarch, int regnum)
836 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
837 if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0
838 && (regnum % gdbarch_num_regs (gdbarch))
839 < mips_regnum (gdbarch)->fp0 + 32)
841 /* The floating-point registers raw, or cooked, always match
842 mips_isa_regsize(), and also map 1:1, byte for byte. */
843 if (mips_isa_regsize (gdbarch) == 4)
844 return builtin_type (gdbarch)->builtin_float;
846 return builtin_type (gdbarch)->builtin_double;
848 else if (regnum < gdbarch_num_regs (gdbarch))
850 /* The raw or ISA registers. These are all sized according to
852 if (mips_isa_regsize (gdbarch) == 4)
853 return builtin_type (gdbarch)->builtin_int32;
855 return builtin_type (gdbarch)->builtin_int64;
859 /* The cooked or ABI registers. These are sized according to
860 the ABI (with a few complications). */
861 if (regnum >= (gdbarch_num_regs (gdbarch)
862 + mips_regnum (gdbarch)->fp_control_status)
863 && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM)
864 /* The pseudo/cooked view of the embedded registers is always
865 32-bit. The raw view is handled below. */
866 return builtin_type (gdbarch)->builtin_int32;
867 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
868 /* The target, while possibly using a 64-bit register buffer,
869 is only transfering 32-bits of each integer register.
870 Reflect this in the cooked/pseudo (ABI) register value. */
871 return builtin_type (gdbarch)->builtin_int32;
872 else if (mips_abi_regsize (gdbarch) == 4)
873 /* The ABI is restricted to 32-bit registers (the ISA could be
875 return builtin_type (gdbarch)->builtin_int32;
878 return builtin_type (gdbarch)->builtin_int64;
882 /* Return the GDB type for the pseudo register REGNUM, which is the
883 ABI-level view. This function is only called if there is a target
884 description which includes registers, so we know precisely the
885 types of hardware registers. */
888 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
890 const int num_regs = gdbarch_num_regs (gdbarch);
891 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
892 int rawnum = regnum % num_regs;
893 struct type *rawtype;
895 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
897 /* Absent registers are still absent. */
898 rawtype = gdbarch_register_type (gdbarch, rawnum);
899 if (TYPE_LENGTH (rawtype) == 0)
902 if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32)
903 /* Present the floating point registers however the hardware did;
904 do not try to convert between FPU layouts. */
907 if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM)
909 /* The pseudo/cooked view of embedded registers is always
910 32-bit, even if the target transfers 64-bit values for them.
911 New targets relying on XML descriptions should only transfer
912 the necessary 32 bits, but older versions of GDB expected 64,
913 so allow the target to provide 64 bits without interfering
914 with the displayed type. */
915 return builtin_type (gdbarch)->builtin_int32;
918 /* Use pointer types for registers if we can. For n32 we can not,
919 since we do not have a 64-bit pointer type. */
920 if (mips_abi_regsize (gdbarch)
921 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
923 if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM)
924 return builtin_type (gdbarch)->builtin_data_ptr;
925 else if (rawnum == MIPS_EMBED_PC_REGNUM)
926 return builtin_type (gdbarch)->builtin_func_ptr;
929 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
930 && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM)
931 return builtin_type (gdbarch)->builtin_int32;
933 /* For all other registers, pass through the hardware type. */
937 /* Should the upper word of 64-bit addresses be zeroed? */
938 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
941 mips_mask_address_p (struct gdbarch_tdep *tdep)
943 switch (mask_address_var)
945 case AUTO_BOOLEAN_TRUE:
947 case AUTO_BOOLEAN_FALSE:
950 case AUTO_BOOLEAN_AUTO:
951 return tdep->default_mask_address_p;
953 internal_error (__FILE__, __LINE__,
954 _("mips_mask_address_p: bad switch"));
960 show_mask_address (struct ui_file *file, int from_tty,
961 struct cmd_list_element *c, const char *value)
963 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
965 deprecated_show_value_hack (file, from_tty, c, value);
966 switch (mask_address_var)
968 case AUTO_BOOLEAN_TRUE:
969 printf_filtered ("The 32 bit mips address mask is enabled\n");
971 case AUTO_BOOLEAN_FALSE:
972 printf_filtered ("The 32 bit mips address mask is disabled\n");
974 case AUTO_BOOLEAN_AUTO:
976 ("The 32 bit address mask is set automatically. Currently %s\n",
977 mips_mask_address_p (tdep) ? "enabled" : "disabled");
980 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
985 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
988 mips_pc_is_mips16 (CORE_ADDR memaddr)
990 struct minimal_symbol *sym;
992 /* A flag indicating that this is a MIPS16 function is stored by
993 elfread.c in the high bit of the info field. Use this to decide
994 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
995 the address is set, assume this is a MIPS16 address. */
996 sym = lookup_minimal_symbol_by_pc (memaddr);
998 return msymbol_is_special (sym);
1000 return is_mips16_addr (memaddr);
1003 /* MIPS believes that the PC has a sign extended value. Perhaps the
1004 all registers should be sign extended for simplicity? */
1007 mips_read_pc (struct regcache *regcache)
1010 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
1011 regcache_cooked_read_signed (regcache, regnum, &pc);
1012 if (is_mips16_addr (pc))
1013 pc = unmake_mips16_addr (pc);
1018 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1022 pc = frame_unwind_register_signed
1023 (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc);
1024 if (is_mips16_addr (pc))
1025 pc = unmake_mips16_addr (pc);
1030 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1032 return frame_unwind_register_signed
1033 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
1036 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1037 dummy frame. The frame ID's base needs to match the TOS value
1038 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1041 static struct frame_id
1042 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1044 return frame_id_build
1045 (get_frame_register_signed (this_frame,
1046 gdbarch_num_regs (gdbarch)
1048 get_frame_pc (this_frame));
1052 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
1054 int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
1055 if (mips_pc_is_mips16 (pc))
1056 regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc));
1058 regcache_cooked_write_unsigned (regcache, regnum, pc);
1061 /* Fetch and return instruction from the specified location. If the PC
1062 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1065 mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr)
1067 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1068 gdb_byte buf[MIPS_INSN32_SIZE];
1072 if (mips_pc_is_mips16 (addr))
1074 instlen = MIPS_INSN16_SIZE;
1075 addr = unmake_mips16_addr (addr);
1078 instlen = MIPS_INSN32_SIZE;
1079 status = target_read_memory (addr, buf, instlen);
1081 memory_error (status, addr);
1082 return extract_unsigned_integer (buf, instlen, byte_order);
1085 /* These are the fields of 32 bit mips instructions. */
1086 #define mips32_op(x) (x >> 26)
1087 #define itype_op(x) (x >> 26)
1088 #define itype_rs(x) ((x >> 21) & 0x1f)
1089 #define itype_rt(x) ((x >> 16) & 0x1f)
1090 #define itype_immediate(x) (x & 0xffff)
1092 #define jtype_op(x) (x >> 26)
1093 #define jtype_target(x) (x & 0x03ffffff)
1095 #define rtype_op(x) (x >> 26)
1096 #define rtype_rs(x) ((x >> 21) & 0x1f)
1097 #define rtype_rt(x) ((x >> 16) & 0x1f)
1098 #define rtype_rd(x) ((x >> 11) & 0x1f)
1099 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1100 #define rtype_funct(x) (x & 0x3f)
1103 mips32_relative_offset (ULONGEST inst)
1105 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
1108 /* Determine where to set a single step breakpoint while considering
1109 branch prediction. */
1111 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
1113 struct gdbarch *gdbarch = get_frame_arch (frame);
1116 inst = mips_fetch_instruction (gdbarch, pc);
1117 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch
1120 if (itype_op (inst) >> 2 == 5)
1121 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1123 op = (itype_op (inst) & 0x03);
1133 goto greater_branch;
1138 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
1139 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1141 int tf = itype_rt (inst) & 0x01;
1142 int cnum = itype_rt (inst) >> 2;
1144 get_frame_register_signed (frame,
1145 mips_regnum (get_frame_arch (frame))->
1147 int cond = ((fcrcs >> 24) & 0xfe) | ((fcrcs >> 23) & 0x01);
1149 if (((cond >> cnum) & 0x01) == tf)
1150 pc += mips32_relative_offset (inst) + 4;
1155 pc += 4; /* Not a branch, next instruction is easy. */
1158 { /* This gets way messy. */
1160 /* Further subdivide into SPECIAL, REGIMM and other. */
1161 switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */
1163 case 0: /* SPECIAL */
1164 op = rtype_funct (inst);
1169 /* Set PC to that address. */
1170 pc = get_frame_register_signed (frame, rtype_rs (inst));
1172 case 12: /* SYSCALL */
1174 struct gdbarch_tdep *tdep;
1176 tdep = gdbarch_tdep (get_frame_arch (frame));
1177 if (tdep->syscall_next_pc != NULL)
1178 pc = tdep->syscall_next_pc (frame);
1187 break; /* end SPECIAL */
1188 case 1: /* REGIMM */
1190 op = itype_rt (inst); /* branch condition */
1195 case 16: /* BLTZAL */
1196 case 18: /* BLTZALL */
1198 if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1199 pc += mips32_relative_offset (inst) + 4;
1201 pc += 8; /* after the delay slot */
1205 case 17: /* BGEZAL */
1206 case 19: /* BGEZALL */
1207 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1208 pc += mips32_relative_offset (inst) + 4;
1210 pc += 8; /* after the delay slot */
1212 /* All of the other instructions in the REGIMM category */
1217 break; /* end REGIMM */
1222 reg = jtype_target (inst) << 2;
1223 /* Upper four bits get never changed... */
1224 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1227 /* FIXME case JALX : */
1230 reg = jtype_target (inst) << 2;
1231 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */
1232 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1234 break; /* The new PC will be alternate mode */
1235 case 4: /* BEQ, BEQL */
1237 if (get_frame_register_signed (frame, itype_rs (inst)) ==
1238 get_frame_register_signed (frame, itype_rt (inst)))
1239 pc += mips32_relative_offset (inst) + 4;
1243 case 5: /* BNE, BNEL */
1245 if (get_frame_register_signed (frame, itype_rs (inst)) !=
1246 get_frame_register_signed (frame, itype_rt (inst)))
1247 pc += mips32_relative_offset (inst) + 4;
1251 case 6: /* BLEZ, BLEZL */
1252 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1253 pc += mips32_relative_offset (inst) + 4;
1259 greater_branch: /* BGTZ, BGTZL */
1260 if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1261 pc += mips32_relative_offset (inst) + 4;
1268 } /* mips32_next_pc */
1270 /* Decoding the next place to set a breakpoint is irregular for the
1271 mips 16 variant, but fortunately, there fewer instructions. We have
1272 to cope ith extensions for 16 bit instructions and a pair of actual
1273 32 bit instructions. We dont want to set a single step instruction
1274 on the extend instruction either. */
1276 /* Lots of mips16 instruction formats */
1277 /* Predicting jumps requires itype,ritype,i8type
1278 and their extensions extItype,extritype,extI8type. */
1279 enum mips16_inst_fmts
1281 itype, /* 0 immediate 5,10 */
1282 ritype, /* 1 5,3,8 */
1283 rrtype, /* 2 5,3,3,5 */
1284 rritype, /* 3 5,3,3,5 */
1285 rrrtype, /* 4 5,3,3,3,2 */
1286 rriatype, /* 5 5,3,3,1,4 */
1287 shifttype, /* 6 5,3,3,3,2 */
1288 i8type, /* 7 5,3,8 */
1289 i8movtype, /* 8 5,3,3,5 */
1290 i8mov32rtype, /* 9 5,3,5,3 */
1291 i64type, /* 10 5,3,8 */
1292 ri64type, /* 11 5,3,3,5 */
1293 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1294 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1295 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1296 extRRItype, /* 15 5,5,5,5,3,3,5 */
1297 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1298 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1299 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1300 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1301 extRi64type, /* 20 5,6,5,5,3,3,5 */
1302 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1304 /* I am heaping all the fields of the formats into one structure and
1305 then, only the fields which are involved in instruction extension. */
1309 unsigned int regx; /* Function in i8 type. */
1314 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1315 for the bits which make up the immediate extension. */
1318 extended_offset (unsigned int extension)
1322 value = (extension >> 16) & 0x1f; /* Extract 15:11. */
1324 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */
1326 value |= extension & 0x1f; /* Extract 4:0. */
1331 /* Only call this function if you know that this is an extendable
1332 instruction. It won't malfunction, but why make excess remote memory
1333 references? If the immediate operands get sign extended or something,
1334 do it after the extension is performed. */
1335 /* FIXME: Every one of these cases needs to worry about sign extension
1336 when the offset is to be used in relative addressing. */
1339 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc)
1341 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1343 pc &= 0xfffffffe; /* Clear the low order bit. */
1344 target_read_memory (pc, buf, 2);
1345 return extract_unsigned_integer (buf, 2, byte_order);
1349 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc,
1350 unsigned int extension,
1352 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1357 switch (insn_format)
1364 value = extended_offset ((extension << 16) | inst);
1365 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
1369 value = inst & 0x7ff;
1370 value = (value ^ 0x400) - 0x400; /* Sign-extend. */
1379 { /* A register identifier and an offset. */
1380 /* Most of the fields are the same as I type but the
1381 immediate value is of a different length. */
1385 value = extended_offset ((extension << 16) | inst);
1386 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
1390 value = inst & 0xff; /* 8 bits */
1391 value = (value ^ 0x80) - 0x80; /* Sign-extend. */
1394 regx = (inst >> 8) & 0x07; /* i8 funct */
1400 unsigned long value;
1401 unsigned int nexthalf;
1402 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1403 value = value << 16;
1404 nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit
1413 internal_error (__FILE__, __LINE__, _("bad switch"));
1415 upk->offset = offset;
1422 add_offset_16 (CORE_ADDR pc, int offset)
1424 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
1428 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
1429 unsigned int extension, unsigned int insn)
1431 struct gdbarch *gdbarch = get_frame_arch (frame);
1432 int op = (insn >> 11);
1435 case 2: /* Branch */
1438 struct upk_mips16 upk;
1439 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk);
1440 pc += (upk.offset << 1) + 2;
1443 case 3: /* JAL , JALX - Watch out, these are 32 bit
1446 struct upk_mips16 upk;
1447 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk);
1448 pc = add_offset_16 (pc, upk.offset);
1449 if ((insn >> 10) & 0x01) /* Exchange mode */
1450 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */
1457 struct upk_mips16 upk;
1459 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
1460 reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]);
1462 pc += (upk.offset << 1) + 2;
1469 struct upk_mips16 upk;
1471 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
1472 reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]);
1474 pc += (upk.offset << 1) + 2;
1479 case 12: /* I8 Formats btez btnez */
1481 struct upk_mips16 upk;
1483 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
1484 /* upk.regx contains the opcode */
1485 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
1486 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1487 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1488 /* pc = add_offset_16(pc,upk.offset) ; */
1489 pc += (upk.offset << 1) + 2;
1494 case 29: /* RR Formats JR, JALR, JALR-RA */
1496 struct upk_mips16 upk;
1497 /* upk.fmt = rrtype; */
1502 upk.regx = (insn >> 8) & 0x07;
1503 upk.regy = (insn >> 5) & 0x07;
1504 if ((upk.regy & 1) == 0)
1505 reg = mips16_to_32_reg[upk.regx];
1507 reg = 31; /* Function return instruction. */
1508 pc = get_frame_register_signed (frame, reg);
1515 /* This is an instruction extension. Fetch the real instruction
1516 (which follows the extension) and decode things based on
1520 pc = extended_mips16_next_pc (frame, pc, insn,
1521 fetch_mips_16 (gdbarch, pc));
1534 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
1536 struct gdbarch *gdbarch = get_frame_arch (frame);
1537 unsigned int insn = fetch_mips_16 (gdbarch, pc);
1538 return extended_mips16_next_pc (frame, pc, 0, insn);
1541 /* The mips_next_pc function supports single_step when the remote
1542 target monitor or stub is not developed enough to do a single_step.
1543 It works by decoding the current instruction and predicting where a
1544 branch will go. This isnt hard because all the data is available.
1545 The MIPS32 and MIPS16 variants are quite different. */
1547 mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1549 if (mips_pc_is_mips16 (pc))
1550 return mips16_next_pc (frame, pc);
1552 return mips32_next_pc (frame, pc);
1555 struct mips_frame_cache
1558 struct trad_frame_saved_reg *saved_regs;
1561 /* Set a register's saved stack address in temp_saved_regs. If an
1562 address has already been set for this register, do nothing; this
1563 way we will only recognize the first save of a given register in a
1566 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1567 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1568 Strictly speaking, only the second range is used as it is only second
1569 range (the ABI instead of ISA registers) that comes into play when finding
1570 saved registers in a frame. */
1573 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
1574 int regnum, CORE_ADDR offset)
1576 if (this_cache != NULL
1577 && this_cache->saved_regs[regnum].addr == -1)
1579 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
1581 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
1587 /* Fetch the immediate value from a MIPS16 instruction.
1588 If the previous instruction was an EXTEND, use it to extend
1589 the upper bits of the immediate value. This is a helper function
1590 for mips16_scan_prologue. */
1593 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1594 unsigned short inst, /* current instruction */
1595 int nbits, /* number of bits in imm field */
1596 int scale, /* scale factor to be applied to imm */
1597 int is_signed) /* is the imm field signed? */
1601 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1603 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1604 if (offset & 0x8000) /* check for negative extend */
1605 offset = 0 - (0x10000 - (offset & 0xffff));
1606 return offset | (inst & 0x1f);
1610 int max_imm = 1 << nbits;
1611 int mask = max_imm - 1;
1612 int sign_bit = max_imm >> 1;
1614 offset = inst & mask;
1615 if (is_signed && (offset & sign_bit))
1616 offset = 0 - (max_imm - offset);
1617 return offset * scale;
1622 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1623 the associated FRAME_CACHE if not null.
1624 Return the address of the first instruction past the prologue. */
1627 mips16_scan_prologue (struct gdbarch *gdbarch,
1628 CORE_ADDR start_pc, CORE_ADDR limit_pc,
1629 struct frame_info *this_frame,
1630 struct mips_frame_cache *this_cache)
1633 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */
1635 long frame_offset = 0; /* Size of stack frame. */
1636 long frame_adjust = 0; /* Offset of FP from SP. */
1637 int frame_reg = MIPS_SP_REGNUM;
1638 unsigned short prev_inst = 0; /* saved copy of previous instruction. */
1639 unsigned inst = 0; /* current instruction */
1640 unsigned entry_inst = 0; /* the entry instruction */
1641 unsigned save_inst = 0; /* the save instruction */
1644 int extend_bytes = 0;
1645 int prev_extend_bytes;
1646 CORE_ADDR end_prologue_addr = 0;
1648 /* Can be called when there's no process, and hence when there's no
1650 if (this_frame != NULL)
1651 sp = get_frame_register_signed (this_frame,
1652 gdbarch_num_regs (gdbarch)
1657 if (limit_pc > start_pc + 200)
1658 limit_pc = start_pc + 200;
1660 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
1662 /* Save the previous instruction. If it's an EXTEND, we'll extract
1663 the immediate offset extension from it in mips16_get_imm. */
1666 /* Fetch and decode the instruction. */
1667 inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc);
1669 /* Normally we ignore extend instructions. However, if it is
1670 not followed by a valid prologue instruction, then this
1671 instruction is not part of the prologue either. We must
1672 remember in this case to adjust the end_prologue_addr back
1674 if ((inst & 0xf800) == 0xf000) /* extend */
1676 extend_bytes = MIPS_INSN16_SIZE;
1680 prev_extend_bytes = extend_bytes;
1683 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1684 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1686 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1687 if (offset < 0) /* Negative stack adjustment? */
1688 frame_offset -= offset;
1690 /* Exit loop if a positive stack adjustment is found, which
1691 usually means that the stack cleanup code in the function
1692 epilogue is reached. */
1695 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1697 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1698 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1699 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1701 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1703 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1704 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1705 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1707 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1709 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1710 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1712 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1714 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1715 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1717 else if (inst == 0x673d) /* move $s1, $sp */
1722 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1724 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1725 frame_addr = sp + offset;
1727 frame_adjust = offset;
1729 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1731 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1732 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1733 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
1735 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1737 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1738 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1739 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
1741 else if ((inst & 0xf81f) == 0xe809
1742 && (inst & 0x700) != 0x700) /* entry */
1743 entry_inst = inst; /* Save for later processing. */
1744 else if ((inst & 0xff80) == 0x6480) /* save */
1746 save_inst = inst; /* Save for later processing. */
1747 if (prev_extend_bytes) /* extend */
1748 save_inst |= prev_inst << 16;
1750 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1751 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
1752 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1754 /* This instruction is part of the prologue, but we don't
1755 need to do anything special to handle it. */
1759 /* This instruction is not an instruction typically found
1760 in a prologue, so we must have reached the end of the
1762 if (end_prologue_addr == 0)
1763 end_prologue_addr = cur_pc - prev_extend_bytes;
1767 /* The entry instruction is typically the first instruction in a function,
1768 and it stores registers at offsets relative to the value of the old SP
1769 (before the prologue). But the value of the sp parameter to this
1770 function is the new SP (after the prologue has been executed). So we
1771 can't calculate those offsets until we've seen the entire prologue,
1772 and can calculate what the old SP must have been. */
1773 if (entry_inst != 0)
1775 int areg_count = (entry_inst >> 8) & 7;
1776 int sreg_count = (entry_inst >> 6) & 3;
1778 /* The entry instruction always subtracts 32 from the SP. */
1781 /* Now we can calculate what the SP must have been at the
1782 start of the function prologue. */
1785 /* Check if a0-a3 were saved in the caller's argument save area. */
1786 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1788 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1789 offset += mips_abi_regsize (gdbarch);
1792 /* Check if the ra register was pushed on the stack. */
1794 if (entry_inst & 0x20)
1796 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1797 offset -= mips_abi_regsize (gdbarch);
1800 /* Check if the s0 and s1 registers were pushed on the stack. */
1801 for (reg = 16; reg < sreg_count + 16; reg++)
1803 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1804 offset -= mips_abi_regsize (gdbarch);
1808 /* The SAVE instruction is similar to ENTRY, except that defined by the
1809 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1810 size of the frame is specified as an immediate field of instruction
1811 and an extended variation exists which lets additional registers and
1812 frame space to be specified. The instruction always treats registers
1813 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1814 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
1816 static int args_table[16] = {
1817 0, 0, 0, 0, 1, 1, 1, 1,
1818 2, 2, 2, 0, 3, 3, 4, -1,
1820 static int astatic_table[16] = {
1821 0, 1, 2, 3, 0, 1, 2, 3,
1822 0, 1, 2, 4, 0, 1, 0, -1,
1824 int aregs = (save_inst >> 16) & 0xf;
1825 int xsregs = (save_inst >> 24) & 0x7;
1826 int args = args_table[aregs];
1827 int astatic = astatic_table[aregs];
1832 warning (_("Invalid number of argument registers encoded in SAVE."));
1837 warning (_("Invalid number of static registers encoded in SAVE."));
1841 /* For standard SAVE the frame size of 0 means 128. */
1842 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
1843 if (frame_size == 0 && (save_inst >> 16) == 0)
1846 frame_offset += frame_size;
1848 /* Now we can calculate what the SP must have been at the
1849 start of the function prologue. */
1852 /* Check if A0-A3 were saved in the caller's argument save area. */
1853 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
1855 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1856 offset += mips_abi_regsize (gdbarch);
1861 /* Check if the RA register was pushed on the stack. */
1862 if (save_inst & 0x40)
1864 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1865 offset -= mips_abi_regsize (gdbarch);
1868 /* Check if the S8 register was pushed on the stack. */
1871 set_reg_offset (gdbarch, this_cache, 30, sp + offset);
1872 offset -= mips_abi_regsize (gdbarch);
1875 /* Check if S2-S7 were pushed on the stack. */
1876 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
1878 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1879 offset -= mips_abi_regsize (gdbarch);
1882 /* Check if the S1 register was pushed on the stack. */
1883 if (save_inst & 0x10)
1885 set_reg_offset (gdbarch, this_cache, 17, sp + offset);
1886 offset -= mips_abi_regsize (gdbarch);
1888 /* Check if the S0 register was pushed on the stack. */
1889 if (save_inst & 0x20)
1891 set_reg_offset (gdbarch, this_cache, 16, sp + offset);
1892 offset -= mips_abi_regsize (gdbarch);
1895 /* Check if A0-A3 were pushed on the stack. */
1896 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
1898 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1899 offset -= mips_abi_regsize (gdbarch);
1903 if (this_cache != NULL)
1906 (get_frame_register_signed (this_frame,
1907 gdbarch_num_regs (gdbarch) + frame_reg)
1908 + frame_offset - frame_adjust);
1909 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1910 be able to get rid of the assignment below, evetually. But it's
1911 still needed for now. */
1912 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
1913 + mips_regnum (gdbarch)->pc]
1914 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
1917 /* If we didn't reach the end of the prologue when scanning the function
1918 instructions, then set end_prologue_addr to the address of the
1919 instruction immediately after the last one we scanned. */
1920 if (end_prologue_addr == 0)
1921 end_prologue_addr = cur_pc;
1923 return end_prologue_addr;
1926 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1927 Procedures that use the 32-bit instruction set are handled by the
1928 mips_insn32 unwinder. */
1930 static struct mips_frame_cache *
1931 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
1933 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1934 struct mips_frame_cache *cache;
1936 if ((*this_cache) != NULL)
1937 return (*this_cache);
1938 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1939 (*this_cache) = cache;
1940 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1942 /* Analyze the function prologue. */
1944 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
1945 CORE_ADDR start_addr;
1947 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1948 if (start_addr == 0)
1949 start_addr = heuristic_proc_start (gdbarch, pc);
1950 /* We can't analyze the prologue if we couldn't find the begining
1952 if (start_addr == 0)
1955 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
1958 /* gdbarch_sp_regnum contains the value and not the address. */
1959 trad_frame_set_value (cache->saved_regs,
1960 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
1963 return (*this_cache);
1967 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
1968 struct frame_id *this_id)
1970 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1972 /* This marks the outermost frame. */
1973 if (info->base == 0)
1975 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
1978 static struct value *
1979 mips_insn16_frame_prev_register (struct frame_info *this_frame,
1980 void **this_cache, int regnum)
1982 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1984 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1988 mips_insn16_frame_sniffer (const struct frame_unwind *self,
1989 struct frame_info *this_frame, void **this_cache)
1991 CORE_ADDR pc = get_frame_pc (this_frame);
1992 if (mips_pc_is_mips16 (pc))
1997 static const struct frame_unwind mips_insn16_frame_unwind =
2000 default_frame_unwind_stop_reason,
2001 mips_insn16_frame_this_id,
2002 mips_insn16_frame_prev_register,
2004 mips_insn16_frame_sniffer
2008 mips_insn16_frame_base_address (struct frame_info *this_frame,
2011 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2016 static const struct frame_base mips_insn16_frame_base =
2018 &mips_insn16_frame_unwind,
2019 mips_insn16_frame_base_address,
2020 mips_insn16_frame_base_address,
2021 mips_insn16_frame_base_address
2024 static const struct frame_base *
2025 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
2027 CORE_ADDR pc = get_frame_pc (this_frame);
2028 if (mips_pc_is_mips16 (pc))
2029 return &mips_insn16_frame_base;
2034 /* Mark all the registers as unset in the saved_regs array
2035 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2038 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
2040 if (this_cache == NULL || this_cache->saved_regs == NULL)
2044 const int num_regs = gdbarch_num_regs (gdbarch);
2047 for (i = 0; i < num_regs; i++)
2049 this_cache->saved_regs[i].addr = -1;
2054 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2055 the associated FRAME_CACHE if not null.
2056 Return the address of the first instruction past the prologue. */
2059 mips32_scan_prologue (struct gdbarch *gdbarch,
2060 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2061 struct frame_info *this_frame,
2062 struct mips_frame_cache *this_cache)
2065 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for
2069 int frame_reg = MIPS_SP_REGNUM;
2071 CORE_ADDR end_prologue_addr = 0;
2072 int seen_sp_adjust = 0;
2073 int load_immediate_bytes = 0;
2074 int in_delay_slot = 0;
2075 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
2077 /* Can be called when there's no process, and hence when there's no
2079 if (this_frame != NULL)
2080 sp = get_frame_register_signed (this_frame,
2081 gdbarch_num_regs (gdbarch)
2086 if (limit_pc > start_pc + 200)
2087 limit_pc = start_pc + 200;
2092 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
2094 unsigned long inst, high_word, low_word;
2097 /* Fetch the instruction. */
2098 inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc);
2100 /* Save some code by pre-extracting some useful fields. */
2101 high_word = (inst >> 16) & 0xffff;
2102 low_word = inst & 0xffff;
2103 reg = high_word & 0x1f;
2105 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2106 || high_word == 0x23bd /* addi $sp,$sp,-i */
2107 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2109 if (low_word & 0x8000) /* Negative stack adjustment? */
2110 frame_offset += 0x10000 - low_word;
2112 /* Exit loop if a positive stack adjustment is found, which
2113 usually means that the stack cleanup code in the function
2114 epilogue is reached. */
2118 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2119 && !regsize_is_64_bits)
2121 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
2123 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2124 && regsize_is_64_bits)
2126 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2127 set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
2129 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2131 /* Old gcc frame, r30 is virtual frame pointer. */
2132 if ((long) low_word != frame_offset)
2133 frame_addr = sp + low_word;
2134 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
2136 unsigned alloca_adjust;
2139 frame_addr = get_frame_register_signed
2140 (this_frame, gdbarch_num_regs (gdbarch) + 30);
2142 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2143 if (alloca_adjust > 0)
2145 /* FP > SP + frame_size. This may be because of
2146 an alloca or somethings similar. Fix sp to
2147 "pre-alloca" value, and try again. */
2148 sp += alloca_adjust;
2149 /* Need to reset the status of all registers. Otherwise,
2150 we will hit a guard that prevents the new address
2151 for each register to be recomputed during the second
2153 reset_saved_regs (gdbarch, this_cache);
2158 /* move $30,$sp. With different versions of gas this will be either
2159 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2160 Accept any one of these. */
2161 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2163 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2164 if (this_frame && frame_reg == MIPS_SP_REGNUM)
2166 unsigned alloca_adjust;
2169 frame_addr = get_frame_register_signed
2170 (this_frame, gdbarch_num_regs (gdbarch) + 30);
2172 alloca_adjust = (unsigned) (frame_addr - sp);
2173 if (alloca_adjust > 0)
2175 /* FP > SP + frame_size. This may be because of
2176 an alloca or somethings similar. Fix sp to
2177 "pre-alloca" value, and try again. */
2179 /* Need to reset the status of all registers. Otherwise,
2180 we will hit a guard that prevents the new address
2181 for each register to be recomputed during the second
2183 reset_saved_regs (gdbarch, this_cache);
2188 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2189 && !regsize_is_64_bits)
2191 set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word);
2193 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2194 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2195 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2196 || high_word == 0x3c1c /* lui $gp,n */
2197 || high_word == 0x279c /* addiu $gp,$gp,n */
2198 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
2199 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
2202 /* These instructions are part of the prologue, but we don't
2203 need to do anything special to handle them. */
2205 /* The instructions below load $at or $t0 with an immediate
2206 value in preparation for a stack adjustment via
2207 subu $sp,$sp,[$at,$t0]. These instructions could also
2208 initialize a local variable, so we accept them only before
2209 a stack adjustment instruction was seen. */
2210 else if (!seen_sp_adjust
2211 && (high_word == 0x3c01 /* lui $at,n */
2212 || high_word == 0x3c08 /* lui $t0,n */
2213 || high_word == 0x3421 /* ori $at,$at,n */
2214 || high_word == 0x3508 /* ori $t0,$t0,n */
2215 || high_word == 0x3401 /* ori $at,$zero,n */
2216 || high_word == 0x3408 /* ori $t0,$zero,n */
2219 if (end_prologue_addr == 0)
2220 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
2224 /* This instruction is not an instruction typically found
2225 in a prologue, so we must have reached the end of the
2227 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2228 loop now? Why would we need to continue scanning the function
2230 if (end_prologue_addr == 0)
2231 end_prologue_addr = cur_pc;
2233 /* Check for branches and jumps. For now, only jump to
2234 register are caught (i.e. returns). */
2235 if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8)
2239 /* If the previous instruction was a jump, we must have reached
2240 the end of the prologue by now. Stop scanning so that we do
2241 not go past the function return. */
2246 if (this_cache != NULL)
2249 (get_frame_register_signed (this_frame,
2250 gdbarch_num_regs (gdbarch) + frame_reg)
2252 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2253 this assignment below, eventually. But it's still needed
2255 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2256 + mips_regnum (gdbarch)->pc]
2257 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2261 /* If we didn't reach the end of the prologue when scanning the function
2262 instructions, then set end_prologue_addr to the address of the
2263 instruction immediately after the last one we scanned. */
2264 /* brobecker/2004-10-10: I don't think this would ever happen, but
2265 we may as well be careful and do our best if we have a null
2266 end_prologue_addr. */
2267 if (end_prologue_addr == 0)
2268 end_prologue_addr = cur_pc;
2270 /* In a frameless function, we might have incorrectly
2271 skipped some load immediate instructions. Undo the skipping
2272 if the load immediate was not followed by a stack adjustment. */
2273 if (load_immediate_bytes && !seen_sp_adjust)
2274 end_prologue_addr -= load_immediate_bytes;
2276 return end_prologue_addr;
2279 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2280 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2281 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2284 static struct mips_frame_cache *
2285 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
2287 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2288 struct mips_frame_cache *cache;
2290 if ((*this_cache) != NULL)
2291 return (*this_cache);
2293 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2294 (*this_cache) = cache;
2295 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2297 /* Analyze the function prologue. */
2299 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2300 CORE_ADDR start_addr;
2302 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2303 if (start_addr == 0)
2304 start_addr = heuristic_proc_start (gdbarch, pc);
2305 /* We can't analyze the prologue if we couldn't find the begining
2307 if (start_addr == 0)
2310 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
2313 /* gdbarch_sp_regnum contains the value and not the address. */
2314 trad_frame_set_value (cache->saved_regs,
2315 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
2318 return (*this_cache);
2322 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
2323 struct frame_id *this_id)
2325 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2327 /* This marks the outermost frame. */
2328 if (info->base == 0)
2330 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2333 static struct value *
2334 mips_insn32_frame_prev_register (struct frame_info *this_frame,
2335 void **this_cache, int regnum)
2337 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2339 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2343 mips_insn32_frame_sniffer (const struct frame_unwind *self,
2344 struct frame_info *this_frame, void **this_cache)
2346 CORE_ADDR pc = get_frame_pc (this_frame);
2347 if (! mips_pc_is_mips16 (pc))
2352 static const struct frame_unwind mips_insn32_frame_unwind =
2355 default_frame_unwind_stop_reason,
2356 mips_insn32_frame_this_id,
2357 mips_insn32_frame_prev_register,
2359 mips_insn32_frame_sniffer
2363 mips_insn32_frame_base_address (struct frame_info *this_frame,
2366 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2371 static const struct frame_base mips_insn32_frame_base =
2373 &mips_insn32_frame_unwind,
2374 mips_insn32_frame_base_address,
2375 mips_insn32_frame_base_address,
2376 mips_insn32_frame_base_address
2379 static const struct frame_base *
2380 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
2382 CORE_ADDR pc = get_frame_pc (this_frame);
2383 if (! mips_pc_is_mips16 (pc))
2384 return &mips_insn32_frame_base;
2389 static struct trad_frame_cache *
2390 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
2393 CORE_ADDR start_addr;
2394 CORE_ADDR stack_addr;
2395 struct trad_frame_cache *this_trad_cache;
2396 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2397 int num_regs = gdbarch_num_regs (gdbarch);
2399 if ((*this_cache) != NULL)
2400 return (*this_cache);
2401 this_trad_cache = trad_frame_cache_zalloc (this_frame);
2402 (*this_cache) = this_trad_cache;
2404 /* The return address is in the link register. */
2405 trad_frame_set_reg_realreg (this_trad_cache,
2406 gdbarch_pc_regnum (gdbarch),
2407 num_regs + MIPS_RA_REGNUM);
2409 /* Frame ID, since it's a frameless / stackless function, no stack
2410 space is allocated and SP on entry is the current SP. */
2411 pc = get_frame_pc (this_frame);
2412 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2413 stack_addr = get_frame_register_signed (this_frame,
2414 num_regs + MIPS_SP_REGNUM);
2415 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
2417 /* Assume that the frame's base is the same as the
2419 trad_frame_set_this_base (this_trad_cache, stack_addr);
2421 return this_trad_cache;
2425 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
2426 struct frame_id *this_id)
2428 struct trad_frame_cache *this_trad_cache
2429 = mips_stub_frame_cache (this_frame, this_cache);
2430 trad_frame_get_id (this_trad_cache, this_id);
2433 static struct value *
2434 mips_stub_frame_prev_register (struct frame_info *this_frame,
2435 void **this_cache, int regnum)
2437 struct trad_frame_cache *this_trad_cache
2438 = mips_stub_frame_cache (this_frame, this_cache);
2439 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
2443 mips_stub_frame_sniffer (const struct frame_unwind *self,
2444 struct frame_info *this_frame, void **this_cache)
2447 struct obj_section *s;
2448 CORE_ADDR pc = get_frame_address_in_block (this_frame);
2449 struct minimal_symbol *msym;
2451 /* Use the stub unwinder for unreadable code. */
2452 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2455 if (in_plt_section (pc, NULL))
2458 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2459 s = find_pc_section (pc);
2462 && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
2463 ".MIPS.stubs") == 0)
2466 /* Calling a PIC function from a non-PIC function passes through a
2467 stub. The stub for foo is named ".pic.foo". */
2468 msym = lookup_minimal_symbol_by_pc (pc);
2470 && SYMBOL_LINKAGE_NAME (msym) != NULL
2471 && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0)
2477 static const struct frame_unwind mips_stub_frame_unwind =
2480 default_frame_unwind_stop_reason,
2481 mips_stub_frame_this_id,
2482 mips_stub_frame_prev_register,
2484 mips_stub_frame_sniffer
2488 mips_stub_frame_base_address (struct frame_info *this_frame,
2491 struct trad_frame_cache *this_trad_cache
2492 = mips_stub_frame_cache (this_frame, this_cache);
2493 return trad_frame_get_this_base (this_trad_cache);
2496 static const struct frame_base mips_stub_frame_base =
2498 &mips_stub_frame_unwind,
2499 mips_stub_frame_base_address,
2500 mips_stub_frame_base_address,
2501 mips_stub_frame_base_address
2504 static const struct frame_base *
2505 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
2507 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
2508 return &mips_stub_frame_base;
2513 /* mips_addr_bits_remove - remove useless address bits */
2516 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
2518 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2520 if (is_mips16_addr (addr))
2521 addr = unmake_mips16_addr (addr);
2523 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
2524 /* This hack is a work-around for existing boards using PMON, the
2525 simulator, and any other 64-bit targets that doesn't have true
2526 64-bit addressing. On these targets, the upper 32 bits of
2527 addresses are ignored by the hardware. Thus, the PC or SP are
2528 likely to have been sign extended to all 1s by instruction
2529 sequences that load 32-bit addresses. For example, a typical
2530 piece of code that loads an address is this:
2532 lui $r2, <upper 16 bits>
2533 ori $r2, <lower 16 bits>
2535 But the lui sign-extends the value such that the upper 32 bits
2536 may be all 1s. The workaround is simply to mask off these
2537 bits. In the future, gcc may be changed to support true 64-bit
2538 addressing, and this masking will have to be disabled. */
2539 return addr &= 0xffffffffUL;
2544 /* Instructions used during single-stepping of atomic sequences. */
2545 #define LL_OPCODE 0x30
2546 #define LLD_OPCODE 0x34
2547 #define SC_OPCODE 0x38
2548 #define SCD_OPCODE 0x3c
2550 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2551 instruction and ending with a SC/SCD instruction. If such a sequence
2552 is found, attempt to step through it. A breakpoint is placed at the end of
2556 deal_with_atomic_sequence (struct gdbarch *gdbarch,
2557 struct address_space *aspace, CORE_ADDR pc)
2559 CORE_ADDR breaks[2] = {-1, -1};
2561 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
2565 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
2566 const int atomic_sequence_length = 16; /* Instruction sequence length. */
2571 insn = mips_fetch_instruction (gdbarch, loc);
2572 /* Assume all atomic sequences start with a ll/lld instruction. */
2573 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
2576 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2578 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2581 loc += MIPS_INSN32_SIZE;
2582 insn = mips_fetch_instruction (gdbarch, loc);
2584 /* Assume that there is at most one branch in the atomic
2585 sequence. If a branch is found, put a breakpoint in its
2586 destination address. */
2587 switch (itype_op (insn))
2589 case 0: /* SPECIAL */
2590 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
2591 return 0; /* fallback to the standard single-step code. */
2593 case 1: /* REGIMM */
2594 is_branch = ((itype_rt (insn) & 0xc) == 0); /* B{LT,GE}Z* */
2598 return 0; /* fallback to the standard single-step code. */
2605 case 22: /* BLEZL */
2606 case 23: /* BGTTL */
2612 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2617 branch_bp = loc + mips32_relative_offset (insn) + 4;
2618 if (last_breakpoint >= 1)
2619 return 0; /* More than one branch found, fallback to the
2620 standard single-step code. */
2621 breaks[1] = branch_bp;
2625 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
2629 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2630 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
2633 loc += MIPS_INSN32_SIZE;
2635 /* Insert a breakpoint right after the end of the atomic sequence. */
2638 /* Check for duplicated breakpoints. Check also for a breakpoint
2639 placed (branch instruction's destination) in the atomic sequence. */
2640 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
2641 last_breakpoint = 0;
2643 /* Effectively inserts the breakpoints. */
2644 for (index = 0; index <= last_breakpoint; index++)
2645 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
2650 /* mips_software_single_step() is called just before we want to resume
2651 the inferior, if we want to single-step it but there is no hardware
2652 or kernel single-step support (MIPS on GNU/Linux for example). We find
2653 the target of the coming instruction and breakpoint it. */
2656 mips_software_single_step (struct frame_info *frame)
2658 struct gdbarch *gdbarch = get_frame_arch (frame);
2659 struct address_space *aspace = get_frame_address_space (frame);
2660 CORE_ADDR pc, next_pc;
2662 pc = get_frame_pc (frame);
2663 if (deal_with_atomic_sequence (gdbarch, aspace, pc))
2666 next_pc = mips_next_pc (frame, pc);
2668 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
2672 /* Test whether the PC points to the return instruction at the
2673 end of a function. */
2676 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
2678 if (mips_pc_is_mips16 (pc))
2679 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2680 generates a "jr $ra"; other times it generates code to load
2681 the return address from the stack to an accessible register (such
2682 as $a3), then a "jr" using that register. This second case
2683 is almost impossible to distinguish from an indirect jump
2684 used for switch statements, so we don't even try. */
2685 return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */
2687 return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */
2691 /* This fencepost looks highly suspicious to me. Removing it also
2692 seems suspicious as it could affect remote debugging across serial
2696 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
2702 struct inferior *inf;
2704 pc = gdbarch_addr_bits_remove (gdbarch, pc);
2706 fence = start_pc - heuristic_fence_post;
2710 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
2711 fence = VM_MIN_ADDRESS;
2713 instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE;
2715 inf = current_inferior ();
2717 /* Search back for previous return. */
2718 for (start_pc -= instlen;; start_pc -= instlen)
2719 if (start_pc < fence)
2721 /* It's not clear to me why we reach this point when
2722 stop_soon, but with this test, at least we
2723 don't print out warnings for every child forked (eg, on
2724 decstation). 22apr93 rich@cygnus.com. */
2725 if (inf->control.stop_soon == NO_STOP_QUIETLY)
2727 static int blurb_printed = 0;
2729 warning (_("GDB can't find the start of the function at %s."),
2730 paddress (gdbarch, pc));
2734 /* This actually happens frequently in embedded
2735 development, when you first connect to a board
2736 and your stack pointer and pc are nowhere in
2737 particular. This message needs to give people
2738 in that situation enough information to
2739 determine that it's no big deal. */
2740 printf_filtered ("\n\
2741 GDB is unable to find the start of the function at %s\n\
2742 and thus can't determine the size of that function's stack frame.\n\
2743 This means that GDB may be unable to access that stack frame, or\n\
2744 the frames below it.\n\
2745 This problem is most likely caused by an invalid program counter or\n\
2747 However, if you think GDB should simply search farther back\n\
2748 from %s for code which looks like the beginning of a\n\
2749 function, you can increase the range of the search using the `set\n\
2750 heuristic-fence-post' command.\n",
2751 paddress (gdbarch, pc), paddress (gdbarch, pc));
2758 else if (mips_pc_is_mips16 (start_pc))
2760 unsigned short inst;
2762 /* On MIPS16, any one of the following is likely to be the
2763 start of a function:
2769 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2770 inst = mips_fetch_instruction (gdbarch, start_pc);
2771 if ((inst & 0xff80) == 0x6480) /* save */
2773 if (start_pc - instlen >= fence)
2775 inst = mips_fetch_instruction (gdbarch, start_pc - instlen);
2776 if ((inst & 0xf800) == 0xf000) /* extend */
2777 start_pc -= instlen;
2781 else if (((inst & 0xf81f) == 0xe809
2782 && (inst & 0x700) != 0x700) /* entry */
2783 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
2784 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
2785 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
2787 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
2788 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2793 else if (mips_about_to_return (gdbarch, start_pc))
2795 /* Skip return and its delay slot. */
2796 start_pc += 2 * MIPS_INSN32_SIZE;
2803 struct mips_objfile_private
2809 /* According to the current ABI, should the type be passed in a
2810 floating-point register (assuming that there is space)? When there
2811 is no FPU, FP are not even considered as possible candidates for
2812 FP registers and, consequently this returns false - forces FP
2813 arguments into integer registers. */
2816 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
2817 struct type *arg_type)
2819 return ((typecode == TYPE_CODE_FLT
2820 || (MIPS_EABI (gdbarch)
2821 && (typecode == TYPE_CODE_STRUCT
2822 || typecode == TYPE_CODE_UNION)
2823 && TYPE_NFIELDS (arg_type) == 1
2824 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
2826 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
2829 /* On o32, argument passing in GPRs depends on the alignment of the type being
2830 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2833 mips_type_needs_double_align (struct type *type)
2835 enum type_code typecode = TYPE_CODE (type);
2837 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2839 else if (typecode == TYPE_CODE_STRUCT)
2841 if (TYPE_NFIELDS (type) < 1)
2843 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2845 else if (typecode == TYPE_CODE_UNION)
2849 n = TYPE_NFIELDS (type);
2850 for (i = 0; i < n; i++)
2851 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2858 /* Adjust the address downward (direction of stack growth) so that it
2859 is correctly aligned for a new stack frame. */
2861 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2863 return align_down (addr, 16);
2867 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2868 struct regcache *regcache, CORE_ADDR bp_addr,
2869 int nargs, struct value **args, CORE_ADDR sp,
2870 int struct_return, CORE_ADDR struct_addr)
2876 int stack_offset = 0;
2877 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2879 CORE_ADDR func_addr = find_function_addr (function, NULL);
2880 int regsize = mips_abi_regsize (gdbarch);
2882 /* For shared libraries, "t9" needs to point at the function
2884 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2886 /* Set the return address register to point to the entry point of
2887 the program, where a breakpoint lies in wait. */
2888 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2890 /* First ensure that the stack and structure return address (if any)
2891 are properly aligned. The stack has to be at least 64-bit
2892 aligned even on 32-bit machines, because doubles must be 64-bit
2893 aligned. For n32 and n64, stack frames need to be 128-bit
2894 aligned, so we round to this widest known alignment. */
2896 sp = align_down (sp, 16);
2897 struct_addr = align_down (struct_addr, 16);
2899 /* Now make space on the stack for the args. We allocate more
2900 than necessary for EABI, because the first few arguments are
2901 passed in registers, but that's OK. */
2902 for (argnum = 0; argnum < nargs; argnum++)
2903 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
2904 sp -= align_up (len, 16);
2907 fprintf_unfiltered (gdb_stdlog,
2908 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2909 paddress (gdbarch, sp), (long) align_up (len, 16));
2911 /* Initialize the integer and float register pointers. */
2912 argreg = MIPS_A0_REGNUM;
2913 float_argreg = mips_fpa0_regnum (gdbarch);
2915 /* The struct_return pointer occupies the first parameter-passing reg. */
2919 fprintf_unfiltered (gdb_stdlog,
2920 "mips_eabi_push_dummy_call: "
2921 "struct_return reg=%d %s\n",
2922 argreg, paddress (gdbarch, struct_addr));
2923 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
2926 /* Now load as many as possible of the first arguments into
2927 registers, and push the rest onto the stack. Loop thru args
2928 from first to last. */
2929 for (argnum = 0; argnum < nargs; argnum++)
2931 const gdb_byte *val;
2932 gdb_byte valbuf[MAX_REGISTER_SIZE];
2933 struct value *arg = args[argnum];
2934 struct type *arg_type = check_typedef (value_type (arg));
2935 int len = TYPE_LENGTH (arg_type);
2936 enum type_code typecode = TYPE_CODE (arg_type);
2939 fprintf_unfiltered (gdb_stdlog,
2940 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2941 argnum + 1, len, (int) typecode);
2943 /* Function pointer arguments to mips16 code need to be made into
2945 if (typecode == TYPE_CODE_PTR
2946 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
2948 CORE_ADDR addr = extract_signed_integer (value_contents (arg),
2950 if (mips_pc_is_mips16 (addr))
2952 store_signed_integer (valbuf, len, byte_order,
2953 make_mips16_addr (addr));
2957 val = value_contents (arg);
2959 /* The EABI passes structures that do not fit in a register by
2961 else if (len > regsize
2962 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2964 store_unsigned_integer (valbuf, regsize, byte_order,
2965 value_address (arg));
2966 typecode = TYPE_CODE_PTR;
2970 fprintf_unfiltered (gdb_stdlog, " push");
2973 val = value_contents (arg);
2975 /* 32-bit ABIs always start floating point arguments in an
2976 even-numbered floating point register. Round the FP register
2977 up before the check to see if there are any FP registers
2978 left. Non MIPS_EABI targets also pass the FP in the integer
2979 registers so also round up normal registers. */
2980 if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
2982 if ((float_argreg & 1))
2986 /* Floating point arguments passed in registers have to be
2987 treated specially. On 32-bit architectures, doubles
2988 are passed in register pairs; the even register gets
2989 the low word, and the odd register gets the high word.
2990 On non-EABI processors, the first two floating point arguments are
2991 also copied to general registers, because MIPS16 functions
2992 don't use float registers for arguments. This duplication of
2993 arguments in general registers can't hurt non-MIPS16 functions
2994 because those registers are normally skipped. */
2995 /* MIPS_EABI squeezes a struct that contains a single floating
2996 point value into an FP register instead of pushing it onto the
2998 if (fp_register_arg_p (gdbarch, typecode, arg_type)
2999 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
3001 /* EABI32 will pass doubles in consecutive registers, even on
3002 64-bit cores. At one time, we used to check the size of
3003 `float_argreg' to determine whether or not to pass doubles
3004 in consecutive registers, but this is not sufficient for
3005 making the ABI determination. */
3006 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
3008 int low_offset = gdbarch_byte_order (gdbarch)
3009 == BFD_ENDIAN_BIG ? 4 : 0;
3012 /* Write the low word of the double to the even register(s). */
3013 regval = extract_signed_integer (val + low_offset,
3016 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3017 float_argreg, phex (regval, 4));
3018 regcache_cooked_write_signed (regcache, float_argreg++, regval);
3020 /* Write the high word of the double to the odd register(s). */
3021 regval = extract_signed_integer (val + 4 - low_offset,
3024 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3025 float_argreg, phex (regval, 4));
3026 regcache_cooked_write_signed (regcache, float_argreg++, regval);
3030 /* This is a floating point value that fits entirely
3031 in a single register. */
3032 /* On 32 bit ABI's the float_argreg is further adjusted
3033 above to ensure that it is even register aligned. */
3034 LONGEST regval = extract_signed_integer (val, len, byte_order);
3036 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3037 float_argreg, phex (regval, len));
3038 regcache_cooked_write_signed (regcache, float_argreg++, regval);
3043 /* Copy the argument to general registers or the stack in
3044 register-sized pieces. Large arguments are split between
3045 registers and stack. */
3046 /* Note: structs whose size is not a multiple of regsize
3047 are treated specially: Irix cc passes
3048 them in registers where gcc sometimes puts them on the
3049 stack. For maximum compatibility, we will put them in
3051 int odd_sized_struct = (len > regsize && len % regsize != 0);
3053 /* Note: Floating-point values that didn't fit into an FP
3054 register are only written to memory. */
3057 /* Remember if the argument was written to the stack. */
3058 int stack_used_p = 0;
3059 int partial_len = (len < regsize ? len : regsize);
3062 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3065 /* Write this portion of the argument to the stack. */
3066 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
3068 || fp_register_arg_p (gdbarch, typecode, arg_type))
3070 /* Should shorter than int integer values be
3071 promoted to int before being stored? */
3072 int longword_offset = 0;
3075 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
3078 && (typecode == TYPE_CODE_INT
3079 || typecode == TYPE_CODE_PTR
3080 || typecode == TYPE_CODE_FLT) && len <= 4)
3081 longword_offset = regsize - len;
3082 else if ((typecode == TYPE_CODE_STRUCT
3083 || typecode == TYPE_CODE_UNION)
3084 && TYPE_LENGTH (arg_type) < regsize)
3085 longword_offset = regsize - len;
3090 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
3091 paddress (gdbarch, stack_offset));
3092 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
3093 paddress (gdbarch, longword_offset));
3096 addr = sp + stack_offset + longword_offset;
3101 fprintf_unfiltered (gdb_stdlog, " @%s ",
3102 paddress (gdbarch, addr));
3103 for (i = 0; i < partial_len; i++)
3105 fprintf_unfiltered (gdb_stdlog, "%02x",
3109 write_memory (addr, val, partial_len);
3112 /* Note!!! This is NOT an else clause. Odd sized
3113 structs may go thru BOTH paths. Floating point
3114 arguments will not. */
3115 /* Write this portion of the argument to a general
3116 purpose register. */
3117 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
3118 && !fp_register_arg_p (gdbarch, typecode, arg_type))
3121 extract_signed_integer (val, partial_len, byte_order);
3124 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3126 phex (regval, regsize));
3127 regcache_cooked_write_signed (regcache, argreg, regval);
3134 /* Compute the offset into the stack at which we will
3135 copy the next parameter.
3137 In the new EABI (and the NABI32), the stack_offset
3138 only needs to be adjusted when it has been used. */
3141 stack_offset += align_up (partial_len, regsize);
3145 fprintf_unfiltered (gdb_stdlog, "\n");
3148 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3150 /* Return adjusted stack pointer. */
3154 /* Determine the return value convention being used. */
3156 static enum return_value_convention
3157 mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type,
3158 struct type *type, struct regcache *regcache,
3159 gdb_byte *readbuf, const gdb_byte *writebuf)
3161 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3162 int fp_return_type = 0;
3163 int offset, regnum, xfer;
3165 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
3166 return RETURN_VALUE_STRUCT_CONVENTION;
3168 /* Floating point type? */
3169 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
3171 if (TYPE_CODE (type) == TYPE_CODE_FLT)
3173 /* Structs with a single field of float type
3174 are returned in a floating point register. */
3175 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
3176 || TYPE_CODE (type) == TYPE_CODE_UNION)
3177 && TYPE_NFIELDS (type) == 1)
3179 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
3181 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
3188 /* A floating-point value belongs in the least significant part
3191 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3192 regnum = mips_regnum (gdbarch)->fp0;
3196 /* An integer value goes in V0/V1. */
3198 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
3199 regnum = MIPS_V0_REGNUM;
3202 offset < TYPE_LENGTH (type);
3203 offset += mips_abi_regsize (gdbarch), regnum++)
3205 xfer = mips_abi_regsize (gdbarch);
3206 if (offset + xfer > TYPE_LENGTH (type))
3207 xfer = TYPE_LENGTH (type) - offset;
3208 mips_xfer_register (gdbarch, regcache,
3209 gdbarch_num_regs (gdbarch) + regnum, xfer,
3210 gdbarch_byte_order (gdbarch), readbuf, writebuf,
3214 return RETURN_VALUE_REGISTER_CONVENTION;
3218 /* N32/N64 ABI stuff. */
3220 /* Search for a naturally aligned double at OFFSET inside a struct
3221 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3225 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
3230 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
3233 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
3236 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
3239 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
3242 struct type *field_type;
3244 /* We're only looking at normal fields. */
3245 if (field_is_static (&TYPE_FIELD (arg_type, i))
3246 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
3249 /* If we have gone past the offset, there is no double to pass. */
3250 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
3254 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
3256 /* If this field is entirely before the requested offset, go
3257 on to the next one. */
3258 if (pos + TYPE_LENGTH (field_type) <= offset)
3261 /* If this is our special aligned double, we can stop. */
3262 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
3263 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
3266 /* This field starts at or before the requested offset, and
3267 overlaps it. If it is a structure, recurse inwards. */
3268 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
3275 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3276 struct regcache *regcache, CORE_ADDR bp_addr,
3277 int nargs, struct value **args, CORE_ADDR sp,
3278 int struct_return, CORE_ADDR struct_addr)
3284 int stack_offset = 0;
3285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3286 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3287 CORE_ADDR func_addr = find_function_addr (function, NULL);
3289 /* For shared libraries, "t9" needs to point at the function
3291 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3293 /* Set the return address register to point to the entry point of
3294 the program, where a breakpoint lies in wait. */
3295 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3297 /* First ensure that the stack and structure return address (if any)
3298 are properly aligned. The stack has to be at least 64-bit
3299 aligned even on 32-bit machines, because doubles must be 64-bit
3300 aligned. For n32 and n64, stack frames need to be 128-bit
3301 aligned, so we round to this widest known alignment. */
3303 sp = align_down (sp, 16);
3304 struct_addr = align_down (struct_addr, 16);
3306 /* Now make space on the stack for the args. */
3307 for (argnum = 0; argnum < nargs; argnum++)
3308 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
3309 sp -= align_up (len, 16);
3312 fprintf_unfiltered (gdb_stdlog,
3313 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3314 paddress (gdbarch, sp), (long) align_up (len, 16));
3316 /* Initialize the integer and float register pointers. */
3317 argreg = MIPS_A0_REGNUM;
3318 float_argreg = mips_fpa0_regnum (gdbarch);
3320 /* The struct_return pointer occupies the first parameter-passing reg. */
3324 fprintf_unfiltered (gdb_stdlog,
3325 "mips_n32n64_push_dummy_call: "
3326 "struct_return reg=%d %s\n",
3327 argreg, paddress (gdbarch, struct_addr));
3328 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3331 /* Now load as many as possible of the first arguments into
3332 registers, and push the rest onto the stack. Loop thru args
3333 from first to last. */
3334 for (argnum = 0; argnum < nargs; argnum++)
3336 const gdb_byte *val;
3337 struct value *arg = args[argnum];
3338 struct type *arg_type = check_typedef (value_type (arg));
3339 int len = TYPE_LENGTH (arg_type);
3340 enum type_code typecode = TYPE_CODE (arg_type);
3343 fprintf_unfiltered (gdb_stdlog,
3344 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3345 argnum + 1, len, (int) typecode);
3347 val = value_contents (arg);
3349 /* A 128-bit long double value requires an even-odd pair of
3350 floating-point registers. */
3352 && fp_register_arg_p (gdbarch, typecode, arg_type)
3353 && (float_argreg & 1))
3359 if (fp_register_arg_p (gdbarch, typecode, arg_type)
3360 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3362 /* This is a floating point value that fits entirely
3363 in a single register or a pair of registers. */
3364 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3365 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
3367 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3368 float_argreg, phex (regval, reglen));
3369 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3372 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3373 argreg, phex (regval, reglen));
3374 regcache_cooked_write_unsigned (regcache, argreg, regval);
3379 regval = extract_unsigned_integer (val + reglen,
3380 reglen, byte_order);
3382 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3383 float_argreg, phex (regval, reglen));
3384 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3387 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3388 argreg, phex (regval, reglen));
3389 regcache_cooked_write_unsigned (regcache, argreg, regval);
3396 /* Copy the argument to general registers or the stack in
3397 register-sized pieces. Large arguments are split between
3398 registers and stack. */
3399 /* For N32/N64, structs, unions, or other composite types are
3400 treated as a sequence of doublewords, and are passed in integer
3401 or floating point registers as though they were simple scalar
3402 parameters to the extent that they fit, with any excess on the
3403 stack packed according to the normal memory layout of the
3405 The caller does not reserve space for the register arguments;
3406 the callee is responsible for reserving it if required. */
3407 /* Note: Floating-point values that didn't fit into an FP
3408 register are only written to memory. */
3411 /* Remember if the argument was written to the stack. */
3412 int stack_used_p = 0;
3413 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3416 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3419 if (fp_register_arg_p (gdbarch, typecode, arg_type))
3420 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
3422 /* Write this portion of the argument to the stack. */
3423 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
3425 /* Should shorter than int integer values be
3426 promoted to int before being stored? */
3427 int longword_offset = 0;
3430 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
3432 if ((typecode == TYPE_CODE_INT
3433 || typecode == TYPE_CODE_PTR)
3435 longword_offset = MIPS64_REGSIZE - len;
3440 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
3441 paddress (gdbarch, stack_offset));
3442 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
3443 paddress (gdbarch, longword_offset));
3446 addr = sp + stack_offset + longword_offset;
3451 fprintf_unfiltered (gdb_stdlog, " @%s ",
3452 paddress (gdbarch, addr));
3453 for (i = 0; i < partial_len; i++)
3455 fprintf_unfiltered (gdb_stdlog, "%02x",
3459 write_memory (addr, val, partial_len);
3462 /* Note!!! This is NOT an else clause. Odd sized
3463 structs may go thru BOTH paths. */
3464 /* Write this portion of the argument to a general
3465 purpose register. */
3466 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3470 /* Sign extend pointers, 32-bit integers and signed
3471 16-bit and 8-bit integers; everything else is taken
3474 if ((partial_len == 4
3475 && (typecode == TYPE_CODE_PTR
3476 || typecode == TYPE_CODE_INT))
3478 && typecode == TYPE_CODE_INT
3479 && !TYPE_UNSIGNED (arg_type)))
3480 regval = extract_signed_integer (val, partial_len,
3483 regval = extract_unsigned_integer (val, partial_len,
3486 /* A non-floating-point argument being passed in a
3487 general register. If a struct or union, and if
3488 the remaining length is smaller than the register
3489 size, we have to adjust the register value on
3492 It does not seem to be necessary to do the
3493 same for integral types. */
3495 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3496 && partial_len < MIPS64_REGSIZE
3497 && (typecode == TYPE_CODE_STRUCT
3498 || typecode == TYPE_CODE_UNION))
3499 regval <<= ((MIPS64_REGSIZE - partial_len)
3503 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3505 phex (regval, MIPS64_REGSIZE));
3506 regcache_cooked_write_unsigned (regcache, argreg, regval);
3508 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
3509 TYPE_LENGTH (arg_type) - len))
3512 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
3514 phex (regval, MIPS64_REGSIZE));
3515 regcache_cooked_write_unsigned (regcache, float_argreg,
3526 /* Compute the offset into the stack at which we will
3527 copy the next parameter.
3529 In N32 (N64?), the stack_offset only needs to be
3530 adjusted when it has been used. */
3533 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
3537 fprintf_unfiltered (gdb_stdlog, "\n");
3540 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3542 /* Return adjusted stack pointer. */
3546 static enum return_value_convention
3547 mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type,
3548 struct type *type, struct regcache *regcache,
3549 gdb_byte *readbuf, const gdb_byte *writebuf)
3551 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3553 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3555 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3556 if needed), as appropriate for the type. Composite results (struct,
3557 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3560 * A struct with only one or two floating point fields is returned in $f0
3561 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3564 * Any other composite results of at most 128 bits are returned in
3565 $2 (first 64 bits) and $3 (remainder, if necessary).
3567 * Larger composite results are handled by converting the function to a
3568 procedure with an implicit first parameter, which is a pointer to an area
3569 reserved by the caller to receive the result. [The o32-bit ABI requires
3570 that all composite results be handled by conversion to implicit first
3571 parameters. The MIPS/SGI Fortran implementation has always made a
3572 specific exception to return COMPLEX results in the floating point
3575 if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
3576 return RETURN_VALUE_STRUCT_CONVENTION;
3577 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3578 && TYPE_LENGTH (type) == 16
3579 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3581 /* A 128-bit floating-point value fills both $f0 and $f2. The
3582 two registers are used in the same as memory order, so the
3583 eight bytes with the lower memory address are in $f0. */
3585 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
3586 mips_xfer_register (gdbarch, regcache,
3587 gdbarch_num_regs (gdbarch)
3588 + mips_regnum (gdbarch)->fp0,
3589 8, gdbarch_byte_order (gdbarch),
3590 readbuf, writebuf, 0);
3591 mips_xfer_register (gdbarch, regcache,
3592 gdbarch_num_regs (gdbarch)
3593 + mips_regnum (gdbarch)->fp0 + 2,
3594 8, gdbarch_byte_order (gdbarch),
3595 readbuf ? readbuf + 8 : readbuf,
3596 writebuf ? writebuf + 8 : writebuf, 0);
3597 return RETURN_VALUE_REGISTER_CONVENTION;
3599 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3600 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3602 /* A single or double floating-point value that fits in FP0. */
3604 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3605 mips_xfer_register (gdbarch, regcache,
3606 gdbarch_num_regs (gdbarch)
3607 + mips_regnum (gdbarch)->fp0,
3609 gdbarch_byte_order (gdbarch),
3610 readbuf, writebuf, 0);
3611 return RETURN_VALUE_REGISTER_CONVENTION;
3613 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3614 && TYPE_NFIELDS (type) <= 2
3615 && TYPE_NFIELDS (type) >= 1
3616 && ((TYPE_NFIELDS (type) == 1
3617 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3619 || (TYPE_NFIELDS (type) == 2
3620 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3622 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
3623 == TYPE_CODE_FLT))))
3625 /* A struct that contains one or two floats. Each value is part
3626 in the least significant part of their floating point
3627 register (or GPR, for soft float). */
3630 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
3631 ? mips_regnum (gdbarch)->fp0
3633 field < TYPE_NFIELDS (type); field++, regnum += 2)
3635 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3638 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3640 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
3642 /* A 16-byte long double field goes in two consecutive
3644 mips_xfer_register (gdbarch, regcache,
3645 gdbarch_num_regs (gdbarch) + regnum,
3647 gdbarch_byte_order (gdbarch),
3648 readbuf, writebuf, offset);
3649 mips_xfer_register (gdbarch, regcache,
3650 gdbarch_num_regs (gdbarch) + regnum + 1,
3652 gdbarch_byte_order (gdbarch),
3653 readbuf, writebuf, offset + 8);
3656 mips_xfer_register (gdbarch, regcache,
3657 gdbarch_num_regs (gdbarch) + regnum,
3658 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3659 gdbarch_byte_order (gdbarch),
3660 readbuf, writebuf, offset);
3662 return RETURN_VALUE_REGISTER_CONVENTION;
3664 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3665 || TYPE_CODE (type) == TYPE_CODE_UNION
3666 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3668 /* A composite type. Extract the left justified value,
3669 regardless of the byte order. I.e. DO NOT USE
3673 for (offset = 0, regnum = MIPS_V0_REGNUM;
3674 offset < TYPE_LENGTH (type);
3675 offset += register_size (gdbarch, regnum), regnum++)
3677 int xfer = register_size (gdbarch, regnum);
3678 if (offset + xfer > TYPE_LENGTH (type))
3679 xfer = TYPE_LENGTH (type) - offset;
3681 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3682 offset, xfer, regnum);
3683 mips_xfer_register (gdbarch, regcache,
3684 gdbarch_num_regs (gdbarch) + regnum,
3685 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
3688 return RETURN_VALUE_REGISTER_CONVENTION;
3692 /* A scalar extract each part but least-significant-byte
3696 for (offset = 0, regnum = MIPS_V0_REGNUM;
3697 offset < TYPE_LENGTH (type);
3698 offset += register_size (gdbarch, regnum), regnum++)
3700 int xfer = register_size (gdbarch, regnum);
3701 if (offset + xfer > TYPE_LENGTH (type))
3702 xfer = TYPE_LENGTH (type) - offset;
3704 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3705 offset, xfer, regnum);
3706 mips_xfer_register (gdbarch, regcache,
3707 gdbarch_num_regs (gdbarch) + regnum,
3708 xfer, gdbarch_byte_order (gdbarch),
3709 readbuf, writebuf, offset);
3711 return RETURN_VALUE_REGISTER_CONVENTION;
3715 /* O32 ABI stuff. */
3718 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3719 struct regcache *regcache, CORE_ADDR bp_addr,
3720 int nargs, struct value **args, CORE_ADDR sp,
3721 int struct_return, CORE_ADDR struct_addr)
3727 int stack_offset = 0;
3728 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3729 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3730 CORE_ADDR func_addr = find_function_addr (function, NULL);
3732 /* For shared libraries, "t9" needs to point at the function
3734 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3736 /* Set the return address register to point to the entry point of
3737 the program, where a breakpoint lies in wait. */
3738 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3740 /* First ensure that the stack and structure return address (if any)
3741 are properly aligned. The stack has to be at least 64-bit
3742 aligned even on 32-bit machines, because doubles must be 64-bit
3743 aligned. For n32 and n64, stack frames need to be 128-bit
3744 aligned, so we round to this widest known alignment. */
3746 sp = align_down (sp, 16);
3747 struct_addr = align_down (struct_addr, 16);
3749 /* Now make space on the stack for the args. */
3750 for (argnum = 0; argnum < nargs; argnum++)
3752 struct type *arg_type = check_typedef (value_type (args[argnum]));
3753 int arglen = TYPE_LENGTH (arg_type);
3755 /* Align to double-word if necessary. */
3756 if (mips_type_needs_double_align (arg_type))
3757 len = align_up (len, MIPS32_REGSIZE * 2);
3758 /* Allocate space on the stack. */
3759 len += align_up (arglen, MIPS32_REGSIZE);
3761 sp -= align_up (len, 16);
3764 fprintf_unfiltered (gdb_stdlog,
3765 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3766 paddress (gdbarch, sp), (long) align_up (len, 16));
3768 /* Initialize the integer and float register pointers. */
3769 argreg = MIPS_A0_REGNUM;
3770 float_argreg = mips_fpa0_regnum (gdbarch);
3772 /* The struct_return pointer occupies the first parameter-passing reg. */
3776 fprintf_unfiltered (gdb_stdlog,
3777 "mips_o32_push_dummy_call: "
3778 "struct_return reg=%d %s\n",
3779 argreg, paddress (gdbarch, struct_addr));
3780 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3781 stack_offset += MIPS32_REGSIZE;
3784 /* Now load as many as possible of the first arguments into
3785 registers, and push the rest onto the stack. Loop thru args
3786 from first to last. */
3787 for (argnum = 0; argnum < nargs; argnum++)
3789 const gdb_byte *val;
3790 struct value *arg = args[argnum];
3791 struct type *arg_type = check_typedef (value_type (arg));
3792 int len = TYPE_LENGTH (arg_type);
3793 enum type_code typecode = TYPE_CODE (arg_type);
3796 fprintf_unfiltered (gdb_stdlog,
3797 "mips_o32_push_dummy_call: %d len=%d type=%d",
3798 argnum + 1, len, (int) typecode);
3800 val = value_contents (arg);
3802 /* 32-bit ABIs always start floating point arguments in an
3803 even-numbered floating point register. Round the FP register
3804 up before the check to see if there are any FP registers
3805 left. O32/O64 targets also pass the FP in the integer
3806 registers so also round up normal registers. */
3807 if (fp_register_arg_p (gdbarch, typecode, arg_type))
3809 if ((float_argreg & 1))
3813 /* Floating point arguments passed in registers have to be
3814 treated specially. On 32-bit architectures, doubles
3815 are passed in register pairs; the even register gets
3816 the low word, and the odd register gets the high word.
3817 On O32/O64, the first two floating point arguments are
3818 also copied to general registers, because MIPS16 functions
3819 don't use float registers for arguments. This duplication of
3820 arguments in general registers can't hurt non-MIPS16 functions
3821 because those registers are normally skipped. */
3823 if (fp_register_arg_p (gdbarch, typecode, arg_type)
3824 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
3826 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
3828 int low_offset = gdbarch_byte_order (gdbarch)
3829 == BFD_ENDIAN_BIG ? 4 : 0;
3830 unsigned long regval;
3832 /* Write the low word of the double to the even register(s). */
3833 regval = extract_unsigned_integer (val + low_offset,
3836 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3837 float_argreg, phex (regval, 4));
3838 regcache_cooked_write_unsigned (regcache,
3839 float_argreg++, regval);
3841 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3842 argreg, phex (regval, 4));
3843 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3845 /* Write the high word of the double to the odd register(s). */
3846 regval = extract_unsigned_integer (val + 4 - low_offset,
3849 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3850 float_argreg, phex (regval, 4));
3851 regcache_cooked_write_unsigned (regcache,
3852 float_argreg++, regval);
3855 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3856 argreg, phex (regval, 4));
3857 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3861 /* This is a floating point value that fits entirely
3862 in a single register. */
3863 /* On 32 bit ABI's the float_argreg is further adjusted
3864 above to ensure that it is even register aligned. */
3865 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
3867 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3868 float_argreg, phex (regval, len));
3869 regcache_cooked_write_unsigned (regcache,
3870 float_argreg++, regval);
3871 /* Although two FP registers are reserved for each
3872 argument, only one corresponding integer register is
3875 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3876 argreg, phex (regval, len));
3877 regcache_cooked_write_unsigned (regcache, argreg++, regval);
3879 /* Reserve space for the FP register. */
3880 stack_offset += align_up (len, MIPS32_REGSIZE);
3884 /* Copy the argument to general registers or the stack in
3885 register-sized pieces. Large arguments are split between
3886 registers and stack. */
3887 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3888 are treated specially: Irix cc passes
3889 them in registers where gcc sometimes puts them on the
3890 stack. For maximum compatibility, we will put them in
3892 int odd_sized_struct = (len > MIPS32_REGSIZE
3893 && len % MIPS32_REGSIZE != 0);
3894 /* Structures should be aligned to eight bytes (even arg registers)
3895 on MIPS_ABI_O32, if their first member has double precision. */
3896 if (mips_type_needs_double_align (arg_type))
3901 stack_offset += MIPS32_REGSIZE;
3906 /* Remember if the argument was written to the stack. */
3907 int stack_used_p = 0;
3908 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
3911 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3914 /* Write this portion of the argument to the stack. */
3915 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
3916 || odd_sized_struct)
3918 /* Should shorter than int integer values be
3919 promoted to int before being stored? */
3920 int longword_offset = 0;
3926 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
3927 paddress (gdbarch, stack_offset));
3928 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
3929 paddress (gdbarch, longword_offset));
3932 addr = sp + stack_offset + longword_offset;
3937 fprintf_unfiltered (gdb_stdlog, " @%s ",
3938 paddress (gdbarch, addr));
3939 for (i = 0; i < partial_len; i++)
3941 fprintf_unfiltered (gdb_stdlog, "%02x",
3945 write_memory (addr, val, partial_len);
3948 /* Note!!! This is NOT an else clause. Odd sized
3949 structs may go thru BOTH paths. */
3950 /* Write this portion of the argument to a general
3951 purpose register. */
3952 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3954 LONGEST regval = extract_signed_integer (val, partial_len,
3956 /* Value may need to be sign extended, because
3957 mips_isa_regsize() != mips_abi_regsize(). */
3959 /* A non-floating-point argument being passed in a
3960 general register. If a struct or union, and if
3961 the remaining length is smaller than the register
3962 size, we have to adjust the register value on
3965 It does not seem to be necessary to do the
3966 same for integral types.
3968 Also don't do this adjustment on O64 binaries.
3970 cagney/2001-07-23: gdb/179: Also, GCC, when
3971 outputting LE O32 with sizeof (struct) <
3972 mips_abi_regsize(), generates a left shift
3973 as part of storing the argument in a register
3974 (the left shift isn't generated when
3975 sizeof (struct) >= mips_abi_regsize()). Since
3976 it is quite possible that this is GCC
3977 contradicting the LE/O32 ABI, GDB has not been
3978 adjusted to accommodate this. Either someone
3979 needs to demonstrate that the LE/O32 ABI
3980 specifies such a left shift OR this new ABI gets
3981 identified as such and GDB gets tweaked
3984 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3985 && partial_len < MIPS32_REGSIZE
3986 && (typecode == TYPE_CODE_STRUCT
3987 || typecode == TYPE_CODE_UNION))
3988 regval <<= ((MIPS32_REGSIZE - partial_len)
3992 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3994 phex (regval, MIPS32_REGSIZE));
3995 regcache_cooked_write_unsigned (regcache, argreg, regval);
3998 /* Prevent subsequent floating point arguments from
3999 being passed in floating point registers. */
4000 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
4006 /* Compute the offset into the stack at which we will
4007 copy the next parameter.
4009 In older ABIs, the caller reserved space for
4010 registers that contained arguments. This was loosely
4011 refered to as their "home". Consequently, space is
4012 always allocated. */
4014 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
4018 fprintf_unfiltered (gdb_stdlog, "\n");
4021 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4023 /* Return adjusted stack pointer. */
4027 static enum return_value_convention
4028 mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type,
4029 struct type *type, struct regcache *regcache,
4030 gdb_byte *readbuf, const gdb_byte *writebuf)
4032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4034 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4035 || TYPE_CODE (type) == TYPE_CODE_UNION
4036 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
4037 return RETURN_VALUE_STRUCT_CONVENTION;
4038 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4039 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4041 /* A single-precision floating-point value. It fits in the
4042 least significant part of FP0. */
4044 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4045 mips_xfer_register (gdbarch, regcache,
4046 gdbarch_num_regs (gdbarch)
4047 + mips_regnum (gdbarch)->fp0,
4049 gdbarch_byte_order (gdbarch),
4050 readbuf, writebuf, 0);
4051 return RETURN_VALUE_REGISTER_CONVENTION;
4053 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4054 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4056 /* A double-precision floating-point value. The most
4057 significant part goes in FP1, and the least significant in
4060 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
4061 switch (gdbarch_byte_order (gdbarch))
4063 case BFD_ENDIAN_LITTLE:
4064 mips_xfer_register (gdbarch, regcache,
4065 gdbarch_num_regs (gdbarch)
4066 + mips_regnum (gdbarch)->fp0 +
4067 0, 4, gdbarch_byte_order (gdbarch),
4068 readbuf, writebuf, 0);
4069 mips_xfer_register (gdbarch, regcache,
4070 gdbarch_num_regs (gdbarch)
4071 + mips_regnum (gdbarch)->fp0 + 1,
4072 4, gdbarch_byte_order (gdbarch),
4073 readbuf, writebuf, 4);
4075 case BFD_ENDIAN_BIG:
4076 mips_xfer_register (gdbarch, regcache,
4077 gdbarch_num_regs (gdbarch)
4078 + mips_regnum (gdbarch)->fp0 + 1,
4079 4, gdbarch_byte_order (gdbarch),
4080 readbuf, writebuf, 0);
4081 mips_xfer_register (gdbarch, regcache,
4082 gdbarch_num_regs (gdbarch)
4083 + mips_regnum (gdbarch)->fp0 + 0,
4084 4, gdbarch_byte_order (gdbarch),
4085 readbuf, writebuf, 4);
4088 internal_error (__FILE__, __LINE__, _("bad switch"));
4090 return RETURN_VALUE_REGISTER_CONVENTION;
4093 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4094 && TYPE_NFIELDS (type) <= 2
4095 && TYPE_NFIELDS (type) >= 1
4096 && ((TYPE_NFIELDS (type) == 1
4097 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4099 || (TYPE_NFIELDS (type) == 2
4100 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4102 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4104 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4106 /* A struct that contains one or two floats. Each value is part
4107 in the least significant part of their floating point
4109 gdb_byte reg[MAX_REGISTER_SIZE];
4112 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
4113 field < TYPE_NFIELDS (type); field++, regnum += 2)
4115 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4118 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
4120 mips_xfer_register (gdbarch, regcache,
4121 gdbarch_num_regs (gdbarch) + regnum,
4122 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4123 gdbarch_byte_order (gdbarch),
4124 readbuf, writebuf, offset);
4126 return RETURN_VALUE_REGISTER_CONVENTION;
4130 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4131 || TYPE_CODE (type) == TYPE_CODE_UNION)
4133 /* A structure or union. Extract the left justified value,
4134 regardless of the byte order. I.e. DO NOT USE
4138 for (offset = 0, regnum = MIPS_V0_REGNUM;
4139 offset < TYPE_LENGTH (type);
4140 offset += register_size (gdbarch, regnum), regnum++)
4142 int xfer = register_size (gdbarch, regnum);
4143 if (offset + xfer > TYPE_LENGTH (type))
4144 xfer = TYPE_LENGTH (type) - offset;
4146 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4147 offset, xfer, regnum);
4148 mips_xfer_register (gdbarch, regcache,
4149 gdbarch_num_regs (gdbarch) + regnum, xfer,
4150 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
4152 return RETURN_VALUE_REGISTER_CONVENTION;
4157 /* A scalar extract each part but least-significant-byte
4158 justified. o32 thinks registers are 4 byte, regardless of
4162 for (offset = 0, regnum = MIPS_V0_REGNUM;
4163 offset < TYPE_LENGTH (type);
4164 offset += MIPS32_REGSIZE, regnum++)
4166 int xfer = MIPS32_REGSIZE;
4167 if (offset + xfer > TYPE_LENGTH (type))
4168 xfer = TYPE_LENGTH (type) - offset;
4170 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4171 offset, xfer, regnum);
4172 mips_xfer_register (gdbarch, regcache,
4173 gdbarch_num_regs (gdbarch) + regnum, xfer,
4174 gdbarch_byte_order (gdbarch),
4175 readbuf, writebuf, offset);
4177 return RETURN_VALUE_REGISTER_CONVENTION;
4181 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4185 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4186 struct regcache *regcache, CORE_ADDR bp_addr,
4188 struct value **args, CORE_ADDR sp,
4189 int struct_return, CORE_ADDR struct_addr)
4195 int stack_offset = 0;
4196 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4197 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4198 CORE_ADDR func_addr = find_function_addr (function, NULL);
4200 /* For shared libraries, "t9" needs to point at the function
4202 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4204 /* Set the return address register to point to the entry point of
4205 the program, where a breakpoint lies in wait. */
4206 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4208 /* First ensure that the stack and structure return address (if any)
4209 are properly aligned. The stack has to be at least 64-bit
4210 aligned even on 32-bit machines, because doubles must be 64-bit
4211 aligned. For n32 and n64, stack frames need to be 128-bit
4212 aligned, so we round to this widest known alignment. */
4214 sp = align_down (sp, 16);
4215 struct_addr = align_down (struct_addr, 16);
4217 /* Now make space on the stack for the args. */
4218 for (argnum = 0; argnum < nargs; argnum++)
4220 struct type *arg_type = check_typedef (value_type (args[argnum]));
4221 int arglen = TYPE_LENGTH (arg_type);
4223 /* Allocate space on the stack. */
4224 len += align_up (arglen, MIPS64_REGSIZE);
4226 sp -= align_up (len, 16);
4229 fprintf_unfiltered (gdb_stdlog,
4230 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4231 paddress (gdbarch, sp), (long) align_up (len, 16));
4233 /* Initialize the integer and float register pointers. */
4234 argreg = MIPS_A0_REGNUM;
4235 float_argreg = mips_fpa0_regnum (gdbarch);
4237 /* The struct_return pointer occupies the first parameter-passing reg. */
4241 fprintf_unfiltered (gdb_stdlog,
4242 "mips_o64_push_dummy_call: "
4243 "struct_return reg=%d %s\n",
4244 argreg, paddress (gdbarch, struct_addr));
4245 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4246 stack_offset += MIPS64_REGSIZE;
4249 /* Now load as many as possible of the first arguments into
4250 registers, and push the rest onto the stack. Loop thru args
4251 from first to last. */
4252 for (argnum = 0; argnum < nargs; argnum++)
4254 const gdb_byte *val;
4255 gdb_byte valbuf[MAX_REGISTER_SIZE];
4256 struct value *arg = args[argnum];
4257 struct type *arg_type = check_typedef (value_type (arg));
4258 int len = TYPE_LENGTH (arg_type);
4259 enum type_code typecode = TYPE_CODE (arg_type);
4262 fprintf_unfiltered (gdb_stdlog,
4263 "mips_o64_push_dummy_call: %d len=%d type=%d",
4264 argnum + 1, len, (int) typecode);
4266 val = value_contents (arg);
4268 /* Function pointer arguments to mips16 code need to be made into
4270 if (typecode == TYPE_CODE_PTR
4271 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
4273 CORE_ADDR addr = extract_signed_integer (value_contents (arg),
4275 if (mips_pc_is_mips16 (addr))
4277 store_signed_integer (valbuf, len, byte_order,
4278 make_mips16_addr (addr));
4283 /* Floating point arguments passed in registers have to be
4284 treated specially. On 32-bit architectures, doubles
4285 are passed in register pairs; the even register gets
4286 the low word, and the odd register gets the high word.
4287 On O32/O64, the first two floating point arguments are
4288 also copied to general registers, because MIPS16 functions
4289 don't use float registers for arguments. This duplication of
4290 arguments in general registers can't hurt non-MIPS16 functions
4291 because those registers are normally skipped. */
4293 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4294 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4296 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
4298 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4299 float_argreg, phex (regval, len));
4300 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
4302 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4303 argreg, phex (regval, len));
4304 regcache_cooked_write_unsigned (regcache, argreg, regval);
4306 /* Reserve space for the FP register. */
4307 stack_offset += align_up (len, MIPS64_REGSIZE);
4311 /* Copy the argument to general registers or the stack in
4312 register-sized pieces. Large arguments are split between
4313 registers and stack. */
4314 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4315 are treated specially: Irix cc passes them in registers
4316 where gcc sometimes puts them on the stack. For maximum
4317 compatibility, we will put them in both places. */
4318 int odd_sized_struct = (len > MIPS64_REGSIZE
4319 && len % MIPS64_REGSIZE != 0);
4322 /* Remember if the argument was written to the stack. */
4323 int stack_used_p = 0;
4324 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4327 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4330 /* Write this portion of the argument to the stack. */
4331 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4332 || odd_sized_struct)
4334 /* Should shorter than int integer values be
4335 promoted to int before being stored? */
4336 int longword_offset = 0;
4339 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4341 if ((typecode == TYPE_CODE_INT
4342 || typecode == TYPE_CODE_PTR
4343 || typecode == TYPE_CODE_FLT)
4345 longword_offset = MIPS64_REGSIZE - len;
4350 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4351 paddress (gdbarch, stack_offset));
4352 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4353 paddress (gdbarch, longword_offset));
4356 addr = sp + stack_offset + longword_offset;
4361 fprintf_unfiltered (gdb_stdlog, " @%s ",
4362 paddress (gdbarch, addr));
4363 for (i = 0; i < partial_len; i++)
4365 fprintf_unfiltered (gdb_stdlog, "%02x",
4369 write_memory (addr, val, partial_len);
4372 /* Note!!! This is NOT an else clause. Odd sized
4373 structs may go thru BOTH paths. */
4374 /* Write this portion of the argument to a general
4375 purpose register. */
4376 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4378 LONGEST regval = extract_signed_integer (val, partial_len,
4380 /* Value may need to be sign extended, because
4381 mips_isa_regsize() != mips_abi_regsize(). */
4383 /* A non-floating-point argument being passed in a
4384 general register. If a struct or union, and if
4385 the remaining length is smaller than the register
4386 size, we have to adjust the register value on
4389 It does not seem to be necessary to do the
4390 same for integral types. */
4392 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
4393 && partial_len < MIPS64_REGSIZE
4394 && (typecode == TYPE_CODE_STRUCT
4395 || typecode == TYPE_CODE_UNION))
4396 regval <<= ((MIPS64_REGSIZE - partial_len)
4400 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4402 phex (regval, MIPS64_REGSIZE));
4403 regcache_cooked_write_unsigned (regcache, argreg, regval);
4406 /* Prevent subsequent floating point arguments from
4407 being passed in floating point registers. */
4408 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
4414 /* Compute the offset into the stack at which we will
4415 copy the next parameter.
4417 In older ABIs, the caller reserved space for
4418 registers that contained arguments. This was loosely
4419 refered to as their "home". Consequently, space is
4420 always allocated. */
4422 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
4426 fprintf_unfiltered (gdb_stdlog, "\n");
4429 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4431 /* Return adjusted stack pointer. */
4435 static enum return_value_convention
4436 mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type,
4437 struct type *type, struct regcache *regcache,
4438 gdb_byte *readbuf, const gdb_byte *writebuf)
4440 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4442 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4443 || TYPE_CODE (type) == TYPE_CODE_UNION
4444 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
4445 return RETURN_VALUE_STRUCT_CONVENTION;
4446 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
4448 /* A floating-point value. It fits in the least significant
4451 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4452 mips_xfer_register (gdbarch, regcache,
4453 gdbarch_num_regs (gdbarch)
4454 + mips_regnum (gdbarch)->fp0,
4456 gdbarch_byte_order (gdbarch),
4457 readbuf, writebuf, 0);
4458 return RETURN_VALUE_REGISTER_CONVENTION;
4462 /* A scalar extract each part but least-significant-byte
4466 for (offset = 0, regnum = MIPS_V0_REGNUM;
4467 offset < TYPE_LENGTH (type);
4468 offset += MIPS64_REGSIZE, regnum++)
4470 int xfer = MIPS64_REGSIZE;
4471 if (offset + xfer > TYPE_LENGTH (type))
4472 xfer = TYPE_LENGTH (type) - offset;
4474 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4475 offset, xfer, regnum);
4476 mips_xfer_register (gdbarch, regcache,
4477 gdbarch_num_regs (gdbarch) + regnum,
4478 xfer, gdbarch_byte_order (gdbarch),
4479 readbuf, writebuf, offset);
4481 return RETURN_VALUE_REGISTER_CONVENTION;
4485 /* Floating point register management.
4487 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4488 64bit operations, these early MIPS cpus treat fp register pairs
4489 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4490 registers and offer a compatibility mode that emulates the MIPS2 fp
4491 model. When operating in MIPS2 fp compat mode, later cpu's split
4492 double precision floats into two 32-bit chunks and store them in
4493 consecutive fp regs. To display 64-bit floats stored in this
4494 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4495 Throw in user-configurable endianness and you have a real mess.
4497 The way this works is:
4498 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4499 double-precision value will be split across two logical registers.
4500 The lower-numbered logical register will hold the low-order bits,
4501 regardless of the processor's endianness.
4502 - If we are on a 64-bit processor, and we are looking for a
4503 single-precision value, it will be in the low ordered bits
4504 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4505 save slot in memory.
4506 - If we are in 64-bit mode, everything is straightforward.
4508 Note that this code only deals with "live" registers at the top of the
4509 stack. We will attempt to deal with saved registers later, when
4510 the raw/cooked register interface is in place. (We need a general
4511 interface that can deal with dynamic saved register sizes -- fp
4512 regs could be 32 bits wide in one frame and 64 on the frame above
4515 /* Copy a 32-bit single-precision value from the current frame
4516 into rare_buffer. */
4519 mips_read_fp_register_single (struct frame_info *frame, int regno,
4520 gdb_byte *rare_buffer)
4522 struct gdbarch *gdbarch = get_frame_arch (frame);
4523 int raw_size = register_size (gdbarch, regno);
4524 gdb_byte *raw_buffer = alloca (raw_size);
4526 if (!frame_register_read (frame, regno, raw_buffer))
4527 error (_("can't read register %d (%s)"),
4528 regno, gdbarch_register_name (gdbarch, regno));
4531 /* We have a 64-bit value for this register. Find the low-order
4535 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4540 memcpy (rare_buffer, raw_buffer + offset, 4);
4544 memcpy (rare_buffer, raw_buffer, 4);
4548 /* Copy a 64-bit double-precision value from the current frame into
4549 rare_buffer. This may include getting half of it from the next
4553 mips_read_fp_register_double (struct frame_info *frame, int regno,
4554 gdb_byte *rare_buffer)
4556 struct gdbarch *gdbarch = get_frame_arch (frame);
4557 int raw_size = register_size (gdbarch, regno);
4559 if (raw_size == 8 && !mips2_fp_compat (frame))
4561 /* We have a 64-bit value for this register, and we should use
4563 if (!frame_register_read (frame, regno, rare_buffer))
4564 error (_("can't read register %d (%s)"),
4565 regno, gdbarch_register_name (gdbarch, regno));
4569 int rawnum = regno % gdbarch_num_regs (gdbarch);
4571 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
4572 internal_error (__FILE__, __LINE__,
4573 _("mips_read_fp_register_double: bad access to "
4574 "odd-numbered FP register"));
4576 /* mips_read_fp_register_single will find the correct 32 bits from
4578 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4580 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4581 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4585 mips_read_fp_register_single (frame, regno, rare_buffer);
4586 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4592 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4594 { /* Do values for FP (float) regs. */
4595 struct gdbarch *gdbarch = get_frame_arch (frame);
4596 gdb_byte *raw_buffer;
4597 double doub, flt1; /* Doubles extracted from raw hex data. */
4600 raw_buffer = alloca (2 * register_size (gdbarch,
4601 mips_regnum (gdbarch)->fp0));
4603 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
4604 fprintf_filtered (file, "%*s",
4605 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
4608 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
4610 struct value_print_options opts;
4612 /* 4-byte registers: Print hex and floating. Also print even
4613 numbered registers as doubles. */
4614 mips_read_fp_register_single (frame, regnum, raw_buffer);
4615 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
4618 get_formatted_print_options (&opts, 'x');
4619 print_scalar_formatted (raw_buffer,
4620 builtin_type (gdbarch)->builtin_uint32,
4623 fprintf_filtered (file, " flt: ");
4625 fprintf_filtered (file, " <invalid float> ");
4627 fprintf_filtered (file, "%-17.9g", flt1);
4629 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
4631 mips_read_fp_register_double (frame, regnum, raw_buffer);
4632 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
4635 fprintf_filtered (file, " dbl: ");
4637 fprintf_filtered (file, "<invalid double>");
4639 fprintf_filtered (file, "%-24.17g", doub);
4644 struct value_print_options opts;
4646 /* Eight byte registers: print each one as hex, float and double. */
4647 mips_read_fp_register_single (frame, regnum, raw_buffer);
4648 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
4651 mips_read_fp_register_double (frame, regnum, raw_buffer);
4652 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
4655 get_formatted_print_options (&opts, 'x');
4656 print_scalar_formatted (raw_buffer,
4657 builtin_type (gdbarch)->builtin_uint64,
4660 fprintf_filtered (file, " flt: ");
4662 fprintf_filtered (file, "<invalid float>");
4664 fprintf_filtered (file, "%-17.9g", flt1);
4666 fprintf_filtered (file, " dbl: ");
4668 fprintf_filtered (file, "<invalid double>");
4670 fprintf_filtered (file, "%-24.17g", doub);
4675 mips_print_register (struct ui_file *file, struct frame_info *frame,
4678 struct gdbarch *gdbarch = get_frame_arch (frame);
4680 struct value_print_options opts;
4683 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4685 mips_print_fp_register (file, frame, regnum);
4689 val = get_frame_register_value (frame, regnum);
4690 if (value_optimized_out (val))
4692 fprintf_filtered (file, "%s: [Invalid]",
4693 gdbarch_register_name (gdbarch, regnum));
4697 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
4699 /* The problem with printing numeric register names (r26, etc.) is that
4700 the user can't use them on input. Probably the best solution is to
4701 fix it so that either the numeric or the funky (a2, etc.) names
4702 are accepted on input. */
4703 if (regnum < MIPS_NUMREGS)
4704 fprintf_filtered (file, "(r%d): ", regnum);
4706 fprintf_filtered (file, ": ");
4708 get_formatted_print_options (&opts, 'x');
4709 val_print_scalar_formatted (value_type (val),
4710 value_contents_for_printing (val),
4711 value_embedded_offset (val),
4716 /* Replacement for generic do_registers_info.
4717 Print regs in pretty columns. */
4720 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4723 fprintf_filtered (file, " ");
4724 mips_print_fp_register (file, frame, regnum);
4725 fprintf_filtered (file, "\n");
4730 /* Print a row's worth of GP (int) registers, with name labels above. */
4733 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4736 struct gdbarch *gdbarch = get_frame_arch (frame);
4737 /* Do values for GP (int) regs. */
4738 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4739 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols
4744 /* For GP registers, we print a separate row of names above the vals. */
4745 for (col = 0, regnum = start_regnum;
4746 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4747 + gdbarch_num_pseudo_regs (gdbarch);
4750 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4751 continue; /* unused register */
4752 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4754 break; /* End the row: reached FP register. */
4755 /* Large registers are handled separately. */
4756 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4759 break; /* End the row before this register. */
4761 /* Print this register on a row by itself. */
4762 mips_print_register (file, frame, regnum);
4763 fprintf_filtered (file, "\n");
4767 fprintf_filtered (file, " ");
4768 fprintf_filtered (file,
4769 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
4770 gdbarch_register_name (gdbarch, regnum));
4777 /* Print the R0 to R31 names. */
4778 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
4779 fprintf_filtered (file, "\n R%-4d",
4780 start_regnum % gdbarch_num_regs (gdbarch));
4782 fprintf_filtered (file, "\n ");
4784 /* Now print the values in hex, 4 or 8 to the row. */
4785 for (col = 0, regnum = start_regnum;
4786 col < ncols && regnum < gdbarch_num_regs (gdbarch)
4787 + gdbarch_num_pseudo_regs (gdbarch);
4790 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4791 continue; /* unused register */
4792 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4794 break; /* End row: reached FP register. */
4795 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4796 break; /* End row: large register. */
4798 /* OK: get the data in raw format. */
4799 if (!frame_register_read (frame, regnum, raw_buffer))
4800 error (_("can't read register %d (%s)"),
4801 regnum, gdbarch_register_name (gdbarch, regnum));
4802 /* pad small registers */
4804 byte < (mips_abi_regsize (gdbarch)
4805 - register_size (gdbarch, regnum)); byte++)
4806 printf_filtered (" ");
4807 /* Now print the register value in hex, endian order. */
4808 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4810 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4811 byte < register_size (gdbarch, regnum); byte++)
4812 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4814 for (byte = register_size (gdbarch, regnum) - 1;
4816 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4817 fprintf_filtered (file, " ");
4820 if (col > 0) /* ie. if we actually printed anything... */
4821 fprintf_filtered (file, "\n");
4826 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4829 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4830 struct frame_info *frame, int regnum, int all)
4832 if (regnum != -1) /* Do one specified register. */
4834 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
4835 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
4836 error (_("Not a valid register for the current processor type"));
4838 mips_print_register (file, frame, regnum);
4839 fprintf_filtered (file, "\n");
4842 /* Do all (or most) registers. */
4844 regnum = gdbarch_num_regs (gdbarch);
4845 while (regnum < gdbarch_num_regs (gdbarch)
4846 + gdbarch_num_pseudo_regs (gdbarch))
4848 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4851 if (all) /* True for "INFO ALL-REGISTERS" command. */
4852 regnum = print_fp_register_row (file, frame, regnum);
4854 regnum += MIPS_NUMREGS; /* Skip floating point regs. */
4857 regnum = print_gp_register_row (file, frame, regnum);
4862 /* Is this a branch with a delay slot? */
4865 is_delayed (unsigned long insn)
4868 for (i = 0; i < NUMOPCODES; ++i)
4869 if (mips_opcodes[i].pinfo != INSN_MACRO
4870 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4872 return (i < NUMOPCODES
4873 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4874 | INSN_COND_BRANCH_DELAY
4875 | INSN_COND_BRANCH_LIKELY)));
4879 mips_single_step_through_delay (struct gdbarch *gdbarch,
4880 struct frame_info *frame)
4882 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4883 CORE_ADDR pc = get_frame_pc (frame);
4884 gdb_byte buf[MIPS_INSN32_SIZE];
4886 /* There is no branch delay slot on MIPS16. */
4887 if (mips_pc_is_mips16 (pc))
4890 if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4))
4893 if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf))
4894 /* If error reading memory, guess that it is not a delayed
4897 return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order));
4900 /* To skip prologues, I use this predicate. Returns either PC itself
4901 if the code at PC does not look like a function prologue; otherwise
4902 returns an address that (if we're lucky) follows the prologue. If
4903 LENIENT, then we must skip everything which is involved in setting
4904 up the frame (it's OK to skip more, just so long as we don't skip
4905 anything which might clobber the registers which are being saved.
4906 We must skip more in the case where part of the prologue is in the
4907 delay slot of a non-prologue instruction). */
4910 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
4913 CORE_ADDR func_addr;
4915 /* See if we can determine the end of the prologue via the symbol table.
4916 If so, then return either PC, or the PC after the prologue, whichever
4918 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
4920 CORE_ADDR post_prologue_pc
4921 = skip_prologue_using_sal (gdbarch, func_addr);
4922 if (post_prologue_pc != 0)
4923 return max (pc, post_prologue_pc);
4926 /* Can't determine prologue from the symbol table, need to examine
4929 /* Find an upper limit on the function prologue using the debug
4930 information. If the debug information could not be used to provide
4931 that bound, then use an arbitrary large number as the upper bound. */
4932 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4934 limit_pc = pc + 100; /* Magic. */
4936 if (mips_pc_is_mips16 (pc))
4937 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
4939 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
4942 /* Check whether the PC is in a function epilogue (32-bit version).
4943 This is a helper function for mips_in_function_epilogue_p. */
4945 mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4947 CORE_ADDR func_addr = 0, func_end = 0;
4949 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4951 /* The MIPS epilogue is max. 12 bytes long. */
4952 CORE_ADDR addr = func_end - 12;
4954 if (addr < func_addr + 4)
4955 addr = func_addr + 4;
4959 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
4961 unsigned long high_word;
4964 inst = mips_fetch_instruction (gdbarch, pc);
4965 high_word = (inst >> 16) & 0xffff;
4967 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
4968 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
4969 && inst != 0x03e00008 /* jr $ra */
4970 && inst != 0x00000000) /* nop */
4980 /* Check whether the PC is in a function epilogue (16-bit version).
4981 This is a helper function for mips_in_function_epilogue_p. */
4983 mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4985 CORE_ADDR func_addr = 0, func_end = 0;
4987 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4989 /* The MIPS epilogue is max. 12 bytes long. */
4990 CORE_ADDR addr = func_end - 12;
4992 if (addr < func_addr + 4)
4993 addr = func_addr + 4;
4997 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
4999 unsigned short inst;
5001 inst = mips_fetch_instruction (gdbarch, pc);
5003 if ((inst & 0xf800) == 0xf000) /* extend */
5006 if (inst != 0x6300 /* addiu $sp,offset */
5007 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
5008 && inst != 0xe820 /* jr $ra */
5009 && inst != 0xe8a0 /* jrc $ra */
5010 && inst != 0x6500) /* nop */
5020 /* The epilogue is defined here as the area at the end of a function,
5021 after an instruction which destroys the function's stack frame. */
5023 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
5025 if (mips_pc_is_mips16 (pc))
5026 return mips16_in_function_epilogue_p (gdbarch, pc);
5028 return mips32_in_function_epilogue_p (gdbarch, pc);
5031 /* Root of all "set mips "/"show mips " commands. This will eventually be
5032 used for all MIPS-specific commands. */
5035 show_mips_command (char *args, int from_tty)
5037 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
5041 set_mips_command (char *args, int from_tty)
5044 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5045 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
5048 /* Commands to show/set the MIPS FPU type. */
5051 show_mipsfpu_command (char *args, int from_tty)
5055 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
5058 ("The MIPS floating-point coprocessor is unknown "
5059 "because the current architecture is not MIPS.\n");
5063 switch (MIPS_FPU_TYPE (target_gdbarch))
5065 case MIPS_FPU_SINGLE:
5066 fpu = "single-precision";
5068 case MIPS_FPU_DOUBLE:
5069 fpu = "double-precision";
5072 fpu = "absent (none)";
5075 internal_error (__FILE__, __LINE__, _("bad switch"));
5077 if (mips_fpu_type_auto)
5078 printf_unfiltered ("The MIPS floating-point coprocessor "
5079 "is set automatically (currently %s)\n",
5083 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
5088 set_mipsfpu_command (char *args, int from_tty)
5090 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5091 "\"single\",\"none\" or \"auto\".\n");
5092 show_mipsfpu_command (args, from_tty);
5096 set_mipsfpu_single_command (char *args, int from_tty)
5098 struct gdbarch_info info;
5099 gdbarch_info_init (&info);
5100 mips_fpu_type = MIPS_FPU_SINGLE;
5101 mips_fpu_type_auto = 0;
5102 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5103 instead of relying on globals. Doing that would let generic code
5104 handle the search for this specific architecture. */
5105 if (!gdbarch_update_p (info))
5106 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
5110 set_mipsfpu_double_command (char *args, int from_tty)
5112 struct gdbarch_info info;
5113 gdbarch_info_init (&info);
5114 mips_fpu_type = MIPS_FPU_DOUBLE;
5115 mips_fpu_type_auto = 0;
5116 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5117 instead of relying on globals. Doing that would let generic code
5118 handle the search for this specific architecture. */
5119 if (!gdbarch_update_p (info))
5120 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
5124 set_mipsfpu_none_command (char *args, int from_tty)
5126 struct gdbarch_info info;
5127 gdbarch_info_init (&info);
5128 mips_fpu_type = MIPS_FPU_NONE;
5129 mips_fpu_type_auto = 0;
5130 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5131 instead of relying on globals. Doing that would let generic code
5132 handle the search for this specific architecture. */
5133 if (!gdbarch_update_p (info))
5134 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
5138 set_mipsfpu_auto_command (char *args, int from_tty)
5140 mips_fpu_type_auto = 1;
5143 /* Attempt to identify the particular processor model by reading the
5144 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5145 the relevant processor still exists (it dates back to '94) and
5146 secondly this is not the way to do this. The processor type should
5147 be set by forcing an architecture change. */
5150 deprecated_mips_set_processor_regs_hack (void)
5152 struct regcache *regcache = get_current_regcache ();
5153 struct gdbarch *gdbarch = get_regcache_arch (regcache);
5154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5157 regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid);
5158 if ((prid & ~0xf) == 0x700)
5159 tdep->mips_processor_reg_names = mips_r3041_reg_names;
5162 /* Just like reinit_frame_cache, but with the right arguments to be
5163 callable as an sfunc. */
5166 reinit_frame_cache_sfunc (char *args, int from_tty,
5167 struct cmd_list_element *c)
5169 reinit_frame_cache ();
5173 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
5175 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5176 disassembler needs to be able to locally determine the ISA, and
5177 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5179 if (mips_pc_is_mips16 (memaddr))
5180 info->mach = bfd_mach_mips16;
5182 /* Round down the instruction address to the appropriate boundary. */
5183 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
5185 /* Set the disassembler options. */
5186 if (!info->disassembler_options)
5187 /* This string is not recognized explicitly by the disassembler,
5188 but it tells the disassembler to not try to guess the ABI from
5189 the bfd elf headers, such that, if the user overrides the ABI
5190 of a program linked as NewABI, the disassembly will follow the
5191 register naming conventions specified by the user. */
5192 info->disassembler_options = "gpr-names=32";
5194 /* Call the appropriate disassembler based on the target endian-ness. */
5195 if (info->endian == BFD_ENDIAN_BIG)
5196 return print_insn_big_mips (memaddr, info);
5198 return print_insn_little_mips (memaddr, info);
5202 gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
5204 /* Set up the disassembler info, so that we get the right
5205 register names from libopcodes. */
5206 info->disassembler_options = "gpr-names=n32";
5207 info->flavour = bfd_target_elf_flavour;
5209 return gdb_print_insn_mips (memaddr, info);
5213 gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
5215 /* Set up the disassembler info, so that we get the right
5216 register names from libopcodes. */
5217 info->disassembler_options = "gpr-names=64";
5218 info->flavour = bfd_target_elf_flavour;
5220 return gdb_print_insn_mips (memaddr, info);
5223 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5224 program counter value to determine whether a 16- or 32-bit breakpoint
5225 should be used. It returns a pointer to a string of bytes that encode a
5226 breakpoint instruction, stores the length of the string to *lenptr, and
5227 adjusts pc (if necessary) to point to the actual memory location where
5228 the breakpoint should be inserted. */
5230 static const gdb_byte *
5231 mips_breakpoint_from_pc (struct gdbarch *gdbarch,
5232 CORE_ADDR *pcptr, int *lenptr)
5234 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5236 if (mips_pc_is_mips16 (*pcptr))
5238 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
5239 *pcptr = unmake_mips16_addr (*pcptr);
5240 *lenptr = sizeof (mips16_big_breakpoint);
5241 return mips16_big_breakpoint;
5245 /* The IDT board uses an unusual breakpoint value, and
5246 sometimes gets confused when it sees the usual MIPS
5247 breakpoint instruction. */
5248 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
5249 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
5250 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
5251 /* Likewise, IRIX appears to expect a different breakpoint,
5252 although this is not apparent until you try to use pthreads. */
5253 static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd };
5255 *lenptr = sizeof (big_breakpoint);
5257 if (strcmp (target_shortname, "mips") == 0)
5258 return idt_big_breakpoint;
5259 else if (strcmp (target_shortname, "ddb") == 0
5260 || strcmp (target_shortname, "pmon") == 0
5261 || strcmp (target_shortname, "lsi") == 0)
5262 return pmon_big_breakpoint;
5263 else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX)
5264 return irix_big_breakpoint;
5266 return big_breakpoint;
5271 if (mips_pc_is_mips16 (*pcptr))
5273 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
5274 *pcptr = unmake_mips16_addr (*pcptr);
5275 *lenptr = sizeof (mips16_little_breakpoint);
5276 return mips16_little_breakpoint;
5280 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
5281 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
5282 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
5284 *lenptr = sizeof (little_breakpoint);
5286 if (strcmp (target_shortname, "mips") == 0)
5287 return idt_little_breakpoint;
5288 else if (strcmp (target_shortname, "ddb") == 0
5289 || strcmp (target_shortname, "pmon") == 0
5290 || strcmp (target_shortname, "lsi") == 0)
5291 return pmon_little_breakpoint;
5293 return little_breakpoint;
5298 /* If PC is in a mips16 call or return stub, return the address of the target
5299 PC, which is either the callee or the caller. There are several
5300 cases which must be handled:
5302 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5303 target PC is in $31 ($ra).
5304 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5305 and the target PC is in $2.
5306 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5307 before the jal instruction, this is effectively a call stub
5308 and the target PC is in $2. Otherwise this is effectively
5309 a return stub and the target PC is in $18.
5311 See the source code for the stubs in gcc/config/mips/mips16.S for
5315 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5317 struct gdbarch *gdbarch = get_frame_arch (frame);
5319 CORE_ADDR start_addr;
5321 /* Find the starting address and name of the function containing the PC. */
5322 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5325 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5326 target PC is in $31 ($ra). */
5327 if (strcmp (name, "__mips16_ret_sf") == 0
5328 || strcmp (name, "__mips16_ret_df") == 0)
5329 return get_frame_register_signed (frame, MIPS_RA_REGNUM);
5331 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5333 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5334 and the target PC is in $2. */
5335 if (name[19] >= '0' && name[19] <= '9')
5336 return get_frame_register_signed (frame, 2);
5338 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5339 before the jal instruction, this is effectively a call stub
5340 and the target PC is in $2. Otherwise this is effectively
5341 a return stub and the target PC is in $18. */
5342 else if (name[19] == 's' || name[19] == 'd')
5344 if (pc == start_addr)
5346 /* Check if the target of the stub is a compiler-generated
5347 stub. Such a stub for a function bar might have a name
5348 like __fn_stub_bar, and might look like this:
5353 la $1,bar (becomes a lui/addiu pair)
5355 So scan down to the lui/addi and extract the target
5356 address from those two instructions. */
5358 CORE_ADDR target_pc = get_frame_register_signed (frame, 2);
5361 /* See if the name of the target function is __fn_stub_*. */
5362 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
5365 if (strncmp (name, "__fn_stub_", 10) != 0
5366 && strcmp (name, "etext") != 0
5367 && strcmp (name, "_etext") != 0)
5370 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5371 The limit on the search is arbitrarily set to 20
5372 instructions. FIXME. */
5373 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE)
5375 ULONGEST inst = mips_fetch_instruction (gdbarch, target_pc);
5376 CORE_ADDR addr = inst;
5378 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5379 pc = (((addr & 0xffff) ^ 0x8000) - 0x8000) << 16;
5381 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5382 return pc + ((addr & 0xffff) ^ 0x8000) - 0x8000;
5386 /* Couldn't find the lui/addui pair, so return stub address. */
5390 /* This is the 'return' part of a call stub. The return
5391 address is in $r18. */
5392 return get_frame_register_signed (frame, 18);
5395 return 0; /* not a stub */
5398 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5399 PC of the stub target. The stub just loads $t9 and jumps to it,
5400 so that $t9 has the correct value at function entry. */
5403 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5405 struct gdbarch *gdbarch = get_frame_arch (frame);
5406 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5407 struct minimal_symbol *msym;
5409 gdb_byte stub_code[16];
5410 int32_t stub_words[4];
5412 /* The stub for foo is named ".pic.foo", and is either two
5413 instructions inserted before foo or a three instruction sequence
5414 which jumps to foo. */
5415 msym = lookup_minimal_symbol_by_pc (pc);
5417 || SYMBOL_VALUE_ADDRESS (msym) != pc
5418 || SYMBOL_LINKAGE_NAME (msym) == NULL
5419 || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0)
5422 /* A two-instruction header. */
5423 if (MSYMBOL_SIZE (msym) == 8)
5426 /* A three-instruction (plus delay slot) trampoline. */
5427 if (MSYMBOL_SIZE (msym) == 16)
5429 if (target_read_memory (pc, stub_code, 16) != 0)
5431 for (i = 0; i < 4; i++)
5432 stub_words[i] = extract_unsigned_integer (stub_code + i * 4,
5435 /* A stub contains these instructions:
5438 addiu t9, t9, %lo(target)
5441 This works even for N64, since stubs are only generated with
5443 if ((stub_words[0] & 0xffff0000U) == 0x3c190000
5444 && (stub_words[1] & 0xfc000000U) == 0x08000000
5445 && (stub_words[2] & 0xffff0000U) == 0x27390000
5446 && stub_words[3] == 0x00000000)
5447 return (((stub_words[0] & 0x0000ffff) << 16)
5448 + (stub_words[2] & 0x0000ffff));
5451 /* Not a recognized stub. */
5456 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5458 CORE_ADDR target_pc;
5460 target_pc = mips_skip_mips16_trampoline_code (frame, pc);
5464 target_pc = find_solib_trampoline_target (frame, pc);
5468 target_pc = mips_skip_pic_trampoline_code (frame, pc);
5475 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5476 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5479 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
5482 if (num >= 0 && num < 32)
5484 else if (num >= 38 && num < 70)
5485 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
5487 regnum = mips_regnum (gdbarch)->hi;
5489 regnum = mips_regnum (gdbarch)->lo;
5491 /* This will hopefully (eventually) provoke a warning. Should
5492 we be calling complaint() here? */
5493 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5494 return gdbarch_num_regs (gdbarch) + regnum;
5498 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5499 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5502 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
5505 if (num >= 0 && num < 32)
5507 else if (num >= 32 && num < 64)
5508 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
5510 regnum = mips_regnum (gdbarch)->hi;
5512 regnum = mips_regnum (gdbarch)->lo;
5514 /* This will hopefully (eventually) provoke a warning. Should we
5515 be calling complaint() here? */
5516 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5517 return gdbarch_num_regs (gdbarch) + regnum;
5521 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
5523 /* Only makes sense to supply raw registers. */
5524 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
5525 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5526 decide if it is valid. Should instead define a standard sim/gdb
5527 register numbering scheme. */
5528 if (gdbarch_register_name (gdbarch,
5529 gdbarch_num_regs (gdbarch) + regnum) != NULL
5530 && gdbarch_register_name (gdbarch,
5531 gdbarch_num_regs (gdbarch)
5532 + regnum)[0] != '\0')
5535 return LEGACY_SIM_REGNO_IGNORE;
5539 /* Convert an integer into an address. Extracting the value signed
5540 guarantees a correctly sign extended address. */
5543 mips_integer_to_address (struct gdbarch *gdbarch,
5544 struct type *type, const gdb_byte *buf)
5546 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5547 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
5550 /* Dummy virtual frame pointer method. This is no more or less accurate
5551 than most other architectures; we just need to be explicit about it,
5552 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5553 an assertion failure. */
5556 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
5557 CORE_ADDR pc, int *reg, LONGEST *offset)
5559 *reg = MIPS_SP_REGNUM;
5564 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5566 enum mips_abi *abip = (enum mips_abi *) obj;
5567 const char *name = bfd_get_section_name (abfd, sect);
5569 if (*abip != MIPS_ABI_UNKNOWN)
5572 if (strncmp (name, ".mdebug.", 8) != 0)
5575 if (strcmp (name, ".mdebug.abi32") == 0)
5576 *abip = MIPS_ABI_O32;
5577 else if (strcmp (name, ".mdebug.abiN32") == 0)
5578 *abip = MIPS_ABI_N32;
5579 else if (strcmp (name, ".mdebug.abi64") == 0)
5580 *abip = MIPS_ABI_N64;
5581 else if (strcmp (name, ".mdebug.abiO64") == 0)
5582 *abip = MIPS_ABI_O64;
5583 else if (strcmp (name, ".mdebug.eabi32") == 0)
5584 *abip = MIPS_ABI_EABI32;
5585 else if (strcmp (name, ".mdebug.eabi64") == 0)
5586 *abip = MIPS_ABI_EABI64;
5588 warning (_("unsupported ABI %s."), name + 8);
5592 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
5594 int *lbp = (int *) obj;
5595 const char *name = bfd_get_section_name (abfd, sect);
5597 if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
5599 else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
5601 else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
5602 warning (_("unrecognized .gcc_compiled_longXX"));
5605 static enum mips_abi
5606 global_mips_abi (void)
5610 for (i = 0; mips_abi_strings[i] != NULL; i++)
5611 if (mips_abi_strings[i] == mips_abi_string)
5612 return (enum mips_abi) i;
5614 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
5618 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
5620 /* If the size matches the set of 32-bit or 64-bit integer registers,
5621 assume that's what we've got. */
5622 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
5623 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
5625 /* If the size matches the full set of registers GDB traditionally
5626 knows about, including floating point, for either 32-bit or
5627 64-bit, assume that's what we've got. */
5628 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
5629 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
5631 /* Otherwise we don't have a useful guess. */
5634 static struct value *
5635 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
5637 const int *reg_p = baton;
5638 return value_of_register (*reg_p, frame);
5641 static struct gdbarch *
5642 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5644 struct gdbarch *gdbarch;
5645 struct gdbarch_tdep *tdep;
5647 enum mips_abi mips_abi, found_abi, wanted_abi;
5649 enum mips_fpu_type fpu_type;
5650 struct tdesc_arch_data *tdesc_data = NULL;
5651 int elf_fpu_type = 0;
5653 /* Check any target description for validity. */
5654 if (tdesc_has_registers (info.target_desc))
5656 static const char *const mips_gprs[] = {
5657 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5658 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5659 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5660 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5662 static const char *const mips_fprs[] = {
5663 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5664 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5665 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5666 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5669 const struct tdesc_feature *feature;
5672 feature = tdesc_find_feature (info.target_desc,
5673 "org.gnu.gdb.mips.cpu");
5674 if (feature == NULL)
5677 tdesc_data = tdesc_data_alloc ();
5680 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
5681 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
5685 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5686 MIPS_EMBED_LO_REGNUM, "lo");
5687 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5688 MIPS_EMBED_HI_REGNUM, "hi");
5689 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5690 MIPS_EMBED_PC_REGNUM, "pc");
5694 tdesc_data_cleanup (tdesc_data);
5698 feature = tdesc_find_feature (info.target_desc,
5699 "org.gnu.gdb.mips.cp0");
5700 if (feature == NULL)
5702 tdesc_data_cleanup (tdesc_data);
5707 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5708 MIPS_EMBED_BADVADDR_REGNUM,
5710 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5711 MIPS_PS_REGNUM, "status");
5712 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5713 MIPS_EMBED_CAUSE_REGNUM, "cause");
5717 tdesc_data_cleanup (tdesc_data);
5721 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5722 backend is not prepared for that, though. */
5723 feature = tdesc_find_feature (info.target_desc,
5724 "org.gnu.gdb.mips.fpu");
5725 if (feature == NULL)
5727 tdesc_data_cleanup (tdesc_data);
5732 for (i = 0; i < 32; i++)
5733 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5734 i + MIPS_EMBED_FP0_REGNUM,
5737 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5738 MIPS_EMBED_FP0_REGNUM + 32, "fcsr");
5739 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5740 MIPS_EMBED_FP0_REGNUM + 33, "fir");
5744 tdesc_data_cleanup (tdesc_data);
5748 /* It would be nice to detect an attempt to use a 64-bit ABI
5749 when only 32-bit registers are provided. */
5752 /* First of all, extract the elf_flags, if available. */
5753 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5754 elf_flags = elf_elfheader (info.abfd)->e_flags;
5755 else if (arches != NULL)
5756 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5760 fprintf_unfiltered (gdb_stdlog,
5761 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5763 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5764 switch ((elf_flags & EF_MIPS_ABI))
5766 case E_MIPS_ABI_O32:
5767 found_abi = MIPS_ABI_O32;
5769 case E_MIPS_ABI_O64:
5770 found_abi = MIPS_ABI_O64;
5772 case E_MIPS_ABI_EABI32:
5773 found_abi = MIPS_ABI_EABI32;
5775 case E_MIPS_ABI_EABI64:
5776 found_abi = MIPS_ABI_EABI64;
5779 if ((elf_flags & EF_MIPS_ABI2))
5780 found_abi = MIPS_ABI_N32;
5782 found_abi = MIPS_ABI_UNKNOWN;
5786 /* GCC creates a pseudo-section whose name describes the ABI. */
5787 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5788 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5790 /* If we have no useful BFD information, use the ABI from the last
5791 MIPS architecture (if there is one). */
5792 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5793 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5795 /* Try the architecture for any hint of the correct ABI. */
5796 if (found_abi == MIPS_ABI_UNKNOWN
5797 && info.bfd_arch_info != NULL
5798 && info.bfd_arch_info->arch == bfd_arch_mips)
5800 switch (info.bfd_arch_info->mach)
5802 case bfd_mach_mips3900:
5803 found_abi = MIPS_ABI_EABI32;
5805 case bfd_mach_mips4100:
5806 case bfd_mach_mips5000:
5807 found_abi = MIPS_ABI_EABI64;
5809 case bfd_mach_mips8000:
5810 case bfd_mach_mips10000:
5811 /* On Irix, ELF64 executables use the N64 ABI. The
5812 pseudo-sections which describe the ABI aren't present
5813 on IRIX. (Even for executables created by gcc.) */
5814 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5815 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5816 found_abi = MIPS_ABI_N64;
5818 found_abi = MIPS_ABI_N32;
5823 /* Default 64-bit objects to N64 instead of O32. */
5824 if (found_abi == MIPS_ABI_UNKNOWN
5825 && info.abfd != NULL
5826 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5827 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5828 found_abi = MIPS_ABI_N64;
5831 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5834 /* What has the user specified from the command line? */
5835 wanted_abi = global_mips_abi ();
5837 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5840 /* Now that we have found what the ABI for this binary would be,
5841 check whether the user is overriding it. */
5842 if (wanted_abi != MIPS_ABI_UNKNOWN)
5843 mips_abi = wanted_abi;
5844 else if (found_abi != MIPS_ABI_UNKNOWN)
5845 mips_abi = found_abi;
5847 mips_abi = MIPS_ABI_O32;
5849 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5852 /* Also used when doing an architecture lookup. */
5854 fprintf_unfiltered (gdb_stdlog,
5855 "mips_gdbarch_init: "
5856 "mips64_transfers_32bit_regs_p = %d\n",
5857 mips64_transfers_32bit_regs_p);
5859 /* Determine the MIPS FPU type. */
5862 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5863 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5864 Tag_GNU_MIPS_ABI_FP);
5865 #endif /* HAVE_ELF */
5867 if (!mips_fpu_type_auto)
5868 fpu_type = mips_fpu_type;
5869 else if (elf_fpu_type != 0)
5871 switch (elf_fpu_type)
5874 fpu_type = MIPS_FPU_DOUBLE;
5877 fpu_type = MIPS_FPU_SINGLE;
5881 /* Soft float or unknown. */
5882 fpu_type = MIPS_FPU_NONE;
5886 else if (info.bfd_arch_info != NULL
5887 && info.bfd_arch_info->arch == bfd_arch_mips)
5888 switch (info.bfd_arch_info->mach)
5890 case bfd_mach_mips3900:
5891 case bfd_mach_mips4100:
5892 case bfd_mach_mips4111:
5893 case bfd_mach_mips4120:
5894 fpu_type = MIPS_FPU_NONE;
5896 case bfd_mach_mips4650:
5897 fpu_type = MIPS_FPU_SINGLE;
5900 fpu_type = MIPS_FPU_DOUBLE;
5903 else if (arches != NULL)
5904 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5906 fpu_type = MIPS_FPU_DOUBLE;
5908 fprintf_unfiltered (gdb_stdlog,
5909 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5911 /* Check for blatant incompatibilities. */
5913 /* If we have only 32-bit registers, then we can't debug a 64-bit
5915 if (info.target_desc
5916 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
5917 && mips_abi != MIPS_ABI_EABI32
5918 && mips_abi != MIPS_ABI_O32)
5920 if (tdesc_data != NULL)
5921 tdesc_data_cleanup (tdesc_data);
5925 /* Try to find a pre-existing architecture. */
5926 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5928 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5930 /* MIPS needs to be pedantic about which ABI the object is
5932 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5934 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5936 /* Need to be pedantic about which register virtual size is
5938 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5939 != mips64_transfers_32bit_regs_p)
5941 /* Be pedantic about which FPU is selected. */
5942 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5945 if (tdesc_data != NULL)
5946 tdesc_data_cleanup (tdesc_data);
5947 return arches->gdbarch;
5950 /* Need a new architecture. Fill in a target specific vector. */
5951 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5952 gdbarch = gdbarch_alloc (&info, tdep);
5953 tdep->elf_flags = elf_flags;
5954 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5955 tdep->found_abi = found_abi;
5956 tdep->mips_abi = mips_abi;
5957 tdep->mips_fpu_type = fpu_type;
5958 tdep->register_size_valid_p = 0;
5959 tdep->register_size = 0;
5960 tdep->gregset = NULL;
5961 tdep->gregset64 = NULL;
5962 tdep->fpregset = NULL;
5963 tdep->fpregset64 = NULL;
5965 if (info.target_desc)
5967 /* Some useful properties can be inferred from the target. */
5968 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
5970 tdep->register_size_valid_p = 1;
5971 tdep->register_size = 4;
5973 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
5975 tdep->register_size_valid_p = 1;
5976 tdep->register_size = 8;
5980 /* Initially set everything according to the default ABI/ISA. */
5981 set_gdbarch_short_bit (gdbarch, 16);
5982 set_gdbarch_int_bit (gdbarch, 32);
5983 set_gdbarch_float_bit (gdbarch, 32);
5984 set_gdbarch_double_bit (gdbarch, 64);
5985 set_gdbarch_long_double_bit (gdbarch, 64);
5986 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5987 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5988 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5990 set_gdbarch_ax_pseudo_register_collect (gdbarch,
5991 mips_ax_pseudo_register_collect);
5992 set_gdbarch_ax_pseudo_register_push_stack
5993 (gdbarch, mips_ax_pseudo_register_push_stack);
5995 set_gdbarch_elf_make_msymbol_special (gdbarch,
5996 mips_elf_make_msymbol_special);
5998 /* Fill in the OS dependant register numbers and names. */
6000 const char **reg_names;
6001 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
6002 struct mips_regnum);
6003 if (tdesc_has_registers (info.target_desc))
6005 regnum->lo = MIPS_EMBED_LO_REGNUM;
6006 regnum->hi = MIPS_EMBED_HI_REGNUM;
6007 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
6008 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
6009 regnum->pc = MIPS_EMBED_PC_REGNUM;
6010 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
6011 regnum->fp_control_status = 70;
6012 regnum->fp_implementation_revision = 71;
6013 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
6016 else if (info.osabi == GDB_OSABI_IRIX)
6021 regnum->badvaddr = 66;
6024 regnum->fp_control_status = 69;
6025 regnum->fp_implementation_revision = 70;
6027 reg_names = mips_irix_reg_names;
6031 regnum->lo = MIPS_EMBED_LO_REGNUM;
6032 regnum->hi = MIPS_EMBED_HI_REGNUM;
6033 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
6034 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
6035 regnum->pc = MIPS_EMBED_PC_REGNUM;
6036 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
6037 regnum->fp_control_status = 70;
6038 regnum->fp_implementation_revision = 71;
6040 if (info.bfd_arch_info != NULL
6041 && info.bfd_arch_info->mach == bfd_mach_mips3900)
6042 reg_names = mips_tx39_reg_names;
6044 reg_names = mips_generic_reg_names;
6046 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6047 replaced by gdbarch_read_pc? */
6048 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
6049 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
6050 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
6051 set_gdbarch_num_regs (gdbarch, num_regs);
6052 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
6053 set_gdbarch_register_name (gdbarch, mips_register_name);
6054 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
6055 tdep->mips_processor_reg_names = reg_names;
6056 tdep->regnum = regnum;
6062 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
6063 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
6064 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
6065 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
6066 tdep->default_mask_address_p = 0;
6067 set_gdbarch_long_bit (gdbarch, 32);
6068 set_gdbarch_ptr_bit (gdbarch, 32);
6069 set_gdbarch_long_long_bit (gdbarch, 64);
6072 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
6073 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
6074 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
6075 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
6076 tdep->default_mask_address_p = 0;
6077 set_gdbarch_long_bit (gdbarch, 32);
6078 set_gdbarch_ptr_bit (gdbarch, 32);
6079 set_gdbarch_long_long_bit (gdbarch, 64);
6081 case MIPS_ABI_EABI32:
6082 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
6083 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
6084 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
6085 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
6086 tdep->default_mask_address_p = 0;
6087 set_gdbarch_long_bit (gdbarch, 32);
6088 set_gdbarch_ptr_bit (gdbarch, 32);
6089 set_gdbarch_long_long_bit (gdbarch, 64);
6091 case MIPS_ABI_EABI64:
6092 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
6093 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
6094 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
6095 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
6096 tdep->default_mask_address_p = 0;
6097 set_gdbarch_long_bit (gdbarch, 64);
6098 set_gdbarch_ptr_bit (gdbarch, 64);
6099 set_gdbarch_long_long_bit (gdbarch, 64);
6102 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
6103 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
6104 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
6105 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
6106 tdep->default_mask_address_p = 0;
6107 set_gdbarch_long_bit (gdbarch, 32);
6108 set_gdbarch_ptr_bit (gdbarch, 32);
6109 set_gdbarch_long_long_bit (gdbarch, 64);
6110 set_gdbarch_long_double_bit (gdbarch, 128);
6111 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
6114 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
6115 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
6116 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
6117 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
6118 tdep->default_mask_address_p = 0;
6119 set_gdbarch_long_bit (gdbarch, 64);
6120 set_gdbarch_ptr_bit (gdbarch, 64);
6121 set_gdbarch_long_long_bit (gdbarch, 64);
6122 set_gdbarch_long_double_bit (gdbarch, 128);
6123 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
6126 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
6129 /* GCC creates a pseudo-section whose name specifies the size of
6130 longs, since -mlong32 or -mlong64 may be used independent of
6131 other options. How those options affect pointer sizes is ABI and
6132 architecture dependent, so use them to override the default sizes
6133 set by the ABI. This table shows the relationship between ABI,
6134 -mlongXX, and size of pointers:
6136 ABI -mlongXX ptr bits
6137 --- -------- --------
6151 Note that for o32 and eabi32, pointers are always 32 bits
6152 regardless of any -mlongXX option. For all others, pointers and
6153 longs are the same, as set by -mlongXX or set by defaults. */
6155 if (info.abfd != NULL)
6159 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
6162 set_gdbarch_long_bit (gdbarch, long_bit);
6166 case MIPS_ABI_EABI32:
6171 case MIPS_ABI_EABI64:
6172 set_gdbarch_ptr_bit (gdbarch, long_bit);
6175 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
6180 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6181 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6184 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6185 flag in object files because to do so would make it impossible to
6186 link with libraries compiled without "-gp32". This is
6187 unnecessarily restrictive.
6189 We could solve this problem by adding "-gp32" multilibs to gcc,
6190 but to set this flag before gcc is built with such multilibs will
6191 break too many systems.''
6193 But even more unhelpfully, the default linker output target for
6194 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6195 for 64-bit programs - you need to change the ABI to change this,
6196 and not all gcc targets support that currently. Therefore using
6197 this flag to detect 32-bit mode would do the wrong thing given
6198 the current gcc - it would make GDB treat these 64-bit programs
6199 as 32-bit programs by default. */
6201 set_gdbarch_read_pc (gdbarch, mips_read_pc);
6202 set_gdbarch_write_pc (gdbarch, mips_write_pc);
6204 /* Add/remove bits from an address. The MIPS needs be careful to
6205 ensure that all 32 bit addresses are sign extended to 64 bits. */
6206 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
6208 /* Unwind the frame. */
6209 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
6210 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
6211 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
6213 /* Map debug register numbers onto internal register numbers. */
6214 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
6215 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
6216 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
6217 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
6218 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
6219 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
6221 /* MIPS version of CALL_DUMMY. */
6223 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6224 replaced by a command, and all targets will default to on stack
6225 (regardless of the stack's execute status). */
6226 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
6227 set_gdbarch_frame_align (gdbarch, mips_frame_align);
6229 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
6230 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
6231 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
6233 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6234 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
6236 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
6238 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
6240 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
6241 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
6242 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
6244 set_gdbarch_register_type (gdbarch, mips_register_type);
6246 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
6248 if (mips_abi == MIPS_ABI_N32)
6249 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
6250 else if (mips_abi == MIPS_ABI_N64)
6251 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
6253 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
6255 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6256 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6257 need to all be folded into the target vector. Since they are
6258 being used as guards for target_stopped_by_watchpoint, why not have
6259 target_stopped_by_watchpoint return the type of watchpoint that the code
6261 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
6263 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
6265 set_gdbarch_single_step_through_delay (gdbarch,
6266 mips_single_step_through_delay);
6268 /* Virtual tables. */
6269 set_gdbarch_vbit_in_delta (gdbarch, 1);
6271 mips_register_g_packet_guesses (gdbarch);
6273 /* Hook in OS ABI-specific overrides, if they have been registered. */
6274 info.tdep_info = (void *) tdesc_data;
6275 gdbarch_init_osabi (info, gdbarch);
6277 /* Unwind the frame. */
6278 dwarf2_append_unwinders (gdbarch);
6279 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
6280 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
6281 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
6282 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
6283 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
6284 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
6285 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
6289 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
6290 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
6292 /* Override the normal target description methods to handle our
6293 dual real and pseudo registers. */
6294 set_gdbarch_register_name (gdbarch, mips_register_name);
6295 set_gdbarch_register_reggroup_p (gdbarch,
6296 mips_tdesc_register_reggroup_p);
6298 num_regs = gdbarch_num_regs (gdbarch);
6299 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
6300 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
6301 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
6304 /* Add ABI-specific aliases for the registers. */
6305 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
6306 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
6307 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
6308 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
6310 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
6311 user_reg_add (gdbarch, mips_o32_aliases[i].name,
6312 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
6314 /* Add some other standard aliases. */
6315 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
6316 user_reg_add (gdbarch, mips_register_aliases[i].name,
6317 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
6319 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)
6320 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,
6321 value_of_mips_user_reg,
6322 &mips_numeric_register_aliases[i].regnum);
6328 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
6330 struct gdbarch_info info;
6332 /* Force the architecture to update, and (if it's a MIPS architecture)
6333 mips_gdbarch_init will take care of the rest. */
6334 gdbarch_info_init (&info);
6335 gdbarch_update_p (info);
6338 /* Print out which MIPS ABI is in use. */
6341 show_mips_abi (struct ui_file *file,
6343 struct cmd_list_element *ignored_cmd,
6344 const char *ignored_value)
6346 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
6349 "The MIPS ABI is unknown because the current architecture "
6353 enum mips_abi global_abi = global_mips_abi ();
6354 enum mips_abi actual_abi = mips_abi (target_gdbarch);
6355 const char *actual_abi_str = mips_abi_strings[actual_abi];
6357 if (global_abi == MIPS_ABI_UNKNOWN)
6360 "The MIPS ABI is set automatically (currently \"%s\").\n",
6362 else if (global_abi == actual_abi)
6365 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6369 /* Probably shouldn't happen... */
6370 fprintf_filtered (file,
6371 "The (auto detected) MIPS ABI \"%s\" is in use "
6372 "even though the user setting was \"%s\".\n",
6373 actual_abi_str, mips_abi_strings[global_abi]);
6379 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
6381 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6385 int ef_mips_32bitmode;
6386 /* Determine the ISA. */
6387 switch (tdep->elf_flags & EF_MIPS_ARCH)
6405 /* Determine the size of a pointer. */
6406 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6407 fprintf_unfiltered (file,
6408 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6410 fprintf_unfiltered (file,
6411 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6413 fprintf_unfiltered (file,
6414 "mips_dump_tdep: ef_mips_arch = %d\n",
6416 fprintf_unfiltered (file,
6417 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6418 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
6419 fprintf_unfiltered (file,
6421 "mips_mask_address_p() %d (default %d)\n",
6422 mips_mask_address_p (tdep),
6423 tdep->default_mask_address_p);
6425 fprintf_unfiltered (file,
6426 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6427 MIPS_DEFAULT_FPU_TYPE,
6428 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6429 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6430 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6432 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
6433 MIPS_EABI (gdbarch));
6434 fprintf_unfiltered (file,
6435 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6436 MIPS_FPU_TYPE (gdbarch),
6437 (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none"
6438 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single"
6439 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double"
6443 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6446 _initialize_mips_tdep (void)
6448 static struct cmd_list_element *mipsfpulist = NULL;
6449 struct cmd_list_element *c;
6451 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
6452 if (MIPS_ABI_LAST + 1
6453 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6454 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
6456 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6458 mips_pdr_data = register_objfile_data ();
6460 /* Create feature sets with the appropriate properties. The values
6461 are not important. */
6462 mips_tdesc_gp32 = allocate_target_description ();
6463 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
6465 mips_tdesc_gp64 = allocate_target_description ();
6466 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
6468 /* Add root prefix command for all "set mips"/"show mips" commands. */
6469 add_prefix_cmd ("mips", no_class, set_mips_command,
6470 _("Various MIPS specific commands."),
6471 &setmipscmdlist, "set mips ", 0, &setlist);
6473 add_prefix_cmd ("mips", no_class, show_mips_command,
6474 _("Various MIPS specific commands."),
6475 &showmipscmdlist, "show mips ", 0, &showlist);
6477 /* Allow the user to override the ABI. */
6478 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
6479 &mips_abi_string, _("\
6480 Set the MIPS ABI used by this program."), _("\
6481 Show the MIPS ABI used by this program."), _("\
6482 This option can be set to one of:\n\
6483 auto - the default ABI associated with the current binary\n\
6492 &setmipscmdlist, &showmipscmdlist);
6494 /* Let the user turn off floating point and set the fence post for
6495 heuristic_proc_start. */
6497 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6498 _("Set use of MIPS floating-point coprocessor."),
6499 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6500 add_cmd ("single", class_support, set_mipsfpu_single_command,
6501 _("Select single-precision MIPS floating-point coprocessor."),
6503 add_cmd ("double", class_support, set_mipsfpu_double_command,
6504 _("Select double-precision MIPS floating-point coprocessor."),
6506 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6507 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6508 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6509 add_cmd ("none", class_support, set_mipsfpu_none_command,
6510 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
6511 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6512 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6513 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6514 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6515 _("Select MIPS floating-point coprocessor automatically."),
6517 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6518 _("Show current use of MIPS floating-point coprocessor target."),
6521 /* We really would like to have both "0" and "unlimited" work, but
6522 command.c doesn't deal with that. So make it a var_zinteger
6523 because the user can always use "999999" or some such for unlimited. */
6524 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
6525 &heuristic_fence_post, _("\
6526 Set the distance searched for the start of a function."), _("\
6527 Show the distance searched for the start of a function."), _("\
6528 If you are debugging a stripped executable, GDB needs to search through the\n\
6529 program for the start of a function. This command sets the distance of the\n\
6530 search. The only need to set it is when debugging a stripped executable."),
6531 reinit_frame_cache_sfunc,
6532 NULL, /* FIXME: i18n: The distance searched for
6533 the start of a function is %s. */
6534 &setlist, &showlist);
6536 /* Allow the user to control whether the upper bits of 64-bit
6537 addresses should be zeroed. */
6538 add_setshow_auto_boolean_cmd ("mask-address", no_class,
6539 &mask_address_var, _("\
6540 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6541 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6542 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6543 allow GDB to determine the correct value."),
6544 NULL, show_mask_address,
6545 &setmipscmdlist, &showmipscmdlist);
6547 /* Allow the user to control the size of 32 bit registers within the
6548 raw remote packet. */
6549 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6550 &mips64_transfers_32bit_regs_p, _("\
6551 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6553 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6555 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6556 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6557 64 bits for others. Use \"off\" to disable compatibility mode"),
6558 set_mips64_transfers_32bit_regs,
6559 NULL, /* FIXME: i18n: Compatibility with 64-bit
6560 MIPS target that transfers 32-bit
6561 quantities is %s. */
6562 &setlist, &showlist);
6564 /* Debug this files internals. */
6565 add_setshow_zinteger_cmd ("mips", class_maintenance,
6567 Set mips debugging."), _("\
6568 Show mips debugging."), _("\
6569 When non-zero, mips specific debugging is enabled."),
6571 NULL, /* FIXME: i18n: Mips debugging is
6573 &setdebuglist, &showdebuglist);