1 /* Target-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "solib-svr4.h"
28 #include "mips-tdep.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
33 #include "trad-frame.h"
34 #include "tramp-frame.h"
37 #include "solib-svr4.h"
40 #include "mips-linux-tdep.h"
42 static struct target_so_ops mips_svr4_so_ops;
44 /* Figure out where the longjmp will land.
45 We expect the first arg to be a pointer to the jmp_buf structure
46 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
47 at. The pc is copied into PC. This routine returns 1 on
50 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
51 #define MIPS_LINUX_JB_PC 0
54 mips_linux_get_longjmp_target (CORE_ADDR *pc)
57 char buf[gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT];
59 jb_addr = read_register (MIPS_A0_REGNUM);
61 if (target_read_memory (jb_addr
62 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
64 gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT))
67 *pc = extract_unsigned_integer (buf,
68 gdbarch_ptr_bit (current_gdbarch)
74 /* Transform the bits comprising a 32-bit register to the right size
75 for regcache_raw_supply(). This is needed when mips_isa_regsize()
79 supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
81 gdb_byte buf[MAX_REGISTER_SIZE];
82 store_signed_integer (buf, register_size (current_gdbarch, regnum),
83 extract_signed_integer (addr, 4));
84 regcache_raw_supply (regcache, regnum, buf);
87 /* Unpack an elf_gregset_t into GDB's register cache. */
90 mips_supply_gregset (struct regcache *regcache,
91 const mips_elf_gregset_t *gregsetp)
94 const mips_elf_greg_t *regp = *gregsetp;
95 char zerobuf[MAX_REGISTER_SIZE];
97 memset (zerobuf, 0, MAX_REGISTER_SIZE);
99 for (regi = EF_REG0; regi <= EF_REG31; regi++)
100 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
102 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->lo,
104 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->hi,
107 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->pc,
109 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr,
110 regp + EF_CP0_BADVADDR);
111 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
112 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->cause,
113 regp + EF_CP0_CAUSE);
115 /* Fill inaccessible registers with zero. */
116 regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf);
117 for (regi = MIPS_FIRST_EMBED_REGNUM;
118 regi < MIPS_LAST_EMBED_REGNUM;
120 regcache_raw_supply (regcache, regi, zerobuf);
123 /* Pack our registers (or one register) into an elf_gregset_t. */
126 mips_fill_gregset (const struct regcache *regcache,
127 mips_elf_gregset_t *gregsetp, int regno)
130 mips_elf_greg_t *regp = *gregsetp;
135 memset (regp, 0, sizeof (mips_elf_gregset_t));
136 for (regi = 0; regi < 32; regi++)
137 mips_fill_gregset (regcache, gregsetp, regi);
138 mips_fill_gregset (regcache, gregsetp,
139 mips_regnum (current_gdbarch)->lo);
140 mips_fill_gregset (regcache, gregsetp,
141 mips_regnum (current_gdbarch)->hi);
142 mips_fill_gregset (regcache, gregsetp,
143 mips_regnum (current_gdbarch)->pc);
144 mips_fill_gregset (regcache, gregsetp,
145 mips_regnum (current_gdbarch)->badvaddr);
146 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
147 mips_fill_gregset (regcache, gregsetp,
148 mips_regnum (current_gdbarch)->cause);
154 dst = regp + regno + EF_REG0;
155 regcache_raw_collect (regcache, regno, dst);
159 if (regno == mips_regnum (current_gdbarch)->lo)
161 else if (regno == mips_regnum (current_gdbarch)->hi)
163 else if (regno == mips_regnum (current_gdbarch)->pc)
164 regaddr = EF_CP0_EPC;
165 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
166 regaddr = EF_CP0_BADVADDR;
167 else if (regno == MIPS_PS_REGNUM)
168 regaddr = EF_CP0_STATUS;
169 else if (regno == mips_regnum (current_gdbarch)->cause)
170 regaddr = EF_CP0_CAUSE;
176 dst = regp + regaddr;
177 regcache_raw_collect (regcache, regno, dst);
181 /* Likewise, unpack an elf_fpregset_t. */
184 mips_supply_fpregset (struct regcache *regcache,
185 const mips_elf_fpregset_t *fpregsetp)
188 char zerobuf[MAX_REGISTER_SIZE];
190 memset (zerobuf, 0, MAX_REGISTER_SIZE);
192 for (regi = 0; regi < 32; regi++)
193 regcache_raw_supply (regcache, FP0_REGNUM + regi, *fpregsetp + regi);
195 regcache_raw_supply (regcache,
196 mips_regnum (current_gdbarch)->fp_control_status,
199 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
200 regcache_raw_supply (regcache,
201 mips_regnum (current_gdbarch)->fp_implementation_revision,
205 /* Likewise, pack one or all floating point registers into an
209 mips_fill_fpregset (const struct regcache *regcache,
210 mips_elf_fpregset_t *fpregsetp, int regno)
214 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
216 to = (char *) (*fpregsetp + regno - FP0_REGNUM);
217 regcache_raw_collect (regcache, regno, to);
219 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
221 to = (char *) (*fpregsetp + 32);
222 regcache_raw_collect (regcache, regno, to);
224 else if (regno == -1)
228 for (regi = 0; regi < 32; regi++)
229 mips_fill_fpregset (regcache, fpregsetp, FP0_REGNUM + regi);
230 mips_fill_fpregset (regcache, fpregsetp,
231 mips_regnum (current_gdbarch)->fp_control_status);
235 /* Support for 64-bit ABIs. */
237 /* Figure out where the longjmp will land.
238 We expect the first arg to be a pointer to the jmp_buf structure
239 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
240 at. The pc is copied into PC. This routine returns 1 on
243 /* Details about jmp_buf. */
245 #define MIPS64_LINUX_JB_PC 0
248 mips64_linux_get_longjmp_target (CORE_ADDR *pc)
251 void *buf = alloca (gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT);
252 int element_size = gdbarch_ptr_bit (current_gdbarch) == 32 ? 4 : 8;
254 jb_addr = read_register (MIPS_A0_REGNUM);
256 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
258 gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT))
261 *pc = extract_unsigned_integer (buf,
262 gdbarch_ptr_bit (current_gdbarch)
268 /* Register set support functions. These operate on standard 64-bit
269 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
270 target will still use the 64-bit format for PTRACE_GETREGS. */
272 /* Supply a 64-bit register. */
275 supply_64bit_reg (struct regcache *regcache, int regnum,
278 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
279 && register_size (current_gdbarch, regnum) == 4)
280 regcache_raw_supply (regcache, regnum, buf + 4);
282 regcache_raw_supply (regcache, regnum, buf);
285 /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
288 mips64_supply_gregset (struct regcache *regcache,
289 const mips64_elf_gregset_t *gregsetp)
292 const mips64_elf_greg_t *regp = *gregsetp;
293 gdb_byte zerobuf[MAX_REGISTER_SIZE];
295 memset (zerobuf, 0, MAX_REGISTER_SIZE);
297 for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++)
298 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
299 (const gdb_byte *)(regp + regi));
301 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->lo,
302 (const gdb_byte *) (regp + MIPS64_EF_LO));
303 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->hi,
304 (const gdb_byte *) (regp + MIPS64_EF_HI));
306 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->pc,
307 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
308 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr,
309 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
310 supply_64bit_reg (regcache, MIPS_PS_REGNUM,
311 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
312 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->cause,
313 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
315 /* Fill inaccessible registers with zero. */
316 regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf);
317 for (regi = MIPS_FIRST_EMBED_REGNUM;
318 regi < MIPS_LAST_EMBED_REGNUM;
320 regcache_raw_supply (regcache, regi, zerobuf);
323 /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
326 mips64_fill_gregset (const struct regcache *regcache,
327 mips64_elf_gregset_t *gregsetp, int regno)
330 mips64_elf_greg_t *regp = *gregsetp;
335 memset (regp, 0, sizeof (mips64_elf_gregset_t));
336 for (regi = 0; regi < 32; regi++)
337 mips64_fill_gregset (regcache, gregsetp, regi);
338 mips64_fill_gregset (regcache, gregsetp,
339 mips_regnum (current_gdbarch)->lo);
340 mips64_fill_gregset (regcache, gregsetp,
341 mips_regnum (current_gdbarch)->hi);
342 mips64_fill_gregset (regcache, gregsetp,
343 mips_regnum (current_gdbarch)->pc);
344 mips64_fill_gregset (regcache, gregsetp,
345 mips_regnum (current_gdbarch)->badvaddr);
346 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
347 mips64_fill_gregset (regcache, gregsetp,
348 mips_regnum (current_gdbarch)->cause);
353 regaddr = regno + MIPS64_EF_REG0;
354 else if (regno == mips_regnum (current_gdbarch)->lo)
355 regaddr = MIPS64_EF_LO;
356 else if (regno == mips_regnum (current_gdbarch)->hi)
357 regaddr = MIPS64_EF_HI;
358 else if (regno == mips_regnum (current_gdbarch)->pc)
359 regaddr = MIPS64_EF_CP0_EPC;
360 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
361 regaddr = MIPS64_EF_CP0_BADVADDR;
362 else if (regno == MIPS_PS_REGNUM)
363 regaddr = MIPS64_EF_CP0_STATUS;
364 else if (regno == mips_regnum (current_gdbarch)->cause)
365 regaddr = MIPS64_EF_CP0_CAUSE;
371 gdb_byte buf[MAX_REGISTER_SIZE];
374 regcache_raw_collect (regcache, regno, buf);
375 val = extract_signed_integer (buf,
376 register_size (current_gdbarch, regno));
377 dst = regp + regaddr;
378 store_signed_integer (dst, 8, val);
382 /* Likewise, unpack an elf_fpregset_t. */
385 mips64_supply_fpregset (struct regcache *regcache,
386 const mips64_elf_fpregset_t *fpregsetp)
390 /* See mips_linux_o32_sigframe_init for a description of the
391 peculiar FP register layout. */
392 if (register_size (current_gdbarch, FP0_REGNUM) == 4)
393 for (regi = 0; regi < 32; regi++)
395 const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1));
396 if ((gdbarch_byte_order (current_gdbarch)
397 == BFD_ENDIAN_BIG) != (regi & 1))
399 regcache_raw_supply (regcache, FP0_REGNUM + regi, reg_ptr);
402 for (regi = 0; regi < 32; regi++)
403 regcache_raw_supply (regcache, FP0_REGNUM + regi,
404 (const char *)(*fpregsetp + regi));
406 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->fp_control_status,
407 (const gdb_byte *)(*fpregsetp + 32));
409 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
410 include it - but the result of PTRACE_GETFPREGS does. The best we
411 can do is to assume that its value is present. */
412 supply_32bit_reg (regcache,
413 mips_regnum (current_gdbarch)->fp_implementation_revision,
414 (const gdb_byte *)(*fpregsetp + 32) + 4);
417 /* Likewise, pack one or all floating point registers into an
421 mips64_fill_fpregset (const struct regcache *regcache,
422 mips64_elf_fpregset_t *fpregsetp, int regno)
426 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
428 /* See mips_linux_o32_sigframe_init for a description of the
429 peculiar FP register layout. */
430 if (register_size (current_gdbarch, regno) == 4)
432 int regi = regno - FP0_REGNUM;
434 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
435 if ((gdbarch_byte_order (current_gdbarch)
436 == BFD_ENDIAN_BIG) != (regi & 1))
438 regcache_raw_collect (regcache, regno, to);
442 to = (gdb_byte *) (*fpregsetp + regno - FP0_REGNUM);
443 regcache_raw_collect (regcache, regno, to);
446 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
448 gdb_byte buf[MAX_REGISTER_SIZE];
451 regcache_raw_collect (regcache, regno, buf);
452 val = extract_signed_integer (buf,
453 register_size (current_gdbarch, regno));
454 to = (gdb_byte *) (*fpregsetp + 32);
455 store_signed_integer (to, 4, val);
457 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
459 gdb_byte buf[MAX_REGISTER_SIZE];
462 regcache_raw_collect (regcache, regno, buf);
463 val = extract_signed_integer (buf,
464 register_size (current_gdbarch, regno));
465 to = (gdb_byte *) (*fpregsetp + 32) + 4;
466 store_signed_integer (to, 4, val);
468 else if (regno == -1)
472 for (regi = 0; regi < 32; regi++)
473 mips64_fill_fpregset (regcache, fpregsetp, FP0_REGNUM + regi);
474 mips64_fill_fpregset (regcache, fpregsetp,
475 mips_regnum (current_gdbarch)->fp_control_status);
476 mips64_fill_fpregset (regcache, fpregsetp,
477 (mips_regnum (current_gdbarch)
478 ->fp_implementation_revision));
483 /* Use a local version of this function to get the correct types for
484 regsets, until multi-arch core support is ready. */
487 fetch_core_registers (struct regcache *regcache,
488 char *core_reg_sect, unsigned core_reg_size,
489 int which, CORE_ADDR reg_addr)
491 mips_elf_gregset_t gregset;
492 mips_elf_fpregset_t fpregset;
493 mips64_elf_gregset_t gregset64;
494 mips64_elf_fpregset_t fpregset64;
498 if (core_reg_size == sizeof (gregset))
500 memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
501 mips_supply_gregset (regcache,
502 (const mips_elf_gregset_t *) &gregset);
504 else if (core_reg_size == sizeof (gregset64))
506 memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64));
507 mips64_supply_gregset (regcache,
508 (const mips64_elf_gregset_t *) &gregset64);
512 warning (_("wrong size gregset struct in core file"));
517 if (core_reg_size == sizeof (fpregset))
519 memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
520 mips_supply_fpregset (regcache,
521 (const mips_elf_fpregset_t *) &fpregset);
523 else if (core_reg_size == sizeof (fpregset64))
525 memcpy ((char *) &fpregset64, core_reg_sect,
526 sizeof (fpregset64));
527 mips64_supply_fpregset (regcache,
528 (const mips64_elf_fpregset_t *) &fpregset64);
532 warning (_("wrong size fpregset struct in core file"));
537 /* Register that we are able to handle ELF file formats using standard
538 procfs "regset" structures. */
540 static struct core_fns regset_core_fns =
542 bfd_target_elf_flavour, /* core_flavour */
543 default_check_format, /* check_format */
544 default_core_sniffer, /* core_sniffer */
545 fetch_core_registers, /* core_read_registers */
550 /* Check the code at PC for a dynamic linker lazy resolution stub.
551 Because they aren't in the .plt section, we pattern-match on the
552 code generated by GNU ld. They look like this:
559 (with the appropriate doubleword instructions for N64). Also
560 return the dynamic symbol index used in the last instruction. */
563 mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
565 unsigned char buf[28], *p;
566 ULONGEST insn, insn1;
567 int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64);
569 read_memory (pc - 12, buf, 28);
573 /* ld t9,0x8010(gp) */
578 /* lw t9,0x8010(gp) */
585 insn = extract_unsigned_integer (p, 4);
593 insn = extract_unsigned_integer (p + 4, 4);
597 if (insn != 0x03e0782d)
603 if (insn != 0x03e07821)
607 insn = extract_unsigned_integer (p + 8, 4);
609 if (insn != 0x0320f809)
612 insn = extract_unsigned_integer (p + 12, 4);
615 /* daddiu t8,zero,0 */
616 if ((insn & 0xffff0000) != 0x64180000)
621 /* addiu t8,zero,0 */
622 if ((insn & 0xffff0000) != 0x24180000)
626 return (insn & 0xffff);
629 /* Return non-zero iff PC belongs to the dynamic linker resolution
630 code or to a stub. */
633 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
635 /* Check whether PC is in the dynamic linker. This also checks
636 whether it is in the .plt section, which MIPS does not use. */
637 if (svr4_in_dynsym_resolve_code (pc))
640 /* Pattern match for the stub. It would be nice if there were a
641 more efficient way to avoid this check. */
642 if (mips_linux_in_dynsym_stub (pc, NULL))
648 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
649 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
650 implementation of this triggers at "fixup" from the same objfile as
651 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
652 "__dl_runtime_resolve" directly. An unresolved PLT entry will
653 point to _dl_runtime_resolve, which will first call
654 __dl_runtime_resolve, and then pass control to the resolved
658 mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
660 struct minimal_symbol *resolver;
662 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
664 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
665 return frame_pc_unwind (get_current_frame ());
670 /* Signal trampoline support. There are four supported layouts for a
671 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
672 n64 rt_sigframe. We handle them all independently; not the most
673 efficient way, but simplest. First, declare all the unwinders. */
675 static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
676 struct frame_info *next_frame,
677 struct trad_frame_cache *this_cache,
680 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
681 struct frame_info *next_frame,
682 struct trad_frame_cache *this_cache,
685 #define MIPS_NR_LINUX 4000
686 #define MIPS_NR_N64_LINUX 5000
687 #define MIPS_NR_N32_LINUX 6000
689 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
690 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
691 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
692 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
694 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
695 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
696 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
697 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
698 #define MIPS_INST_SYSCALL 0x0000000c
700 static const struct tramp_frame mips_linux_o32_sigframe = {
704 { MIPS_INST_LI_V0_SIGRETURN, -1 },
705 { MIPS_INST_SYSCALL, -1 },
706 { TRAMP_SENTINEL_INSN, -1 }
708 mips_linux_o32_sigframe_init
711 static const struct tramp_frame mips_linux_o32_rt_sigframe = {
715 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
716 { MIPS_INST_SYSCALL, -1 },
717 { TRAMP_SENTINEL_INSN, -1 } },
718 mips_linux_o32_sigframe_init
721 static const struct tramp_frame mips_linux_n32_rt_sigframe = {
725 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
726 { MIPS_INST_SYSCALL, -1 },
727 { TRAMP_SENTINEL_INSN, -1 }
729 mips_linux_n32n64_sigframe_init
732 static const struct tramp_frame mips_linux_n64_rt_sigframe = {
736 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
737 { MIPS_INST_SYSCALL, -1 },
738 { TRAMP_SENTINEL_INSN, -1 }
740 mips_linux_n32n64_sigframe_init
744 /* The unwinder for o32 signal frames. The legacy structures look
748 u32 sf_ass[4]; [argument save space for o32]
749 u32 sf_code[2]; [signal trampoline]
750 struct sigcontext sf_sc;
755 unsigned int sc_regmask; [Unused]
756 unsigned int sc_status;
757 unsigned long long sc_pc;
758 unsigned long long sc_regs[32];
759 unsigned long long sc_fpregs[32];
760 unsigned int sc_ownedfp;
761 unsigned int sc_fpc_csr;
762 unsigned int sc_fpc_eir; [Unused]
763 unsigned int sc_used_math;
764 unsigned int sc_ssflags; [Unused]
765 [Alignment hole of four bytes]
766 unsigned long long sc_mdhi;
767 unsigned long long sc_mdlo;
769 unsigned int sc_cause; [Unused]
770 unsigned int sc_badvaddr; [Unused]
772 unsigned long sc_sigset[4]; [kernel's sigset_t]
775 The RT signal frames look like this:
778 u32 rs_ass[4]; [argument save space for o32]
779 u32 rs_code[2] [signal trampoline]
780 struct siginfo rs_info;
781 struct ucontext rs_uc;
785 unsigned long uc_flags;
786 struct ucontext *uc_link;
788 [Alignment hole of four bytes]
789 struct sigcontext uc_mcontext;
794 #define SIGFRAME_CODE_OFFSET (4 * 4)
795 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
797 #define RTSIGFRAME_SIGINFO_SIZE 128
798 #define STACK_T_SIZE (3 * 4)
799 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
800 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
801 + RTSIGFRAME_SIGINFO_SIZE \
802 + UCONTEXT_SIGCONTEXT_OFFSET)
804 #define SIGCONTEXT_PC (1 * 8)
805 #define SIGCONTEXT_REGS (2 * 8)
806 #define SIGCONTEXT_FPREGS (34 * 8)
807 #define SIGCONTEXT_FPCSR (66 * 8 + 4)
808 #define SIGCONTEXT_HI (69 * 8)
809 #define SIGCONTEXT_LO (70 * 8)
810 #define SIGCONTEXT_CAUSE (71 * 8 + 0)
811 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
813 #define SIGCONTEXT_REG_SIZE 8
816 mips_linux_o32_sigframe_init (const struct tramp_frame *self,
817 struct frame_info *next_frame,
818 struct trad_frame_cache *this_cache,
821 int ireg, reg_position;
822 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
823 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
826 if (self == &mips_linux_o32_sigframe)
827 sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET;
829 sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET;
831 /* I'm not proud of this hack. Eventually we will have the
832 infrastructure to indicate the size of saved registers on a
833 per-frame basis, but right now we don't; the kernel saves eight
834 bytes but we only want four. Use regs_base to access any
836 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
837 regs_base = sigcontext_base + 4;
839 regs_base = sigcontext_base;
842 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM
843 + gdbarch_num_regs (current_gdbarch),
844 regs_base + SIGCONTEXT_REGS);
847 for (ireg = 1; ireg < 32; ireg++)
848 trad_frame_set_reg_addr (this_cache,
849 ireg + MIPS_ZERO_REGNUM
850 + gdbarch_num_regs (current_gdbarch),
851 regs_base + SIGCONTEXT_REGS
852 + ireg * SIGCONTEXT_REG_SIZE);
854 /* The way that floating point registers are saved, unfortunately,
855 depends on the architecture the kernel is built for. For the r3000 and
856 tx39, four bytes of each register are at the beginning of each of the
857 32 eight byte slots. For everything else, the registers are saved
858 using double precision; only the even-numbered slots are initialized,
859 and the high bits are the odd-numbered register. Assume the latter
860 layout, since we can't tell, and it's much more common. Which bits are
861 the "high" bits depends on endianness. */
862 for (ireg = 0; ireg < 32; ireg++)
863 if ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
864 trad_frame_set_reg_addr (this_cache,
866 gdbarch_num_regs (current_gdbarch),
867 sigcontext_base + SIGCONTEXT_FPREGS + 4
868 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
870 trad_frame_set_reg_addr (this_cache,
872 + gdbarch_num_regs (current_gdbarch),
873 sigcontext_base + SIGCONTEXT_FPREGS
874 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
876 trad_frame_set_reg_addr (this_cache,
877 regs->pc + gdbarch_num_regs (current_gdbarch),
878 regs_base + SIGCONTEXT_PC);
880 trad_frame_set_reg_addr (this_cache,
881 regs->fp_control_status
882 + gdbarch_num_regs (current_gdbarch),
883 sigcontext_base + SIGCONTEXT_FPCSR);
884 trad_frame_set_reg_addr (this_cache,
885 regs->hi + gdbarch_num_regs (current_gdbarch),
886 regs_base + SIGCONTEXT_HI);
887 trad_frame_set_reg_addr (this_cache,
888 regs->lo + gdbarch_num_regs (current_gdbarch),
889 regs_base + SIGCONTEXT_LO);
890 trad_frame_set_reg_addr (this_cache,
891 regs->cause + gdbarch_num_regs (current_gdbarch),
892 sigcontext_base + SIGCONTEXT_CAUSE);
893 trad_frame_set_reg_addr (this_cache,
894 regs->badvaddr + gdbarch_num_regs (current_gdbarch),
895 sigcontext_base + SIGCONTEXT_BADVADDR);
897 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
898 trad_frame_set_id (this_cache,
899 frame_id_build (func - SIGFRAME_CODE_OFFSET,
904 /* For N32/N64 things look different. There is no non-rt signal frame.
906 struct rt_sigframe_n32 {
907 u32 rs_ass[4]; [ argument save space for o32 ]
908 u32 rs_code[2]; [ signal trampoline ]
909 struct siginfo rs_info;
910 struct ucontextn32 rs_uc;
917 struct sigcontext uc_mcontext;
918 sigset_t uc_sigmask; [ mask last for extensibility ]
921 struct rt_sigframe_n32 {
922 u32 rs_ass[4]; [ argument save space for o32 ]
923 u32 rs_code[2]; [ signal trampoline ]
924 struct siginfo rs_info;
925 struct ucontext rs_uc;
929 unsigned long uc_flags;
930 struct ucontext *uc_link;
932 struct sigcontext uc_mcontext;
933 sigset_t uc_sigmask; [ mask last for extensibility ]
936 And the sigcontext is different (this is for both n32 and n64):
939 unsigned long long sc_regs[32];
940 unsigned long long sc_fpregs[32];
941 unsigned long long sc_mdhi;
942 unsigned long long sc_mdlo;
943 unsigned long long sc_pc;
944 unsigned int sc_status;
945 unsigned int sc_fpc_csr;
946 unsigned int sc_fpc_eir;
947 unsigned int sc_used_math;
948 unsigned int sc_cause;
949 unsigned int sc_badvaddr;
953 #define N32_STACK_T_SIZE STACK_T_SIZE
954 #define N64_STACK_T_SIZE (2 * 8 + 4)
955 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
956 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
957 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
958 + RTSIGFRAME_SIGINFO_SIZE \
959 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
960 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
961 + RTSIGFRAME_SIGINFO_SIZE \
962 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
964 #define N64_SIGCONTEXT_REGS (0 * 8)
965 #define N64_SIGCONTEXT_FPREGS (32 * 8)
966 #define N64_SIGCONTEXT_HI (64 * 8)
967 #define N64_SIGCONTEXT_LO (65 * 8)
968 #define N64_SIGCONTEXT_PC (66 * 8)
969 #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
970 #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
971 #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
972 #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
974 #define N64_SIGCONTEXT_REG_SIZE 8
977 mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
978 struct frame_info *next_frame,
979 struct trad_frame_cache *this_cache,
982 int ireg, reg_position;
983 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
984 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
986 if (self == &mips_linux_n32_rt_sigframe)
987 sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET;
989 sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET;
992 trad_frame_set_reg_addr (this_cache,
994 + gdbarch_num_regs (current_gdbarch),
995 sigcontext_base + N64_SIGCONTEXT_REGS);
998 for (ireg = 1; ireg < 32; ireg++)
999 trad_frame_set_reg_addr (this_cache,
1000 ireg + MIPS_ZERO_REGNUM
1001 + gdbarch_num_regs (current_gdbarch),
1002 sigcontext_base + N64_SIGCONTEXT_REGS
1003 + ireg * N64_SIGCONTEXT_REG_SIZE);
1005 for (ireg = 0; ireg < 32; ireg++)
1006 trad_frame_set_reg_addr (this_cache,
1008 + gdbarch_num_regs (current_gdbarch),
1009 sigcontext_base + N64_SIGCONTEXT_FPREGS
1010 + ireg * N64_SIGCONTEXT_REG_SIZE);
1012 trad_frame_set_reg_addr (this_cache,
1013 regs->pc + gdbarch_num_regs (current_gdbarch),
1014 sigcontext_base + N64_SIGCONTEXT_PC);
1016 trad_frame_set_reg_addr (this_cache,
1017 regs->fp_control_status
1018 + gdbarch_num_regs (current_gdbarch),
1019 sigcontext_base + N64_SIGCONTEXT_FPCSR);
1020 trad_frame_set_reg_addr (this_cache,
1021 regs->hi + gdbarch_num_regs (current_gdbarch),
1022 sigcontext_base + N64_SIGCONTEXT_HI);
1023 trad_frame_set_reg_addr (this_cache,
1024 regs->lo + gdbarch_num_regs (current_gdbarch),
1025 sigcontext_base + N64_SIGCONTEXT_LO);
1026 trad_frame_set_reg_addr (this_cache,
1027 regs->cause + gdbarch_num_regs (current_gdbarch),
1028 sigcontext_base + N64_SIGCONTEXT_CAUSE);
1029 trad_frame_set_reg_addr (this_cache,
1030 regs->badvaddr + gdbarch_num_regs (current_gdbarch),
1031 sigcontext_base + N64_SIGCONTEXT_BADVADDR);
1033 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1034 trad_frame_set_id (this_cache,
1035 frame_id_build (func - SIGFRAME_CODE_OFFSET,
1040 /* Initialize one of the GNU/Linux OS ABIs. */
1043 mips_linux_init_abi (struct gdbarch_info info,
1044 struct gdbarch *gdbarch)
1046 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1047 enum mips_abi abi = mips_abi (gdbarch);
1052 set_gdbarch_get_longjmp_target (gdbarch,
1053 mips_linux_get_longjmp_target);
1054 set_solib_svr4_fetch_link_map_offsets
1055 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
1056 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1057 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
1060 set_gdbarch_get_longjmp_target (gdbarch,
1061 mips_linux_get_longjmp_target);
1062 set_solib_svr4_fetch_link_map_offsets
1063 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
1064 set_gdbarch_long_double_bit (gdbarch, 128);
1065 /* These floatformats should probably be renamed. MIPS uses
1066 the same 128-bit IEEE floating point format that IA-64 uses,
1067 except that the quiet/signalling NaN bit is reversed (GDB
1068 does not distinguish between quiet and signalling NaNs). */
1069 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
1070 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
1073 set_gdbarch_get_longjmp_target (gdbarch,
1074 mips64_linux_get_longjmp_target);
1075 set_solib_svr4_fetch_link_map_offsets
1076 (gdbarch, svr4_lp64_fetch_link_map_offsets);
1077 set_gdbarch_long_double_bit (gdbarch, 128);
1078 /* These floatformats should probably be renamed. MIPS uses
1079 the same 128-bit IEEE floating point format that IA-64 uses,
1080 except that the quiet/signalling NaN bit is reversed (GDB
1081 does not distinguish between quiet and signalling NaNs). */
1082 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
1083 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
1086 internal_error (__FILE__, __LINE__, _("can't handle ABI"));
1090 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
1091 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1093 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
1095 /* Enable TLS support. */
1096 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1097 svr4_fetch_objfile_link_map);
1099 /* Initialize this lazily, to avoid an initialization order
1100 dependency on solib-svr4.c's _initialize routine. */
1101 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
1103 mips_svr4_so_ops = svr4_so_ops;
1104 mips_svr4_so_ops.in_dynsym_resolve_code
1105 = mips_linux_in_dynsym_resolve_code;
1107 set_solib_ops (gdbarch, &mips_svr4_so_ops);
1111 _initialize_mips_linux_tdep (void)
1113 const struct bfd_arch_info *arch_info;
1115 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1117 arch_info = arch_info->next)
1119 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1121 mips_linux_init_abi);
1124 deprecated_add_core_fns (®set_core_fns);