1 /* Target-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "solib-svr4.h"
26 #include "mips-tdep.h"
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
31 #include "trad-frame.h"
32 #include "tramp-frame.h"
35 #include "solib-svr4.h"
38 #include "target-descriptions.h"
39 #include "mips-linux-tdep.h"
40 #include "glibc-tdep.h"
42 static struct target_so_ops mips_svr4_so_ops;
44 /* Figure out where the longjmp will land.
45 We expect the first arg to be a pointer to the jmp_buf structure
46 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
47 at. The pc is copied into PC. This routine returns 1 on
50 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
51 #define MIPS_LINUX_JB_PC 0
54 mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
57 struct gdbarch *gdbarch = get_frame_arch (frame);
58 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
59 char buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
61 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
63 if (target_read_memory (jb_addr
64 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
65 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
68 *pc = extract_unsigned_integer (buf,
69 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
75 /* Transform the bits comprising a 32-bit register to the right size
76 for regcache_raw_supply(). This is needed when mips_isa_regsize()
80 supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
82 struct gdbarch *gdbarch = get_regcache_arch (regcache);
83 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
84 gdb_byte buf[MAX_REGISTER_SIZE];
85 store_signed_integer (buf, register_size (gdbarch, regnum), byte_order,
86 extract_signed_integer (addr, 4, byte_order));
87 regcache_raw_supply (regcache, regnum, buf);
90 /* Unpack an elf_gregset_t into GDB's register cache. */
93 mips_supply_gregset (struct regcache *regcache,
94 const mips_elf_gregset_t *gregsetp)
97 const mips_elf_greg_t *regp = *gregsetp;
98 char zerobuf[MAX_REGISTER_SIZE];
99 struct gdbarch *gdbarch = get_regcache_arch (regcache);
101 memset (zerobuf, 0, MAX_REGISTER_SIZE);
103 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++)
104 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
106 if (mips_linux_restart_reg_p (gdbarch))
107 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0);
109 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO);
110 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI);
112 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc,
114 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
115 regp + EF_CP0_BADVADDR);
116 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
117 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause,
118 regp + EF_CP0_CAUSE);
120 /* Fill inaccessible registers with zero. */
121 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
122 regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf);
123 for (regi = MIPS_FIRST_EMBED_REGNUM;
124 regi <= MIPS_LAST_EMBED_REGNUM;
126 regcache_raw_supply (regcache, regi, zerobuf);
129 /* Pack our registers (or one register) into an elf_gregset_t. */
132 mips_fill_gregset (const struct regcache *regcache,
133 mips_elf_gregset_t *gregsetp, int regno)
135 struct gdbarch *gdbarch = get_regcache_arch (regcache);
137 mips_elf_greg_t *regp = *gregsetp;
142 memset (regp, 0, sizeof (mips_elf_gregset_t));
143 for (regi = 1; regi < 32; regi++)
144 mips_fill_gregset (regcache, gregsetp, regi);
145 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
146 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
147 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
148 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
149 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
150 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
151 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
155 if (regno > 0 && regno < 32)
157 dst = regp + regno + EF_REG0;
158 regcache_raw_collect (regcache, regno, dst);
162 if (regno == mips_regnum (gdbarch)->lo)
164 else if (regno == mips_regnum (gdbarch)->hi)
166 else if (regno == mips_regnum (gdbarch)->pc)
167 regaddr = EF_CP0_EPC;
168 else if (regno == mips_regnum (gdbarch)->badvaddr)
169 regaddr = EF_CP0_BADVADDR;
170 else if (regno == MIPS_PS_REGNUM)
171 regaddr = EF_CP0_STATUS;
172 else if (regno == mips_regnum (gdbarch)->cause)
173 regaddr = EF_CP0_CAUSE;
174 else if (mips_linux_restart_reg_p (gdbarch)
175 && regno == MIPS_RESTART_REGNUM)
182 dst = regp + regaddr;
183 regcache_raw_collect (regcache, regno, dst);
187 /* Likewise, unpack an elf_fpregset_t. */
190 mips_supply_fpregset (struct regcache *regcache,
191 const mips_elf_fpregset_t *fpregsetp)
193 struct gdbarch *gdbarch = get_regcache_arch (regcache);
195 char zerobuf[MAX_REGISTER_SIZE];
197 memset (zerobuf, 0, MAX_REGISTER_SIZE);
199 for (regi = 0; regi < 32; regi++)
200 regcache_raw_supply (regcache,
201 gdbarch_fp0_regnum (gdbarch) + regi,
204 regcache_raw_supply (regcache,
205 mips_regnum (gdbarch)->fp_control_status,
208 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
209 regcache_raw_supply (regcache,
210 mips_regnum (gdbarch)->fp_implementation_revision,
214 /* Likewise, pack one or all floating point registers into an
218 mips_fill_fpregset (const struct regcache *regcache,
219 mips_elf_fpregset_t *fpregsetp, int regno)
221 struct gdbarch *gdbarch = get_regcache_arch (regcache);
224 if ((regno >= gdbarch_fp0_regnum (gdbarch))
225 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
227 to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch));
228 regcache_raw_collect (regcache, regno, to);
230 else if (regno == mips_regnum (gdbarch)->fp_control_status)
232 to = (char *) (*fpregsetp + 32);
233 regcache_raw_collect (regcache, regno, to);
235 else if (regno == -1)
239 for (regi = 0; regi < 32; regi++)
240 mips_fill_fpregset (regcache, fpregsetp,
241 gdbarch_fp0_regnum (gdbarch) + regi);
242 mips_fill_fpregset (regcache, fpregsetp,
243 mips_regnum (gdbarch)->fp_control_status);
247 /* Support for 64-bit ABIs. */
249 /* Figure out where the longjmp will land.
250 We expect the first arg to be a pointer to the jmp_buf structure
251 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
252 at. The pc is copied into PC. This routine returns 1 on
255 /* Details about jmp_buf. */
257 #define MIPS64_LINUX_JB_PC 0
260 mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
263 struct gdbarch *gdbarch = get_frame_arch (frame);
264 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
265 void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
266 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8;
268 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
270 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
272 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
275 *pc = extract_unsigned_integer (buf,
276 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
282 /* Register set support functions. These operate on standard 64-bit
283 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
284 target will still use the 64-bit format for PTRACE_GETREGS. */
286 /* Supply a 64-bit register. */
289 supply_64bit_reg (struct regcache *regcache, int regnum,
292 struct gdbarch *gdbarch = get_regcache_arch (regcache);
293 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
294 && register_size (gdbarch, regnum) == 4)
295 regcache_raw_supply (regcache, regnum, buf + 4);
297 regcache_raw_supply (regcache, regnum, buf);
300 /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
303 mips64_supply_gregset (struct regcache *regcache,
304 const mips64_elf_gregset_t *gregsetp)
307 const mips64_elf_greg_t *regp = *gregsetp;
308 gdb_byte zerobuf[MAX_REGISTER_SIZE];
309 struct gdbarch *gdbarch = get_regcache_arch (regcache);
311 memset (zerobuf, 0, MAX_REGISTER_SIZE);
313 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++)
314 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
315 (const gdb_byte *)(regp + regi));
317 if (mips_linux_restart_reg_p (gdbarch))
318 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM,
319 (const gdb_byte *)(regp + MIPS64_EF_REG0));
321 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo,
322 (const gdb_byte *) (regp + MIPS64_EF_LO));
323 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi,
324 (const gdb_byte *) (regp + MIPS64_EF_HI));
326 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc,
327 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
328 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
329 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
330 supply_64bit_reg (regcache, MIPS_PS_REGNUM,
331 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
332 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause,
333 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
335 /* Fill inaccessible registers with zero. */
336 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
337 regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf);
338 for (regi = MIPS_FIRST_EMBED_REGNUM;
339 regi <= MIPS_LAST_EMBED_REGNUM;
341 regcache_raw_supply (regcache, regi, zerobuf);
344 /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
347 mips64_fill_gregset (const struct regcache *regcache,
348 mips64_elf_gregset_t *gregsetp, int regno)
350 struct gdbarch *gdbarch = get_regcache_arch (regcache);
351 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
353 mips64_elf_greg_t *regp = *gregsetp;
358 memset (regp, 0, sizeof (mips64_elf_gregset_t));
359 for (regi = 1; regi < 32; regi++)
360 mips64_fill_gregset (regcache, gregsetp, regi);
361 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
362 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
363 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
364 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
365 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
366 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
367 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
371 if (regno > 0 && regno < 32)
372 regaddr = regno + MIPS64_EF_REG0;
373 else if (regno == mips_regnum (gdbarch)->lo)
374 regaddr = MIPS64_EF_LO;
375 else if (regno == mips_regnum (gdbarch)->hi)
376 regaddr = MIPS64_EF_HI;
377 else if (regno == mips_regnum (gdbarch)->pc)
378 regaddr = MIPS64_EF_CP0_EPC;
379 else if (regno == mips_regnum (gdbarch)->badvaddr)
380 regaddr = MIPS64_EF_CP0_BADVADDR;
381 else if (regno == MIPS_PS_REGNUM)
382 regaddr = MIPS64_EF_CP0_STATUS;
383 else if (regno == mips_regnum (gdbarch)->cause)
384 regaddr = MIPS64_EF_CP0_CAUSE;
385 else if (mips_linux_restart_reg_p (gdbarch)
386 && regno == MIPS_RESTART_REGNUM)
387 regaddr = MIPS64_EF_REG0;
393 gdb_byte buf[MAX_REGISTER_SIZE];
396 regcache_raw_collect (regcache, regno, buf);
397 val = extract_signed_integer (buf, register_size (gdbarch, regno),
399 dst = regp + regaddr;
400 store_signed_integer (dst, 8, byte_order, val);
404 /* Likewise, unpack an elf_fpregset_t. */
407 mips64_supply_fpregset (struct regcache *regcache,
408 const mips64_elf_fpregset_t *fpregsetp)
410 struct gdbarch *gdbarch = get_regcache_arch (regcache);
413 /* See mips_linux_o32_sigframe_init for a description of the
414 peculiar FP register layout. */
415 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4)
416 for (regi = 0; regi < 32; regi++)
418 const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1));
419 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
421 regcache_raw_supply (regcache,
422 gdbarch_fp0_regnum (gdbarch) + regi,
426 for (regi = 0; regi < 32; regi++)
427 regcache_raw_supply (regcache,
428 gdbarch_fp0_regnum (gdbarch) + regi,
429 (const char *)(*fpregsetp + regi));
431 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status,
432 (const gdb_byte *)(*fpregsetp + 32));
434 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
435 include it - but the result of PTRACE_GETFPREGS does. The best we
436 can do is to assume that its value is present. */
437 supply_32bit_reg (regcache,
438 mips_regnum (gdbarch)->fp_implementation_revision,
439 (const gdb_byte *)(*fpregsetp + 32) + 4);
442 /* Likewise, pack one or all floating point registers into an
446 mips64_fill_fpregset (const struct regcache *regcache,
447 mips64_elf_fpregset_t *fpregsetp, int regno)
449 struct gdbarch *gdbarch = get_regcache_arch (regcache);
450 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
453 if ((regno >= gdbarch_fp0_regnum (gdbarch))
454 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
456 /* See mips_linux_o32_sigframe_init for a description of the
457 peculiar FP register layout. */
458 if (register_size (gdbarch, regno) == 4)
460 int regi = regno - gdbarch_fp0_regnum (gdbarch);
462 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
463 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
465 regcache_raw_collect (regcache, regno, to);
469 to = (gdb_byte *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch));
470 regcache_raw_collect (regcache, regno, to);
473 else if (regno == mips_regnum (gdbarch)->fp_control_status)
475 gdb_byte buf[MAX_REGISTER_SIZE];
478 regcache_raw_collect (regcache, regno, buf);
479 val = extract_signed_integer (buf, register_size (gdbarch, regno),
481 to = (gdb_byte *) (*fpregsetp + 32);
482 store_signed_integer (to, 4, byte_order, val);
484 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
486 gdb_byte buf[MAX_REGISTER_SIZE];
489 regcache_raw_collect (regcache, regno, buf);
490 val = extract_signed_integer (buf, register_size (gdbarch, regno),
492 to = (gdb_byte *) (*fpregsetp + 32) + 4;
493 store_signed_integer (to, 4, byte_order, val);
495 else if (regno == -1)
499 for (regi = 0; regi < 32; regi++)
500 mips64_fill_fpregset (regcache, fpregsetp,
501 gdbarch_fp0_regnum (gdbarch) + regi);
502 mips64_fill_fpregset (regcache, fpregsetp,
503 mips_regnum (gdbarch)->fp_control_status);
504 mips64_fill_fpregset (regcache, fpregsetp,
505 (mips_regnum (gdbarch)
506 ->fp_implementation_revision));
511 /* Use a local version of this function to get the correct types for
512 regsets, until multi-arch core support is ready. */
515 fetch_core_registers (struct regcache *regcache,
516 char *core_reg_sect, unsigned core_reg_size,
517 int which, CORE_ADDR reg_addr)
519 mips_elf_gregset_t gregset;
520 mips_elf_fpregset_t fpregset;
521 mips64_elf_gregset_t gregset64;
522 mips64_elf_fpregset_t fpregset64;
526 if (core_reg_size == sizeof (gregset))
528 memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
529 mips_supply_gregset (regcache,
530 (const mips_elf_gregset_t *) &gregset);
532 else if (core_reg_size == sizeof (gregset64))
534 memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64));
535 mips64_supply_gregset (regcache,
536 (const mips64_elf_gregset_t *) &gregset64);
540 warning (_("wrong size gregset struct in core file"));
545 if (core_reg_size == sizeof (fpregset))
547 memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
548 mips_supply_fpregset (regcache,
549 (const mips_elf_fpregset_t *) &fpregset);
551 else if (core_reg_size == sizeof (fpregset64))
553 memcpy ((char *) &fpregset64, core_reg_sect,
554 sizeof (fpregset64));
555 mips64_supply_fpregset (regcache,
556 (const mips64_elf_fpregset_t *) &fpregset64);
560 warning (_("wrong size fpregset struct in core file"));
565 /* Register that we are able to handle ELF file formats using standard
566 procfs "regset" structures. */
568 static struct core_fns regset_core_fns =
570 bfd_target_elf_flavour, /* core_flavour */
571 default_check_format, /* check_format */
572 default_core_sniffer, /* core_sniffer */
573 fetch_core_registers, /* core_read_registers */
577 static const struct target_desc *
578 mips_linux_core_read_description (struct gdbarch *gdbarch,
579 struct target_ops *target,
582 asection *section = bfd_get_section_by_name (abfd, ".reg");
586 switch (bfd_section_size (abfd, section))
588 case sizeof (mips_elf_gregset_t):
589 return mips_tdesc_gp32;
591 case sizeof (mips64_elf_gregset_t):
592 return mips_tdesc_gp64;
600 /* Check the code at PC for a dynamic linker lazy resolution stub.
601 Because they aren't in the .plt section, we pattern-match on the
602 code generated by GNU ld. They look like this:
609 (with the appropriate doubleword instructions for N64). Also
610 return the dynamic symbol index used in the last instruction. */
613 mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
615 unsigned char buf[28], *p;
616 ULONGEST insn, insn1;
617 int n64 = (mips_abi (target_gdbarch) == MIPS_ABI_N64);
618 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch);
620 read_memory (pc - 12, buf, 28);
624 /* ld t9,0x8010(gp) */
629 /* lw t9,0x8010(gp) */
636 insn = extract_unsigned_integer (p, 4, byte_order);
644 insn = extract_unsigned_integer (p + 4, 4, byte_order);
648 if (insn != 0x03e0782d)
654 if (insn != 0x03e07821)
658 insn = extract_unsigned_integer (p + 8, 4, byte_order);
660 if (insn != 0x0320f809)
663 insn = extract_unsigned_integer (p + 12, 4, byte_order);
666 /* daddiu t8,zero,0 */
667 if ((insn & 0xffff0000) != 0x64180000)
672 /* addiu t8,zero,0 */
673 if ((insn & 0xffff0000) != 0x24180000)
677 return (insn & 0xffff);
680 /* Return non-zero iff PC belongs to the dynamic linker resolution
681 code, a PLT entry, or a lazy binding stub. */
684 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
686 /* Check whether PC is in the dynamic linker. This also checks
687 whether it is in the .plt section, used by non-PIC executables. */
688 if (svr4_in_dynsym_resolve_code (pc))
691 /* Pattern match for the stub. It would be nice if there were a
692 more efficient way to avoid this check. */
693 if (mips_linux_in_dynsym_stub (pc, NULL))
699 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
700 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
701 implementation of this triggers at "fixup" from the same objfile as
702 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
703 "__dl_runtime_resolve" directly. An unresolved lazy binding
704 stub will point to _dl_runtime_resolve, which will first call
705 __dl_runtime_resolve, and then pass control to the resolved
709 mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
711 struct minimal_symbol *resolver;
713 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
715 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
716 return frame_unwind_caller_pc (get_current_frame ());
718 return glibc_skip_solib_resolver (gdbarch, pc);
721 /* Signal trampoline support. There are four supported layouts for a
722 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
723 n64 rt_sigframe. We handle them all independently; not the most
724 efficient way, but simplest. First, declare all the unwinders. */
726 static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
727 struct frame_info *this_frame,
728 struct trad_frame_cache *this_cache,
731 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
732 struct frame_info *this_frame,
733 struct trad_frame_cache *this_cache,
736 #define MIPS_NR_LINUX 4000
737 #define MIPS_NR_N64_LINUX 5000
738 #define MIPS_NR_N32_LINUX 6000
740 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
741 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
742 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
743 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
745 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
746 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
747 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
748 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
749 #define MIPS_INST_SYSCALL 0x0000000c
751 static const struct tramp_frame mips_linux_o32_sigframe = {
755 { MIPS_INST_LI_V0_SIGRETURN, -1 },
756 { MIPS_INST_SYSCALL, -1 },
757 { TRAMP_SENTINEL_INSN, -1 }
759 mips_linux_o32_sigframe_init
762 static const struct tramp_frame mips_linux_o32_rt_sigframe = {
766 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
767 { MIPS_INST_SYSCALL, -1 },
768 { TRAMP_SENTINEL_INSN, -1 } },
769 mips_linux_o32_sigframe_init
772 static const struct tramp_frame mips_linux_n32_rt_sigframe = {
776 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
777 { MIPS_INST_SYSCALL, -1 },
778 { TRAMP_SENTINEL_INSN, -1 }
780 mips_linux_n32n64_sigframe_init
783 static const struct tramp_frame mips_linux_n64_rt_sigframe = {
787 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
788 { MIPS_INST_SYSCALL, -1 },
789 { TRAMP_SENTINEL_INSN, -1 }
791 mips_linux_n32n64_sigframe_init
795 /* The unwinder for o32 signal frames. The legacy structures look
799 u32 sf_ass[4]; [argument save space for o32]
800 u32 sf_code[2]; [signal trampoline or fill]
801 struct sigcontext sf_sc;
806 unsigned int sc_regmask; [Unused]
807 unsigned int sc_status;
808 unsigned long long sc_pc;
809 unsigned long long sc_regs[32];
810 unsigned long long sc_fpregs[32];
811 unsigned int sc_ownedfp;
812 unsigned int sc_fpc_csr;
813 unsigned int sc_fpc_eir; [Unused]
814 unsigned int sc_used_math;
815 unsigned int sc_ssflags; [Unused]
816 [Alignment hole of four bytes]
817 unsigned long long sc_mdhi;
818 unsigned long long sc_mdlo;
820 unsigned int sc_cause; [Unused]
821 unsigned int sc_badvaddr; [Unused]
823 unsigned long sc_sigset[4]; [kernel's sigset_t]
826 The RT signal frames look like this:
829 u32 rs_ass[4]; [argument save space for o32]
830 u32 rs_code[2] [signal trampoline or fill]
831 struct siginfo rs_info;
832 struct ucontext rs_uc;
836 unsigned long uc_flags;
837 struct ucontext *uc_link;
839 [Alignment hole of four bytes]
840 struct sigcontext uc_mcontext;
845 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
847 #define RTSIGFRAME_SIGINFO_SIZE 128
848 #define STACK_T_SIZE (3 * 4)
849 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
850 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
851 + RTSIGFRAME_SIGINFO_SIZE \
852 + UCONTEXT_SIGCONTEXT_OFFSET)
854 #define SIGCONTEXT_PC (1 * 8)
855 #define SIGCONTEXT_REGS (2 * 8)
856 #define SIGCONTEXT_FPREGS (34 * 8)
857 #define SIGCONTEXT_FPCSR (66 * 8 + 4)
858 #define SIGCONTEXT_HI (69 * 8)
859 #define SIGCONTEXT_LO (70 * 8)
860 #define SIGCONTEXT_CAUSE (71 * 8 + 0)
861 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
863 #define SIGCONTEXT_REG_SIZE 8
866 mips_linux_o32_sigframe_init (const struct tramp_frame *self,
867 struct frame_info *this_frame,
868 struct trad_frame_cache *this_cache,
871 struct gdbarch *gdbarch = get_frame_arch (this_frame);
872 int ireg, reg_position;
873 CORE_ADDR frame_sp = get_frame_sp (this_frame);
874 CORE_ADDR sigcontext_base;
875 const struct mips_regnum *regs = mips_regnum (gdbarch);
878 if (self == &mips_linux_o32_sigframe)
879 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
881 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
883 /* I'm not proud of this hack. Eventually we will have the
884 infrastructure to indicate the size of saved registers on a
885 per-frame basis, but right now we don't; the kernel saves eight
886 bytes but we only want four. Use regs_base to access any
888 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
889 regs_base = sigcontext_base + 4;
891 regs_base = sigcontext_base;
893 if (mips_linux_restart_reg_p (gdbarch))
894 trad_frame_set_reg_addr (this_cache,
896 + gdbarch_num_regs (gdbarch)),
897 regs_base + SIGCONTEXT_REGS);
899 for (ireg = 1; ireg < 32; ireg++)
900 trad_frame_set_reg_addr (this_cache,
901 ireg + MIPS_ZERO_REGNUM
902 + gdbarch_num_regs (gdbarch),
903 regs_base + SIGCONTEXT_REGS
904 + ireg * SIGCONTEXT_REG_SIZE);
906 /* The way that floating point registers are saved, unfortunately,
907 depends on the architecture the kernel is built for. For the r3000 and
908 tx39, four bytes of each register are at the beginning of each of the
909 32 eight byte slots. For everything else, the registers are saved
910 using double precision; only the even-numbered slots are initialized,
911 and the high bits are the odd-numbered register. Assume the latter
912 layout, since we can't tell, and it's much more common. Which bits are
913 the "high" bits depends on endianness. */
914 for (ireg = 0; ireg < 32; ireg++)
915 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
916 trad_frame_set_reg_addr (this_cache,
918 gdbarch_num_regs (gdbarch),
919 sigcontext_base + SIGCONTEXT_FPREGS + 4
920 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
922 trad_frame_set_reg_addr (this_cache,
924 + gdbarch_num_regs (gdbarch),
925 sigcontext_base + SIGCONTEXT_FPREGS
926 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
928 trad_frame_set_reg_addr (this_cache,
929 regs->pc + gdbarch_num_regs (gdbarch),
930 regs_base + SIGCONTEXT_PC);
932 trad_frame_set_reg_addr (this_cache,
933 regs->fp_control_status
934 + gdbarch_num_regs (gdbarch),
935 sigcontext_base + SIGCONTEXT_FPCSR);
936 trad_frame_set_reg_addr (this_cache,
937 regs->hi + gdbarch_num_regs (gdbarch),
938 regs_base + SIGCONTEXT_HI);
939 trad_frame_set_reg_addr (this_cache,
940 regs->lo + gdbarch_num_regs (gdbarch),
941 regs_base + SIGCONTEXT_LO);
942 trad_frame_set_reg_addr (this_cache,
943 regs->cause + gdbarch_num_regs (gdbarch),
944 sigcontext_base + SIGCONTEXT_CAUSE);
945 trad_frame_set_reg_addr (this_cache,
946 regs->badvaddr + gdbarch_num_regs (gdbarch),
947 sigcontext_base + SIGCONTEXT_BADVADDR);
949 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
950 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
954 /* For N32/N64 things look different. There is no non-rt signal frame.
956 struct rt_sigframe_n32 {
957 u32 rs_ass[4]; [ argument save space for o32 ]
958 u32 rs_code[2]; [ signal trampoline or fill ]
959 struct siginfo rs_info;
960 struct ucontextn32 rs_uc;
967 struct sigcontext uc_mcontext;
968 sigset_t uc_sigmask; [ mask last for extensibility ]
972 u32 rs_ass[4]; [ argument save space for o32 ]
973 u32 rs_code[2]; [ signal trampoline ]
974 struct siginfo rs_info;
975 struct ucontext rs_uc;
979 unsigned long uc_flags;
980 struct ucontext *uc_link;
982 struct sigcontext uc_mcontext;
983 sigset_t uc_sigmask; [ mask last for extensibility ]
986 And the sigcontext is different (this is for both n32 and n64):
989 unsigned long long sc_regs[32];
990 unsigned long long sc_fpregs[32];
991 unsigned long long sc_mdhi;
992 unsigned long long sc_hi1;
993 unsigned long long sc_hi2;
994 unsigned long long sc_hi3;
995 unsigned long long sc_mdlo;
996 unsigned long long sc_lo1;
997 unsigned long long sc_lo2;
998 unsigned long long sc_lo3;
999 unsigned long long sc_pc;
1000 unsigned int sc_fpc_csr;
1001 unsigned int sc_used_math;
1002 unsigned int sc_dsp;
1003 unsigned int sc_reserved;
1006 That is the post-2.6.12 definition of the 64-bit sigcontext; before
1007 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
1011 #define N32_STACK_T_SIZE STACK_T_SIZE
1012 #define N64_STACK_T_SIZE (2 * 8 + 4)
1013 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1014 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1015 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1016 + RTSIGFRAME_SIGINFO_SIZE \
1017 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1018 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1019 + RTSIGFRAME_SIGINFO_SIZE \
1020 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1022 #define N64_SIGCONTEXT_REGS (0 * 8)
1023 #define N64_SIGCONTEXT_FPREGS (32 * 8)
1024 #define N64_SIGCONTEXT_HI (64 * 8)
1025 #define N64_SIGCONTEXT_LO (68 * 8)
1026 #define N64_SIGCONTEXT_PC (72 * 8)
1027 #define N64_SIGCONTEXT_FPCSR (73 * 8)
1029 #define N64_SIGCONTEXT_REG_SIZE 8
1032 mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
1033 struct frame_info *this_frame,
1034 struct trad_frame_cache *this_cache,
1037 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1038 int ireg, reg_position;
1039 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1040 CORE_ADDR sigcontext_base;
1041 const struct mips_regnum *regs = mips_regnum (gdbarch);
1043 if (self == &mips_linux_n32_rt_sigframe)
1044 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
1046 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
1048 if (mips_linux_restart_reg_p (gdbarch))
1049 trad_frame_set_reg_addr (this_cache,
1050 (MIPS_RESTART_REGNUM
1051 + gdbarch_num_regs (gdbarch)),
1052 sigcontext_base + N64_SIGCONTEXT_REGS);
1054 for (ireg = 1; ireg < 32; ireg++)
1055 trad_frame_set_reg_addr (this_cache,
1056 ireg + MIPS_ZERO_REGNUM
1057 + gdbarch_num_regs (gdbarch),
1058 sigcontext_base + N64_SIGCONTEXT_REGS
1059 + ireg * N64_SIGCONTEXT_REG_SIZE);
1061 for (ireg = 0; ireg < 32; ireg++)
1062 trad_frame_set_reg_addr (this_cache,
1064 + gdbarch_num_regs (gdbarch),
1065 sigcontext_base + N64_SIGCONTEXT_FPREGS
1066 + ireg * N64_SIGCONTEXT_REG_SIZE);
1068 trad_frame_set_reg_addr (this_cache,
1069 regs->pc + gdbarch_num_regs (gdbarch),
1070 sigcontext_base + N64_SIGCONTEXT_PC);
1072 trad_frame_set_reg_addr (this_cache,
1073 regs->fp_control_status
1074 + gdbarch_num_regs (gdbarch),
1075 sigcontext_base + N64_SIGCONTEXT_FPCSR);
1076 trad_frame_set_reg_addr (this_cache,
1077 regs->hi + gdbarch_num_regs (gdbarch),
1078 sigcontext_base + N64_SIGCONTEXT_HI);
1079 trad_frame_set_reg_addr (this_cache,
1080 regs->lo + gdbarch_num_regs (gdbarch),
1081 sigcontext_base + N64_SIGCONTEXT_LO);
1083 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1084 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
1088 mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
1090 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1091 regcache_cooked_write_unsigned (regcache, gdbarch_pc_regnum (gdbarch), pc);
1093 /* Clear the syscall restart flag. */
1094 if (mips_linux_restart_reg_p (gdbarch))
1095 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
1098 /* Return 1 if MIPS_RESTART_REGNUM is usable. */
1101 mips_linux_restart_reg_p (struct gdbarch *gdbarch)
1103 /* If we do not have a target description with registers, then
1104 MIPS_RESTART_REGNUM will not be included in the register set. */
1105 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
1108 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
1109 either be GPR-sized or missing. */
1110 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
1113 /* When FRAME is at a syscall instruction, return the PC of the next
1114 instruction to be executed. */
1117 mips_linux_syscall_next_pc (struct frame_info *frame)
1119 CORE_ADDR pc = get_frame_pc (frame);
1120 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
1122 /* If we are about to make a sigreturn syscall, use the unwinder to
1123 decode the signal frame. */
1124 if (v0 == MIPS_NR_sigreturn
1125 || v0 == MIPS_NR_rt_sigreturn
1126 || v0 == MIPS_NR_N64_rt_sigreturn
1127 || v0 == MIPS_NR_N32_rt_sigreturn)
1128 return frame_unwind_caller_pc (get_current_frame ());
1133 /* Initialize one of the GNU/Linux OS ABIs. */
1136 mips_linux_init_abi (struct gdbarch_info info,
1137 struct gdbarch *gdbarch)
1139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1140 enum mips_abi abi = mips_abi (gdbarch);
1141 struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info;
1146 set_gdbarch_get_longjmp_target (gdbarch,
1147 mips_linux_get_longjmp_target);
1148 set_solib_svr4_fetch_link_map_offsets
1149 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
1150 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1151 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
1154 set_gdbarch_get_longjmp_target (gdbarch,
1155 mips_linux_get_longjmp_target);
1156 set_solib_svr4_fetch_link_map_offsets
1157 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
1158 set_gdbarch_long_double_bit (gdbarch, 128);
1159 /* These floatformats should probably be renamed. MIPS uses
1160 the same 128-bit IEEE floating point format that IA-64 uses,
1161 except that the quiet/signalling NaN bit is reversed (GDB
1162 does not distinguish between quiet and signalling NaNs). */
1163 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
1164 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
1167 set_gdbarch_get_longjmp_target (gdbarch,
1168 mips64_linux_get_longjmp_target);
1169 set_solib_svr4_fetch_link_map_offsets
1170 (gdbarch, svr4_lp64_fetch_link_map_offsets);
1171 set_gdbarch_long_double_bit (gdbarch, 128);
1172 /* These floatformats should probably be renamed. MIPS uses
1173 the same 128-bit IEEE floating point format that IA-64 uses,
1174 except that the quiet/signalling NaN bit is reversed (GDB
1175 does not distinguish between quiet and signalling NaNs). */
1176 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
1177 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
1183 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1185 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
1187 /* Enable TLS support. */
1188 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1189 svr4_fetch_objfile_link_map);
1191 /* Initialize this lazily, to avoid an initialization order
1192 dependency on solib-svr4.c's _initialize routine. */
1193 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
1195 mips_svr4_so_ops = svr4_so_ops;
1196 mips_svr4_so_ops.in_dynsym_resolve_code
1197 = mips_linux_in_dynsym_resolve_code;
1199 set_solib_ops (gdbarch, &mips_svr4_so_ops);
1201 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
1203 set_gdbarch_core_read_description (gdbarch,
1204 mips_linux_core_read_description);
1206 tdep->syscall_next_pc = mips_linux_syscall_next_pc;
1210 const struct tdesc_feature *feature;
1212 /* If we have target-described registers, then we can safely
1213 reserve a number for MIPS_RESTART_REGNUM (whether it is
1214 described or not). */
1215 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
1216 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
1218 /* If it's present, then assign it to the reserved number. */
1219 feature = tdesc_find_feature (info.target_desc,
1220 "org.gnu.gdb.mips.linux");
1221 if (feature != NULL)
1222 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
1227 /* Provide a prototype to silence -Wmissing-prototypes. */
1228 extern initialize_file_ftype _initialize_mips_linux_tdep;
1231 _initialize_mips_linux_tdep (void)
1233 const struct bfd_arch_info *arch_info;
1235 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1237 arch_info = arch_info->next)
1239 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1241 mips_linux_init_abi);
1244 deprecated_add_core_fns (®set_core_fns);