1 /* Native-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb_assert.h"
25 #include "mips-tdep.h"
28 #include "linux-nat.h"
29 #include "mips-linux-tdep.h"
30 #include "target-descriptions.h"
32 #include "gdb_proc_service.h"
36 #include <sys/ptrace.h>
37 #include <asm/ptrace.h>
39 #include "features/mips-linux.c"
40 #include "features/mips-dsp-linux.c"
41 #include "features/mips64-linux.c"
42 #include "features/mips64-dsp-linux.c"
44 #ifndef PTRACE_GET_THREAD_AREA
45 #define PTRACE_GET_THREAD_AREA 25
48 /* Assume that we have PTRACE_GETREGS et al. support. If we do not,
49 we'll clear this and use PTRACE_PEEKUSER instead. */
50 static int have_ptrace_regsets = 1;
52 /* Whether or not to print the mirrored debug registers. */
54 static int maint_show_dr;
56 /* Saved function pointers to fetch and store a single register using
57 PTRACE_PEEKUSER and PTRACE_POKEUSER. */
59 static void (*super_fetch_registers) (struct target_ops *,
60 struct regcache *, int);
61 static void (*super_store_registers) (struct target_ops *,
62 struct regcache *, int);
64 static void (*super_close) (void);
66 /* Map gdb internal register number to ptrace ``address''.
67 These ``addresses'' are normally defined in <asm/ptrace.h>.
69 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
70 and there's no point in reading or setting MIPS_ZERO_REGNUM.
71 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
74 mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
78 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
79 error (_("Bogon register number %d."), regno);
81 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
83 else if ((regno >= mips_regnum (gdbarch)->fp0)
84 && (regno < mips_regnum (gdbarch)->fp0 + 32))
85 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
86 else if (regno == mips_regnum (gdbarch)->pc)
88 else if (regno == mips_regnum (gdbarch)->cause)
89 regaddr = store? (CORE_ADDR) -1 : CAUSE;
90 else if (regno == mips_regnum (gdbarch)->badvaddr)
91 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
92 else if (regno == mips_regnum (gdbarch)->lo)
94 else if (regno == mips_regnum (gdbarch)->hi)
96 else if (regno == mips_regnum (gdbarch)->fp_control_status)
98 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
99 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
100 else if (mips_regnum (gdbarch)->dspacc != -1
101 && regno >= mips_regnum (gdbarch)->dspacc
102 && regno < mips_regnum (gdbarch)->dspacc + 6)
103 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
104 else if (regno == mips_regnum (gdbarch)->dspctl)
105 regaddr = DSP_CONTROL;
106 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
109 regaddr = (CORE_ADDR) -1;
115 mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
119 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
120 error (_("Bogon register number %d."), regno);
122 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
124 else if ((regno >= mips_regnum (gdbarch)->fp0)
125 && (regno < mips_regnum (gdbarch)->fp0 + 32))
126 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
127 else if (regno == mips_regnum (gdbarch)->pc)
129 else if (regno == mips_regnum (gdbarch)->cause)
130 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
131 else if (regno == mips_regnum (gdbarch)->badvaddr)
132 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
133 else if (regno == mips_regnum (gdbarch)->lo)
134 regaddr = MIPS64_MMLO;
135 else if (regno == mips_regnum (gdbarch)->hi)
136 regaddr = MIPS64_MMHI;
137 else if (regno == mips_regnum (gdbarch)->fp_control_status)
138 regaddr = MIPS64_FPC_CSR;
139 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
140 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
141 else if (mips_regnum (gdbarch)->dspacc != -1
142 && regno >= mips_regnum (gdbarch)->dspacc
143 && regno < mips_regnum (gdbarch)->dspacc + 6)
144 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
145 else if (regno == mips_regnum (gdbarch)->dspctl)
146 regaddr = DSP_CONTROL;
147 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
150 regaddr = (CORE_ADDR) -1;
155 /* Fetch the thread-local storage pointer for libthread_db. */
158 ps_get_thread_area (const struct ps_prochandle *ph,
159 lwpid_t lwpid, int idx, void **base)
161 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
164 /* IDX is the bias from the thread pointer to the beginning of the
165 thread descriptor. It has to be subtracted due to implementation
166 quirks in libthread_db. */
167 *base = (void *) ((char *)*base - idx);
172 /* Wrapper functions. These are only used by libthread_db. */
175 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
177 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
178 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
180 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
184 fill_gregset (const struct regcache *regcache,
185 gdb_gregset_t *gregsetp, int regno)
187 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
188 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
190 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
194 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
196 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
197 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
199 mips64_supply_fpregset (regcache,
200 (const mips64_elf_fpregset_t *) fpregsetp);
204 fill_fpregset (const struct regcache *regcache,
205 gdb_fpregset_t *fpregsetp, int regno)
207 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
208 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
210 mips64_fill_fpregset (regcache,
211 (mips64_elf_fpregset_t *) fpregsetp, regno);
215 /* Fetch REGNO (or all registers if REGNO == -1) from the target
216 using PTRACE_GETREGS et al. */
219 mips64_linux_regsets_fetch_registers (struct target_ops *ops,
220 struct regcache *regcache, int regno)
222 struct gdbarch *gdbarch = get_regcache_arch (regcache);
228 if (regno >= mips_regnum (gdbarch)->fp0
229 && regno <= mips_regnum (gdbarch)->fp0 + 32)
231 else if (regno == mips_regnum (gdbarch)->fp_control_status)
233 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
238 /* DSP registers are optional and not a part of any set. */
239 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
242 else if (regno >= mips_regnum (gdbarch)->dspacc
243 && regno < mips_regnum (gdbarch)->dspacc + 6)
245 else if (regno == mips_regnum (gdbarch)->dspctl)
250 tid = ptid_get_lwp (inferior_ptid);
252 tid = ptid_get_pid (inferior_ptid);
254 if (regno == -1 || (!is_fp && !is_dsp))
256 mips64_elf_gregset_t regs;
258 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
262 have_ptrace_regsets = 0;
265 perror_with_name (_("Couldn't get registers"));
268 mips64_supply_gregset (regcache,
269 (const mips64_elf_gregset_t *) ®s);
272 if (regno == -1 || is_fp)
274 mips64_elf_fpregset_t fp_regs;
276 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
277 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
281 have_ptrace_regsets = 0;
284 perror_with_name (_("Couldn't get FP registers"));
287 mips64_supply_fpregset (regcache,
288 (const mips64_elf_fpregset_t *) &fp_regs);
292 super_fetch_registers (ops, regcache, regno);
293 else if (regno == -1 && have_dsp)
295 for (regi = mips_regnum (gdbarch)->dspacc;
296 regi < mips_regnum (gdbarch)->dspacc + 6;
298 super_fetch_registers (ops, regcache, regi);
299 super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
303 /* Store REGNO (or all registers if REGNO == -1) to the target
304 using PTRACE_SETREGS et al. */
307 mips64_linux_regsets_store_registers (struct target_ops *ops,
308 struct regcache *regcache, int regno)
310 struct gdbarch *gdbarch = get_regcache_arch (regcache);
316 if (regno >= mips_regnum (gdbarch)->fp0
317 && regno <= mips_regnum (gdbarch)->fp0 + 32)
319 else if (regno == mips_regnum (gdbarch)->fp_control_status)
321 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
326 /* DSP registers are optional and not a part of any set. */
327 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
330 else if (regno >= mips_regnum (gdbarch)->dspacc
331 && regno < mips_regnum (gdbarch)->dspacc + 6)
333 else if (regno == mips_regnum (gdbarch)->dspctl)
338 tid = ptid_get_lwp (inferior_ptid);
340 tid = ptid_get_pid (inferior_ptid);
342 if (regno == -1 || (!is_fp && !is_dsp))
344 mips64_elf_gregset_t regs;
346 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
347 perror_with_name (_("Couldn't get registers"));
349 mips64_fill_gregset (regcache, ®s, regno);
351 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
352 perror_with_name (_("Couldn't set registers"));
355 if (regno == -1 || is_fp)
357 mips64_elf_fpregset_t fp_regs;
359 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
360 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
361 perror_with_name (_("Couldn't get FP registers"));
363 mips64_fill_fpregset (regcache, &fp_regs, regno);
365 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
366 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
367 perror_with_name (_("Couldn't set FP registers"));
371 super_store_registers (ops, regcache, regno);
372 else if (regno == -1 && have_dsp)
374 for (regi = mips_regnum (gdbarch)->dspacc;
375 regi < mips_regnum (gdbarch)->dspacc + 6;
377 super_store_registers (ops, regcache, regi);
378 super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
382 /* Fetch REGNO (or all registers if REGNO == -1) from the target
383 using any working method. */
386 mips64_linux_fetch_registers (struct target_ops *ops,
387 struct regcache *regcache, int regnum)
389 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
390 if (have_ptrace_regsets)
391 mips64_linux_regsets_fetch_registers (ops, regcache, regnum);
393 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
394 back to PTRACE_PEEKUSER. */
395 if (!have_ptrace_regsets)
396 super_fetch_registers (ops, regcache, regnum);
399 /* Store REGNO (or all registers if REGNO == -1) to the target
400 using any working method. */
403 mips64_linux_store_registers (struct target_ops *ops,
404 struct regcache *regcache, int regnum)
406 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
407 if (have_ptrace_regsets)
408 mips64_linux_regsets_store_registers (ops, regcache, regnum);
410 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
411 back to PTRACE_PEEKUSER. */
412 if (!have_ptrace_regsets)
413 super_store_registers (ops, regcache, regnum);
416 /* Return the address in the core dump or inferior of register
420 mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p)
422 if (mips_abi_regsize (gdbarch) == 8)
423 return mips64_linux_register_addr (gdbarch, regno, store_p);
425 return mips_linux_register_addr (gdbarch, regno, store_p);
428 static const struct target_desc *
429 mips_linux_read_description (struct target_ops *ops)
431 static int have_dsp = -1;
437 tid = ptid_get_lwp (inferior_ptid);
439 tid = ptid_get_pid (inferior_ptid);
441 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
451 perror_with_name (_("Couldn't check DSP support"));
456 /* Report that target registers are a size we know for sure
457 that we can get from ptrace. */
458 if (_MIPS_SIM == _ABIO32)
459 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
461 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
464 #define MAX_DEBUG_REGISTER 8
466 /* If macro PTRACE_GET_WATCH_REGS is not defined, kernel header doesn't
467 have hardware watchpoint-related structures. Define them below. */
469 #ifndef PTRACE_GET_WATCH_REGS
470 # define PTRACE_GET_WATCH_REGS 0xd0
471 # define PTRACE_SET_WATCH_REGS 0xd1
473 enum pt_watch_style {
474 pt_watch_style_mips32,
475 pt_watch_style_mips64
478 /* A value of zero in a watchlo indicates that it is available. */
480 struct mips32_watch_regs
482 uint32_t watchlo[MAX_DEBUG_REGISTER];
483 /* Lower 16 bits of watchhi. */
484 uint16_t watchhi[MAX_DEBUG_REGISTER];
485 /* Valid mask and I R W bits.
486 * bit 0 -- 1 if W bit is usable.
487 * bit 1 -- 1 if R bit is usable.
488 * bit 2 -- 1 if I bit is usable.
489 * bits 3 - 11 -- Valid watchhi mask bits.
491 uint16_t watch_masks[MAX_DEBUG_REGISTER];
492 /* The number of valid watch register pairs. */
494 /* There is confusion across gcc versions about structure alignment,
495 so we force 8 byte alignment for these structures so they match
496 the kernel even if it was build with a different gcc version. */
497 } __attribute__ ((aligned (8)));
499 struct mips64_watch_regs
501 uint64_t watchlo[MAX_DEBUG_REGISTER];
502 uint16_t watchhi[MAX_DEBUG_REGISTER];
503 uint16_t watch_masks[MAX_DEBUG_REGISTER];
505 } __attribute__ ((aligned (8)));
509 enum pt_watch_style style;
512 struct mips32_watch_regs mips32;
513 struct mips64_watch_regs mips64;
517 #endif /* !PTRACE_GET_WATCH_REGS */
523 #define W_MASK (1 << W_BIT)
524 #define R_MASK (1 << R_BIT)
525 #define I_MASK (1 << I_BIT)
527 #define IRW_MASK (I_MASK | R_MASK | W_MASK)
529 /* -1 if the kernel and/or CPU do not support watch registers.
530 1 if watch_readback is valid and we can read style, num_valid
532 0 if we need to read the watch_readback. */
534 static int watch_readback_valid;
536 /* Cached watch register read values. */
538 static struct pt_watch_regs watch_readback;
540 /* We keep list of all watchpoints we should install and calculate the
541 watch register values each time the list changes. This allows for
542 easy sharing of watch registers for more than one watchpoint. */
544 struct mips_watchpoint
549 struct mips_watchpoint *next;
552 static struct mips_watchpoint *current_watches;
554 /* The current set of watch register values for writing the
557 static struct pt_watch_regs watch_mirror;
559 /* Assuming usable watch registers, return the irw_mask. */
562 get_irw_mask (struct pt_watch_regs *regs, int set)
566 case pt_watch_style_mips32:
567 return regs->mips32.watch_masks[set] & IRW_MASK;
568 case pt_watch_style_mips64:
569 return regs->mips64.watch_masks[set] & IRW_MASK;
571 internal_error (__FILE__, __LINE__,
572 _("Unrecognized watch register style"));
576 /* Assuming usable watch registers, return the reg_mask. */
579 get_reg_mask (struct pt_watch_regs *regs, int set)
583 case pt_watch_style_mips32:
584 return regs->mips32.watch_masks[set] & ~IRW_MASK;
585 case pt_watch_style_mips64:
586 return regs->mips64.watch_masks[set] & ~IRW_MASK;
588 internal_error (__FILE__, __LINE__,
589 _("Unrecognized watch register style"));
593 /* Assuming usable watch registers, return the num_valid. */
596 get_num_valid (struct pt_watch_regs *regs)
600 case pt_watch_style_mips32:
601 return regs->mips32.num_valid;
602 case pt_watch_style_mips64:
603 return regs->mips64.num_valid;
605 internal_error (__FILE__, __LINE__,
606 _("Unrecognized watch register style"));
610 /* Assuming usable watch registers, return the watchlo. */
613 get_watchlo (struct pt_watch_regs *regs, int set)
617 case pt_watch_style_mips32:
618 return regs->mips32.watchlo[set];
619 case pt_watch_style_mips64:
620 return regs->mips64.watchlo[set];
622 internal_error (__FILE__, __LINE__,
623 _("Unrecognized watch register style"));
627 /* Assuming usable watch registers, set a watchlo value. */
630 set_watchlo (struct pt_watch_regs *regs, int set, CORE_ADDR value)
634 case pt_watch_style_mips32:
635 /* The cast will never throw away bits as 64 bit addresses can
636 never be used on a 32 bit kernel. */
637 regs->mips32.watchlo[set] = (uint32_t)value;
639 case pt_watch_style_mips64:
640 regs->mips64.watchlo[set] = value;
643 internal_error (__FILE__, __LINE__,
644 _("Unrecognized watch register style"));
648 /* Assuming usable watch registers, return the watchhi. */
651 get_watchhi (struct pt_watch_regs *regs, int n)
655 case pt_watch_style_mips32:
656 return regs->mips32.watchhi[n];
657 case pt_watch_style_mips64:
658 return regs->mips64.watchhi[n];
660 internal_error (__FILE__, __LINE__,
661 _("Unrecognized watch register style"));
665 /* Assuming usable watch registers, set a watchhi value. */
668 set_watchhi (struct pt_watch_regs *regs, int n, uint16_t value)
672 case pt_watch_style_mips32:
673 regs->mips32.watchhi[n] = value;
675 case pt_watch_style_mips64:
676 regs->mips64.watchhi[n] = value;
679 internal_error (__FILE__, __LINE__,
680 _("Unrecognized watch register style"));
685 mips_show_dr (const char *func, CORE_ADDR addr,
686 int len, enum target_hw_bp_type type)
690 puts_unfiltered (func);
692 printf_unfiltered (" (addr=%s, len=%d, type=%s)",
693 paddress (target_gdbarch (), addr), len,
694 type == hw_write ? "data-write"
695 : (type == hw_read ? "data-read"
696 : (type == hw_access ? "data-read/write"
697 : (type == hw_execute ? "instruction-execute"
699 puts_unfiltered (":\n");
701 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
702 printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
703 paddress (target_gdbarch (),
704 get_watchlo (&watch_mirror, i)),
705 paddress (target_gdbarch (),
706 get_watchhi (&watch_mirror, i)));
709 /* Return 1 if watch registers are usable. Cached information is used
710 unless force is true. */
713 mips_linux_read_watch_registers (int force)
717 if (force || watch_readback_valid == 0)
719 tid = ptid_get_lwp (inferior_ptid);
720 if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1)
722 watch_readback_valid = -1;
725 switch (watch_readback.style)
727 case pt_watch_style_mips32:
728 if (watch_readback.mips32.num_valid == 0)
730 watch_readback_valid = -1;
734 case pt_watch_style_mips64:
735 if (watch_readback.mips64.num_valid == 0)
737 watch_readback_valid = -1;
742 watch_readback_valid = -1;
745 /* Watch registers appear to be usable. */
746 watch_readback_valid = 1;
748 return (watch_readback_valid == 1) ? 1 : 0;
751 /* Convert GDB's type to an IRW mask. */
754 type_to_irw (int type)
763 return (W_MASK | R_MASK);
769 /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
770 handle the specified watch type. */
773 mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
776 uint32_t wanted_mask, irw_mask;
778 if (!mips_linux_read_watch_registers (0))
783 case bp_hardware_watchpoint:
784 wanted_mask = W_MASK;
786 case bp_read_watchpoint:
787 wanted_mask = R_MASK;
789 case bp_access_watchpoint:
790 wanted_mask = R_MASK | W_MASK;
796 for (i = 0; i < get_num_valid (&watch_readback) && cnt; i++)
798 irw_mask = get_irw_mask (&watch_readback, i);
799 if ((irw_mask & wanted_mask) == wanted_mask)
802 return (cnt == 0) ? 1 : 0;
805 /* Target to_stopped_by_watchpoint implementation. Return 1 if
806 stopped by watchpoint. The watchhi R and W bits indicate the watch
807 register triggered. */
810 mips_linux_stopped_by_watchpoint (void)
815 if (!mips_linux_read_watch_registers (1))
818 num_valid = get_num_valid (&watch_readback);
820 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
821 if (get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
827 /* Target to_stopped_data_address implementation. Set the address
828 where the watch triggered (if known). Return 1 if the address was
832 mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr)
834 /* On mips we don't know the low order 3 bits of the data address,
835 so we must return false. */
839 /* Set any low order bits in mask that are not set. */
842 fill_mask (CORE_ADDR mask)
845 while (f && f < mask)
853 /* Try to add a single watch to the specified registers. Return 1 on
854 success, 0 on failure. */
857 try_one_watch (struct pt_watch_regs *regs, CORE_ADDR addr,
858 int len, unsigned irw)
860 CORE_ADDR base_addr, last_byte, break_addr, segment_len;
861 CORE_ADDR mask_bits, t_low, t_low_end;
864 struct pt_watch_regs regs_copy;
869 last_byte = addr + len - 1;
870 mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK;
871 base_addr = addr & ~mask_bits;
873 /* Check to see if it is covered by current registers. */
874 for (i = 0; i < get_num_valid (regs); i++)
876 t_low = get_watchlo (regs, i);
877 if (t_low != 0 && irw == ((unsigned)t_low & irw))
879 t_hi = get_watchhi (regs, i) | IRW_MASK;
880 t_low &= ~(CORE_ADDR)t_hi;
881 if (addr >= t_low && last_byte <= (t_low + t_hi))
885 /* Try to find an empty register. */
887 for (i = 0; i < get_num_valid (regs); i++)
889 t_low = get_watchlo (regs, i);
890 if (t_low == 0 && irw == (get_irw_mask (regs, i) & irw))
892 if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK))
894 /* It fits, we'll take it. */
895 set_watchlo (regs, i, base_addr | irw);
896 set_watchhi (regs, i, mask_bits & ~IRW_MASK);
901 /* It doesn't fit, but has the proper IRW capabilities. */
906 if (free_watches > 1)
908 /* Try to split it across several registers. */
910 for (i = 0; i < get_num_valid (®s_copy); i++)
912 t_low = get_watchlo (®s_copy, i);
913 t_hi = get_reg_mask (®s_copy, i) | IRW_MASK;
914 if (t_low == 0 && irw == (t_hi & irw))
916 t_low = addr & ~(CORE_ADDR)t_hi;
917 break_addr = t_low + t_hi + 1;
918 if (break_addr >= addr + len)
921 segment_len = break_addr - addr;
922 mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
923 set_watchlo (®s_copy, i, (addr & ~mask_bits) | irw);
924 set_watchhi (®s_copy, i, mask_bits & ~IRW_MASK);
925 if (break_addr >= addr + len)
930 len = addr + len - break_addr;
935 /* It didn't fit anywhere, we failed. */
939 /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
940 the specified region can be covered by the watch registers. */
943 mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
945 struct pt_watch_regs dummy_regs;
948 if (!mips_linux_read_watch_registers (0))
951 dummy_regs = watch_readback;
952 /* Clear them out. */
953 for (i = 0; i < get_num_valid (&dummy_regs); i++)
954 set_watchlo (&dummy_regs, i, 0);
955 return try_one_watch (&dummy_regs, addr, len, 0);
959 /* Write the mirrored watch register values for each thread. */
962 write_watchpoint_regs (void)
969 tid = ptid_get_lwp (lp->ptid);
970 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1)
971 perror_with_name (_("Couldn't write debug register"));
976 /* linux_nat new_thread implementation. Write the mirrored watch
977 register values for the new thread. */
980 mips_linux_new_thread (struct lwp_info *lp)
984 if (!mips_linux_read_watch_registers (0))
987 tid = ptid_get_lwp (lp->ptid);
988 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1)
989 perror_with_name (_("Couldn't write debug register"));
992 /* Fill in the watch registers with the currently cached watches. */
995 populate_regs_from_watches (struct pt_watch_regs *regs)
997 struct mips_watchpoint *w;
1000 /* Clear them out. */
1001 for (i = 0; i < get_num_valid (regs); i++)
1003 set_watchlo (regs, i, 0);
1004 set_watchhi (regs, i, 0);
1007 w = current_watches;
1010 i = try_one_watch (regs, w->addr, w->len, type_to_irw (w->type));
1011 /* They must all fit, because we previously calculated that they
1018 /* Target to_insert_watchpoint implementation. Try to insert a new
1019 watch. Return zero on success. */
1022 mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type,
1023 struct expression *cond)
1025 struct pt_watch_regs regs;
1026 struct mips_watchpoint *new_watch;
1027 struct mips_watchpoint **pw;
1032 if (!mips_linux_read_watch_registers (0))
1038 regs = watch_readback;
1039 /* Add the current watches. */
1040 populate_regs_from_watches (®s);
1042 /* Now try to add the new watch. */
1043 if (!try_one_watch (®s, addr, len, type_to_irw (type)))
1046 /* It fit. Stick it on the end of the list. */
1047 new_watch = (struct mips_watchpoint *)
1048 xmalloc (sizeof (struct mips_watchpoint));
1049 new_watch->addr = addr;
1050 new_watch->len = len;
1051 new_watch->type = type;
1052 new_watch->next = NULL;
1054 pw = ¤t_watches;
1059 watch_mirror = regs;
1060 retval = write_watchpoint_regs ();
1063 mips_show_dr ("insert_watchpoint", addr, len, type);
1068 /* Target to_remove_watchpoint implementation. Try to remove a watch.
1069 Return zero on success. */
1072 mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
1073 struct expression *cond)
1078 struct mips_watchpoint **pw;
1079 struct mips_watchpoint *w;
1081 /* Search for a known watch that matches. Then unlink and free
1084 pw = ¤t_watches;
1087 if (w->addr == addr && w->len == len && w->type == type)
1098 return -1; /* We don't know about it, fail doing nothing. */
1100 /* At this point watch_readback is known to be valid because we
1101 could not have added the watch without reading it. */
1102 gdb_assert (watch_readback_valid == 1);
1104 watch_mirror = watch_readback;
1105 populate_regs_from_watches (&watch_mirror);
1107 retval = write_watchpoint_regs ();
1110 mips_show_dr ("remove_watchpoint", addr, len, type);
1115 /* Target to_close implementation. Free any watches and call the
1116 super implementation. */
1119 mips_linux_close (void)
1121 struct mips_watchpoint *w;
1122 struct mips_watchpoint *nw;
1124 /* Clean out the current_watches list. */
1125 w = current_watches;
1132 current_watches = NULL;
1138 void _initialize_mips_linux_nat (void);
1141 _initialize_mips_linux_nat (void)
1143 struct target_ops *t;
1145 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
1146 &maint_show_dr, _("\
1147 Set whether to show variables that mirror the mips debug registers."), _("\
1148 Show whether to show variables that mirror the mips debug registers."), _("\
1149 Use \"on\" to enable, \"off\" to disable.\n\
1150 If enabled, the debug registers values are shown when GDB inserts\n\
1151 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1152 triggers a breakpoint or watchpoint."),
1155 &maintenance_set_cmdlist,
1156 &maintenance_show_cmdlist);
1158 t = linux_trad_target (mips_linux_register_u_offset);
1160 super_close = t->to_close;
1161 t->to_close = mips_linux_close;
1163 super_fetch_registers = t->to_fetch_registers;
1164 super_store_registers = t->to_store_registers;
1166 t->to_fetch_registers = mips64_linux_fetch_registers;
1167 t->to_store_registers = mips64_linux_store_registers;
1169 t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint;
1170 t->to_remove_watchpoint = mips_linux_remove_watchpoint;
1171 t->to_insert_watchpoint = mips_linux_insert_watchpoint;
1172 t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint;
1173 t->to_stopped_data_address = mips_linux_stopped_data_address;
1174 t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint;
1176 t->to_read_description = mips_linux_read_description;
1178 linux_nat_add_target (t);
1179 linux_nat_set_new_thread (t, mips_linux_new_thread);
1181 /* Initialize the standard target descriptions. */
1182 initialize_tdesc_mips_linux ();
1183 initialize_tdesc_mips_dsp_linux ();
1184 initialize_tdesc_mips64_linux ();
1185 initialize_tdesc_mips64_dsp_linux ();