1 /* Native-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_assert.h"
26 #include "mips-tdep.h"
29 #include "linux-nat.h"
30 #include "mips-linux-tdep.h"
31 #include "target-descriptions.h"
33 #include "gdb_proc_service.h"
37 #include <sys/ptrace.h>
39 #include "features/mips-linux.c"
40 #include "features/mips64-linux.c"
42 #ifndef PTRACE_GET_THREAD_AREA
43 #define PTRACE_GET_THREAD_AREA 25
46 /* Assume that we have PTRACE_GETREGS et al. support. If we do not,
47 we'll clear this and use PTRACE_PEEKUSER instead. */
48 static int have_ptrace_regsets = 1;
50 /* Whether or not to print the mirrored debug registers. */
52 static int maint_show_dr;
54 /* Saved function pointers to fetch and store a single register using
55 PTRACE_PEEKUSER and PTRACE_POKEUSER. */
57 static void (*super_fetch_registers) (struct target_ops *,
58 struct regcache *, int);
59 static void (*super_store_registers) (struct target_ops *,
60 struct regcache *, int);
62 static void (*super_close) (int);
64 /* Map gdb internal register number to ptrace ``address''.
65 These ``addresses'' are normally defined in <asm/ptrace.h>.
67 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
68 and there's no point in reading or setting MIPS_ZERO_REGNUM.
69 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
72 mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
76 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
77 error (_("Bogon register number %d."), regno);
79 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
81 else if ((regno >= mips_regnum (gdbarch)->fp0)
82 && (regno < mips_regnum (gdbarch)->fp0 + 32))
83 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
84 else if (regno == mips_regnum (gdbarch)->pc)
86 else if (regno == mips_regnum (gdbarch)->cause)
87 regaddr = store? (CORE_ADDR) -1 : CAUSE;
88 else if (regno == mips_regnum (gdbarch)->badvaddr)
89 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
90 else if (regno == mips_regnum (gdbarch)->lo)
92 else if (regno == mips_regnum (gdbarch)->hi)
94 else if (regno == mips_regnum (gdbarch)->fp_control_status)
96 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
97 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
98 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
101 regaddr = (CORE_ADDR) -1;
107 mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
111 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
112 error (_("Bogon register number %d."), regno);
114 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
116 else if ((regno >= mips_regnum (gdbarch)->fp0)
117 && (regno < mips_regnum (gdbarch)->fp0 + 32))
118 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
119 else if (regno == mips_regnum (gdbarch)->pc)
121 else if (regno == mips_regnum (gdbarch)->cause)
122 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
123 else if (regno == mips_regnum (gdbarch)->badvaddr)
124 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
125 else if (regno == mips_regnum (gdbarch)->lo)
126 regaddr = MIPS64_MMLO;
127 else if (regno == mips_regnum (gdbarch)->hi)
128 regaddr = MIPS64_MMHI;
129 else if (regno == mips_regnum (gdbarch)->fp_control_status)
130 regaddr = MIPS64_FPC_CSR;
131 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
132 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
133 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
136 regaddr = (CORE_ADDR) -1;
141 /* Fetch the thread-local storage pointer for libthread_db. */
144 ps_get_thread_area (const struct ps_prochandle *ph,
145 lwpid_t lwpid, int idx, void **base)
147 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
150 /* IDX is the bias from the thread pointer to the beginning of the
151 thread descriptor. It has to be subtracted due to implementation
152 quirks in libthread_db. */
153 *base = (void *) ((char *)*base - idx);
158 /* Wrapper functions. These are only used by libthread_db. */
161 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
163 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
164 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
166 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
170 fill_gregset (const struct regcache *regcache,
171 gdb_gregset_t *gregsetp, int regno)
173 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
174 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
176 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
180 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
182 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
183 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
185 mips64_supply_fpregset (regcache,
186 (const mips64_elf_fpregset_t *) fpregsetp);
190 fill_fpregset (const struct regcache *regcache,
191 gdb_fpregset_t *fpregsetp, int regno)
193 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
194 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
196 mips64_fill_fpregset (regcache,
197 (mips64_elf_fpregset_t *) fpregsetp, regno);
201 /* Fetch REGNO (or all registers if REGNO == -1) from the target
202 using PTRACE_GETREGS et al. */
205 mips64_linux_regsets_fetch_registers (struct regcache *regcache, int regno)
207 struct gdbarch *gdbarch = get_regcache_arch (regcache);
211 if (regno >= mips_regnum (gdbarch)->fp0
212 && regno <= mips_regnum (gdbarch)->fp0 + 32)
214 else if (regno == mips_regnum (gdbarch)->fp_control_status)
216 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
221 tid = ptid_get_lwp (inferior_ptid);
223 tid = ptid_get_pid (inferior_ptid);
225 if (regno == -1 || !is_fp)
227 mips64_elf_gregset_t regs;
229 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
233 have_ptrace_regsets = 0;
236 perror_with_name (_("Couldn't get registers"));
239 mips64_supply_gregset (regcache,
240 (const mips64_elf_gregset_t *) ®s);
243 if (regno == -1 || is_fp)
245 mips64_elf_fpregset_t fp_regs;
247 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
248 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
252 have_ptrace_regsets = 0;
255 perror_with_name (_("Couldn't get FP registers"));
258 mips64_supply_fpregset (regcache,
259 (const mips64_elf_fpregset_t *) &fp_regs);
263 /* Store REGNO (or all registers if REGNO == -1) to the target
264 using PTRACE_SETREGS et al. */
267 mips64_linux_regsets_store_registers (const struct regcache *regcache,
270 struct gdbarch *gdbarch = get_regcache_arch (regcache);
274 if (regno >= mips_regnum (gdbarch)->fp0
275 && regno <= mips_regnum (gdbarch)->fp0 + 32)
277 else if (regno == mips_regnum (gdbarch)->fp_control_status)
279 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
284 tid = ptid_get_lwp (inferior_ptid);
286 tid = ptid_get_pid (inferior_ptid);
288 if (regno == -1 || !is_fp)
290 mips64_elf_gregset_t regs;
292 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
293 perror_with_name (_("Couldn't get registers"));
295 mips64_fill_gregset (regcache, ®s, regno);
297 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
298 perror_with_name (_("Couldn't set registers"));
301 if (regno == -1 || is_fp)
303 mips64_elf_fpregset_t fp_regs;
305 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
306 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
307 perror_with_name (_("Couldn't get FP registers"));
309 mips64_fill_fpregset (regcache, &fp_regs, regno);
311 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
312 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
313 perror_with_name (_("Couldn't set FP registers"));
317 /* Fetch REGNO (or all registers if REGNO == -1) from the target
318 using any working method. */
321 mips64_linux_fetch_registers (struct target_ops *ops,
322 struct regcache *regcache, int regnum)
324 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
325 if (have_ptrace_regsets)
326 mips64_linux_regsets_fetch_registers (regcache, regnum);
328 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
329 back to PTRACE_PEEKUSER. */
330 if (!have_ptrace_regsets)
331 super_fetch_registers (ops, regcache, regnum);
334 /* Store REGNO (or all registers if REGNO == -1) to the target
335 using any working method. */
338 mips64_linux_store_registers (struct target_ops *ops,
339 struct regcache *regcache, int regnum)
341 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
342 if (have_ptrace_regsets)
343 mips64_linux_regsets_store_registers (regcache, regnum);
345 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
346 back to PTRACE_PEEKUSER. */
347 if (!have_ptrace_regsets)
348 super_store_registers (ops, regcache, regnum);
351 /* Return the address in the core dump or inferior of register
355 mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p)
357 if (mips_abi_regsize (gdbarch) == 8)
358 return mips64_linux_register_addr (gdbarch, regno, store_p);
360 return mips_linux_register_addr (gdbarch, regno, store_p);
363 static const struct target_desc *
364 mips_linux_read_description (struct target_ops *ops)
366 /* Report that target registers are a size we know for sure
367 that we can get from ptrace. */
368 if (_MIPS_SIM == _ABIO32)
369 return tdesc_mips_linux;
371 return tdesc_mips64_linux;
374 #ifndef PTRACE_GET_WATCH_REGS
375 # define PTRACE_GET_WATCH_REGS 0xd0
378 #ifndef PTRACE_SET_WATCH_REGS
379 # define PTRACE_SET_WATCH_REGS 0xd1
386 #define W_MASK (1 << W_BIT)
387 #define R_MASK (1 << R_BIT)
388 #define I_MASK (1 << I_BIT)
390 #define IRW_MASK (I_MASK | R_MASK | W_MASK)
392 enum pt_watch_style {
393 pt_watch_style_mips32,
394 pt_watch_style_mips64
397 #define MAX_DEBUG_REGISTER 8
399 /* A value of zero in a watchlo indicates that it is available. */
401 struct mips32_watch_regs
403 uint32_t watchlo[MAX_DEBUG_REGISTER];
404 /* Lower 16 bits of watchhi. */
405 uint16_t watchhi[MAX_DEBUG_REGISTER];
406 /* Valid mask and I R W bits.
407 * bit 0 -- 1 if W bit is usable.
408 * bit 1 -- 1 if R bit is usable.
409 * bit 2 -- 1 if I bit is usable.
410 * bits 3 - 11 -- Valid watchhi mask bits.
412 uint16_t watch_masks[MAX_DEBUG_REGISTER];
413 /* The number of valid watch register pairs. */
415 /* There is confusion across gcc versions about structure alignment,
416 so we force 8 byte alignment for these structures so they match
417 the kernel even if it was build with a different gcc version. */
418 } __attribute__ ((aligned (8)));
420 struct mips64_watch_regs
422 uint64_t watchlo[MAX_DEBUG_REGISTER];
423 uint16_t watchhi[MAX_DEBUG_REGISTER];
424 uint16_t watch_masks[MAX_DEBUG_REGISTER];
426 } __attribute__ ((aligned (8)));
430 enum pt_watch_style style;
433 struct mips32_watch_regs mips32;
434 struct mips64_watch_regs mips64;
438 /* -1 if the kernel and/or CPU do not support watch registers.
439 1 if watch_readback is valid and we can read style, num_valid
441 0 if we need to read the watch_readback. */
443 static int watch_readback_valid;
445 /* Cached watch register read values. */
447 static struct pt_watch_regs watch_readback;
449 /* We keep list of all watchpoints we should install and calculate the
450 watch register values each time the list changes. This allows for
451 easy sharing of watch registers for more than one watchpoint. */
453 struct mips_watchpoint
458 struct mips_watchpoint *next;
461 static struct mips_watchpoint *current_watches;
463 /* The current set of watch register values for writing the
466 static struct pt_watch_regs watch_mirror;
468 /* Assuming usable watch registers, return the irw_mask. */
471 get_irw_mask (struct pt_watch_regs *regs, int set)
475 case pt_watch_style_mips32:
476 return regs->mips32.watch_masks[set] & IRW_MASK;
477 case pt_watch_style_mips64:
478 return regs->mips64.watch_masks[set] & IRW_MASK;
480 internal_error (__FILE__, __LINE__,
481 _("Unrecognized watch register style"));
485 /* Assuming usable watch registers, return the reg_mask. */
488 get_reg_mask (struct pt_watch_regs *regs, int set)
492 case pt_watch_style_mips32:
493 return regs->mips32.watch_masks[set] & ~IRW_MASK;
494 case pt_watch_style_mips64:
495 return regs->mips64.watch_masks[set] & ~IRW_MASK;
497 internal_error (__FILE__, __LINE__,
498 _("Unrecognized watch register style"));
502 /* Assuming usable watch registers, return the num_valid. */
505 get_num_valid (struct pt_watch_regs *regs)
509 case pt_watch_style_mips32:
510 return regs->mips32.num_valid;
511 case pt_watch_style_mips64:
512 return regs->mips64.num_valid;
514 internal_error (__FILE__, __LINE__,
515 _("Unrecognized watch register style"));
519 /* Assuming usable watch registers, return the watchlo. */
522 get_watchlo (struct pt_watch_regs *regs, int set)
526 case pt_watch_style_mips32:
527 return regs->mips32.watchlo[set];
528 case pt_watch_style_mips64:
529 return regs->mips64.watchlo[set];
531 internal_error (__FILE__, __LINE__,
532 _("Unrecognized watch register style"));
536 /* Assuming usable watch registers, set a watchlo value. */
539 set_watchlo (struct pt_watch_regs *regs, int set, CORE_ADDR value)
543 case pt_watch_style_mips32:
544 /* The cast will never throw away bits as 64 bit addresses can
545 never be used on a 32 bit kernel. */
546 regs->mips32.watchlo[set] = (uint32_t)value;
548 case pt_watch_style_mips64:
549 regs->mips64.watchlo[set] = value;
552 internal_error (__FILE__, __LINE__,
553 _("Unrecognized watch register style"));
557 /* Assuming usable watch registers, return the watchhi. */
560 get_watchhi (struct pt_watch_regs *regs, int n)
564 case pt_watch_style_mips32:
565 return regs->mips32.watchhi[n];
566 case pt_watch_style_mips64:
567 return regs->mips64.watchhi[n];
569 internal_error (__FILE__, __LINE__,
570 _("Unrecognized watch register style"));
574 /* Assuming usable watch registers, set a watchhi value. */
577 set_watchhi (struct pt_watch_regs *regs, int n, uint16_t value)
581 case pt_watch_style_mips32:
582 regs->mips32.watchhi[n] = value;
584 case pt_watch_style_mips64:
585 regs->mips64.watchhi[n] = value;
588 internal_error (__FILE__, __LINE__,
589 _("Unrecognized watch register style"));
594 mips_show_dr (const char *func, CORE_ADDR addr,
595 int len, enum target_hw_bp_type type)
599 puts_unfiltered (func);
601 printf_unfiltered (" (addr=%s, len=%d, type=%s)",
602 paddress (target_gdbarch, addr), len,
603 type == hw_write ? "data-write"
604 : (type == hw_read ? "data-read"
605 : (type == hw_access ? "data-read/write"
606 : (type == hw_execute ? "instruction-execute"
608 puts_unfiltered (":\n");
610 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
611 printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
612 paddress (target_gdbarch,
613 get_watchlo (&watch_mirror, i)),
614 paddress (target_gdbarch,
615 get_watchhi (&watch_mirror, i)));
618 /* Return 1 if watch registers are usable. Cached information is used
619 unless force is true. */
622 mips_linux_read_watch_registers (int force)
626 if (force || watch_readback_valid == 0)
628 tid = ptid_get_lwp (inferior_ptid);
629 if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1)
631 watch_readback_valid = -1;
634 switch (watch_readback.style)
636 case pt_watch_style_mips32:
637 if (watch_readback.mips32.num_valid == 0)
639 watch_readback_valid = -1;
643 case pt_watch_style_mips64:
644 if (watch_readback.mips64.num_valid == 0)
646 watch_readback_valid = -1;
651 watch_readback_valid = -1;
654 /* Watch registers appear to be usable. */
655 watch_readback_valid = 1;
657 return (watch_readback_valid == 1) ? 1 : 0;
660 /* Convert GDB's type to an IRW mask. */
663 type_to_irw (int type)
672 return (W_MASK | R_MASK);
678 /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
679 handle the specified watch type. */
682 mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
685 uint32_t wanted_mask, irw_mask;
687 if (!mips_linux_read_watch_registers (0))
692 case bp_hardware_watchpoint:
693 wanted_mask = W_MASK;
695 case bp_read_watchpoint:
696 wanted_mask = R_MASK;
698 case bp_access_watchpoint:
699 wanted_mask = R_MASK | W_MASK;
705 for (i = 0; i < get_num_valid (&watch_readback) && cnt; i++)
707 irw_mask = get_irw_mask (&watch_readback, i);
708 if ((irw_mask & wanted_mask) == wanted_mask)
711 return (cnt == 0) ? 1 : 0;
714 /* Target to_stopped_by_watchpoint implementation. Return 1 if
715 stopped by watchpoint. The watchhi R and W bits indicate the watch
716 register triggered. */
719 mips_linux_stopped_by_watchpoint (void)
724 if (!mips_linux_read_watch_registers (1))
727 num_valid = get_num_valid (&watch_readback);
729 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
730 if (get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
736 /* Target to_stopped_data_address implementation. Set the address
737 where the watch triggered (if known). Return 1 if the address was
741 mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr)
743 /* On mips we don't know the low order 3 bits of the data address,
744 so we must return false. */
748 /* Set any low order bits in mask that are not set. */
751 fill_mask (CORE_ADDR mask)
754 while (f && f < mask)
762 /* Try to add a single watch to the specified registers. Return 1 on
763 success, 0 on failure. */
766 try_one_watch (struct pt_watch_regs *regs, CORE_ADDR addr,
767 int len, unsigned irw)
769 CORE_ADDR base_addr, last_byte, break_addr, segment_len;
770 CORE_ADDR mask_bits, t_low, t_low_end;
773 struct pt_watch_regs regs_copy;
778 last_byte = addr + len - 1;
779 mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK;
780 base_addr = addr & ~mask_bits;
782 /* Check to see if it is covered by current registers. */
783 for (i = 0; i < get_num_valid (regs); i++)
785 t_low = get_watchlo (regs, i);
786 if (t_low != 0 && irw == ((unsigned)t_low & irw))
788 t_hi = get_watchhi (regs, i) | IRW_MASK;
789 t_low &= ~(CORE_ADDR)t_hi;
790 if (addr >= t_low && last_byte <= (t_low + t_hi))
794 /* Try to find an empty register. */
796 for (i = 0; i < get_num_valid (regs); i++)
798 t_low = get_watchlo (regs, i);
799 if (t_low == 0 && irw == (get_irw_mask (regs, i) & irw))
801 if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK))
803 /* It fits, we'll take it. */
804 set_watchlo (regs, i, base_addr | irw);
805 set_watchhi (regs, i, mask_bits & ~IRW_MASK);
810 /* It doesn't fit, but has the proper IRW capabilities. */
815 if (free_watches > 1)
817 /* Try to split it across several registers. */
819 for (i = 0; i < get_num_valid (®s_copy); i++)
821 t_low = get_watchlo (®s_copy, i);
822 t_hi = get_reg_mask (®s_copy, i) | IRW_MASK;
823 if (t_low == 0 && irw == (t_hi & irw))
825 t_low = addr & ~(CORE_ADDR)t_hi;
826 break_addr = t_low + t_hi + 1;
827 if (break_addr >= addr + len)
830 segment_len = break_addr - addr;
831 mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
832 set_watchlo (®s_copy, i, (addr & ~mask_bits) | irw);
833 set_watchhi (®s_copy, i, mask_bits & ~IRW_MASK);
834 if (break_addr >= addr + len)
839 len = addr + len - break_addr;
844 /* It didn't fit anywhere, we failed. */
848 /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
849 the specified region can be covered by the watch registers. */
852 mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
854 struct pt_watch_regs dummy_regs;
857 if (!mips_linux_read_watch_registers (0))
860 dummy_regs = watch_readback;
861 /* Clear them out. */
862 for (i = 0; i < get_num_valid (&dummy_regs); i++)
863 set_watchlo (&dummy_regs, i, 0);
864 return try_one_watch (&dummy_regs, addr, len, 0);
868 /* Write the mirrored watch register values for each thread. */
871 write_watchpoint_regs (void)
878 tid = ptid_get_lwp (lp->ptid);
879 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1)
880 perror_with_name (_("Couldn't write debug register"));
885 /* linux_nat new_thread implementation. Write the mirrored watch
886 register values for the new thread. */
889 mips_linux_new_thread (struct lwp_info *lp)
893 if (!mips_linux_read_watch_registers (0))
896 tid = ptid_get_lwp (lp->ptid);
897 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1)
898 perror_with_name (_("Couldn't write debug register"));
901 /* Fill in the watch registers with the currently cached watches. */
904 populate_regs_from_watches (struct pt_watch_regs *regs)
906 struct mips_watchpoint *w;
909 /* Clear them out. */
910 for (i = 0; i < get_num_valid (regs); i++)
912 set_watchlo (regs, i, 0);
913 set_watchhi (regs, i, 0);
919 i = try_one_watch (regs, w->addr, w->len, type_to_irw (w->type));
920 /* They must all fit, because we previously calculated that they
927 /* Target to_insert_watchpoint implementation. Try to insert a new
928 watch. Return zero on success. */
931 mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type,
932 struct expression *cond)
934 struct pt_watch_regs regs;
935 struct mips_watchpoint *new_watch;
936 struct mips_watchpoint **pw;
941 if (!mips_linux_read_watch_registers (0))
947 regs = watch_readback;
948 /* Add the current watches. */
949 populate_regs_from_watches (®s);
951 /* Now try to add the new watch. */
952 if (!try_one_watch (®s, addr, len, type_to_irw (type)))
955 /* It fit. Stick it on the end of the list. */
956 new_watch = (struct mips_watchpoint *)
957 xmalloc (sizeof (struct mips_watchpoint));
958 new_watch->addr = addr;
959 new_watch->len = len;
960 new_watch->type = type;
961 new_watch->next = NULL;
963 pw = ¤t_watches;
969 retval = write_watchpoint_regs ();
972 mips_show_dr ("insert_watchpoint", addr, len, type);
977 /* Target to_remove_watchpoint implementation. Try to remove a watch.
978 Return zero on success. */
981 mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
982 struct expression *cond)
987 struct mips_watchpoint **pw;
988 struct mips_watchpoint *w;
990 /* Search for a known watch that matches. Then unlink and free
993 pw = ¤t_watches;
996 if (w->addr == addr && w->len == len && w->type == type)
1007 return -1; /* We don't know about it, fail doing nothing. */
1009 /* At this point watch_readback is known to be valid because we
1010 could not have added the watch without reading it. */
1011 gdb_assert (watch_readback_valid == 1);
1013 watch_mirror = watch_readback;
1014 populate_regs_from_watches (&watch_mirror);
1016 retval = write_watchpoint_regs ();
1019 mips_show_dr ("remove_watchpoint", addr, len, type);
1024 /* Target to_close implementation. Free any watches and call the
1025 super implementation. */
1028 mips_linux_close (int quitting)
1030 struct mips_watchpoint *w;
1031 struct mips_watchpoint *nw;
1033 /* Clean out the current_watches list. */
1034 w = current_watches;
1041 current_watches = NULL;
1044 super_close (quitting);
1047 void _initialize_mips_linux_nat (void);
1050 _initialize_mips_linux_nat (void)
1052 struct target_ops *t;
1054 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
1055 &maint_show_dr, _("\
1056 Set whether to show variables that mirror the mips debug registers."), _("\
1057 Show whether to show variables that mirror the mips debug registers."), _("\
1058 Use \"on\" to enable, \"off\" to disable.\n\
1059 If enabled, the debug registers values are shown when GDB inserts\n\
1060 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1061 triggers a breakpoint or watchpoint."),
1064 &maintenance_set_cmdlist,
1065 &maintenance_show_cmdlist);
1067 t = linux_trad_target (mips_linux_register_u_offset);
1069 super_close = t->to_close;
1070 t->to_close = mips_linux_close;
1072 super_fetch_registers = t->to_fetch_registers;
1073 super_store_registers = t->to_store_registers;
1075 t->to_fetch_registers = mips64_linux_fetch_registers;
1076 t->to_store_registers = mips64_linux_store_registers;
1078 t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint;
1079 t->to_remove_watchpoint = mips_linux_remove_watchpoint;
1080 t->to_insert_watchpoint = mips_linux_insert_watchpoint;
1081 t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint;
1082 t->to_stopped_data_address = mips_linux_stopped_data_address;
1083 t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint;
1085 t->to_read_description = mips_linux_read_description;
1087 linux_nat_add_target (t);
1088 linux_nat_set_new_thread (t, mips_linux_new_thread);
1090 /* Initialize the standard target descriptions. */
1091 initialize_tdesc_mips_linux ();
1092 initialize_tdesc_mips64_linux ();