1 /* Native-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb_assert.h"
25 #include "mips-tdep.h"
28 #include "linux-nat.h"
29 #include "mips-linux-tdep.h"
30 #include "target-descriptions.h"
32 #include "gdb_proc_service.h"
36 #include <sys/ptrace.h>
38 #include "features/mips-linux.c"
39 #include "features/mips-dsp-linux.c"
40 #include "features/mips64-linux.c"
41 #include "features/mips64-dsp-linux.c"
43 #ifndef PTRACE_GET_THREAD_AREA
44 #define PTRACE_GET_THREAD_AREA 25
47 /* Assume that we have PTRACE_GETREGS et al. support. If we do not,
48 we'll clear this and use PTRACE_PEEKUSER instead. */
49 static int have_ptrace_regsets = 1;
51 /* Whether or not to print the mirrored debug registers. */
53 static int maint_show_dr;
55 /* Saved function pointers to fetch and store a single register using
56 PTRACE_PEEKUSER and PTRACE_POKEUSER. */
58 static void (*super_fetch_registers) (struct target_ops *,
59 struct regcache *, int);
60 static void (*super_store_registers) (struct target_ops *,
61 struct regcache *, int);
63 static void (*super_close) (int);
65 /* Map gdb internal register number to ptrace ``address''.
66 These ``addresses'' are normally defined in <asm/ptrace.h>.
68 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
69 and there's no point in reading or setting MIPS_ZERO_REGNUM.
70 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
73 mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
77 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
78 error (_("Bogon register number %d."), regno);
80 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
82 else if ((regno >= mips_regnum (gdbarch)->fp0)
83 && (regno < mips_regnum (gdbarch)->fp0 + 32))
84 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
85 else if (regno == mips_regnum (gdbarch)->pc)
87 else if (regno == mips_regnum (gdbarch)->cause)
88 regaddr = store? (CORE_ADDR) -1 : CAUSE;
89 else if (regno == mips_regnum (gdbarch)->badvaddr)
90 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
91 else if (regno == mips_regnum (gdbarch)->lo)
93 else if (regno == mips_regnum (gdbarch)->hi)
95 else if (regno == mips_regnum (gdbarch)->fp_control_status)
97 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
98 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
99 else if (mips_regnum (gdbarch)->dspacc != -1
100 && regno >= mips_regnum (gdbarch)->dspacc
101 && regno < mips_regnum (gdbarch)->dspacc + 6)
102 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
103 else if (regno == mips_regnum (gdbarch)->dspctl)
104 regaddr = DSP_CONTROL;
105 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
108 regaddr = (CORE_ADDR) -1;
114 mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
118 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
119 error (_("Bogon register number %d."), regno);
121 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
123 else if ((regno >= mips_regnum (gdbarch)->fp0)
124 && (regno < mips_regnum (gdbarch)->fp0 + 32))
125 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
126 else if (regno == mips_regnum (gdbarch)->pc)
128 else if (regno == mips_regnum (gdbarch)->cause)
129 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
130 else if (regno == mips_regnum (gdbarch)->badvaddr)
131 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
132 else if (regno == mips_regnum (gdbarch)->lo)
133 regaddr = MIPS64_MMLO;
134 else if (regno == mips_regnum (gdbarch)->hi)
135 regaddr = MIPS64_MMHI;
136 else if (regno == mips_regnum (gdbarch)->fp_control_status)
137 regaddr = MIPS64_FPC_CSR;
138 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
139 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
140 else if (mips_regnum (gdbarch)->dspacc != -1
141 && regno >= mips_regnum (gdbarch)->dspacc
142 && regno < mips_regnum (gdbarch)->dspacc + 6)
143 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
144 else if (regno == mips_regnum (gdbarch)->dspctl)
145 regaddr = DSP_CONTROL;
146 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
149 regaddr = (CORE_ADDR) -1;
154 /* Fetch the thread-local storage pointer for libthread_db. */
157 ps_get_thread_area (const struct ps_prochandle *ph,
158 lwpid_t lwpid, int idx, void **base)
160 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
163 /* IDX is the bias from the thread pointer to the beginning of the
164 thread descriptor. It has to be subtracted due to implementation
165 quirks in libthread_db. */
166 *base = (void *) ((char *)*base - idx);
171 /* Wrapper functions. These are only used by libthread_db. */
174 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
176 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
177 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
179 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
183 fill_gregset (const struct regcache *regcache,
184 gdb_gregset_t *gregsetp, int regno)
186 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
187 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
189 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
193 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
195 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
196 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
198 mips64_supply_fpregset (regcache,
199 (const mips64_elf_fpregset_t *) fpregsetp);
203 fill_fpregset (const struct regcache *regcache,
204 gdb_fpregset_t *fpregsetp, int regno)
206 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
207 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
209 mips64_fill_fpregset (regcache,
210 (mips64_elf_fpregset_t *) fpregsetp, regno);
214 /* Fetch REGNO (or all registers if REGNO == -1) from the target
215 using PTRACE_GETREGS et al. */
218 mips64_linux_regsets_fetch_registers (struct target_ops *ops,
219 struct regcache *regcache, int regno)
221 struct gdbarch *gdbarch = get_regcache_arch (regcache);
227 if (regno >= mips_regnum (gdbarch)->fp0
228 && regno <= mips_regnum (gdbarch)->fp0 + 32)
230 else if (regno == mips_regnum (gdbarch)->fp_control_status)
232 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
237 /* DSP registers are optional and not a part of any set. */
238 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
241 else if (regno >= mips_regnum (gdbarch)->dspacc
242 && regno < mips_regnum (gdbarch)->dspacc + 6)
244 else if (regno == mips_regnum (gdbarch)->dspctl)
249 tid = ptid_get_lwp (inferior_ptid);
251 tid = ptid_get_pid (inferior_ptid);
253 if (regno == -1 || (!is_fp && !is_dsp))
255 mips64_elf_gregset_t regs;
257 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
261 have_ptrace_regsets = 0;
264 perror_with_name (_("Couldn't get registers"));
267 mips64_supply_gregset (regcache,
268 (const mips64_elf_gregset_t *) ®s);
271 if (regno == -1 || is_fp)
273 mips64_elf_fpregset_t fp_regs;
275 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
276 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
280 have_ptrace_regsets = 0;
283 perror_with_name (_("Couldn't get FP registers"));
286 mips64_supply_fpregset (regcache,
287 (const mips64_elf_fpregset_t *) &fp_regs);
291 super_fetch_registers (ops, regcache, regno);
292 else if (regno == -1 && have_dsp)
294 for (regi = mips_regnum (gdbarch)->dspacc;
295 regi < mips_regnum (gdbarch)->dspacc + 6;
297 super_fetch_registers (ops, regcache, regi);
298 super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
302 /* Store REGNO (or all registers if REGNO == -1) to the target
303 using PTRACE_SETREGS et al. */
306 mips64_linux_regsets_store_registers (struct target_ops *ops,
307 struct regcache *regcache, int regno)
309 struct gdbarch *gdbarch = get_regcache_arch (regcache);
315 if (regno >= mips_regnum (gdbarch)->fp0
316 && regno <= mips_regnum (gdbarch)->fp0 + 32)
318 else if (regno == mips_regnum (gdbarch)->fp_control_status)
320 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
325 /* DSP registers are optional and not a part of any set. */
326 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
329 if (regno >= mips_regnum (gdbarch)->dspacc
330 && regno < mips_regnum (gdbarch)->dspacc + 6)
332 else if (regno == mips_regnum (gdbarch)->dspctl)
337 tid = ptid_get_lwp (inferior_ptid);
339 tid = ptid_get_pid (inferior_ptid);
341 if (regno == -1 || (!is_fp && !is_dsp))
343 mips64_elf_gregset_t regs;
345 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
346 perror_with_name (_("Couldn't get registers"));
348 mips64_fill_gregset (regcache, ®s, regno);
350 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
351 perror_with_name (_("Couldn't set registers"));
354 if (regno == -1 || is_fp)
356 mips64_elf_fpregset_t fp_regs;
358 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
359 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
360 perror_with_name (_("Couldn't get FP registers"));
362 mips64_fill_fpregset (regcache, &fp_regs, regno);
364 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
365 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
366 perror_with_name (_("Couldn't set FP registers"));
370 super_store_registers (ops, regcache, regno);
371 else if (regno == -1 && have_dsp)
373 for (regi = mips_regnum (gdbarch)->dspacc;
374 regi < mips_regnum (gdbarch)->dspacc + 6;
376 super_store_registers (ops, regcache, regi);
377 super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
381 /* Fetch REGNO (or all registers if REGNO == -1) from the target
382 using any working method. */
385 mips64_linux_fetch_registers (struct target_ops *ops,
386 struct regcache *regcache, int regnum)
388 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
389 if (have_ptrace_regsets)
390 mips64_linux_regsets_fetch_registers (ops, regcache, regnum);
392 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
393 back to PTRACE_PEEKUSER. */
394 if (!have_ptrace_regsets)
395 super_fetch_registers (ops, regcache, regnum);
398 /* Store REGNO (or all registers if REGNO == -1) to the target
399 using any working method. */
402 mips64_linux_store_registers (struct target_ops *ops,
403 struct regcache *regcache, int regnum)
405 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
406 if (have_ptrace_regsets)
407 mips64_linux_regsets_store_registers (ops, regcache, regnum);
409 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
410 back to PTRACE_PEEKUSER. */
411 if (!have_ptrace_regsets)
412 super_store_registers (ops, regcache, regnum);
415 /* Return the address in the core dump or inferior of register
419 mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p)
421 if (mips_abi_regsize (gdbarch) == 8)
422 return mips64_linux_register_addr (gdbarch, regno, store_p);
424 return mips_linux_register_addr (gdbarch, regno, store_p);
427 static const struct target_desc *
428 mips_linux_read_description (struct target_ops *ops)
430 static int have_dsp = -1;
436 tid = ptid_get_lwp (inferior_ptid);
438 tid = ptid_get_pid (inferior_ptid);
440 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
450 perror_with_name (_("Couldn't check DSP support"));
455 /* Report that target registers are a size we know for sure
456 that we can get from ptrace. */
457 if (_MIPS_SIM == _ABIO32)
458 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
460 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
463 #ifndef PTRACE_GET_WATCH_REGS
464 # define PTRACE_GET_WATCH_REGS 0xd0
467 #ifndef PTRACE_SET_WATCH_REGS
468 # define PTRACE_SET_WATCH_REGS 0xd1
475 #define W_MASK (1 << W_BIT)
476 #define R_MASK (1 << R_BIT)
477 #define I_MASK (1 << I_BIT)
479 #define IRW_MASK (I_MASK | R_MASK | W_MASK)
481 enum pt_watch_style {
482 pt_watch_style_mips32,
483 pt_watch_style_mips64
486 #define MAX_DEBUG_REGISTER 8
488 /* A value of zero in a watchlo indicates that it is available. */
490 struct mips32_watch_regs
492 uint32_t watchlo[MAX_DEBUG_REGISTER];
493 /* Lower 16 bits of watchhi. */
494 uint16_t watchhi[MAX_DEBUG_REGISTER];
495 /* Valid mask and I R W bits.
496 * bit 0 -- 1 if W bit is usable.
497 * bit 1 -- 1 if R bit is usable.
498 * bit 2 -- 1 if I bit is usable.
499 * bits 3 - 11 -- Valid watchhi mask bits.
501 uint16_t watch_masks[MAX_DEBUG_REGISTER];
502 /* The number of valid watch register pairs. */
504 /* There is confusion across gcc versions about structure alignment,
505 so we force 8 byte alignment for these structures so they match
506 the kernel even if it was build with a different gcc version. */
507 } __attribute__ ((aligned (8)));
509 struct mips64_watch_regs
511 uint64_t watchlo[MAX_DEBUG_REGISTER];
512 uint16_t watchhi[MAX_DEBUG_REGISTER];
513 uint16_t watch_masks[MAX_DEBUG_REGISTER];
515 } __attribute__ ((aligned (8)));
519 enum pt_watch_style style;
522 struct mips32_watch_regs mips32;
523 struct mips64_watch_regs mips64;
527 /* -1 if the kernel and/or CPU do not support watch registers.
528 1 if watch_readback is valid and we can read style, num_valid
530 0 if we need to read the watch_readback. */
532 static int watch_readback_valid;
534 /* Cached watch register read values. */
536 static struct pt_watch_regs watch_readback;
538 /* We keep list of all watchpoints we should install and calculate the
539 watch register values each time the list changes. This allows for
540 easy sharing of watch registers for more than one watchpoint. */
542 struct mips_watchpoint
547 struct mips_watchpoint *next;
550 static struct mips_watchpoint *current_watches;
552 /* The current set of watch register values for writing the
555 static struct pt_watch_regs watch_mirror;
557 /* Assuming usable watch registers, return the irw_mask. */
560 get_irw_mask (struct pt_watch_regs *regs, int set)
564 case pt_watch_style_mips32:
565 return regs->mips32.watch_masks[set] & IRW_MASK;
566 case pt_watch_style_mips64:
567 return regs->mips64.watch_masks[set] & IRW_MASK;
569 internal_error (__FILE__, __LINE__,
570 _("Unrecognized watch register style"));
574 /* Assuming usable watch registers, return the reg_mask. */
577 get_reg_mask (struct pt_watch_regs *regs, int set)
581 case pt_watch_style_mips32:
582 return regs->mips32.watch_masks[set] & ~IRW_MASK;
583 case pt_watch_style_mips64:
584 return regs->mips64.watch_masks[set] & ~IRW_MASK;
586 internal_error (__FILE__, __LINE__,
587 _("Unrecognized watch register style"));
591 /* Assuming usable watch registers, return the num_valid. */
594 get_num_valid (struct pt_watch_regs *regs)
598 case pt_watch_style_mips32:
599 return regs->mips32.num_valid;
600 case pt_watch_style_mips64:
601 return regs->mips64.num_valid;
603 internal_error (__FILE__, __LINE__,
604 _("Unrecognized watch register style"));
608 /* Assuming usable watch registers, return the watchlo. */
611 get_watchlo (struct pt_watch_regs *regs, int set)
615 case pt_watch_style_mips32:
616 return regs->mips32.watchlo[set];
617 case pt_watch_style_mips64:
618 return regs->mips64.watchlo[set];
620 internal_error (__FILE__, __LINE__,
621 _("Unrecognized watch register style"));
625 /* Assuming usable watch registers, set a watchlo value. */
628 set_watchlo (struct pt_watch_regs *regs, int set, CORE_ADDR value)
632 case pt_watch_style_mips32:
633 /* The cast will never throw away bits as 64 bit addresses can
634 never be used on a 32 bit kernel. */
635 regs->mips32.watchlo[set] = (uint32_t)value;
637 case pt_watch_style_mips64:
638 regs->mips64.watchlo[set] = value;
641 internal_error (__FILE__, __LINE__,
642 _("Unrecognized watch register style"));
646 /* Assuming usable watch registers, return the watchhi. */
649 get_watchhi (struct pt_watch_regs *regs, int n)
653 case pt_watch_style_mips32:
654 return regs->mips32.watchhi[n];
655 case pt_watch_style_mips64:
656 return regs->mips64.watchhi[n];
658 internal_error (__FILE__, __LINE__,
659 _("Unrecognized watch register style"));
663 /* Assuming usable watch registers, set a watchhi value. */
666 set_watchhi (struct pt_watch_regs *regs, int n, uint16_t value)
670 case pt_watch_style_mips32:
671 regs->mips32.watchhi[n] = value;
673 case pt_watch_style_mips64:
674 regs->mips64.watchhi[n] = value;
677 internal_error (__FILE__, __LINE__,
678 _("Unrecognized watch register style"));
683 mips_show_dr (const char *func, CORE_ADDR addr,
684 int len, enum target_hw_bp_type type)
688 puts_unfiltered (func);
690 printf_unfiltered (" (addr=%s, len=%d, type=%s)",
691 paddress (target_gdbarch (), addr), len,
692 type == hw_write ? "data-write"
693 : (type == hw_read ? "data-read"
694 : (type == hw_access ? "data-read/write"
695 : (type == hw_execute ? "instruction-execute"
697 puts_unfiltered (":\n");
699 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
700 printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
701 paddress (target_gdbarch (),
702 get_watchlo (&watch_mirror, i)),
703 paddress (target_gdbarch (),
704 get_watchhi (&watch_mirror, i)));
707 /* Return 1 if watch registers are usable. Cached information is used
708 unless force is true. */
711 mips_linux_read_watch_registers (int force)
715 if (force || watch_readback_valid == 0)
717 tid = ptid_get_lwp (inferior_ptid);
718 if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1)
720 watch_readback_valid = -1;
723 switch (watch_readback.style)
725 case pt_watch_style_mips32:
726 if (watch_readback.mips32.num_valid == 0)
728 watch_readback_valid = -1;
732 case pt_watch_style_mips64:
733 if (watch_readback.mips64.num_valid == 0)
735 watch_readback_valid = -1;
740 watch_readback_valid = -1;
743 /* Watch registers appear to be usable. */
744 watch_readback_valid = 1;
746 return (watch_readback_valid == 1) ? 1 : 0;
749 /* Convert GDB's type to an IRW mask. */
752 type_to_irw (int type)
761 return (W_MASK | R_MASK);
767 /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
768 handle the specified watch type. */
771 mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
774 uint32_t wanted_mask, irw_mask;
776 if (!mips_linux_read_watch_registers (0))
781 case bp_hardware_watchpoint:
782 wanted_mask = W_MASK;
784 case bp_read_watchpoint:
785 wanted_mask = R_MASK;
787 case bp_access_watchpoint:
788 wanted_mask = R_MASK | W_MASK;
794 for (i = 0; i < get_num_valid (&watch_readback) && cnt; i++)
796 irw_mask = get_irw_mask (&watch_readback, i);
797 if ((irw_mask & wanted_mask) == wanted_mask)
800 return (cnt == 0) ? 1 : 0;
803 /* Target to_stopped_by_watchpoint implementation. Return 1 if
804 stopped by watchpoint. The watchhi R and W bits indicate the watch
805 register triggered. */
808 mips_linux_stopped_by_watchpoint (void)
813 if (!mips_linux_read_watch_registers (1))
816 num_valid = get_num_valid (&watch_readback);
818 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
819 if (get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
825 /* Target to_stopped_data_address implementation. Set the address
826 where the watch triggered (if known). Return 1 if the address was
830 mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr)
832 /* On mips we don't know the low order 3 bits of the data address,
833 so we must return false. */
837 /* Set any low order bits in mask that are not set. */
840 fill_mask (CORE_ADDR mask)
843 while (f && f < mask)
851 /* Try to add a single watch to the specified registers. Return 1 on
852 success, 0 on failure. */
855 try_one_watch (struct pt_watch_regs *regs, CORE_ADDR addr,
856 int len, unsigned irw)
858 CORE_ADDR base_addr, last_byte, break_addr, segment_len;
859 CORE_ADDR mask_bits, t_low, t_low_end;
862 struct pt_watch_regs regs_copy;
867 last_byte = addr + len - 1;
868 mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK;
869 base_addr = addr & ~mask_bits;
871 /* Check to see if it is covered by current registers. */
872 for (i = 0; i < get_num_valid (regs); i++)
874 t_low = get_watchlo (regs, i);
875 if (t_low != 0 && irw == ((unsigned)t_low & irw))
877 t_hi = get_watchhi (regs, i) | IRW_MASK;
878 t_low &= ~(CORE_ADDR)t_hi;
879 if (addr >= t_low && last_byte <= (t_low + t_hi))
883 /* Try to find an empty register. */
885 for (i = 0; i < get_num_valid (regs); i++)
887 t_low = get_watchlo (regs, i);
888 if (t_low == 0 && irw == (get_irw_mask (regs, i) & irw))
890 if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK))
892 /* It fits, we'll take it. */
893 set_watchlo (regs, i, base_addr | irw);
894 set_watchhi (regs, i, mask_bits & ~IRW_MASK);
899 /* It doesn't fit, but has the proper IRW capabilities. */
904 if (free_watches > 1)
906 /* Try to split it across several registers. */
908 for (i = 0; i < get_num_valid (®s_copy); i++)
910 t_low = get_watchlo (®s_copy, i);
911 t_hi = get_reg_mask (®s_copy, i) | IRW_MASK;
912 if (t_low == 0 && irw == (t_hi & irw))
914 t_low = addr & ~(CORE_ADDR)t_hi;
915 break_addr = t_low + t_hi + 1;
916 if (break_addr >= addr + len)
919 segment_len = break_addr - addr;
920 mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
921 set_watchlo (®s_copy, i, (addr & ~mask_bits) | irw);
922 set_watchhi (®s_copy, i, mask_bits & ~IRW_MASK);
923 if (break_addr >= addr + len)
928 len = addr + len - break_addr;
933 /* It didn't fit anywhere, we failed. */
937 /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
938 the specified region can be covered by the watch registers. */
941 mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
943 struct pt_watch_regs dummy_regs;
946 if (!mips_linux_read_watch_registers (0))
949 dummy_regs = watch_readback;
950 /* Clear them out. */
951 for (i = 0; i < get_num_valid (&dummy_regs); i++)
952 set_watchlo (&dummy_regs, i, 0);
953 return try_one_watch (&dummy_regs, addr, len, 0);
957 /* Write the mirrored watch register values for each thread. */
960 write_watchpoint_regs (void)
967 tid = ptid_get_lwp (lp->ptid);
968 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1)
969 perror_with_name (_("Couldn't write debug register"));
974 /* linux_nat new_thread implementation. Write the mirrored watch
975 register values for the new thread. */
978 mips_linux_new_thread (struct lwp_info *lp)
982 if (!mips_linux_read_watch_registers (0))
985 tid = ptid_get_lwp (lp->ptid);
986 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1)
987 perror_with_name (_("Couldn't write debug register"));
990 /* Fill in the watch registers with the currently cached watches. */
993 populate_regs_from_watches (struct pt_watch_regs *regs)
995 struct mips_watchpoint *w;
998 /* Clear them out. */
999 for (i = 0; i < get_num_valid (regs); i++)
1001 set_watchlo (regs, i, 0);
1002 set_watchhi (regs, i, 0);
1005 w = current_watches;
1008 i = try_one_watch (regs, w->addr, w->len, type_to_irw (w->type));
1009 /* They must all fit, because we previously calculated that they
1016 /* Target to_insert_watchpoint implementation. Try to insert a new
1017 watch. Return zero on success. */
1020 mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type,
1021 struct expression *cond)
1023 struct pt_watch_regs regs;
1024 struct mips_watchpoint *new_watch;
1025 struct mips_watchpoint **pw;
1030 if (!mips_linux_read_watch_registers (0))
1036 regs = watch_readback;
1037 /* Add the current watches. */
1038 populate_regs_from_watches (®s);
1040 /* Now try to add the new watch. */
1041 if (!try_one_watch (®s, addr, len, type_to_irw (type)))
1044 /* It fit. Stick it on the end of the list. */
1045 new_watch = (struct mips_watchpoint *)
1046 xmalloc (sizeof (struct mips_watchpoint));
1047 new_watch->addr = addr;
1048 new_watch->len = len;
1049 new_watch->type = type;
1050 new_watch->next = NULL;
1052 pw = ¤t_watches;
1057 watch_mirror = regs;
1058 retval = write_watchpoint_regs ();
1061 mips_show_dr ("insert_watchpoint", addr, len, type);
1066 /* Target to_remove_watchpoint implementation. Try to remove a watch.
1067 Return zero on success. */
1070 mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
1071 struct expression *cond)
1076 struct mips_watchpoint **pw;
1077 struct mips_watchpoint *w;
1079 /* Search for a known watch that matches. Then unlink and free
1082 pw = ¤t_watches;
1085 if (w->addr == addr && w->len == len && w->type == type)
1096 return -1; /* We don't know about it, fail doing nothing. */
1098 /* At this point watch_readback is known to be valid because we
1099 could not have added the watch without reading it. */
1100 gdb_assert (watch_readback_valid == 1);
1102 watch_mirror = watch_readback;
1103 populate_regs_from_watches (&watch_mirror);
1105 retval = write_watchpoint_regs ();
1108 mips_show_dr ("remove_watchpoint", addr, len, type);
1113 /* Target to_close implementation. Free any watches and call the
1114 super implementation. */
1117 mips_linux_close (int quitting)
1119 struct mips_watchpoint *w;
1120 struct mips_watchpoint *nw;
1122 /* Clean out the current_watches list. */
1123 w = current_watches;
1130 current_watches = NULL;
1133 super_close (quitting);
1136 void _initialize_mips_linux_nat (void);
1139 _initialize_mips_linux_nat (void)
1141 struct target_ops *t;
1143 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
1144 &maint_show_dr, _("\
1145 Set whether to show variables that mirror the mips debug registers."), _("\
1146 Show whether to show variables that mirror the mips debug registers."), _("\
1147 Use \"on\" to enable, \"off\" to disable.\n\
1148 If enabled, the debug registers values are shown when GDB inserts\n\
1149 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1150 triggers a breakpoint or watchpoint."),
1153 &maintenance_set_cmdlist,
1154 &maintenance_show_cmdlist);
1156 t = linux_trad_target (mips_linux_register_u_offset);
1158 super_close = t->to_close;
1159 t->to_close = mips_linux_close;
1161 super_fetch_registers = t->to_fetch_registers;
1162 super_store_registers = t->to_store_registers;
1164 t->to_fetch_registers = mips64_linux_fetch_registers;
1165 t->to_store_registers = mips64_linux_store_registers;
1167 t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint;
1168 t->to_remove_watchpoint = mips_linux_remove_watchpoint;
1169 t->to_insert_watchpoint = mips_linux_insert_watchpoint;
1170 t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint;
1171 t->to_stopped_data_address = mips_linux_stopped_data_address;
1172 t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint;
1174 t->to_read_description = mips_linux_read_description;
1176 linux_nat_add_target (t);
1177 linux_nat_set_new_thread (t, mips_linux_new_thread);
1179 /* Initialize the standard target descriptions. */
1180 initialize_tdesc_mips_linux ();
1181 initialize_tdesc_mips_dsp_linux ();
1182 initialize_tdesc_mips64_linux ();
1183 initialize_tdesc_mips64_dsp_linux ();