1 /* Target-dependent code for the Toshiba MeP for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 Contributed by Red Hat, Inc.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
31 #include "gdb_string.h"
38 #include "arch-utils.h"
41 #include "floatformat.h"
42 #include "sim-regno.h"
44 #include "trad-frame.h"
45 #include "reggroups.h"
48 #include "prologue-value.h"
49 #include "opcode/cgen-bitset.h"
52 #include "gdb_assert.h"
54 /* Get the user's customized MeP coprocessor register names from
56 #include "opcodes/mep-desc.h"
57 #include "opcodes/mep-opc.h"
60 /* The gdbarch_tdep structure. */
62 /* A quick recap for GDB hackers not familiar with the whole Toshiba
63 Media Processor story:
65 The MeP media engine is a configureable processor: users can design
66 their own coprocessors, implement custom instructions, adjust cache
67 sizes, select optional standard facilities like add-and-saturate
68 instructions, and so on. Then, they can build custom versions of
69 the GNU toolchain to support their customized chips. The
70 MeP-Integrator program (see utils/mep) takes a GNU toolchain source
71 tree, and a config file pointing to various files provided by the
72 user describing their customizations, and edits the source tree to
73 produce a compiler that can generate their custom instructions, an
74 assembler that can assemble them and recognize their custom
75 register names, and so on.
77 Furthermore, the user can actually specify several of these custom
78 configurations, called 'me_modules', and get a toolchain which can
79 produce code for any of them, given a compiler/assembler switch;
80 you say something like 'gcc -mconfig=mm_max' to generate code for
81 the me_module named 'mm_max'.
83 GDB, in particular, needs to:
85 - use the coprocessor control register names provided by the user
86 in their hardware description, in expressions, 'info register'
87 output, and disassembly,
89 - know the number, names, and types of the coprocessor's
90 general-purpose registers, adjust the 'info all-registers' output
91 accordingly, and print error messages if the user refers to one
94 - allow access to the control bus space only when the configuration
95 actually has a control bus, and recognize which regions of the
96 control bus space are actually populated,
98 - disassemble using the user's provided mnemonics for their custom
101 - recognize whether the $hi and $lo registers are present, and
102 allow access to them only when they are actually there.
104 There are three sources of information about what sort of me_module
105 we're actually dealing with:
107 - A MeP executable file indicates which me_module it was compiled
108 for, and libopcodes has tables describing each module. So, given
109 an executable file, we can find out about the processor it was
112 - There are SID command-line options to select a particular
113 me_module, overriding the one specified in the ELF file. SID
114 provides GDB with a fake read-only register, 'module', which
115 indicates which me_module GDB is communicating with an instance
118 - There are SID command-line options to enable or disable certain
119 optional processor features, overriding the defaults for the
120 selected me_module. The MeP $OPT register indicates which
121 options are present on the current processor. */
126 /* A CGEN cpu descriptor for this BFD architecture and machine.
128 Note: this is *not* customized for any particular me_module; the
129 MeP libopcodes machinery actually puts off module-specific
130 customization until the last minute. So this contains
131 information about all supported me_modules. */
132 CGEN_CPU_DESC cpu_desc;
134 /* The me_module index from the ELF file we used to select this
135 architecture, or CONFIG_NONE if there was none.
137 Note that we should prefer to use the me_module number available
138 via the 'module' register, whenever we're actually talking to a
141 In the absence of live information, we'd like to get the
142 me_module number from the ELF file. But which ELF file: the
143 executable file, the core file, ... ? The answer is, "the last
144 ELF file we used to set the current architecture". Thus, we
145 create a separate instance of the gdbarch structure for each
146 me_module value mep_gdbarch_init sees, and store the me_module
147 value from the ELF file here. */
148 CONFIG_ATTR me_module;
153 /* Getting me_module information from the CGEN tables. */
156 /* Find an entry in the DESC's hardware table whose name begins with
157 PREFIX, and whose ISA mask intersects COPRO_ISA_MASK, but does not
158 intersect with GENERIC_ISA_MASK. If there is no matching entry,
160 static const CGEN_HW_ENTRY *
161 find_hw_entry_by_prefix_and_isa (CGEN_CPU_DESC desc,
163 CGEN_BITSET *copro_isa_mask,
164 CGEN_BITSET *generic_isa_mask)
166 int prefix_len = strlen (prefix);
169 for (i = 0; i < desc->hw_table.num_entries; i++)
171 const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i];
172 if (strncmp (prefix, hw->name, prefix_len) == 0)
174 CGEN_BITSET *hw_isa_mask
176 &CGEN_ATTR_CGEN_HW_ISA_VALUE (CGEN_HW_ATTRS (hw)));
178 if (cgen_bitset_intersect_p (hw_isa_mask, copro_isa_mask)
179 && ! cgen_bitset_intersect_p (hw_isa_mask, generic_isa_mask))
188 /* Find an entry in DESC's hardware table whose type is TYPE. Return
189 zero if there is none. */
190 static const CGEN_HW_ENTRY *
191 find_hw_entry_by_type (CGEN_CPU_DESC desc, CGEN_HW_TYPE type)
195 for (i = 0; i < desc->hw_table.num_entries; i++)
197 const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i];
199 if (hw->type == type)
207 /* Return the CGEN hardware table entry for the coprocessor register
208 set for ME_MODULE, whose name prefix is PREFIX. If ME_MODULE has
209 no such register set, return zero. If ME_MODULE is the generic
210 me_module CONFIG_NONE, return the table entry for the register set
211 whose hardware type is GENERIC_TYPE. */
212 static const CGEN_HW_ENTRY *
213 me_module_register_set (CONFIG_ATTR me_module,
215 CGEN_HW_TYPE generic_type)
217 /* This is kind of tricky, because the hardware table is constructed
218 in a way that isn't very helpful. Perhaps we can fix that, but
219 here's how it works at the moment:
221 The configuration map, `mep_config_map', is indexed by me_module
222 number, and indicates which coprocessor and core ISAs that
223 me_module supports. The 'core_isa' mask includes all the core
224 ISAs, and the 'cop_isa' mask includes all the coprocessor ISAs.
225 The entry for the generic me_module, CONFIG_NONE, has an empty
226 'cop_isa', and its 'core_isa' selects only the standard MeP
229 The CGEN CPU descriptor's hardware table, desc->hw_table, has
230 entries for all the register sets, for all me_modules. Each
231 entry has a mask indicating which ISAs use that register set.
232 So, if an me_module supports some coprocessor ISA, we can find
233 applicable register sets by scanning the hardware table for
234 register sets whose masks include (at least some of) those ISAs.
236 Each hardware table entry also has a name, whose prefix says
237 whether it's a general-purpose ("h-cr") or control ("h-ccr")
238 coprocessor register set. It might be nicer to have an attribute
239 indicating what sort of register set it was, that we could use
240 instead of pattern-matching on the name.
242 When there is no hardware table entry whose mask includes a
243 particular coprocessor ISA and whose name starts with a given
244 prefix, then that means that that coprocessor doesn't have any
245 registers of that type. In such cases, this function must return
248 Coprocessor register sets' masks may or may not include the core
249 ISA for the me_module they belong to. Those generated by a2cgen
250 do, but the sample me_module included in the unconfigured tree,
253 There are generic coprocessor register sets, intended only for
254 use with the generic me_module. Unfortunately, their masks
255 include *all* ISAs --- even those for coprocessors that don't
256 have such register sets. This makes detecting the case where a
257 coprocessor lacks a particular register set more complicated.
259 So, here's the approach we take:
261 - For CONFIG_NONE, we return the generic coprocessor register set.
263 - For any other me_module, we search for a register set whose
264 mask contains any of the me_module's coprocessor ISAs,
265 specifically excluding the generic coprocessor register sets. */
267 CGEN_CPU_DESC desc = gdbarch_tdep (target_gdbarch)->cpu_desc;
268 const CGEN_HW_ENTRY *hw;
270 if (me_module == CONFIG_NONE)
271 hw = find_hw_entry_by_type (desc, generic_type);
274 CGEN_BITSET *cop = &mep_config_map[me_module].cop_isa;
275 CGEN_BITSET *core = &mep_config_map[me_module].core_isa;
276 CGEN_BITSET *generic = &mep_config_map[CONFIG_NONE].core_isa;
277 CGEN_BITSET *cop_and_core;
279 /* The coprocessor ISAs include the ISA for the specific core which
280 has that coprocessor. */
281 cop_and_core = cgen_bitset_copy (cop);
282 cgen_bitset_union (cop, core, cop_and_core);
283 hw = find_hw_entry_by_prefix_and_isa (desc, prefix, cop_and_core, generic);
290 /* Given a hardware table entry HW representing a register set, return
291 a pointer to the keyword table with all the register names. If HW
292 is NULL, return NULL, to propage the "no such register set" info
294 static CGEN_KEYWORD *
295 register_set_keyword_table (const CGEN_HW_ENTRY *hw)
300 /* Check that HW is actually a keyword table. */
301 gdb_assert (hw->asm_type == CGEN_ASM_KEYWORD);
303 /* The 'asm_data' field of a register set's hardware table entry
304 refers to a keyword table. */
305 return (CGEN_KEYWORD *) hw->asm_data;
309 /* Given a keyword table KEYWORD and a register number REGNUM, return
310 the name of the register, or "" if KEYWORD contains no register
311 whose number is REGNUM. */
313 register_name_from_keyword (CGEN_KEYWORD *keyword_table, int regnum)
315 const CGEN_KEYWORD_ENTRY *entry
316 = cgen_keyword_lookup_value (keyword_table, regnum);
320 char *name = entry->name;
322 /* The CGEN keyword entries for register names include the
323 leading $, which appears in MeP assembly as well as in GDB.
324 But we don't want to return that; GDB core code adds that
336 /* Masks for option bits in the OPT special-purpose register. */
338 MEP_OPT_DIV = 1 << 25, /* 32-bit divide instruction option */
339 MEP_OPT_MUL = 1 << 24, /* 32-bit multiply instruction option */
340 MEP_OPT_BIT = 1 << 23, /* bit manipulation instruction option */
341 MEP_OPT_SAT = 1 << 22, /* saturation instruction option */
342 MEP_OPT_CLP = 1 << 21, /* clip instruction option */
343 MEP_OPT_MIN = 1 << 20, /* min/max instruction option */
344 MEP_OPT_AVE = 1 << 19, /* average instruction option */
345 MEP_OPT_ABS = 1 << 18, /* absolute difference instruction option */
346 MEP_OPT_LDZ = 1 << 16, /* leading zero instruction option */
347 MEP_OPT_VL64 = 1 << 6, /* 64-bit VLIW operation mode option */
348 MEP_OPT_VL32 = 1 << 5, /* 32-bit VLIW operation mode option */
349 MEP_OPT_COP = 1 << 4, /* coprocessor option */
350 MEP_OPT_DSP = 1 << 2, /* DSP option */
351 MEP_OPT_UCI = 1 << 1, /* UCI option */
352 MEP_OPT_DBG = 1 << 0, /* DBG function option */
356 /* Given the option_mask value for a particular entry in
357 mep_config_map, produce the value the processor's OPT register
358 would use to represent the same set of options. */
360 opt_from_option_mask (unsigned int option_mask)
362 /* A table mapping OPT register bits onto CGEN config map option
365 unsigned int opt_bit, option_mask_bit;
367 { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN },
368 { MEP_OPT_MUL, 1 << CGEN_INSN_OPTIONAL_MUL_INSN },
369 { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN },
370 { MEP_OPT_DBG, 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN },
371 { MEP_OPT_LDZ, 1 << CGEN_INSN_OPTIONAL_LDZ_INSN },
372 { MEP_OPT_ABS, 1 << CGEN_INSN_OPTIONAL_ABS_INSN },
373 { MEP_OPT_AVE, 1 << CGEN_INSN_OPTIONAL_AVE_INSN },
374 { MEP_OPT_MIN, 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN },
375 { MEP_OPT_CLP, 1 << CGEN_INSN_OPTIONAL_CLIP_INSN },
376 { MEP_OPT_SAT, 1 << CGEN_INSN_OPTIONAL_SAT_INSN },
377 { MEP_OPT_UCI, 1 << CGEN_INSN_OPTIONAL_UCI_INSN },
378 { MEP_OPT_DSP, 1 << CGEN_INSN_OPTIONAL_DSP_INSN },
379 { MEP_OPT_COP, 1 << CGEN_INSN_OPTIONAL_CP_INSN },
383 unsigned int opt = 0;
385 for (i = 0; i < (sizeof (bits) / sizeof (bits[0])); i++)
386 if (option_mask & bits[i].option_mask_bit)
387 opt |= bits[i].opt_bit;
393 /* Return the value the $OPT register would use to represent the set
394 of options for ME_MODULE. */
396 me_module_opt (CONFIG_ATTR me_module)
398 return opt_from_option_mask (mep_config_map[me_module].option_mask);
402 /* Return the width of ME_MODULE's coprocessor data bus, in bits.
403 This is either 32 or 64. */
405 me_module_cop_data_bus_width (CONFIG_ATTR me_module)
407 if (mep_config_map[me_module].option_mask
408 & (1 << CGEN_INSN_OPTIONAL_CP64_INSN))
415 /* Return true if ME_MODULE is big-endian, false otherwise. */
417 me_module_big_endian (CONFIG_ATTR me_module)
419 return mep_config_map[me_module].big_endian;
423 /* Return the name of ME_MODULE, or NULL if it has no name. */
425 me_module_name (CONFIG_ATTR me_module)
427 /* The default me_module has "" as its name, but it's easier for our
428 callers to test for NULL. */
429 if (! mep_config_map[me_module].name
430 || mep_config_map[me_module].name[0] == '\0')
433 return mep_config_map[me_module].name;
439 /* The MeP spec defines the following registers:
440 16 general purpose registers (r0-r15)
441 32 control/special registers (csr0-csr31)
442 32 coprocessor general-purpose registers (c0 -- c31)
443 64 coprocessor control registers (ccr0 -- ccr63)
445 For the raw registers, we assign numbers here explicitly, instead
446 of letting the enum assign them for us; the numbers are a matter of
447 external protocol, and shouldn't shift around as things are edited.
449 We access the control/special registers via pseudoregisters, to
450 enforce read-only portions that some registers have.
452 We access the coprocessor general purpose and control registers via
453 pseudoregisters, to make sure they appear in the proper order in
454 the 'info all-registers' command (which uses the register number
455 ordering), and also to allow them to be renamed and resized
456 depending on the me_module in use.
458 The MeP allows coprocessor general-purpose registers to be either
459 32 or 64 bits long, depending on the configuration. Since we don't
460 want the format of the 'g' packet to vary from one core to another,
461 the raw coprocessor GPRs are always 64 bits. GDB doesn't allow the
462 types of registers to change (see the implementation of
463 register_type), so we have four banks of pseudoregisters for the
464 coprocessor gprs --- 32-bit vs. 64-bit, and integer
465 vs. floating-point --- and we show or hide them depending on the
469 MEP_FIRST_RAW_REGNUM = 0,
471 MEP_FIRST_GPR_REGNUM = 0,
485 MEP_FP_REGNUM = MEP_R8_REGNUM,
487 MEP_TP_REGNUM = MEP_R13_REGNUM, /* (r13) Tiny data pointer */
489 MEP_GP_REGNUM = MEP_R14_REGNUM, /* (r14) Global pointer */
491 MEP_SP_REGNUM = MEP_R15_REGNUM, /* (r15) Stack pointer */
492 MEP_LAST_GPR_REGNUM = MEP_R15_REGNUM,
494 /* The raw control registers. These are the values as received via
495 the remote protocol, directly from the target; we only let user
496 code touch the via the pseudoregisters, which enforce read-only
498 MEP_FIRST_RAW_CSR_REGNUM = 16,
499 MEP_RAW_PC_REGNUM = 16, /* Program counter */
500 MEP_RAW_LP_REGNUM = 17, /* Link pointer */
501 MEP_RAW_SAR_REGNUM = 18, /* Raw shift amount */
502 MEP_RAW_CSR3_REGNUM = 19, /* csr3: reserved */
503 MEP_RAW_RPB_REGNUM = 20, /* Raw repeat begin address */
504 MEP_RAW_RPE_REGNUM = 21, /* Repeat end address */
505 MEP_RAW_RPC_REGNUM = 22, /* Repeat count */
506 MEP_RAW_HI_REGNUM = 23, /* Upper 32 bits of result of 64 bit mult/div */
507 MEP_RAW_LO_REGNUM = 24, /* Lower 32 bits of result of 64 bit mult/div */
508 MEP_RAW_CSR9_REGNUM = 25, /* csr3: reserved */
509 MEP_RAW_CSR10_REGNUM = 26, /* csr3: reserved */
510 MEP_RAW_CSR11_REGNUM = 27, /* csr3: reserved */
511 MEP_RAW_MB0_REGNUM = 28, /* Raw modulo begin address 0 */
512 MEP_RAW_ME0_REGNUM = 29, /* Raw modulo end address 0 */
513 MEP_RAW_MB1_REGNUM = 30, /* Raw modulo begin address 1 */
514 MEP_RAW_ME1_REGNUM = 31, /* Raw modulo end address 1 */
515 MEP_RAW_PSW_REGNUM = 32, /* Raw program status word */
516 MEP_RAW_ID_REGNUM = 33, /* Raw processor ID/revision */
517 MEP_RAW_TMP_REGNUM = 34, /* Temporary */
518 MEP_RAW_EPC_REGNUM = 35, /* Exception program counter */
519 MEP_RAW_EXC_REGNUM = 36, /* Raw exception cause */
520 MEP_RAW_CFG_REGNUM = 37, /* Raw processor configuration*/
521 MEP_RAW_CSR22_REGNUM = 38, /* csr3: reserved */
522 MEP_RAW_NPC_REGNUM = 39, /* Nonmaskable interrupt PC */
523 MEP_RAW_DBG_REGNUM = 40, /* Raw debug */
524 MEP_RAW_DEPC_REGNUM = 41, /* Debug exception PC */
525 MEP_RAW_OPT_REGNUM = 42, /* Raw options */
526 MEP_RAW_RCFG_REGNUM = 43, /* Raw local ram config */
527 MEP_RAW_CCFG_REGNUM = 44, /* Raw cache config */
528 MEP_RAW_CSR29_REGNUM = 45, /* csr3: reserved */
529 MEP_RAW_CSR30_REGNUM = 46, /* csr3: reserved */
530 MEP_RAW_CSR31_REGNUM = 47, /* csr3: reserved */
531 MEP_LAST_RAW_CSR_REGNUM = MEP_RAW_CSR31_REGNUM,
533 /* The raw coprocessor general-purpose registers. These are all 64
535 MEP_FIRST_RAW_CR_REGNUM = 48,
536 MEP_LAST_RAW_CR_REGNUM = MEP_FIRST_RAW_CR_REGNUM + 31,
538 MEP_FIRST_RAW_CCR_REGNUM = 80,
539 MEP_LAST_RAW_CCR_REGNUM = MEP_FIRST_RAW_CCR_REGNUM + 63,
541 /* The module number register. This is the index of the me_module
542 of which the current target is an instance. (This is not a real
543 MeP-specified register; it's provided by SID.) */
546 MEP_LAST_RAW_REGNUM = MEP_MODULE_REGNUM,
548 MEP_NUM_RAW_REGS = MEP_LAST_RAW_REGNUM + 1,
550 /* Pseudoregisters. See mep_pseudo_register_read and
551 mep_pseudo_register_write. */
552 MEP_FIRST_PSEUDO_REGNUM = MEP_NUM_RAW_REGS,
554 /* We have a pseudoregister for every control/special register, to
555 implement registers with read-only bits. */
556 MEP_FIRST_CSR_REGNUM = MEP_FIRST_PSEUDO_REGNUM,
557 MEP_PC_REGNUM = MEP_FIRST_CSR_REGNUM, /* Program counter */
558 MEP_LP_REGNUM, /* Link pointer */
559 MEP_SAR_REGNUM, /* shift amount */
560 MEP_CSR3_REGNUM, /* csr3: reserved */
561 MEP_RPB_REGNUM, /* repeat begin address */
562 MEP_RPE_REGNUM, /* Repeat end address */
563 MEP_RPC_REGNUM, /* Repeat count */
564 MEP_HI_REGNUM, /* Upper 32 bits of the result of 64 bit mult/div */
565 MEP_LO_REGNUM, /* Lower 32 bits of the result of 64 bit mult/div */
566 MEP_CSR9_REGNUM, /* csr3: reserved */
567 MEP_CSR10_REGNUM, /* csr3: reserved */
568 MEP_CSR11_REGNUM, /* csr3: reserved */
569 MEP_MB0_REGNUM, /* modulo begin address 0 */
570 MEP_ME0_REGNUM, /* modulo end address 0 */
571 MEP_MB1_REGNUM, /* modulo begin address 1 */
572 MEP_ME1_REGNUM, /* modulo end address 1 */
573 MEP_PSW_REGNUM, /* program status word */
574 MEP_ID_REGNUM, /* processor ID/revision */
575 MEP_TMP_REGNUM, /* Temporary */
576 MEP_EPC_REGNUM, /* Exception program counter */
577 MEP_EXC_REGNUM, /* exception cause */
578 MEP_CFG_REGNUM, /* processor configuration*/
579 MEP_CSR22_REGNUM, /* csr3: reserved */
580 MEP_NPC_REGNUM, /* Nonmaskable interrupt PC */
581 MEP_DBG_REGNUM, /* debug */
582 MEP_DEPC_REGNUM, /* Debug exception PC */
583 MEP_OPT_REGNUM, /* options */
584 MEP_RCFG_REGNUM, /* local ram config */
585 MEP_CCFG_REGNUM, /* cache config */
586 MEP_CSR29_REGNUM, /* csr3: reserved */
587 MEP_CSR30_REGNUM, /* csr3: reserved */
588 MEP_CSR31_REGNUM, /* csr3: reserved */
589 MEP_LAST_CSR_REGNUM = MEP_CSR31_REGNUM,
591 /* The 32-bit integer view of the coprocessor GPR's. */
592 MEP_FIRST_CR32_REGNUM,
593 MEP_LAST_CR32_REGNUM = MEP_FIRST_CR32_REGNUM + 31,
595 /* The 32-bit floating-point view of the coprocessor GPR's. */
596 MEP_FIRST_FP_CR32_REGNUM,
597 MEP_LAST_FP_CR32_REGNUM = MEP_FIRST_FP_CR32_REGNUM + 31,
599 /* The 64-bit integer view of the coprocessor GPR's. */
600 MEP_FIRST_CR64_REGNUM,
601 MEP_LAST_CR64_REGNUM = MEP_FIRST_CR64_REGNUM + 31,
603 /* The 64-bit floating-point view of the coprocessor GPR's. */
604 MEP_FIRST_FP_CR64_REGNUM,
605 MEP_LAST_FP_CR64_REGNUM = MEP_FIRST_FP_CR64_REGNUM + 31,
607 MEP_FIRST_CCR_REGNUM,
608 MEP_LAST_CCR_REGNUM = MEP_FIRST_CCR_REGNUM + 63,
610 MEP_LAST_PSEUDO_REGNUM = MEP_LAST_CCR_REGNUM,
612 MEP_NUM_PSEUDO_REGS = (MEP_LAST_PSEUDO_REGNUM - MEP_LAST_RAW_REGNUM),
614 MEP_NUM_REGS = MEP_NUM_RAW_REGS + MEP_NUM_PSEUDO_REGS
618 #define IN_SET(set, n) \
619 (MEP_FIRST_ ## set ## _REGNUM <= (n) && (n) <= MEP_LAST_ ## set ## _REGNUM)
621 #define IS_GPR_REGNUM(n) (IN_SET (GPR, (n)))
622 #define IS_RAW_CSR_REGNUM(n) (IN_SET (RAW_CSR, (n)))
623 #define IS_RAW_CR_REGNUM(n) (IN_SET (RAW_CR, (n)))
624 #define IS_RAW_CCR_REGNUM(n) (IN_SET (RAW_CCR, (n)))
626 #define IS_CSR_REGNUM(n) (IN_SET (CSR, (n)))
627 #define IS_CR32_REGNUM(n) (IN_SET (CR32, (n)))
628 #define IS_FP_CR32_REGNUM(n) (IN_SET (FP_CR32, (n)))
629 #define IS_CR64_REGNUM(n) (IN_SET (CR64, (n)))
630 #define IS_FP_CR64_REGNUM(n) (IN_SET (FP_CR64, (n)))
631 #define IS_CR_REGNUM(n) (IS_CR32_REGNUM (n) || IS_FP_CR32_REGNUM (n) \
632 || IS_CR64_REGNUM (n) || IS_FP_CR64_REGNUM (n))
633 #define IS_CCR_REGNUM(n) (IN_SET (CCR, (n)))
635 #define IS_RAW_REGNUM(n) (IN_SET (RAW, (n)))
636 #define IS_PSEUDO_REGNUM(n) (IN_SET (PSEUDO, (n)))
638 #define NUM_REGS_IN_SET(set) \
639 (MEP_LAST_ ## set ## _REGNUM - MEP_FIRST_ ## set ## _REGNUM + 1)
641 #define MEP_GPR_SIZE (4) /* Size of a MeP general-purpose register. */
642 #define MEP_PSW_SIZE (4) /* Size of the PSW register. */
643 #define MEP_LP_SIZE (4) /* Size of the LP register. */
646 /* Many of the control/special registers contain bits that cannot be
647 written to; some are entirely read-only. So we present them all as
650 The following table describes the special properties of each CSR. */
651 struct mep_csr_register
653 /* The number of this CSR's raw register. */
656 /* The number of this CSR's pseudoregister. */
659 /* A mask of the bits that are writeable: if a bit is set here, then
660 it can be modified; if the bit is clear, then it cannot. */
661 LONGEST writeable_bits;
665 /* mep_csr_registers[i] describes the i'th CSR.
666 We just list the register numbers here explicitly to help catch
668 #define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM
669 struct mep_csr_register mep_csr_registers[] = {
670 { CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */
671 { CSR(LP), 0xffffffff },
672 { CSR(SAR), 0x0000003f },
673 { CSR(CSR3), 0xffffffff },
674 { CSR(RPB), 0xfffffffe },
675 { CSR(RPE), 0xffffffff },
676 { CSR(RPC), 0xffffffff },
677 { CSR(HI), 0xffffffff },
678 { CSR(LO), 0xffffffff },
679 { CSR(CSR9), 0xffffffff },
680 { CSR(CSR10), 0xffffffff },
681 { CSR(CSR11), 0xffffffff },
682 { CSR(MB0), 0x0000ffff },
683 { CSR(ME0), 0x0000ffff },
684 { CSR(MB1), 0x0000ffff },
685 { CSR(ME1), 0x0000ffff },
686 { CSR(PSW), 0x000003ff },
687 { CSR(ID), 0x00000000 },
688 { CSR(TMP), 0xffffffff },
689 { CSR(EPC), 0xffffffff },
690 { CSR(EXC), 0x000030f0 },
691 { CSR(CFG), 0x00c0001b },
692 { CSR(CSR22), 0xffffffff },
693 { CSR(NPC), 0xffffffff },
694 { CSR(DBG), 0x00000580 },
695 { CSR(DEPC), 0xffffffff },
696 { CSR(OPT), 0x00000000 },
697 { CSR(RCFG), 0x00000000 },
698 { CSR(CCFG), 0x00000000 },
699 { CSR(CSR29), 0xffffffff },
700 { CSR(CSR30), 0xffffffff },
701 { CSR(CSR31), 0xffffffff },
705 /* If R is the number of a raw register, then mep_raw_to_pseudo[R] is
706 the number of the corresponding pseudoregister. Otherwise,
707 mep_raw_to_pseudo[R] == R. */
708 static int mep_raw_to_pseudo[MEP_NUM_REGS];
710 /* If R is the number of a pseudoregister, then mep_pseudo_to_raw[R]
711 is the number of the underlying raw register. Otherwise
712 mep_pseudo_to_raw[R] == R. */
713 static int mep_pseudo_to_raw[MEP_NUM_REGS];
716 mep_init_pseudoregister_maps (void)
720 /* Verify that mep_csr_registers covers all the CSRs, in order. */
721 gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (CSR));
722 gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (RAW_CSR));
724 /* Verify that the raw and pseudo ranges have matching sizes. */
725 gdb_assert (NUM_REGS_IN_SET (RAW_CSR) == NUM_REGS_IN_SET (CSR));
726 gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR32));
727 gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR64));
728 gdb_assert (NUM_REGS_IN_SET (RAW_CCR) == NUM_REGS_IN_SET (CCR));
730 for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++)
732 struct mep_csr_register *r = &mep_csr_registers[i];
734 gdb_assert (r->pseudo == MEP_FIRST_CSR_REGNUM + i);
735 gdb_assert (r->raw == MEP_FIRST_RAW_CSR_REGNUM + i);
738 /* Set up the initial raw<->pseudo mappings. */
739 for (i = 0; i < MEP_NUM_REGS; i++)
741 mep_raw_to_pseudo[i] = i;
742 mep_pseudo_to_raw[i] = i;
745 /* Add the CSR raw<->pseudo mappings. */
746 for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++)
748 struct mep_csr_register *r = &mep_csr_registers[i];
750 mep_raw_to_pseudo[r->raw] = r->pseudo;
751 mep_pseudo_to_raw[r->pseudo] = r->raw;
754 /* Add the CR raw<->pseudo mappings. */
755 for (i = 0; i < NUM_REGS_IN_SET (RAW_CR); i++)
757 int raw = MEP_FIRST_RAW_CR_REGNUM + i;
758 int pseudo32 = MEP_FIRST_CR32_REGNUM + i;
759 int pseudofp32 = MEP_FIRST_FP_CR32_REGNUM + i;
760 int pseudo64 = MEP_FIRST_CR64_REGNUM + i;
761 int pseudofp64 = MEP_FIRST_FP_CR64_REGNUM + i;
763 /* Truly, the raw->pseudo mapping depends on the current module.
764 But we use the raw->pseudo mapping when we read the debugging
765 info; at that point, we don't know what module we'll actually
766 be running yet. So, we always supply the 64-bit register
767 numbers; GDB knows how to pick a smaller value out of a
768 larger register properly. */
769 mep_raw_to_pseudo[raw] = pseudo64;
770 mep_pseudo_to_raw[pseudo32] = raw;
771 mep_pseudo_to_raw[pseudofp32] = raw;
772 mep_pseudo_to_raw[pseudo64] = raw;
773 mep_pseudo_to_raw[pseudofp64] = raw;
776 /* Add the CCR raw<->pseudo mappings. */
777 for (i = 0; i < NUM_REGS_IN_SET (CCR); i++)
779 int raw = MEP_FIRST_RAW_CCR_REGNUM + i;
780 int pseudo = MEP_FIRST_CCR_REGNUM + i;
781 mep_raw_to_pseudo[raw] = pseudo;
782 mep_pseudo_to_raw[pseudo] = raw;
788 mep_debug_reg_to_regnum (struct gdbarch *gdbarch, int debug_reg)
790 /* The debug info uses the raw register numbers. */
791 return mep_raw_to_pseudo[debug_reg];
795 /* Return the size, in bits, of the coprocessor pseudoregister
798 mep_pseudo_cr_size (int pseudo)
800 if (IS_CR32_REGNUM (pseudo)
801 || IS_FP_CR32_REGNUM (pseudo))
803 else if (IS_CR64_REGNUM (pseudo)
804 || IS_FP_CR64_REGNUM (pseudo))
811 /* If the coprocessor pseudoregister numbered PSEUDO is a
812 floating-point register, return non-zero; if it is an integer
813 register, return zero. */
815 mep_pseudo_cr_is_float (int pseudo)
817 return (IS_FP_CR32_REGNUM (pseudo)
818 || IS_FP_CR64_REGNUM (pseudo));
822 /* Given a coprocessor GPR pseudoregister number, return its index
823 within that register bank. */
825 mep_pseudo_cr_index (int pseudo)
827 if (IS_CR32_REGNUM (pseudo))
828 return pseudo - MEP_FIRST_CR32_REGNUM;
829 else if (IS_FP_CR32_REGNUM (pseudo))
830 return pseudo - MEP_FIRST_FP_CR32_REGNUM;
831 else if (IS_CR64_REGNUM (pseudo))
832 return pseudo - MEP_FIRST_CR64_REGNUM;
833 else if (IS_FP_CR64_REGNUM (pseudo))
834 return pseudo - MEP_FIRST_FP_CR64_REGNUM;
840 /* Return the me_module index describing the current target.
842 If the current target has registers (e.g., simulator, remote
843 target), then this uses the value of the 'module' register, raw
844 register MEP_MODULE_REGNUM. Otherwise, this retrieves the value
845 from the ELF header's e_flags field of the current executable
850 if (target_has_registers)
853 regcache_cooked_read_unsigned (get_current_regcache (),
854 MEP_MODULE_REGNUM, ®val);
858 return gdbarch_tdep (target_gdbarch)->me_module;
862 /* Return the set of options for the current target, in the form that
863 the OPT register would use.
865 If the current target has registers (e.g., simulator, remote
866 target), then this is the actual value of the OPT register. If the
867 current target does not have registers (e.g., an executable file),
868 then use the 'module_opt' field we computed when we build the
869 gdbarch object for this module. */
873 if (target_has_registers)
876 regcache_cooked_read_unsigned (get_current_regcache (),
877 MEP_OPT_REGNUM, ®val);
881 return me_module_opt (current_me_module ());
885 /* Return the width of the current me_module's coprocessor data bus,
886 in bits. This is either 32 or 64. */
888 current_cop_data_bus_width ()
890 return me_module_cop_data_bus_width (current_me_module ());
894 /* Return the keyword table of coprocessor general-purpose register
895 names appropriate for the me_module we're dealing with. */
896 static CGEN_KEYWORD *
899 const CGEN_HW_ENTRY *hw
900 = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR);
902 return register_set_keyword_table (hw);
906 /* Return non-zero if the coprocessor general-purpose registers are
907 floating-point values, zero otherwise. */
909 current_cr_is_float ()
911 const CGEN_HW_ENTRY *hw
912 = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR);
914 return CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE (CGEN_HW_ATTRS (hw));
918 /* Return the keyword table of coprocessor control register names
919 appropriate for the me_module we're dealing with. */
920 static CGEN_KEYWORD *
923 const CGEN_HW_ENTRY *hw
924 = me_module_register_set (current_me_module (), "h-ccr-", HW_H_CCR);
926 return register_set_keyword_table (hw);
931 mep_register_name (struct gdbarch *gdbarch, int regnr)
933 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
935 /* General-purpose registers. */
936 static const char *gpr_names[] = {
937 "r0", "r1", "r2", "r3", /* 0 */
938 "r4", "r5", "r6", "r7", /* 4 */
939 "fp", "r9", "r10", "r11", /* 8 */
940 "r12", "tp", "gp", "sp" /* 12 */
943 /* Special-purpose registers. */
944 static const char *csr_names[] = {
945 "pc", "lp", "sar", "", /* 0 csr3: reserved */
946 "rpb", "rpe", "rpc", "hi", /* 4 */
947 "lo", "", "", "", /* 8 csr9-csr11: reserved */
948 "mb0", "me0", "mb1", "me1", /* 12 */
950 "psw", "id", "tmp", "epc", /* 16 */
951 "exc", "cfg", "", "npc", /* 20 csr22: reserved */
952 "dbg", "depc", "opt", "rcfg", /* 24 */
953 "ccfg", "", "", "" /* 28 csr29-csr31: reserved */
956 if (IS_GPR_REGNUM (regnr))
957 return gpr_names[regnr - MEP_R0_REGNUM];
958 else if (IS_CSR_REGNUM (regnr))
960 /* The 'hi' and 'lo' registers are only present on processors
961 that have the 'MUL' or 'DIV' instructions enabled. */
962 if ((regnr == MEP_HI_REGNUM || regnr == MEP_LO_REGNUM)
963 && (! (current_options () & (MEP_OPT_MUL | MEP_OPT_DIV))))
966 return csr_names[regnr - MEP_FIRST_CSR_REGNUM];
968 else if (IS_CR_REGNUM (regnr))
974 /* Does this module have a coprocessor at all? */
975 if (! (current_options () & MEP_OPT_COP))
978 names = current_cr_names ();
980 /* This module's coprocessor has no general-purpose registers. */
983 cr_size = current_cop_data_bus_width ();
984 if (cr_size != mep_pseudo_cr_size (regnr))
985 /* This module's coprocessor's GPR's are of a different size. */
988 cr_is_float = current_cr_is_float ();
989 /* The extra ! operators ensure we get boolean equality, not
991 if (! cr_is_float != ! mep_pseudo_cr_is_float (regnr))
992 /* This module's coprocessor's GPR's are of a different type. */
995 return register_name_from_keyword (names, mep_pseudo_cr_index (regnr));
997 else if (IS_CCR_REGNUM (regnr))
999 /* Does this module have a coprocessor at all? */
1000 if (! (current_options () & MEP_OPT_COP))
1004 CGEN_KEYWORD *names = current_ccr_names ();
1007 /* This me_module's coprocessor has no control registers. */
1010 return register_name_from_keyword (names, regnr-MEP_FIRST_CCR_REGNUM);
1014 /* It might be nice to give the 'module' register a name, but that
1015 would affect the output of 'info all-registers', which would
1016 disturb the test suites. So we leave it invisible. */
1022 /* Custom register groups for the MeP. */
1023 static struct reggroup *mep_csr_reggroup; /* control/special */
1024 static struct reggroup *mep_cr_reggroup; /* coprocessor general-purpose */
1025 static struct reggroup *mep_ccr_reggroup; /* coprocessor control */
1029 mep_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1030 struct reggroup *group)
1032 /* Filter reserved or unused register numbers. */
1034 const char *name = mep_register_name (gdbarch, regnum);
1036 if (! name || name[0] == '\0')
1040 /* We could separate the GPRs and the CSRs. Toshiba has approved of
1041 the existing behavior, so we'd want to run that by them. */
1042 if (group == general_reggroup)
1043 return (IS_GPR_REGNUM (regnum)
1044 || IS_CSR_REGNUM (regnum));
1046 /* Everything is in the 'all' reggroup, except for the raw CSR's. */
1047 else if (group == all_reggroup)
1048 return (IS_GPR_REGNUM (regnum)
1049 || IS_CSR_REGNUM (regnum)
1050 || IS_CR_REGNUM (regnum)
1051 || IS_CCR_REGNUM (regnum));
1053 /* All registers should be saved and restored, except for the raw
1056 This is probably right if the coprocessor is something like a
1057 floating-point unit, but would be wrong if the coprocessor is
1058 something that does I/O, where register accesses actually cause
1059 externally-visible actions. But I get the impression that the
1060 coprocessor isn't supposed to do things like that --- you'd use a
1061 hardware engine, perhaps. */
1062 else if (group == save_reggroup || group == restore_reggroup)
1063 return (IS_GPR_REGNUM (regnum)
1064 || IS_CSR_REGNUM (regnum)
1065 || IS_CR_REGNUM (regnum)
1066 || IS_CCR_REGNUM (regnum));
1068 else if (group == mep_csr_reggroup)
1069 return IS_CSR_REGNUM (regnum);
1070 else if (group == mep_cr_reggroup)
1071 return IS_CR_REGNUM (regnum);
1072 else if (group == mep_ccr_reggroup)
1073 return IS_CCR_REGNUM (regnum);
1079 static struct type *
1080 mep_register_type (struct gdbarch *gdbarch, int reg_nr)
1082 /* Coprocessor general-purpose registers may be either 32 or 64 bits
1083 long. So for them, the raw registers are always 64 bits long (to
1084 keep the 'g' packet format fixed), and the pseudoregisters vary
1086 if (IS_RAW_CR_REGNUM (reg_nr))
1087 return builtin_type_uint64;
1089 /* Since GDB doesn't allow registers to change type, we have two
1090 banks of pseudoregisters for the coprocessor general-purpose
1091 registers: one that gives a 32-bit view, and one that gives a
1092 64-bit view. We hide or show one or the other depending on the
1094 if (IS_CR_REGNUM (reg_nr))
1096 int size = mep_pseudo_cr_size (reg_nr);
1099 if (mep_pseudo_cr_is_float (reg_nr))
1100 return builtin_type (gdbarch)->builtin_float;
1102 return builtin_type_uint32;
1104 else if (size == 64)
1106 if (mep_pseudo_cr_is_float (reg_nr))
1107 return builtin_type (gdbarch)->builtin_double;
1109 return builtin_type_uint64;
1115 /* All other registers are 32 bits long. */
1117 return builtin_type_uint32;
1122 mep_read_pc (struct regcache *regcache)
1125 regcache_cooked_read_unsigned (regcache, MEP_PC_REGNUM, &pc);
1130 mep_write_pc (struct regcache *regcache, CORE_ADDR pc)
1132 regcache_cooked_write_unsigned (regcache, MEP_PC_REGNUM, pc);
1137 mep_pseudo_cr32_read (struct gdbarch *gdbarch,
1138 struct regcache *regcache,
1142 /* Read the raw register into a 64-bit buffer, and then return the
1143 appropriate end of that buffer. */
1144 int rawnum = mep_pseudo_to_raw[cookednum];
1147 gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64));
1148 gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4);
1149 regcache_raw_read (regcache, rawnum, buf64);
1150 /* Slow, but legible. */
1151 store_unsigned_integer (buf, 4, extract_unsigned_integer (buf64, 8));
1156 mep_pseudo_cr64_read (struct gdbarch *gdbarch,
1157 struct regcache *regcache,
1161 regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf);
1166 mep_pseudo_register_read (struct gdbarch *gdbarch,
1167 struct regcache *regcache,
1171 if (IS_CSR_REGNUM (cookednum)
1172 || IS_CCR_REGNUM (cookednum))
1173 regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf);
1174 else if (IS_CR32_REGNUM (cookednum)
1175 || IS_FP_CR32_REGNUM (cookednum))
1176 mep_pseudo_cr32_read (gdbarch, regcache, cookednum, buf);
1177 else if (IS_CR64_REGNUM (cookednum)
1178 || IS_FP_CR64_REGNUM (cookednum))
1179 mep_pseudo_cr64_read (gdbarch, regcache, cookednum, buf);
1186 mep_pseudo_csr_write (struct gdbarch *gdbarch,
1187 struct regcache *regcache,
1191 int size = register_size (gdbarch, cookednum);
1192 struct mep_csr_register *r
1193 = &mep_csr_registers[cookednum - MEP_FIRST_CSR_REGNUM];
1195 if (r->writeable_bits == 0)
1196 /* A completely read-only register; avoid the read-modify-
1197 write cycle, and juts ignore the entire write. */
1201 /* A partially writeable register; do a read-modify-write cycle. */
1204 ULONGEST mixed_bits;
1206 regcache_raw_read_unsigned (regcache, r->raw, &old_bits);
1207 new_bits = extract_unsigned_integer (buf, size);
1208 mixed_bits = ((r->writeable_bits & new_bits)
1209 | (~r->writeable_bits & old_bits));
1210 regcache_raw_write_unsigned (regcache, r->raw, mixed_bits);
1216 mep_pseudo_cr32_write (struct gdbarch *gdbarch,
1217 struct regcache *regcache,
1221 /* Expand the 32-bit value into a 64-bit value, and write that to
1222 the pseudoregister. */
1223 int rawnum = mep_pseudo_to_raw[cookednum];
1226 gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64));
1227 gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4);
1228 /* Slow, but legible. */
1229 store_unsigned_integer (buf64, 8, extract_unsigned_integer (buf, 4));
1230 regcache_raw_write (regcache, rawnum, buf64);
1235 mep_pseudo_cr64_write (struct gdbarch *gdbarch,
1236 struct regcache *regcache,
1240 regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf);
1245 mep_pseudo_register_write (struct gdbarch *gdbarch,
1246 struct regcache *regcache,
1248 const gdb_byte *buf)
1250 if (IS_CSR_REGNUM (cookednum))
1251 mep_pseudo_csr_write (gdbarch, regcache, cookednum, buf);
1252 else if (IS_CR32_REGNUM (cookednum)
1253 || IS_FP_CR32_REGNUM (cookednum))
1254 mep_pseudo_cr32_write (gdbarch, regcache, cookednum, buf);
1255 else if (IS_CR64_REGNUM (cookednum)
1256 || IS_FP_CR64_REGNUM (cookednum))
1257 mep_pseudo_cr64_write (gdbarch, regcache, cookednum, buf);
1258 else if (IS_CCR_REGNUM (cookednum))
1259 regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf);
1268 /* The mep disassembler needs to know about the section in order to
1271 mep_gdb_print_insn (bfd_vma pc, disassemble_info * info)
1273 struct obj_section * s = find_pc_section (pc);
1277 /* The libopcodes disassembly code uses the section to find the
1278 BFD, the BFD to find the ELF header, the ELF header to find
1279 the me_module index, and the me_module index to select the
1280 right instructions to print. */
1281 info->section = s->the_bfd_section;
1282 info->arch = bfd_arch_mep;
1284 return print_insn_mep (pc, info);
1291 /* Prologue analysis. */
1294 /* The MeP has two classes of instructions: "core" instructions, which
1295 are pretty normal RISC chip stuff, and "coprocessor" instructions,
1296 which are mostly concerned with moving data in and out of
1297 coprocessor registers, and branching on coprocessor condition
1298 codes. There's space in the instruction set for custom coprocessor
1301 Instructions can be 16 or 32 bits long; the top two bits of the
1302 first byte indicate the length. The coprocessor instructions are
1303 mixed in with the core instructions, and there's no easy way to
1304 distinguish them; you have to completely decode them to tell one
1307 The MeP also supports a "VLIW" operation mode, where instructions
1308 always occur in fixed-width bundles. The bundles are either 32
1309 bits or 64 bits long, depending on a fixed configuration flag. You
1310 decode the first part of the bundle as normal; if it's a core
1311 instruction, and there's any space left in the bundle, the
1312 remainder of the bundle is a coprocessor instruction, which will
1313 execute in parallel with the core instruction. If the first part
1314 of the bundle is a coprocessor instruction, it occupies the entire
1317 So, here are all the cases:
1320 Every bundle is four bytes long, and naturally aligned, and can hold
1321 one or two instructions:
1322 - 16-bit core instruction; 16-bit coprocessor instruction
1323 These execute in parallel.
1324 - 32-bit core instruction
1325 - 32-bit coprocessor instruction
1328 Every bundle is eight bytes long, and naturally aligned, and can hold
1329 one or two instructions:
1330 - 16-bit core instruction; 48-bit (!) coprocessor instruction
1331 These execute in parallel.
1332 - 32-bit core instruction; 32-bit coprocessor instruction
1333 These execute in parallel.
1334 - 64-bit coprocessor instruction
1336 Now, the MeP manual doesn't define any 48- or 64-bit coprocessor
1337 instruction, so I don't really know what's up there; perhaps these
1338 are always the user-defined coprocessor instructions. */
1341 /* Return non-zero if PC is in a VLIW code section, zero
1344 mep_pc_in_vliw_section (CORE_ADDR pc)
1346 struct obj_section *s = find_pc_section (pc);
1348 return (s->the_bfd_section->flags & SEC_MEP_VLIW);
1353 /* Set *INSN to the next core instruction at PC, and return the
1354 address of the next instruction.
1356 The MeP instruction encoding is endian-dependent. 16- and 32-bit
1357 instructions are encoded as one or two two-byte parts, and each
1358 part is byte-swapped independently. Thus:
1363 asm ("movu $1, 0x123456");
1364 asm ("sb $1,0x5678($2)");
1365 asm ("clip $1, 19");
1368 compiles to this big-endian code:
1370 0: d1 56 12 34 movu $1,0x123456
1371 4: c1 28 56 78 sb $1,22136($2)
1372 8: f1 01 10 98 clip $1,0x13
1375 and this little-endian code:
1377 0: 56 d1 34 12 movu $1,0x123456
1378 4: 28 c1 78 56 sb $1,22136($2)
1379 8: 01 f1 98 10 clip $1,0x13
1382 Instructions are returned in *INSN in an endian-independent form: a
1383 given instruction always appears in *INSN the same way, regardless
1384 of whether the instruction stream is big-endian or little-endian.
1386 *INSN's most significant 16 bits are the first (i.e., at lower
1387 addresses) 16 bit part of the instruction. Its least significant
1388 16 bits are the second (i.e., higher-addressed) 16 bit part of the
1389 instruction, or zero for a 16-bit instruction. Both 16-bit parts
1390 are fetched using the current endianness.
1392 So, the *INSN values for the instruction sequence above would be
1393 the following, in either endianness:
1395 0xd1561234 movu $1,0x123456
1396 0xc1285678 sb $1,22136($2)
1397 0xf1011098 clip $1,0x13
1400 (In a sense, it would be more natural to return 16-bit instructions
1401 in the least significant 16 bits of *INSN, but that would be
1402 ambiguous. In order to tell whether you're looking at a 16- or a
1403 32-bit instruction, you have to consult the major opcode field ---
1404 the most significant four bits of the instruction's first 16-bit
1405 part. But if we put 16-bit instructions at the least significant
1406 end of *INSN, then you don't know where to find the major opcode
1407 field until you know if it's a 16- or a 32-bit instruction ---
1408 which is where we started.)
1410 If PC points to a core / coprocessor bundle in a VLIW section, set
1411 *INSN to the core instruction, and return the address of the next
1412 bundle. This has the effect of skipping the bundled coprocessor
1413 instruction. That's okay, since coprocessor instructions aren't
1414 significant to prologue analysis --- for the time being,
1418 mep_get_insn (CORE_ADDR pc, long *insn)
1420 int pc_in_vliw_section;
1427 /* Are we in a VLIW section? */
1428 pc_in_vliw_section = mep_pc_in_vliw_section (pc);
1429 if (pc_in_vliw_section)
1431 /* Yes, find out which bundle size. */
1432 vliw_mode = current_options () & (MEP_OPT_VL32 | MEP_OPT_VL64);
1434 /* If PC is in a VLIW section, but the current core doesn't say
1435 that it supports either VLIW mode, then we don't have enough
1436 information to parse the instruction stream it contains.
1437 Since the "undifferentiated" standard core doesn't have
1438 either VLIW mode bit set, this could happen.
1440 But it shouldn't be an error to (say) set a breakpoint in a
1441 VLIW section, if you know you'll never reach it. (Perhaps
1442 you have a script that sets a bunch of standard breakpoints.)
1444 So we'll just return zero here, and hope for the best. */
1445 if (! (vliw_mode & (MEP_OPT_VL32 | MEP_OPT_VL64)))
1448 /* If both VL32 and VL64 are set, that's bogus, too. */
1449 if (vliw_mode == (MEP_OPT_VL32 | MEP_OPT_VL64))
1455 read_memory (pc, buf, sizeof (buf));
1456 *insn = extract_unsigned_integer (buf, 2) << 16;
1458 /* The major opcode --- the top four bits of the first 16-bit
1459 part --- indicates whether this instruction is 16 or 32 bits
1460 long. All 32-bit instructions have a major opcode whose top
1461 two bits are 11; all the rest are 16-bit instructions. */
1462 if ((*insn & 0xc0000000) == 0xc0000000)
1464 /* Fetch the second 16-bit part of the instruction. */
1465 read_memory (pc + 2, buf, sizeof (buf));
1466 *insn = *insn | extract_unsigned_integer (buf, 2);
1469 /* If we're in VLIW code, then the VLIW width determines the address
1470 of the next instruction. */
1473 /* In 32-bit VLIW code, all bundles are 32 bits long. We ignore the
1474 coprocessor half of a core / copro bundle. */
1475 if (vliw_mode == MEP_OPT_VL32)
1478 /* In 64-bit VLIW code, all bundles are 64 bits long. We ignore the
1479 coprocessor half of a core / copro bundle. */
1480 else if (vliw_mode == MEP_OPT_VL64)
1483 /* We'd better be in either core, 32-bit VLIW, or 64-bit VLIW mode. */
1488 /* Otherwise, the top two bits of the major opcode are (again) what
1489 we need to check. */
1490 else if ((*insn & 0xc0000000) == 0xc0000000)
1495 return pc + insn_len;
1499 /* Sign-extend the LEN-bit value N. */
1500 #define SEXT(n, len) ((((int) (n)) ^ (1 << ((len) - 1))) - (1 << ((len) - 1)))
1502 /* Return the LEN-bit field at POS from I. */
1503 #define FIELD(i, pos, len) (((i) >> (pos)) & ((1 << (len)) - 1))
1505 /* Like FIELD, but sign-extend the field's value. */
1506 #define SFIELD(i, pos, len) (SEXT (FIELD ((i), (pos), (len)), (len)))
1509 /* Macros for decoding instructions.
1511 Remember that 16-bit instructions are placed in bits 16..31 of i,
1512 not at the least significant end; this means that the major opcode
1513 field is always in the same place, regardless of the width of the
1514 instruction. As a reminder of this, we show the lower 16 bits of a
1515 16-bit instruction as xxxx_xxxx_xxxx_xxxx. */
1517 /* SB Rn,(Rm) 0000_nnnn_mmmm_1000 */
1518 /* SH Rn,(Rm) 0000_nnnn_mmmm_1001 */
1519 /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 */
1521 /* SW Rn,disp16(Rm) 1100_nnnn_mmmm_1010 dddd_dddd_dddd_dddd */
1522 #define IS_SW(i) (((i) & 0xf00f0000) == 0xc00a0000)
1523 /* SB Rn,disp16(Rm) 1100_nnnn_mmmm_1000 dddd_dddd_dddd_dddd */
1524 #define IS_SB(i) (((i) & 0xf00f0000) == 0xc0080000)
1525 /* SH Rn,disp16(Rm) 1100_nnnn_mmmm_1001 dddd_dddd_dddd_dddd */
1526 #define IS_SH(i) (((i) & 0xf00f0000) == 0xc0090000)
1527 #define SWBH_32_BASE(i) (FIELD (i, 20, 4))
1528 #define SWBH_32_SOURCE(i) (FIELD (i, 24, 4))
1529 #define SWBH_32_OFFSET(i) (SFIELD (i, 0, 16))
1531 /* SW Rn,disp7.align4(SP) 0100_nnnn_0ddd_dd10 xxxx_xxxx_xxxx_xxxx */
1532 #define IS_SW_IMMD(i) (((i) & 0xf0830000) == 0x40020000)
1533 #define SW_IMMD_SOURCE(i) (FIELD (i, 24, 4))
1534 #define SW_IMMD_OFFSET(i) (FIELD (i, 18, 5) << 2)
1536 /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 xxxx_xxxx_xxxx_xxxx */
1537 #define IS_SW_REG(i) (((i) & 0xf00f0000) == 0x000a0000)
1538 #define SW_REG_SOURCE(i) (FIELD (i, 24, 4))
1539 #define SW_REG_BASE(i) (FIELD (i, 20, 4))
1541 /* ADD3 Rl,Rn,Rm 1001_nnnn_mmmm_llll xxxx_xxxx_xxxx_xxxx */
1542 #define IS_ADD3_16_REG(i) (((i) & 0xf0000000) == 0x90000000)
1543 #define ADD3_16_REG_SRC1(i) (FIELD (i, 20, 4)) /* n */
1544 #define ADD3_16_REG_SRC2(i) (FIELD (i, 24, 4)) /* m */
1546 /* ADD3 Rn,Rm,imm16 1100_nnnn_mmmm_0000 iiii_iiii_iiii_iiii */
1547 #define IS_ADD3_32(i) (((i) & 0xf00f0000) == 0xc0000000)
1548 #define ADD3_32_TARGET(i) (FIELD (i, 24, 4))
1549 #define ADD3_32_SOURCE(i) (FIELD (i, 20, 4))
1550 #define ADD3_32_OFFSET(i) (SFIELD (i, 0, 16))
1552 /* ADD3 Rn,SP,imm7.align4 0100_nnnn_0iii_ii00 xxxx_xxxx_xxxx_xxxx */
1553 #define IS_ADD3_16(i) (((i) & 0xf0830000) == 0x40000000)
1554 #define ADD3_16_TARGET(i) (FIELD (i, 24, 4))
1555 #define ADD3_16_OFFSET(i) (FIELD (i, 18, 5) << 2)
1557 /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */
1558 #define IS_ADD(i) (((i) & 0xf0030000) == 0x60000000)
1559 #define ADD_TARGET(i) (FIELD (i, 24, 4))
1560 #define ADD_OFFSET(i) (SFIELD (i, 18, 6))
1562 /* LDC Rn,imm5 0111_nnnn_iiii_101I xxxx_xxxx_xxxx_xxxx
1564 #define IS_LDC(i) (((i) & 0xf00e0000) == 0x700a0000)
1565 #define LDC_IMM(i) ((FIELD (i, 16, 1) << 4) | FIELD (i, 20, 4))
1566 #define LDC_TARGET(i) (FIELD (i, 24, 4))
1568 /* LW Rn,disp16(Rm) 1100_nnnn_mmmm_1110 dddd_dddd_dddd_dddd */
1569 #define IS_LW(i) (((i) & 0xf00f0000) == 0xc00e0000)
1570 #define LW_TARGET(i) (FIELD (i, 24, 4))
1571 #define LW_BASE(i) (FIELD (i, 20, 4))
1572 #define LW_OFFSET(i) (SFIELD (i, 0, 16))
1574 /* MOV Rn,Rm 0000_nnnn_mmmm_0000 xxxx_xxxx_xxxx_xxxx */
1575 #define IS_MOV(i) (((i) & 0xf00f0000) == 0x00000000)
1576 #define MOV_TARGET(i) (FIELD (i, 24, 4))
1577 #define MOV_SOURCE(i) (FIELD (i, 20, 4))
1579 /* BRA disp12.align2 1011_dddd_dddd_ddd0 xxxx_xxxx_xxxx_xxxx */
1580 #define IS_BRA(i) (((i) & 0xf0010000) == 0xb0000000)
1581 #define BRA_DISP(i) (SFIELD (i, 17, 11) << 1)
1584 /* This structure holds the results of a prologue analysis. */
1587 /* The architecture for which we generated this prologue info. */
1588 struct gdbarch *gdbarch;
1590 /* The offset from the frame base to the stack pointer --- always
1593 Calling this a "size" is a bit misleading, but given that the
1594 stack grows downwards, using offsets for everything keeps one
1595 from going completely sign-crazy: you never change anything's
1596 sign for an ADD instruction; always change the second operand's
1597 sign for a SUB instruction; and everything takes care of
1601 /* Non-zero if this function has initialized the frame pointer from
1602 the stack pointer, zero otherwise. */
1605 /* If has_frame_ptr is non-zero, this is the offset from the frame
1606 base to where the frame pointer points. This is always zero or
1608 int frame_ptr_offset;
1610 /* The address of the first instruction at which the frame has been
1611 set up and the arguments are where the debug info says they are
1612 --- as best as we can tell. */
1613 CORE_ADDR prologue_end;
1615 /* reg_offset[R] is the offset from the CFA at which register R is
1616 saved, or 1 if register R has not been saved. (Real values are
1617 always zero or negative.) */
1618 int reg_offset[MEP_NUM_REGS];
1621 /* Return non-zero if VALUE is an incoming argument register. */
1624 is_arg_reg (pv_t value)
1626 return (value.kind == pvk_register
1627 && MEP_R1_REGNUM <= value.reg && value.reg <= MEP_R4_REGNUM
1631 /* Return non-zero if a store of REG's current value VALUE to ADDR is
1632 probably spilling an argument register to its stack slot in STACK.
1633 Such instructions should be included in the prologue, if possible.
1635 The store is a spill if:
1636 - the value being stored is REG's original value;
1637 - the value has not already been stored somewhere in STACK; and
1638 - ADDR is a stack slot's address (e.g., relative to the original
1639 value of the SP). */
1641 is_arg_spill (struct gdbarch *gdbarch, pv_t value, pv_t addr,
1642 struct pv_area *stack)
1644 return (is_arg_reg (value)
1645 && pv_is_register (addr, MEP_SP_REGNUM)
1646 && ! pv_area_find_reg (stack, gdbarch, value.reg, 0));
1650 /* Function for finding saved registers in a 'struct pv_area'; we pass
1651 this to pv_area_scan.
1653 If VALUE is a saved register, ADDR says it was saved at a constant
1654 offset from the frame base, and SIZE indicates that the whole
1655 register was saved, record its offset in RESULT_UNTYPED. */
1657 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value)
1659 struct mep_prologue *result = (struct mep_prologue *) result_untyped;
1661 if (value.kind == pvk_register
1663 && pv_is_register (addr, MEP_SP_REGNUM)
1664 && size == register_size (result->gdbarch, value.reg))
1665 result->reg_offset[value.reg] = addr.k;
1669 /* Analyze a prologue starting at START_PC, going no further than
1670 LIMIT_PC. Fill in RESULT as appropriate. */
1672 mep_analyze_prologue (struct gdbarch *gdbarch,
1673 CORE_ADDR start_pc, CORE_ADDR limit_pc,
1674 struct mep_prologue *result)
1680 pv_t reg[MEP_NUM_REGS];
1681 struct pv_area *stack;
1682 struct cleanup *back_to;
1683 CORE_ADDR after_last_frame_setup_insn = start_pc;
1685 memset (result, 0, sizeof (*result));
1686 result->gdbarch = gdbarch;
1688 for (rn = 0; rn < MEP_NUM_REGS; rn++)
1690 reg[rn] = pv_register (rn, 0);
1691 result->reg_offset[rn] = 1;
1694 stack = make_pv_area (MEP_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1695 back_to = make_cleanup_free_pv_area (stack);
1698 while (pc < limit_pc)
1701 pv_t pre_insn_fp, pre_insn_sp;
1703 next_pc = mep_get_insn (pc, &insn);
1705 /* A zero return from mep_get_insn means that either we weren't
1706 able to read the instruction from memory, or that we don't
1707 have enough information to be able to reliably decode it. So
1708 we'll store here and hope for the best. */
1712 /* Note the current values of the SP and FP, so we can tell if
1713 this instruction changed them, below. */
1714 pre_insn_fp = reg[MEP_FP_REGNUM];
1715 pre_insn_sp = reg[MEP_SP_REGNUM];
1719 int rn = ADD_TARGET (insn);
1720 CORE_ADDR imm6 = ADD_OFFSET (insn);
1722 reg[rn] = pv_add_constant (reg[rn], imm6);
1724 else if (IS_ADD3_16 (insn))
1726 int rn = ADD3_16_TARGET (insn);
1727 int imm7 = ADD3_16_OFFSET (insn);
1729 reg[rn] = pv_add_constant (reg[MEP_SP_REGNUM], imm7);
1731 else if (IS_ADD3_32 (insn))
1733 int rn = ADD3_32_TARGET (insn);
1734 int rm = ADD3_32_SOURCE (insn);
1735 int imm16 = ADD3_32_OFFSET (insn);
1737 reg[rn] = pv_add_constant (reg[rm], imm16);
1739 else if (IS_SW_REG (insn))
1741 int rn = SW_REG_SOURCE (insn);
1742 int rm = SW_REG_BASE (insn);
1744 /* If simulating this store would require us to forget
1745 everything we know about the stack frame in the name of
1746 accuracy, it would be better to just quit now. */
1747 if (pv_area_store_would_trash (stack, reg[rm]))
1750 if (is_arg_spill (gdbarch, reg[rn], reg[rm], stack))
1751 after_last_frame_setup_insn = next_pc;
1753 pv_area_store (stack, reg[rm], 4, reg[rn]);
1755 else if (IS_SW_IMMD (insn))
1757 int rn = SW_IMMD_SOURCE (insn);
1758 int offset = SW_IMMD_OFFSET (insn);
1759 pv_t addr = pv_add_constant (reg[MEP_SP_REGNUM], offset);
1761 /* If simulating this store would require us to forget
1762 everything we know about the stack frame in the name of
1763 accuracy, it would be better to just quit now. */
1764 if (pv_area_store_would_trash (stack, addr))
1767 if (is_arg_spill (gdbarch, reg[rn], addr, stack))
1768 after_last_frame_setup_insn = next_pc;
1770 pv_area_store (stack, addr, 4, reg[rn]);
1772 else if (IS_MOV (insn))
1774 int rn = MOV_TARGET (insn);
1775 int rm = MOV_SOURCE (insn);
1779 if (pv_is_register (reg[rm], rm) && is_arg_reg (reg[rm]))
1780 after_last_frame_setup_insn = next_pc;
1782 else if (IS_SB (insn) || IS_SH (insn) || IS_SW (insn))
1784 int rn = SWBH_32_SOURCE (insn);
1785 int rm = SWBH_32_BASE (insn);
1786 int disp = SWBH_32_OFFSET (insn);
1787 int size = (IS_SB (insn) ? 1
1790 : (gdb_assert (0), 1));
1791 pv_t addr = pv_add_constant (reg[rm], disp);
1793 if (pv_area_store_would_trash (stack, addr))
1796 if (is_arg_spill (gdbarch, reg[rn], addr, stack))
1797 after_last_frame_setup_insn = next_pc;
1799 pv_area_store (stack, addr, size, reg[rn]);
1801 else if (IS_LDC (insn))
1803 int rn = LDC_TARGET (insn);
1804 int cr = LDC_IMM (insn) + MEP_FIRST_CSR_REGNUM;
1808 else if (IS_LW (insn))
1810 int rn = LW_TARGET (insn);
1811 int rm = LW_BASE (insn);
1812 int offset = LW_OFFSET (insn);
1813 pv_t addr = pv_add_constant (reg[rm], offset);
1815 reg[rn] = pv_area_fetch (stack, addr, 4);
1817 else if (IS_BRA (insn) && BRA_DISP (insn) > 0)
1819 /* When a loop appears as the first statement of a function
1820 body, gcc 4.x will use a BRA instruction to branch to the
1821 loop condition checking code. This BRA instruction is
1822 marked as part of the prologue. We therefore set next_pc
1823 to this branch target and also stop the prologue scan.
1824 The instructions at and beyond the branch target should
1825 no longer be associated with the prologue.
1827 Note that we only consider forward branches here. We
1828 presume that a forward branch is being used to skip over
1831 A backwards branch is covered by the default case below.
1832 If we were to encounter a backwards branch, that would
1833 most likely mean that we've scanned through a loop body.
1834 We definitely want to stop the prologue scan when this
1835 happens and that is precisely what is done by the default
1837 next_pc = pc + BRA_DISP (insn);
1838 after_last_frame_setup_insn = next_pc;
1842 /* We've hit some instruction we don't know how to simulate.
1843 Strictly speaking, we should set every value we're
1844 tracking to "unknown". But we'll be optimistic, assume
1845 that we have enough information already, and stop
1849 /* If this instruction changed the FP or decreased the SP (i.e.,
1850 allocated more stack space), then this may be a good place to
1851 declare the prologue finished. However, there are some
1854 - If the instruction just changed the FP back to its original
1855 value, then that's probably a restore instruction. The
1856 prologue should definitely end before that.
1858 - If the instruction increased the value of the SP (that is,
1859 shrunk the frame), then it's probably part of a frame
1860 teardown sequence, and the prologue should end before that. */
1862 if (! pv_is_identical (reg[MEP_FP_REGNUM], pre_insn_fp))
1864 if (! pv_is_register_k (reg[MEP_FP_REGNUM], MEP_FP_REGNUM, 0))
1865 after_last_frame_setup_insn = next_pc;
1867 else if (! pv_is_identical (reg[MEP_SP_REGNUM], pre_insn_sp))
1869 /* The comparison of constants looks odd, there, because .k
1870 is unsigned. All it really means is that the new value
1871 is lower than it was before the instruction. */
1872 if (pv_is_register (pre_insn_sp, MEP_SP_REGNUM)
1873 && pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM)
1874 && ((pre_insn_sp.k - reg[MEP_SP_REGNUM].k)
1875 < (reg[MEP_SP_REGNUM].k - pre_insn_sp.k)))
1876 after_last_frame_setup_insn = next_pc;
1882 /* Is the frame size (offset, really) a known constant? */
1883 if (pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM))
1884 result->frame_size = reg[MEP_SP_REGNUM].k;
1886 /* Was the frame pointer initialized? */
1887 if (pv_is_register (reg[MEP_FP_REGNUM], MEP_SP_REGNUM))
1889 result->has_frame_ptr = 1;
1890 result->frame_ptr_offset = reg[MEP_FP_REGNUM].k;
1893 /* Record where all the registers were saved. */
1894 pv_area_scan (stack, check_for_saved, (void *) result);
1896 result->prologue_end = after_last_frame_setup_insn;
1898 do_cleanups (back_to);
1903 mep_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1906 CORE_ADDR func_addr, func_end;
1907 struct mep_prologue p;
1909 /* Try to find the extent of the function that contains PC. */
1910 if (! find_pc_partial_function (pc, &name, &func_addr, &func_end))
1913 mep_analyze_prologue (gdbarch, pc, func_end, &p);
1914 return p.prologue_end;
1921 static const unsigned char *
1922 mep_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
1924 static unsigned char breakpoint[] = { 0x70, 0x32 };
1925 *lenptr = sizeof (breakpoint);
1931 /* Frames and frame unwinding. */
1934 static struct mep_prologue *
1935 mep_analyze_frame_prologue (struct frame_info *this_frame,
1936 void **this_prologue_cache)
1938 if (! *this_prologue_cache)
1940 CORE_ADDR func_start, stop_addr;
1942 *this_prologue_cache
1943 = FRAME_OBSTACK_ZALLOC (struct mep_prologue);
1945 func_start = get_frame_func (this_frame);
1946 stop_addr = get_frame_pc (this_frame);
1948 /* If we couldn't find any function containing the PC, then
1949 just initialize the prologue cache, but don't do anything. */
1951 stop_addr = func_start;
1953 mep_analyze_prologue (get_frame_arch (this_frame),
1954 func_start, stop_addr, *this_prologue_cache);
1957 return *this_prologue_cache;
1961 /* Given the next frame and a prologue cache, return this frame's
1964 mep_frame_base (struct frame_info *this_frame,
1965 void **this_prologue_cache)
1967 struct mep_prologue *p
1968 = mep_analyze_frame_prologue (this_frame, this_prologue_cache);
1970 /* In functions that use alloca, the distance between the stack
1971 pointer and the frame base varies dynamically, so we can't use
1972 the SP plus static information like prologue analysis to find the
1973 frame base. However, such functions must have a frame pointer,
1974 to be able to restore the SP on exit. So whenever we do have a
1975 frame pointer, use that to find the base. */
1976 if (p->has_frame_ptr)
1979 = get_frame_register_unsigned (this_frame, MEP_FP_REGNUM);
1980 return fp - p->frame_ptr_offset;
1985 = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM);
1986 return sp - p->frame_size;
1992 mep_frame_this_id (struct frame_info *this_frame,
1993 void **this_prologue_cache,
1994 struct frame_id *this_id)
1996 *this_id = frame_id_build (mep_frame_base (this_frame, this_prologue_cache),
1997 get_frame_func (this_frame));
2001 static struct value *
2002 mep_frame_prev_register (struct frame_info *this_frame,
2003 void **this_prologue_cache, int regnum)
2005 struct mep_prologue *p
2006 = mep_analyze_frame_prologue (this_frame, this_prologue_cache);
2008 /* There are a number of complications in unwinding registers on the
2009 MeP, having to do with core functions calling VLIW functions and
2012 The least significant bit of the link register, LP.LTOM, is the
2013 VLIW mode toggle bit: it's set if a core function called a VLIW
2014 function, or vice versa, and clear when the caller and callee
2015 were both in the same mode.
2017 So, if we're asked to unwind the PC, then we really want to
2018 unwind the LP and clear the least significant bit. (Real return
2019 addresses are always even.) And if we want to unwind the program
2020 status word (PSW), we need to toggle PSW.OM if LP.LTOM is set.
2022 Tweaking the register values we return in this way means that the
2023 bits in BUFFERP[] are not the same as the bits you'd find at
2024 ADDRP in the inferior, so we make sure lvalp is not_lval when we
2026 if (regnum == MEP_PC_REGNUM)
2028 struct value *value;
2030 value = mep_frame_prev_register (this_frame, this_prologue_cache,
2032 lp = value_as_long (value);
2033 release_value (value);
2036 return frame_unwind_got_constant (this_frame, regnum, lp & ~1);
2040 CORE_ADDR frame_base = mep_frame_base (this_frame, this_prologue_cache);
2041 struct value *value;
2043 /* Our caller's SP is our frame base. */
2044 if (regnum == MEP_SP_REGNUM)
2045 return frame_unwind_got_constant (this_frame, regnum, frame_base);
2047 /* If prologue analysis says we saved this register somewhere,
2048 return a description of the stack slot holding it. */
2049 if (p->reg_offset[regnum] != 1)
2050 value = frame_unwind_got_memory (this_frame, regnum,
2051 frame_base + p->reg_offset[regnum]);
2053 /* Otherwise, presume we haven't changed the value of this
2054 register, and get it from the next frame. */
2056 value = frame_unwind_got_register (this_frame, regnum, regnum);
2058 /* If we need to toggle the operating mode, do so. */
2059 if (regnum == MEP_PSW_REGNUM)
2063 psw = value_as_long (value);
2064 release_value (value);
2067 /* Get the LP's value, too. */
2068 value = get_frame_register_value (this_frame, MEP_LP_REGNUM);
2069 lp = value_as_long (value);
2070 release_value (value);
2073 /* If LP.LTOM is set, then toggle PSW.OM. */
2077 return frame_unwind_got_constant (this_frame, regnum, psw);
2085 static const struct frame_unwind mep_frame_unwind = {
2088 mep_frame_prev_register,
2090 default_frame_sniffer
2094 /* Our general unwinding function can handle unwinding the PC. */
2096 mep_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2098 return frame_unwind_register_unsigned (next_frame, MEP_PC_REGNUM);
2102 /* Our general unwinding function can handle unwinding the SP. */
2104 mep_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2106 return frame_unwind_register_unsigned (next_frame, MEP_SP_REGNUM);
2111 /* Return values. */
2115 mep_use_struct_convention (struct type *type)
2117 return (TYPE_LENGTH (type) > MEP_GPR_SIZE);
2122 mep_extract_return_value (struct gdbarch *arch,
2124 struct regcache *regcache,
2127 int byte_order = gdbarch_byte_order (arch);
2129 /* Values that don't occupy a full register appear at the less
2130 significant end of the value. This is the offset to where the
2134 /* Return values > MEP_GPR_SIZE bytes are returned in memory,
2135 pointed to by R0. */
2136 gdb_assert (TYPE_LENGTH (type) <= MEP_GPR_SIZE);
2138 if (byte_order == BFD_ENDIAN_BIG)
2139 offset = MEP_GPR_SIZE - TYPE_LENGTH (type);
2143 /* Return values that do fit in a single register are returned in R0. */
2144 regcache_cooked_read_part (regcache, MEP_R0_REGNUM,
2145 offset, TYPE_LENGTH (type),
2151 mep_store_return_value (struct gdbarch *arch,
2153 struct regcache *regcache,
2154 const gdb_byte *valbuf)
2156 int byte_order = gdbarch_byte_order (arch);
2158 /* Values that fit in a single register go in R0. */
2159 if (TYPE_LENGTH (type) <= MEP_GPR_SIZE)
2161 /* Values that don't occupy a full register appear at the least
2162 significant end of the value. This is the offset to where the
2166 if (byte_order == BFD_ENDIAN_BIG)
2167 offset = MEP_GPR_SIZE - TYPE_LENGTH (type);
2171 regcache_cooked_write_part (regcache, MEP_R0_REGNUM,
2172 offset, TYPE_LENGTH (type),
2176 /* Return values larger than a single register are returned in
2177 memory, pointed to by R0. Unfortunately, we can't count on R0
2178 pointing to the return buffer, so we raise an error here. */
2180 error ("GDB cannot set return values larger than four bytes; "
2181 "the Media Processor's\n"
2182 "calling conventions do not provide enough information "
2184 "Try using the 'return' command with no argument.");
2187 static enum return_value_convention
2188 mep_return_value (struct gdbarch *gdbarch, struct type *func_type,
2189 struct type *type, struct regcache *regcache,
2190 gdb_byte *readbuf, const gdb_byte *writebuf)
2192 if (mep_use_struct_convention (type))
2197 /* Although the address of the struct buffer gets passed in R1, it's
2198 returned in R0. Fetch R0's value and then read the memory
2200 regcache_raw_read_unsigned (regcache, MEP_R0_REGNUM, &addr);
2201 read_memory (addr, readbuf, TYPE_LENGTH (type));
2205 /* Return values larger than a single register are returned in
2206 memory, pointed to by R0. Unfortunately, we can't count on R0
2207 pointing to the return buffer, so we raise an error here. */
2208 error ("GDB cannot set return values larger than four bytes; "
2209 "the Media Processor's\n"
2210 "calling conventions do not provide enough information "
2212 "Try using the 'return' command with no argument.");
2214 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2218 mep_extract_return_value (gdbarch, type, regcache, readbuf);
2220 mep_store_return_value (gdbarch, type, regcache, writebuf);
2222 return RETURN_VALUE_REGISTER_CONVENTION;
2226 /* Inferior calls. */
2230 mep_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2232 /* Require word alignment. */
2237 /* From "lang_spec2.txt":
2239 4.2 Calling conventions
2241 4.2.1 Core register conventions
2243 - Parameters should be evaluated from left to right, and they
2244 should be held in $1,$2,$3,$4 in order. The fifth parameter or
2245 after should be held in the stack. If the size is larger than 4
2246 bytes in the first four parameters, the pointer should be held in
2247 the registers instead. If the size is larger than 4 bytes in the
2248 fifth parameter or after, the pointer should be held in the stack.
2250 - Return value of a function should be held in register $0. If the
2251 size of return value is larger than 4 bytes, $1 should hold the
2252 pointer pointing memory that would hold the return value. In this
2253 case, the first parameter should be held in $2, the second one in
2254 $3, and the third one in $4, and the forth parameter or after
2255 should be held in the stack.
2257 [This doesn't say so, but arguments shorter than four bytes are
2258 passed in the least significant end of a four-byte word when
2259 they're passed on the stack.] */
2262 /* Traverse the list of ARGC arguments ARGV; for every ARGV[i] too
2263 large to fit in a register, save it on the stack, and place its
2264 address in COPY[i]. SP is the initial stack pointer; return the
2265 new stack pointer. */
2267 push_large_arguments (CORE_ADDR sp, int argc, struct value **argv,
2272 for (i = 0; i < argc; i++)
2274 unsigned arg_len = TYPE_LENGTH (value_type (argv[i]));
2276 if (arg_len > MEP_GPR_SIZE)
2278 /* Reserve space for the copy, and then round the SP down, to
2279 make sure it's all aligned properly. */
2280 sp = (sp - arg_len) & -4;
2281 write_memory (sp, value_contents (argv[i]), arg_len);
2291 mep_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2292 struct regcache *regcache, CORE_ADDR bp_addr,
2293 int argc, struct value **argv, CORE_ADDR sp,
2295 CORE_ADDR struct_addr)
2297 CORE_ADDR *copy = (CORE_ADDR *) alloca (argc * sizeof (copy[0]));
2298 CORE_ADDR func_addr = find_function_addr (function, NULL);
2301 /* The number of the next register available to hold an argument. */
2304 /* The address of the next stack slot available to hold an argument. */
2305 CORE_ADDR arg_stack;
2307 /* The address of the end of the stack area for arguments. This is
2308 just for error checking. */
2309 CORE_ADDR arg_stack_end;
2311 sp = push_large_arguments (sp, argc, argv, copy);
2313 /* Reserve space for the stack arguments, if any. */
2315 if (argc + (struct_addr ? 1 : 0) > 4)
2316 sp -= ((argc + (struct_addr ? 1 : 0)) - 4) * MEP_GPR_SIZE;
2318 arg_reg = MEP_R1_REGNUM;
2321 /* If we're returning a structure by value, push the pointer to the
2322 buffer as the first argument. */
2325 regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr);
2329 for (i = 0; i < argc; i++)
2331 unsigned arg_size = TYPE_LENGTH (value_type (argv[i]));
2334 /* Arguments that fit in a GPR get expanded to fill the GPR. */
2335 if (arg_size <= MEP_GPR_SIZE)
2336 value = extract_unsigned_integer (value_contents (argv[i]),
2337 TYPE_LENGTH (value_type (argv[i])));
2339 /* Arguments too large to fit in a GPR get copied to the stack,
2340 and we pass a pointer to the copy. */
2344 /* We use $1 -- $4 for passing arguments, then use the stack. */
2345 if (arg_reg <= MEP_R4_REGNUM)
2347 regcache_cooked_write_unsigned (regcache, arg_reg, value);
2352 char buf[MEP_GPR_SIZE];
2353 store_unsigned_integer (buf, MEP_GPR_SIZE, value);
2354 write_memory (arg_stack, buf, MEP_GPR_SIZE);
2355 arg_stack += MEP_GPR_SIZE;
2359 gdb_assert (arg_stack <= arg_stack_end);
2361 /* Set the return address. */
2362 regcache_cooked_write_unsigned (regcache, MEP_LP_REGNUM, bp_addr);
2364 /* Update the stack pointer. */
2365 regcache_cooked_write_unsigned (regcache, MEP_SP_REGNUM, sp);
2371 static struct frame_id
2372 mep_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2374 CORE_ADDR sp = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM);
2375 return frame_id_build (sp, get_frame_pc (this_frame));
2380 /* Initialization. */
2383 static struct gdbarch *
2384 mep_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2386 struct gdbarch *gdbarch;
2387 struct gdbarch_tdep *tdep;
2389 /* Which me_module are we building a gdbarch object for? */
2390 CONFIG_ATTR me_module;
2392 /* If we have a BFD in hand, figure out which me_module it was built
2393 for. Otherwise, use the no-particular-me_module code. */
2396 /* The way to get the me_module code depends on the object file
2397 format. At the moment, we only know how to handle ELF. */
2398 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2399 me_module = elf_elfheader (info.abfd)->e_flags & EF_MEP_INDEX_MASK;
2401 me_module = CONFIG_NONE;
2404 me_module = CONFIG_NONE;
2406 /* If we're setting the architecture from a file, check the
2407 endianness of the file against that of the me_module. */
2410 /* The negations on either side make the comparison treat all
2411 non-zero (true) values as equal. */
2412 if (! bfd_big_endian (info.abfd) != ! me_module_big_endian (me_module))
2414 const char *module_name = me_module_name (me_module);
2415 const char *module_endianness
2416 = me_module_big_endian (me_module) ? "big" : "little";
2417 const char *file_name = bfd_get_filename (info.abfd);
2418 const char *file_endianness
2419 = bfd_big_endian (info.abfd) ? "big" : "little";
2421 fputc_unfiltered ('\n', gdb_stderr);
2423 warning ("the MeP module '%s' is %s-endian, but the executable\n"
2425 module_name, module_endianness,
2426 file_name, file_endianness);
2428 warning ("the selected MeP module is %s-endian, but the "
2431 module_endianness, file_name, file_endianness);
2435 /* Find a candidate among the list of architectures we've created
2436 already. info->bfd_arch_info needs to match, but we also want
2437 the right me_module: the ELF header's e_flags field needs to
2439 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2441 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2442 if (gdbarch_tdep (arches->gdbarch)->me_module == me_module)
2443 return arches->gdbarch;
2445 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
2446 gdbarch = gdbarch_alloc (&info, tdep);
2448 /* Get a CGEN CPU descriptor for this architecture. */
2450 const char *mach_name = info.bfd_arch_info->printable_name;
2451 enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG
2453 : CGEN_ENDIAN_LITTLE);
2455 tdep->cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2456 CGEN_CPU_OPEN_ENDIAN, endian,
2460 tdep->me_module = me_module;
2463 set_gdbarch_read_pc (gdbarch, mep_read_pc);
2464 set_gdbarch_write_pc (gdbarch, mep_write_pc);
2465 set_gdbarch_num_regs (gdbarch, MEP_NUM_RAW_REGS);
2466 set_gdbarch_sp_regnum (gdbarch, MEP_SP_REGNUM);
2467 set_gdbarch_register_name (gdbarch, mep_register_name);
2468 set_gdbarch_register_type (gdbarch, mep_register_type);
2469 set_gdbarch_num_pseudo_regs (gdbarch, MEP_NUM_PSEUDO_REGS);
2470 set_gdbarch_pseudo_register_read (gdbarch, mep_pseudo_register_read);
2471 set_gdbarch_pseudo_register_write (gdbarch, mep_pseudo_register_write);
2472 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum);
2473 set_gdbarch_stab_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum);
2475 set_gdbarch_register_reggroup_p (gdbarch, mep_register_reggroup_p);
2476 reggroup_add (gdbarch, all_reggroup);
2477 reggroup_add (gdbarch, general_reggroup);
2478 reggroup_add (gdbarch, save_reggroup);
2479 reggroup_add (gdbarch, restore_reggroup);
2480 reggroup_add (gdbarch, mep_csr_reggroup);
2481 reggroup_add (gdbarch, mep_cr_reggroup);
2482 reggroup_add (gdbarch, mep_ccr_reggroup);
2485 set_gdbarch_print_insn (gdbarch, mep_gdb_print_insn);
2488 set_gdbarch_breakpoint_from_pc (gdbarch, mep_breakpoint_from_pc);
2489 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2490 set_gdbarch_skip_prologue (gdbarch, mep_skip_prologue);
2492 /* Frames and frame unwinding. */
2493 frame_unwind_append_unwinder (gdbarch, &mep_frame_unwind);
2494 set_gdbarch_unwind_pc (gdbarch, mep_unwind_pc);
2495 set_gdbarch_unwind_sp (gdbarch, mep_unwind_sp);
2496 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2497 set_gdbarch_frame_args_skip (gdbarch, 0);
2499 /* Return values. */
2500 set_gdbarch_return_value (gdbarch, mep_return_value);
2502 /* Inferior function calls. */
2503 set_gdbarch_frame_align (gdbarch, mep_frame_align);
2504 set_gdbarch_push_dummy_call (gdbarch, mep_push_dummy_call);
2505 set_gdbarch_dummy_id (gdbarch, mep_dummy_id);
2510 /* Provide a prototype to silence -Wmissing-prototypes. */
2511 extern initialize_file_ftype _initialize_mep_tdep;
2514 _initialize_mep_tdep (void)
2516 mep_csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
2517 mep_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
2518 mep_ccr_reggroup = reggroup_new ("ccr", USER_REGGROUP);
2520 register_gdbarch_init (bfd_arch_mep, mep_gdbarch_init);
2522 mep_init_pseudoregister_maps ();