1 /* Target-dependent code for Renesas M32R, for GDB.
3 Copyright (C) 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
29 #include "gdb_string.h"
36 #include "arch-utils.h"
38 #include "trad-frame.h"
41 #include "gdb_assert.h"
43 #include "m32r-tdep.h"
47 extern void _initialize_m32r_tdep (void);
50 m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
52 /* Align to the size of an instruction (so that they can safely be
53 pushed onto the stack. */
60 The little endian mode of M32R is unique. In most of architectures,
61 two 16-bit instructions, A and B, are placed as the following:
69 In M32R, they are placed like this:
77 This is because M32R always fetches instructions in 32-bit.
79 The following functions take care of this behavior. */
82 m32r_memory_insert_breakpoint (struct bp_target_info *bp_tgt)
84 CORE_ADDR addr = bp_tgt->placed_address;
87 gdb_byte *contents_cache = bp_tgt->shadow_contents;
88 gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */
90 /* Save the memory contents. */
91 val = target_read_memory (addr & 0xfffffffc, contents_cache, 4);
93 return val; /* return error */
95 bp_tgt->placed_size = bp_tgt->shadow_len = 4;
97 /* Determine appropriate breakpoint contents and size for this address. */
98 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
102 buf[0] = bp_entry[0];
103 buf[1] = bp_entry[1];
104 buf[2] = contents_cache[2] & 0x7f;
105 buf[3] = contents_cache[3];
109 buf[0] = contents_cache[0];
110 buf[1] = contents_cache[1];
111 buf[2] = bp_entry[0];
112 buf[3] = bp_entry[1];
115 else /* little-endian */
119 buf[0] = contents_cache[0];
120 buf[1] = contents_cache[1] & 0x7f;
121 buf[2] = bp_entry[1];
122 buf[3] = bp_entry[0];
126 buf[0] = bp_entry[1];
127 buf[1] = bp_entry[0];
128 buf[2] = contents_cache[2];
129 buf[3] = contents_cache[3];
133 /* Write the breakpoint. */
134 val = target_write_memory (addr & 0xfffffffc, buf, 4);
139 m32r_memory_remove_breakpoint (struct bp_target_info *bp_tgt)
141 CORE_ADDR addr = bp_tgt->placed_address;
144 gdb_byte *contents_cache = bp_tgt->shadow_contents;
146 buf[0] = contents_cache[0];
147 buf[1] = contents_cache[1];
148 buf[2] = contents_cache[2];
149 buf[3] = contents_cache[3];
151 /* Remove parallel bit. */
152 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
154 if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0)
157 else /* little-endian */
159 if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0)
163 /* Write contents. */
164 val = target_write_memory (addr & 0xfffffffc, buf, 4);
168 static const gdb_byte *
169 m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
171 static gdb_byte be_bp_entry[] = { 0x10, 0xf1, 0x70, 0x00 }; /* dpt -> nop */
172 static gdb_byte le_bp_entry[] = { 0x00, 0x70, 0xf1, 0x10 }; /* dpt -> nop */
175 /* Determine appropriate breakpoint. */
176 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
178 if ((*pcptr & 3) == 0)
191 if ((*pcptr & 3) == 0)
198 bp = le_bp_entry + 2;
207 char *m32r_register_names[] = {
208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
209 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",
210 "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",
215 m32r_register_name (struct gdbarch *gdbarch, int reg_nr)
219 if (reg_nr >= M32R_NUM_REGS)
221 return m32r_register_names[reg_nr];
225 /* Return the GDB type object for the "standard" data type
226 of data in register N. */
229 m32r_register_type (struct gdbarch *gdbarch, int reg_nr)
231 if (reg_nr == M32R_PC_REGNUM)
232 return builtin_type_void_func_ptr;
233 else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM)
234 return builtin_type_void_data_ptr;
236 return builtin_type_int32;
240 /* Write into appropriate registers a function return value
241 of type TYPE, given in virtual format.
243 Things always get returned in RET1_REGNUM, RET2_REGNUM. */
246 m32r_store_return_value (struct type *type, struct regcache *regcache,
250 int len = TYPE_LENGTH (type);
252 regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len);
253 regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval);
257 regval = extract_unsigned_integer ((gdb_byte *) valbuf + 4, len - 4);
258 regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval);
262 /* This is required by skip_prologue. The results of decoding a prologue
263 should be cached because this thrashing is getting nuts. */
266 decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit,
267 CORE_ADDR *pl_endptr, unsigned long *framelength)
269 unsigned long framesize;
272 CORE_ADDR after_prologue = 0;
273 CORE_ADDR after_push = 0;
274 CORE_ADDR after_stack_adjust = 0;
275 CORE_ADDR current_pc;
276 LONGEST return_value;
281 for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2)
283 /* Check if current pc's location is readable. */
284 if (!safe_read_memory_integer (current_pc, 2, &return_value))
287 insn = read_memory_unsigned_integer (current_pc, 2);
292 /* If this is a 32 bit instruction, we dont want to examine its
293 immediate data as though it were an instruction */
294 if (current_pc & 0x02)
296 /* decode this instruction further */
303 if (current_pc == scan_limit)
304 scan_limit += 2; /* extend the search */
306 current_pc += 2; /* skip the immediate data */
308 /* Check if current pc's location is readable. */
309 if (!safe_read_memory_integer (current_pc, 2, &return_value))
312 if (insn == 0x8faf) /* add3 sp, sp, xxxx */
313 /* add 16 bit sign-extended offset */
316 -((short) read_memory_unsigned_integer (current_pc, 2));
320 if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */
321 && safe_read_memory_integer (current_pc + 2, 2,
323 && read_memory_unsigned_integer (current_pc + 2,
325 /* subtract 24 bit sign-extended negative-offset */
327 insn = read_memory_unsigned_integer (current_pc - 2, 4);
328 if (insn & 0x00800000) /* sign extend */
329 insn |= 0xff000000; /* negative */
331 insn &= 0x00ffffff; /* positive */
335 after_push = current_pc + 2;
339 op1 = insn & 0xf000; /* isolate just the first nibble */
341 if ((insn & 0xf0ff) == 0x207f)
345 regno = ((insn >> 8) & 0xf);
349 if ((insn >> 8) == 0x4f) /* addi sp, xx */
350 /* add 8 bit sign-extended offset */
352 int stack_adjust = (signed char) (insn & 0xff);
354 /* there are probably two of these stack adjustments:
355 1) A negative one in the prologue, and
356 2) A positive one in the epilogue.
357 We are only interested in the first one. */
359 if (stack_adjust < 0)
361 framesize -= stack_adjust;
363 /* A frameless function may have no "mv fp, sp".
364 In that case, this is the end of the prologue. */
365 after_stack_adjust = current_pc + 2;
371 after_prologue = current_pc + 2;
372 break; /* end of stack adjustments */
375 /* Nop looks like a branch, continue explicitly */
378 after_prologue = current_pc + 2;
379 continue; /* nop occurs between pushes */
381 /* End of prolog if any of these are trap instructions */
382 if ((insn & 0xfff0) == 0x10f0)
384 after_prologue = current_pc;
387 /* End of prolog if any of these are branch instructions */
388 if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000))
390 after_prologue = current_pc;
393 /* Some of the branch instructions are mixed with other types */
396 int subop = insn & 0x0ff0;
397 if ((subop == 0x0ec0) || (subop == 0x0fc0))
399 after_prologue = current_pc;
400 continue; /* jmp , jl */
406 *framelength = framesize;
408 if (current_pc >= scan_limit)
412 if (after_stack_adjust != 0)
413 /* We did not find a "mv fp,sp", but we DID find
414 a stack_adjust. Is it safe to use that as the
415 end of the prologue? I just don't know. */
417 *pl_endptr = after_stack_adjust;
419 else if (after_push != 0)
420 /* We did not find a "mv fp,sp", but we DID find
421 a push. Is it safe to use that as the
422 end of the prologue? I just don't know. */
424 *pl_endptr = after_push;
427 /* We reached the end of the loop without finding the end
428 of the prologue. No way to win -- we should report failure.
429 The way we do that is to return the original start_pc.
430 GDB will set a breakpoint at the start of the function (etc.) */
431 *pl_endptr = start_pc;
436 if (after_prologue == 0)
437 after_prologue = current_pc;
440 *pl_endptr = after_prologue;
443 } /* decode_prologue */
445 /* Function: skip_prologue
446 Find end of function prologue */
448 #define DEFAULT_SEARCH_LIMIT 128
451 m32r_skip_prologue (CORE_ADDR pc)
453 CORE_ADDR func_addr, func_end;
454 struct symtab_and_line sal;
455 LONGEST return_value;
457 /* See what the symbol table says */
459 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
461 sal = find_pc_line (func_addr, 0);
463 if (sal.line != 0 && sal.end <= func_end)
468 /* Either there's no line info, or the line after the prologue is after
469 the end of the function. In this case, there probably isn't a
472 func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT);
476 func_end = pc + DEFAULT_SEARCH_LIMIT;
478 /* If pc's location is not readable, just quit. */
479 if (!safe_read_memory_integer (pc, 4, &return_value))
482 /* Find the end of prologue. */
483 if (decode_prologue (pc, func_end, &sal.end, NULL) < 0)
489 struct m32r_unwind_cache
491 /* The previous frame's inner most stack address. Used as this
492 frame ID's stack_addr. */
494 /* The frame's base, optionally used by the high-level debug info. */
497 /* How far the SP and r13 (FP) have been offset from the start of
498 the stack frame (as defined by the previous frame's stack
503 /* Table indicating the location of each and every register. */
504 struct trad_frame_saved_reg *saved_regs;
507 /* Put here the code to store, into fi->saved_regs, the addresses of
508 the saved registers of frame described by FRAME_INFO. This
509 includes special registers such as pc and fp saved in special ways
510 in the stack frame. sp is even more special: the address we return
511 for it IS the sp for the next frame. */
513 static struct m32r_unwind_cache *
514 m32r_frame_unwind_cache (struct frame_info *next_frame,
515 void **this_prologue_cache)
517 CORE_ADDR pc, scan_limit;
520 unsigned long op, op2;
522 struct m32r_unwind_cache *info;
525 if ((*this_prologue_cache))
526 return (*this_prologue_cache);
528 info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache);
529 (*this_prologue_cache) = info;
530 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
534 info->uses_frame = 0;
536 scan_limit = frame_pc_unwind (next_frame);
537 for (pc = frame_func_unwind (next_frame, NORMAL_FRAME);
538 pc > 0 && pc < scan_limit; pc += 2)
542 op = get_frame_memory_unsigned (next_frame, pc, 4);
543 if ((op & 0x80000000) == 0x80000000)
545 /* 32-bit instruction */
546 if ((op & 0xffff0000) == 0x8faf0000)
548 /* add3 sp,sp,xxxx */
549 short n = op & 0xffff;
550 info->sp_offset += n;
552 else if (((op >> 8) == 0xe4)
553 && get_frame_memory_unsigned (next_frame, pc + 2,
556 /* ld24 r4, xxxxxx; sub sp, r4 */
557 unsigned long n = op & 0xffffff;
558 info->sp_offset += n;
559 pc += 2; /* skip sub instruction */
562 if (pc == scan_limit)
563 scan_limit += 2; /* extend the search */
564 pc += 2; /* skip the immediate data */
569 /* 16-bit instructions */
570 op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff;
571 if ((op & 0xf0ff) == 0x207f)
574 int regno = ((op >> 8) & 0xf);
575 info->sp_offset -= 4;
576 info->saved_regs[regno].addr = info->sp_offset;
578 else if ((op & 0xff00) == 0x4f00)
581 int n = (signed char) (op & 0xff);
582 info->sp_offset += n;
584 else if (op == 0x1d8f)
587 info->uses_frame = 1;
588 info->r13_offset = info->sp_offset;
589 break; /* end of stack adjustments */
591 else if ((op & 0xfff0) == 0x10f0)
593 /* end of prologue if this is a trap instruction */
594 break; /* end of stack adjustments */
598 info->size = -info->sp_offset;
600 /* Compute the previous frame's stack pointer (which is also the
601 frame's ID's stack address), and this frame's base pointer. */
602 if (info->uses_frame)
604 /* The SP was moved to the FP. This indicates that a new frame
605 was created. Get THIS frame's FP value by unwinding it from
607 this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM);
608 /* The FP points at the last saved register. Adjust the FP back
609 to before the first saved register giving the SP. */
610 prev_sp = this_base + info->size;
614 /* Assume that the FP is this frame's SP but with that pushed
615 stack space added back. */
616 this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
617 prev_sp = this_base + info->size;
620 /* Convert that SP/BASE into real addresses. */
621 info->prev_sp = prev_sp;
622 info->base = this_base;
624 /* Adjust all the saved registers so that they contain addresses and
626 for (i = 0; i < gdbarch_num_regs (get_frame_arch (next_frame)) - 1; i++)
627 if (trad_frame_addr_p (info->saved_regs, i))
628 info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr);
630 /* The call instruction moves the caller's PC in the callee's LR.
631 Since this is an unwind, do the reverse. Copy the location of LR
632 into PC (the address / regnum) so that a request for PC will be
633 converted into a request for the LR. */
634 info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM];
636 /* The previous frame's SP needed to be computed. Save the computed
638 trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp);
644 m32r_read_pc (struct regcache *regcache)
647 regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc);
652 m32r_write_pc (struct regcache *regcache, CORE_ADDR val)
654 regcache_cooked_write_unsigned (regcache, M32R_PC_REGNUM, val);
658 m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
660 return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
665 m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
666 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
667 struct value **args, CORE_ADDR sp, int struct_return,
668 CORE_ADDR struct_addr)
670 int stack_offset, stack_alloc;
671 int argreg = ARG1_REGNUM;
674 enum type_code typecode;
677 gdb_byte valbuf[MAX_REGISTER_SIZE];
679 int odd_sized_struct;
681 /* first force sp to a 4-byte alignment */
684 /* Set the return address. For the m32r, the return breakpoint is
685 always at BP_ADDR. */
686 regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr);
688 /* If STRUCT_RETURN is true, then the struct return address (in
689 STRUCT_ADDR) will consume the first argument-passing register.
690 Both adjust the register count and store that value. */
693 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
697 /* Now make sure there's space on the stack */
698 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
699 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3);
700 sp -= stack_alloc; /* make room on stack for args */
702 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
704 type = value_type (args[argnum]);
705 typecode = TYPE_CODE (type);
706 len = TYPE_LENGTH (type);
708 memset (valbuf, 0, sizeof (valbuf));
710 /* Passes structures that do not fit in 2 registers by reference. */
712 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
714 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum]));
715 typecode = TYPE_CODE_PTR;
721 /* value gets right-justified in the register or stack word */
722 memcpy (valbuf + (register_size (gdbarch, argreg) - len),
723 (gdb_byte *) value_contents (args[argnum]), len);
727 val = (gdb_byte *) value_contents (args[argnum]);
731 if (argreg > ARGN_REGNUM)
733 /* must go on the stack */
734 write_memory (sp + stack_offset, val, 4);
737 else if (argreg <= ARGN_REGNUM)
739 /* there's room in a register */
741 extract_unsigned_integer (val,
742 register_size (gdbarch, argreg));
743 regcache_cooked_write_unsigned (regcache, argreg++, regval);
746 /* Store the value 4 bytes at a time. This means that things
747 larger than 4 bytes may go partly in registers and partly
749 len -= register_size (gdbarch, argreg);
750 val += register_size (gdbarch, argreg);
754 /* Finally, update the SP register. */
755 regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp);
761 /* Given a return value in `regbuf' with a type `valtype',
762 extract and copy its value into `valbuf'. */
765 m32r_extract_return_value (struct type *type, struct regcache *regcache,
768 bfd_byte *valbuf = dst;
769 int len = TYPE_LENGTH (type);
772 /* By using store_unsigned_integer we avoid having to do
773 anything special for small big-endian values. */
774 regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp);
775 store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp);
777 /* Ignore return values more than 8 bytes in size because the m32r
778 returns anything more than 8 bytes in the stack. */
781 regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp);
782 store_unsigned_integer (valbuf + len - 4, 4, tmp);
786 enum return_value_convention
787 m32r_return_value (struct gdbarch *gdbarch, struct type *valtype,
788 struct regcache *regcache, gdb_byte *readbuf,
789 const gdb_byte *writebuf)
791 if (TYPE_LENGTH (valtype) > 8)
792 return RETURN_VALUE_STRUCT_CONVENTION;
796 m32r_extract_return_value (valtype, regcache, readbuf);
797 if (writebuf != NULL)
798 m32r_store_return_value (valtype, regcache, writebuf);
799 return RETURN_VALUE_REGISTER_CONVENTION;
806 m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
808 return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM);
811 /* Given a GDB frame, determine the address of the calling function's
812 frame. This will be used to create a new GDB frame struct. */
815 m32r_frame_this_id (struct frame_info *next_frame,
816 void **this_prologue_cache, struct frame_id *this_id)
818 struct m32r_unwind_cache *info
819 = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
822 struct minimal_symbol *msym_stack;
825 /* The FUNC is easy. */
826 func = frame_func_unwind (next_frame, NORMAL_FRAME);
828 /* Check if the stack is empty. */
829 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
830 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
833 /* Hopefully the prologue analysis either correctly determined the
834 frame's base (which is the SP from the previous frame), or set
835 that base to "NULL". */
836 base = info->prev_sp;
840 id = frame_id_build (base, func);
845 m32r_frame_prev_register (struct frame_info *next_frame,
846 void **this_prologue_cache,
847 int regnum, int *optimizedp,
848 enum lval_type *lvalp, CORE_ADDR *addrp,
849 int *realnump, gdb_byte *bufferp)
851 struct m32r_unwind_cache *info
852 = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
853 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
854 optimizedp, lvalp, addrp, realnump, bufferp);
857 static const struct frame_unwind m32r_frame_unwind = {
860 m32r_frame_prev_register
863 static const struct frame_unwind *
864 m32r_frame_sniffer (struct frame_info *next_frame)
866 return &m32r_frame_unwind;
870 m32r_frame_base_address (struct frame_info *next_frame, void **this_cache)
872 struct m32r_unwind_cache *info
873 = m32r_frame_unwind_cache (next_frame, this_cache);
877 static const struct frame_base m32r_frame_base = {
879 m32r_frame_base_address,
880 m32r_frame_base_address,
881 m32r_frame_base_address
884 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
885 dummy frame. The frame ID's base needs to match the TOS value
886 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
889 static struct frame_id
890 m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
892 return frame_id_build (m32r_unwind_sp (gdbarch, next_frame),
893 frame_pc_unwind (next_frame));
897 static gdbarch_init_ftype m32r_gdbarch_init;
899 static struct gdbarch *
900 m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
902 struct gdbarch *gdbarch;
903 struct gdbarch_tdep *tdep;
905 /* If there is already a candidate, use it. */
906 arches = gdbarch_list_lookup_by_info (arches, &info);
908 return arches->gdbarch;
910 /* Allocate space for the new architecture. */
911 tdep = XMALLOC (struct gdbarch_tdep);
912 gdbarch = gdbarch_alloc (&info, tdep);
914 set_gdbarch_read_pc (gdbarch, m32r_read_pc);
915 set_gdbarch_write_pc (gdbarch, m32r_write_pc);
916 set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);
918 set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS);
919 set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM);
920 set_gdbarch_register_name (gdbarch, m32r_register_name);
921 set_gdbarch_register_type (gdbarch, m32r_register_type);
923 set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call);
924 set_gdbarch_return_value (gdbarch, m32r_return_value);
926 set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);
927 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
928 set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc);
929 set_gdbarch_memory_insert_breakpoint (gdbarch,
930 m32r_memory_insert_breakpoint);
931 set_gdbarch_memory_remove_breakpoint (gdbarch,
932 m32r_memory_remove_breakpoint);
934 set_gdbarch_frame_align (gdbarch, m32r_frame_align);
936 frame_base_set_default (gdbarch, &m32r_frame_base);
938 /* Methods for saving / extracting a dummy frame's ID. The ID's
939 stack address must match the SP value returned by
940 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */
941 set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id);
943 /* Return the unwound PC value. */
944 set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc);
946 set_gdbarch_print_insn (gdbarch, print_insn_m32r);
948 /* Hook in ABI-specific overrides, if they have been registered. */
949 gdbarch_init_osabi (info, gdbarch);
951 /* Hook in the default unwinders. */
952 frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer);
954 /* Support simple overlay manager. */
955 set_gdbarch_overlay_update (gdbarch, simple_overlay_update);
961 _initialize_m32r_tdep (void)
963 register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init);