1 /* Target-dependent code for Renesas M32R, for GDB.
3 Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
31 #include "gdb_string.h"
37 #include "arch-utils.h"
39 #include "trad-frame.h"
42 #include "gdb_assert.h"
44 #include "m32r-tdep.h"
48 extern void _initialize_m32r_tdep (void);
51 m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
53 /* Align to the size of an instruction (so that they can safely be
54 pushed onto the stack. */
58 /* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
59 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
60 is the type (which is known to be struct, union or array).
62 The m32r returns anything less than 8 bytes in size in
66 m32r_use_struct_convention (int gcc_p, struct type *type)
68 return (TYPE_LENGTH (type) > 8);
73 #define M32R_BE_BREAKPOINT32 {0x10, 0xf1, 0x70, 0x00}
74 #define M32R_LE_BREAKPOINT32 {0xf1, 0x10, 0x00, 0x70}
75 #define M32R_BE_BREAKPOINT16 {0x10, 0xf1}
76 #define M32R_LE_BREAKPOINT16 {0xf1, 0x10}
79 m32r_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
85 bplen = (addr & 3) ? 2 : 4;
87 /* Save the memory contents. */
88 val = target_read_memory (addr, contents_cache, bplen);
90 return val; /* return error */
92 /* Determine appropriate breakpoint contents and size for this address. */
93 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
96 && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80)))
98 static unsigned char insn[] = M32R_BE_BREAKPOINT32;
100 bplen = sizeof (insn);
104 static unsigned char insn[] = M32R_BE_BREAKPOINT16;
106 bplen = sizeof (insn);
110 { /* little-endian */
111 if (((addr & 3) == 0)
112 && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80)))
114 static unsigned char insn[] = M32R_LE_BREAKPOINT32;
116 bplen = sizeof (insn);
120 static unsigned char insn[] = M32R_LE_BREAKPOINT16;
122 bplen = sizeof (insn);
126 /* Write the breakpoint. */
127 val = target_write_memory (addr, (char *) bp, bplen);
132 m32r_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
137 /* Determine appropriate breakpoint contents and size for this address. */
138 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
140 if (((addr & 3) == 0)
141 && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80)))
143 static unsigned char insn[] = M32R_BE_BREAKPOINT32;
144 bplen = sizeof (insn);
148 static unsigned char insn[] = M32R_BE_BREAKPOINT16;
149 bplen = sizeof (insn);
155 if (((addr & 3) == 0)
156 && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80)))
158 static unsigned char insn[] = M32R_BE_BREAKPOINT32;
159 bplen = sizeof (insn);
163 static unsigned char insn[] = M32R_BE_BREAKPOINT16;
164 bplen = sizeof (insn);
168 /* Write contents. */
169 val = target_write_memory (addr, contents_cache, bplen);
173 static const unsigned char *
174 m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
178 /* Determine appropriate breakpoint. */
179 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
181 if ((*pcptr & 3) == 0)
183 static unsigned char insn[] = M32R_BE_BREAKPOINT32;
185 *lenptr = sizeof (insn);
189 static unsigned char insn[] = M32R_BE_BREAKPOINT16;
191 *lenptr = sizeof (insn);
196 if ((*pcptr & 3) == 0)
198 static unsigned char insn[] = M32R_LE_BREAKPOINT32;
200 *lenptr = sizeof (insn);
204 static unsigned char insn[] = M32R_LE_BREAKPOINT16;
206 *lenptr = sizeof (insn);
214 char *m32r_register_names[] = {
215 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
216 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",
217 "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",
222 m32r_register_name (int reg_nr)
226 if (reg_nr >= M32R_NUM_REGS)
228 return m32r_register_names[reg_nr];
232 /* Return the GDB type object for the "standard" data type
233 of data in register N. */
236 m32r_register_type (struct gdbarch *gdbarch, int reg_nr)
238 if (reg_nr == M32R_PC_REGNUM)
239 return builtin_type_void_func_ptr;
240 else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM)
241 return builtin_type_void_data_ptr;
243 return builtin_type_int32;
247 /* Write into appropriate registers a function return value
248 of type TYPE, given in virtual format.
250 Things always get returned in RET1_REGNUM, RET2_REGNUM. */
253 m32r_store_return_value (struct type *type, struct regcache *regcache,
257 int len = TYPE_LENGTH (type);
259 regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len);
260 regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval);
264 regval = extract_unsigned_integer ((char *) valbuf + 4, len - 4);
265 regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval);
269 /* Extract from an array REGBUF containing the (raw) register state
270 the address in which a function should return its structure value,
271 as a CORE_ADDR (or an expression that can be used as one). */
274 m32r_extract_struct_value_address (struct regcache *regcache)
277 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr);
282 /* This is required by skip_prologue. The results of decoding a prologue
283 should be cached because this thrashing is getting nuts. */
286 decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit,
287 CORE_ADDR *pl_endptr)
289 unsigned long framesize;
292 int maybe_one_more = 0;
293 CORE_ADDR after_prologue = 0;
294 CORE_ADDR after_stack_adjust = 0;
295 CORE_ADDR current_pc;
300 for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2)
302 insn = read_memory_unsigned_integer (current_pc, 2);
304 /* If this is a 32 bit instruction, we dont want to examine its
305 immediate data as though it were an instruction */
306 if (current_pc & 0x02)
308 /* Clear the parallel execution bit from 16 bit instruction */
311 /* The last instruction was a branch, usually terminates
312 the series, but if this is a parallel instruction,
313 it may be a stack framing instruction */
314 if (!(insn & 0x8000))
316 /* nope, we are really done */
320 /* decode this instruction further */
326 break; /* This isnt the one more */
329 if (current_pc == scan_limit)
330 scan_limit += 2; /* extend the search */
331 current_pc += 2; /* skip the immediate data */
332 if (insn == 0x8faf) /* add3 sp, sp, xxxx */
333 /* add 16 bit sign-extended offset */
336 -((short) read_memory_unsigned_integer (current_pc, 2));
340 if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */
341 && read_memory_unsigned_integer (current_pc + 2,
343 /* subtract 24 bit sign-extended negative-offset */
345 insn = read_memory_unsigned_integer (current_pc - 2, 4);
346 if (insn & 0x00800000) /* sign extend */
347 insn |= 0xff000000; /* negative */
349 insn &= 0x00ffffff; /* positive */
353 after_prologue = current_pc;
357 op1 = insn & 0xf000; /* isolate just the first nibble */
359 if ((insn & 0xf0ff) == 0x207f)
363 regno = ((insn >> 8) & 0xf);
367 if ((insn >> 8) == 0x4f) /* addi sp, xx */
368 /* add 8 bit sign-extended offset */
370 int stack_adjust = (char) (insn & 0xff);
372 /* there are probably two of these stack adjustments:
373 1) A negative one in the prologue, and
374 2) A positive one in the epilogue.
375 We are only interested in the first one. */
377 if (stack_adjust < 0)
379 framesize -= stack_adjust;
381 /* A frameless function may have no "mv fp, sp".
382 In that case, this is the end of the prologue. */
383 after_stack_adjust = current_pc + 2;
389 after_prologue = current_pc + 2;
390 break; /* end of stack adjustments */
392 /* Nop looks like a branch, continue explicitly */
395 after_prologue = current_pc + 2;
396 continue; /* nop occurs between pushes */
398 /* End of prolog if any of these are branch instructions */
399 if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000))
401 after_prologue = current_pc;
405 /* Some of the branch instructions are mixed with other types */
408 int subop = insn & 0x0ff0;
409 if ((subop == 0x0ec0) || (subop == 0x0fc0))
411 after_prologue = current_pc;
413 continue; /* jmp , jl */
418 if (current_pc >= scan_limit)
422 if (after_stack_adjust != 0)
423 /* We did not find a "mv fp,sp", but we DID find
424 a stack_adjust. Is it safe to use that as the
425 end of the prologue? I just don't know. */
427 *pl_endptr = after_stack_adjust;
430 /* We reached the end of the loop without finding the end
431 of the prologue. No way to win -- we should report failure.
432 The way we do that is to return the original start_pc.
433 GDB will set a breakpoint at the start of the function (etc.) */
434 *pl_endptr = start_pc;
438 if (after_prologue == 0)
439 after_prologue = current_pc;
442 *pl_endptr = after_prologue;
443 } /* decode_prologue */
445 /* Function: skip_prologue
446 Find end of function prologue */
448 #define DEFAULT_SEARCH_LIMIT 44
451 m32r_skip_prologue (CORE_ADDR pc)
453 CORE_ADDR func_addr, func_end;
454 struct symtab_and_line sal;
456 /* See what the symbol table says */
458 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
460 sal = find_pc_line (func_addr, 0);
462 if (sal.line != 0 && sal.end <= func_end)
467 /* Either there's no line info, or the line after the prologue is after
468 the end of the function. In this case, there probably isn't a
471 func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT);
475 func_end = pc + DEFAULT_SEARCH_LIMIT;
476 decode_prologue (pc, func_end, &sal.end);
481 struct m32r_unwind_cache
483 /* The previous frame's inner most stack address. Used as this
484 frame ID's stack_addr. */
486 /* The frame's base, optionally used by the high-level debug info. */
489 /* How far the SP and r13 (FP) have been offset from the start of
490 the stack frame (as defined by the previous frame's stack
495 /* Table indicating the location of each and every register. */
496 struct trad_frame_saved_reg *saved_regs;
499 /* Put here the code to store, into fi->saved_regs, the addresses of
500 the saved registers of frame described by FRAME_INFO. This
501 includes special registers such as pc and fp saved in special ways
502 in the stack frame. sp is even more special: the address we return
503 for it IS the sp for the next frame. */
505 static struct m32r_unwind_cache *
506 m32r_frame_unwind_cache (struct frame_info *next_frame,
507 void **this_prologue_cache)
514 struct m32r_unwind_cache *info;
516 if ((*this_prologue_cache))
517 return (*this_prologue_cache);
519 info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache);
520 (*this_prologue_cache) = info;
521 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
526 info->uses_frame = 0;
527 for (pc = frame_func_unwind (next_frame);
528 pc > 0 && pc < frame_pc_unwind (next_frame); pc += 2)
532 op = get_frame_memory_unsigned (next_frame, pc, 4);
533 if ((op & 0x80000000) == 0x80000000)
535 /* 32-bit instruction */
536 if ((op & 0xffff0000) == 0x8faf0000)
538 /* add3 sp,sp,xxxx */
539 short n = op & 0xffff;
540 info->sp_offset += n;
542 else if (((op >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */
543 && get_frame_memory_unsigned (next_frame, pc + 4,
546 unsigned long n = op & 0xffffff;
547 info->sp_offset += n;
558 /* 16-bit instructions */
559 op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff;
560 if ((op & 0xf0ff) == 0x207f)
563 int regno = ((op >> 8) & 0xf);
564 info->sp_offset -= 4;
565 info->saved_regs[regno].addr = info->sp_offset;
567 else if ((op & 0xff00) == 0x4f00)
570 int n = (char) (op & 0xff);
571 info->sp_offset += n;
573 else if (op == 0x1d8f)
576 info->uses_frame = 1;
577 info->r13_offset = info->sp_offset;
579 else if (op == 0x7000)
586 info->size = -info->sp_offset;
588 /* Compute the previous frame's stack pointer (which is also the
589 frame's ID's stack address), and this frame's base pointer. */
590 if (info->uses_frame)
592 /* The SP was moved to the FP. This indicates that a new frame
593 was created. Get THIS frame's FP value by unwinding it from
595 this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM);
596 /* The FP points at the last saved register. Adjust the FP back
597 to before the first saved register giving the SP. */
598 prev_sp = this_base + info->size;
602 /* Assume that the FP is this frame's SP but with that pushed
603 stack space added back. */
604 this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
605 prev_sp = this_base + info->size;
608 /* Convert that SP/BASE into real addresses. */
609 info->prev_sp = prev_sp;
610 info->base = this_base;
612 /* Adjust all the saved registers so that they contain addresses and
614 for (i = 0; i < NUM_REGS - 1; i++)
615 if (trad_frame_addr_p (info->saved_regs, i))
616 info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr);
618 /* The call instruction moves the caller's PC in the callee's LR.
619 Since this is an unwind, do the reverse. Copy the location of LR
620 into PC (the address / regnum) so that a request for PC will be
621 converted into a request for the LR. */
622 info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM];
624 /* The previous frame's SP needed to be computed. Save the computed
626 trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp);
632 m32r_read_pc (ptid_t ptid)
637 save_ptid = inferior_ptid;
638 inferior_ptid = ptid;
639 regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc);
640 inferior_ptid = save_ptid;
645 m32r_write_pc (CORE_ADDR val, ptid_t ptid)
649 save_ptid = inferior_ptid;
650 inferior_ptid = ptid;
651 write_register (M32R_PC_REGNUM, val);
652 inferior_ptid = save_ptid;
656 m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
658 return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
663 m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
664 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
665 struct value **args, CORE_ADDR sp, int struct_return,
666 CORE_ADDR struct_addr)
668 int stack_offset, stack_alloc;
669 int argreg = ARG1_REGNUM;
672 enum type_code typecode;
675 char valbuf[MAX_REGISTER_SIZE];
677 int odd_sized_struct;
679 /* first force sp to a 4-byte alignment */
682 /* Set the return address. For the m32r, the return breakpoint is
683 always at BP_ADDR. */
684 regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr);
686 /* If STRUCT_RETURN is true, then the struct return address (in
687 STRUCT_ADDR) will consume the first argument-passing register.
688 Both adjust the register count and store that value. */
691 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
695 /* Now make sure there's space on the stack */
696 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
697 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
698 sp -= stack_alloc; /* make room on stack for args */
700 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
702 type = VALUE_TYPE (args[argnum]);
703 typecode = TYPE_CODE (type);
704 len = TYPE_LENGTH (type);
706 memset (valbuf, 0, sizeof (valbuf));
708 /* Passes structures that do not fit in 2 registers by reference. */
710 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
712 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum]));
713 typecode = TYPE_CODE_PTR;
719 /* value gets right-justified in the register or stack word */
720 memcpy (valbuf + (register_size (gdbarch, argreg) - len),
721 (char *) VALUE_CONTENTS (args[argnum]), len);
725 val = (char *) VALUE_CONTENTS (args[argnum]);
729 if (argreg > ARGN_REGNUM)
731 /* must go on the stack */
732 write_memory (sp + stack_offset, val, 4);
735 else if (argreg <= ARGN_REGNUM)
737 /* there's room in a register */
739 extract_unsigned_integer (val,
740 register_size (gdbarch, argreg));
741 regcache_cooked_write_unsigned (regcache, argreg++, regval);
744 /* Store the value 4 bytes at a time. This means that things
745 larger than 4 bytes may go partly in registers and partly
747 len -= register_size (gdbarch, argreg);
748 val += register_size (gdbarch, argreg);
752 /* Finally, update the SP register. */
753 regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp);
759 /* Given a return value in `regbuf' with a type `valtype',
760 extract and copy its value into `valbuf'. */
763 m32r_extract_return_value (struct type *type, struct regcache *regcache,
766 bfd_byte *valbuf = dst;
767 int len = TYPE_LENGTH (type);
770 /* By using store_unsigned_integer we avoid having to do
771 anything special for small big-endian values. */
772 regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp);
773 store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp);
775 /* Ignore return values more than 8 bytes in size because the m32r
776 returns anything more than 8 bytes in the stack. */
779 regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp);
780 store_unsigned_integer (valbuf + len - 4, 4, tmp);
786 m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
788 return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM);
791 /* Given a GDB frame, determine the address of the calling function's
792 frame. This will be used to create a new GDB frame struct. */
795 m32r_frame_this_id (struct frame_info *next_frame,
796 void **this_prologue_cache, struct frame_id *this_id)
798 struct m32r_unwind_cache *info
799 = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
802 struct minimal_symbol *msym_stack;
805 /* The FUNC is easy. */
806 func = frame_func_unwind (next_frame);
808 /* Check if the stack is empty. */
809 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
810 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
813 /* Hopefully the prologue analysis either correctly determined the
814 frame's base (which is the SP from the previous frame), or set
815 that base to "NULL". */
816 base = info->prev_sp;
820 id = frame_id_build (base, func);
825 m32r_frame_prev_register (struct frame_info *next_frame,
826 void **this_prologue_cache,
827 int regnum, int *optimizedp,
828 enum lval_type *lvalp, CORE_ADDR *addrp,
829 int *realnump, void *bufferp)
831 struct m32r_unwind_cache *info
832 = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
833 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
834 optimizedp, lvalp, addrp, realnump, bufferp);
837 static const struct frame_unwind m32r_frame_unwind = {
840 m32r_frame_prev_register
843 static const struct frame_unwind *
844 m32r_frame_sniffer (struct frame_info *next_frame)
846 return &m32r_frame_unwind;
850 m32r_frame_base_address (struct frame_info *next_frame, void **this_cache)
852 struct m32r_unwind_cache *info
853 = m32r_frame_unwind_cache (next_frame, this_cache);
857 static const struct frame_base m32r_frame_base = {
859 m32r_frame_base_address,
860 m32r_frame_base_address,
861 m32r_frame_base_address
864 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
865 dummy frame. The frame ID's base needs to match the TOS value
866 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
869 static struct frame_id
870 m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
872 return frame_id_build (m32r_unwind_sp (gdbarch, next_frame),
873 frame_pc_unwind (next_frame));
877 static gdbarch_init_ftype m32r_gdbarch_init;
879 static struct gdbarch *
880 m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
882 struct gdbarch *gdbarch;
883 struct gdbarch_tdep *tdep;
885 /* If there is already a candidate, use it. */
886 arches = gdbarch_list_lookup_by_info (arches, &info);
888 return arches->gdbarch;
890 /* Allocate space for the new architecture. */
891 tdep = XMALLOC (struct gdbarch_tdep);
892 gdbarch = gdbarch_alloc (&info, tdep);
894 set_gdbarch_read_pc (gdbarch, m32r_read_pc);
895 set_gdbarch_write_pc (gdbarch, m32r_write_pc);
896 set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);
898 set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS);
899 set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM);
900 set_gdbarch_register_name (gdbarch, m32r_register_name);
901 set_gdbarch_register_type (gdbarch, m32r_register_type);
903 set_gdbarch_extract_return_value (gdbarch, m32r_extract_return_value);
904 set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call);
905 set_gdbarch_store_return_value (gdbarch, m32r_store_return_value);
906 set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
907 m32r_extract_struct_value_address);
908 set_gdbarch_deprecated_use_struct_convention (gdbarch,
909 m32r_use_struct_convention);
911 set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);
912 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
913 set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc);
914 set_gdbarch_memory_insert_breakpoint (gdbarch,
915 m32r_memory_insert_breakpoint);
916 set_gdbarch_memory_remove_breakpoint (gdbarch,
917 m32r_memory_remove_breakpoint);
919 set_gdbarch_frame_align (gdbarch, m32r_frame_align);
921 frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer);
922 frame_base_set_default (gdbarch, &m32r_frame_base);
924 /* Methods for saving / extracting a dummy frame's ID. The ID's
925 stack address must match the SP value returned by
926 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */
927 set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id);
929 /* Return the unwound PC value. */
930 set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc);
932 set_gdbarch_print_insn (gdbarch, print_insn_m32r);
938 _initialize_m32r_tdep (void)
940 register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init);