1 /* Renesas M32C target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 2004-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb/sim-m32c.h"
27 #include "arch-utils.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
31 #include "dwarf2expr.h"
35 #include "reggroups.h"
36 #include "prologue-value.h"
41 /* The m32c tdep structure. */
43 static struct reggroup *m32c_dma_reggroup;
47 /* The type of a function that moves the value of REG between CACHE or
48 BUF --- in either direction. */
49 typedef enum register_status (m32c_write_reg_t) (struct m32c_reg *reg,
50 struct regcache *cache,
53 typedef enum register_status (m32c_read_reg_t) (struct m32c_reg *reg,
54 struct regcache *cache,
59 /* The name of this register. */
65 /* The architecture this register belongs to. */
68 /* Its GDB register number. */
71 /* Its sim register number. */
74 /* Its DWARF register number, or -1 if it doesn't have one. */
77 /* Register group memberships. */
78 unsigned int general_p : 1;
79 unsigned int dma_p : 1;
80 unsigned int system_p : 1;
81 unsigned int save_restore_p : 1;
83 /* Functions to read its value from a regcache, and write its value
85 m32c_read_reg_t *read;
86 m32c_write_reg_t *write;
88 /* Data for READ and WRITE functions. The exact meaning depends on
89 the specific functions selected; see the comments for those
91 struct m32c_reg *rx, *ry;
96 /* An overestimate of the number of raw and pseudoregisters we will
97 have. The exact answer depends on the variant of the architecture
98 at hand, but we can use this to declare statically allocated
99 arrays, and bump it up when needed. */
100 #define M32C_MAX_NUM_REGS (75)
102 /* The largest assigned DWARF register number. */
103 #define M32C_MAX_DWARF_REGNUM (40)
108 /* All the registers for this variant, indexed by GDB register
109 number, and the number of registers present. */
110 struct m32c_reg regs[M32C_MAX_NUM_REGS];
112 /* The number of valid registers. */
115 /* Interesting registers. These are pointers into REGS. */
116 struct m32c_reg *pc, *flg;
117 struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1;
118 struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0;
119 struct m32c_reg *sb, *fb, *sp;
121 /* A table indexed by DWARF register numbers, pointing into
123 struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1];
125 /* Types for this architecture. We can't use the builtin_type_foo
126 types, because they're not initialized when building a gdbarch
128 struct type *voyd, *ptr_voyd, *func_voyd;
129 struct type *uint8, *uint16;
130 struct type *int8, *int16, *int32, *int64;
132 /* The types for data address and code address registers. */
133 struct type *data_addr_reg_type, *code_addr_reg_type;
135 /* The number of bytes a return address pushed by a 'jsr' instruction
136 occupies on the stack. */
139 /* The number of bytes an address register occupies on the stack
140 when saved by an 'enter' or 'pushm' instruction. */
148 make_types (struct gdbarch *arch)
150 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
151 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
152 int data_addr_reg_bits, code_addr_reg_bits;
156 /* This is used to clip CORE_ADDR values, so this value is
157 appropriate both on the m32c, where pointers are 32 bits long,
158 and on the m16c, where pointers are sixteen bits long, but there
159 may be code above the 64k boundary. */
160 set_gdbarch_addr_bit (arch, 24);
162 /* GCC uses 32 bits for addrs in the dwarf info, even though
163 only 16/24 bits are used. Setting addr_bit to 24 causes
164 errors in reading the dwarf addresses. */
165 set_gdbarch_addr_bit (arch, 32);
168 set_gdbarch_int_bit (arch, 16);
172 data_addr_reg_bits = 16;
173 code_addr_reg_bits = 24;
174 set_gdbarch_ptr_bit (arch, 16);
175 tdep->ret_addr_bytes = 3;
176 tdep->push_addr_bytes = 2;
180 data_addr_reg_bits = 24;
181 code_addr_reg_bits = 24;
182 set_gdbarch_ptr_bit (arch, 32);
183 tdep->ret_addr_bytes = 4;
184 tdep->push_addr_bytes = 4;
188 gdb_assert_not_reached ("unexpected mach");
191 /* The builtin_type_mumble variables are sometimes uninitialized when
192 this is called, so we avoid using them. */
193 tdep->voyd = arch_type (arch, TYPE_CODE_VOID, 1, "void");
195 = arch_pointer_type (arch, gdbarch_ptr_bit (arch), NULL, tdep->voyd);
196 tdep->func_voyd = lookup_function_type (tdep->voyd);
198 xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t",
199 gdbarch_bfd_arch_info (arch)->printable_name);
200 tdep->data_addr_reg_type
201 = arch_pointer_type (arch, data_addr_reg_bits, type_name, tdep->voyd);
203 xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t",
204 gdbarch_bfd_arch_info (arch)->printable_name);
205 tdep->code_addr_reg_type
206 = arch_pointer_type (arch, code_addr_reg_bits, type_name, tdep->func_voyd);
208 tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t");
209 tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t");
210 tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t");
211 tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t");
212 tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t");
213 tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t");
221 m32c_register_name (struct gdbarch *gdbarch, int num)
223 return gdbarch_tdep (gdbarch)->regs[num].name;
228 m32c_register_type (struct gdbarch *arch, int reg_nr)
230 return gdbarch_tdep (arch)->regs[reg_nr].type;
235 m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr)
237 return gdbarch_tdep (gdbarch)->regs[reg_nr].sim_num;
242 m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr)
244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
245 if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM
246 && tdep->dwarf_regs[reg_nr])
247 return tdep->dwarf_regs[reg_nr]->num;
249 /* The DWARF CFI code expects to see -1 for invalid register
256 m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
257 struct reggroup *group)
259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
260 struct m32c_reg *reg = &tdep->regs[regnum];
262 /* The anonymous raw registers aren't in any groups. */
266 if (group == all_reggroup)
269 if (group == general_reggroup
273 if (group == m32c_dma_reggroup
277 if (group == system_reggroup
281 /* Since the m32c DWARF register numbers refer to cooked registers, not
282 raw registers, and frame_pop depends on the save and restore groups
283 containing registers the DWARF CFI will actually mention, our save
284 and restore groups are cooked registers, not raw registers. (This is
285 why we can't use the default reggroup function.) */
286 if ((group == save_reggroup
287 || group == restore_reggroup)
288 && reg->save_restore_p)
295 /* Register move functions. We declare them here using
296 m32c_{read,write}_reg_t to check the types. */
297 static m32c_read_reg_t m32c_raw_read;
298 static m32c_read_reg_t m32c_banked_read;
299 static m32c_read_reg_t m32c_sb_read;
300 static m32c_read_reg_t m32c_part_read;
301 static m32c_read_reg_t m32c_cat_read;
302 static m32c_read_reg_t m32c_r3r2r1r0_read;
304 static m32c_write_reg_t m32c_raw_write;
305 static m32c_write_reg_t m32c_banked_write;
306 static m32c_write_reg_t m32c_sb_write;
307 static m32c_write_reg_t m32c_part_write;
308 static m32c_write_reg_t m32c_cat_write;
309 static m32c_write_reg_t m32c_r3r2r1r0_write;
311 /* Copy the value of the raw register REG from CACHE to BUF. */
312 static enum register_status
313 m32c_raw_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
315 return regcache_raw_read (cache, reg->num, buf);
319 /* Copy the value of the raw register REG from BUF to CACHE. */
320 static enum register_status
321 m32c_raw_write (struct m32c_reg *reg, struct regcache *cache,
324 regcache_raw_write (cache, reg->num, buf);
330 /* Return the value of the 'flg' register in CACHE. */
332 m32c_read_flg (struct regcache *cache)
334 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (cache));
336 regcache_raw_read_unsigned (cache, tdep->flg->num, &flg);
341 /* Evaluate the real register number of a banked register. */
342 static struct m32c_reg *
343 m32c_banked_register (struct m32c_reg *reg, struct regcache *cache)
345 return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx);
349 /* Move the value of a banked register from CACHE to BUF.
350 If the value of the 'flg' register in CACHE has any of the bits
351 masked in REG->n set, then read REG->ry. Otherwise, read
353 static enum register_status
354 m32c_banked_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
356 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
357 return regcache_raw_read (cache, bank_reg->num, buf);
361 /* Move the value of a banked register from BUF to CACHE.
362 If the value of the 'flg' register in CACHE has any of the bits
363 masked in REG->n set, then write REG->ry. Otherwise, write
365 static enum register_status
366 m32c_banked_write (struct m32c_reg *reg, struct regcache *cache,
369 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
370 regcache_raw_write (cache, bank_reg->num, buf);
376 /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a
377 banked register; on bfd_mach_m16c, it's not. */
378 static enum register_status
379 m32c_sb_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
381 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
382 return m32c_raw_read (reg->rx, cache, buf);
384 return m32c_banked_read (reg, cache, buf);
388 /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a
389 banked register; on bfd_mach_m16c, it's not. */
390 static enum register_status
391 m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, const gdb_byte *buf)
393 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
394 m32c_raw_write (reg->rx, cache, buf);
396 m32c_banked_write (reg, cache, buf);
402 /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P
403 and *LEN_P to the offset and length, in bytes, of the part REG
404 occupies in its underlying register. The offset is from the
405 lower-addressed end, regardless of the architecture's endianness.
406 (The M32C family is always little-endian, but let's keep those
407 assumptions out of here.) */
409 m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p)
411 /* The length of the containing register, of which REG is one part. */
412 int containing_len = TYPE_LENGTH (reg->rx->type);
414 /* The length of one "element" in our imaginary array. */
415 int elt_len = TYPE_LENGTH (reg->type);
417 /* The offset of REG's "element" from the least significant end of
418 the containing register. */
419 int elt_offset = reg->n * elt_len;
421 /* If we extend off the end, trim the length of the element. */
422 if (elt_offset + elt_len > containing_len)
424 elt_len = containing_len - elt_offset;
425 /* We shouldn't be declaring partial registers that go off the
426 end of their containing registers. */
427 gdb_assert (elt_len > 0);
430 /* Flip the offset around if we're big-endian. */
431 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
432 elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len;
434 *offset_p = elt_offset;
439 /* Move the value of a partial register (r0h, intbl, etc.) from CACHE
440 to BUF. Treating the value of the register REG->rx as an array of
441 REG->type values, where higher indices refer to more significant
442 bits, read the value of the REG->n'th element. */
443 static enum register_status
444 m32c_part_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
448 memset (buf, 0, TYPE_LENGTH (reg->type));
449 m32c_find_part (reg, &offset, &len);
450 return regcache_cooked_read_part (cache, reg->rx->num, offset, len, buf);
454 /* Move the value of a banked register from BUF to CACHE.
455 Treating the value of the register REG->rx as an array of REG->type
456 values, where higher indices refer to more significant bits, write
457 the value of the REG->n'th element. */
458 static enum register_status
459 m32c_part_write (struct m32c_reg *reg, struct regcache *cache,
464 m32c_find_part (reg, &offset, &len);
465 regcache_cooked_write_part (cache, reg->rx->num, offset, len, buf);
471 /* Move the value of REG from CACHE to BUF. REG's value is the
472 concatenation of the values of the registers REG->rx and REG->ry,
473 with REG->rx contributing the more significant bits. */
474 static enum register_status
475 m32c_cat_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
477 int high_bytes = TYPE_LENGTH (reg->rx->type);
478 int low_bytes = TYPE_LENGTH (reg->ry->type);
479 enum register_status status;
481 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
483 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
485 status = regcache_cooked_read (cache, reg->rx->num, buf);
486 if (status == REG_VALID)
487 status = regcache_cooked_read (cache, reg->ry->num, buf + high_bytes);
491 status = regcache_cooked_read (cache, reg->rx->num, buf + low_bytes);
492 if (status == REG_VALID)
493 status = regcache_cooked_read (cache, reg->ry->num, buf);
500 /* Move the value of REG from CACHE to BUF. REG's value is the
501 concatenation of the values of the registers REG->rx and REG->ry,
502 with REG->rx contributing the more significant bits. */
503 static enum register_status
504 m32c_cat_write (struct m32c_reg *reg, struct regcache *cache,
507 int high_bytes = TYPE_LENGTH (reg->rx->type);
508 int low_bytes = TYPE_LENGTH (reg->ry->type);
510 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
512 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
514 regcache_cooked_write (cache, reg->rx->num, buf);
515 regcache_cooked_write (cache, reg->ry->num, buf + high_bytes);
519 regcache_cooked_write (cache, reg->rx->num, buf + low_bytes);
520 regcache_cooked_write (cache, reg->ry->num, buf);
527 /* Copy the value of the raw register REG from CACHE to BUF. REG is
528 the concatenation (from most significant to least) of r3, r2, r1,
530 static enum register_status
531 m32c_r3r2r1r0_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
533 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
534 int len = TYPE_LENGTH (tdep->r0->type);
535 enum register_status status;
537 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
539 status = regcache_cooked_read (cache, tdep->r0->num, buf + len * 3);
540 if (status == REG_VALID)
541 status = regcache_cooked_read (cache, tdep->r1->num, buf + len * 2);
542 if (status == REG_VALID)
543 status = regcache_cooked_read (cache, tdep->r2->num, buf + len * 1);
544 if (status == REG_VALID)
545 status = regcache_cooked_read (cache, tdep->r3->num, buf);
549 status = regcache_cooked_read (cache, tdep->r0->num, buf);
550 if (status == REG_VALID)
551 status = regcache_cooked_read (cache, tdep->r1->num, buf + len * 1);
552 if (status == REG_VALID)
553 status = regcache_cooked_read (cache, tdep->r2->num, buf + len * 2);
554 if (status == REG_VALID)
555 status = regcache_cooked_read (cache, tdep->r3->num, buf + len * 3);
562 /* Copy the value of the raw register REG from BUF to CACHE. REG is
563 the concatenation (from most significant to least) of r3, r2, r1,
565 static enum register_status
566 m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache,
569 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
570 int len = TYPE_LENGTH (tdep->r0->type);
572 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
574 regcache_cooked_write (cache, tdep->r0->num, buf + len * 3);
575 regcache_cooked_write (cache, tdep->r1->num, buf + len * 2);
576 regcache_cooked_write (cache, tdep->r2->num, buf + len * 1);
577 regcache_cooked_write (cache, tdep->r3->num, buf);
581 regcache_cooked_write (cache, tdep->r0->num, buf);
582 regcache_cooked_write (cache, tdep->r1->num, buf + len * 1);
583 regcache_cooked_write (cache, tdep->r2->num, buf + len * 2);
584 regcache_cooked_write (cache, tdep->r3->num, buf + len * 3);
591 static enum register_status
592 m32c_pseudo_register_read (struct gdbarch *arch,
593 struct regcache *cache,
597 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
598 struct m32c_reg *reg;
600 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
601 gdb_assert (arch == get_regcache_arch (cache));
602 gdb_assert (arch == tdep->regs[cookednum].arch);
603 reg = &tdep->regs[cookednum];
605 return reg->read (reg, cache, buf);
610 m32c_pseudo_register_write (struct gdbarch *arch,
611 struct regcache *cache,
615 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
616 struct m32c_reg *reg;
618 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
619 gdb_assert (arch == get_regcache_arch (cache));
620 gdb_assert (arch == tdep->regs[cookednum].arch);
621 reg = &tdep->regs[cookednum];
623 reg->write (reg, cache, buf);
627 /* Add a register with the given fields to the end of ARCH's table.
628 Return a pointer to the newly added register. */
629 static struct m32c_reg *
630 add_reg (struct gdbarch *arch,
634 m32c_read_reg_t *read,
635 m32c_write_reg_t *write,
640 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
641 struct m32c_reg *r = &tdep->regs[tdep->num_regs];
643 gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS);
648 r->num = tdep->num_regs;
649 r->sim_num = sim_num;
654 r->save_restore_p = 0;
667 /* Record NUM as REG's DWARF register number. */
669 set_dwarf_regnum (struct m32c_reg *reg, int num)
671 gdb_assert (num < M32C_MAX_NUM_REGS);
673 /* Update the reg->DWARF mapping. Only count the first number
674 assigned to this register. */
675 if (reg->dwarf_num == -1)
676 reg->dwarf_num = num;
678 /* Update the DWARF->reg mapping. */
679 gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg;
683 /* Mark REG as a general-purpose register, and return it. */
684 static struct m32c_reg *
685 mark_general (struct m32c_reg *reg)
692 /* Mark REG as a DMA register, and return it. */
693 static struct m32c_reg *
694 mark_dma (struct m32c_reg *reg)
701 /* Mark REG as a SYSTEM register, and return it. */
702 static struct m32c_reg *
703 mark_system (struct m32c_reg *reg)
710 /* Mark REG as a save-restore register, and return it. */
711 static struct m32c_reg *
712 mark_save_restore (struct m32c_reg *reg)
714 reg->save_restore_p = 1;
719 #define FLAGBIT_B 0x0010
720 #define FLAGBIT_U 0x0080
722 /* Handy macros for declaring registers. These all evaluate to
723 pointers to the register declared. Macros that define two
724 registers evaluate to a pointer to the first. */
726 /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */
727 #define R(name, type, sim_num) \
728 (add_reg (arch, (name), (type), (sim_num), \
729 m32c_raw_read, m32c_raw_write, NULL, NULL, 0))
731 /* The simulator register number for a raw register named NAME. */
732 #define SIM(name) (m32c_sim_reg_ ## name)
734 /* A raw unsigned 16-bit data register named NAME.
735 NAME should be an identifier, not a string. */
737 (R(#name, tdep->uint16, SIM (name)))
739 /* A raw data address register named NAME.
740 NAME should be an identifier, not a string. */
742 (R(#name, tdep->data_addr_reg_type, SIM (name)))
744 /* A raw code address register named NAME. NAME should
745 be an identifier, not a string. */
747 (R(#name, tdep->code_addr_reg_type, SIM (name)))
749 /* A pair of raw registers named NAME0 and NAME1, with type TYPE.
750 NAME should be an identifier, not a string. */
751 #define RP(name, type) \
752 (R(#name "0", (type), SIM (name ## 0)), \
753 R(#name "1", (type), SIM (name ## 1)) - 1)
755 /* A raw banked general-purpose data register named NAME.
756 NAME should be an identifier, not a string. */
758 (R(NULL, tdep->int16, SIM (name ## _bank0)), \
759 R(NULL, tdep->int16, SIM (name ## _bank1)) - 1)
761 /* A raw banked data address register named NAME.
762 NAME should be an identifier, not a string. */
764 (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \
765 R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1)
767 /* A cooked register named NAME referring to a raw banked register
768 from the bank selected by the current value of FLG. RAW_PAIR
769 should be a pointer to the first register in the banked pair.
770 NAME must be an identifier, not a string. */
771 #define CB(name, raw_pair) \
772 (add_reg (arch, #name, (raw_pair)->type, 0, \
773 m32c_banked_read, m32c_banked_write, \
774 (raw_pair), (raw_pair + 1), FLAGBIT_B))
776 /* A pair of registers named NAMEH and NAMEL, of type TYPE, that
777 access the top and bottom halves of the register pointed to by
778 NAME. NAME should be an identifier. */
779 #define CHL(name, type) \
780 (add_reg (arch, #name "h", (type), 0, \
781 m32c_part_read, m32c_part_write, name, NULL, 1), \
782 add_reg (arch, #name "l", (type), 0, \
783 m32c_part_read, m32c_part_write, name, NULL, 0) - 1)
785 /* A register constructed by concatenating the two registers HIGH and
786 LOW, whose name is HIGHLOW and whose type is TYPE. */
787 #define CCAT(high, low, type) \
788 (add_reg (arch, #high #low, (type), 0, \
789 m32c_cat_read, m32c_cat_write, (high), (low), 0))
791 /* Abbreviations for marking register group membership. */
792 #define G(reg) (mark_general (reg))
793 #define S(reg) (mark_system (reg))
794 #define DMA(reg) (mark_dma (reg))
797 /* Construct the register set for ARCH. */
799 make_regs (struct gdbarch *arch)
801 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
802 int mach = gdbarch_bfd_arch_info (arch)->mach;
815 struct m32c_reg *r0hl;
816 struct m32c_reg *r1hl;
817 struct m32c_reg *r2r0;
818 struct m32c_reg *r3r1;
819 struct m32c_reg *r3r1r2r0;
820 struct m32c_reg *r3r2r1r0;
821 struct m32c_reg *a1a0;
823 struct m32c_reg *raw_r0_pair = RBD (r0);
824 struct m32c_reg *raw_r1_pair = RBD (r1);
825 struct m32c_reg *raw_r2_pair = RBD (r2);
826 struct m32c_reg *raw_r3_pair = RBD (r3);
827 struct m32c_reg *raw_a0_pair = RBA (a0);
828 struct m32c_reg *raw_a1_pair = RBA (a1);
829 struct m32c_reg *raw_fb_pair = RBA (fb);
831 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
832 We always declare both raw registers, and deal with the distinction
833 in the pseudoregister. */
834 struct m32c_reg *raw_sb_pair = RBA (sb);
836 struct m32c_reg *usp = S (RA (usp));
837 struct m32c_reg *isp = S (RA (isp));
838 struct m32c_reg *intb = S (RC (intb));
839 struct m32c_reg *pc = G (RC (pc));
840 struct m32c_reg *flg = G (R16U (flg));
842 if (mach == bfd_mach_m32c)
844 struct m32c_reg *svf = S (R16U (svf));
845 struct m32c_reg *svp = S (RC (svp));
846 struct m32c_reg *vct = S (RC (vct));
848 struct m32c_reg *dmd01 = DMA (RP (dmd, tdep->uint8));
849 struct m32c_reg *dct01 = DMA (RP (dct, tdep->uint16));
850 struct m32c_reg *drc01 = DMA (RP (drc, tdep->uint16));
851 struct m32c_reg *dma01 = DMA (RP (dma, tdep->data_addr_reg_type));
852 struct m32c_reg *dsa01 = DMA (RP (dsa, tdep->data_addr_reg_type));
853 struct m32c_reg *dra01 = DMA (RP (dra, tdep->data_addr_reg_type));
856 num_raw_regs = tdep->num_regs;
858 r0 = G (CB (r0, raw_r0_pair));
859 r1 = G (CB (r1, raw_r1_pair));
860 r2 = G (CB (r2, raw_r2_pair));
861 r3 = G (CB (r3, raw_r3_pair));
862 a0 = G (CB (a0, raw_a0_pair));
863 a1 = G (CB (a1, raw_a1_pair));
864 fb = G (CB (fb, raw_fb_pair));
866 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
867 Specify custom read/write functions that do the right thing. */
868 sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0,
869 m32c_sb_read, m32c_sb_write,
870 raw_sb_pair, raw_sb_pair + 1, 0));
872 /* The current sp is either usp or isp, depending on the value of
873 the FLG register's U bit. */
874 sp = G (add_reg (arch, "sp", usp->type, 0,
875 m32c_banked_read, m32c_banked_write,
876 isp, usp, FLAGBIT_U));
878 r0hl = CHL (r0, tdep->int8);
879 r1hl = CHL (r1, tdep->int8);
880 CHL (r2, tdep->int8);
881 CHL (r3, tdep->int8);
882 CHL (intb, tdep->int16);
884 r2r0 = CCAT (r2, r0, tdep->int32);
885 r3r1 = CCAT (r3, r1, tdep->int32);
886 r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64);
889 = add_reg (arch, "r3r2r1r0", tdep->int64, 0,
890 m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0);
892 if (mach == bfd_mach_m16c)
893 a1a0 = CCAT (a1, a0, tdep->int32);
897 num_cooked_regs = tdep->num_regs - num_raw_regs;
906 tdep->r3r2r1r0 = r3r2r1r0;
907 tdep->r3r1r2r0 = r3r1r2r0;
914 /* Set up the DWARF register table. */
915 memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs));
916 set_dwarf_regnum (r0hl + 1, 0x01);
917 set_dwarf_regnum (r0hl + 0, 0x02);
918 set_dwarf_regnum (r1hl + 1, 0x03);
919 set_dwarf_regnum (r1hl + 0, 0x04);
920 set_dwarf_regnum (r0, 0x05);
921 set_dwarf_regnum (r1, 0x06);
922 set_dwarf_regnum (r2, 0x07);
923 set_dwarf_regnum (r3, 0x08);
924 set_dwarf_regnum (a0, 0x09);
925 set_dwarf_regnum (a1, 0x0a);
926 set_dwarf_regnum (fb, 0x0b);
927 set_dwarf_regnum (sp, 0x0c);
928 set_dwarf_regnum (pc, 0x0d); /* GCC's invention */
929 set_dwarf_regnum (sb, 0x13);
930 set_dwarf_regnum (r2r0, 0x15);
931 set_dwarf_regnum (r3r1, 0x16);
933 set_dwarf_regnum (a1a0, 0x17);
935 /* Enumerate the save/restore register group.
937 The regcache_save and regcache_restore functions apply their read
938 function to each register in this group.
940 Since frame_pop supplies frame_unwind_register as its read
941 function, the registers meaningful to the Dwarf unwinder need to
944 On the other hand, when we make inferior calls, save_inferior_status
945 and restore_inferior_status use them to preserve the current register
946 values across the inferior call. For this, you'd kind of like to
947 preserve all the raw registers, to protect the interrupted code from
948 any sort of bank switching the callee might have done. But we handle
949 those cases so badly anyway --- for example, it matters whether we
950 restore FLG before or after we restore the general-purpose registers,
951 but there's no way to express that --- that it isn't worth worrying
954 We omit control registers like inthl: if you call a function that
955 changes those, it's probably because you wanted that change to be
956 visible to the interrupted code. */
957 mark_save_restore (r0);
958 mark_save_restore (r1);
959 mark_save_restore (r2);
960 mark_save_restore (r3);
961 mark_save_restore (a0);
962 mark_save_restore (a1);
963 mark_save_restore (sb);
964 mark_save_restore (fb);
965 mark_save_restore (sp);
966 mark_save_restore (pc);
967 mark_save_restore (flg);
969 set_gdbarch_num_regs (arch, num_raw_regs);
970 set_gdbarch_num_pseudo_regs (arch, num_cooked_regs);
971 set_gdbarch_pc_regnum (arch, pc->num);
972 set_gdbarch_sp_regnum (arch, sp->num);
973 set_gdbarch_register_name (arch, m32c_register_name);
974 set_gdbarch_register_type (arch, m32c_register_type);
975 set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read);
976 set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write);
977 set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno);
978 set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
979 set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
980 set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p);
982 reggroup_add (arch, general_reggroup);
983 reggroup_add (arch, all_reggroup);
984 reggroup_add (arch, save_reggroup);
985 reggroup_add (arch, restore_reggroup);
986 reggroup_add (arch, system_reggroup);
987 reggroup_add (arch, m32c_dma_reggroup);
993 static const unsigned char break_insn[] = { 0x00 }; /* brk */
995 GDBARCH_BREAKPOINT_MANIPULATION (m32c, break_insn)
998 /* Prologue analysis. */
1000 enum m32c_prologue_kind
1002 /* This function uses a frame pointer. */
1003 prologue_with_frame_ptr,
1005 /* This function has no frame pointer. */
1006 prologue_sans_frame_ptr,
1008 /* This function sets up the stack, so its frame is the first
1009 frame on the stack. */
1010 prologue_first_frame
1013 struct m32c_prologue
1015 /* For consistency with the DWARF 2 .debug_frame info generated by
1016 GCC, a frame's CFA is the address immediately after the saved
1019 /* The architecture for which we generated this prologue info. */
1020 struct gdbarch *arch;
1022 enum m32c_prologue_kind kind;
1024 /* If KIND is prologue_with_frame_ptr, this is the offset from the
1025 CFA to where the frame pointer points. This is always zero or
1027 LONGEST frame_ptr_offset;
1029 /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to
1030 the stack pointer --- always zero or negative.
1032 Calling this a "size" is a bit misleading, but given that the
1033 stack grows downwards, using offsets for everything keeps one
1034 from going completely sign-crazy: you never change anything's
1035 sign for an ADD instruction; always change the second operand's
1036 sign for a SUB instruction; and everything takes care of
1039 Functions that use alloca don't have a constant frame size. But
1040 they always have frame pointers, so we must use that to find the
1041 CFA (and perhaps to unwind the stack pointer). */
1044 /* The address of the first instruction at which the frame has been
1045 set up and the arguments are where the debug info says they are
1046 --- as best as we can tell. */
1047 CORE_ADDR prologue_end;
1049 /* reg_offset[R] is the offset from the CFA at which register R is
1050 saved, or 1 if register R has not been saved. (Real values are
1051 always zero or negative.) */
1052 LONGEST reg_offset[M32C_MAX_NUM_REGS];
1056 /* The longest I've seen, anyway. */
1057 #define M32C_MAX_INSN_LEN (9)
1059 /* Processor state, for the prologue analyzer. */
1060 struct m32c_pv_state
1062 struct gdbarch *arch;
1063 pv_t r0, r1, r2, r3;
1067 struct pv_area *stack;
1069 /* Bytes from the current PC, the address they were read from,
1070 and the address of the next unconsumed byte. */
1071 gdb_byte insn[M32C_MAX_INSN_LEN];
1072 CORE_ADDR scan_pc, next_addr;
1076 /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if
1077 all went well, or non-zero if simulating the action would trash our
1080 m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size)
1082 if (pv_area_store_would_trash (state->stack, state->sp))
1085 state->sp = pv_add_constant (state->sp, -size);
1086 pv_area_store (state->stack, state->sp, size, value);
1095 srcdest_partial_reg,
1099 /* A source or destination location for an m16c or m32c
1103 /* If srcdest_reg, the location is a register pointed to by REG.
1104 If srcdest_partial_reg, the location is part of a register pointed
1105 to by REG. We don't try to handle this too well.
1106 If srcdest_mem, the location is memory whose address is ADDR. */
1107 enum srcdest_kind kind;
1112 /* Return the SIZE-byte value at LOC in STATE. */
1114 m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size)
1116 if (loc.kind == srcdest_mem)
1117 return pv_area_fetch (state->stack, loc.addr, size);
1118 else if (loc.kind == srcdest_partial_reg)
1119 return pv_unknown ();
1125 /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if
1126 all went well, or non-zero if simulating the store would trash our
1129 m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc,
1130 pv_t value, int size)
1132 if (loc.kind == srcdest_mem)
1134 if (pv_area_store_would_trash (state->stack, loc.addr))
1136 pv_area_store (state->stack, loc.addr, size, value);
1138 else if (loc.kind == srcdest_partial_reg)
1139 *loc.reg = pv_unknown ();
1148 m32c_sign_ext (int v, int bits)
1150 int mask = 1 << (bits - 1);
1151 return (v ^ mask) - mask;
1155 m32c_next_byte (struct m32c_pv_state *st)
1157 gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn));
1158 return st->insn[st->next_addr++ - st->scan_pc];
1162 m32c_udisp8 (struct m32c_pv_state *st)
1164 return m32c_next_byte (st);
1169 m32c_sdisp8 (struct m32c_pv_state *st)
1171 return m32c_sign_ext (m32c_next_byte (st), 8);
1176 m32c_udisp16 (struct m32c_pv_state *st)
1178 int low = m32c_next_byte (st);
1179 int high = m32c_next_byte (st);
1181 return low + (high << 8);
1186 m32c_sdisp16 (struct m32c_pv_state *st)
1188 int low = m32c_next_byte (st);
1189 int high = m32c_next_byte (st);
1191 return m32c_sign_ext (low + (high << 8), 16);
1196 m32c_udisp24 (struct m32c_pv_state *st)
1198 int low = m32c_next_byte (st);
1199 int mid = m32c_next_byte (st);
1200 int high = m32c_next_byte (st);
1202 return low + (mid << 8) + (high << 16);
1206 /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */
1208 m32c_get_src23 (unsigned char *i)
1210 return (((i[0] & 0x70) >> 2)
1211 | ((i[1] & 0x30) >> 4));
1215 /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */
1217 m32c_get_dest23 (unsigned char *i)
1219 return (((i[0] & 0x0e) << 1)
1220 | ((i[1] & 0xc0) >> 6));
1224 static struct srcdest
1225 m32c_decode_srcdest4 (struct m32c_pv_state *st,
1231 sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg);
1233 sd.kind = srcdest_mem;
1235 sd.addr = pv_unknown ();
1240 case 0x0: sd.reg = (size == 1 ? &st->r0 : &st->r0); break;
1241 case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break;
1242 case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break;
1243 case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break;
1245 case 0x4: sd.reg = &st->a0; break;
1246 case 0x5: sd.reg = &st->a1; break;
1248 case 0x6: sd.addr = st->a0; break;
1249 case 0x7: sd.addr = st->a1; break;
1251 case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1252 case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1253 case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1254 case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1256 case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1257 case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1258 case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1259 case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1262 gdb_assert_not_reached ("unexpected srcdest4");
1269 static struct srcdest
1270 m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind)
1274 sd.addr = pv_unknown ();
1283 sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg;
1288 sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg;
1292 sd.kind = srcdest_mem;
1299 case 0x12: sd.reg = &st->r0; break;
1300 case 0x13: sd.reg = &st->r1; break;
1301 case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break;
1302 case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break;
1303 case 0x02: sd.reg = &st->a0; break;
1304 case 0x03: sd.reg = &st->a1; break;
1306 case 0x00: sd.addr = st->a0; break;
1307 case 0x01: sd.addr = st->a1; break;
1308 case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1309 case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1310 case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1311 case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1312 case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1313 case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1314 case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1315 case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break;
1316 case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break;
1317 case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break;
1318 case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1319 case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break;
1321 gdb_assert_not_reached ("unexpected sd23");
1326 sd.addr = m32c_srcdest_fetch (st, sd, 4);
1327 sd.kind = srcdest_mem;
1334 /* The r16c and r32c machines have instructions with similar
1335 semantics, but completely different machine language encodings. So
1336 we break out the semantics into their own functions, and leave
1337 machine-specific decoding in m32c_analyze_prologue.
1339 The following functions all expect their arguments already decoded,
1340 and they all return zero if analysis should continue past this
1341 instruction, or non-zero if analysis should stop. */
1344 /* Simulate an 'enter SIZE' instruction in STATE. */
1346 m32c_pv_enter (struct m32c_pv_state *state, int size)
1348 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1350 /* If simulating this store would require us to forget
1351 everything we know about the stack frame in the name of
1352 accuracy, it would be better to just quit now. */
1353 if (pv_area_store_would_trash (state->stack, state->sp))
1356 if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes))
1358 state->fb = state->sp;
1359 state->sp = pv_add_constant (state->sp, -size);
1366 m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg,
1367 int bit, int src, int size)
1371 if (m32c_pv_push (state, reg, size))
1379 /* Simulate a 'pushm SRC' instruction in STATE. */
1381 m32c_pv_pushm (struct m32c_pv_state *state, int src)
1383 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1385 /* The bits in SRC indicating which registers to save are:
1386 r0 r1 r2 r3 a0 a1 sb fb */
1388 ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes)
1389 || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes)
1390 || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes)
1391 || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes)
1392 || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2)
1393 || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2)
1394 || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2)
1395 || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2));
1398 /* Return non-zero if VALUE is the first incoming argument register. */
1401 m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value)
1403 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1404 return (value.kind == pvk_register
1405 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1406 ? (value.reg == tdep->r1->num)
1407 : (value.reg == tdep->r0->num))
1411 /* Return non-zero if VALUE is an incoming argument register. */
1414 m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value)
1416 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1417 return (value.kind == pvk_register
1418 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1419 ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num)
1420 : (value.reg == tdep->r0->num))
1424 /* Return non-zero if a store of VALUE to LOC is probably spilling an
1425 argument register to its stack slot in STATE. Such instructions
1426 should be included in the prologue, if possible.
1428 The store is a spill if:
1429 - the value being stored is the original value of an argument register;
1430 - the value has not already been stored somewhere in STACK; and
1431 - LOC is a stack slot (e.g., a memory location whose address is
1432 relative to the original value of the SP). */
1435 m32c_is_arg_spill (struct m32c_pv_state *st,
1439 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1441 return (m32c_is_arg_reg (st, value)
1442 && loc.kind == srcdest_mem
1443 && pv_is_register (loc.addr, tdep->sp->num)
1444 && ! pv_area_find_reg (st->stack, st->arch, value.reg, 0));
1447 /* Return non-zero if a store of VALUE to LOC is probably
1448 copying the struct return address into an address register
1449 for immediate use. This is basically a "spill" into the
1450 address register, instead of onto the stack.
1452 The prerequisites are:
1453 - value being stored is original value of the FIRST arg register;
1454 - value has not already been stored on stack; and
1455 - LOC is an address register (a0 or a1). */
1458 m32c_is_struct_return (struct m32c_pv_state *st,
1462 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1464 return (m32c_is_1st_arg_reg (st, value)
1465 && !pv_area_find_reg (st->stack, st->arch, value.reg, 0)
1466 && loc.kind == srcdest_reg
1467 && (pv_is_register (*loc.reg, tdep->a0->num)
1468 || pv_is_register (*loc.reg, tdep->a1->num)));
1471 /* Return non-zero if a 'pushm' saving the registers indicated by SRC
1472 was a register save:
1473 - all the named registers should have their original values, and
1474 - the stack pointer should be at a constant offset from the
1475 original stack pointer. */
1477 m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src)
1479 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1480 /* The bits in SRC indicating which registers to save are:
1481 r0 r1 r2 r3 a0 a1 sb fb */
1483 (pv_is_register (st->sp, tdep->sp->num)
1484 && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0))
1485 && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0))
1486 && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0))
1487 && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0))
1488 && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0))
1489 && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0))
1490 && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0))
1491 && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0)));
1495 /* Function for finding saved registers in a 'struct pv_area'; we pass
1496 this to pv_area_scan.
1498 If VALUE is a saved register, ADDR says it was saved at a constant
1499 offset from the frame base, and SIZE indicates that the whole
1500 register was saved, record its offset in RESULT_UNTYPED. */
1502 check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value)
1504 struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped;
1505 struct gdbarch *arch = prologue->arch;
1506 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1508 /* Is this the unchanged value of some register being saved on the
1510 if (value.kind == pvk_register
1512 && pv_is_register (addr, tdep->sp->num))
1514 /* Some registers require special handling: they're saved as a
1515 larger value than the register itself. */
1516 CORE_ADDR saved_size = register_size (arch, value.reg);
1518 if (value.reg == tdep->pc->num)
1519 saved_size = tdep->ret_addr_bytes;
1520 else if (register_type (arch, value.reg)
1521 == tdep->data_addr_reg_type)
1522 saved_size = tdep->push_addr_bytes;
1524 if (size == saved_size)
1526 /* Find which end of the saved value corresponds to our
1528 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
1529 prologue->reg_offset[value.reg]
1530 = (addr.k + saved_size - register_size (arch, value.reg));
1532 prologue->reg_offset[value.reg] = addr.k;
1538 /* Analyze the function prologue for ARCH at START, going no further
1539 than LIMIT, and place a description of what we found in
1542 m32c_analyze_prologue (struct gdbarch *arch,
1543 CORE_ADDR start, CORE_ADDR limit,
1544 struct m32c_prologue *prologue)
1546 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1547 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
1548 CORE_ADDR after_last_frame_related_insn;
1549 struct cleanup *back_to;
1550 struct m32c_pv_state st;
1553 st.r0 = pv_register (tdep->r0->num, 0);
1554 st.r1 = pv_register (tdep->r1->num, 0);
1555 st.r2 = pv_register (tdep->r2->num, 0);
1556 st.r3 = pv_register (tdep->r3->num, 0);
1557 st.a0 = pv_register (tdep->a0->num, 0);
1558 st.a1 = pv_register (tdep->a1->num, 0);
1559 st.sb = pv_register (tdep->sb->num, 0);
1560 st.fb = pv_register (tdep->fb->num, 0);
1561 st.sp = pv_register (tdep->sp->num, 0);
1562 st.pc = pv_register (tdep->pc->num, 0);
1563 st.stack = make_pv_area (tdep->sp->num, gdbarch_addr_bit (arch));
1564 back_to = make_cleanup_free_pv_area (st.stack);
1566 /* Record that the call instruction has saved the return address on
1568 m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes);
1570 memset (prologue, 0, sizeof (*prologue));
1571 prologue->arch = arch;
1574 for (i = 0; i < M32C_MAX_NUM_REGS; i++)
1575 prologue->reg_offset[i] = 1;
1578 st.scan_pc = after_last_frame_related_insn = start;
1580 while (st.scan_pc < limit)
1582 pv_t pre_insn_fb = st.fb;
1583 pv_t pre_insn_sp = st.sp;
1585 /* In theory we could get in trouble by trying to read ahead
1586 here, when we only know we're expecting one byte. In
1587 practice I doubt anyone will care, and it makes the rest of
1589 if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn)))
1590 /* If we can't fetch the instruction from memory, stop here
1591 and hope for the best. */
1593 st.next_addr = st.scan_pc;
1595 /* The assembly instructions are written as they appear in the
1596 section of the processor manuals that describe the
1597 instruction encodings.
1599 When a single assembly language instruction has several
1600 different machine-language encodings, the manual
1601 distinguishes them by a number in parens, before the
1602 mnemonic. Those numbers are included, as well.
1604 The srcdest decoding instructions have the same names as the
1605 analogous functions in the simulator. */
1606 if (mach == bfd_mach_m16c)
1608 /* (1) ENTER #imm8 */
1609 if (st.insn[0] == 0x7c && st.insn[1] == 0xf2)
1611 if (m32c_pv_enter (&st, st.insn[2]))
1616 else if (st.insn[0] == 0xec)
1618 int src = st.insn[1];
1619 if (m32c_pv_pushm (&st, src))
1623 if (m32c_pushm_is_reg_save (&st, src))
1624 after_last_frame_related_insn = st.next_addr;
1627 /* (6) MOV.size:G src, dest */
1628 else if ((st.insn[0] & 0xfe) == 0x72)
1630 int size = (st.insn[0] & 0x01) ? 2 : 1;
1632 struct srcdest dest;
1637 = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size);
1639 = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size);
1640 src_value = m32c_srcdest_fetch (&st, src, size);
1642 if (m32c_is_arg_spill (&st, dest, src_value))
1643 after_last_frame_related_insn = st.next_addr;
1644 else if (m32c_is_struct_return (&st, dest, src_value))
1645 after_last_frame_related_insn = st.next_addr;
1647 if (m32c_srcdest_store (&st, dest, src_value, size))
1651 /* (1) LDC #IMM16, sp */
1652 else if (st.insn[0] == 0xeb
1653 && st.insn[1] == 0x50)
1656 st.sp = pv_constant (m32c_udisp16 (&st));
1660 /* We've hit some instruction we don't know how to simulate.
1661 Strictly speaking, we should set every value we're
1662 tracking to "unknown". But we'll be optimistic, assume
1663 that we have enough information already, and stop
1669 int src_indirect = 0;
1670 int dest_indirect = 0;
1673 gdb_assert (mach == bfd_mach_m32c);
1675 /* Check for prefix bytes indicating indirect addressing. */
1676 if (st.insn[0] == 0x41)
1681 else if (st.insn[0] == 0x09)
1686 else if (st.insn[0] == 0x49)
1688 src_indirect = dest_indirect = 1;
1692 /* (1) ENTER #imm8 */
1693 if (st.insn[i] == 0xec)
1695 if (m32c_pv_enter (&st, st.insn[i + 1]))
1701 else if (st.insn[i] == 0x8f)
1703 int src = st.insn[i + 1];
1704 if (m32c_pv_pushm (&st, src))
1708 if (m32c_pushm_is_reg_save (&st, src))
1709 after_last_frame_related_insn = st.next_addr;
1712 /* (7) MOV.size:G src, dest */
1713 else if ((st.insn[i] & 0x80) == 0x80
1714 && (st.insn[i + 1] & 0x0f) == 0x0b
1715 && m32c_get_src23 (&st.insn[i]) < 20
1716 && m32c_get_dest23 (&st.insn[i]) < 20)
1719 struct srcdest dest;
1721 int bw = st.insn[i] & 0x01;
1722 int size = bw ? 2 : 1;
1726 = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]),
1727 size, src_indirect);
1729 = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]),
1730 size, dest_indirect);
1731 src_value = m32c_srcdest_fetch (&st, src, size);
1733 if (m32c_is_arg_spill (&st, dest, src_value))
1734 after_last_frame_related_insn = st.next_addr;
1736 if (m32c_srcdest_store (&st, dest, src_value, size))
1739 /* (2) LDC #IMM24, sp */
1740 else if (st.insn[i] == 0xd5
1741 && st.insn[i + 1] == 0x29)
1744 st.sp = pv_constant (m32c_udisp24 (&st));
1747 /* We've hit some instruction we don't know how to simulate.
1748 Strictly speaking, we should set every value we're
1749 tracking to "unknown". But we'll be optimistic, assume
1750 that we have enough information already, and stop
1755 /* If this instruction changed the FB or decreased the SP (i.e.,
1756 allocated more stack space), then this may be a good place to
1757 declare the prologue finished. However, there are some
1760 - If the instruction just changed the FB back to its original
1761 value, then that's probably a restore instruction. The
1762 prologue should definitely end before that.
1764 - If the instruction increased the value of the SP (that is,
1765 shrunk the frame), then it's probably part of a frame
1766 teardown sequence, and the prologue should end before
1769 if (! pv_is_identical (st.fb, pre_insn_fb))
1771 if (! pv_is_register_k (st.fb, tdep->fb->num, 0))
1772 after_last_frame_related_insn = st.next_addr;
1774 else if (! pv_is_identical (st.sp, pre_insn_sp))
1776 /* The comparison of the constants looks odd, there, because
1777 .k is unsigned. All it really means is that the SP is
1778 lower than it was before the instruction. */
1779 if ( pv_is_register (pre_insn_sp, tdep->sp->num)
1780 && pv_is_register (st.sp, tdep->sp->num)
1781 && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k)))
1782 after_last_frame_related_insn = st.next_addr;
1785 st.scan_pc = st.next_addr;
1788 /* Did we load a constant value into the stack pointer? */
1789 if (pv_is_constant (st.sp))
1790 prologue->kind = prologue_first_frame;
1792 /* Alternatively, did we initialize the frame pointer? Remember
1793 that the CFA is the address after the return address. */
1794 if (pv_is_register (st.fb, tdep->sp->num))
1796 prologue->kind = prologue_with_frame_ptr;
1797 prologue->frame_ptr_offset = st.fb.k;
1800 /* Is the frame size a known constant? Remember that frame_size is
1801 actually the offset from the CFA to the SP (i.e., a negative
1803 else if (pv_is_register (st.sp, tdep->sp->num))
1805 prologue->kind = prologue_sans_frame_ptr;
1806 prologue->frame_size = st.sp.k;
1809 /* We haven't been able to make sense of this function's frame. Treat
1810 it as the first frame. */
1812 prologue->kind = prologue_first_frame;
1814 /* Record where all the registers were saved. */
1815 pv_area_scan (st.stack, check_for_saved, (void *) prologue);
1817 prologue->prologue_end = after_last_frame_related_insn;
1819 do_cleanups (back_to);
1824 m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip)
1827 CORE_ADDR func_addr, func_end, sal_end;
1828 struct m32c_prologue p;
1830 /* Try to find the extent of the function that contains IP. */
1831 if (! find_pc_partial_function (ip, &name, &func_addr, &func_end))
1834 /* Find end by prologue analysis. */
1835 m32c_analyze_prologue (gdbarch, ip, func_end, &p);
1836 /* Find end by line info. */
1837 sal_end = skip_prologue_using_sal (gdbarch, ip);
1838 /* Return whichever is lower. */
1839 if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end)
1842 return p.prologue_end;
1847 /* Stack unwinding. */
1849 static struct m32c_prologue *
1850 m32c_analyze_frame_prologue (struct frame_info *this_frame,
1851 void **this_prologue_cache)
1853 if (! *this_prologue_cache)
1855 CORE_ADDR func_start = get_frame_func (this_frame);
1856 CORE_ADDR stop_addr = get_frame_pc (this_frame);
1858 /* If we couldn't find any function containing the PC, then
1859 just initialize the prologue cache, but don't do anything. */
1861 stop_addr = func_start;
1863 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue);
1864 m32c_analyze_prologue (get_frame_arch (this_frame),
1865 func_start, stop_addr,
1866 (struct m32c_prologue *) *this_prologue_cache);
1869 return (struct m32c_prologue *) *this_prologue_cache;
1874 m32c_frame_base (struct frame_info *this_frame,
1875 void **this_prologue_cache)
1877 struct m32c_prologue *p
1878 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache);
1879 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1881 /* In functions that use alloca, the distance between the stack
1882 pointer and the frame base varies dynamically, so we can't use
1883 the SP plus static information like prologue analysis to find the
1884 frame base. However, such functions must have a frame pointer,
1885 to be able to restore the SP on exit. So whenever we do have a
1886 frame pointer, use that to find the base. */
1889 case prologue_with_frame_ptr:
1892 = get_frame_register_unsigned (this_frame, tdep->fb->num);
1893 return fb - p->frame_ptr_offset;
1896 case prologue_sans_frame_ptr:
1899 = get_frame_register_unsigned (this_frame, tdep->sp->num);
1900 return sp - p->frame_size;
1903 case prologue_first_frame:
1907 gdb_assert_not_reached ("unexpected prologue kind");
1913 m32c_this_id (struct frame_info *this_frame,
1914 void **this_prologue_cache,
1915 struct frame_id *this_id)
1917 CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache);
1920 *this_id = frame_id_build (base, get_frame_func (this_frame));
1921 /* Otherwise, leave it unset, and that will terminate the backtrace. */
1925 static struct value *
1926 m32c_prev_register (struct frame_info *this_frame,
1927 void **this_prologue_cache, int regnum)
1929 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1930 struct m32c_prologue *p
1931 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache);
1932 CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache);
1934 if (regnum == tdep->sp->num)
1935 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1937 /* If prologue analysis says we saved this register somewhere,
1938 return a description of the stack slot holding it. */
1939 if (p->reg_offset[regnum] != 1)
1940 return frame_unwind_got_memory (this_frame, regnum,
1941 frame_base + p->reg_offset[regnum]);
1943 /* Otherwise, presume we haven't changed the value of this
1944 register, and get it from the next frame. */
1945 return frame_unwind_got_register (this_frame, regnum, regnum);
1949 static const struct frame_unwind m32c_unwind = {
1951 default_frame_unwind_stop_reason,
1955 default_frame_sniffer
1960 m32c_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1962 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1963 return frame_unwind_register_unsigned (next_frame, tdep->pc->num);
1968 m32c_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1970 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1971 return frame_unwind_register_unsigned (next_frame, tdep->sp->num);
1975 /* Inferior calls. */
1977 /* The calling conventions, according to GCC:
1981 First arg may be passed in r1l or r1 if it (1) fits (QImode or
1982 HImode), (2) is named, and (3) is an integer or pointer type (no
1983 structs, floats, etc). Otherwise, it's passed on the stack.
1985 Second arg may be passed in r2, same restrictions (but not QImode),
1986 even if the first arg is passed on the stack.
1988 Third and further args are passed on the stack. No padding is
1989 used, stack "alignment" is 8 bits.
1994 First arg may be passed in r0l or r0, same restrictions as above.
1996 Second and further args are passed on the stack. Padding is used
1997 after QImode parameters (i.e. lower-addressed byte is the value,
1998 higher-addressed byte is the padding), stack "alignment" is 16
2002 /* Return true if TYPE is a type that can be passed in registers. (We
2003 ignore the size, and pay attention only to the type code;
2004 acceptable sizes depends on which register is being considered to
2007 m32c_reg_arg_type (struct type *type)
2009 enum type_code code = TYPE_CODE (type);
2011 return (code == TYPE_CODE_INT
2012 || code == TYPE_CODE_ENUM
2013 || code == TYPE_CODE_PTR
2014 || code == TYPE_CODE_REF
2015 || code == TYPE_CODE_BOOL
2016 || code == TYPE_CODE_CHAR);
2021 m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2022 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2023 struct value **args, CORE_ADDR sp, int struct_return,
2024 CORE_ADDR struct_addr)
2026 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2027 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2028 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
2032 /* The number of arguments given in this function's prototype, or
2033 zero if it has a non-prototyped function type. The m32c ABI
2034 passes arguments mentioned in the prototype differently from
2035 those in the ellipsis of a varargs function, or from those passed
2036 to a non-prototyped function. */
2037 int num_prototyped_args = 0;
2040 struct type *func_type = value_type (function);
2042 /* Dereference function pointer types. */
2043 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
2044 func_type = TYPE_TARGET_TYPE (func_type);
2046 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC ||
2047 TYPE_CODE (func_type) == TYPE_CODE_METHOD);
2050 /* The ABI description in gcc/config/m32c/m32c.abi says that
2051 we need to handle prototyped and non-prototyped functions
2052 separately, but the code in GCC doesn't actually do so. */
2053 if (TYPE_PROTOTYPED (func_type))
2055 num_prototyped_args = TYPE_NFIELDS (func_type);
2058 /* First, if the function returns an aggregate by value, push a
2059 pointer to a buffer for it. This doesn't affect the way
2060 subsequent arguments are allocated to registers. */
2063 int ptr_len = TYPE_LENGTH (tdep->ptr_voyd);
2065 write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr);
2068 /* Push the arguments. */
2069 for (i = nargs - 1; i >= 0; i--)
2071 struct value *arg = args[i];
2072 const gdb_byte *arg_bits = value_contents (arg);
2073 struct type *arg_type = value_type (arg);
2074 ULONGEST arg_size = TYPE_LENGTH (arg_type);
2076 /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */
2079 && i < num_prototyped_args
2080 && m32c_reg_arg_type (arg_type))
2082 /* Extract and re-store as an integer as a terse way to make
2083 sure it ends up in the least significant end of r1. (GDB
2084 should avoid assuming endianness, even on uni-endian
2086 ULONGEST u = extract_unsigned_integer (arg_bits, arg_size,
2088 struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0;
2089 regcache_cooked_write_unsigned (regcache, reg->num, u);
2092 /* Can it go in r2? */
2093 else if (mach == bfd_mach_m16c
2096 && i < num_prototyped_args
2097 && m32c_reg_arg_type (arg_type))
2098 regcache_cooked_write (regcache, tdep->r2->num, arg_bits);
2100 /* Everything else goes on the stack. */
2105 /* Align the stack. */
2106 if (mach == bfd_mach_m32c)
2109 write_memory (sp, arg_bits, arg_size);
2113 /* This is the CFA we use to identify the dummy frame. */
2116 /* Push the return address. */
2117 sp -= tdep->ret_addr_bytes;
2118 write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order,
2121 /* Update the stack pointer. */
2122 regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp);
2124 /* We need to borrow an odd trick from the i386 target here.
2126 The value we return from this function gets used as the stack
2127 address (the CFA) for the dummy frame's ID. The obvious thing is
2128 to return the new TOS. However, that points at the return
2129 address, saved on the stack, which is inconsistent with the CFA's
2130 described by GCC's DWARF 2 .debug_frame information: DWARF 2
2131 .debug_frame info uses the address immediately after the saved
2132 return address. So you end up with a dummy frame whose CFA
2133 points at the return address, but the frame for the function
2134 being called has a CFA pointing after the return address: the
2135 younger CFA is *greater than* the older CFA. The sanity checks
2136 in frame.c don't like that.
2138 So we try to be consistent with the CFA's used by DWARF 2.
2139 Having a dummy frame and a real frame with the *same* CFA is
2145 static struct frame_id
2146 m32c_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2148 /* This needs to return a frame ID whose PC is the return address
2149 passed to m32c_push_dummy_call, and whose stack_addr is the SP
2150 m32c_push_dummy_call returned.
2152 m32c_unwind_sp gives us the CFA, which is the value the SP had
2153 before the return address was pushed. */
2154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2155 CORE_ADDR sp = get_frame_register_unsigned (this_frame, tdep->sp->num);
2156 return frame_id_build (sp, get_frame_pc (this_frame));
2161 /* Return values. */
2163 /* Return value conventions, according to GCC:
2174 Aggregate values (regardless of size) are returned by pushing a
2175 pointer to a temporary area on the stack after the args are pushed.
2176 The function fills in this area with the value. Note that this
2177 pointer on the stack does not affect how register arguments, if any,
2184 /* Return non-zero if values of type TYPE are returned by storing them
2185 in a buffer whose address is passed on the stack, ahead of the
2188 m32c_return_by_passed_buf (struct type *type)
2190 enum type_code code = TYPE_CODE (type);
2192 return (code == TYPE_CODE_STRUCT
2193 || code == TYPE_CODE_UNION);
2196 static enum return_value_convention
2197 m32c_return_value (struct gdbarch *gdbarch,
2198 struct value *function,
2199 struct type *valtype,
2200 struct regcache *regcache,
2202 const gdb_byte *writebuf)
2204 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2205 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2206 enum return_value_convention conv;
2207 ULONGEST valtype_len = TYPE_LENGTH (valtype);
2209 if (m32c_return_by_passed_buf (valtype))
2210 conv = RETURN_VALUE_STRUCT_CONVENTION;
2212 conv = RETURN_VALUE_REGISTER_CONVENTION;
2216 /* We should never be called to find values being returned by
2217 RETURN_VALUE_STRUCT_CONVENTION. Those can't be located,
2218 unless we made the call ourselves. */
2219 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2221 gdb_assert (valtype_len <= 8);
2223 /* Anything that fits in r0 is returned there. */
2224 if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2227 regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u);
2228 store_unsigned_integer (readbuf, valtype_len, byte_order, u);
2232 /* Everything else is passed in mem0, using as many bytes as
2233 needed. This is not what the Renesas tools do, but it's
2234 what GCC does at the moment. */
2235 struct bound_minimal_symbol mem0
2236 = lookup_minimal_symbol ("mem0", NULL, NULL);
2239 error (_("The return value is stored in memory at 'mem0', "
2240 "but GDB cannot find\n"
2242 read_memory (BMSYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len);
2248 /* We should never be called to store values to be returned
2249 using RETURN_VALUE_STRUCT_CONVENTION. We have no way of
2250 finding the buffer, unless we made the call ourselves. */
2251 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2253 gdb_assert (valtype_len <= 8);
2255 /* Anything that fits in r0 is returned there. */
2256 if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2258 ULONGEST u = extract_unsigned_integer (writebuf, valtype_len,
2260 regcache_cooked_write_unsigned (regcache, tdep->r0->num, u);
2264 /* Everything else is passed in mem0, using as many bytes as
2265 needed. This is not what the Renesas tools do, but it's
2266 what GCC does at the moment. */
2267 struct bound_minimal_symbol mem0
2268 = lookup_minimal_symbol ("mem0", NULL, NULL);
2271 error (_("The return value is stored in memory at 'mem0', "
2272 "but GDB cannot find\n"
2274 write_memory (BMSYMBOL_VALUE_ADDRESS (mem0), writebuf, valtype_len);
2285 /* The m16c and m32c use a trampoline function for indirect function
2286 calls. An indirect call looks like this:
2288 ... push arguments ...
2289 ... push target function address ...
2292 The code for m32c_jsri16 looks like this:
2296 # Save return address.
2298 pop.b m32c_jsri_ret+2
2300 # Store target function address.
2301 pop.w m32c_jsri_addr
2303 # Re-push return address.
2304 push.b m32c_jsri_ret+2
2305 push.w m32c_jsri_ret
2307 # Call the target function.
2308 jmpi.a m32c_jsri_addr
2310 Without further information, GDB will treat calls to m32c_jsri16
2311 like calls to any other function. Since m32c_jsri16 doesn't have
2312 debugging information, that normally means that GDB sets a step-
2313 resume breakpoint and lets the program continue --- which is not
2314 what the user wanted. (Giving the trampoline debugging info
2315 doesn't help: the user expects the program to stop in the function
2316 their program is calling, not in some trampoline code they've never
2319 The gdbarch_skip_trampoline_code method tells GDB how to step
2320 through such trampoline functions transparently to the user. When
2321 given the address of a trampoline function's first instruction,
2322 gdbarch_skip_trampoline_code should return the address of the first
2323 instruction of the function really being called. If GDB decides it
2324 wants to step into that function, it will set a breakpoint there
2325 and silently continue to it.
2327 We recognize the trampoline by name, and extract the target address
2328 directly from the stack. This isn't great, but recognizing by its
2329 code sequence seems more fragile. */
2332 m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc)
2334 struct gdbarch *gdbarch = get_frame_arch (frame);
2335 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2336 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2338 /* It would be nicer to simply look up the addresses of known
2339 trampolines once, and then compare stop_pc with them. However,
2340 we'd need to ensure that that cached address got invalidated when
2341 someone loaded a new executable, and I'm not quite sure of the
2342 best way to do that. find_pc_partial_function does do some
2343 caching, so we'll see how this goes. */
2345 CORE_ADDR start, end;
2347 if (find_pc_partial_function (stop_pc, &name, &start, &end))
2349 /* Are we stopped at the beginning of the trampoline function? */
2350 if (strcmp (name, "m32c_jsri16") == 0
2351 && stop_pc == start)
2353 /* Get the stack pointer. The return address is at the top,
2354 and the target function's address is just below that. We
2355 know it's a two-byte address, since the trampoline is
2357 CORE_ADDR sp = get_frame_sp (get_current_frame ());
2359 = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes,
2362 /* What we have now is the address of a jump instruction.
2363 What we need is the destination of that jump.
2364 The opcode is 1 byte, and the destination is the next 3 bytes. */
2366 target = read_memory_unsigned_integer (target + 1, 3, byte_order);
2375 /* Address/pointer conversions. */
2377 /* On the m16c, there is a 24-bit address space, but only a very few
2378 instructions can generate addresses larger than 0xffff: jumps,
2379 jumps to subroutines, and the lde/std (load/store extended)
2382 Since GCC can only support one size of pointer, we can't have
2383 distinct 'near' and 'far' pointer types; we have to pick one size
2384 for everything. If we wanted to use 24-bit pointers, then GCC
2385 would have to use lde and ste for all memory references, which
2386 would be terrible for performance and code size. So the GNU
2387 toolchain uses 16-bit pointers for everything, and gives up the
2388 ability to have pointers point outside the first 64k of memory.
2390 However, as a special hack, we let the linker place functions at
2391 addresses above 0xffff, as long as it also places a trampoline in
2392 the low 64k for every function whose address is taken. Each
2393 trampoline consists of a single jmp.a instruction that jumps to the
2394 function's real entry point. Pointers to functions can be 16 bits
2395 long, even though the functions themselves are at higher addresses:
2396 the pointers refer to the trampolines, not the functions.
2398 This complicates things for GDB, however: given the address of a
2399 function (from debug info or linker symbols, say) which could be
2400 anywhere in the 24-bit address space, how can we find an
2401 appropriate 16-bit value to use as a pointer to it?
2403 If the linker has not generated a trampoline for the function,
2404 we're out of luck. Well, I guess we could malloc some space and
2405 write a jmp.a instruction to it, but I'm not going to get into that
2408 If the linker has generated a trampoline for the function, then it
2409 also emitted a symbol for the trampoline: if the function's linker
2410 symbol is named NAME, then the function's trampoline's linker
2411 symbol is named NAME.plt.
2413 So, given a code address:
2414 - We try to find a linker symbol at that address.
2415 - If we find such a symbol named NAME, we look for a linker symbol
2417 - If we find such a symbol, we assume it is a trampoline, and use
2418 its address as the pointer value.
2420 And, given a function pointer:
2421 - We try to find a linker symbol at that address named NAME.plt.
2422 - If we find such a symbol, we look for a linker symbol named NAME.
2423 - If we find that, we provide that as the function's address.
2424 - If any of the above steps fail, we return the original address
2425 unchanged; it might really be a function in the low 64k.
2427 See? You *knew* there was a reason you wanted to be a computer
2431 m32c_m16c_address_to_pointer (struct gdbarch *gdbarch,
2432 struct type *type, gdb_byte *buf, CORE_ADDR addr)
2434 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2435 enum type_code target_code;
2436 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR ||
2437 TYPE_CODE (type) == TYPE_CODE_REF);
2439 target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2441 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2443 const char *func_name;
2445 struct bound_minimal_symbol tramp_msym;
2447 /* Try to find a linker symbol at this address. */
2448 struct bound_minimal_symbol func_msym
2449 = lookup_minimal_symbol_by_pc (addr);
2451 if (! func_msym.minsym)
2452 error (_("Cannot convert code address %s to function pointer:\n"
2453 "couldn't find a symbol at that address, to find trampoline."),
2454 paddress (gdbarch, addr));
2456 func_name = MSYMBOL_LINKAGE_NAME (func_msym.minsym);
2457 tramp_name = (char *) xmalloc (strlen (func_name) + 5);
2458 strcpy (tramp_name, func_name);
2459 strcat (tramp_name, ".plt");
2461 /* Try to find a linker symbol for the trampoline. */
2462 tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL);
2464 /* We've either got another copy of the name now, or don't need
2465 the name any more. */
2468 if (! tramp_msym.minsym)
2472 /* No PLT entry found. Mask off the upper bits of the address
2473 to make a pointer. As noted in the warning to the user
2474 below, this value might be useful if converted back into
2475 an address by GDB, but will otherwise, almost certainly,
2478 Using this masked result does seem to be useful
2479 in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into
2480 PASSes. These results appear to be correct as well.
2482 We print a warning here so that the user can make a
2483 determination about whether the result is useful or not. */
2484 ptrval = addr & 0xffff;
2486 warning (_("Cannot convert code address %s to function pointer:\n"
2487 "couldn't find trampoline named '%s.plt'.\n"
2488 "Returning pointer value %s instead; this may produce\n"
2489 "a useful result if converted back into an address by GDB,\n"
2490 "but will most likely not be useful otherwise.\n"),
2491 paddress (gdbarch, addr), func_name,
2492 paddress (gdbarch, ptrval));
2499 /* The trampoline's address is our pointer. */
2500 addr = BMSYMBOL_VALUE_ADDRESS (tramp_msym);
2504 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, addr);
2509 m32c_m16c_pointer_to_address (struct gdbarch *gdbarch,
2510 struct type *type, const gdb_byte *buf)
2512 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2514 enum type_code target_code;
2516 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR ||
2517 TYPE_CODE (type) == TYPE_CODE_REF);
2519 ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
2521 target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2523 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2525 /* See if there is a minimal symbol at that address whose name is
2527 struct bound_minimal_symbol ptr_msym = lookup_minimal_symbol_by_pc (ptr);
2529 if (ptr_msym.minsym)
2531 const char *ptr_msym_name = MSYMBOL_LINKAGE_NAME (ptr_msym.minsym);
2532 int len = strlen (ptr_msym_name);
2535 && strcmp (ptr_msym_name + len - 4, ".plt") == 0)
2537 struct bound_minimal_symbol func_msym;
2538 /* We have a .plt symbol; try to find the symbol for the
2539 corresponding function.
2541 Since the trampoline contains a jump instruction, we
2542 could also just extract the jump's target address. I
2543 don't see much advantage one way or the other. */
2544 char *func_name = (char *) xmalloc (len - 4 + 1);
2545 memcpy (func_name, ptr_msym_name, len - 4);
2546 func_name[len - 4] = '\0';
2548 = lookup_minimal_symbol (func_name, NULL, NULL);
2550 /* If we do have such a symbol, return its value as the
2551 function's true address. */
2552 if (func_msym.minsym)
2553 ptr = BMSYMBOL_VALUE_ADDRESS (func_msym);
2560 for (aspace = 1; aspace <= 15; aspace++)
2562 ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr);
2564 if (ptr_msym.minsym)
2565 ptr |= aspace << 16;
2574 m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
2576 LONGEST *frame_offset)
2579 CORE_ADDR func_addr, func_end;
2580 struct m32c_prologue p;
2582 struct regcache *regcache = get_current_regcache ();
2583 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2585 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
2586 internal_error (__FILE__, __LINE__,
2587 _("No virtual frame pointer available"));
2589 m32c_analyze_prologue (gdbarch, func_addr, pc, &p);
2592 case prologue_with_frame_ptr:
2593 *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num;
2594 *frame_offset = p.frame_ptr_offset;
2596 case prologue_sans_frame_ptr:
2597 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num;
2598 *frame_offset = p.frame_size;
2601 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num;
2606 if (*frame_regnum > gdbarch_num_regs (gdbarch))
2607 internal_error (__FILE__, __LINE__,
2608 _("No virtual frame pointer available"));
2612 /* Initialization. */
2614 static struct gdbarch *
2615 m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2617 struct gdbarch *gdbarch;
2618 struct gdbarch_tdep *tdep;
2619 unsigned long mach = info.bfd_arch_info->mach;
2621 /* Find a candidate among the list of architectures we've created
2623 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2625 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2626 return arches->gdbarch;
2628 tdep = XCNEW (struct gdbarch_tdep);
2629 gdbarch = gdbarch_alloc (&info, tdep);
2631 /* Essential types. */
2632 make_types (gdbarch);
2634 /* Address/pointer conversions. */
2635 if (mach == bfd_mach_m16c)
2637 set_gdbarch_address_to_pointer (gdbarch, m32c_m16c_address_to_pointer);
2638 set_gdbarch_pointer_to_address (gdbarch, m32c_m16c_pointer_to_address);
2642 make_regs (gdbarch);
2645 set_gdbarch_print_insn (gdbarch, print_insn_m32c);
2648 SET_GDBARCH_BREAKPOINT_MANIPULATION (m32c);
2650 /* Prologue analysis and unwinding. */
2651 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2652 set_gdbarch_skip_prologue (gdbarch, m32c_skip_prologue);
2653 set_gdbarch_unwind_pc (gdbarch, m32c_unwind_pc);
2654 set_gdbarch_unwind_sp (gdbarch, m32c_unwind_sp);
2656 /* I'm dropping the dwarf2 sniffer because it has a few problems.
2657 They may be in the dwarf2 cfi code in GDB, or they may be in
2658 the debug info emitted by the upstream toolchain. I don't
2659 know which, but I do know that the prologue analyzer works better.
2661 dwarf2_append_sniffers (gdbarch);
2663 frame_unwind_append_unwinder (gdbarch, &m32c_unwind);
2665 /* Inferior calls. */
2666 set_gdbarch_push_dummy_call (gdbarch, m32c_push_dummy_call);
2667 set_gdbarch_return_value (gdbarch, m32c_return_value);
2668 set_gdbarch_dummy_id (gdbarch, m32c_dummy_id);
2671 set_gdbarch_skip_trampoline_code (gdbarch, m32c_skip_trampoline_code);
2673 set_gdbarch_virtual_frame_pointer (gdbarch, m32c_virtual_frame_pointer);
2675 /* m32c function boundary addresses are not necessarily even.
2676 Therefore, the `vbit', which indicates a pointer to a virtual
2677 member function, is stored in the delta field, rather than as
2678 the low bit of a function pointer address.
2680 In order to verify this, see the definition of
2681 TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the
2682 definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */
2683 set_gdbarch_vbit_in_delta (gdbarch, 1);
2688 /* Provide a prototype to silence -Wmissing-prototypes. */
2689 extern initialize_file_ftype _initialize_m32c_tdep;
2692 _initialize_m32c_tdep (void)
2694 register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init);
2696 m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP);