1 /* Renesas M32C target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 2004-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb/sim-m32c.h"
27 #include "arch-utils.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
31 #include "dwarf2expr.h"
35 #include "reggroups.h"
36 #include "prologue-value.h"
41 /* The m32c tdep structure. */
43 static struct reggroup *m32c_dma_reggroup;
47 /* The type of a function that moves the value of REG between CACHE or
48 BUF --- in either direction. */
49 typedef enum register_status (m32c_write_reg_t) (struct m32c_reg *reg,
50 struct regcache *cache,
53 typedef enum register_status (m32c_read_reg_t) (struct m32c_reg *reg,
54 readable_regcache *cache,
59 /* The name of this register. */
65 /* The architecture this register belongs to. */
68 /* Its GDB register number. */
71 /* Its sim register number. */
74 /* Its DWARF register number, or -1 if it doesn't have one. */
77 /* Register group memberships. */
78 unsigned int general_p : 1;
79 unsigned int dma_p : 1;
80 unsigned int system_p : 1;
81 unsigned int save_restore_p : 1;
83 /* Functions to read its value from a regcache, and write its value
85 m32c_read_reg_t *read;
86 m32c_write_reg_t *write;
88 /* Data for READ and WRITE functions. The exact meaning depends on
89 the specific functions selected; see the comments for those
91 struct m32c_reg *rx, *ry;
96 /* An overestimate of the number of raw and pseudoregisters we will
97 have. The exact answer depends on the variant of the architecture
98 at hand, but we can use this to declare statically allocated
99 arrays, and bump it up when needed. */
100 #define M32C_MAX_NUM_REGS (75)
102 /* The largest assigned DWARF register number. */
103 #define M32C_MAX_DWARF_REGNUM (40)
108 /* All the registers for this variant, indexed by GDB register
109 number, and the number of registers present. */
110 struct m32c_reg regs[M32C_MAX_NUM_REGS];
112 /* The number of valid registers. */
115 /* Interesting registers. These are pointers into REGS. */
116 struct m32c_reg *pc, *flg;
117 struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1;
118 struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0;
119 struct m32c_reg *sb, *fb, *sp;
121 /* A table indexed by DWARF register numbers, pointing into
123 struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1];
125 /* Types for this architecture. We can't use the builtin_type_foo
126 types, because they're not initialized when building a gdbarch
128 struct type *voyd, *ptr_voyd, *func_voyd;
129 struct type *uint8, *uint16;
130 struct type *int8, *int16, *int32, *int64;
132 /* The types for data address and code address registers. */
133 struct type *data_addr_reg_type, *code_addr_reg_type;
135 /* The number of bytes a return address pushed by a 'jsr' instruction
136 occupies on the stack. */
139 /* The number of bytes an address register occupies on the stack
140 when saved by an 'enter' or 'pushm' instruction. */
148 make_types (struct gdbarch *arch)
150 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
151 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
152 int data_addr_reg_bits, code_addr_reg_bits;
156 /* This is used to clip CORE_ADDR values, so this value is
157 appropriate both on the m32c, where pointers are 32 bits long,
158 and on the m16c, where pointers are sixteen bits long, but there
159 may be code above the 64k boundary. */
160 set_gdbarch_addr_bit (arch, 24);
162 /* GCC uses 32 bits for addrs in the dwarf info, even though
163 only 16/24 bits are used. Setting addr_bit to 24 causes
164 errors in reading the dwarf addresses. */
165 set_gdbarch_addr_bit (arch, 32);
168 set_gdbarch_int_bit (arch, 16);
172 data_addr_reg_bits = 16;
173 code_addr_reg_bits = 24;
174 set_gdbarch_ptr_bit (arch, 16);
175 tdep->ret_addr_bytes = 3;
176 tdep->push_addr_bytes = 2;
180 data_addr_reg_bits = 24;
181 code_addr_reg_bits = 24;
182 set_gdbarch_ptr_bit (arch, 32);
183 tdep->ret_addr_bytes = 4;
184 tdep->push_addr_bytes = 4;
188 gdb_assert_not_reached ("unexpected mach");
191 /* The builtin_type_mumble variables are sometimes uninitialized when
192 this is called, so we avoid using them. */
193 tdep->voyd = arch_type (arch, TYPE_CODE_VOID, TARGET_CHAR_BIT, "void");
195 = arch_pointer_type (arch, gdbarch_ptr_bit (arch), NULL, tdep->voyd);
196 tdep->func_voyd = lookup_function_type (tdep->voyd);
198 xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t",
199 gdbarch_bfd_arch_info (arch)->printable_name);
200 tdep->data_addr_reg_type
201 = arch_pointer_type (arch, data_addr_reg_bits, type_name, tdep->voyd);
203 xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t",
204 gdbarch_bfd_arch_info (arch)->printable_name);
205 tdep->code_addr_reg_type
206 = arch_pointer_type (arch, code_addr_reg_bits, type_name, tdep->func_voyd);
208 tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t");
209 tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t");
210 tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t");
211 tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t");
212 tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t");
213 tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t");
221 m32c_register_name (struct gdbarch *gdbarch, int num)
223 return gdbarch_tdep (gdbarch)->regs[num].name;
228 m32c_register_type (struct gdbarch *arch, int reg_nr)
230 return gdbarch_tdep (arch)->regs[reg_nr].type;
235 m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr)
237 return gdbarch_tdep (gdbarch)->regs[reg_nr].sim_num;
242 m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr)
244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
245 if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM
246 && tdep->dwarf_regs[reg_nr])
247 return tdep->dwarf_regs[reg_nr]->num;
249 /* The DWARF CFI code expects to see -1 for invalid register
256 m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
257 struct reggroup *group)
259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
260 struct m32c_reg *reg = &tdep->regs[regnum];
262 /* The anonymous raw registers aren't in any groups. */
266 if (group == all_reggroup)
269 if (group == general_reggroup
273 if (group == m32c_dma_reggroup
277 if (group == system_reggroup
281 /* Since the m32c DWARF register numbers refer to cooked registers, not
282 raw registers, and frame_pop depends on the save and restore groups
283 containing registers the DWARF CFI will actually mention, our save
284 and restore groups are cooked registers, not raw registers. (This is
285 why we can't use the default reggroup function.) */
286 if ((group == save_reggroup
287 || group == restore_reggroup)
288 && reg->save_restore_p)
295 /* Register move functions. We declare them here using
296 m32c_{read,write}_reg_t to check the types. */
297 static m32c_read_reg_t m32c_raw_read;
298 static m32c_read_reg_t m32c_banked_read;
299 static m32c_read_reg_t m32c_sb_read;
300 static m32c_read_reg_t m32c_part_read;
301 static m32c_read_reg_t m32c_cat_read;
302 static m32c_read_reg_t m32c_r3r2r1r0_read;
304 static m32c_write_reg_t m32c_raw_write;
305 static m32c_write_reg_t m32c_banked_write;
306 static m32c_write_reg_t m32c_sb_write;
307 static m32c_write_reg_t m32c_part_write;
308 static m32c_write_reg_t m32c_cat_write;
309 static m32c_write_reg_t m32c_r3r2r1r0_write;
311 /* Copy the value of the raw register REG from CACHE to BUF. */
312 static enum register_status
313 m32c_raw_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf)
315 return cache->raw_read (reg->num, buf);
319 /* Copy the value of the raw register REG from BUF to CACHE. */
320 static enum register_status
321 m32c_raw_write (struct m32c_reg *reg, struct regcache *cache,
324 cache->raw_write (reg->num, buf);
330 /* Return the value of the 'flg' register in CACHE. */
332 m32c_read_flg (readable_regcache *cache)
334 struct gdbarch_tdep *tdep = gdbarch_tdep (cache->arch ());
337 cache->raw_read (tdep->flg->num, &flg);
342 /* Evaluate the real register number of a banked register. */
343 static struct m32c_reg *
344 m32c_banked_register (struct m32c_reg *reg, readable_regcache *cache)
346 return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx);
350 /* Move the value of a banked register from CACHE to BUF.
351 If the value of the 'flg' register in CACHE has any of the bits
352 masked in REG->n set, then read REG->ry. Otherwise, read
354 static enum register_status
355 m32c_banked_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf)
357 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
358 return cache->raw_read (bank_reg->num, buf);
362 /* Move the value of a banked register from BUF to CACHE.
363 If the value of the 'flg' register in CACHE has any of the bits
364 masked in REG->n set, then write REG->ry. Otherwise, write
366 static enum register_status
367 m32c_banked_write (struct m32c_reg *reg, struct regcache *cache,
370 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
371 cache->raw_write (bank_reg->num, buf);
377 /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a
378 banked register; on bfd_mach_m16c, it's not. */
379 static enum register_status
380 m32c_sb_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf)
382 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
383 return m32c_raw_read (reg->rx, cache, buf);
385 return m32c_banked_read (reg, cache, buf);
389 /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a
390 banked register; on bfd_mach_m16c, it's not. */
391 static enum register_status
392 m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, const gdb_byte *buf)
394 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
395 m32c_raw_write (reg->rx, cache, buf);
397 m32c_banked_write (reg, cache, buf);
403 /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P
404 and *LEN_P to the offset and length, in bytes, of the part REG
405 occupies in its underlying register. The offset is from the
406 lower-addressed end, regardless of the architecture's endianness.
407 (The M32C family is always little-endian, but let's keep those
408 assumptions out of here.) */
410 m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p)
412 /* The length of the containing register, of which REG is one part. */
413 int containing_len = TYPE_LENGTH (reg->rx->type);
415 /* The length of one "element" in our imaginary array. */
416 int elt_len = TYPE_LENGTH (reg->type);
418 /* The offset of REG's "element" from the least significant end of
419 the containing register. */
420 int elt_offset = reg->n * elt_len;
422 /* If we extend off the end, trim the length of the element. */
423 if (elt_offset + elt_len > containing_len)
425 elt_len = containing_len - elt_offset;
426 /* We shouldn't be declaring partial registers that go off the
427 end of their containing registers. */
428 gdb_assert (elt_len > 0);
431 /* Flip the offset around if we're big-endian. */
432 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
433 elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len;
435 *offset_p = elt_offset;
440 /* Move the value of a partial register (r0h, intbl, etc.) from CACHE
441 to BUF. Treating the value of the register REG->rx as an array of
442 REG->type values, where higher indices refer to more significant
443 bits, read the value of the REG->n'th element. */
444 static enum register_status
445 m32c_part_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf)
449 memset (buf, 0, TYPE_LENGTH (reg->type));
450 m32c_find_part (reg, &offset, &len);
451 return cache->cooked_read_part (reg->rx->num, offset, len, buf);
455 /* Move the value of a banked register from BUF to CACHE.
456 Treating the value of the register REG->rx as an array of REG->type
457 values, where higher indices refer to more significant bits, write
458 the value of the REG->n'th element. */
459 static enum register_status
460 m32c_part_write (struct m32c_reg *reg, struct regcache *cache,
465 m32c_find_part (reg, &offset, &len);
466 cache->cooked_write_part (reg->rx->num, offset, len, buf);
472 /* Move the value of REG from CACHE to BUF. REG's value is the
473 concatenation of the values of the registers REG->rx and REG->ry,
474 with REG->rx contributing the more significant bits. */
475 static enum register_status
476 m32c_cat_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf)
478 int high_bytes = TYPE_LENGTH (reg->rx->type);
479 int low_bytes = TYPE_LENGTH (reg->ry->type);
480 enum register_status status;
482 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
484 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
486 status = cache->cooked_read (reg->rx->num, buf);
487 if (status == REG_VALID)
488 status = cache->cooked_read (reg->ry->num, buf + high_bytes);
492 status = cache->cooked_read (reg->rx->num, buf + low_bytes);
493 if (status == REG_VALID)
494 status = cache->cooked_read (reg->ry->num, buf);
500 /* Move the value of REG from CACHE to BUF. REG's value is the
501 concatenation of the values of the registers REG->rx and REG->ry,
502 with REG->rx contributing the more significant bits. */
503 static enum register_status
504 m32c_cat_write (struct m32c_reg *reg, struct regcache *cache,
507 int high_bytes = TYPE_LENGTH (reg->rx->type);
508 int low_bytes = TYPE_LENGTH (reg->ry->type);
510 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
512 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
514 cache->cooked_write (reg->rx->num, buf);
515 cache->cooked_write (reg->ry->num, buf + high_bytes);
519 cache->cooked_write (reg->rx->num, buf + low_bytes);
520 cache->cooked_write (reg->ry->num, buf);
527 /* Copy the value of the raw register REG from CACHE to BUF. REG is
528 the concatenation (from most significant to least) of r3, r2, r1,
530 static enum register_status
531 m32c_r3r2r1r0_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf)
533 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
534 int len = TYPE_LENGTH (tdep->r0->type);
535 enum register_status status;
537 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
539 status = cache->cooked_read (tdep->r0->num, buf + len * 3);
540 if (status == REG_VALID)
541 status = cache->cooked_read (tdep->r1->num, buf + len * 2);
542 if (status == REG_VALID)
543 status = cache->cooked_read (tdep->r2->num, buf + len * 1);
544 if (status == REG_VALID)
545 status = cache->cooked_read (tdep->r3->num, buf);
549 status = cache->cooked_read (tdep->r0->num, buf);
550 if (status == REG_VALID)
551 status = cache->cooked_read (tdep->r1->num, buf + len * 1);
552 if (status == REG_VALID)
553 status = cache->cooked_read (tdep->r2->num, buf + len * 2);
554 if (status == REG_VALID)
555 status = cache->cooked_read (tdep->r3->num, buf + len * 3);
562 /* Copy the value of the raw register REG from BUF to CACHE. REG is
563 the concatenation (from most significant to least) of r3, r2, r1,
565 static enum register_status
566 m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache,
569 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
570 int len = TYPE_LENGTH (tdep->r0->type);
572 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
574 cache->cooked_write (tdep->r0->num, buf + len * 3);
575 cache->cooked_write (tdep->r1->num, buf + len * 2);
576 cache->cooked_write (tdep->r2->num, buf + len * 1);
577 cache->cooked_write (tdep->r3->num, buf);
581 cache->cooked_write (tdep->r0->num, buf);
582 cache->cooked_write (tdep->r1->num, buf + len * 1);
583 cache->cooked_write (tdep->r2->num, buf + len * 2);
584 cache->cooked_write (tdep->r3->num, buf + len * 3);
591 static enum register_status
592 m32c_pseudo_register_read (struct gdbarch *arch,
593 readable_regcache *cache,
597 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
598 struct m32c_reg *reg;
600 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
601 gdb_assert (arch == cache->arch ());
602 gdb_assert (arch == tdep->regs[cookednum].arch);
603 reg = &tdep->regs[cookednum];
605 return reg->read (reg, cache, buf);
610 m32c_pseudo_register_write (struct gdbarch *arch,
611 struct regcache *cache,
615 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
616 struct m32c_reg *reg;
618 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
619 gdb_assert (arch == cache->arch ());
620 gdb_assert (arch == tdep->regs[cookednum].arch);
621 reg = &tdep->regs[cookednum];
623 reg->write (reg, cache, buf);
627 /* Add a register with the given fields to the end of ARCH's table.
628 Return a pointer to the newly added register. */
629 static struct m32c_reg *
630 add_reg (struct gdbarch *arch,
634 m32c_read_reg_t *read,
635 m32c_write_reg_t *write,
640 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
641 struct m32c_reg *r = &tdep->regs[tdep->num_regs];
643 gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS);
648 r->num = tdep->num_regs;
649 r->sim_num = sim_num;
654 r->save_restore_p = 0;
667 /* Record NUM as REG's DWARF register number. */
669 set_dwarf_regnum (struct m32c_reg *reg, int num)
671 gdb_assert (num < M32C_MAX_NUM_REGS);
673 /* Update the reg->DWARF mapping. Only count the first number
674 assigned to this register. */
675 if (reg->dwarf_num == -1)
676 reg->dwarf_num = num;
678 /* Update the DWARF->reg mapping. */
679 gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg;
683 /* Mark REG as a general-purpose register, and return it. */
684 static struct m32c_reg *
685 mark_general (struct m32c_reg *reg)
692 /* Mark REG as a DMA register. */
694 mark_dma (struct m32c_reg *reg)
700 /* Mark REG as a SYSTEM register, and return it. */
701 static struct m32c_reg *
702 mark_system (struct m32c_reg *reg)
709 /* Mark REG as a save-restore register, and return it. */
710 static struct m32c_reg *
711 mark_save_restore (struct m32c_reg *reg)
713 reg->save_restore_p = 1;
718 #define FLAGBIT_B 0x0010
719 #define FLAGBIT_U 0x0080
721 /* Handy macros for declaring registers. These all evaluate to
722 pointers to the register declared. Macros that define two
723 registers evaluate to a pointer to the first. */
725 /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */
726 #define R(name, type, sim_num) \
727 (add_reg (arch, (name), (type), (sim_num), \
728 m32c_raw_read, m32c_raw_write, NULL, NULL, 0))
730 /* The simulator register number for a raw register named NAME. */
731 #define SIM(name) (m32c_sim_reg_ ## name)
733 /* A raw unsigned 16-bit data register named NAME.
734 NAME should be an identifier, not a string. */
736 (R(#name, tdep->uint16, SIM (name)))
738 /* A raw data address register named NAME.
739 NAME should be an identifier, not a string. */
741 (R(#name, tdep->data_addr_reg_type, SIM (name)))
743 /* A raw code address register named NAME. NAME should
744 be an identifier, not a string. */
746 (R(#name, tdep->code_addr_reg_type, SIM (name)))
748 /* A pair of raw registers named NAME0 and NAME1, with type TYPE.
749 NAME should be an identifier, not a string. */
750 #define RP(name, type) \
751 (R(#name "0", (type), SIM (name ## 0)), \
752 R(#name "1", (type), SIM (name ## 1)) - 1)
754 /* A raw banked general-purpose data register named NAME.
755 NAME should be an identifier, not a string. */
757 (R(NULL, tdep->int16, SIM (name ## _bank0)), \
758 R(NULL, tdep->int16, SIM (name ## _bank1)) - 1)
760 /* A raw banked data address register named NAME.
761 NAME should be an identifier, not a string. */
763 (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \
764 R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1)
766 /* A cooked register named NAME referring to a raw banked register
767 from the bank selected by the current value of FLG. RAW_PAIR
768 should be a pointer to the first register in the banked pair.
769 NAME must be an identifier, not a string. */
770 #define CB(name, raw_pair) \
771 (add_reg (arch, #name, (raw_pair)->type, 0, \
772 m32c_banked_read, m32c_banked_write, \
773 (raw_pair), (raw_pair + 1), FLAGBIT_B))
775 /* A pair of registers named NAMEH and NAMEL, of type TYPE, that
776 access the top and bottom halves of the register pointed to by
777 NAME. NAME should be an identifier. */
778 #define CHL(name, type) \
779 (add_reg (arch, #name "h", (type), 0, \
780 m32c_part_read, m32c_part_write, name, NULL, 1), \
781 add_reg (arch, #name "l", (type), 0, \
782 m32c_part_read, m32c_part_write, name, NULL, 0) - 1)
784 /* A register constructed by concatenating the two registers HIGH and
785 LOW, whose name is HIGHLOW and whose type is TYPE. */
786 #define CCAT(high, low, type) \
787 (add_reg (arch, #high #low, (type), 0, \
788 m32c_cat_read, m32c_cat_write, (high), (low), 0))
790 /* Abbreviations for marking register group membership. */
791 #define G(reg) (mark_general (reg))
792 #define S(reg) (mark_system (reg))
793 #define DMA(reg) (mark_dma (reg))
796 /* Construct the register set for ARCH. */
798 make_regs (struct gdbarch *arch)
800 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
801 int mach = gdbarch_bfd_arch_info (arch)->mach;
814 struct m32c_reg *r0hl;
815 struct m32c_reg *r1hl;
816 struct m32c_reg *r2r0;
817 struct m32c_reg *r3r1;
818 struct m32c_reg *r3r1r2r0;
819 struct m32c_reg *r3r2r1r0;
820 struct m32c_reg *a1a0;
822 struct m32c_reg *raw_r0_pair = RBD (r0);
823 struct m32c_reg *raw_r1_pair = RBD (r1);
824 struct m32c_reg *raw_r2_pair = RBD (r2);
825 struct m32c_reg *raw_r3_pair = RBD (r3);
826 struct m32c_reg *raw_a0_pair = RBA (a0);
827 struct m32c_reg *raw_a1_pair = RBA (a1);
828 struct m32c_reg *raw_fb_pair = RBA (fb);
830 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
831 We always declare both raw registers, and deal with the distinction
832 in the pseudoregister. */
833 struct m32c_reg *raw_sb_pair = RBA (sb);
835 struct m32c_reg *usp = S (RA (usp));
836 struct m32c_reg *isp = S (RA (isp));
837 struct m32c_reg *intb = S (RC (intb));
838 struct m32c_reg *pc = G (RC (pc));
839 struct m32c_reg *flg = G (R16U (flg));
841 if (mach == bfd_mach_m32c)
847 DMA (RP (dmd, tdep->uint8));
848 DMA (RP (dct, tdep->uint16));
849 DMA (RP (drc, tdep->uint16));
850 DMA (RP (dma, tdep->data_addr_reg_type));
851 DMA (RP (dsa, tdep->data_addr_reg_type));
852 DMA (RP (dra, tdep->data_addr_reg_type));
855 num_raw_regs = tdep->num_regs;
857 r0 = G (CB (r0, raw_r0_pair));
858 r1 = G (CB (r1, raw_r1_pair));
859 r2 = G (CB (r2, raw_r2_pair));
860 r3 = G (CB (r3, raw_r3_pair));
861 a0 = G (CB (a0, raw_a0_pair));
862 a1 = G (CB (a1, raw_a1_pair));
863 fb = G (CB (fb, raw_fb_pair));
865 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
866 Specify custom read/write functions that do the right thing. */
867 sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0,
868 m32c_sb_read, m32c_sb_write,
869 raw_sb_pair, raw_sb_pair + 1, 0));
871 /* The current sp is either usp or isp, depending on the value of
872 the FLG register's U bit. */
873 sp = G (add_reg (arch, "sp", usp->type, 0,
874 m32c_banked_read, m32c_banked_write,
875 isp, usp, FLAGBIT_U));
877 r0hl = CHL (r0, tdep->int8);
878 r1hl = CHL (r1, tdep->int8);
879 CHL (r2, tdep->int8);
880 CHL (r3, tdep->int8);
881 CHL (intb, tdep->int16);
883 r2r0 = CCAT (r2, r0, tdep->int32);
884 r3r1 = CCAT (r3, r1, tdep->int32);
885 r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64);
888 = add_reg (arch, "r3r2r1r0", tdep->int64, 0,
889 m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0);
891 if (mach == bfd_mach_m16c)
892 a1a0 = CCAT (a1, a0, tdep->int32);
896 num_cooked_regs = tdep->num_regs - num_raw_regs;
905 tdep->r3r2r1r0 = r3r2r1r0;
906 tdep->r3r1r2r0 = r3r1r2r0;
913 /* Set up the DWARF register table. */
914 memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs));
915 set_dwarf_regnum (r0hl + 1, 0x01);
916 set_dwarf_regnum (r0hl + 0, 0x02);
917 set_dwarf_regnum (r1hl + 1, 0x03);
918 set_dwarf_regnum (r1hl + 0, 0x04);
919 set_dwarf_regnum (r0, 0x05);
920 set_dwarf_regnum (r1, 0x06);
921 set_dwarf_regnum (r2, 0x07);
922 set_dwarf_regnum (r3, 0x08);
923 set_dwarf_regnum (a0, 0x09);
924 set_dwarf_regnum (a1, 0x0a);
925 set_dwarf_regnum (fb, 0x0b);
926 set_dwarf_regnum (sp, 0x0c);
927 set_dwarf_regnum (pc, 0x0d); /* GCC's invention */
928 set_dwarf_regnum (sb, 0x13);
929 set_dwarf_regnum (r2r0, 0x15);
930 set_dwarf_regnum (r3r1, 0x16);
932 set_dwarf_regnum (a1a0, 0x17);
934 /* Enumerate the save/restore register group.
936 The regcache_save and regcache_restore functions apply their read
937 function to each register in this group.
939 Since frame_pop supplies frame_unwind_register as its read
940 function, the registers meaningful to the Dwarf unwinder need to
943 On the other hand, when we make inferior calls, save_inferior_status
944 and restore_inferior_status use them to preserve the current register
945 values across the inferior call. For this, you'd kind of like to
946 preserve all the raw registers, to protect the interrupted code from
947 any sort of bank switching the callee might have done. But we handle
948 those cases so badly anyway --- for example, it matters whether we
949 restore FLG before or after we restore the general-purpose registers,
950 but there's no way to express that --- that it isn't worth worrying
953 We omit control registers like inthl: if you call a function that
954 changes those, it's probably because you wanted that change to be
955 visible to the interrupted code. */
956 mark_save_restore (r0);
957 mark_save_restore (r1);
958 mark_save_restore (r2);
959 mark_save_restore (r3);
960 mark_save_restore (a0);
961 mark_save_restore (a1);
962 mark_save_restore (sb);
963 mark_save_restore (fb);
964 mark_save_restore (sp);
965 mark_save_restore (pc);
966 mark_save_restore (flg);
968 set_gdbarch_num_regs (arch, num_raw_regs);
969 set_gdbarch_num_pseudo_regs (arch, num_cooked_regs);
970 set_gdbarch_pc_regnum (arch, pc->num);
971 set_gdbarch_sp_regnum (arch, sp->num);
972 set_gdbarch_register_name (arch, m32c_register_name);
973 set_gdbarch_register_type (arch, m32c_register_type);
974 set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read);
975 set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write);
976 set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno);
977 set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
978 set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
979 set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p);
981 reggroup_add (arch, general_reggroup);
982 reggroup_add (arch, all_reggroup);
983 reggroup_add (arch, save_reggroup);
984 reggroup_add (arch, restore_reggroup);
985 reggroup_add (arch, system_reggroup);
986 reggroup_add (arch, m32c_dma_reggroup);
992 constexpr gdb_byte m32c_break_insn[] = { 0x00 }; /* brk */
994 typedef BP_MANIPULATION (m32c_break_insn) m32c_breakpoint;
997 /* Prologue analysis. */
999 enum m32c_prologue_kind
1001 /* This function uses a frame pointer. */
1002 prologue_with_frame_ptr,
1004 /* This function has no frame pointer. */
1005 prologue_sans_frame_ptr,
1007 /* This function sets up the stack, so its frame is the first
1008 frame on the stack. */
1009 prologue_first_frame
1012 struct m32c_prologue
1014 /* For consistency with the DWARF 2 .debug_frame info generated by
1015 GCC, a frame's CFA is the address immediately after the saved
1018 /* The architecture for which we generated this prologue info. */
1019 struct gdbarch *arch;
1021 enum m32c_prologue_kind kind;
1023 /* If KIND is prologue_with_frame_ptr, this is the offset from the
1024 CFA to where the frame pointer points. This is always zero or
1026 LONGEST frame_ptr_offset;
1028 /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to
1029 the stack pointer --- always zero or negative.
1031 Calling this a "size" is a bit misleading, but given that the
1032 stack grows downwards, using offsets for everything keeps one
1033 from going completely sign-crazy: you never change anything's
1034 sign for an ADD instruction; always change the second operand's
1035 sign for a SUB instruction; and everything takes care of
1038 Functions that use alloca don't have a constant frame size. But
1039 they always have frame pointers, so we must use that to find the
1040 CFA (and perhaps to unwind the stack pointer). */
1043 /* The address of the first instruction at which the frame has been
1044 set up and the arguments are where the debug info says they are
1045 --- as best as we can tell. */
1046 CORE_ADDR prologue_end;
1048 /* reg_offset[R] is the offset from the CFA at which register R is
1049 saved, or 1 if register R has not been saved. (Real values are
1050 always zero or negative.) */
1051 LONGEST reg_offset[M32C_MAX_NUM_REGS];
1055 /* The longest I've seen, anyway. */
1056 #define M32C_MAX_INSN_LEN (9)
1058 /* Processor state, for the prologue analyzer. */
1059 struct m32c_pv_state
1061 struct gdbarch *arch;
1062 pv_t r0, r1, r2, r3;
1066 struct pv_area *stack;
1068 /* Bytes from the current PC, the address they were read from,
1069 and the address of the next unconsumed byte. */
1070 gdb_byte insn[M32C_MAX_INSN_LEN];
1071 CORE_ADDR scan_pc, next_addr;
1075 /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if
1076 all went well, or non-zero if simulating the action would trash our
1079 m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size)
1081 if (state->stack->store_would_trash (state->sp))
1084 state->sp = pv_add_constant (state->sp, -size);
1085 state->stack->store (state->sp, size, value);
1094 srcdest_partial_reg,
1098 /* A source or destination location for an m16c or m32c
1102 /* If srcdest_reg, the location is a register pointed to by REG.
1103 If srcdest_partial_reg, the location is part of a register pointed
1104 to by REG. We don't try to handle this too well.
1105 If srcdest_mem, the location is memory whose address is ADDR. */
1106 enum srcdest_kind kind;
1111 /* Return the SIZE-byte value at LOC in STATE. */
1113 m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size)
1115 if (loc.kind == srcdest_mem)
1116 return state->stack->fetch (loc.addr, size);
1117 else if (loc.kind == srcdest_partial_reg)
1118 return pv_unknown ();
1124 /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if
1125 all went well, or non-zero if simulating the store would trash our
1128 m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc,
1129 pv_t value, int size)
1131 if (loc.kind == srcdest_mem)
1133 if (state->stack->store_would_trash (loc.addr))
1135 state->stack->store (loc.addr, size, value);
1137 else if (loc.kind == srcdest_partial_reg)
1138 *loc.reg = pv_unknown ();
1147 m32c_sign_ext (int v, int bits)
1149 int mask = 1 << (bits - 1);
1150 return (v ^ mask) - mask;
1154 m32c_next_byte (struct m32c_pv_state *st)
1156 gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn));
1157 return st->insn[st->next_addr++ - st->scan_pc];
1161 m32c_udisp8 (struct m32c_pv_state *st)
1163 return m32c_next_byte (st);
1168 m32c_sdisp8 (struct m32c_pv_state *st)
1170 return m32c_sign_ext (m32c_next_byte (st), 8);
1175 m32c_udisp16 (struct m32c_pv_state *st)
1177 int low = m32c_next_byte (st);
1178 int high = m32c_next_byte (st);
1180 return low + (high << 8);
1185 m32c_sdisp16 (struct m32c_pv_state *st)
1187 int low = m32c_next_byte (st);
1188 int high = m32c_next_byte (st);
1190 return m32c_sign_ext (low + (high << 8), 16);
1195 m32c_udisp24 (struct m32c_pv_state *st)
1197 int low = m32c_next_byte (st);
1198 int mid = m32c_next_byte (st);
1199 int high = m32c_next_byte (st);
1201 return low + (mid << 8) + (high << 16);
1205 /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */
1207 m32c_get_src23 (unsigned char *i)
1209 return (((i[0] & 0x70) >> 2)
1210 | ((i[1] & 0x30) >> 4));
1214 /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */
1216 m32c_get_dest23 (unsigned char *i)
1218 return (((i[0] & 0x0e) << 1)
1219 | ((i[1] & 0xc0) >> 6));
1223 static struct srcdest
1224 m32c_decode_srcdest4 (struct m32c_pv_state *st,
1230 sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg);
1232 sd.kind = srcdest_mem;
1234 sd.addr = pv_unknown ();
1239 case 0x0: sd.reg = (size == 1 ? &st->r0 : &st->r0); break;
1240 case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break;
1241 case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break;
1242 case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break;
1244 case 0x4: sd.reg = &st->a0; break;
1245 case 0x5: sd.reg = &st->a1; break;
1247 case 0x6: sd.addr = st->a0; break;
1248 case 0x7: sd.addr = st->a1; break;
1250 case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1251 case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1252 case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1253 case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1255 case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1256 case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1257 case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1258 case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1261 gdb_assert_not_reached ("unexpected srcdest4");
1268 static struct srcdest
1269 m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind)
1273 sd.addr = pv_unknown ();
1282 sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg;
1287 sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg;
1291 sd.kind = srcdest_mem;
1298 case 0x12: sd.reg = &st->r0; break;
1299 case 0x13: sd.reg = &st->r1; break;
1300 case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break;
1301 case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break;
1302 case 0x02: sd.reg = &st->a0; break;
1303 case 0x03: sd.reg = &st->a1; break;
1305 case 0x00: sd.addr = st->a0; break;
1306 case 0x01: sd.addr = st->a1; break;
1307 case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1308 case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1309 case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1310 case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1311 case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1312 case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1313 case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1314 case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break;
1315 case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break;
1316 case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break;
1317 case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1318 case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break;
1320 gdb_assert_not_reached ("unexpected sd23");
1325 sd.addr = m32c_srcdest_fetch (st, sd, 4);
1326 sd.kind = srcdest_mem;
1333 /* The r16c and r32c machines have instructions with similar
1334 semantics, but completely different machine language encodings. So
1335 we break out the semantics into their own functions, and leave
1336 machine-specific decoding in m32c_analyze_prologue.
1338 The following functions all expect their arguments already decoded,
1339 and they all return zero if analysis should continue past this
1340 instruction, or non-zero if analysis should stop. */
1343 /* Simulate an 'enter SIZE' instruction in STATE. */
1345 m32c_pv_enter (struct m32c_pv_state *state, int size)
1347 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1349 /* If simulating this store would require us to forget
1350 everything we know about the stack frame in the name of
1351 accuracy, it would be better to just quit now. */
1352 if (state->stack->store_would_trash (state->sp))
1355 if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes))
1357 state->fb = state->sp;
1358 state->sp = pv_add_constant (state->sp, -size);
1365 m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg,
1366 int bit, int src, int size)
1370 if (m32c_pv_push (state, reg, size))
1378 /* Simulate a 'pushm SRC' instruction in STATE. */
1380 m32c_pv_pushm (struct m32c_pv_state *state, int src)
1382 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1384 /* The bits in SRC indicating which registers to save are:
1385 r0 r1 r2 r3 a0 a1 sb fb */
1387 ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes)
1388 || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes)
1389 || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes)
1390 || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes)
1391 || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2)
1392 || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2)
1393 || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2)
1394 || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2));
1397 /* Return non-zero if VALUE is the first incoming argument register. */
1400 m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value)
1402 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1403 return (value.kind == pvk_register
1404 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1405 ? (value.reg == tdep->r1->num)
1406 : (value.reg == tdep->r0->num))
1410 /* Return non-zero if VALUE is an incoming argument register. */
1413 m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value)
1415 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1416 return (value.kind == pvk_register
1417 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1418 ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num)
1419 : (value.reg == tdep->r0->num))
1423 /* Return non-zero if a store of VALUE to LOC is probably spilling an
1424 argument register to its stack slot in STATE. Such instructions
1425 should be included in the prologue, if possible.
1427 The store is a spill if:
1428 - the value being stored is the original value of an argument register;
1429 - the value has not already been stored somewhere in STACK; and
1430 - LOC is a stack slot (e.g., a memory location whose address is
1431 relative to the original value of the SP). */
1434 m32c_is_arg_spill (struct m32c_pv_state *st,
1438 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1440 return (m32c_is_arg_reg (st, value)
1441 && loc.kind == srcdest_mem
1442 && pv_is_register (loc.addr, tdep->sp->num)
1443 && ! st->stack->find_reg (st->arch, value.reg, 0));
1446 /* Return non-zero if a store of VALUE to LOC is probably
1447 copying the struct return address into an address register
1448 for immediate use. This is basically a "spill" into the
1449 address register, instead of onto the stack.
1451 The prerequisites are:
1452 - value being stored is original value of the FIRST arg register;
1453 - value has not already been stored on stack; and
1454 - LOC is an address register (a0 or a1). */
1457 m32c_is_struct_return (struct m32c_pv_state *st,
1461 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1463 return (m32c_is_1st_arg_reg (st, value)
1464 && !st->stack->find_reg (st->arch, value.reg, 0)
1465 && loc.kind == srcdest_reg
1466 && (pv_is_register (*loc.reg, tdep->a0->num)
1467 || pv_is_register (*loc.reg, tdep->a1->num)));
1470 /* Return non-zero if a 'pushm' saving the registers indicated by SRC
1471 was a register save:
1472 - all the named registers should have their original values, and
1473 - the stack pointer should be at a constant offset from the
1474 original stack pointer. */
1476 m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src)
1478 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1479 /* The bits in SRC indicating which registers to save are:
1480 r0 r1 r2 r3 a0 a1 sb fb */
1482 (pv_is_register (st->sp, tdep->sp->num)
1483 && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0))
1484 && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0))
1485 && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0))
1486 && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0))
1487 && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0))
1488 && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0))
1489 && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0))
1490 && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0)));
1494 /* Function for finding saved registers in a 'struct pv_area'; we pass
1495 this to pv_area::scan.
1497 If VALUE is a saved register, ADDR says it was saved at a constant
1498 offset from the frame base, and SIZE indicates that the whole
1499 register was saved, record its offset in RESULT_UNTYPED. */
1501 check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value)
1503 struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped;
1504 struct gdbarch *arch = prologue->arch;
1505 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1507 /* Is this the unchanged value of some register being saved on the
1509 if (value.kind == pvk_register
1511 && pv_is_register (addr, tdep->sp->num))
1513 /* Some registers require special handling: they're saved as a
1514 larger value than the register itself. */
1515 CORE_ADDR saved_size = register_size (arch, value.reg);
1517 if (value.reg == tdep->pc->num)
1518 saved_size = tdep->ret_addr_bytes;
1519 else if (register_type (arch, value.reg)
1520 == tdep->data_addr_reg_type)
1521 saved_size = tdep->push_addr_bytes;
1523 if (size == saved_size)
1525 /* Find which end of the saved value corresponds to our
1527 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
1528 prologue->reg_offset[value.reg]
1529 = (addr.k + saved_size - register_size (arch, value.reg));
1531 prologue->reg_offset[value.reg] = addr.k;
1537 /* Analyze the function prologue for ARCH at START, going no further
1538 than LIMIT, and place a description of what we found in
1541 m32c_analyze_prologue (struct gdbarch *arch,
1542 CORE_ADDR start, CORE_ADDR limit,
1543 struct m32c_prologue *prologue)
1545 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1546 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
1547 CORE_ADDR after_last_frame_related_insn;
1548 struct m32c_pv_state st;
1551 st.r0 = pv_register (tdep->r0->num, 0);
1552 st.r1 = pv_register (tdep->r1->num, 0);
1553 st.r2 = pv_register (tdep->r2->num, 0);
1554 st.r3 = pv_register (tdep->r3->num, 0);
1555 st.a0 = pv_register (tdep->a0->num, 0);
1556 st.a1 = pv_register (tdep->a1->num, 0);
1557 st.sb = pv_register (tdep->sb->num, 0);
1558 st.fb = pv_register (tdep->fb->num, 0);
1559 st.sp = pv_register (tdep->sp->num, 0);
1560 st.pc = pv_register (tdep->pc->num, 0);
1561 pv_area stack (tdep->sp->num, gdbarch_addr_bit (arch));
1564 /* Record that the call instruction has saved the return address on
1566 m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes);
1568 memset (prologue, 0, sizeof (*prologue));
1569 prologue->arch = arch;
1572 for (i = 0; i < M32C_MAX_NUM_REGS; i++)
1573 prologue->reg_offset[i] = 1;
1576 st.scan_pc = after_last_frame_related_insn = start;
1578 while (st.scan_pc < limit)
1580 pv_t pre_insn_fb = st.fb;
1581 pv_t pre_insn_sp = st.sp;
1583 /* In theory we could get in trouble by trying to read ahead
1584 here, when we only know we're expecting one byte. In
1585 practice I doubt anyone will care, and it makes the rest of
1587 if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn)))
1588 /* If we can't fetch the instruction from memory, stop here
1589 and hope for the best. */
1591 st.next_addr = st.scan_pc;
1593 /* The assembly instructions are written as they appear in the
1594 section of the processor manuals that describe the
1595 instruction encodings.
1597 When a single assembly language instruction has several
1598 different machine-language encodings, the manual
1599 distinguishes them by a number in parens, before the
1600 mnemonic. Those numbers are included, as well.
1602 The srcdest decoding instructions have the same names as the
1603 analogous functions in the simulator. */
1604 if (mach == bfd_mach_m16c)
1606 /* (1) ENTER #imm8 */
1607 if (st.insn[0] == 0x7c && st.insn[1] == 0xf2)
1609 if (m32c_pv_enter (&st, st.insn[2]))
1614 else if (st.insn[0] == 0xec)
1616 int src = st.insn[1];
1617 if (m32c_pv_pushm (&st, src))
1621 if (m32c_pushm_is_reg_save (&st, src))
1622 after_last_frame_related_insn = st.next_addr;
1625 /* (6) MOV.size:G src, dest */
1626 else if ((st.insn[0] & 0xfe) == 0x72)
1628 int size = (st.insn[0] & 0x01) ? 2 : 1;
1630 struct srcdest dest;
1635 = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size);
1637 = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size);
1638 src_value = m32c_srcdest_fetch (&st, src, size);
1640 if (m32c_is_arg_spill (&st, dest, src_value))
1641 after_last_frame_related_insn = st.next_addr;
1642 else if (m32c_is_struct_return (&st, dest, src_value))
1643 after_last_frame_related_insn = st.next_addr;
1645 if (m32c_srcdest_store (&st, dest, src_value, size))
1649 /* (1) LDC #IMM16, sp */
1650 else if (st.insn[0] == 0xeb
1651 && st.insn[1] == 0x50)
1654 st.sp = pv_constant (m32c_udisp16 (&st));
1658 /* We've hit some instruction we don't know how to simulate.
1659 Strictly speaking, we should set every value we're
1660 tracking to "unknown". But we'll be optimistic, assume
1661 that we have enough information already, and stop
1667 int src_indirect = 0;
1668 int dest_indirect = 0;
1671 gdb_assert (mach == bfd_mach_m32c);
1673 /* Check for prefix bytes indicating indirect addressing. */
1674 if (st.insn[0] == 0x41)
1679 else if (st.insn[0] == 0x09)
1684 else if (st.insn[0] == 0x49)
1686 src_indirect = dest_indirect = 1;
1690 /* (1) ENTER #imm8 */
1691 if (st.insn[i] == 0xec)
1693 if (m32c_pv_enter (&st, st.insn[i + 1]))
1699 else if (st.insn[i] == 0x8f)
1701 int src = st.insn[i + 1];
1702 if (m32c_pv_pushm (&st, src))
1706 if (m32c_pushm_is_reg_save (&st, src))
1707 after_last_frame_related_insn = st.next_addr;
1710 /* (7) MOV.size:G src, dest */
1711 else if ((st.insn[i] & 0x80) == 0x80
1712 && (st.insn[i + 1] & 0x0f) == 0x0b
1713 && m32c_get_src23 (&st.insn[i]) < 20
1714 && m32c_get_dest23 (&st.insn[i]) < 20)
1717 struct srcdest dest;
1719 int bw = st.insn[i] & 0x01;
1720 int size = bw ? 2 : 1;
1724 = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]),
1725 size, src_indirect);
1727 = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]),
1728 size, dest_indirect);
1729 src_value = m32c_srcdest_fetch (&st, src, size);
1731 if (m32c_is_arg_spill (&st, dest, src_value))
1732 after_last_frame_related_insn = st.next_addr;
1734 if (m32c_srcdest_store (&st, dest, src_value, size))
1737 /* (2) LDC #IMM24, sp */
1738 else if (st.insn[i] == 0xd5
1739 && st.insn[i + 1] == 0x29)
1742 st.sp = pv_constant (m32c_udisp24 (&st));
1745 /* We've hit some instruction we don't know how to simulate.
1746 Strictly speaking, we should set every value we're
1747 tracking to "unknown". But we'll be optimistic, assume
1748 that we have enough information already, and stop
1753 /* If this instruction changed the FB or decreased the SP (i.e.,
1754 allocated more stack space), then this may be a good place to
1755 declare the prologue finished. However, there are some
1758 - If the instruction just changed the FB back to its original
1759 value, then that's probably a restore instruction. The
1760 prologue should definitely end before that.
1762 - If the instruction increased the value of the SP (that is,
1763 shrunk the frame), then it's probably part of a frame
1764 teardown sequence, and the prologue should end before
1767 if (! pv_is_identical (st.fb, pre_insn_fb))
1769 if (! pv_is_register_k (st.fb, tdep->fb->num, 0))
1770 after_last_frame_related_insn = st.next_addr;
1772 else if (! pv_is_identical (st.sp, pre_insn_sp))
1774 /* The comparison of the constants looks odd, there, because
1775 .k is unsigned. All it really means is that the SP is
1776 lower than it was before the instruction. */
1777 if ( pv_is_register (pre_insn_sp, tdep->sp->num)
1778 && pv_is_register (st.sp, tdep->sp->num)
1779 && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k)))
1780 after_last_frame_related_insn = st.next_addr;
1783 st.scan_pc = st.next_addr;
1786 /* Did we load a constant value into the stack pointer? */
1787 if (pv_is_constant (st.sp))
1788 prologue->kind = prologue_first_frame;
1790 /* Alternatively, did we initialize the frame pointer? Remember
1791 that the CFA is the address after the return address. */
1792 if (pv_is_register (st.fb, tdep->sp->num))
1794 prologue->kind = prologue_with_frame_ptr;
1795 prologue->frame_ptr_offset = st.fb.k;
1798 /* Is the frame size a known constant? Remember that frame_size is
1799 actually the offset from the CFA to the SP (i.e., a negative
1801 else if (pv_is_register (st.sp, tdep->sp->num))
1803 prologue->kind = prologue_sans_frame_ptr;
1804 prologue->frame_size = st.sp.k;
1807 /* We haven't been able to make sense of this function's frame. Treat
1808 it as the first frame. */
1810 prologue->kind = prologue_first_frame;
1812 /* Record where all the registers were saved. */
1813 st.stack->scan (check_for_saved, (void *) prologue);
1815 prologue->prologue_end = after_last_frame_related_insn;
1820 m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip)
1823 CORE_ADDR func_addr, func_end, sal_end;
1824 struct m32c_prologue p;
1826 /* Try to find the extent of the function that contains IP. */
1827 if (! find_pc_partial_function (ip, &name, &func_addr, &func_end))
1830 /* Find end by prologue analysis. */
1831 m32c_analyze_prologue (gdbarch, ip, func_end, &p);
1832 /* Find end by line info. */
1833 sal_end = skip_prologue_using_sal (gdbarch, ip);
1834 /* Return whichever is lower. */
1835 if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end)
1838 return p.prologue_end;
1843 /* Stack unwinding. */
1845 static struct m32c_prologue *
1846 m32c_analyze_frame_prologue (struct frame_info *this_frame,
1847 void **this_prologue_cache)
1849 if (! *this_prologue_cache)
1851 CORE_ADDR func_start = get_frame_func (this_frame);
1852 CORE_ADDR stop_addr = get_frame_pc (this_frame);
1854 /* If we couldn't find any function containing the PC, then
1855 just initialize the prologue cache, but don't do anything. */
1857 stop_addr = func_start;
1859 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue);
1860 m32c_analyze_prologue (get_frame_arch (this_frame),
1861 func_start, stop_addr,
1862 (struct m32c_prologue *) *this_prologue_cache);
1865 return (struct m32c_prologue *) *this_prologue_cache;
1870 m32c_frame_base (struct frame_info *this_frame,
1871 void **this_prologue_cache)
1873 struct m32c_prologue *p
1874 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache);
1875 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1877 /* In functions that use alloca, the distance between the stack
1878 pointer and the frame base varies dynamically, so we can't use
1879 the SP plus static information like prologue analysis to find the
1880 frame base. However, such functions must have a frame pointer,
1881 to be able to restore the SP on exit. So whenever we do have a
1882 frame pointer, use that to find the base. */
1885 case prologue_with_frame_ptr:
1888 = get_frame_register_unsigned (this_frame, tdep->fb->num);
1889 return fb - p->frame_ptr_offset;
1892 case prologue_sans_frame_ptr:
1895 = get_frame_register_unsigned (this_frame, tdep->sp->num);
1896 return sp - p->frame_size;
1899 case prologue_first_frame:
1903 gdb_assert_not_reached ("unexpected prologue kind");
1909 m32c_this_id (struct frame_info *this_frame,
1910 void **this_prologue_cache,
1911 struct frame_id *this_id)
1913 CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache);
1916 *this_id = frame_id_build (base, get_frame_func (this_frame));
1917 /* Otherwise, leave it unset, and that will terminate the backtrace. */
1921 static struct value *
1922 m32c_prev_register (struct frame_info *this_frame,
1923 void **this_prologue_cache, int regnum)
1925 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1926 struct m32c_prologue *p
1927 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache);
1928 CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache);
1930 if (regnum == tdep->sp->num)
1931 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1933 /* If prologue analysis says we saved this register somewhere,
1934 return a description of the stack slot holding it. */
1935 if (p->reg_offset[regnum] != 1)
1936 return frame_unwind_got_memory (this_frame, regnum,
1937 frame_base + p->reg_offset[regnum]);
1939 /* Otherwise, presume we haven't changed the value of this
1940 register, and get it from the next frame. */
1941 return frame_unwind_got_register (this_frame, regnum, regnum);
1945 static const struct frame_unwind m32c_unwind = {
1947 default_frame_unwind_stop_reason,
1951 default_frame_sniffer
1956 m32c_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1958 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1959 return frame_unwind_register_unsigned (next_frame, tdep->pc->num);
1964 m32c_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1966 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1967 return frame_unwind_register_unsigned (next_frame, tdep->sp->num);
1971 /* Inferior calls. */
1973 /* The calling conventions, according to GCC:
1977 First arg may be passed in r1l or r1 if it (1) fits (QImode or
1978 HImode), (2) is named, and (3) is an integer or pointer type (no
1979 structs, floats, etc). Otherwise, it's passed on the stack.
1981 Second arg may be passed in r2, same restrictions (but not QImode),
1982 even if the first arg is passed on the stack.
1984 Third and further args are passed on the stack. No padding is
1985 used, stack "alignment" is 8 bits.
1990 First arg may be passed in r0l or r0, same restrictions as above.
1992 Second and further args are passed on the stack. Padding is used
1993 after QImode parameters (i.e. lower-addressed byte is the value,
1994 higher-addressed byte is the padding), stack "alignment" is 16
1998 /* Return true if TYPE is a type that can be passed in registers. (We
1999 ignore the size, and pay attention only to the type code;
2000 acceptable sizes depends on which register is being considered to
2003 m32c_reg_arg_type (struct type *type)
2005 enum type_code code = TYPE_CODE (type);
2007 return (code == TYPE_CODE_INT
2008 || code == TYPE_CODE_ENUM
2009 || code == TYPE_CODE_PTR
2010 || TYPE_IS_REFERENCE (type)
2011 || code == TYPE_CODE_BOOL
2012 || code == TYPE_CODE_CHAR);
2017 m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2018 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2019 struct value **args, CORE_ADDR sp, int struct_return,
2020 CORE_ADDR struct_addr)
2022 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2023 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2024 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
2028 /* The number of arguments given in this function's prototype, or
2029 zero if it has a non-prototyped function type. The m32c ABI
2030 passes arguments mentioned in the prototype differently from
2031 those in the ellipsis of a varargs function, or from those passed
2032 to a non-prototyped function. */
2033 int num_prototyped_args = 0;
2036 struct type *func_type = value_type (function);
2038 /* Dereference function pointer types. */
2039 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
2040 func_type = TYPE_TARGET_TYPE (func_type);
2042 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC ||
2043 TYPE_CODE (func_type) == TYPE_CODE_METHOD);
2046 /* The ABI description in gcc/config/m32c/m32c.abi says that
2047 we need to handle prototyped and non-prototyped functions
2048 separately, but the code in GCC doesn't actually do so. */
2049 if (TYPE_PROTOTYPED (func_type))
2051 num_prototyped_args = TYPE_NFIELDS (func_type);
2054 /* First, if the function returns an aggregate by value, push a
2055 pointer to a buffer for it. This doesn't affect the way
2056 subsequent arguments are allocated to registers. */
2059 int ptr_len = TYPE_LENGTH (tdep->ptr_voyd);
2061 write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr);
2064 /* Push the arguments. */
2065 for (i = nargs - 1; i >= 0; i--)
2067 struct value *arg = args[i];
2068 const gdb_byte *arg_bits = value_contents (arg);
2069 struct type *arg_type = value_type (arg);
2070 ULONGEST arg_size = TYPE_LENGTH (arg_type);
2072 /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */
2075 && i < num_prototyped_args
2076 && m32c_reg_arg_type (arg_type))
2078 /* Extract and re-store as an integer as a terse way to make
2079 sure it ends up in the least significant end of r1. (GDB
2080 should avoid assuming endianness, even on uni-endian
2082 ULONGEST u = extract_unsigned_integer (arg_bits, arg_size,
2084 struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0;
2085 regcache_cooked_write_unsigned (regcache, reg->num, u);
2088 /* Can it go in r2? */
2089 else if (mach == bfd_mach_m16c
2092 && i < num_prototyped_args
2093 && m32c_reg_arg_type (arg_type))
2094 regcache->cooked_write (tdep->r2->num, arg_bits);
2096 /* Everything else goes on the stack. */
2101 /* Align the stack. */
2102 if (mach == bfd_mach_m32c)
2105 write_memory (sp, arg_bits, arg_size);
2109 /* This is the CFA we use to identify the dummy frame. */
2112 /* Push the return address. */
2113 sp -= tdep->ret_addr_bytes;
2114 write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order,
2117 /* Update the stack pointer. */
2118 regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp);
2120 /* We need to borrow an odd trick from the i386 target here.
2122 The value we return from this function gets used as the stack
2123 address (the CFA) for the dummy frame's ID. The obvious thing is
2124 to return the new TOS. However, that points at the return
2125 address, saved on the stack, which is inconsistent with the CFA's
2126 described by GCC's DWARF 2 .debug_frame information: DWARF 2
2127 .debug_frame info uses the address immediately after the saved
2128 return address. So you end up with a dummy frame whose CFA
2129 points at the return address, but the frame for the function
2130 being called has a CFA pointing after the return address: the
2131 younger CFA is *greater than* the older CFA. The sanity checks
2132 in frame.c don't like that.
2134 So we try to be consistent with the CFA's used by DWARF 2.
2135 Having a dummy frame and a real frame with the *same* CFA is
2141 static struct frame_id
2142 m32c_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2144 /* This needs to return a frame ID whose PC is the return address
2145 passed to m32c_push_dummy_call, and whose stack_addr is the SP
2146 m32c_push_dummy_call returned.
2148 m32c_unwind_sp gives us the CFA, which is the value the SP had
2149 before the return address was pushed. */
2150 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2151 CORE_ADDR sp = get_frame_register_unsigned (this_frame, tdep->sp->num);
2152 return frame_id_build (sp, get_frame_pc (this_frame));
2157 /* Return values. */
2159 /* Return value conventions, according to GCC:
2170 Aggregate values (regardless of size) are returned by pushing a
2171 pointer to a temporary area on the stack after the args are pushed.
2172 The function fills in this area with the value. Note that this
2173 pointer on the stack does not affect how register arguments, if any,
2180 /* Return non-zero if values of type TYPE are returned by storing them
2181 in a buffer whose address is passed on the stack, ahead of the
2184 m32c_return_by_passed_buf (struct type *type)
2186 enum type_code code = TYPE_CODE (type);
2188 return (code == TYPE_CODE_STRUCT
2189 || code == TYPE_CODE_UNION);
2192 static enum return_value_convention
2193 m32c_return_value (struct gdbarch *gdbarch,
2194 struct value *function,
2195 struct type *valtype,
2196 struct regcache *regcache,
2198 const gdb_byte *writebuf)
2200 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2201 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2202 enum return_value_convention conv;
2203 ULONGEST valtype_len = TYPE_LENGTH (valtype);
2205 if (m32c_return_by_passed_buf (valtype))
2206 conv = RETURN_VALUE_STRUCT_CONVENTION;
2208 conv = RETURN_VALUE_REGISTER_CONVENTION;
2212 /* We should never be called to find values being returned by
2213 RETURN_VALUE_STRUCT_CONVENTION. Those can't be located,
2214 unless we made the call ourselves. */
2215 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2217 gdb_assert (valtype_len <= 8);
2219 /* Anything that fits in r0 is returned there. */
2220 if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2223 regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u);
2224 store_unsigned_integer (readbuf, valtype_len, byte_order, u);
2228 /* Everything else is passed in mem0, using as many bytes as
2229 needed. This is not what the Renesas tools do, but it's
2230 what GCC does at the moment. */
2231 struct bound_minimal_symbol mem0
2232 = lookup_minimal_symbol ("mem0", NULL, NULL);
2235 error (_("The return value is stored in memory at 'mem0', "
2236 "but GDB cannot find\n"
2238 read_memory (BMSYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len);
2244 /* We should never be called to store values to be returned
2245 using RETURN_VALUE_STRUCT_CONVENTION. We have no way of
2246 finding the buffer, unless we made the call ourselves. */
2247 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2249 gdb_assert (valtype_len <= 8);
2251 /* Anything that fits in r0 is returned there. */
2252 if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2254 ULONGEST u = extract_unsigned_integer (writebuf, valtype_len,
2256 regcache_cooked_write_unsigned (regcache, tdep->r0->num, u);
2260 /* Everything else is passed in mem0, using as many bytes as
2261 needed. This is not what the Renesas tools do, but it's
2262 what GCC does at the moment. */
2263 struct bound_minimal_symbol mem0
2264 = lookup_minimal_symbol ("mem0", NULL, NULL);
2267 error (_("The return value is stored in memory at 'mem0', "
2268 "but GDB cannot find\n"
2270 write_memory (BMSYMBOL_VALUE_ADDRESS (mem0), writebuf, valtype_len);
2281 /* The m16c and m32c use a trampoline function for indirect function
2282 calls. An indirect call looks like this:
2284 ... push arguments ...
2285 ... push target function address ...
2288 The code for m32c_jsri16 looks like this:
2292 # Save return address.
2294 pop.b m32c_jsri_ret+2
2296 # Store target function address.
2297 pop.w m32c_jsri_addr
2299 # Re-push return address.
2300 push.b m32c_jsri_ret+2
2301 push.w m32c_jsri_ret
2303 # Call the target function.
2304 jmpi.a m32c_jsri_addr
2306 Without further information, GDB will treat calls to m32c_jsri16
2307 like calls to any other function. Since m32c_jsri16 doesn't have
2308 debugging information, that normally means that GDB sets a step-
2309 resume breakpoint and lets the program continue --- which is not
2310 what the user wanted. (Giving the trampoline debugging info
2311 doesn't help: the user expects the program to stop in the function
2312 their program is calling, not in some trampoline code they've never
2315 The gdbarch_skip_trampoline_code method tells GDB how to step
2316 through such trampoline functions transparently to the user. When
2317 given the address of a trampoline function's first instruction,
2318 gdbarch_skip_trampoline_code should return the address of the first
2319 instruction of the function really being called. If GDB decides it
2320 wants to step into that function, it will set a breakpoint there
2321 and silently continue to it.
2323 We recognize the trampoline by name, and extract the target address
2324 directly from the stack. This isn't great, but recognizing by its
2325 code sequence seems more fragile. */
2328 m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc)
2330 struct gdbarch *gdbarch = get_frame_arch (frame);
2331 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2332 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2334 /* It would be nicer to simply look up the addresses of known
2335 trampolines once, and then compare stop_pc with them. However,
2336 we'd need to ensure that that cached address got invalidated when
2337 someone loaded a new executable, and I'm not quite sure of the
2338 best way to do that. find_pc_partial_function does do some
2339 caching, so we'll see how this goes. */
2341 CORE_ADDR start, end;
2343 if (find_pc_partial_function (stop_pc, &name, &start, &end))
2345 /* Are we stopped at the beginning of the trampoline function? */
2346 if (strcmp (name, "m32c_jsri16") == 0
2347 && stop_pc == start)
2349 /* Get the stack pointer. The return address is at the top,
2350 and the target function's address is just below that. We
2351 know it's a two-byte address, since the trampoline is
2353 CORE_ADDR sp = get_frame_sp (get_current_frame ());
2355 = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes,
2358 /* What we have now is the address of a jump instruction.
2359 What we need is the destination of that jump.
2360 The opcode is 1 byte, and the destination is the next 3 bytes. */
2362 target = read_memory_unsigned_integer (target + 1, 3, byte_order);
2371 /* Address/pointer conversions. */
2373 /* On the m16c, there is a 24-bit address space, but only a very few
2374 instructions can generate addresses larger than 0xffff: jumps,
2375 jumps to subroutines, and the lde/std (load/store extended)
2378 Since GCC can only support one size of pointer, we can't have
2379 distinct 'near' and 'far' pointer types; we have to pick one size
2380 for everything. If we wanted to use 24-bit pointers, then GCC
2381 would have to use lde and ste for all memory references, which
2382 would be terrible for performance and code size. So the GNU
2383 toolchain uses 16-bit pointers for everything, and gives up the
2384 ability to have pointers point outside the first 64k of memory.
2386 However, as a special hack, we let the linker place functions at
2387 addresses above 0xffff, as long as it also places a trampoline in
2388 the low 64k for every function whose address is taken. Each
2389 trampoline consists of a single jmp.a instruction that jumps to the
2390 function's real entry point. Pointers to functions can be 16 bits
2391 long, even though the functions themselves are at higher addresses:
2392 the pointers refer to the trampolines, not the functions.
2394 This complicates things for GDB, however: given the address of a
2395 function (from debug info or linker symbols, say) which could be
2396 anywhere in the 24-bit address space, how can we find an
2397 appropriate 16-bit value to use as a pointer to it?
2399 If the linker has not generated a trampoline for the function,
2400 we're out of luck. Well, I guess we could malloc some space and
2401 write a jmp.a instruction to it, but I'm not going to get into that
2404 If the linker has generated a trampoline for the function, then it
2405 also emitted a symbol for the trampoline: if the function's linker
2406 symbol is named NAME, then the function's trampoline's linker
2407 symbol is named NAME.plt.
2409 So, given a code address:
2410 - We try to find a linker symbol at that address.
2411 - If we find such a symbol named NAME, we look for a linker symbol
2413 - If we find such a symbol, we assume it is a trampoline, and use
2414 its address as the pointer value.
2416 And, given a function pointer:
2417 - We try to find a linker symbol at that address named NAME.plt.
2418 - If we find such a symbol, we look for a linker symbol named NAME.
2419 - If we find that, we provide that as the function's address.
2420 - If any of the above steps fail, we return the original address
2421 unchanged; it might really be a function in the low 64k.
2423 See? You *knew* there was a reason you wanted to be a computer
2427 m32c_m16c_address_to_pointer (struct gdbarch *gdbarch,
2428 struct type *type, gdb_byte *buf, CORE_ADDR addr)
2430 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2431 enum type_code target_code;
2432 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type));
2434 target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2436 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2438 const char *func_name;
2440 struct bound_minimal_symbol tramp_msym;
2442 /* Try to find a linker symbol at this address. */
2443 struct bound_minimal_symbol func_msym
2444 = lookup_minimal_symbol_by_pc (addr);
2446 if (! func_msym.minsym)
2447 error (_("Cannot convert code address %s to function pointer:\n"
2448 "couldn't find a symbol at that address, to find trampoline."),
2449 paddress (gdbarch, addr));
2451 func_name = MSYMBOL_LINKAGE_NAME (func_msym.minsym);
2452 tramp_name = (char *) xmalloc (strlen (func_name) + 5);
2453 strcpy (tramp_name, func_name);
2454 strcat (tramp_name, ".plt");
2456 /* Try to find a linker symbol for the trampoline. */
2457 tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL);
2459 /* We've either got another copy of the name now, or don't need
2460 the name any more. */
2463 if (! tramp_msym.minsym)
2467 /* No PLT entry found. Mask off the upper bits of the address
2468 to make a pointer. As noted in the warning to the user
2469 below, this value might be useful if converted back into
2470 an address by GDB, but will otherwise, almost certainly,
2473 Using this masked result does seem to be useful
2474 in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into
2475 PASSes. These results appear to be correct as well.
2477 We print a warning here so that the user can make a
2478 determination about whether the result is useful or not. */
2479 ptrval = addr & 0xffff;
2481 warning (_("Cannot convert code address %s to function pointer:\n"
2482 "couldn't find trampoline named '%s.plt'.\n"
2483 "Returning pointer value %s instead; this may produce\n"
2484 "a useful result if converted back into an address by GDB,\n"
2485 "but will most likely not be useful otherwise.\n"),
2486 paddress (gdbarch, addr), func_name,
2487 paddress (gdbarch, ptrval));
2494 /* The trampoline's address is our pointer. */
2495 addr = BMSYMBOL_VALUE_ADDRESS (tramp_msym);
2499 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, addr);
2504 m32c_m16c_pointer_to_address (struct gdbarch *gdbarch,
2505 struct type *type, const gdb_byte *buf)
2507 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2509 enum type_code target_code;
2511 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type));
2513 ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
2515 target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2517 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2519 /* See if there is a minimal symbol at that address whose name is
2521 struct bound_minimal_symbol ptr_msym = lookup_minimal_symbol_by_pc (ptr);
2523 if (ptr_msym.minsym)
2525 const char *ptr_msym_name = MSYMBOL_LINKAGE_NAME (ptr_msym.minsym);
2526 int len = strlen (ptr_msym_name);
2529 && strcmp (ptr_msym_name + len - 4, ".plt") == 0)
2531 struct bound_minimal_symbol func_msym;
2532 /* We have a .plt symbol; try to find the symbol for the
2533 corresponding function.
2535 Since the trampoline contains a jump instruction, we
2536 could also just extract the jump's target address. I
2537 don't see much advantage one way or the other. */
2538 char *func_name = (char *) xmalloc (len - 4 + 1);
2539 memcpy (func_name, ptr_msym_name, len - 4);
2540 func_name[len - 4] = '\0';
2542 = lookup_minimal_symbol (func_name, NULL, NULL);
2544 /* If we do have such a symbol, return its value as the
2545 function's true address. */
2546 if (func_msym.minsym)
2547 ptr = BMSYMBOL_VALUE_ADDRESS (func_msym);
2554 for (aspace = 1; aspace <= 15; aspace++)
2556 ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr);
2558 if (ptr_msym.minsym)
2559 ptr |= aspace << 16;
2568 m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
2570 LONGEST *frame_offset)
2573 CORE_ADDR func_addr, func_end;
2574 struct m32c_prologue p;
2576 struct regcache *regcache = get_current_regcache ();
2577 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2579 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
2580 internal_error (__FILE__, __LINE__,
2581 _("No virtual frame pointer available"));
2583 m32c_analyze_prologue (gdbarch, func_addr, pc, &p);
2586 case prologue_with_frame_ptr:
2587 *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num;
2588 *frame_offset = p.frame_ptr_offset;
2590 case prologue_sans_frame_ptr:
2591 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num;
2592 *frame_offset = p.frame_size;
2595 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num;
2600 if (*frame_regnum > gdbarch_num_regs (gdbarch))
2601 internal_error (__FILE__, __LINE__,
2602 _("No virtual frame pointer available"));
2606 /* Initialization. */
2608 static struct gdbarch *
2609 m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2611 struct gdbarch *gdbarch;
2612 struct gdbarch_tdep *tdep;
2613 unsigned long mach = info.bfd_arch_info->mach;
2615 /* Find a candidate among the list of architectures we've created
2617 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2619 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2620 return arches->gdbarch;
2622 tdep = XCNEW (struct gdbarch_tdep);
2623 gdbarch = gdbarch_alloc (&info, tdep);
2625 /* Essential types. */
2626 make_types (gdbarch);
2628 /* Address/pointer conversions. */
2629 if (mach == bfd_mach_m16c)
2631 set_gdbarch_address_to_pointer (gdbarch, m32c_m16c_address_to_pointer);
2632 set_gdbarch_pointer_to_address (gdbarch, m32c_m16c_pointer_to_address);
2636 make_regs (gdbarch);
2639 set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32c_breakpoint::kind_from_pc);
2640 set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32c_breakpoint::bp_from_kind);
2642 /* Prologue analysis and unwinding. */
2643 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2644 set_gdbarch_skip_prologue (gdbarch, m32c_skip_prologue);
2645 set_gdbarch_unwind_pc (gdbarch, m32c_unwind_pc);
2646 set_gdbarch_unwind_sp (gdbarch, m32c_unwind_sp);
2648 /* I'm dropping the dwarf2 sniffer because it has a few problems.
2649 They may be in the dwarf2 cfi code in GDB, or they may be in
2650 the debug info emitted by the upstream toolchain. I don't
2651 know which, but I do know that the prologue analyzer works better.
2653 dwarf2_append_sniffers (gdbarch);
2655 frame_unwind_append_unwinder (gdbarch, &m32c_unwind);
2657 /* Inferior calls. */
2658 set_gdbarch_push_dummy_call (gdbarch, m32c_push_dummy_call);
2659 set_gdbarch_return_value (gdbarch, m32c_return_value);
2660 set_gdbarch_dummy_id (gdbarch, m32c_dummy_id);
2663 set_gdbarch_skip_trampoline_code (gdbarch, m32c_skip_trampoline_code);
2665 set_gdbarch_virtual_frame_pointer (gdbarch, m32c_virtual_frame_pointer);
2667 /* m32c function boundary addresses are not necessarily even.
2668 Therefore, the `vbit', which indicates a pointer to a virtual
2669 member function, is stored in the delta field, rather than as
2670 the low bit of a function pointer address.
2672 In order to verify this, see the definition of
2673 TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the
2674 definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */
2675 set_gdbarch_vbit_in_delta (gdbarch, 1);
2681 _initialize_m32c_tdep (void)
2683 register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init);
2685 m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP);