1 /* Renesas M32C target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 2004-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb/sim-m32c.h"
27 #include "arch-utils.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
31 #include "dwarf2expr.h"
35 #include "reggroups.h"
36 #include "prologue-value.h"
41 /* The m32c tdep structure. */
43 static struct reggroup *m32c_dma_reggroup;
47 /* The type of a function that moves the value of REG between CACHE or
48 BUF --- in either direction. */
49 typedef enum register_status (m32c_write_reg_t) (struct m32c_reg *reg,
50 struct regcache *cache,
53 typedef enum register_status (m32c_read_reg_t) (struct m32c_reg *reg,
54 struct regcache *cache,
59 /* The name of this register. */
65 /* The architecture this register belongs to. */
68 /* Its GDB register number. */
71 /* Its sim register number. */
74 /* Its DWARF register number, or -1 if it doesn't have one. */
77 /* Register group memberships. */
78 unsigned int general_p : 1;
79 unsigned int dma_p : 1;
80 unsigned int system_p : 1;
81 unsigned int save_restore_p : 1;
83 /* Functions to read its value from a regcache, and write its value
85 m32c_read_reg_t *read;
86 m32c_write_reg_t *write;
88 /* Data for READ and WRITE functions. The exact meaning depends on
89 the specific functions selected; see the comments for those
91 struct m32c_reg *rx, *ry;
96 /* An overestimate of the number of raw and pseudoregisters we will
97 have. The exact answer depends on the variant of the architecture
98 at hand, but we can use this to declare statically allocated
99 arrays, and bump it up when needed. */
100 #define M32C_MAX_NUM_REGS (75)
102 /* The largest assigned DWARF register number. */
103 #define M32C_MAX_DWARF_REGNUM (40)
108 /* All the registers for this variant, indexed by GDB register
109 number, and the number of registers present. */
110 struct m32c_reg regs[M32C_MAX_NUM_REGS];
112 /* The number of valid registers. */
115 /* Interesting registers. These are pointers into REGS. */
116 struct m32c_reg *pc, *flg;
117 struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1;
118 struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0;
119 struct m32c_reg *sb, *fb, *sp;
121 /* A table indexed by DWARF register numbers, pointing into
123 struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1];
125 /* Types for this architecture. We can't use the builtin_type_foo
126 types, because they're not initialized when building a gdbarch
128 struct type *voyd, *ptr_voyd, *func_voyd;
129 struct type *uint8, *uint16;
130 struct type *int8, *int16, *int32, *int64;
132 /* The types for data address and code address registers. */
133 struct type *data_addr_reg_type, *code_addr_reg_type;
135 /* The number of bytes a return address pushed by a 'jsr' instruction
136 occupies on the stack. */
139 /* The number of bytes an address register occupies on the stack
140 when saved by an 'enter' or 'pushm' instruction. */
148 make_types (struct gdbarch *arch)
150 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
151 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
152 int data_addr_reg_bits, code_addr_reg_bits;
156 /* This is used to clip CORE_ADDR values, so this value is
157 appropriate both on the m32c, where pointers are 32 bits long,
158 and on the m16c, where pointers are sixteen bits long, but there
159 may be code above the 64k boundary. */
160 set_gdbarch_addr_bit (arch, 24);
162 /* GCC uses 32 bits for addrs in the dwarf info, even though
163 only 16/24 bits are used. Setting addr_bit to 24 causes
164 errors in reading the dwarf addresses. */
165 set_gdbarch_addr_bit (arch, 32);
168 set_gdbarch_int_bit (arch, 16);
172 data_addr_reg_bits = 16;
173 code_addr_reg_bits = 24;
174 set_gdbarch_ptr_bit (arch, 16);
175 tdep->ret_addr_bytes = 3;
176 tdep->push_addr_bytes = 2;
180 data_addr_reg_bits = 24;
181 code_addr_reg_bits = 24;
182 set_gdbarch_ptr_bit (arch, 32);
183 tdep->ret_addr_bytes = 4;
184 tdep->push_addr_bytes = 4;
188 gdb_assert_not_reached ("unexpected mach");
191 /* The builtin_type_mumble variables are sometimes uninitialized when
192 this is called, so we avoid using them. */
193 tdep->voyd = arch_type (arch, TYPE_CODE_VOID, TARGET_CHAR_BIT, "void");
195 = arch_pointer_type (arch, gdbarch_ptr_bit (arch), NULL, tdep->voyd);
196 tdep->func_voyd = lookup_function_type (tdep->voyd);
198 xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t",
199 gdbarch_bfd_arch_info (arch)->printable_name);
200 tdep->data_addr_reg_type
201 = arch_pointer_type (arch, data_addr_reg_bits, type_name, tdep->voyd);
203 xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t",
204 gdbarch_bfd_arch_info (arch)->printable_name);
205 tdep->code_addr_reg_type
206 = arch_pointer_type (arch, code_addr_reg_bits, type_name, tdep->func_voyd);
208 tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t");
209 tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t");
210 tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t");
211 tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t");
212 tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t");
213 tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t");
221 m32c_register_name (struct gdbarch *gdbarch, int num)
223 return gdbarch_tdep (gdbarch)->regs[num].name;
228 m32c_register_type (struct gdbarch *arch, int reg_nr)
230 return gdbarch_tdep (arch)->regs[reg_nr].type;
235 m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr)
237 return gdbarch_tdep (gdbarch)->regs[reg_nr].sim_num;
242 m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr)
244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
245 if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM
246 && tdep->dwarf_regs[reg_nr])
247 return tdep->dwarf_regs[reg_nr]->num;
249 /* The DWARF CFI code expects to see -1 for invalid register
256 m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
257 struct reggroup *group)
259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
260 struct m32c_reg *reg = &tdep->regs[regnum];
262 /* The anonymous raw registers aren't in any groups. */
266 if (group == all_reggroup)
269 if (group == general_reggroup
273 if (group == m32c_dma_reggroup
277 if (group == system_reggroup
281 /* Since the m32c DWARF register numbers refer to cooked registers, not
282 raw registers, and frame_pop depends on the save and restore groups
283 containing registers the DWARF CFI will actually mention, our save
284 and restore groups are cooked registers, not raw registers. (This is
285 why we can't use the default reggroup function.) */
286 if ((group == save_reggroup
287 || group == restore_reggroup)
288 && reg->save_restore_p)
295 /* Register move functions. We declare them here using
296 m32c_{read,write}_reg_t to check the types. */
297 static m32c_read_reg_t m32c_raw_read;
298 static m32c_read_reg_t m32c_banked_read;
299 static m32c_read_reg_t m32c_sb_read;
300 static m32c_read_reg_t m32c_part_read;
301 static m32c_read_reg_t m32c_cat_read;
302 static m32c_read_reg_t m32c_r3r2r1r0_read;
304 static m32c_write_reg_t m32c_raw_write;
305 static m32c_write_reg_t m32c_banked_write;
306 static m32c_write_reg_t m32c_sb_write;
307 static m32c_write_reg_t m32c_part_write;
308 static m32c_write_reg_t m32c_cat_write;
309 static m32c_write_reg_t m32c_r3r2r1r0_write;
311 /* Copy the value of the raw register REG from CACHE to BUF. */
312 static enum register_status
313 m32c_raw_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
315 return cache->raw_read (reg->num, buf);
319 /* Copy the value of the raw register REG from BUF to CACHE. */
320 static enum register_status
321 m32c_raw_write (struct m32c_reg *reg, struct regcache *cache,
324 regcache_raw_write (cache, reg->num, buf);
330 /* Return the value of the 'flg' register in CACHE. */
332 m32c_read_flg (struct regcache *cache)
334 struct gdbarch_tdep *tdep = gdbarch_tdep (cache->arch ());
337 cache->raw_read (tdep->flg->num, &flg);
342 /* Evaluate the real register number of a banked register. */
343 static struct m32c_reg *
344 m32c_banked_register (struct m32c_reg *reg, struct regcache *cache)
346 return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx);
350 /* Move the value of a banked register from CACHE to BUF.
351 If the value of the 'flg' register in CACHE has any of the bits
352 masked in REG->n set, then read REG->ry. Otherwise, read
354 static enum register_status
355 m32c_banked_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
357 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
358 return cache->raw_read (bank_reg->num, buf);
362 /* Move the value of a banked register from BUF to CACHE.
363 If the value of the 'flg' register in CACHE has any of the bits
364 masked in REG->n set, then write REG->ry. Otherwise, write
366 static enum register_status
367 m32c_banked_write (struct m32c_reg *reg, struct regcache *cache,
370 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
371 regcache_raw_write (cache, bank_reg->num, buf);
377 /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a
378 banked register; on bfd_mach_m16c, it's not. */
379 static enum register_status
380 m32c_sb_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
382 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
383 return m32c_raw_read (reg->rx, cache, buf);
385 return m32c_banked_read (reg, cache, buf);
389 /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a
390 banked register; on bfd_mach_m16c, it's not. */
391 static enum register_status
392 m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, const gdb_byte *buf)
394 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
395 m32c_raw_write (reg->rx, cache, buf);
397 m32c_banked_write (reg, cache, buf);
403 /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P
404 and *LEN_P to the offset and length, in bytes, of the part REG
405 occupies in its underlying register. The offset is from the
406 lower-addressed end, regardless of the architecture's endianness.
407 (The M32C family is always little-endian, but let's keep those
408 assumptions out of here.) */
410 m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p)
412 /* The length of the containing register, of which REG is one part. */
413 int containing_len = TYPE_LENGTH (reg->rx->type);
415 /* The length of one "element" in our imaginary array. */
416 int elt_len = TYPE_LENGTH (reg->type);
418 /* The offset of REG's "element" from the least significant end of
419 the containing register. */
420 int elt_offset = reg->n * elt_len;
422 /* If we extend off the end, trim the length of the element. */
423 if (elt_offset + elt_len > containing_len)
425 elt_len = containing_len - elt_offset;
426 /* We shouldn't be declaring partial registers that go off the
427 end of their containing registers. */
428 gdb_assert (elt_len > 0);
431 /* Flip the offset around if we're big-endian. */
432 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
433 elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len;
435 *offset_p = elt_offset;
440 /* Move the value of a partial register (r0h, intbl, etc.) from CACHE
441 to BUF. Treating the value of the register REG->rx as an array of
442 REG->type values, where higher indices refer to more significant
443 bits, read the value of the REG->n'th element. */
444 static enum register_status
445 m32c_part_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
449 memset (buf, 0, TYPE_LENGTH (reg->type));
450 m32c_find_part (reg, &offset, &len);
451 return cache->cooked_read_part (reg->rx->num, offset, len, buf);
455 /* Move the value of a banked register from BUF to CACHE.
456 Treating the value of the register REG->rx as an array of REG->type
457 values, where higher indices refer to more significant bits, write
458 the value of the REG->n'th element. */
459 static enum register_status
460 m32c_part_write (struct m32c_reg *reg, struct regcache *cache,
465 m32c_find_part (reg, &offset, &len);
466 regcache_cooked_write_part (cache, reg->rx->num, offset, len, buf);
472 /* Move the value of REG from CACHE to BUF. REG's value is the
473 concatenation of the values of the registers REG->rx and REG->ry,
474 with REG->rx contributing the more significant bits. */
475 static enum register_status
476 m32c_cat_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
478 int high_bytes = TYPE_LENGTH (reg->rx->type);
479 int low_bytes = TYPE_LENGTH (reg->ry->type);
480 enum register_status status;
482 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
484 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
486 status = regcache_cooked_read (cache, reg->rx->num, buf);
487 if (status == REG_VALID)
488 status = regcache_cooked_read (cache, reg->ry->num, buf + high_bytes);
492 status = regcache_cooked_read (cache, reg->rx->num, buf + low_bytes);
493 if (status == REG_VALID)
494 status = regcache_cooked_read (cache, reg->ry->num, buf);
501 /* Move the value of REG from CACHE to BUF. REG's value is the
502 concatenation of the values of the registers REG->rx and REG->ry,
503 with REG->rx contributing the more significant bits. */
504 static enum register_status
505 m32c_cat_write (struct m32c_reg *reg, struct regcache *cache,
508 int high_bytes = TYPE_LENGTH (reg->rx->type);
509 int low_bytes = TYPE_LENGTH (reg->ry->type);
511 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
513 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
515 regcache_cooked_write (cache, reg->rx->num, buf);
516 regcache_cooked_write (cache, reg->ry->num, buf + high_bytes);
520 regcache_cooked_write (cache, reg->rx->num, buf + low_bytes);
521 regcache_cooked_write (cache, reg->ry->num, buf);
528 /* Copy the value of the raw register REG from CACHE to BUF. REG is
529 the concatenation (from most significant to least) of r3, r2, r1,
531 static enum register_status
532 m32c_r3r2r1r0_read (struct m32c_reg *reg, struct regcache *cache, gdb_byte *buf)
534 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
535 int len = TYPE_LENGTH (tdep->r0->type);
536 enum register_status status;
538 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
540 status = regcache_cooked_read (cache, tdep->r0->num, buf + len * 3);
541 if (status == REG_VALID)
542 status = regcache_cooked_read (cache, tdep->r1->num, buf + len * 2);
543 if (status == REG_VALID)
544 status = regcache_cooked_read (cache, tdep->r2->num, buf + len * 1);
545 if (status == REG_VALID)
546 status = regcache_cooked_read (cache, tdep->r3->num, buf);
550 status = regcache_cooked_read (cache, tdep->r0->num, buf);
551 if (status == REG_VALID)
552 status = regcache_cooked_read (cache, tdep->r1->num, buf + len * 1);
553 if (status == REG_VALID)
554 status = regcache_cooked_read (cache, tdep->r2->num, buf + len * 2);
555 if (status == REG_VALID)
556 status = regcache_cooked_read (cache, tdep->r3->num, buf + len * 3);
563 /* Copy the value of the raw register REG from BUF to CACHE. REG is
564 the concatenation (from most significant to least) of r3, r2, r1,
566 static enum register_status
567 m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache,
570 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
571 int len = TYPE_LENGTH (tdep->r0->type);
573 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
575 regcache_cooked_write (cache, tdep->r0->num, buf + len * 3);
576 regcache_cooked_write (cache, tdep->r1->num, buf + len * 2);
577 regcache_cooked_write (cache, tdep->r2->num, buf + len * 1);
578 regcache_cooked_write (cache, tdep->r3->num, buf);
582 regcache_cooked_write (cache, tdep->r0->num, buf);
583 regcache_cooked_write (cache, tdep->r1->num, buf + len * 1);
584 regcache_cooked_write (cache, tdep->r2->num, buf + len * 2);
585 regcache_cooked_write (cache, tdep->r3->num, buf + len * 3);
592 static enum register_status
593 m32c_pseudo_register_read (struct gdbarch *arch,
594 struct regcache *cache,
598 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
599 struct m32c_reg *reg;
601 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
602 gdb_assert (arch == cache->arch ());
603 gdb_assert (arch == tdep->regs[cookednum].arch);
604 reg = &tdep->regs[cookednum];
606 return reg->read (reg, cache, buf);
611 m32c_pseudo_register_write (struct gdbarch *arch,
612 struct regcache *cache,
616 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
617 struct m32c_reg *reg;
619 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
620 gdb_assert (arch == cache->arch ());
621 gdb_assert (arch == tdep->regs[cookednum].arch);
622 reg = &tdep->regs[cookednum];
624 reg->write (reg, cache, buf);
628 /* Add a register with the given fields to the end of ARCH's table.
629 Return a pointer to the newly added register. */
630 static struct m32c_reg *
631 add_reg (struct gdbarch *arch,
635 m32c_read_reg_t *read,
636 m32c_write_reg_t *write,
641 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
642 struct m32c_reg *r = &tdep->regs[tdep->num_regs];
644 gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS);
649 r->num = tdep->num_regs;
650 r->sim_num = sim_num;
655 r->save_restore_p = 0;
668 /* Record NUM as REG's DWARF register number. */
670 set_dwarf_regnum (struct m32c_reg *reg, int num)
672 gdb_assert (num < M32C_MAX_NUM_REGS);
674 /* Update the reg->DWARF mapping. Only count the first number
675 assigned to this register. */
676 if (reg->dwarf_num == -1)
677 reg->dwarf_num = num;
679 /* Update the DWARF->reg mapping. */
680 gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg;
684 /* Mark REG as a general-purpose register, and return it. */
685 static struct m32c_reg *
686 mark_general (struct m32c_reg *reg)
693 /* Mark REG as a DMA register, and return it. */
694 static struct m32c_reg *
695 mark_dma (struct m32c_reg *reg)
702 /* Mark REG as a SYSTEM register, and return it. */
703 static struct m32c_reg *
704 mark_system (struct m32c_reg *reg)
711 /* Mark REG as a save-restore register, and return it. */
712 static struct m32c_reg *
713 mark_save_restore (struct m32c_reg *reg)
715 reg->save_restore_p = 1;
720 #define FLAGBIT_B 0x0010
721 #define FLAGBIT_U 0x0080
723 /* Handy macros for declaring registers. These all evaluate to
724 pointers to the register declared. Macros that define two
725 registers evaluate to a pointer to the first. */
727 /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */
728 #define R(name, type, sim_num) \
729 (add_reg (arch, (name), (type), (sim_num), \
730 m32c_raw_read, m32c_raw_write, NULL, NULL, 0))
732 /* The simulator register number for a raw register named NAME. */
733 #define SIM(name) (m32c_sim_reg_ ## name)
735 /* A raw unsigned 16-bit data register named NAME.
736 NAME should be an identifier, not a string. */
738 (R(#name, tdep->uint16, SIM (name)))
740 /* A raw data address register named NAME.
741 NAME should be an identifier, not a string. */
743 (R(#name, tdep->data_addr_reg_type, SIM (name)))
745 /* A raw code address register named NAME. NAME should
746 be an identifier, not a string. */
748 (R(#name, tdep->code_addr_reg_type, SIM (name)))
750 /* A pair of raw registers named NAME0 and NAME1, with type TYPE.
751 NAME should be an identifier, not a string. */
752 #define RP(name, type) \
753 (R(#name "0", (type), SIM (name ## 0)), \
754 R(#name "1", (type), SIM (name ## 1)) - 1)
756 /* A raw banked general-purpose data register named NAME.
757 NAME should be an identifier, not a string. */
759 (R(NULL, tdep->int16, SIM (name ## _bank0)), \
760 R(NULL, tdep->int16, SIM (name ## _bank1)) - 1)
762 /* A raw banked data address register named NAME.
763 NAME should be an identifier, not a string. */
765 (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \
766 R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1)
768 /* A cooked register named NAME referring to a raw banked register
769 from the bank selected by the current value of FLG. RAW_PAIR
770 should be a pointer to the first register in the banked pair.
771 NAME must be an identifier, not a string. */
772 #define CB(name, raw_pair) \
773 (add_reg (arch, #name, (raw_pair)->type, 0, \
774 m32c_banked_read, m32c_banked_write, \
775 (raw_pair), (raw_pair + 1), FLAGBIT_B))
777 /* A pair of registers named NAMEH and NAMEL, of type TYPE, that
778 access the top and bottom halves of the register pointed to by
779 NAME. NAME should be an identifier. */
780 #define CHL(name, type) \
781 (add_reg (arch, #name "h", (type), 0, \
782 m32c_part_read, m32c_part_write, name, NULL, 1), \
783 add_reg (arch, #name "l", (type), 0, \
784 m32c_part_read, m32c_part_write, name, NULL, 0) - 1)
786 /* A register constructed by concatenating the two registers HIGH and
787 LOW, whose name is HIGHLOW and whose type is TYPE. */
788 #define CCAT(high, low, type) \
789 (add_reg (arch, #high #low, (type), 0, \
790 m32c_cat_read, m32c_cat_write, (high), (low), 0))
792 /* Abbreviations for marking register group membership. */
793 #define G(reg) (mark_general (reg))
794 #define S(reg) (mark_system (reg))
795 #define DMA(reg) (mark_dma (reg))
798 /* Construct the register set for ARCH. */
800 make_regs (struct gdbarch *arch)
802 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
803 int mach = gdbarch_bfd_arch_info (arch)->mach;
816 struct m32c_reg *r0hl;
817 struct m32c_reg *r1hl;
818 struct m32c_reg *r2r0;
819 struct m32c_reg *r3r1;
820 struct m32c_reg *r3r1r2r0;
821 struct m32c_reg *r3r2r1r0;
822 struct m32c_reg *a1a0;
824 struct m32c_reg *raw_r0_pair = RBD (r0);
825 struct m32c_reg *raw_r1_pair = RBD (r1);
826 struct m32c_reg *raw_r2_pair = RBD (r2);
827 struct m32c_reg *raw_r3_pair = RBD (r3);
828 struct m32c_reg *raw_a0_pair = RBA (a0);
829 struct m32c_reg *raw_a1_pair = RBA (a1);
830 struct m32c_reg *raw_fb_pair = RBA (fb);
832 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
833 We always declare both raw registers, and deal with the distinction
834 in the pseudoregister. */
835 struct m32c_reg *raw_sb_pair = RBA (sb);
837 struct m32c_reg *usp = S (RA (usp));
838 struct m32c_reg *isp = S (RA (isp));
839 struct m32c_reg *intb = S (RC (intb));
840 struct m32c_reg *pc = G (RC (pc));
841 struct m32c_reg *flg = G (R16U (flg));
843 if (mach == bfd_mach_m32c)
845 struct m32c_reg *svf = S (R16U (svf));
846 struct m32c_reg *svp = S (RC (svp));
847 struct m32c_reg *vct = S (RC (vct));
849 struct m32c_reg *dmd01 = DMA (RP (dmd, tdep->uint8));
850 struct m32c_reg *dct01 = DMA (RP (dct, tdep->uint16));
851 struct m32c_reg *drc01 = DMA (RP (drc, tdep->uint16));
852 struct m32c_reg *dma01 = DMA (RP (dma, tdep->data_addr_reg_type));
853 struct m32c_reg *dsa01 = DMA (RP (dsa, tdep->data_addr_reg_type));
854 struct m32c_reg *dra01 = DMA (RP (dra, tdep->data_addr_reg_type));
857 num_raw_regs = tdep->num_regs;
859 r0 = G (CB (r0, raw_r0_pair));
860 r1 = G (CB (r1, raw_r1_pair));
861 r2 = G (CB (r2, raw_r2_pair));
862 r3 = G (CB (r3, raw_r3_pair));
863 a0 = G (CB (a0, raw_a0_pair));
864 a1 = G (CB (a1, raw_a1_pair));
865 fb = G (CB (fb, raw_fb_pair));
867 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
868 Specify custom read/write functions that do the right thing. */
869 sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0,
870 m32c_sb_read, m32c_sb_write,
871 raw_sb_pair, raw_sb_pair + 1, 0));
873 /* The current sp is either usp or isp, depending on the value of
874 the FLG register's U bit. */
875 sp = G (add_reg (arch, "sp", usp->type, 0,
876 m32c_banked_read, m32c_banked_write,
877 isp, usp, FLAGBIT_U));
879 r0hl = CHL (r0, tdep->int8);
880 r1hl = CHL (r1, tdep->int8);
881 CHL (r2, tdep->int8);
882 CHL (r3, tdep->int8);
883 CHL (intb, tdep->int16);
885 r2r0 = CCAT (r2, r0, tdep->int32);
886 r3r1 = CCAT (r3, r1, tdep->int32);
887 r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64);
890 = add_reg (arch, "r3r2r1r0", tdep->int64, 0,
891 m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0);
893 if (mach == bfd_mach_m16c)
894 a1a0 = CCAT (a1, a0, tdep->int32);
898 num_cooked_regs = tdep->num_regs - num_raw_regs;
907 tdep->r3r2r1r0 = r3r2r1r0;
908 tdep->r3r1r2r0 = r3r1r2r0;
915 /* Set up the DWARF register table. */
916 memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs));
917 set_dwarf_regnum (r0hl + 1, 0x01);
918 set_dwarf_regnum (r0hl + 0, 0x02);
919 set_dwarf_regnum (r1hl + 1, 0x03);
920 set_dwarf_regnum (r1hl + 0, 0x04);
921 set_dwarf_regnum (r0, 0x05);
922 set_dwarf_regnum (r1, 0x06);
923 set_dwarf_regnum (r2, 0x07);
924 set_dwarf_regnum (r3, 0x08);
925 set_dwarf_regnum (a0, 0x09);
926 set_dwarf_regnum (a1, 0x0a);
927 set_dwarf_regnum (fb, 0x0b);
928 set_dwarf_regnum (sp, 0x0c);
929 set_dwarf_regnum (pc, 0x0d); /* GCC's invention */
930 set_dwarf_regnum (sb, 0x13);
931 set_dwarf_regnum (r2r0, 0x15);
932 set_dwarf_regnum (r3r1, 0x16);
934 set_dwarf_regnum (a1a0, 0x17);
936 /* Enumerate the save/restore register group.
938 The regcache_save and regcache_restore functions apply their read
939 function to each register in this group.
941 Since frame_pop supplies frame_unwind_register as its read
942 function, the registers meaningful to the Dwarf unwinder need to
945 On the other hand, when we make inferior calls, save_inferior_status
946 and restore_inferior_status use them to preserve the current register
947 values across the inferior call. For this, you'd kind of like to
948 preserve all the raw registers, to protect the interrupted code from
949 any sort of bank switching the callee might have done. But we handle
950 those cases so badly anyway --- for example, it matters whether we
951 restore FLG before or after we restore the general-purpose registers,
952 but there's no way to express that --- that it isn't worth worrying
955 We omit control registers like inthl: if you call a function that
956 changes those, it's probably because you wanted that change to be
957 visible to the interrupted code. */
958 mark_save_restore (r0);
959 mark_save_restore (r1);
960 mark_save_restore (r2);
961 mark_save_restore (r3);
962 mark_save_restore (a0);
963 mark_save_restore (a1);
964 mark_save_restore (sb);
965 mark_save_restore (fb);
966 mark_save_restore (sp);
967 mark_save_restore (pc);
968 mark_save_restore (flg);
970 set_gdbarch_num_regs (arch, num_raw_regs);
971 set_gdbarch_num_pseudo_regs (arch, num_cooked_regs);
972 set_gdbarch_pc_regnum (arch, pc->num);
973 set_gdbarch_sp_regnum (arch, sp->num);
974 set_gdbarch_register_name (arch, m32c_register_name);
975 set_gdbarch_register_type (arch, m32c_register_type);
976 set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read);
977 set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write);
978 set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno);
979 set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
980 set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
981 set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p);
983 reggroup_add (arch, general_reggroup);
984 reggroup_add (arch, all_reggroup);
985 reggroup_add (arch, save_reggroup);
986 reggroup_add (arch, restore_reggroup);
987 reggroup_add (arch, system_reggroup);
988 reggroup_add (arch, m32c_dma_reggroup);
994 constexpr gdb_byte m32c_break_insn[] = { 0x00 }; /* brk */
996 typedef BP_MANIPULATION (m32c_break_insn) m32c_breakpoint;
999 /* Prologue analysis. */
1001 enum m32c_prologue_kind
1003 /* This function uses a frame pointer. */
1004 prologue_with_frame_ptr,
1006 /* This function has no frame pointer. */
1007 prologue_sans_frame_ptr,
1009 /* This function sets up the stack, so its frame is the first
1010 frame on the stack. */
1011 prologue_first_frame
1014 struct m32c_prologue
1016 /* For consistency with the DWARF 2 .debug_frame info generated by
1017 GCC, a frame's CFA is the address immediately after the saved
1020 /* The architecture for which we generated this prologue info. */
1021 struct gdbarch *arch;
1023 enum m32c_prologue_kind kind;
1025 /* If KIND is prologue_with_frame_ptr, this is the offset from the
1026 CFA to where the frame pointer points. This is always zero or
1028 LONGEST frame_ptr_offset;
1030 /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to
1031 the stack pointer --- always zero or negative.
1033 Calling this a "size" is a bit misleading, but given that the
1034 stack grows downwards, using offsets for everything keeps one
1035 from going completely sign-crazy: you never change anything's
1036 sign for an ADD instruction; always change the second operand's
1037 sign for a SUB instruction; and everything takes care of
1040 Functions that use alloca don't have a constant frame size. But
1041 they always have frame pointers, so we must use that to find the
1042 CFA (and perhaps to unwind the stack pointer). */
1045 /* The address of the first instruction at which the frame has been
1046 set up and the arguments are where the debug info says they are
1047 --- as best as we can tell. */
1048 CORE_ADDR prologue_end;
1050 /* reg_offset[R] is the offset from the CFA at which register R is
1051 saved, or 1 if register R has not been saved. (Real values are
1052 always zero or negative.) */
1053 LONGEST reg_offset[M32C_MAX_NUM_REGS];
1057 /* The longest I've seen, anyway. */
1058 #define M32C_MAX_INSN_LEN (9)
1060 /* Processor state, for the prologue analyzer. */
1061 struct m32c_pv_state
1063 struct gdbarch *arch;
1064 pv_t r0, r1, r2, r3;
1068 struct pv_area *stack;
1070 /* Bytes from the current PC, the address they were read from,
1071 and the address of the next unconsumed byte. */
1072 gdb_byte insn[M32C_MAX_INSN_LEN];
1073 CORE_ADDR scan_pc, next_addr;
1077 /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if
1078 all went well, or non-zero if simulating the action would trash our
1081 m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size)
1083 if (state->stack->store_would_trash (state->sp))
1086 state->sp = pv_add_constant (state->sp, -size);
1087 state->stack->store (state->sp, size, value);
1096 srcdest_partial_reg,
1100 /* A source or destination location for an m16c or m32c
1104 /* If srcdest_reg, the location is a register pointed to by REG.
1105 If srcdest_partial_reg, the location is part of a register pointed
1106 to by REG. We don't try to handle this too well.
1107 If srcdest_mem, the location is memory whose address is ADDR. */
1108 enum srcdest_kind kind;
1113 /* Return the SIZE-byte value at LOC in STATE. */
1115 m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size)
1117 if (loc.kind == srcdest_mem)
1118 return state->stack->fetch (loc.addr, size);
1119 else if (loc.kind == srcdest_partial_reg)
1120 return pv_unknown ();
1126 /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if
1127 all went well, or non-zero if simulating the store would trash our
1130 m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc,
1131 pv_t value, int size)
1133 if (loc.kind == srcdest_mem)
1135 if (state->stack->store_would_trash (loc.addr))
1137 state->stack->store (loc.addr, size, value);
1139 else if (loc.kind == srcdest_partial_reg)
1140 *loc.reg = pv_unknown ();
1149 m32c_sign_ext (int v, int bits)
1151 int mask = 1 << (bits - 1);
1152 return (v ^ mask) - mask;
1156 m32c_next_byte (struct m32c_pv_state *st)
1158 gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn));
1159 return st->insn[st->next_addr++ - st->scan_pc];
1163 m32c_udisp8 (struct m32c_pv_state *st)
1165 return m32c_next_byte (st);
1170 m32c_sdisp8 (struct m32c_pv_state *st)
1172 return m32c_sign_ext (m32c_next_byte (st), 8);
1177 m32c_udisp16 (struct m32c_pv_state *st)
1179 int low = m32c_next_byte (st);
1180 int high = m32c_next_byte (st);
1182 return low + (high << 8);
1187 m32c_sdisp16 (struct m32c_pv_state *st)
1189 int low = m32c_next_byte (st);
1190 int high = m32c_next_byte (st);
1192 return m32c_sign_ext (low + (high << 8), 16);
1197 m32c_udisp24 (struct m32c_pv_state *st)
1199 int low = m32c_next_byte (st);
1200 int mid = m32c_next_byte (st);
1201 int high = m32c_next_byte (st);
1203 return low + (mid << 8) + (high << 16);
1207 /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */
1209 m32c_get_src23 (unsigned char *i)
1211 return (((i[0] & 0x70) >> 2)
1212 | ((i[1] & 0x30) >> 4));
1216 /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */
1218 m32c_get_dest23 (unsigned char *i)
1220 return (((i[0] & 0x0e) << 1)
1221 | ((i[1] & 0xc0) >> 6));
1225 static struct srcdest
1226 m32c_decode_srcdest4 (struct m32c_pv_state *st,
1232 sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg);
1234 sd.kind = srcdest_mem;
1236 sd.addr = pv_unknown ();
1241 case 0x0: sd.reg = (size == 1 ? &st->r0 : &st->r0); break;
1242 case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break;
1243 case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break;
1244 case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break;
1246 case 0x4: sd.reg = &st->a0; break;
1247 case 0x5: sd.reg = &st->a1; break;
1249 case 0x6: sd.addr = st->a0; break;
1250 case 0x7: sd.addr = st->a1; break;
1252 case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1253 case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1254 case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1255 case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1257 case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1258 case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1259 case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1260 case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1263 gdb_assert_not_reached ("unexpected srcdest4");
1270 static struct srcdest
1271 m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind)
1275 sd.addr = pv_unknown ();
1284 sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg;
1289 sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg;
1293 sd.kind = srcdest_mem;
1300 case 0x12: sd.reg = &st->r0; break;
1301 case 0x13: sd.reg = &st->r1; break;
1302 case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break;
1303 case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break;
1304 case 0x02: sd.reg = &st->a0; break;
1305 case 0x03: sd.reg = &st->a1; break;
1307 case 0x00: sd.addr = st->a0; break;
1308 case 0x01: sd.addr = st->a1; break;
1309 case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1310 case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1311 case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1312 case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1313 case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1314 case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1315 case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1316 case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break;
1317 case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break;
1318 case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break;
1319 case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1320 case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break;
1322 gdb_assert_not_reached ("unexpected sd23");
1327 sd.addr = m32c_srcdest_fetch (st, sd, 4);
1328 sd.kind = srcdest_mem;
1335 /* The r16c and r32c machines have instructions with similar
1336 semantics, but completely different machine language encodings. So
1337 we break out the semantics into their own functions, and leave
1338 machine-specific decoding in m32c_analyze_prologue.
1340 The following functions all expect their arguments already decoded,
1341 and they all return zero if analysis should continue past this
1342 instruction, or non-zero if analysis should stop. */
1345 /* Simulate an 'enter SIZE' instruction in STATE. */
1347 m32c_pv_enter (struct m32c_pv_state *state, int size)
1349 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1351 /* If simulating this store would require us to forget
1352 everything we know about the stack frame in the name of
1353 accuracy, it would be better to just quit now. */
1354 if (state->stack->store_would_trash (state->sp))
1357 if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes))
1359 state->fb = state->sp;
1360 state->sp = pv_add_constant (state->sp, -size);
1367 m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg,
1368 int bit, int src, int size)
1372 if (m32c_pv_push (state, reg, size))
1380 /* Simulate a 'pushm SRC' instruction in STATE. */
1382 m32c_pv_pushm (struct m32c_pv_state *state, int src)
1384 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1386 /* The bits in SRC indicating which registers to save are:
1387 r0 r1 r2 r3 a0 a1 sb fb */
1389 ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes)
1390 || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes)
1391 || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes)
1392 || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes)
1393 || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2)
1394 || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2)
1395 || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2)
1396 || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2));
1399 /* Return non-zero if VALUE is the first incoming argument register. */
1402 m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value)
1404 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1405 return (value.kind == pvk_register
1406 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1407 ? (value.reg == tdep->r1->num)
1408 : (value.reg == tdep->r0->num))
1412 /* Return non-zero if VALUE is an incoming argument register. */
1415 m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value)
1417 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1418 return (value.kind == pvk_register
1419 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1420 ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num)
1421 : (value.reg == tdep->r0->num))
1425 /* Return non-zero if a store of VALUE to LOC is probably spilling an
1426 argument register to its stack slot in STATE. Such instructions
1427 should be included in the prologue, if possible.
1429 The store is a spill if:
1430 - the value being stored is the original value of an argument register;
1431 - the value has not already been stored somewhere in STACK; and
1432 - LOC is a stack slot (e.g., a memory location whose address is
1433 relative to the original value of the SP). */
1436 m32c_is_arg_spill (struct m32c_pv_state *st,
1440 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1442 return (m32c_is_arg_reg (st, value)
1443 && loc.kind == srcdest_mem
1444 && pv_is_register (loc.addr, tdep->sp->num)
1445 && ! st->stack->find_reg (st->arch, value.reg, 0));
1448 /* Return non-zero if a store of VALUE to LOC is probably
1449 copying the struct return address into an address register
1450 for immediate use. This is basically a "spill" into the
1451 address register, instead of onto the stack.
1453 The prerequisites are:
1454 - value being stored is original value of the FIRST arg register;
1455 - value has not already been stored on stack; and
1456 - LOC is an address register (a0 or a1). */
1459 m32c_is_struct_return (struct m32c_pv_state *st,
1463 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1465 return (m32c_is_1st_arg_reg (st, value)
1466 && !st->stack->find_reg (st->arch, value.reg, 0)
1467 && loc.kind == srcdest_reg
1468 && (pv_is_register (*loc.reg, tdep->a0->num)
1469 || pv_is_register (*loc.reg, tdep->a1->num)));
1472 /* Return non-zero if a 'pushm' saving the registers indicated by SRC
1473 was a register save:
1474 - all the named registers should have their original values, and
1475 - the stack pointer should be at a constant offset from the
1476 original stack pointer. */
1478 m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src)
1480 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1481 /* The bits in SRC indicating which registers to save are:
1482 r0 r1 r2 r3 a0 a1 sb fb */
1484 (pv_is_register (st->sp, tdep->sp->num)
1485 && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0))
1486 && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0))
1487 && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0))
1488 && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0))
1489 && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0))
1490 && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0))
1491 && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0))
1492 && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0)));
1496 /* Function for finding saved registers in a 'struct pv_area'; we pass
1497 this to pv_area::scan.
1499 If VALUE is a saved register, ADDR says it was saved at a constant
1500 offset from the frame base, and SIZE indicates that the whole
1501 register was saved, record its offset in RESULT_UNTYPED. */
1503 check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value)
1505 struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped;
1506 struct gdbarch *arch = prologue->arch;
1507 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1509 /* Is this the unchanged value of some register being saved on the
1511 if (value.kind == pvk_register
1513 && pv_is_register (addr, tdep->sp->num))
1515 /* Some registers require special handling: they're saved as a
1516 larger value than the register itself. */
1517 CORE_ADDR saved_size = register_size (arch, value.reg);
1519 if (value.reg == tdep->pc->num)
1520 saved_size = tdep->ret_addr_bytes;
1521 else if (register_type (arch, value.reg)
1522 == tdep->data_addr_reg_type)
1523 saved_size = tdep->push_addr_bytes;
1525 if (size == saved_size)
1527 /* Find which end of the saved value corresponds to our
1529 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
1530 prologue->reg_offset[value.reg]
1531 = (addr.k + saved_size - register_size (arch, value.reg));
1533 prologue->reg_offset[value.reg] = addr.k;
1539 /* Analyze the function prologue for ARCH at START, going no further
1540 than LIMIT, and place a description of what we found in
1543 m32c_analyze_prologue (struct gdbarch *arch,
1544 CORE_ADDR start, CORE_ADDR limit,
1545 struct m32c_prologue *prologue)
1547 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1548 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
1549 CORE_ADDR after_last_frame_related_insn;
1550 struct m32c_pv_state st;
1553 st.r0 = pv_register (tdep->r0->num, 0);
1554 st.r1 = pv_register (tdep->r1->num, 0);
1555 st.r2 = pv_register (tdep->r2->num, 0);
1556 st.r3 = pv_register (tdep->r3->num, 0);
1557 st.a0 = pv_register (tdep->a0->num, 0);
1558 st.a1 = pv_register (tdep->a1->num, 0);
1559 st.sb = pv_register (tdep->sb->num, 0);
1560 st.fb = pv_register (tdep->fb->num, 0);
1561 st.sp = pv_register (tdep->sp->num, 0);
1562 st.pc = pv_register (tdep->pc->num, 0);
1563 pv_area stack (tdep->sp->num, gdbarch_addr_bit (arch));
1566 /* Record that the call instruction has saved the return address on
1568 m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes);
1570 memset (prologue, 0, sizeof (*prologue));
1571 prologue->arch = arch;
1574 for (i = 0; i < M32C_MAX_NUM_REGS; i++)
1575 prologue->reg_offset[i] = 1;
1578 st.scan_pc = after_last_frame_related_insn = start;
1580 while (st.scan_pc < limit)
1582 pv_t pre_insn_fb = st.fb;
1583 pv_t pre_insn_sp = st.sp;
1585 /* In theory we could get in trouble by trying to read ahead
1586 here, when we only know we're expecting one byte. In
1587 practice I doubt anyone will care, and it makes the rest of
1589 if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn)))
1590 /* If we can't fetch the instruction from memory, stop here
1591 and hope for the best. */
1593 st.next_addr = st.scan_pc;
1595 /* The assembly instructions are written as they appear in the
1596 section of the processor manuals that describe the
1597 instruction encodings.
1599 When a single assembly language instruction has several
1600 different machine-language encodings, the manual
1601 distinguishes them by a number in parens, before the
1602 mnemonic. Those numbers are included, as well.
1604 The srcdest decoding instructions have the same names as the
1605 analogous functions in the simulator. */
1606 if (mach == bfd_mach_m16c)
1608 /* (1) ENTER #imm8 */
1609 if (st.insn[0] == 0x7c && st.insn[1] == 0xf2)
1611 if (m32c_pv_enter (&st, st.insn[2]))
1616 else if (st.insn[0] == 0xec)
1618 int src = st.insn[1];
1619 if (m32c_pv_pushm (&st, src))
1623 if (m32c_pushm_is_reg_save (&st, src))
1624 after_last_frame_related_insn = st.next_addr;
1627 /* (6) MOV.size:G src, dest */
1628 else if ((st.insn[0] & 0xfe) == 0x72)
1630 int size = (st.insn[0] & 0x01) ? 2 : 1;
1632 struct srcdest dest;
1637 = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size);
1639 = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size);
1640 src_value = m32c_srcdest_fetch (&st, src, size);
1642 if (m32c_is_arg_spill (&st, dest, src_value))
1643 after_last_frame_related_insn = st.next_addr;
1644 else if (m32c_is_struct_return (&st, dest, src_value))
1645 after_last_frame_related_insn = st.next_addr;
1647 if (m32c_srcdest_store (&st, dest, src_value, size))
1651 /* (1) LDC #IMM16, sp */
1652 else if (st.insn[0] == 0xeb
1653 && st.insn[1] == 0x50)
1656 st.sp = pv_constant (m32c_udisp16 (&st));
1660 /* We've hit some instruction we don't know how to simulate.
1661 Strictly speaking, we should set every value we're
1662 tracking to "unknown". But we'll be optimistic, assume
1663 that we have enough information already, and stop
1669 int src_indirect = 0;
1670 int dest_indirect = 0;
1673 gdb_assert (mach == bfd_mach_m32c);
1675 /* Check for prefix bytes indicating indirect addressing. */
1676 if (st.insn[0] == 0x41)
1681 else if (st.insn[0] == 0x09)
1686 else if (st.insn[0] == 0x49)
1688 src_indirect = dest_indirect = 1;
1692 /* (1) ENTER #imm8 */
1693 if (st.insn[i] == 0xec)
1695 if (m32c_pv_enter (&st, st.insn[i + 1]))
1701 else if (st.insn[i] == 0x8f)
1703 int src = st.insn[i + 1];
1704 if (m32c_pv_pushm (&st, src))
1708 if (m32c_pushm_is_reg_save (&st, src))
1709 after_last_frame_related_insn = st.next_addr;
1712 /* (7) MOV.size:G src, dest */
1713 else if ((st.insn[i] & 0x80) == 0x80
1714 && (st.insn[i + 1] & 0x0f) == 0x0b
1715 && m32c_get_src23 (&st.insn[i]) < 20
1716 && m32c_get_dest23 (&st.insn[i]) < 20)
1719 struct srcdest dest;
1721 int bw = st.insn[i] & 0x01;
1722 int size = bw ? 2 : 1;
1726 = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]),
1727 size, src_indirect);
1729 = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]),
1730 size, dest_indirect);
1731 src_value = m32c_srcdest_fetch (&st, src, size);
1733 if (m32c_is_arg_spill (&st, dest, src_value))
1734 after_last_frame_related_insn = st.next_addr;
1736 if (m32c_srcdest_store (&st, dest, src_value, size))
1739 /* (2) LDC #IMM24, sp */
1740 else if (st.insn[i] == 0xd5
1741 && st.insn[i + 1] == 0x29)
1744 st.sp = pv_constant (m32c_udisp24 (&st));
1747 /* We've hit some instruction we don't know how to simulate.
1748 Strictly speaking, we should set every value we're
1749 tracking to "unknown". But we'll be optimistic, assume
1750 that we have enough information already, and stop
1755 /* If this instruction changed the FB or decreased the SP (i.e.,
1756 allocated more stack space), then this may be a good place to
1757 declare the prologue finished. However, there are some
1760 - If the instruction just changed the FB back to its original
1761 value, then that's probably a restore instruction. The
1762 prologue should definitely end before that.
1764 - If the instruction increased the value of the SP (that is,
1765 shrunk the frame), then it's probably part of a frame
1766 teardown sequence, and the prologue should end before
1769 if (! pv_is_identical (st.fb, pre_insn_fb))
1771 if (! pv_is_register_k (st.fb, tdep->fb->num, 0))
1772 after_last_frame_related_insn = st.next_addr;
1774 else if (! pv_is_identical (st.sp, pre_insn_sp))
1776 /* The comparison of the constants looks odd, there, because
1777 .k is unsigned. All it really means is that the SP is
1778 lower than it was before the instruction. */
1779 if ( pv_is_register (pre_insn_sp, tdep->sp->num)
1780 && pv_is_register (st.sp, tdep->sp->num)
1781 && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k)))
1782 after_last_frame_related_insn = st.next_addr;
1785 st.scan_pc = st.next_addr;
1788 /* Did we load a constant value into the stack pointer? */
1789 if (pv_is_constant (st.sp))
1790 prologue->kind = prologue_first_frame;
1792 /* Alternatively, did we initialize the frame pointer? Remember
1793 that the CFA is the address after the return address. */
1794 if (pv_is_register (st.fb, tdep->sp->num))
1796 prologue->kind = prologue_with_frame_ptr;
1797 prologue->frame_ptr_offset = st.fb.k;
1800 /* Is the frame size a known constant? Remember that frame_size is
1801 actually the offset from the CFA to the SP (i.e., a negative
1803 else if (pv_is_register (st.sp, tdep->sp->num))
1805 prologue->kind = prologue_sans_frame_ptr;
1806 prologue->frame_size = st.sp.k;
1809 /* We haven't been able to make sense of this function's frame. Treat
1810 it as the first frame. */
1812 prologue->kind = prologue_first_frame;
1814 /* Record where all the registers were saved. */
1815 st.stack->scan (check_for_saved, (void *) prologue);
1817 prologue->prologue_end = after_last_frame_related_insn;
1822 m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip)
1825 CORE_ADDR func_addr, func_end, sal_end;
1826 struct m32c_prologue p;
1828 /* Try to find the extent of the function that contains IP. */
1829 if (! find_pc_partial_function (ip, &name, &func_addr, &func_end))
1832 /* Find end by prologue analysis. */
1833 m32c_analyze_prologue (gdbarch, ip, func_end, &p);
1834 /* Find end by line info. */
1835 sal_end = skip_prologue_using_sal (gdbarch, ip);
1836 /* Return whichever is lower. */
1837 if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end)
1840 return p.prologue_end;
1845 /* Stack unwinding. */
1847 static struct m32c_prologue *
1848 m32c_analyze_frame_prologue (struct frame_info *this_frame,
1849 void **this_prologue_cache)
1851 if (! *this_prologue_cache)
1853 CORE_ADDR func_start = get_frame_func (this_frame);
1854 CORE_ADDR stop_addr = get_frame_pc (this_frame);
1856 /* If we couldn't find any function containing the PC, then
1857 just initialize the prologue cache, but don't do anything. */
1859 stop_addr = func_start;
1861 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue);
1862 m32c_analyze_prologue (get_frame_arch (this_frame),
1863 func_start, stop_addr,
1864 (struct m32c_prologue *) *this_prologue_cache);
1867 return (struct m32c_prologue *) *this_prologue_cache;
1872 m32c_frame_base (struct frame_info *this_frame,
1873 void **this_prologue_cache)
1875 struct m32c_prologue *p
1876 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache);
1877 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1879 /* In functions that use alloca, the distance between the stack
1880 pointer and the frame base varies dynamically, so we can't use
1881 the SP plus static information like prologue analysis to find the
1882 frame base. However, such functions must have a frame pointer,
1883 to be able to restore the SP on exit. So whenever we do have a
1884 frame pointer, use that to find the base. */
1887 case prologue_with_frame_ptr:
1890 = get_frame_register_unsigned (this_frame, tdep->fb->num);
1891 return fb - p->frame_ptr_offset;
1894 case prologue_sans_frame_ptr:
1897 = get_frame_register_unsigned (this_frame, tdep->sp->num);
1898 return sp - p->frame_size;
1901 case prologue_first_frame:
1905 gdb_assert_not_reached ("unexpected prologue kind");
1911 m32c_this_id (struct frame_info *this_frame,
1912 void **this_prologue_cache,
1913 struct frame_id *this_id)
1915 CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache);
1918 *this_id = frame_id_build (base, get_frame_func (this_frame));
1919 /* Otherwise, leave it unset, and that will terminate the backtrace. */
1923 static struct value *
1924 m32c_prev_register (struct frame_info *this_frame,
1925 void **this_prologue_cache, int regnum)
1927 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1928 struct m32c_prologue *p
1929 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache);
1930 CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache);
1932 if (regnum == tdep->sp->num)
1933 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1935 /* If prologue analysis says we saved this register somewhere,
1936 return a description of the stack slot holding it. */
1937 if (p->reg_offset[regnum] != 1)
1938 return frame_unwind_got_memory (this_frame, regnum,
1939 frame_base + p->reg_offset[regnum]);
1941 /* Otherwise, presume we haven't changed the value of this
1942 register, and get it from the next frame. */
1943 return frame_unwind_got_register (this_frame, regnum, regnum);
1947 static const struct frame_unwind m32c_unwind = {
1949 default_frame_unwind_stop_reason,
1953 default_frame_sniffer
1958 m32c_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1960 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1961 return frame_unwind_register_unsigned (next_frame, tdep->pc->num);
1966 m32c_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1968 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1969 return frame_unwind_register_unsigned (next_frame, tdep->sp->num);
1973 /* Inferior calls. */
1975 /* The calling conventions, according to GCC:
1979 First arg may be passed in r1l or r1 if it (1) fits (QImode or
1980 HImode), (2) is named, and (3) is an integer or pointer type (no
1981 structs, floats, etc). Otherwise, it's passed on the stack.
1983 Second arg may be passed in r2, same restrictions (but not QImode),
1984 even if the first arg is passed on the stack.
1986 Third and further args are passed on the stack. No padding is
1987 used, stack "alignment" is 8 bits.
1992 First arg may be passed in r0l or r0, same restrictions as above.
1994 Second and further args are passed on the stack. Padding is used
1995 after QImode parameters (i.e. lower-addressed byte is the value,
1996 higher-addressed byte is the padding), stack "alignment" is 16
2000 /* Return true if TYPE is a type that can be passed in registers. (We
2001 ignore the size, and pay attention only to the type code;
2002 acceptable sizes depends on which register is being considered to
2005 m32c_reg_arg_type (struct type *type)
2007 enum type_code code = TYPE_CODE (type);
2009 return (code == TYPE_CODE_INT
2010 || code == TYPE_CODE_ENUM
2011 || code == TYPE_CODE_PTR
2012 || TYPE_IS_REFERENCE (type)
2013 || code == TYPE_CODE_BOOL
2014 || code == TYPE_CODE_CHAR);
2019 m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2020 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2021 struct value **args, CORE_ADDR sp, int struct_return,
2022 CORE_ADDR struct_addr)
2024 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2025 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2026 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
2030 /* The number of arguments given in this function's prototype, or
2031 zero if it has a non-prototyped function type. The m32c ABI
2032 passes arguments mentioned in the prototype differently from
2033 those in the ellipsis of a varargs function, or from those passed
2034 to a non-prototyped function. */
2035 int num_prototyped_args = 0;
2038 struct type *func_type = value_type (function);
2040 /* Dereference function pointer types. */
2041 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
2042 func_type = TYPE_TARGET_TYPE (func_type);
2044 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC ||
2045 TYPE_CODE (func_type) == TYPE_CODE_METHOD);
2048 /* The ABI description in gcc/config/m32c/m32c.abi says that
2049 we need to handle prototyped and non-prototyped functions
2050 separately, but the code in GCC doesn't actually do so. */
2051 if (TYPE_PROTOTYPED (func_type))
2053 num_prototyped_args = TYPE_NFIELDS (func_type);
2056 /* First, if the function returns an aggregate by value, push a
2057 pointer to a buffer for it. This doesn't affect the way
2058 subsequent arguments are allocated to registers. */
2061 int ptr_len = TYPE_LENGTH (tdep->ptr_voyd);
2063 write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr);
2066 /* Push the arguments. */
2067 for (i = nargs - 1; i >= 0; i--)
2069 struct value *arg = args[i];
2070 const gdb_byte *arg_bits = value_contents (arg);
2071 struct type *arg_type = value_type (arg);
2072 ULONGEST arg_size = TYPE_LENGTH (arg_type);
2074 /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */
2077 && i < num_prototyped_args
2078 && m32c_reg_arg_type (arg_type))
2080 /* Extract and re-store as an integer as a terse way to make
2081 sure it ends up in the least significant end of r1. (GDB
2082 should avoid assuming endianness, even on uni-endian
2084 ULONGEST u = extract_unsigned_integer (arg_bits, arg_size,
2086 struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0;
2087 regcache_cooked_write_unsigned (regcache, reg->num, u);
2090 /* Can it go in r2? */
2091 else if (mach == bfd_mach_m16c
2094 && i < num_prototyped_args
2095 && m32c_reg_arg_type (arg_type))
2096 regcache_cooked_write (regcache, tdep->r2->num, arg_bits);
2098 /* Everything else goes on the stack. */
2103 /* Align the stack. */
2104 if (mach == bfd_mach_m32c)
2107 write_memory (sp, arg_bits, arg_size);
2111 /* This is the CFA we use to identify the dummy frame. */
2114 /* Push the return address. */
2115 sp -= tdep->ret_addr_bytes;
2116 write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order,
2119 /* Update the stack pointer. */
2120 regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp);
2122 /* We need to borrow an odd trick from the i386 target here.
2124 The value we return from this function gets used as the stack
2125 address (the CFA) for the dummy frame's ID. The obvious thing is
2126 to return the new TOS. However, that points at the return
2127 address, saved on the stack, which is inconsistent with the CFA's
2128 described by GCC's DWARF 2 .debug_frame information: DWARF 2
2129 .debug_frame info uses the address immediately after the saved
2130 return address. So you end up with a dummy frame whose CFA
2131 points at the return address, but the frame for the function
2132 being called has a CFA pointing after the return address: the
2133 younger CFA is *greater than* the older CFA. The sanity checks
2134 in frame.c don't like that.
2136 So we try to be consistent with the CFA's used by DWARF 2.
2137 Having a dummy frame and a real frame with the *same* CFA is
2143 static struct frame_id
2144 m32c_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2146 /* This needs to return a frame ID whose PC is the return address
2147 passed to m32c_push_dummy_call, and whose stack_addr is the SP
2148 m32c_push_dummy_call returned.
2150 m32c_unwind_sp gives us the CFA, which is the value the SP had
2151 before the return address was pushed. */
2152 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2153 CORE_ADDR sp = get_frame_register_unsigned (this_frame, tdep->sp->num);
2154 return frame_id_build (sp, get_frame_pc (this_frame));
2159 /* Return values. */
2161 /* Return value conventions, according to GCC:
2172 Aggregate values (regardless of size) are returned by pushing a
2173 pointer to a temporary area on the stack after the args are pushed.
2174 The function fills in this area with the value. Note that this
2175 pointer on the stack does not affect how register arguments, if any,
2182 /* Return non-zero if values of type TYPE are returned by storing them
2183 in a buffer whose address is passed on the stack, ahead of the
2186 m32c_return_by_passed_buf (struct type *type)
2188 enum type_code code = TYPE_CODE (type);
2190 return (code == TYPE_CODE_STRUCT
2191 || code == TYPE_CODE_UNION);
2194 static enum return_value_convention
2195 m32c_return_value (struct gdbarch *gdbarch,
2196 struct value *function,
2197 struct type *valtype,
2198 struct regcache *regcache,
2200 const gdb_byte *writebuf)
2202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2203 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2204 enum return_value_convention conv;
2205 ULONGEST valtype_len = TYPE_LENGTH (valtype);
2207 if (m32c_return_by_passed_buf (valtype))
2208 conv = RETURN_VALUE_STRUCT_CONVENTION;
2210 conv = RETURN_VALUE_REGISTER_CONVENTION;
2214 /* We should never be called to find values being returned by
2215 RETURN_VALUE_STRUCT_CONVENTION. Those can't be located,
2216 unless we made the call ourselves. */
2217 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2219 gdb_assert (valtype_len <= 8);
2221 /* Anything that fits in r0 is returned there. */
2222 if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2225 regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u);
2226 store_unsigned_integer (readbuf, valtype_len, byte_order, u);
2230 /* Everything else is passed in mem0, using as many bytes as
2231 needed. This is not what the Renesas tools do, but it's
2232 what GCC does at the moment. */
2233 struct bound_minimal_symbol mem0
2234 = lookup_minimal_symbol ("mem0", NULL, NULL);
2237 error (_("The return value is stored in memory at 'mem0', "
2238 "but GDB cannot find\n"
2240 read_memory (BMSYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len);
2246 /* We should never be called to store values to be returned
2247 using RETURN_VALUE_STRUCT_CONVENTION. We have no way of
2248 finding the buffer, unless we made the call ourselves. */
2249 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2251 gdb_assert (valtype_len <= 8);
2253 /* Anything that fits in r0 is returned there. */
2254 if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2256 ULONGEST u = extract_unsigned_integer (writebuf, valtype_len,
2258 regcache_cooked_write_unsigned (regcache, tdep->r0->num, u);
2262 /* Everything else is passed in mem0, using as many bytes as
2263 needed. This is not what the Renesas tools do, but it's
2264 what GCC does at the moment. */
2265 struct bound_minimal_symbol mem0
2266 = lookup_minimal_symbol ("mem0", NULL, NULL);
2269 error (_("The return value is stored in memory at 'mem0', "
2270 "but GDB cannot find\n"
2272 write_memory (BMSYMBOL_VALUE_ADDRESS (mem0), writebuf, valtype_len);
2283 /* The m16c and m32c use a trampoline function for indirect function
2284 calls. An indirect call looks like this:
2286 ... push arguments ...
2287 ... push target function address ...
2290 The code for m32c_jsri16 looks like this:
2294 # Save return address.
2296 pop.b m32c_jsri_ret+2
2298 # Store target function address.
2299 pop.w m32c_jsri_addr
2301 # Re-push return address.
2302 push.b m32c_jsri_ret+2
2303 push.w m32c_jsri_ret
2305 # Call the target function.
2306 jmpi.a m32c_jsri_addr
2308 Without further information, GDB will treat calls to m32c_jsri16
2309 like calls to any other function. Since m32c_jsri16 doesn't have
2310 debugging information, that normally means that GDB sets a step-
2311 resume breakpoint and lets the program continue --- which is not
2312 what the user wanted. (Giving the trampoline debugging info
2313 doesn't help: the user expects the program to stop in the function
2314 their program is calling, not in some trampoline code they've never
2317 The gdbarch_skip_trampoline_code method tells GDB how to step
2318 through such trampoline functions transparently to the user. When
2319 given the address of a trampoline function's first instruction,
2320 gdbarch_skip_trampoline_code should return the address of the first
2321 instruction of the function really being called. If GDB decides it
2322 wants to step into that function, it will set a breakpoint there
2323 and silently continue to it.
2325 We recognize the trampoline by name, and extract the target address
2326 directly from the stack. This isn't great, but recognizing by its
2327 code sequence seems more fragile. */
2330 m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc)
2332 struct gdbarch *gdbarch = get_frame_arch (frame);
2333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2334 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2336 /* It would be nicer to simply look up the addresses of known
2337 trampolines once, and then compare stop_pc with them. However,
2338 we'd need to ensure that that cached address got invalidated when
2339 someone loaded a new executable, and I'm not quite sure of the
2340 best way to do that. find_pc_partial_function does do some
2341 caching, so we'll see how this goes. */
2343 CORE_ADDR start, end;
2345 if (find_pc_partial_function (stop_pc, &name, &start, &end))
2347 /* Are we stopped at the beginning of the trampoline function? */
2348 if (strcmp (name, "m32c_jsri16") == 0
2349 && stop_pc == start)
2351 /* Get the stack pointer. The return address is at the top,
2352 and the target function's address is just below that. We
2353 know it's a two-byte address, since the trampoline is
2355 CORE_ADDR sp = get_frame_sp (get_current_frame ());
2357 = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes,
2360 /* What we have now is the address of a jump instruction.
2361 What we need is the destination of that jump.
2362 The opcode is 1 byte, and the destination is the next 3 bytes. */
2364 target = read_memory_unsigned_integer (target + 1, 3, byte_order);
2373 /* Address/pointer conversions. */
2375 /* On the m16c, there is a 24-bit address space, but only a very few
2376 instructions can generate addresses larger than 0xffff: jumps,
2377 jumps to subroutines, and the lde/std (load/store extended)
2380 Since GCC can only support one size of pointer, we can't have
2381 distinct 'near' and 'far' pointer types; we have to pick one size
2382 for everything. If we wanted to use 24-bit pointers, then GCC
2383 would have to use lde and ste for all memory references, which
2384 would be terrible for performance and code size. So the GNU
2385 toolchain uses 16-bit pointers for everything, and gives up the
2386 ability to have pointers point outside the first 64k of memory.
2388 However, as a special hack, we let the linker place functions at
2389 addresses above 0xffff, as long as it also places a trampoline in
2390 the low 64k for every function whose address is taken. Each
2391 trampoline consists of a single jmp.a instruction that jumps to the
2392 function's real entry point. Pointers to functions can be 16 bits
2393 long, even though the functions themselves are at higher addresses:
2394 the pointers refer to the trampolines, not the functions.
2396 This complicates things for GDB, however: given the address of a
2397 function (from debug info or linker symbols, say) which could be
2398 anywhere in the 24-bit address space, how can we find an
2399 appropriate 16-bit value to use as a pointer to it?
2401 If the linker has not generated a trampoline for the function,
2402 we're out of luck. Well, I guess we could malloc some space and
2403 write a jmp.a instruction to it, but I'm not going to get into that
2406 If the linker has generated a trampoline for the function, then it
2407 also emitted a symbol for the trampoline: if the function's linker
2408 symbol is named NAME, then the function's trampoline's linker
2409 symbol is named NAME.plt.
2411 So, given a code address:
2412 - We try to find a linker symbol at that address.
2413 - If we find such a symbol named NAME, we look for a linker symbol
2415 - If we find such a symbol, we assume it is a trampoline, and use
2416 its address as the pointer value.
2418 And, given a function pointer:
2419 - We try to find a linker symbol at that address named NAME.plt.
2420 - If we find such a symbol, we look for a linker symbol named NAME.
2421 - If we find that, we provide that as the function's address.
2422 - If any of the above steps fail, we return the original address
2423 unchanged; it might really be a function in the low 64k.
2425 See? You *knew* there was a reason you wanted to be a computer
2429 m32c_m16c_address_to_pointer (struct gdbarch *gdbarch,
2430 struct type *type, gdb_byte *buf, CORE_ADDR addr)
2432 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2433 enum type_code target_code;
2434 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type));
2436 target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2438 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2440 const char *func_name;
2442 struct bound_minimal_symbol tramp_msym;
2444 /* Try to find a linker symbol at this address. */
2445 struct bound_minimal_symbol func_msym
2446 = lookup_minimal_symbol_by_pc (addr);
2448 if (! func_msym.minsym)
2449 error (_("Cannot convert code address %s to function pointer:\n"
2450 "couldn't find a symbol at that address, to find trampoline."),
2451 paddress (gdbarch, addr));
2453 func_name = MSYMBOL_LINKAGE_NAME (func_msym.minsym);
2454 tramp_name = (char *) xmalloc (strlen (func_name) + 5);
2455 strcpy (tramp_name, func_name);
2456 strcat (tramp_name, ".plt");
2458 /* Try to find a linker symbol for the trampoline. */
2459 tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL);
2461 /* We've either got another copy of the name now, or don't need
2462 the name any more. */
2465 if (! tramp_msym.minsym)
2469 /* No PLT entry found. Mask off the upper bits of the address
2470 to make a pointer. As noted in the warning to the user
2471 below, this value might be useful if converted back into
2472 an address by GDB, but will otherwise, almost certainly,
2475 Using this masked result does seem to be useful
2476 in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into
2477 PASSes. These results appear to be correct as well.
2479 We print a warning here so that the user can make a
2480 determination about whether the result is useful or not. */
2481 ptrval = addr & 0xffff;
2483 warning (_("Cannot convert code address %s to function pointer:\n"
2484 "couldn't find trampoline named '%s.plt'.\n"
2485 "Returning pointer value %s instead; this may produce\n"
2486 "a useful result if converted back into an address by GDB,\n"
2487 "but will most likely not be useful otherwise.\n"),
2488 paddress (gdbarch, addr), func_name,
2489 paddress (gdbarch, ptrval));
2496 /* The trampoline's address is our pointer. */
2497 addr = BMSYMBOL_VALUE_ADDRESS (tramp_msym);
2501 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, addr);
2506 m32c_m16c_pointer_to_address (struct gdbarch *gdbarch,
2507 struct type *type, const gdb_byte *buf)
2509 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2511 enum type_code target_code;
2513 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type));
2515 ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
2517 target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2519 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2521 /* See if there is a minimal symbol at that address whose name is
2523 struct bound_minimal_symbol ptr_msym = lookup_minimal_symbol_by_pc (ptr);
2525 if (ptr_msym.minsym)
2527 const char *ptr_msym_name = MSYMBOL_LINKAGE_NAME (ptr_msym.minsym);
2528 int len = strlen (ptr_msym_name);
2531 && strcmp (ptr_msym_name + len - 4, ".plt") == 0)
2533 struct bound_minimal_symbol func_msym;
2534 /* We have a .plt symbol; try to find the symbol for the
2535 corresponding function.
2537 Since the trampoline contains a jump instruction, we
2538 could also just extract the jump's target address. I
2539 don't see much advantage one way or the other. */
2540 char *func_name = (char *) xmalloc (len - 4 + 1);
2541 memcpy (func_name, ptr_msym_name, len - 4);
2542 func_name[len - 4] = '\0';
2544 = lookup_minimal_symbol (func_name, NULL, NULL);
2546 /* If we do have such a symbol, return its value as the
2547 function's true address. */
2548 if (func_msym.minsym)
2549 ptr = BMSYMBOL_VALUE_ADDRESS (func_msym);
2556 for (aspace = 1; aspace <= 15; aspace++)
2558 ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr);
2560 if (ptr_msym.minsym)
2561 ptr |= aspace << 16;
2570 m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
2572 LONGEST *frame_offset)
2575 CORE_ADDR func_addr, func_end;
2576 struct m32c_prologue p;
2578 struct regcache *regcache = get_current_regcache ();
2579 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2581 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
2582 internal_error (__FILE__, __LINE__,
2583 _("No virtual frame pointer available"));
2585 m32c_analyze_prologue (gdbarch, func_addr, pc, &p);
2588 case prologue_with_frame_ptr:
2589 *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num;
2590 *frame_offset = p.frame_ptr_offset;
2592 case prologue_sans_frame_ptr:
2593 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num;
2594 *frame_offset = p.frame_size;
2597 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num;
2602 if (*frame_regnum > gdbarch_num_regs (gdbarch))
2603 internal_error (__FILE__, __LINE__,
2604 _("No virtual frame pointer available"));
2608 /* Initialization. */
2610 static struct gdbarch *
2611 m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2613 struct gdbarch *gdbarch;
2614 struct gdbarch_tdep *tdep;
2615 unsigned long mach = info.bfd_arch_info->mach;
2617 /* Find a candidate among the list of architectures we've created
2619 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2621 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2622 return arches->gdbarch;
2624 tdep = XCNEW (struct gdbarch_tdep);
2625 gdbarch = gdbarch_alloc (&info, tdep);
2627 /* Essential types. */
2628 make_types (gdbarch);
2630 /* Address/pointer conversions. */
2631 if (mach == bfd_mach_m16c)
2633 set_gdbarch_address_to_pointer (gdbarch, m32c_m16c_address_to_pointer);
2634 set_gdbarch_pointer_to_address (gdbarch, m32c_m16c_pointer_to_address);
2638 make_regs (gdbarch);
2641 set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32c_breakpoint::kind_from_pc);
2642 set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32c_breakpoint::bp_from_kind);
2644 /* Prologue analysis and unwinding. */
2645 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2646 set_gdbarch_skip_prologue (gdbarch, m32c_skip_prologue);
2647 set_gdbarch_unwind_pc (gdbarch, m32c_unwind_pc);
2648 set_gdbarch_unwind_sp (gdbarch, m32c_unwind_sp);
2650 /* I'm dropping the dwarf2 sniffer because it has a few problems.
2651 They may be in the dwarf2 cfi code in GDB, or they may be in
2652 the debug info emitted by the upstream toolchain. I don't
2653 know which, but I do know that the prologue analyzer works better.
2655 dwarf2_append_sniffers (gdbarch);
2657 frame_unwind_append_unwinder (gdbarch, &m32c_unwind);
2659 /* Inferior calls. */
2660 set_gdbarch_push_dummy_call (gdbarch, m32c_push_dummy_call);
2661 set_gdbarch_return_value (gdbarch, m32c_return_value);
2662 set_gdbarch_dummy_id (gdbarch, m32c_dummy_id);
2665 set_gdbarch_skip_trampoline_code (gdbarch, m32c_skip_trampoline_code);
2667 set_gdbarch_virtual_frame_pointer (gdbarch, m32c_virtual_frame_pointer);
2669 /* m32c function boundary addresses are not necessarily even.
2670 Therefore, the `vbit', which indicates a pointer to a virtual
2671 member function, is stored in the delta field, rather than as
2672 the low bit of a function pointer address.
2674 In order to verify this, see the definition of
2675 TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the
2676 definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */
2677 set_gdbarch_vbit_in_delta (gdbarch, 1);
2683 _initialize_m32c_tdep (void)
2685 register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init);
2687 m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP);