1 /* Functions specific to running gdb native on IA-64 running
4 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
5 2009, 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb_string.h"
28 #include "ia64-tdep.h"
29 #include "linux-nat.h"
32 #include <sys/ptrace.h>
37 #include <sys/syscall.h>
40 #include <asm/ptrace_offsets.h>
41 #include <sys/procfs.h>
43 /* Prototypes for supply_gregset etc. */
46 /* These must match the order of the register names.
48 Some sort of lookup table is needed because the offsets associated
49 with the registers are all over the board. */
51 static int u_offsets[] =
53 /* general registers */
54 -1, /* gr0 not available; i.e, it's always zero. */
86 /* gr32 through gr127 not directly available via the ptrace interface. */
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 /* Floating point registers */
94 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
221 /* Predicate registers - we don't fetch these individually. */
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 -1, -1, -1, -1, -1, -1, -1, -1,
230 /* branch registers */
239 /* Virtual frame pointer and virtual return address pointer. */
241 /* other registers */
244 PT_CR_IPSR, /* psr */
246 /* kernel registers not visible via ptrace interface (?) */
247 -1, -1, -1, -1, -1, -1, -1, -1,
249 -1, -1, -1, -1, -1, -1, -1, -1,
255 -1, /* Not available: FCR, IA32 floating control register. */
257 -1, /* Not available: EFLAG */
258 -1, /* Not available: CSD */
259 -1, /* Not available: SSD */
260 -1, /* Not available: CFLG */
261 -1, /* Not available: FSR */
262 -1, /* Not available: FIR */
263 -1, /* Not available: FDR */
271 -1, /* Not available: ITC */
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, /* Not available: EC, the Epilog Count register. */
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
284 /* nat bits - not fetched directly; instead we obtain these bits from
285 either rnat or unat or from memory. */
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 -1, -1, -1, -1, -1, -1, -1, -1,
305 ia64_register_addr (struct gdbarch *gdbarch, int regno)
309 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
310 error (_("Invalid register number %d."), regno);
312 if (u_offsets[regno] == -1)
315 addr = (CORE_ADDR) u_offsets[regno];
321 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
324 || regno >= gdbarch_num_regs (gdbarch)
325 || u_offsets[regno] == -1;
329 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
331 /* Rationale behind not permitting stores to bspstore...
333 The IA-64 architecture provides bspstore and bsp which refer
334 memory locations in the RSE's backing store. bspstore is the
335 next location which will be written when the RSE needs to write
336 to memory. bsp is the address at which r32 in the current frame
337 would be found if it were written to the backing store.
339 The IA-64 architecture provides read-only access to bsp and
340 read/write access to bspstore (but only when the RSE is in
341 the enforced lazy mode). It should be noted that stores
342 to bspstore also affect the value of bsp. Changing bspstore
343 does not affect the number of dirty entries between bspstore
344 and bsp, so changing bspstore by N words will also cause bsp
345 to be changed by (roughly) N as well. (It could be N-1 or N+1
346 depending upon where the NaT collection bits fall.)
348 OTOH, the Linux kernel provides read/write access to bsp (and
349 currently read/write access to bspstore as well). But it
350 is definitely the case that if you change one, the other
351 will change at the same time. It is more useful to gdb to
352 be able to change bsp. So in order to prevent strange and
353 undesirable things from happening when a dummy stack frame
354 is popped (after calling an inferior function), we allow
355 bspstore to be read, but not written. (Note that popping
356 a (generic) dummy stack frame causes all registers that
357 were previously read from the inferior process to be written
361 || regno >= gdbarch_num_regs (gdbarch)
362 || u_offsets[regno] == -1
363 || regno == IA64_BSPSTORE_REGNUM;
367 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
370 const greg_t *regp = (const greg_t *) gregsetp;
372 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
374 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
377 /* FIXME: NAT collection bits are at index 32; gotta deal with these
380 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
382 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
384 regcache_raw_supply (regcache, regi,
385 regp + 34 + (regi - IA64_BR0_REGNUM));
388 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
389 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
390 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
391 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
392 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
393 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
394 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
395 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
396 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
397 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
398 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
399 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
400 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
404 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
407 greg_t *regp = (greg_t *) gregsetp;
409 #define COPY_REG(_idx_,_regi_) \
410 if ((regno == -1) || regno == _regi_) \
411 regcache_raw_collect (regcache, _regi_, regp + _idx_)
413 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
415 COPY_REG (regi - IA64_GR0_REGNUM, regi);
418 /* FIXME: NAT collection bits at index 32? */
420 COPY_REG (33, IA64_PR_REGNUM);
422 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
424 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
427 COPY_REG (42, IA64_IP_REGNUM);
428 COPY_REG (43, IA64_CFM_REGNUM);
429 COPY_REG (44, IA64_PSR_REGNUM);
430 COPY_REG (45, IA64_RSC_REGNUM);
431 COPY_REG (46, IA64_BSP_REGNUM);
432 COPY_REG (47, IA64_BSPSTORE_REGNUM);
433 COPY_REG (48, IA64_RNAT_REGNUM);
434 COPY_REG (49, IA64_CCV_REGNUM);
435 COPY_REG (50, IA64_UNAT_REGNUM);
436 COPY_REG (51, IA64_FPSR_REGNUM);
437 COPY_REG (52, IA64_PFS_REGNUM);
438 COPY_REG (53, IA64_LC_REGNUM);
439 COPY_REG (54, IA64_EC_REGNUM);
442 /* Given a pointer to a floating point register set in /proc format
443 (fpregset_t *), unpack the register contents and supply them as gdb's
444 idea of the current floating point register values. */
447 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
452 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
454 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
455 regcache_raw_supply (regcache, regi, from);
459 /* Given a pointer to a floating point register set in /proc format
460 (fpregset_t *), update the register specified by REGNO from gdb's idea
461 of the current floating point register set. If REGNO is -1, update
465 fill_fpregset (const struct regcache *regcache,
466 fpregset_t *fpregsetp, int regno)
470 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
472 if ((regno == -1) || (regno == regi))
473 regcache_raw_collect (regcache, regi,
474 &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
478 #define IA64_PSR_DB (1UL << 24)
479 #define IA64_PSR_DD (1UL << 39)
482 enable_watchpoints_in_psr (ptid_t ptid)
484 struct regcache *regcache = get_thread_regcache (ptid);
487 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
488 if (!(psr & IA64_PSR_DB))
490 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
491 watchpoints and breakpoints. */
492 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
496 static long debug_registers[8];
499 store_debug_register (ptid_t ptid, int idx, long val)
507 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
511 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
515 store_debug_register (ptid, 2 * idx, *dbr_addr);
517 store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
521 is_power_of_2 (int val)
526 for (i = 0; i < 8 * sizeof (val); i++)
530 return onecount <= 1;
534 ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw,
535 struct expression *cond)
539 long dbr_addr, dbr_mask;
540 int max_watchpoints = 4;
542 if (len <= 0 || !is_power_of_2 (len))
545 for (idx = 0; idx < max_watchpoints; idx++)
547 dbr_mask = debug_registers[idx * 2 + 1];
548 if ((dbr_mask & (0x3UL << 62)) == 0)
550 /* Exit loop if both r and w bits clear. */
555 if (idx == max_watchpoints)
558 dbr_addr = (long) addr;
559 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
560 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
564 dbr_mask |= (1L << 62); /* Set w bit */
567 dbr_mask |= (1L << 63); /* Set r bit */
570 dbr_mask |= (3L << 62); /* Set both r and w bits */
576 debug_registers[2 * idx] = dbr_addr;
577 debug_registers[2 * idx + 1] = dbr_mask;
580 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
581 enable_watchpoints_in_psr (lp->ptid);
588 ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
589 struct expression *cond)
592 long dbr_addr, dbr_mask;
593 int max_watchpoints = 4;
595 if (len <= 0 || !is_power_of_2 (len))
598 for (idx = 0; idx < max_watchpoints; idx++)
600 dbr_addr = debug_registers[2 * idx];
601 dbr_mask = debug_registers[2 * idx + 1];
602 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
606 debug_registers[2 * idx] = 0;
607 debug_registers[2 * idx + 1] = 0;
612 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
621 ia64_linux_new_thread (struct lwp_info *lp)
626 for (i = 0; i < 8; i++)
628 if (debug_registers[i] != 0)
630 store_debug_register (lp->ptid, i, debug_registers[i]);
634 enable_watchpoints_in_psr (lp->ptid);
638 ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
641 struct siginfo *siginfo_p;
642 struct regcache *regcache = get_current_regcache ();
644 siginfo_p = linux_nat_get_siginfo (inferior_ptid);
646 if (siginfo_p->si_signo != SIGTRAP
647 || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
650 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
651 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
652 for the next instruction. */
653 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
655 *addr_p = (CORE_ADDR)siginfo_p->si_addr;
660 ia64_linux_stopped_by_watchpoint (void)
663 return ia64_linux_stopped_data_address (¤t_target, &addr);
667 ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
673 /* Fetch register REGNUM from the inferior. */
676 ia64_linux_fetch_register (struct regcache *regcache, int regnum)
678 struct gdbarch *gdbarch = get_regcache_arch (regcache);
681 PTRACE_TYPE_RET *buf;
684 if (ia64_cannot_fetch_register (gdbarch, regnum))
686 regcache_raw_supply (regcache, regnum, NULL);
690 /* Cater for systems like GNU/Linux, that implement threads as
691 separate processes. */
692 pid = ptid_get_lwp (inferior_ptid);
694 pid = ptid_get_pid (inferior_ptid);
696 /* This isn't really an address, but ptrace thinks of it as one. */
697 addr = ia64_register_addr (gdbarch, regnum);
698 size = register_size (gdbarch, regnum);
700 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
703 /* Read the register contents from the inferior a chunk at a time. */
704 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
707 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
709 error (_("Couldn't read register %s (#%d): %s."),
710 gdbarch_register_name (gdbarch, regnum),
711 regnum, safe_strerror (errno));
713 addr += sizeof (PTRACE_TYPE_RET);
715 regcache_raw_supply (regcache, regnum, buf);
718 /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
719 for all registers. */
722 ia64_linux_fetch_registers (struct target_ops *ops,
723 struct regcache *regcache, int regnum)
727 regnum < gdbarch_num_regs (get_regcache_arch (regcache));
729 ia64_linux_fetch_register (regcache, regnum);
731 ia64_linux_fetch_register (regcache, regnum);
734 /* Store register REGNUM into the inferior. */
737 ia64_linux_store_register (const struct regcache *regcache, int regnum)
739 struct gdbarch *gdbarch = get_regcache_arch (regcache);
742 PTRACE_TYPE_RET *buf;
745 if (ia64_cannot_store_register (gdbarch, regnum))
748 /* Cater for systems like GNU/Linux, that implement threads as
749 separate processes. */
750 pid = ptid_get_lwp (inferior_ptid);
752 pid = ptid_get_pid (inferior_ptid);
754 /* This isn't really an address, but ptrace thinks of it as one. */
755 addr = ia64_register_addr (gdbarch, regnum);
756 size = register_size (gdbarch, regnum);
758 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
761 /* Write the register contents into the inferior a chunk at a time. */
762 regcache_raw_collect (regcache, regnum, buf);
763 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
766 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
768 error (_("Couldn't write register %s (#%d): %s."),
769 gdbarch_register_name (gdbarch, regnum),
770 regnum, safe_strerror (errno));
772 addr += sizeof (PTRACE_TYPE_RET);
776 /* Store register REGNUM back into the inferior. If REGNUM is -1, do
777 this for all registers. */
780 ia64_linux_store_registers (struct target_ops *ops,
781 struct regcache *regcache, int regnum)
785 regnum < gdbarch_num_regs (get_regcache_arch (regcache));
787 ia64_linux_store_register (regcache, regnum);
789 ia64_linux_store_register (regcache, regnum);
793 static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
794 const char *, gdb_byte *,
795 const gdb_byte *, ULONGEST, LONGEST);
798 ia64_linux_xfer_partial (struct target_ops *ops,
799 enum target_object object,
801 gdb_byte *readbuf, const gdb_byte *writebuf,
802 ULONGEST offset, LONGEST len)
804 if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
805 return syscall (__NR_getunwind, readbuf, len);
807 return super_xfer_partial (ops, object, annex, readbuf, writebuf,
811 /* For break.b instruction ia64 CPU forgets the immediate value and generates
812 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
813 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
814 difference for the signals here. */
817 ia64_linux_status_is_event (int status)
819 return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
820 || WSTOPSIG (status) == SIGILL);
823 void _initialize_ia64_linux_nat (void);
826 _initialize_ia64_linux_nat (void)
828 struct target_ops *t;
830 /* Fill in the generic GNU/Linux methods. */
833 /* Override the default fetch/store register routines. */
834 t->to_fetch_registers = ia64_linux_fetch_registers;
835 t->to_store_registers = ia64_linux_store_registers;
837 /* Override the default to_xfer_partial. */
838 super_xfer_partial = t->to_xfer_partial;
839 t->to_xfer_partial = ia64_linux_xfer_partial;
841 /* Override watchpoint routines. */
843 /* The IA-64 architecture can step over a watch point (without triggering
844 it again) if the "dd" (data debug fault disable) bit in the processor
847 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
848 code there has determined that a hardware watchpoint has indeed
849 been hit. The CPU will then be able to execute one instruction
850 without triggering a watchpoint. */
852 t->to_have_steppable_watchpoint = 1;
853 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
854 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
855 t->to_stopped_data_address = ia64_linux_stopped_data_address;
856 t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
857 t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
859 /* Register the target. */
860 linux_nat_add_target (t);
861 linux_nat_set_new_thread (t, ia64_linux_new_thread);
862 linux_nat_set_status_is_event (t, ia64_linux_status_is_event);