1 /* Functions specific to running gdb native on IA-64 running
4 Copyright (C) 1999-2017 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "ia64-tdep.h"
27 #include "linux-nat.h"
30 #include "nat/gdb_ptrace.h"
35 #include <sys/syscall.h>
38 #include <asm/ptrace_offsets.h>
39 #include <sys/procfs.h>
41 /* Prototypes for supply_gregset etc. */
44 #include "inf-ptrace.h"
46 /* These must match the order of the register names.
48 Some sort of lookup table is needed because the offsets associated
49 with the registers are all over the board. */
51 static int u_offsets[] =
53 /* general registers */
54 -1, /* gr0 not available; i.e, it's always zero. */
86 /* gr32 through gr127 not directly available via the ptrace interface. */
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 /* Floating point registers */
94 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
221 /* Predicate registers - we don't fetch these individually. */
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 -1, -1, -1, -1, -1, -1, -1, -1,
230 /* branch registers */
239 /* Virtual frame pointer and virtual return address pointer. */
241 /* other registers */
244 PT_CR_IPSR, /* psr */
246 /* kernel registers not visible via ptrace interface (?) */
247 -1, -1, -1, -1, -1, -1, -1, -1,
249 -1, -1, -1, -1, -1, -1, -1, -1,
255 -1, /* Not available: FCR, IA32 floating control register. */
257 -1, /* Not available: EFLAG */
258 -1, /* Not available: CSD */
259 -1, /* Not available: SSD */
260 -1, /* Not available: CFLG */
261 -1, /* Not available: FSR */
262 -1, /* Not available: FIR */
263 -1, /* Not available: FDR */
271 -1, /* Not available: ITC */
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1,
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
284 /* nat bits - not fetched directly; instead we obtain these bits from
285 either rnat or unat or from memory. */
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 -1, -1, -1, -1, -1, -1, -1, -1,
305 ia64_register_addr (struct gdbarch *gdbarch, int regno)
309 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
310 error (_("Invalid register number %d."), regno);
312 if (u_offsets[regno] == -1)
315 addr = (CORE_ADDR) u_offsets[regno];
321 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
324 || regno >= gdbarch_num_regs (gdbarch)
325 || u_offsets[regno] == -1;
329 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
331 /* Rationale behind not permitting stores to bspstore...
333 The IA-64 architecture provides bspstore and bsp which refer
334 memory locations in the RSE's backing store. bspstore is the
335 next location which will be written when the RSE needs to write
336 to memory. bsp is the address at which r32 in the current frame
337 would be found if it were written to the backing store.
339 The IA-64 architecture provides read-only access to bsp and
340 read/write access to bspstore (but only when the RSE is in
341 the enforced lazy mode). It should be noted that stores
342 to bspstore also affect the value of bsp. Changing bspstore
343 does not affect the number of dirty entries between bspstore
344 and bsp, so changing bspstore by N words will also cause bsp
345 to be changed by (roughly) N as well. (It could be N-1 or N+1
346 depending upon where the NaT collection bits fall.)
348 OTOH, the Linux kernel provides read/write access to bsp (and
349 currently read/write access to bspstore as well). But it
350 is definitely the case that if you change one, the other
351 will change at the same time. It is more useful to gdb to
352 be able to change bsp. So in order to prevent strange and
353 undesirable things from happening when a dummy stack frame
354 is popped (after calling an inferior function), we allow
355 bspstore to be read, but not written. (Note that popping
356 a (generic) dummy stack frame causes all registers that
357 were previously read from the inferior process to be written
361 || regno >= gdbarch_num_regs (gdbarch)
362 || u_offsets[regno] == -1
363 || regno == IA64_BSPSTORE_REGNUM;
367 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
370 const greg_t *regp = (const greg_t *) gregsetp;
372 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
374 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
377 /* FIXME: NAT collection bits are at index 32; gotta deal with these
380 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
382 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
384 regcache_raw_supply (regcache, regi,
385 regp + 34 + (regi - IA64_BR0_REGNUM));
388 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
389 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
390 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
391 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
392 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
393 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
394 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
395 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
396 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
397 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
398 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
399 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
400 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
404 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
407 greg_t *regp = (greg_t *) gregsetp;
409 #define COPY_REG(_idx_,_regi_) \
410 if ((regno == -1) || regno == _regi_) \
411 regcache_raw_collect (regcache, _regi_, regp + _idx_)
413 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
415 COPY_REG (regi - IA64_GR0_REGNUM, regi);
418 /* FIXME: NAT collection bits at index 32? */
420 COPY_REG (33, IA64_PR_REGNUM);
422 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
424 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
427 COPY_REG (42, IA64_IP_REGNUM);
428 COPY_REG (43, IA64_CFM_REGNUM);
429 COPY_REG (44, IA64_PSR_REGNUM);
430 COPY_REG (45, IA64_RSC_REGNUM);
431 COPY_REG (46, IA64_BSP_REGNUM);
432 COPY_REG (47, IA64_BSPSTORE_REGNUM);
433 COPY_REG (48, IA64_RNAT_REGNUM);
434 COPY_REG (49, IA64_CCV_REGNUM);
435 COPY_REG (50, IA64_UNAT_REGNUM);
436 COPY_REG (51, IA64_FPSR_REGNUM);
437 COPY_REG (52, IA64_PFS_REGNUM);
438 COPY_REG (53, IA64_LC_REGNUM);
439 COPY_REG (54, IA64_EC_REGNUM);
442 /* Given a pointer to a floating point register set in /proc format
443 (fpregset_t *), unpack the register contents and supply them as gdb's
444 idea of the current floating point register values. */
447 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
451 const gdb_byte f_zero[16] = { 0 };
452 const gdb_byte f_one[16] =
453 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
455 /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs
456 did the same. So ignore whatever might be recorded in fpregset_t
457 for fr0/fr1 and always supply their expected values. */
459 /* fr0 is always read as zero. */
460 regcache_raw_supply (regcache, IA64_FR0_REGNUM, f_zero);
461 /* fr1 is always read as one (1.0). */
462 regcache_raw_supply (regcache, IA64_FR1_REGNUM, f_one);
464 for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
466 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
467 regcache_raw_supply (regcache, regi, from);
471 /* Given a pointer to a floating point register set in /proc format
472 (fpregset_t *), update the register specified by REGNO from gdb's idea
473 of the current floating point register set. If REGNO is -1, update
477 fill_fpregset (const struct regcache *regcache,
478 fpregset_t *fpregsetp, int regno)
482 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
484 if ((regno == -1) || (regno == regi))
485 regcache_raw_collect (regcache, regi,
486 &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
490 #define IA64_PSR_DB (1UL << 24)
491 #define IA64_PSR_DD (1UL << 39)
494 enable_watchpoints_in_psr (ptid_t ptid)
496 struct regcache *regcache = get_thread_regcache (ptid);
499 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
500 if (!(psr & IA64_PSR_DB))
502 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
503 watchpoints and breakpoints. */
504 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
508 static long debug_registers[8];
511 store_debug_register (ptid_t ptid, int idx, long val)
515 tid = ptid_get_lwp (ptid);
517 tid = ptid_get_pid (ptid);
519 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
523 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
527 store_debug_register (ptid, 2 * idx, *dbr_addr);
529 store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
533 is_power_of_2 (int val)
538 for (i = 0; i < 8 * sizeof (val); i++)
542 return onecount <= 1;
546 ia64_linux_insert_watchpoint (struct target_ops *self,
547 CORE_ADDR addr, int len,
548 enum target_hw_bp_type type,
549 struct expression *cond)
553 long dbr_addr, dbr_mask;
554 int max_watchpoints = 4;
556 if (len <= 0 || !is_power_of_2 (len))
559 for (idx = 0; idx < max_watchpoints; idx++)
561 dbr_mask = debug_registers[idx * 2 + 1];
562 if ((dbr_mask & (0x3UL << 62)) == 0)
564 /* Exit loop if both r and w bits clear. */
569 if (idx == max_watchpoints)
572 dbr_addr = (long) addr;
573 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
574 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
578 dbr_mask |= (1L << 62); /* Set w bit */
581 dbr_mask |= (1L << 63); /* Set r bit */
584 dbr_mask |= (3L << 62); /* Set both r and w bits */
590 debug_registers[2 * idx] = dbr_addr;
591 debug_registers[2 * idx + 1] = dbr_mask;
594 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
595 enable_watchpoints_in_psr (lp->ptid);
602 ia64_linux_remove_watchpoint (struct target_ops *self,
603 CORE_ADDR addr, int len,
604 enum target_hw_bp_type type,
605 struct expression *cond)
608 long dbr_addr, dbr_mask;
609 int max_watchpoints = 4;
611 if (len <= 0 || !is_power_of_2 (len))
614 for (idx = 0; idx < max_watchpoints; idx++)
616 dbr_addr = debug_registers[2 * idx];
617 dbr_mask = debug_registers[2 * idx + 1];
618 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
622 debug_registers[2 * idx] = 0;
623 debug_registers[2 * idx + 1] = 0;
628 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
637 ia64_linux_new_thread (struct lwp_info *lp)
642 for (i = 0; i < 8; i++)
644 if (debug_registers[i] != 0)
646 store_debug_register (lp->ptid, i, debug_registers[i]);
650 enable_watchpoints_in_psr (lp->ptid);
654 ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
658 struct regcache *regcache = get_current_regcache ();
660 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
663 if (siginfo.si_signo != SIGTRAP
664 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
667 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
668 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
669 for the next instruction. */
670 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
672 *addr_p = (CORE_ADDR) siginfo.si_addr;
677 ia64_linux_stopped_by_watchpoint (struct target_ops *ops)
680 return ia64_linux_stopped_data_address (ops, &addr);
684 ia64_linux_can_use_hw_breakpoint (struct target_ops *self,
686 int cnt, int othertype)
692 /* Fetch register REGNUM from the inferior. */
695 ia64_linux_fetch_register (struct regcache *regcache, int regnum)
697 struct gdbarch *gdbarch = regcache->arch ();
700 PTRACE_TYPE_RET *buf;
704 /* r0 cannot be fetched but is always zero. */
705 if (regnum == IA64_GR0_REGNUM)
707 const gdb_byte zero[8] = { 0 };
709 gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
710 regcache_raw_supply (regcache, regnum, zero);
714 /* fr0 cannot be fetched but is always zero. */
715 if (regnum == IA64_FR0_REGNUM)
717 const gdb_byte f_zero[16] = { 0 };
719 gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum));
720 regcache_raw_supply (regcache, regnum, f_zero);
724 /* fr1 cannot be fetched but is always one (1.0). */
725 if (regnum == IA64_FR1_REGNUM)
727 const gdb_byte f_one[16] =
728 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
730 gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
731 regcache_raw_supply (regcache, regnum, f_one);
735 if (ia64_cannot_fetch_register (gdbarch, regnum))
737 regcache_raw_supply (regcache, regnum, NULL);
741 pid = get_ptrace_pid (regcache_get_ptid (regcache));
743 /* This isn't really an address, but ptrace thinks of it as one. */
744 addr = ia64_register_addr (gdbarch, regnum);
745 size = register_size (gdbarch, regnum);
747 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
748 buf = (PTRACE_TYPE_RET *) alloca (size);
750 /* Read the register contents from the inferior a chunk at a time. */
751 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
754 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
756 error (_("Couldn't read register %s (#%d): %s."),
757 gdbarch_register_name (gdbarch, regnum),
758 regnum, safe_strerror (errno));
760 addr += sizeof (PTRACE_TYPE_RET);
762 regcache_raw_supply (regcache, regnum, buf);
765 /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
766 for all registers. */
769 ia64_linux_fetch_registers (struct target_ops *ops,
770 struct regcache *regcache, int regnum)
774 regnum < gdbarch_num_regs (regcache->arch ());
776 ia64_linux_fetch_register (regcache, regnum);
778 ia64_linux_fetch_register (regcache, regnum);
781 /* Store register REGNUM into the inferior. */
784 ia64_linux_store_register (const struct regcache *regcache, int regnum)
786 struct gdbarch *gdbarch = regcache->arch ();
789 PTRACE_TYPE_RET *buf;
793 if (ia64_cannot_store_register (gdbarch, regnum))
796 pid = get_ptrace_pid (regcache_get_ptid (regcache));
798 /* This isn't really an address, but ptrace thinks of it as one. */
799 addr = ia64_register_addr (gdbarch, regnum);
800 size = register_size (gdbarch, regnum);
802 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
803 buf = (PTRACE_TYPE_RET *) alloca (size);
805 /* Write the register contents into the inferior a chunk at a time. */
806 regcache_raw_collect (regcache, regnum, buf);
807 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
810 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
812 error (_("Couldn't write register %s (#%d): %s."),
813 gdbarch_register_name (gdbarch, regnum),
814 regnum, safe_strerror (errno));
816 addr += sizeof (PTRACE_TYPE_RET);
820 /* Store register REGNUM back into the inferior. If REGNUM is -1, do
821 this for all registers. */
824 ia64_linux_store_registers (struct target_ops *ops,
825 struct regcache *regcache, int regnum)
829 regnum < gdbarch_num_regs (regcache->arch ());
831 ia64_linux_store_register (regcache, regnum);
833 ia64_linux_store_register (regcache, regnum);
837 static target_xfer_partial_ftype *super_xfer_partial;
839 /* Implement the to_xfer_partial target_ops method. */
841 static enum target_xfer_status
842 ia64_linux_xfer_partial (struct target_ops *ops,
843 enum target_object object,
845 gdb_byte *readbuf, const gdb_byte *writebuf,
846 ULONGEST offset, ULONGEST len,
847 ULONGEST *xfered_len)
849 if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL)
851 static long gate_table_size;
855 /* Probe for the table size once. */
856 if (gate_table_size == 0)
857 gate_table_size = syscall (__NR_getunwind, NULL, 0);
858 if (gate_table_size < 0)
859 return TARGET_XFER_E_IO;
861 if (offset >= gate_table_size)
862 return TARGET_XFER_EOF;
864 tmp_buf = (gdb_byte *) alloca (gate_table_size);
865 res = syscall (__NR_getunwind, tmp_buf, gate_table_size);
867 return TARGET_XFER_E_IO;
868 gdb_assert (res == gate_table_size);
870 if (offset + len > gate_table_size)
871 len = gate_table_size - offset;
873 memcpy (readbuf, tmp_buf + offset, len);
875 return TARGET_XFER_OK;
878 return super_xfer_partial (ops, object, annex, readbuf, writebuf,
879 offset, len, xfered_len);
882 /* For break.b instruction ia64 CPU forgets the immediate value and generates
883 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
884 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
885 difference for the signals here. */
888 ia64_linux_status_is_event (int status)
890 return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
891 || WSTOPSIG (status) == SIGILL);
895 _initialize_ia64_linux_nat (void)
897 struct target_ops *t;
899 /* Fill in the generic GNU/Linux methods. */
902 /* Override the default fetch/store register routines. */
903 t->to_fetch_registers = ia64_linux_fetch_registers;
904 t->to_store_registers = ia64_linux_store_registers;
906 /* Override the default to_xfer_partial. */
907 super_xfer_partial = t->to_xfer_partial;
908 t->to_xfer_partial = ia64_linux_xfer_partial;
910 /* Override watchpoint routines. */
912 /* The IA-64 architecture can step over a watch point (without triggering
913 it again) if the "dd" (data debug fault disable) bit in the processor
916 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
917 code there has determined that a hardware watchpoint has indeed
918 been hit. The CPU will then be able to execute one instruction
919 without triggering a watchpoint. */
921 t->to_have_steppable_watchpoint = 1;
922 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
923 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
924 t->to_stopped_data_address = ia64_linux_stopped_data_address;
925 t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
926 t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
928 /* Register the target. */
929 linux_nat_add_target (t);
930 linux_nat_set_new_thread (t, ia64_linux_new_thread);
931 linux_nat_set_status_is_event (t, ia64_linux_status_is_event);