1 /* Intel 387 floating point stuff.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "floatformat.h"
32 #include "i386-tdep.h"
33 #include "i387-tdep.h"
34 #include "i386-xstate.h"
36 /* Print the floating point number specified by RAW. */
39 print_i387_value (struct gdbarch *gdbarch,
40 const gdb_byte *raw, struct ui_file *file)
44 /* Using extract_typed_floating here might affect the representation
45 of certain numbers such as NaNs, even if GDB is running natively.
46 This is fine since our caller already detects such special
47 numbers and we print the hexadecimal representation anyway. */
48 value = extract_typed_floating (raw, i387_ext_type (gdbarch));
50 /* We try to print 19 digits. The last digit may or may not contain
51 garbage, but we'd better print one too many. We need enough room
52 to print the value, 1 position for the sign, 1 for the decimal
53 point, 19 for the digits and 6 for the exponent adds up to 27. */
54 #ifdef PRINTF_HAS_LONG_DOUBLE
55 fprintf_filtered (file, " %-+27.19Lg", (long double) value);
57 fprintf_filtered (file, " %-+27.19g", (double) value);
61 /* Print the classification for the register contents RAW. */
64 print_i387_ext (struct gdbarch *gdbarch,
65 const gdb_byte *raw, struct ui_file *file)
69 unsigned int exponent;
70 unsigned long fraction[2];
73 integer = raw[7] & 0x80;
74 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
75 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
76 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
77 | (raw[5] << 8) | raw[4]);
79 if (exponent == 0x7fff && integer)
81 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
83 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
84 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
85 /* Real Indefinite (QNaN). */
86 fputs_unfiltered (" Real Indefinite (QNaN)", file);
87 else if (fraction[1] & 0x40000000)
89 fputs_filtered (" QNaN", file);
92 fputs_filtered (" SNaN", file);
94 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
96 print_i387_value (gdbarch, raw, file);
97 else if (exponent == 0x0000)
99 /* Denormal or zero. */
100 print_i387_value (gdbarch, raw, file);
103 /* Pseudo-denormal. */
104 fputs_filtered (" Pseudo-denormal", file);
105 else if (fraction[0] || fraction[1])
107 fputs_filtered (" Denormal", file);
111 fputs_filtered (" Unsupported", file);
114 /* Print the status word STATUS. If STATUS_P is false, then STATUS
118 print_i387_status_word (int status_p,
119 unsigned int status, struct ui_file *file)
121 fprintf_filtered (file, "Status Word: ");
124 fprintf_filtered (file, "%s\n", _("<unavailable>"));
128 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
129 fputs_filtered (" ", file);
130 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
131 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
132 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
133 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
134 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
135 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
136 fputs_filtered (" ", file);
137 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
138 fputs_filtered (" ", file);
139 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
140 fputs_filtered (" ", file);
141 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
142 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
143 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
144 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
146 fputs_filtered ("\n", file);
148 fprintf_filtered (file,
149 " TOP: %d\n", ((status >> 11) & 7));
152 /* Print the control word CONTROL. If CONTROL_P is false, then
153 CONTROL was unavailable. */
156 print_i387_control_word (int control_p,
157 unsigned int control, struct ui_file *file)
159 fprintf_filtered (file, "Control Word: ");
162 fprintf_filtered (file, "%s\n", _("<unavailable>"));
166 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
167 fputs_filtered (" ", file);
168 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
169 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
170 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
171 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
172 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
173 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
175 fputs_filtered ("\n", file);
177 fputs_filtered (" PC: ", file);
178 switch ((control >> 8) & 3)
181 fputs_filtered ("Single Precision (24-bits)\n", file);
184 fputs_filtered ("Reserved\n", file);
187 fputs_filtered ("Double Precision (53-bits)\n", file);
190 fputs_filtered ("Extended Precision (64-bits)\n", file);
194 fputs_filtered (" RC: ", file);
195 switch ((control >> 10) & 3)
198 fputs_filtered ("Round to nearest\n", file);
201 fputs_filtered ("Round down\n", file);
204 fputs_filtered ("Round up\n", file);
207 fputs_filtered ("Round toward zero\n", file);
212 /* Print out the i387 floating point state. Note that we ignore FRAME
213 in the code below. That's OK since floating-point registers are
214 never saved on the stack. */
217 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
218 struct frame_info *frame, const char *args)
220 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
240 gdb_assert (gdbarch == get_frame_arch (frame));
242 fctrl_p = read_frame_register_unsigned (frame,
243 I387_FCTRL_REGNUM (tdep), &fctrl);
244 fstat_p = read_frame_register_unsigned (frame,
245 I387_FSTAT_REGNUM (tdep), &fstat);
246 ftag_p = read_frame_register_unsigned (frame,
247 I387_FTAG_REGNUM (tdep), &ftag);
248 fiseg_p = read_frame_register_unsigned (frame,
249 I387_FISEG_REGNUM (tdep), &fiseg);
250 fioff_p = read_frame_register_unsigned (frame,
251 I387_FIOFF_REGNUM (tdep), &fioff);
252 foseg_p = read_frame_register_unsigned (frame,
253 I387_FOSEG_REGNUM (tdep), &foseg);
254 fooff_p = read_frame_register_unsigned (frame,
255 I387_FOOFF_REGNUM (tdep), &fooff);
256 fop_p = read_frame_register_unsigned (frame,
257 I387_FOP_REGNUM (tdep), &fop);
261 top = ((fstat >> 11) & 7);
263 for (fpreg = 7; fpreg >= 0; fpreg--)
265 struct value *regval;
270 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
274 tag = (ftag >> (fpreg * 2)) & 3;
279 fputs_filtered ("Valid ", file);
282 fputs_filtered ("Zero ", file);
285 fputs_filtered ("Special ", file);
288 fputs_filtered ("Empty ", file);
293 fputs_filtered ("Unknown ", file);
295 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
296 regval = get_frame_register_value (frame, regnum);
298 if (value_entirely_available (regval))
300 const gdb_byte *raw = value_contents (regval);
302 fputs_filtered ("0x", file);
303 for (i = 9; i >= 0; i--)
304 fprintf_filtered (file, "%02x", raw[i]);
306 if (tag != -1 && tag != 3)
307 print_i387_ext (gdbarch, raw, file);
310 fprintf_filtered (file, "%s", _("<unavailable>"));
312 fputs_filtered ("\n", file);
316 fputs_filtered ("\n", file);
317 print_i387_status_word (fstat_p, fstat, file);
318 print_i387_control_word (fctrl_p, fctrl, file);
319 fprintf_filtered (file, "Tag Word: %s\n",
320 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
321 fprintf_filtered (file, "Instruction Pointer: %s:",
322 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
323 fprintf_filtered (file, "%s\n",
324 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
325 fprintf_filtered (file, "Operand Pointer: %s:",
326 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
327 fprintf_filtered (file, "%s\n",
328 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
329 fprintf_filtered (file, "Opcode: %s\n",
331 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
332 : _("<unavailable>"));
336 /* Return nonzero if a value of type TYPE stored in register REGNUM
337 needs any special handling. */
340 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
343 if (i386_fp_regnum_p (gdbarch, regnum))
345 /* Floating point registers must be converted unless we are
346 accessing them in their hardware type. */
347 if (type == i387_ext_type (gdbarch))
356 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
357 return its contents in TO. */
360 i387_register_to_value (struct frame_info *frame, int regnum,
361 struct type *type, gdb_byte *to,
362 int *optimizedp, int *unavailablep)
364 struct gdbarch *gdbarch = get_frame_arch (frame);
365 gdb_byte from[I386_MAX_REGISTER_SIZE];
367 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
369 /* We only support floating-point values. */
370 if (TYPE_CODE (type) != TYPE_CODE_FLT)
372 warning (_("Cannot convert floating-point register value "
373 "to non-floating-point type."));
374 *optimizedp = *unavailablep = 0;
378 /* Convert to TYPE. */
379 if (!get_frame_register_bytes (frame, regnum, 0, TYPE_LENGTH (type),
380 from, optimizedp, unavailablep))
383 convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
384 *optimizedp = *unavailablep = 0;
388 /* Write the contents FROM of a value of type TYPE into register
389 REGNUM in frame FRAME. */
392 i387_value_to_register (struct frame_info *frame, int regnum,
393 struct type *type, const gdb_byte *from)
395 struct gdbarch *gdbarch = get_frame_arch (frame);
396 gdb_byte to[I386_MAX_REGISTER_SIZE];
398 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
400 /* We only support floating-point values. */
401 if (TYPE_CODE (type) != TYPE_CODE_FLT)
403 warning (_("Cannot convert non-floating-point type "
404 "to floating-point register value."));
408 /* Convert from TYPE. */
409 convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
410 put_frame_register (frame, regnum, to);
414 /* Handle FSAVE and FXSAVE formats. */
416 /* At fsave_offset[REGNUM] you'll find the offset to the location in
417 the data structure used by the "fsave" instruction where GDB
418 register REGNUM is stored. */
420 static int fsave_offset[] =
422 28 + 0 * 10, /* %st(0) ... */
429 28 + 7 * 10, /* ... %st(7). */
430 0, /* `fctrl' (16 bits). */
431 4, /* `fstat' (16 bits). */
432 8, /* `ftag' (16 bits). */
433 16, /* `fiseg' (16 bits). */
435 24, /* `foseg' (16 bits). */
437 18 /* `fop' (bottom 11 bits). */
440 #define FSAVE_ADDR(tdep, fsave, regnum) \
441 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
444 /* Fill register REGNUM in REGCACHE with the appropriate value from
445 *FSAVE. This function masks off any of the reserved bits in
449 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
451 struct gdbarch *gdbarch = get_regcache_arch (regcache);
452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
453 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
454 const gdb_byte *regs = fsave;
457 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
459 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
460 if (regnum == -1 || regnum == i)
464 regcache_raw_supply (regcache, i, NULL);
468 /* Most of the FPU control registers occupy only 16 bits in the
469 fsave area. Give those a special treatment. */
470 if (i >= I387_FCTRL_REGNUM (tdep)
471 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
475 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
477 if (i == I387_FOP_REGNUM (tdep))
478 val[1] &= ((1 << 3) - 1);
479 regcache_raw_supply (regcache, i, val);
482 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
485 /* Provide dummy values for the SSE registers. */
486 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
487 if (regnum == -1 || regnum == i)
488 regcache_raw_supply (regcache, i, NULL);
489 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
493 store_unsigned_integer (buf, 4, byte_order, 0x1f80);
494 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
498 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
499 with the value from REGCACHE. If REGNUM is -1, do this for all
500 registers. This function doesn't touch any of the reserved bits in
504 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
506 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
507 gdb_byte *regs = fsave;
510 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
512 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
513 if (regnum == -1 || regnum == i)
515 /* Most of the FPU control registers occupy only 16 bits in
516 the fsave area. Give those a special treatment. */
517 if (i >= I387_FCTRL_REGNUM (tdep)
518 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
522 regcache_raw_collect (regcache, i, buf);
524 if (i == I387_FOP_REGNUM (tdep))
526 /* The opcode occupies only 11 bits. Make sure we
527 don't touch the other bits. */
528 buf[1] &= ((1 << 3) - 1);
529 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
531 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
534 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
539 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
540 the data structure used by the "fxsave" instruction where GDB
541 register REGNUM is stored. */
543 static int fxsave_offset[] =
545 32, /* %st(0) through ... */
552 144, /* ... %st(7) (80 bits each). */
553 0, /* `fctrl' (16 bits). */
554 2, /* `fstat' (16 bits). */
555 4, /* `ftag' (16 bits). */
556 12, /* `fiseg' (16 bits). */
558 20, /* `foseg' (16 bits). */
560 6, /* `fop' (bottom 11 bits). */
561 160 + 0 * 16, /* %xmm0 through ... */
576 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
579 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
580 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
582 /* We made an unfortunate choice in putting %mxcsr after the SSE
583 registers %xmm0-%xmm7 instead of before, since it makes supporting
584 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
585 don't include the offset for %mxcsr here above. */
587 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
589 static int i387_tag (const gdb_byte *raw);
592 /* Fill register REGNUM in REGCACHE with the appropriate
593 floating-point or SSE register value from *FXSAVE. This function
594 masks off any of the reserved bits in *FXSAVE. */
597 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
599 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
600 const gdb_byte *regs = fxsave;
603 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
604 gdb_assert (tdep->num_xmm_regs > 0);
606 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
607 if (regnum == -1 || regnum == i)
611 regcache_raw_supply (regcache, i, NULL);
615 /* Most of the FPU control registers occupy only 16 bits in
616 the fxsave area. Give those a special treatment. */
617 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
618 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
622 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
624 if (i == I387_FOP_REGNUM (tdep))
625 val[1] &= ((1 << 3) - 1);
626 else if (i== I387_FTAG_REGNUM (tdep))
628 /* The fxsave area contains a simplified version of
629 the tag word. We have to look at the actual 80-bit
630 FP data to recreate the traditional i387 tag word. */
632 unsigned long ftag = 0;
636 top = ((FXSAVE_ADDR (tdep, regs,
637 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
640 for (fpreg = 7; fpreg >= 0; fpreg--)
644 if (val[0] & (1 << fpreg))
646 int thisreg = (fpreg + 8 - top) % 8
647 + I387_ST0_REGNUM (tdep);
648 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
653 ftag |= tag << (2 * fpreg);
655 val[0] = ftag & 0xff;
656 val[1] = (ftag >> 8) & 0xff;
658 regcache_raw_supply (regcache, i, val);
661 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
664 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
667 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
669 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
670 FXSAVE_MXCSR_ADDR (regs));
674 /* Fill register REGNUM (if it is a floating-point or SSE register) in
675 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
676 all registers. This function doesn't touch any of the reserved
680 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
682 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
683 gdb_byte *regs = fxsave;
686 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
687 gdb_assert (tdep->num_xmm_regs > 0);
689 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
690 if (regnum == -1 || regnum == i)
692 /* Most of the FPU control registers occupy only 16 bits in
693 the fxsave area. Give those a special treatment. */
694 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
695 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
699 regcache_raw_collect (regcache, i, buf);
701 if (i == I387_FOP_REGNUM (tdep))
703 /* The opcode occupies only 11 bits. Make sure we
704 don't touch the other bits. */
705 buf[1] &= ((1 << 3) - 1);
706 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
708 else if (i == I387_FTAG_REGNUM (tdep))
710 /* Converting back is much easier. */
715 ftag = (buf[1] << 8) | buf[0];
719 for (fpreg = 7; fpreg >= 0; fpreg--)
721 int tag = (ftag >> (fpreg * 2)) & 3;
724 buf[0] |= (1 << fpreg);
727 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
730 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
733 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
734 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
735 FXSAVE_MXCSR_ADDR (regs));
738 /* `xstate_bv' is at byte offset 512. */
739 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
741 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
742 the upper 128bit of AVX register data structure used by the "xsave"
743 instruction where GDB register REGNUM is stored. */
745 static int xsave_avxh_offset[] =
747 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
762 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
765 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
766 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
768 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
769 the upper 128bit of ZMM register data structure used by the "xsave"
770 instruction where GDB register REGNUM is stored. */
772 static int xsave_ymm_avx512_offset[] =
774 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
775 1664 + 16 + 0 * 64, /* %ymm16 through... */
790 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
793 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
794 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
796 static int xsave_xmm_avx512_offset[] =
798 1664 + 0 * 64, /* %ymm16 through... */
813 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
816 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
817 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
819 static int xsave_mpx_offset[] = {
820 960 + 0 * 16, /* bnd0r...bnd3r registers. */
824 1024 + 0 * 8, /* bndcfg ... bndstatus. */
828 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
829 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
831 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
832 of the AVX512 opmask register data structure used by the "xsave"
833 instruction where GDB register REGNUM is stored. */
835 static int xsave_avx512_k_offset[] =
837 1088 + 0 * 8, /* %k0 through... */
844 1088 + 7 * 8 /* %k7 (64 bits each). */
847 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
848 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
850 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
851 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
852 instruction where GDB register REGNUM is stored. */
854 static int xsave_avx512_zmm_h_offset[] =
857 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
871 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
872 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
887 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
890 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
891 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
893 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
896 i387_supply_xsave (struct regcache *regcache, int regnum,
899 struct gdbarch *gdbarch = get_regcache_arch (regcache);
900 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
901 const gdb_byte *regs = xsave;
903 unsigned int clear_bv;
904 static const gdb_byte zero[MAX_REGISTER_SIZE] = { 0 };
914 avx512_ymmh_avx512 = 0x40,
915 avx512_xmm_avx512 = 0x80,
916 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
917 | avx512_ymmh_avx512 | avx512_xmm_avx512
920 gdb_assert (regs != NULL);
921 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
922 gdb_assert (tdep->num_xmm_regs > 0);
926 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
927 && regnum < I387_ZMMENDH_REGNUM (tdep))
928 regclass = avx512_zmm_h;
929 else if (regnum >= I387_K0_REGNUM (tdep)
930 && regnum < I387_KEND_REGNUM (tdep))
932 else if (regnum >= I387_YMM16H_REGNUM (tdep)
933 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
934 regclass = avx512_ymmh_avx512;
935 else if (regnum >= I387_XMM16_REGNUM (tdep)
936 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
937 regclass = avx512_xmm_avx512;
938 else if (regnum >= I387_YMM0H_REGNUM (tdep)
939 && regnum < I387_YMMENDH_REGNUM (tdep))
941 else if (regnum >= I387_BND0R_REGNUM (tdep)
942 && regnum < I387_MPXEND_REGNUM (tdep))
944 else if (regnum >= I387_XMM0_REGNUM (tdep)
945 && regnum < I387_MXCSR_REGNUM (tdep))
947 else if (regnum >= I387_ST0_REGNUM (tdep)
948 && regnum < I387_FCTRL_REGNUM (tdep))
953 if (regclass != none)
955 /* Get `xstat_bv'. */
956 const gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
958 /* The supported bits in `xstat_bv' are 1 byte. Clear part in
959 vector registers if its bit in xstat_bv is zero. */
960 clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
963 clear_bv = I386_XSTATE_ALL_MASK;
965 /* With the delayed xsave mechanism, in between the program
966 starting, and the program accessing the vector registers for the
967 first time, the register's values are invalid. The kernel
968 initializes register states to zero when they are set the first
969 time in a program. This means that from the user-space programs'
970 perspective, it's the same as if the registers have always been
971 zero from the start of the program. Therefore, the debugger
972 should provide the same illusion to the user. */
980 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
981 regcache_raw_supply (regcache, regnum, zero);
983 regcache_raw_supply (regcache, regnum,
984 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
988 if ((clear_bv & I386_XSTATE_K))
989 regcache_raw_supply (regcache, regnum, zero);
991 regcache_raw_supply (regcache, regnum,
992 XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
995 case avx512_ymmh_avx512:
996 if ((clear_bv & I386_XSTATE_ZMM))
997 regcache_raw_supply (regcache, regnum, zero);
999 regcache_raw_supply (regcache, regnum,
1000 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1003 case avx512_xmm_avx512:
1004 if ((clear_bv & I386_XSTATE_ZMM))
1005 regcache_raw_supply (regcache, regnum, zero);
1007 regcache_raw_supply (regcache, regnum,
1008 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1012 if ((clear_bv & I386_XSTATE_AVX))
1013 regcache_raw_supply (regcache, regnum, zero);
1015 regcache_raw_supply (regcache, regnum,
1016 XSAVE_AVXH_ADDR (tdep, regs, regnum));
1020 if ((clear_bv & I386_XSTATE_BNDREGS))
1021 regcache_raw_supply (regcache, regnum, zero);
1023 regcache_raw_supply (regcache, regnum,
1024 XSAVE_MPX_ADDR (tdep, regs, regnum));
1028 if ((clear_bv & I386_XSTATE_SSE))
1029 regcache_raw_supply (regcache, regnum, zero);
1031 regcache_raw_supply (regcache, regnum,
1032 FXSAVE_ADDR (tdep, regs, regnum));
1036 if ((clear_bv & I386_XSTATE_X87))
1037 regcache_raw_supply (regcache, regnum, zero);
1039 regcache_raw_supply (regcache, regnum,
1040 FXSAVE_ADDR (tdep, regs, regnum));
1044 /* Handle the upper ZMM registers. */
1045 if ((tdep->xcr0 & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1047 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1049 for (i = I387_ZMM0H_REGNUM (tdep);
1050 i < I387_ZMMENDH_REGNUM (tdep);
1052 regcache_raw_supply (regcache, i, zero);
1056 for (i = I387_ZMM0H_REGNUM (tdep);
1057 i < I387_ZMMENDH_REGNUM (tdep);
1059 regcache_raw_supply (regcache, i,
1060 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1064 /* Handle AVX512 OpMask registers. */
1065 if ((tdep->xcr0 & I386_XSTATE_K))
1067 if ((clear_bv & I386_XSTATE_K))
1069 for (i = I387_K0_REGNUM (tdep);
1070 i < I387_KEND_REGNUM (tdep);
1072 regcache_raw_supply (regcache, i, zero);
1076 for (i = I387_K0_REGNUM (tdep);
1077 i < I387_KEND_REGNUM (tdep);
1079 regcache_raw_supply (regcache, i,
1080 XSAVE_AVX512_K_ADDR (tdep, regs, i));
1084 /* Handle the YMM_AVX512 registers. */
1085 if ((tdep->xcr0 & I386_XSTATE_ZMM))
1087 if ((clear_bv & I386_XSTATE_ZMM))
1089 for (i = I387_YMM16H_REGNUM (tdep);
1090 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1092 regcache_raw_supply (regcache, i, zero);
1093 for (i = I387_XMM16_REGNUM (tdep);
1094 i < I387_XMM_AVX512_END_REGNUM (tdep);
1096 regcache_raw_supply (regcache, i, zero);
1100 for (i = I387_YMM16H_REGNUM (tdep);
1101 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1103 regcache_raw_supply (regcache, i,
1104 XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1105 for (i = I387_XMM16_REGNUM (tdep);
1106 i < I387_XMM_AVX512_END_REGNUM (tdep);
1108 regcache_raw_supply (regcache, i,
1109 XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1112 /* Handle the upper YMM registers. */
1113 if ((tdep->xcr0 & I386_XSTATE_AVX))
1115 if ((clear_bv & I386_XSTATE_AVX))
1117 for (i = I387_YMM0H_REGNUM (tdep);
1118 i < I387_YMMENDH_REGNUM (tdep);
1120 regcache_raw_supply (regcache, i, zero);
1124 for (i = I387_YMM0H_REGNUM (tdep);
1125 i < I387_YMMENDH_REGNUM (tdep);
1127 regcache_raw_supply (regcache, i,
1128 XSAVE_AVXH_ADDR (tdep, regs, i));
1132 /* Handle the MPX registers. */
1133 if ((tdep->xcr0 & I386_XSTATE_BNDREGS))
1135 if (clear_bv & I386_XSTATE_BNDREGS)
1137 for (i = I387_BND0R_REGNUM (tdep);
1138 i < I387_BNDCFGU_REGNUM (tdep); i++)
1139 regcache_raw_supply (regcache, i, zero);
1143 for (i = I387_BND0R_REGNUM (tdep);
1144 i < I387_BNDCFGU_REGNUM (tdep); i++)
1145 regcache_raw_supply (regcache, i,
1146 XSAVE_MPX_ADDR (tdep, regs, i));
1150 /* Handle the MPX registers. */
1151 if ((tdep->xcr0 & I386_XSTATE_BNDCFG))
1153 if (clear_bv & I386_XSTATE_BNDCFG)
1155 for (i = I387_BNDCFGU_REGNUM (tdep);
1156 i < I387_MPXEND_REGNUM (tdep); i++)
1157 regcache_raw_supply (regcache, i, zero);
1161 for (i = I387_BNDCFGU_REGNUM (tdep);
1162 i < I387_MPXEND_REGNUM (tdep); i++)
1163 regcache_raw_supply (regcache, i,
1164 XSAVE_MPX_ADDR (tdep, regs, i));
1168 /* Handle the XMM registers. */
1169 if ((tdep->xcr0 & I386_XSTATE_SSE))
1171 if ((clear_bv & I386_XSTATE_SSE))
1173 for (i = I387_XMM0_REGNUM (tdep);
1174 i < I387_MXCSR_REGNUM (tdep);
1176 regcache_raw_supply (regcache, i, zero);
1180 for (i = I387_XMM0_REGNUM (tdep);
1181 i < I387_MXCSR_REGNUM (tdep); i++)
1182 regcache_raw_supply (regcache, i,
1183 FXSAVE_ADDR (tdep, regs, i));
1187 /* Handle the x87 registers. */
1188 if ((tdep->xcr0 & I386_XSTATE_X87))
1190 if ((clear_bv & I386_XSTATE_X87))
1192 for (i = I387_ST0_REGNUM (tdep);
1193 i < I387_FCTRL_REGNUM (tdep);
1195 regcache_raw_supply (regcache, i, zero);
1199 for (i = I387_ST0_REGNUM (tdep);
1200 i < I387_FCTRL_REGNUM (tdep);
1202 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1208 /* Only handle x87 control registers. */
1209 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1210 if (regnum == -1 || regnum == i)
1212 /* Most of the FPU control registers occupy only 16 bits in
1213 the xsave extended state. Give those a special treatment. */
1214 if (i != I387_FIOFF_REGNUM (tdep)
1215 && i != I387_FOOFF_REGNUM (tdep))
1219 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1220 val[2] = val[3] = 0;
1221 if (i == I387_FOP_REGNUM (tdep))
1222 val[1] &= ((1 << 3) - 1);
1223 else if (i== I387_FTAG_REGNUM (tdep))
1225 /* The fxsave area contains a simplified version of
1226 the tag word. We have to look at the actual 80-bit
1227 FP data to recreate the traditional i387 tag word. */
1229 unsigned long ftag = 0;
1233 top = ((FXSAVE_ADDR (tdep, regs,
1234 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1237 for (fpreg = 7; fpreg >= 0; fpreg--)
1241 if (val[0] & (1 << fpreg))
1243 int thisreg = (fpreg + 8 - top) % 8
1244 + I387_ST0_REGNUM (tdep);
1245 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1248 tag = 3; /* Empty */
1250 ftag |= tag << (2 * fpreg);
1252 val[0] = ftag & 0xff;
1253 val[1] = (ftag >> 8) & 0xff;
1255 regcache_raw_supply (regcache, i, val);
1258 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1261 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1262 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
1263 FXSAVE_MXCSR_ADDR (regs));
1266 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1269 i387_collect_xsave (const struct regcache *regcache, int regnum,
1270 void *xsave, int gcore)
1272 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1274 gdb_byte *regs = xsave;
1284 avx512_k = 0x20 | check,
1285 avx512_zmm_h = 0x40 | check,
1286 avx512_ymmh_avx512 = 0x80 | check,
1287 avx512_xmm_avx512 = 0x100 | check,
1288 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
1289 | avx512_ymmh_avx512 | avx512_xmm_avx512
1292 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1293 gdb_assert (tdep->num_xmm_regs > 0);
1297 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1298 && regnum < I387_ZMMENDH_REGNUM (tdep))
1299 regclass = avx512_zmm_h;
1300 else if (regnum >= I387_K0_REGNUM (tdep)
1301 && regnum < I387_KEND_REGNUM (tdep))
1302 regclass = avx512_k;
1303 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1304 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1305 regclass = avx512_ymmh_avx512;
1306 else if (regnum >= I387_XMM16_REGNUM (tdep)
1307 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1308 regclass = avx512_xmm_avx512;
1309 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1310 && regnum < I387_YMMENDH_REGNUM (tdep))
1312 else if (regnum >= I387_BND0R_REGNUM (tdep)
1313 && regnum < I387_MPXEND_REGNUM (tdep))
1315 else if (regnum >= I387_XMM0_REGNUM (tdep)
1316 && regnum < I387_MXCSR_REGNUM (tdep))
1318 else if (regnum >= I387_ST0_REGNUM (tdep)
1319 && regnum < I387_FCTRL_REGNUM (tdep))
1326 /* Clear XSAVE extended state. */
1327 memset (regs, 0, I386_XSTATE_SIZE (tdep->xcr0));
1329 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1330 if (tdep->xsave_xcr0_offset != -1)
1331 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1332 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1335 if ((regclass & check))
1337 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1338 gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
1339 unsigned int xstate_bv = 0;
1340 /* The supported bits in `xstat_bv' are 1 byte. */
1341 unsigned int clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
1344 /* Clear register set if its bit in xstat_bv is zero. */
1347 if ((clear_bv & I386_XSTATE_BNDREGS))
1348 for (i = I387_BND0R_REGNUM (tdep);
1349 i < I387_BNDCFGU_REGNUM (tdep); i++)
1350 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
1352 if ((clear_bv & I386_XSTATE_BNDCFG))
1353 for (i = I387_BNDCFGU_REGNUM (tdep);
1354 i < I387_MPXEND_REGNUM (tdep); i++)
1355 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
1357 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1358 for (i = I387_ZMM0H_REGNUM (tdep);
1359 i < I387_ZMMENDH_REGNUM (tdep); i++)
1360 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1362 if ((clear_bv & I386_XSTATE_K))
1363 for (i = I387_K0_REGNUM (tdep);
1364 i < I387_KEND_REGNUM (tdep); i++)
1365 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1367 if ((clear_bv & I386_XSTATE_ZMM))
1369 for (i = I387_YMM16H_REGNUM (tdep);
1370 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1371 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1372 for (i = I387_XMM16_REGNUM (tdep);
1373 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1374 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1377 if ((clear_bv & I386_XSTATE_AVX))
1378 for (i = I387_YMM0H_REGNUM (tdep);
1379 i < I387_YMMENDH_REGNUM (tdep); i++)
1380 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1382 if ((clear_bv & I386_XSTATE_SSE))
1383 for (i = I387_XMM0_REGNUM (tdep);
1384 i < I387_MXCSR_REGNUM (tdep); i++)
1385 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1387 if ((clear_bv & I386_XSTATE_X87))
1388 for (i = I387_ST0_REGNUM (tdep);
1389 i < I387_FCTRL_REGNUM (tdep); i++)
1390 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1393 if (regclass == all)
1395 /* Check if any ZMMH registers are changed. */
1396 if ((tdep->xcr0 & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1397 for (i = I387_ZMM0H_REGNUM (tdep);
1398 i < I387_ZMMENDH_REGNUM (tdep); i++)
1400 regcache_raw_collect (regcache, i, raw);
1401 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
1402 if (memcmp (raw, p, 32) != 0)
1404 xstate_bv |= (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM);
1405 memcpy (p, raw, 32);
1409 /* Check if any K registers are changed. */
1410 if ((tdep->xcr0 & I386_XSTATE_K))
1411 for (i = I387_K0_REGNUM (tdep);
1412 i < I387_KEND_REGNUM (tdep); i++)
1414 regcache_raw_collect (regcache, i, raw);
1415 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1416 if (memcmp (raw, p, 8) != 0)
1418 xstate_bv |= I386_XSTATE_K;
1423 /* Check if any XMM or upper YMM registers are changed. */
1424 if ((tdep->xcr0 & I386_XSTATE_ZMM))
1426 for (i = I387_YMM16H_REGNUM (tdep);
1427 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1429 regcache_raw_collect (regcache, i, raw);
1430 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1431 if (memcmp (raw, p, 16) != 0)
1433 xstate_bv |= I386_XSTATE_ZMM;
1434 memcpy (p, raw, 16);
1437 for (i = I387_XMM16_REGNUM (tdep);
1438 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1440 regcache_raw_collect (regcache, i, raw);
1441 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1442 if (memcmp (raw, p, 16) != 0)
1444 xstate_bv |= I386_XSTATE_ZMM;
1445 memcpy (p, raw, 16);
1450 /* Check if any upper YMM registers are changed. */
1451 if ((tdep->xcr0 & I386_XSTATE_AVX))
1452 for (i = I387_YMM0H_REGNUM (tdep);
1453 i < I387_YMMENDH_REGNUM (tdep); i++)
1455 regcache_raw_collect (regcache, i, raw);
1456 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1457 if (memcmp (raw, p, 16))
1459 xstate_bv |= I386_XSTATE_AVX;
1460 memcpy (p, raw, 16);
1463 /* Check if any upper MPX registers are changed. */
1464 if ((tdep->xcr0 & I386_XSTATE_BNDREGS))
1465 for (i = I387_BND0R_REGNUM (tdep);
1466 i < I387_BNDCFGU_REGNUM (tdep); i++)
1468 regcache_raw_collect (regcache, i, raw);
1469 p = XSAVE_MPX_ADDR (tdep, regs, i);
1470 if (memcmp (raw, p, 16))
1472 xstate_bv |= I386_XSTATE_BNDREGS;
1473 memcpy (p, raw, 16);
1477 /* Check if any upper MPX registers are changed. */
1478 if ((tdep->xcr0 & I386_XSTATE_BNDCFG))
1479 for (i = I387_BNDCFGU_REGNUM (tdep);
1480 i < I387_MPXEND_REGNUM (tdep); i++)
1482 regcache_raw_collect (regcache, i, raw);
1483 p = XSAVE_MPX_ADDR (tdep, regs, i);
1484 if (memcmp (raw, p, 8))
1486 xstate_bv |= I386_XSTATE_BNDCFG;
1491 /* Check if any SSE registers are changed. */
1492 if ((tdep->xcr0 & I386_XSTATE_SSE))
1493 for (i = I387_XMM0_REGNUM (tdep);
1494 i < I387_MXCSR_REGNUM (tdep); i++)
1496 regcache_raw_collect (regcache, i, raw);
1497 p = FXSAVE_ADDR (tdep, regs, i);
1498 if (memcmp (raw, p, 16))
1500 xstate_bv |= I386_XSTATE_SSE;
1501 memcpy (p, raw, 16);
1505 /* Check if any X87 registers are changed. */
1506 if ((tdep->xcr0 & I386_XSTATE_X87))
1507 for (i = I387_ST0_REGNUM (tdep);
1508 i < I387_FCTRL_REGNUM (tdep); i++)
1510 regcache_raw_collect (regcache, i, raw);
1511 p = FXSAVE_ADDR (tdep, regs, i);
1512 if (memcmp (raw, p, 10))
1514 xstate_bv |= I386_XSTATE_X87;
1515 memcpy (p, raw, 10);
1521 /* Check if REGNUM is changed. */
1522 regcache_raw_collect (regcache, regnum, raw);
1527 internal_error (__FILE__, __LINE__,
1528 _("invalid i387 regclass"));
1531 /* This is a ZMM register. */
1532 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
1533 if (memcmp (raw, p, 32) != 0)
1535 xstate_bv |= (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM);
1536 memcpy (p, raw, 32);
1540 /* This is a AVX512 mask register. */
1541 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1542 if (memcmp (raw, p, 8) != 0)
1544 xstate_bv |= I386_XSTATE_K;
1549 case avx512_ymmh_avx512:
1550 /* This is an upper YMM16-31 register. */
1551 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1552 if (memcmp (raw, p, 16) != 0)
1554 xstate_bv |= I386_XSTATE_ZMM;
1555 memcpy (p, raw, 16);
1559 case avx512_xmm_avx512:
1560 /* This is an upper XMM16-31 register. */
1561 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1562 if (memcmp (raw, p, 16) != 0)
1564 xstate_bv |= I386_XSTATE_ZMM;
1565 memcpy (p, raw, 16);
1570 /* This is an upper YMM register. */
1571 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1572 if (memcmp (raw, p, 16))
1574 xstate_bv |= I386_XSTATE_AVX;
1575 memcpy (p, raw, 16);
1580 if (regnum < I387_BNDCFGU_REGNUM (tdep))
1582 regcache_raw_collect (regcache, regnum, raw);
1583 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1584 if (memcmp (raw, p, 16))
1586 xstate_bv |= I386_XSTATE_BNDREGS;
1587 memcpy (p, raw, 16);
1592 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1593 xstate_bv |= I386_XSTATE_BNDCFG;
1599 /* This is an SSE register. */
1600 p = FXSAVE_ADDR (tdep, regs, regnum);
1601 if (memcmp (raw, p, 16))
1603 xstate_bv |= I386_XSTATE_SSE;
1604 memcpy (p, raw, 16);
1609 /* This is an x87 register. */
1610 p = FXSAVE_ADDR (tdep, regs, regnum);
1611 if (memcmp (raw, p, 10))
1613 xstate_bv |= I386_XSTATE_X87;
1614 memcpy (p, raw, 10);
1620 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1621 registers are changed. */
1624 /* The supported bits in `xstat_bv' are 1 byte. */
1625 *xstate_bv_p |= (gdb_byte) xstate_bv;
1630 internal_error (__FILE__, __LINE__,
1631 _("invalid i387 regclass"));
1642 case avx512_ymmh_avx512:
1643 case avx512_xmm_avx512:
1644 /* Register REGNUM has been updated. Return. */
1650 /* Return if REGNUM isn't changed. */
1651 if (regclass != all)
1656 /* Only handle x87 control registers. */
1657 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1658 if (regnum == -1 || regnum == i)
1660 /* Most of the FPU control registers occupy only 16 bits in
1661 the xsave extended state. Give those a special treatment. */
1662 if (i != I387_FIOFF_REGNUM (tdep)
1663 && i != I387_FOOFF_REGNUM (tdep))
1667 regcache_raw_collect (regcache, i, buf);
1669 if (i == I387_FOP_REGNUM (tdep))
1671 /* The opcode occupies only 11 bits. Make sure we
1672 don't touch the other bits. */
1673 buf[1] &= ((1 << 3) - 1);
1674 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1676 else if (i == I387_FTAG_REGNUM (tdep))
1678 /* Converting back is much easier. */
1680 unsigned short ftag;
1683 ftag = (buf[1] << 8) | buf[0];
1687 for (fpreg = 7; fpreg >= 0; fpreg--)
1689 int tag = (ftag >> (fpreg * 2)) & 3;
1692 buf[0] |= (1 << fpreg);
1695 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
1698 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1701 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1702 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
1703 FXSAVE_MXCSR_ADDR (regs));
1706 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1710 i387_tag (const gdb_byte *raw)
1713 unsigned int exponent;
1714 unsigned long fraction[2];
1716 integer = raw[7] & 0x80;
1717 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1718 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1719 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1720 | (raw[5] << 8) | raw[4]);
1722 if (exponent == 0x7fff)
1727 else if (exponent == 0x0000)
1729 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1755 /* Prepare the FPU stack in REGCACHE for a function return. */
1758 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1760 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1763 /* Set the top of the floating-point register stack to 7. The
1764 actual value doesn't really matter, but 7 is what a normal
1765 function return would end up with if the program started out with
1766 a freshly initialized FPU. */
1767 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1769 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1771 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1772 floating-point register stack to 7, the appropriate value for the
1773 tag word is 0x3fff. */
1774 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);