1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
56 #include "features/i386/i386-avx-mpx.c"
57 #include "features/i386/i386-avx-avx512.c"
58 #include "features/i386/i386-avx-mpx-avx512-pku.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
74 static const char *i386_register_names[] =
76 "eax", "ecx", "edx", "ebx",
77 "esp", "ebp", "esi", "edi",
78 "eip", "eflags", "cs", "ss",
79 "ds", "es", "fs", "gs",
80 "st0", "st1", "st2", "st3",
81 "st4", "st5", "st6", "st7",
82 "fctrl", "fstat", "ftag", "fiseg",
83 "fioff", "foseg", "fooff", "fop",
84 "xmm0", "xmm1", "xmm2", "xmm3",
85 "xmm4", "xmm5", "xmm6", "xmm7",
89 static const char *i386_zmm_names[] =
91 "zmm0", "zmm1", "zmm2", "zmm3",
92 "zmm4", "zmm5", "zmm6", "zmm7"
95 static const char *i386_zmmh_names[] =
97 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
98 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
101 static const char *i386_k_names[] =
103 "k0", "k1", "k2", "k3",
104 "k4", "k5", "k6", "k7"
107 static const char *i386_ymm_names[] =
109 "ymm0", "ymm1", "ymm2", "ymm3",
110 "ymm4", "ymm5", "ymm6", "ymm7",
113 static const char *i386_ymmh_names[] =
115 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
116 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
119 static const char *i386_mpx_names[] =
121 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
124 static const char* i386_pkeys_names[] =
129 /* Register names for MPX pseudo-registers. */
131 static const char *i386_bnd_names[] =
133 "bnd0", "bnd1", "bnd2", "bnd3"
136 /* Register names for MMX pseudo-registers. */
138 static const char *i386_mmx_names[] =
140 "mm0", "mm1", "mm2", "mm3",
141 "mm4", "mm5", "mm6", "mm7"
144 /* Register names for byte pseudo-registers. */
146 static const char *i386_byte_names[] =
148 "al", "cl", "dl", "bl",
149 "ah", "ch", "dh", "bh"
152 /* Register names for word pseudo-registers. */
154 static const char *i386_word_names[] =
156 "ax", "cx", "dx", "bx",
160 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
161 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
162 we have 16 upper ZMM regs that have to be handled differently. */
164 const int num_lower_zmm_regs = 16;
169 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
172 int mm0_regnum = tdep->mm0_regnum;
177 regnum -= mm0_regnum;
178 return regnum >= 0 && regnum < tdep->num_mmx_regs;
184 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
188 regnum -= tdep->al_regnum;
189 return regnum >= 0 && regnum < tdep->num_byte_regs;
195 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
197 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
199 regnum -= tdep->ax_regnum;
200 return regnum >= 0 && regnum < tdep->num_word_regs;
203 /* Dword register? */
206 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
209 int eax_regnum = tdep->eax_regnum;
214 regnum -= eax_regnum;
215 return regnum >= 0 && regnum < tdep->num_dword_regs;
218 /* AVX512 register? */
221 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224 int zmm0h_regnum = tdep->zmm0h_regnum;
226 if (zmm0h_regnum < 0)
229 regnum -= zmm0h_regnum;
230 return regnum >= 0 && regnum < tdep->num_zmm_regs;
234 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
236 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
237 int zmm0_regnum = tdep->zmm0_regnum;
242 regnum -= zmm0_regnum;
243 return regnum >= 0 && regnum < tdep->num_zmm_regs;
247 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
250 int k0_regnum = tdep->k0_regnum;
256 return regnum >= 0 && regnum < I387_NUM_K_REGS;
260 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
262 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
263 int ymm0h_regnum = tdep->ymm0h_regnum;
265 if (ymm0h_regnum < 0)
268 regnum -= ymm0h_regnum;
269 return regnum >= 0 && regnum < tdep->num_ymm_regs;
275 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
277 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
278 int ymm0_regnum = tdep->ymm0_regnum;
283 regnum -= ymm0_regnum;
284 return regnum >= 0 && regnum < tdep->num_ymm_regs;
288 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
290 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
291 int ymm16h_regnum = tdep->ymm16h_regnum;
293 if (ymm16h_regnum < 0)
296 regnum -= ymm16h_regnum;
297 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
301 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
303 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
304 int ymm16_regnum = tdep->ymm16_regnum;
306 if (ymm16_regnum < 0)
309 regnum -= ymm16_regnum;
310 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
316 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
318 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
319 int bnd0_regnum = tdep->bnd0_regnum;
324 regnum -= bnd0_regnum;
325 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
331 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
336 if (num_xmm_regs == 0)
339 regnum -= I387_XMM0_REGNUM (tdep);
340 return regnum >= 0 && regnum < num_xmm_regs;
343 /* XMM_512 register? */
346 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
348 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
349 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
351 if (num_xmm_avx512_regs == 0)
354 regnum -= I387_XMM16_REGNUM (tdep);
355 return regnum >= 0 && regnum < num_xmm_avx512_regs;
359 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
361 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
363 if (I387_NUM_XMM_REGS (tdep) == 0)
366 return (regnum == I387_MXCSR_REGNUM (tdep));
372 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
374 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
376 if (I387_ST0_REGNUM (tdep) < 0)
379 return (I387_ST0_REGNUM (tdep) <= regnum
380 && regnum < I387_FCTRL_REGNUM (tdep));
384 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
386 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
388 if (I387_ST0_REGNUM (tdep) < 0)
391 return (I387_FCTRL_REGNUM (tdep) <= regnum
392 && regnum < I387_XMM0_REGNUM (tdep));
395 /* BNDr (raw) register? */
398 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
400 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
402 if (I387_BND0R_REGNUM (tdep) < 0)
405 regnum -= tdep->bnd0r_regnum;
406 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
409 /* BND control register? */
412 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
414 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416 if (I387_BNDCFGU_REGNUM (tdep) < 0)
419 regnum -= I387_BNDCFGU_REGNUM (tdep);
420 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
426 i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum)
428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
429 int pkru_regnum = tdep->pkru_regnum;
434 regnum -= pkru_regnum;
435 return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS;
438 /* Return the name of register REGNUM, or the empty string if it is
439 an anonymous register. */
442 i386_register_name (struct gdbarch *gdbarch, int regnum)
444 /* Hide the upper YMM registers. */
445 if (i386_ymmh_regnum_p (gdbarch, regnum))
448 /* Hide the upper YMM16-31 registers. */
449 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
452 /* Hide the upper ZMM registers. */
453 if (i386_zmmh_regnum_p (gdbarch, regnum))
456 return tdesc_register_name (gdbarch, regnum);
459 /* Return the name of register REGNUM. */
462 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
464 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
465 if (i386_bnd_regnum_p (gdbarch, regnum))
466 return i386_bnd_names[regnum - tdep->bnd0_regnum];
467 if (i386_mmx_regnum_p (gdbarch, regnum))
468 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
469 else if (i386_ymm_regnum_p (gdbarch, regnum))
470 return i386_ymm_names[regnum - tdep->ymm0_regnum];
471 else if (i386_zmm_regnum_p (gdbarch, regnum))
472 return i386_zmm_names[regnum - tdep->zmm0_regnum];
473 else if (i386_byte_regnum_p (gdbarch, regnum))
474 return i386_byte_names[regnum - tdep->al_regnum];
475 else if (i386_word_regnum_p (gdbarch, regnum))
476 return i386_word_names[regnum - tdep->ax_regnum];
478 internal_error (__FILE__, __LINE__, _("invalid regnum"));
481 /* Convert a dbx register number REG to the appropriate register
482 number used by GDB. */
485 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
487 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
489 /* This implements what GCC calls the "default" register map
490 (dbx_register_map[]). */
492 if (reg >= 0 && reg <= 7)
494 /* General-purpose registers. The debug info calls %ebp
495 register 4, and %esp register 5. */
502 else if (reg >= 12 && reg <= 19)
504 /* Floating-point registers. */
505 return reg - 12 + I387_ST0_REGNUM (tdep);
507 else if (reg >= 21 && reg <= 28)
510 int ymm0_regnum = tdep->ymm0_regnum;
513 && i386_xmm_regnum_p (gdbarch, reg))
514 return reg - 21 + ymm0_regnum;
516 return reg - 21 + I387_XMM0_REGNUM (tdep);
518 else if (reg >= 29 && reg <= 36)
521 return reg - 29 + I387_MM0_REGNUM (tdep);
524 /* This will hopefully provoke a warning. */
525 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
528 /* Convert SVR4 DWARF register number REG to the appropriate register number
532 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
534 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
536 /* This implements the GCC register map that tries to be compatible
537 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
539 /* The SVR4 register numbering includes %eip and %eflags, and
540 numbers the floating point registers differently. */
541 if (reg >= 0 && reg <= 9)
543 /* General-purpose registers. */
546 else if (reg >= 11 && reg <= 18)
548 /* Floating-point registers. */
549 return reg - 11 + I387_ST0_REGNUM (tdep);
551 else if (reg >= 21 && reg <= 36)
553 /* The SSE and MMX registers have the same numbers as with dbx. */
554 return i386_dbx_reg_to_regnum (gdbarch, reg);
559 case 37: return I387_FCTRL_REGNUM (tdep);
560 case 38: return I387_FSTAT_REGNUM (tdep);
561 case 39: return I387_MXCSR_REGNUM (tdep);
562 case 40: return I386_ES_REGNUM;
563 case 41: return I386_CS_REGNUM;
564 case 42: return I386_SS_REGNUM;
565 case 43: return I386_DS_REGNUM;
566 case 44: return I386_FS_REGNUM;
567 case 45: return I386_GS_REGNUM;
573 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
574 num_regs + num_pseudo_regs for other debug formats. */
577 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
579 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
582 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
588 /* This is the variable that is set with "set disassembly-flavor", and
589 its legitimate values. */
590 static const char att_flavor[] = "att";
591 static const char intel_flavor[] = "intel";
592 static const char *const valid_flavors[] =
598 static const char *disassembly_flavor = att_flavor;
601 /* Use the program counter to determine the contents and size of a
602 breakpoint instruction. Return a pointer to a string of bytes that
603 encode a breakpoint instruction, store the length of the string in
604 *LEN and optionally adjust *PC to point to the correct memory
605 location for inserting the breakpoint.
607 On the i386 we have a single breakpoint that fits in a single byte
608 and can be inserted anywhere.
610 This function is 64-bit safe. */
612 constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */
614 typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint;
617 /* Displaced instruction handling. */
619 /* Skip the legacy instruction prefixes in INSN.
620 Not all prefixes are valid for any particular insn
621 but we needn't care, the insn will fault if it's invalid.
622 The result is a pointer to the first opcode byte,
623 or NULL if we run off the end of the buffer. */
626 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
628 gdb_byte *end = insn + max_len;
634 case DATA_PREFIX_OPCODE:
635 case ADDR_PREFIX_OPCODE:
636 case CS_PREFIX_OPCODE:
637 case DS_PREFIX_OPCODE:
638 case ES_PREFIX_OPCODE:
639 case FS_PREFIX_OPCODE:
640 case GS_PREFIX_OPCODE:
641 case SS_PREFIX_OPCODE:
642 case LOCK_PREFIX_OPCODE:
643 case REPE_PREFIX_OPCODE:
644 case REPNE_PREFIX_OPCODE:
656 i386_absolute_jmp_p (const gdb_byte *insn)
658 /* jmp far (absolute address in operand). */
664 /* jump near, absolute indirect (/4). */
665 if ((insn[1] & 0x38) == 0x20)
668 /* jump far, absolute indirect (/5). */
669 if ((insn[1] & 0x38) == 0x28)
676 /* Return non-zero if INSN is a jump, zero otherwise. */
679 i386_jmp_p (const gdb_byte *insn)
681 /* jump short, relative. */
685 /* jump near, relative. */
689 return i386_absolute_jmp_p (insn);
693 i386_absolute_call_p (const gdb_byte *insn)
695 /* call far, absolute. */
701 /* Call near, absolute indirect (/2). */
702 if ((insn[1] & 0x38) == 0x10)
705 /* Call far, absolute indirect (/3). */
706 if ((insn[1] & 0x38) == 0x18)
714 i386_ret_p (const gdb_byte *insn)
718 case 0xc2: /* ret near, pop N bytes. */
719 case 0xc3: /* ret near */
720 case 0xca: /* ret far, pop N bytes. */
721 case 0xcb: /* ret far */
722 case 0xcf: /* iret */
731 i386_call_p (const gdb_byte *insn)
733 if (i386_absolute_call_p (insn))
736 /* call near, relative. */
743 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
744 length in bytes. Otherwise, return zero. */
747 i386_syscall_p (const gdb_byte *insn, int *lengthp)
749 /* Is it 'int $0x80'? */
750 if ((insn[0] == 0xcd && insn[1] == 0x80)
751 /* Or is it 'sysenter'? */
752 || (insn[0] == 0x0f && insn[1] == 0x34)
753 /* Or is it 'syscall'? */
754 || (insn[0] == 0x0f && insn[1] == 0x05))
763 /* The gdbarch insn_is_call method. */
766 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
768 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
770 read_code (addr, buf, I386_MAX_INSN_LEN);
771 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
773 return i386_call_p (insn);
776 /* The gdbarch insn_is_ret method. */
779 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
781 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
783 read_code (addr, buf, I386_MAX_INSN_LEN);
784 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
786 return i386_ret_p (insn);
789 /* The gdbarch insn_is_jump method. */
792 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
794 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
796 read_code (addr, buf, I386_MAX_INSN_LEN);
797 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
799 return i386_jmp_p (insn);
802 /* Some kernels may run one past a syscall insn, so we have to cope.
803 Otherwise this is just simple_displaced_step_copy_insn. */
805 struct displaced_step_closure *
806 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
807 CORE_ADDR from, CORE_ADDR to,
808 struct regcache *regs)
810 size_t len = gdbarch_max_insn_length (gdbarch);
811 gdb_byte *buf = (gdb_byte *) xmalloc (len);
813 read_memory (from, buf, len);
815 /* GDB may get control back after the insn after the syscall.
816 Presumably this is a kernel bug.
817 If this is a syscall, make sure there's a nop afterwards. */
822 insn = i386_skip_prefixes (buf, len);
823 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
824 insn[syscall_length] = NOP_OPCODE;
827 write_memory (to, buf, len);
831 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
832 paddress (gdbarch, from), paddress (gdbarch, to));
833 displaced_step_dump_bytes (gdb_stdlog, buf, len);
836 return (struct displaced_step_closure *) buf;
839 /* Fix up the state of registers and memory after having single-stepped
840 a displaced instruction. */
843 i386_displaced_step_fixup (struct gdbarch *gdbarch,
844 struct displaced_step_closure *closure,
845 CORE_ADDR from, CORE_ADDR to,
846 struct regcache *regs)
848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
850 /* The offset we applied to the instruction's address.
851 This could well be negative (when viewed as a signed 32-bit
852 value), but ULONGEST won't reflect that, so take care when
854 ULONGEST insn_offset = to - from;
856 /* Since we use simple_displaced_step_copy_insn, our closure is a
857 copy of the instruction. */
858 gdb_byte *insn = (gdb_byte *) closure;
859 /* The start of the insn, needed in case we see some prefixes. */
860 gdb_byte *insn_start = insn;
863 fprintf_unfiltered (gdb_stdlog,
864 "displaced: fixup (%s, %s), "
865 "insn = 0x%02x 0x%02x ...\n",
866 paddress (gdbarch, from), paddress (gdbarch, to),
869 /* The list of issues to contend with here is taken from
870 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
871 Yay for Free Software! */
873 /* Relocate the %eip, if necessary. */
875 /* The instruction recognizers we use assume any leading prefixes
876 have been skipped. */
878 /* This is the size of the buffer in closure. */
879 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
880 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
881 /* If there are too many prefixes, just ignore the insn.
882 It will fault when run. */
887 /* Except in the case of absolute or indirect jump or call
888 instructions, or a return instruction, the new eip is relative to
889 the displaced instruction; make it relative. Well, signal
890 handler returns don't need relocation either, but we use the
891 value of %eip to recognize those; see below. */
892 if (! i386_absolute_jmp_p (insn)
893 && ! i386_absolute_call_p (insn)
894 && ! i386_ret_p (insn))
899 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
901 /* A signal trampoline system call changes the %eip, resuming
902 execution of the main program after the signal handler has
903 returned. That makes them like 'return' instructions; we
904 shouldn't relocate %eip.
906 But most system calls don't, and we do need to relocate %eip.
908 Our heuristic for distinguishing these cases: if stepping
909 over the system call instruction left control directly after
910 the instruction, the we relocate --- control almost certainly
911 doesn't belong in the displaced copy. Otherwise, we assume
912 the instruction has put control where it belongs, and leave
913 it unrelocated. Goodness help us if there are PC-relative
915 if (i386_syscall_p (insn, &insn_len)
916 && orig_eip != to + (insn - insn_start) + insn_len
917 /* GDB can get control back after the insn after the syscall.
918 Presumably this is a kernel bug.
919 i386_displaced_step_copy_insn ensures its a nop,
920 we add one to the length for it. */
921 && orig_eip != to + (insn - insn_start) + insn_len + 1)
924 fprintf_unfiltered (gdb_stdlog,
925 "displaced: syscall changed %%eip; "
930 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
932 /* If we just stepped over a breakpoint insn, we don't backup
933 the pc on purpose; this is to match behaviour without
936 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
939 fprintf_unfiltered (gdb_stdlog,
941 "relocated %%eip from %s to %s\n",
942 paddress (gdbarch, orig_eip),
943 paddress (gdbarch, eip));
947 /* If the instruction was PUSHFL, then the TF bit will be set in the
948 pushed value, and should be cleared. We'll leave this for later,
949 since GDB already messes up the TF flag when stepping over a
952 /* If the instruction was a call, the return address now atop the
953 stack is the address following the copied instruction. We need
954 to make it the address following the original instruction. */
955 if (i386_call_p (insn))
959 const ULONGEST retaddr_len = 4;
961 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
962 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
963 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
964 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
967 fprintf_unfiltered (gdb_stdlog,
968 "displaced: relocated return addr at %s to %s\n",
969 paddress (gdbarch, esp),
970 paddress (gdbarch, retaddr));
975 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
977 target_write_memory (*to, buf, len);
982 i386_relocate_instruction (struct gdbarch *gdbarch,
983 CORE_ADDR *to, CORE_ADDR oldloc)
985 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
986 gdb_byte buf[I386_MAX_INSN_LEN];
987 int offset = 0, rel32, newrel;
989 gdb_byte *insn = buf;
991 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
993 insn_length = gdb_buffered_insn_length (gdbarch, insn,
994 I386_MAX_INSN_LEN, oldloc);
996 /* Get past the prefixes. */
997 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
999 /* Adjust calls with 32-bit relative addresses as push/jump, with
1000 the address pushed being the location where the original call in
1001 the user program would return to. */
1002 if (insn[0] == 0xe8)
1004 gdb_byte push_buf[16];
1005 unsigned int ret_addr;
1007 /* Where "ret" in the original code will return to. */
1008 ret_addr = oldloc + insn_length;
1009 push_buf[0] = 0x68; /* pushq $... */
1010 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1011 /* Push the push. */
1012 append_insns (to, 5, push_buf);
1014 /* Convert the relative call to a relative jump. */
1017 /* Adjust the destination offset. */
1018 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1019 newrel = (oldloc - *to) + rel32;
1020 store_signed_integer (insn + 1, 4, byte_order, newrel);
1022 if (debug_displaced)
1023 fprintf_unfiltered (gdb_stdlog,
1024 "Adjusted insn rel32=%s at %s to"
1025 " rel32=%s at %s\n",
1026 hex_string (rel32), paddress (gdbarch, oldloc),
1027 hex_string (newrel), paddress (gdbarch, *to));
1029 /* Write the adjusted jump into its displaced location. */
1030 append_insns (to, 5, insn);
1034 /* Adjust jumps with 32-bit relative addresses. Calls are already
1036 if (insn[0] == 0xe9)
1038 /* Adjust conditional jumps. */
1039 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1044 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1045 newrel = (oldloc - *to) + rel32;
1046 store_signed_integer (insn + offset, 4, byte_order, newrel);
1047 if (debug_displaced)
1048 fprintf_unfiltered (gdb_stdlog,
1049 "Adjusted insn rel32=%s at %s to"
1050 " rel32=%s at %s\n",
1051 hex_string (rel32), paddress (gdbarch, oldloc),
1052 hex_string (newrel), paddress (gdbarch, *to));
1055 /* Write the adjusted instructions into their displaced
1057 append_insns (to, insn_length, buf);
1061 #ifdef I386_REGNO_TO_SYMMETRY
1062 #error "The Sequent Symmetry is no longer supported."
1065 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1066 and %esp "belong" to the calling function. Therefore these
1067 registers should be saved if they're going to be modified. */
1069 /* The maximum number of saved registers. This should include all
1070 registers mentioned above, and %eip. */
1071 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1073 struct i386_frame_cache
1081 /* Saved registers. */
1082 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1087 /* Stack space reserved for local variables. */
1091 /* Allocate and initialize a frame cache. */
1093 static struct i386_frame_cache *
1094 i386_alloc_frame_cache (void)
1096 struct i386_frame_cache *cache;
1099 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1104 cache->sp_offset = -4;
1107 /* Saved registers. We initialize these to -1 since zero is a valid
1108 offset (that's where %ebp is supposed to be stored). */
1109 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1110 cache->saved_regs[i] = -1;
1111 cache->saved_sp = 0;
1112 cache->saved_sp_reg = -1;
1113 cache->pc_in_eax = 0;
1115 /* Frameless until proven otherwise. */
1121 /* If the instruction at PC is a jump, return the address of its
1122 target. Otherwise, return PC. */
1125 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1127 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1132 if (target_read_code (pc, &op, 1))
1139 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1145 /* Relative jump: if data16 == 0, disp32, else disp16. */
1148 delta = read_memory_integer (pc + 2, 2, byte_order);
1150 /* Include the size of the jmp instruction (including the
1156 delta = read_memory_integer (pc + 1, 4, byte_order);
1158 /* Include the size of the jmp instruction. */
1163 /* Relative jump, disp8 (ignore data16). */
1164 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1166 delta += data16 + 2;
1173 /* Check whether PC points at a prologue for a function returning a
1174 structure or union. If so, it updates CACHE and returns the
1175 address of the first instruction after the code sequence that
1176 removes the "hidden" argument from the stack or CURRENT_PC,
1177 whichever is smaller. Otherwise, return PC. */
1180 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1181 struct i386_frame_cache *cache)
1183 /* Functions that return a structure or union start with:
1186 xchgl %eax, (%esp) 0x87 0x04 0x24
1187 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1189 (the System V compiler puts out the second `xchg' instruction,
1190 and the assembler doesn't try to optimize it, so the 'sib' form
1191 gets generated). This sequence is used to get the address of the
1192 return buffer for a function that returns a structure. */
1193 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1194 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1198 if (current_pc <= pc)
1201 if (target_read_code (pc, &op, 1))
1204 if (op != 0x58) /* popl %eax */
1207 if (target_read_code (pc + 1, buf, 4))
1210 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1213 if (current_pc == pc)
1215 cache->sp_offset += 4;
1219 if (current_pc == pc + 1)
1221 cache->pc_in_eax = 1;
1225 if (buf[1] == proto1[1])
1232 i386_skip_probe (CORE_ADDR pc)
1234 /* A function may start with
1248 if (target_read_code (pc, &op, 1))
1251 if (op == 0x68 || op == 0x6a)
1255 /* Skip past the `pushl' instruction; it has either a one-byte or a
1256 four-byte operand, depending on the opcode. */
1262 /* Read the following 8 bytes, which should be `call _probe' (6
1263 bytes) followed by `addl $4,%esp' (2 bytes). */
1264 read_memory (pc + delta, buf, sizeof (buf));
1265 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1266 pc += delta + sizeof (buf);
1272 /* GCC 4.1 and later, can put code in the prologue to realign the
1273 stack pointer. Check whether PC points to such code, and update
1274 CACHE accordingly. Return the first instruction after the code
1275 sequence or CURRENT_PC, whichever is smaller. If we don't
1276 recognize the code, return PC. */
1279 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1280 struct i386_frame_cache *cache)
1282 /* There are 2 code sequences to re-align stack before the frame
1285 1. Use a caller-saved saved register:
1291 2. Use a callee-saved saved register:
1298 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1300 0x83 0xe4 0xf0 andl $-16, %esp
1301 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1306 int offset, offset_and;
1307 static int regnums[8] = {
1308 I386_EAX_REGNUM, /* %eax */
1309 I386_ECX_REGNUM, /* %ecx */
1310 I386_EDX_REGNUM, /* %edx */
1311 I386_EBX_REGNUM, /* %ebx */
1312 I386_ESP_REGNUM, /* %esp */
1313 I386_EBP_REGNUM, /* %ebp */
1314 I386_ESI_REGNUM, /* %esi */
1315 I386_EDI_REGNUM /* %edi */
1318 if (target_read_code (pc, buf, sizeof buf))
1321 /* Check caller-saved saved register. The first instruction has
1322 to be "leal 4(%esp), %reg". */
1323 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1325 /* MOD must be binary 10 and R/M must be binary 100. */
1326 if ((buf[1] & 0xc7) != 0x44)
1329 /* REG has register number. */
1330 reg = (buf[1] >> 3) & 7;
1335 /* Check callee-saved saved register. The first instruction
1336 has to be "pushl %reg". */
1337 if ((buf[0] & 0xf8) != 0x50)
1343 /* The next instruction has to be "leal 8(%esp), %reg". */
1344 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1347 /* MOD must be binary 10 and R/M must be binary 100. */
1348 if ((buf[2] & 0xc7) != 0x44)
1351 /* REG has register number. Registers in pushl and leal have to
1353 if (reg != ((buf[2] >> 3) & 7))
1359 /* Rigister can't be %esp nor %ebp. */
1360 if (reg == 4 || reg == 5)
1363 /* The next instruction has to be "andl $-XXX, %esp". */
1364 if (buf[offset + 1] != 0xe4
1365 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1368 offset_and = offset;
1369 offset += buf[offset] == 0x81 ? 6 : 3;
1371 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1372 0xfc. REG must be binary 110 and MOD must be binary 01. */
1373 if (buf[offset] != 0xff
1374 || buf[offset + 2] != 0xfc
1375 || (buf[offset + 1] & 0xf8) != 0x70)
1378 /* R/M has register. Registers in leal and pushl have to be the
1380 if (reg != (buf[offset + 1] & 7))
1383 if (current_pc > pc + offset_and)
1384 cache->saved_sp_reg = regnums[reg];
1386 return std::min (pc + offset + 3, current_pc);
1389 /* Maximum instruction length we need to handle. */
1390 #define I386_MAX_MATCHED_INSN_LEN 6
1392 /* Instruction description. */
1396 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1397 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1400 /* Return whether instruction at PC matches PATTERN. */
1403 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1407 if (target_read_code (pc, &op, 1))
1410 if ((op & pattern.mask[0]) == pattern.insn[0])
1412 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1413 int insn_matched = 1;
1416 gdb_assert (pattern.len > 1);
1417 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1419 if (target_read_code (pc + 1, buf, pattern.len - 1))
1422 for (i = 1; i < pattern.len; i++)
1424 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1427 return insn_matched;
1432 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1433 the first instruction description that matches. Otherwise, return
1436 static struct i386_insn *
1437 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1439 struct i386_insn *pattern;
1441 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1443 if (i386_match_pattern (pc, *pattern))
1450 /* Return whether PC points inside a sequence of instructions that
1451 matches INSN_PATTERNS. */
1454 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1456 CORE_ADDR current_pc;
1458 struct i386_insn *insn;
1460 insn = i386_match_insn (pc, insn_patterns);
1465 ix = insn - insn_patterns;
1466 for (i = ix - 1; i >= 0; i--)
1468 current_pc -= insn_patterns[i].len;
1470 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1474 current_pc = pc + insn->len;
1475 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1477 if (!i386_match_pattern (current_pc, *insn))
1480 current_pc += insn->len;
1486 /* Some special instructions that might be migrated by GCC into the
1487 part of the prologue that sets up the new stack frame. Because the
1488 stack frame hasn't been setup yet, no registers have been saved
1489 yet, and only the scratch registers %eax, %ecx and %edx can be
1492 struct i386_insn i386_frame_setup_skip_insns[] =
1494 /* Check for `movb imm8, r' and `movl imm32, r'.
1496 ??? Should we handle 16-bit operand-sizes here? */
1498 /* `movb imm8, %al' and `movb imm8, %ah' */
1499 /* `movb imm8, %cl' and `movb imm8, %ch' */
1500 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1501 /* `movb imm8, %dl' and `movb imm8, %dh' */
1502 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1503 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1504 { 5, { 0xb8 }, { 0xfe } },
1505 /* `movl imm32, %edx' */
1506 { 5, { 0xba }, { 0xff } },
1508 /* Check for `mov imm32, r32'. Note that there is an alternative
1509 encoding for `mov m32, %eax'.
1511 ??? Should we handle SIB adressing here?
1512 ??? Should we handle 16-bit operand-sizes here? */
1514 /* `movl m32, %eax' */
1515 { 5, { 0xa1 }, { 0xff } },
1516 /* `movl m32, %eax' and `mov; m32, %ecx' */
1517 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1518 /* `movl m32, %edx' */
1519 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1521 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1522 Because of the symmetry, there are actually two ways to encode
1523 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1524 opcode bytes 0x31 and 0x33 for `xorl'. */
1526 /* `subl %eax, %eax' */
1527 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1528 /* `subl %ecx, %ecx' */
1529 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1530 /* `subl %edx, %edx' */
1531 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1532 /* `xorl %eax, %eax' */
1533 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1534 /* `xorl %ecx, %ecx' */
1535 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1536 /* `xorl %edx, %edx' */
1537 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1542 /* Check whether PC points to a no-op instruction. */
1544 i386_skip_noop (CORE_ADDR pc)
1549 if (target_read_code (pc, &op, 1))
1555 /* Ignore `nop' instruction. */
1559 if (target_read_code (pc, &op, 1))
1563 /* Ignore no-op instruction `mov %edi, %edi'.
1564 Microsoft system dlls often start with
1565 a `mov %edi,%edi' instruction.
1566 The 5 bytes before the function start are
1567 filled with `nop' instructions.
1568 This pattern can be used for hot-patching:
1569 The `mov %edi, %edi' instruction can be replaced by a
1570 near jump to the location of the 5 `nop' instructions
1571 which can be replaced by a 32-bit jump to anywhere
1572 in the 32-bit address space. */
1574 else if (op == 0x8b)
1576 if (target_read_code (pc + 1, &op, 1))
1582 if (target_read_code (pc, &op, 1))
1592 /* Check whether PC points at a code that sets up a new stack frame.
1593 If so, it updates CACHE and returns the address of the first
1594 instruction after the sequence that sets up the frame or LIMIT,
1595 whichever is smaller. If we don't recognize the code, return PC. */
1598 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1599 CORE_ADDR pc, CORE_ADDR limit,
1600 struct i386_frame_cache *cache)
1602 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1603 struct i386_insn *insn;
1610 if (target_read_code (pc, &op, 1))
1613 if (op == 0x55) /* pushl %ebp */
1615 /* Take into account that we've executed the `pushl %ebp' that
1616 starts this instruction sequence. */
1617 cache->saved_regs[I386_EBP_REGNUM] = 0;
1618 cache->sp_offset += 4;
1621 /* If that's all, return now. */
1625 /* Check for some special instructions that might be migrated by
1626 GCC into the prologue and skip them. At this point in the
1627 prologue, code should only touch the scratch registers %eax,
1628 %ecx and %edx, so while the number of posibilities is sheer,
1631 Make sure we only skip these instructions if we later see the
1632 `movl %esp, %ebp' that actually sets up the frame. */
1633 while (pc + skip < limit)
1635 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1642 /* If that's all, return now. */
1643 if (limit <= pc + skip)
1646 if (target_read_code (pc + skip, &op, 1))
1649 /* The i386 prologue looks like
1655 and a different prologue can be generated for atom.
1659 lea -0x10(%esp),%esp
1661 We handle both of them here. */
1665 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1667 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1673 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1678 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1679 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1688 /* OK, we actually have a frame. We just don't know how large
1689 it is yet. Set its size to zero. We'll adjust it if
1690 necessary. We also now commit to skipping the special
1691 instructions mentioned before. */
1694 /* If that's all, return now. */
1698 /* Check for stack adjustment
1704 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1705 reg, so we don't have to worry about a data16 prefix. */
1706 if (target_read_code (pc, &op, 1))
1710 /* `subl' with 8-bit immediate. */
1711 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1712 /* Some instruction starting with 0x83 other than `subl'. */
1715 /* `subl' with signed 8-bit immediate (though it wouldn't
1716 make sense to be negative). */
1717 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1720 else if (op == 0x81)
1722 /* Maybe it is `subl' with a 32-bit immediate. */
1723 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1724 /* Some instruction starting with 0x81 other than `subl'. */
1727 /* It is `subl' with a 32-bit immediate. */
1728 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1731 else if (op == 0x8d)
1733 /* The ModR/M byte is 0x64. */
1734 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1736 /* 'lea' with 8-bit displacement. */
1737 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1742 /* Some instruction other than `subl' nor 'lea'. */
1746 else if (op == 0xc8) /* enter */
1748 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1755 /* Check whether PC points at code that saves registers on the stack.
1756 If so, it updates CACHE and returns the address of the first
1757 instruction after the register saves or CURRENT_PC, whichever is
1758 smaller. Otherwise, return PC. */
1761 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1762 struct i386_frame_cache *cache)
1764 CORE_ADDR offset = 0;
1768 if (cache->locals > 0)
1769 offset -= cache->locals;
1770 for (i = 0; i < 8 && pc < current_pc; i++)
1772 if (target_read_code (pc, &op, 1))
1774 if (op < 0x50 || op > 0x57)
1778 cache->saved_regs[op - 0x50] = offset;
1779 cache->sp_offset += 4;
1786 /* Do a full analysis of the prologue at PC and update CACHE
1787 accordingly. Bail out early if CURRENT_PC is reached. Return the
1788 address where the analysis stopped.
1790 We handle these cases:
1792 The startup sequence can be at the start of the function, or the
1793 function can start with a branch to startup code at the end.
1795 %ebp can be set up with either the 'enter' instruction, or "pushl
1796 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1797 once used in the System V compiler).
1799 Local space is allocated just below the saved %ebp by either the
1800 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1801 16-bit unsigned argument for space to allocate, and the 'addl'
1802 instruction could have either a signed byte, or 32-bit immediate.
1804 Next, the registers used by this function are pushed. With the
1805 System V compiler they will always be in the order: %edi, %esi,
1806 %ebx (and sometimes a harmless bug causes it to also save but not
1807 restore %eax); however, the code below is willing to see the pushes
1808 in any order, and will handle up to 8 of them.
1810 If the setup sequence is at the end of the function, then the next
1811 instruction will be a branch back to the start. */
1814 i386_analyze_prologue (struct gdbarch *gdbarch,
1815 CORE_ADDR pc, CORE_ADDR current_pc,
1816 struct i386_frame_cache *cache)
1818 pc = i386_skip_noop (pc);
1819 pc = i386_follow_jump (gdbarch, pc);
1820 pc = i386_analyze_struct_return (pc, current_pc, cache);
1821 pc = i386_skip_probe (pc);
1822 pc = i386_analyze_stack_align (pc, current_pc, cache);
1823 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1824 return i386_analyze_register_saves (pc, current_pc, cache);
1827 /* Return PC of first real instruction. */
1830 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1832 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1834 static gdb_byte pic_pat[6] =
1836 0xe8, 0, 0, 0, 0, /* call 0x0 */
1837 0x5b, /* popl %ebx */
1839 struct i386_frame_cache cache;
1843 CORE_ADDR func_addr;
1845 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1847 CORE_ADDR post_prologue_pc
1848 = skip_prologue_using_sal (gdbarch, func_addr);
1849 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1851 /* Clang always emits a line note before the prologue and another
1852 one after. We trust clang to emit usable line notes. */
1853 if (post_prologue_pc
1855 && COMPUNIT_PRODUCER (cust) != NULL
1856 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1857 return std::max (start_pc, post_prologue_pc);
1861 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1862 if (cache.locals < 0)
1865 /* Found valid frame setup. */
1867 /* The native cc on SVR4 in -K PIC mode inserts the following code
1868 to get the address of the global offset table (GOT) into register
1873 movl %ebx,x(%ebp) (optional)
1876 This code is with the rest of the prologue (at the end of the
1877 function), so we have to skip it to get to the first real
1878 instruction at the start of the function. */
1880 for (i = 0; i < 6; i++)
1882 if (target_read_code (pc + i, &op, 1))
1885 if (pic_pat[i] != op)
1892 if (target_read_code (pc + delta, &op, 1))
1895 if (op == 0x89) /* movl %ebx, x(%ebp) */
1897 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1899 if (op == 0x5d) /* One byte offset from %ebp. */
1901 else if (op == 0x9d) /* Four byte offset from %ebp. */
1903 else /* Unexpected instruction. */
1906 if (target_read_code (pc + delta, &op, 1))
1911 if (delta > 0 && op == 0x81
1912 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1919 /* If the function starts with a branch (to startup code at the end)
1920 the last instruction should bring us back to the first
1921 instruction of the real code. */
1922 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1923 pc = i386_follow_jump (gdbarch, pc);
1928 /* Check that the code pointed to by PC corresponds to a call to
1929 __main, skip it if so. Return PC otherwise. */
1932 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1934 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1937 if (target_read_code (pc, &op, 1))
1943 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1945 /* Make sure address is computed correctly as a 32bit
1946 integer even if CORE_ADDR is 64 bit wide. */
1947 struct bound_minimal_symbol s;
1948 CORE_ADDR call_dest;
1950 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1951 call_dest = call_dest & 0xffffffffU;
1952 s = lookup_minimal_symbol_by_pc (call_dest);
1953 if (s.minsym != NULL
1954 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1955 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1963 /* This function is 64-bit safe. */
1966 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1970 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1971 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1975 /* Normal frames. */
1978 i386_frame_cache_1 (struct frame_info *this_frame,
1979 struct i386_frame_cache *cache)
1981 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1982 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1986 cache->pc = get_frame_func (this_frame);
1988 /* In principle, for normal frames, %ebp holds the frame pointer,
1989 which holds the base address for the current stack frame.
1990 However, for functions that don't need it, the frame pointer is
1991 optional. For these "frameless" functions the frame pointer is
1992 actually the frame pointer of the calling frame. Signal
1993 trampolines are just a special case of a "frameless" function.
1994 They (usually) share their frame pointer with the frame that was
1995 in progress when the signal occurred. */
1997 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1998 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1999 if (cache->base == 0)
2005 /* For normal frames, %eip is stored at 4(%ebp). */
2006 cache->saved_regs[I386_EIP_REGNUM] = 4;
2009 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2012 if (cache->locals < 0)
2014 /* We didn't find a valid frame, which means that CACHE->base
2015 currently holds the frame pointer for our calling frame. If
2016 we're at the start of a function, or somewhere half-way its
2017 prologue, the function's frame probably hasn't been fully
2018 setup yet. Try to reconstruct the base address for the stack
2019 frame by looking at the stack pointer. For truly "frameless"
2020 functions this might work too. */
2022 if (cache->saved_sp_reg != -1)
2024 /* Saved stack pointer has been saved. */
2025 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2026 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2028 /* We're halfway aligning the stack. */
2029 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2030 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2032 /* This will be added back below. */
2033 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2035 else if (cache->pc != 0
2036 || target_read_code (get_frame_pc (this_frame), buf, 1))
2038 /* We're in a known function, but did not find a frame
2039 setup. Assume that the function does not use %ebp.
2040 Alternatively, we may have jumped to an invalid
2041 address; in that case there is definitely no new
2043 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2044 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2048 /* We're in an unknown function. We could not find the start
2049 of the function to analyze the prologue; our best option is
2050 to assume a typical frame layout with the caller's %ebp
2052 cache->saved_regs[I386_EBP_REGNUM] = 0;
2055 if (cache->saved_sp_reg != -1)
2057 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2058 register may be unavailable). */
2059 if (cache->saved_sp == 0
2060 && deprecated_frame_register_read (this_frame,
2061 cache->saved_sp_reg, buf))
2062 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2064 /* Now that we have the base address for the stack frame we can
2065 calculate the value of %esp in the calling frame. */
2066 else if (cache->saved_sp == 0)
2067 cache->saved_sp = cache->base + 8;
2069 /* Adjust all the saved registers such that they contain addresses
2070 instead of offsets. */
2071 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2072 if (cache->saved_regs[i] != -1)
2073 cache->saved_regs[i] += cache->base;
2078 static struct i386_frame_cache *
2079 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2081 struct i386_frame_cache *cache;
2084 return (struct i386_frame_cache *) *this_cache;
2086 cache = i386_alloc_frame_cache ();
2087 *this_cache = cache;
2091 i386_frame_cache_1 (this_frame, cache);
2093 CATCH (ex, RETURN_MASK_ERROR)
2095 if (ex.error != NOT_AVAILABLE_ERROR)
2096 throw_exception (ex);
2104 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2105 struct frame_id *this_id)
2107 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2110 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2111 else if (cache->base == 0)
2113 /* This marks the outermost frame. */
2117 /* See the end of i386_push_dummy_call. */
2118 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2122 static enum unwind_stop_reason
2123 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2126 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2129 return UNWIND_UNAVAILABLE;
2131 /* This marks the outermost frame. */
2132 if (cache->base == 0)
2133 return UNWIND_OUTERMOST;
2135 return UNWIND_NO_REASON;
2138 static struct value *
2139 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2142 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2144 gdb_assert (regnum >= 0);
2146 /* The System V ABI says that:
2148 "The flags register contains the system flags, such as the
2149 direction flag and the carry flag. The direction flag must be
2150 set to the forward (that is, zero) direction before entry and
2151 upon exit from a function. Other user flags have no specified
2152 role in the standard calling sequence and are not preserved."
2154 To guarantee the "upon exit" part of that statement we fake a
2155 saved flags register that has its direction flag cleared.
2157 Note that GCC doesn't seem to rely on the fact that the direction
2158 flag is cleared after a function return; it always explicitly
2159 clears the flag before operations where it matters.
2161 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2162 right thing to do. The way we fake the flags register here makes
2163 it impossible to change it. */
2165 if (regnum == I386_EFLAGS_REGNUM)
2169 val = get_frame_register_unsigned (this_frame, regnum);
2171 return frame_unwind_got_constant (this_frame, regnum, val);
2174 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2175 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2177 if (regnum == I386_ESP_REGNUM
2178 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2180 /* If the SP has been saved, but we don't know where, then this
2181 means that SAVED_SP_REG register was found unavailable back
2182 when we built the cache. */
2183 if (cache->saved_sp == 0)
2184 return frame_unwind_got_register (this_frame, regnum,
2185 cache->saved_sp_reg);
2187 return frame_unwind_got_constant (this_frame, regnum,
2191 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2192 return frame_unwind_got_memory (this_frame, regnum,
2193 cache->saved_regs[regnum]);
2195 return frame_unwind_got_register (this_frame, regnum, regnum);
2198 static const struct frame_unwind i386_frame_unwind =
2201 i386_frame_unwind_stop_reason,
2203 i386_frame_prev_register,
2205 default_frame_sniffer
2208 /* Normal frames, but in a function epilogue. */
2210 /* Implement the stack_frame_destroyed_p gdbarch method.
2212 The epilogue is defined here as the 'ret' instruction, which will
2213 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2214 the function's stack frame. */
2217 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2220 struct compunit_symtab *cust;
2222 cust = find_pc_compunit_symtab (pc);
2223 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2226 if (target_read_memory (pc, &insn, 1))
2227 return 0; /* Can't read memory at pc. */
2229 if (insn != 0xc3) /* 'ret' instruction. */
2236 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2237 struct frame_info *this_frame,
2238 void **this_prologue_cache)
2240 if (frame_relative_level (this_frame) == 0)
2241 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2242 get_frame_pc (this_frame));
2247 static struct i386_frame_cache *
2248 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2250 struct i386_frame_cache *cache;
2254 return (struct i386_frame_cache *) *this_cache;
2256 cache = i386_alloc_frame_cache ();
2257 *this_cache = cache;
2261 cache->pc = get_frame_func (this_frame);
2263 /* At this point the stack looks as if we just entered the
2264 function, with the return address at the top of the
2266 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2267 cache->base = sp + cache->sp_offset;
2268 cache->saved_sp = cache->base + 8;
2269 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2273 CATCH (ex, RETURN_MASK_ERROR)
2275 if (ex.error != NOT_AVAILABLE_ERROR)
2276 throw_exception (ex);
2283 static enum unwind_stop_reason
2284 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2287 struct i386_frame_cache *cache =
2288 i386_epilogue_frame_cache (this_frame, this_cache);
2291 return UNWIND_UNAVAILABLE;
2293 return UNWIND_NO_REASON;
2297 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2299 struct frame_id *this_id)
2301 struct i386_frame_cache *cache =
2302 i386_epilogue_frame_cache (this_frame, this_cache);
2305 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2307 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2310 static struct value *
2311 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2312 void **this_cache, int regnum)
2314 /* Make sure we've initialized the cache. */
2315 i386_epilogue_frame_cache (this_frame, this_cache);
2317 return i386_frame_prev_register (this_frame, this_cache, regnum);
2320 static const struct frame_unwind i386_epilogue_frame_unwind =
2323 i386_epilogue_frame_unwind_stop_reason,
2324 i386_epilogue_frame_this_id,
2325 i386_epilogue_frame_prev_register,
2327 i386_epilogue_frame_sniffer
2331 /* Stack-based trampolines. */
2333 /* These trampolines are used on cross x86 targets, when taking the
2334 address of a nested function. When executing these trampolines,
2335 no stack frame is set up, so we are in a similar situation as in
2336 epilogues and i386_epilogue_frame_this_id can be re-used. */
2338 /* Static chain passed in register. */
2340 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2342 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2343 { 5, { 0xb8 }, { 0xfe } },
2346 { 5, { 0xe9 }, { 0xff } },
2351 /* Static chain passed on stack (when regparm=3). */
2353 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2356 { 5, { 0x68 }, { 0xff } },
2359 { 5, { 0xe9 }, { 0xff } },
2364 /* Return whether PC points inside a stack trampoline. */
2367 i386_in_stack_tramp_p (CORE_ADDR pc)
2372 /* A stack trampoline is detected if no name is associated
2373 to the current pc and if it points inside a trampoline
2376 find_pc_partial_function (pc, &name, NULL, NULL);
2380 if (target_read_memory (pc, &insn, 1))
2383 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2384 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2391 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2392 struct frame_info *this_frame,
2395 if (frame_relative_level (this_frame) == 0)
2396 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2401 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2404 i386_epilogue_frame_unwind_stop_reason,
2405 i386_epilogue_frame_this_id,
2406 i386_epilogue_frame_prev_register,
2408 i386_stack_tramp_frame_sniffer
2411 /* Generate a bytecode expression to get the value of the saved PC. */
2414 i386_gen_return_address (struct gdbarch *gdbarch,
2415 struct agent_expr *ax, struct axs_value *value,
2418 /* The following sequence assumes the traditional use of the base
2420 ax_reg (ax, I386_EBP_REGNUM);
2422 ax_simple (ax, aop_add);
2423 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2424 value->kind = axs_lvalue_memory;
2428 /* Signal trampolines. */
2430 static struct i386_frame_cache *
2431 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2433 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2434 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2435 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2436 struct i386_frame_cache *cache;
2441 return (struct i386_frame_cache *) *this_cache;
2443 cache = i386_alloc_frame_cache ();
2447 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2448 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2450 addr = tdep->sigcontext_addr (this_frame);
2451 if (tdep->sc_reg_offset)
2455 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2457 for (i = 0; i < tdep->sc_num_regs; i++)
2458 if (tdep->sc_reg_offset[i] != -1)
2459 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2463 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2464 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2469 CATCH (ex, RETURN_MASK_ERROR)
2471 if (ex.error != NOT_AVAILABLE_ERROR)
2472 throw_exception (ex);
2476 *this_cache = cache;
2480 static enum unwind_stop_reason
2481 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2484 struct i386_frame_cache *cache =
2485 i386_sigtramp_frame_cache (this_frame, this_cache);
2488 return UNWIND_UNAVAILABLE;
2490 return UNWIND_NO_REASON;
2494 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2495 struct frame_id *this_id)
2497 struct i386_frame_cache *cache =
2498 i386_sigtramp_frame_cache (this_frame, this_cache);
2501 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2504 /* See the end of i386_push_dummy_call. */
2505 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2509 static struct value *
2510 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2511 void **this_cache, int regnum)
2513 /* Make sure we've initialized the cache. */
2514 i386_sigtramp_frame_cache (this_frame, this_cache);
2516 return i386_frame_prev_register (this_frame, this_cache, regnum);
2520 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2521 struct frame_info *this_frame,
2522 void **this_prologue_cache)
2524 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2526 /* We shouldn't even bother if we don't have a sigcontext_addr
2528 if (tdep->sigcontext_addr == NULL)
2531 if (tdep->sigtramp_p != NULL)
2533 if (tdep->sigtramp_p (this_frame))
2537 if (tdep->sigtramp_start != 0)
2539 CORE_ADDR pc = get_frame_pc (this_frame);
2541 gdb_assert (tdep->sigtramp_end != 0);
2542 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2549 static const struct frame_unwind i386_sigtramp_frame_unwind =
2552 i386_sigtramp_frame_unwind_stop_reason,
2553 i386_sigtramp_frame_this_id,
2554 i386_sigtramp_frame_prev_register,
2556 i386_sigtramp_frame_sniffer
2561 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2563 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2568 static const struct frame_base i386_frame_base =
2571 i386_frame_base_address,
2572 i386_frame_base_address,
2573 i386_frame_base_address
2576 static struct frame_id
2577 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2581 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2583 /* See the end of i386_push_dummy_call. */
2584 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2587 /* _Decimal128 function return values need 16-byte alignment on the
2591 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2593 return sp & -(CORE_ADDR)16;
2597 /* Figure out where the longjmp will land. Slurp the args out of the
2598 stack. We expect the first arg to be a pointer to the jmp_buf
2599 structure from which we extract the address that we will land at.
2600 This address is copied into PC. This routine returns non-zero on
2604 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2607 CORE_ADDR sp, jb_addr;
2608 struct gdbarch *gdbarch = get_frame_arch (frame);
2609 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2610 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2612 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2613 longjmp will land. */
2614 if (jb_pc_offset == -1)
2617 get_frame_register (frame, I386_ESP_REGNUM, buf);
2618 sp = extract_unsigned_integer (buf, 4, byte_order);
2619 if (target_read_memory (sp + 4, buf, 4))
2622 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2623 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2626 *pc = extract_unsigned_integer (buf, 4, byte_order);
2631 /* Check whether TYPE must be 16-byte-aligned when passed as a
2632 function argument. 16-byte vectors, _Decimal128 and structures or
2633 unions containing such types must be 16-byte-aligned; other
2634 arguments are 4-byte-aligned. */
2637 i386_16_byte_align_p (struct type *type)
2639 type = check_typedef (type);
2640 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2641 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2642 && TYPE_LENGTH (type) == 16)
2644 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2645 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2646 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2647 || TYPE_CODE (type) == TYPE_CODE_UNION)
2650 for (i = 0; i < TYPE_NFIELDS (type); i++)
2652 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2659 /* Implementation for set_gdbarch_push_dummy_code. */
2662 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2663 struct value **args, int nargs, struct type *value_type,
2664 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2665 struct regcache *regcache)
2667 /* Use 0xcc breakpoint - 1 byte. */
2671 /* Keep the stack aligned. */
2676 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2677 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2678 struct value **args, CORE_ADDR sp, int struct_return,
2679 CORE_ADDR struct_addr)
2681 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2687 /* BND registers can be in arbitrary values at the moment of the
2688 inferior call. This can cause boundary violations that are not
2689 due to a real bug or even desired by the user. The best to be done
2690 is set the BND registers to allow access to the whole memory, INIT
2691 state, before pushing the inferior call. */
2692 i387_reset_bnd_regs (gdbarch, regcache);
2694 /* Determine the total space required for arguments and struct
2695 return address in a first pass (allowing for 16-byte-aligned
2696 arguments), then push arguments in a second pass. */
2698 for (write_pass = 0; write_pass < 2; write_pass++)
2700 int args_space_used = 0;
2706 /* Push value address. */
2707 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2708 write_memory (sp, buf, 4);
2709 args_space_used += 4;
2715 for (i = 0; i < nargs; i++)
2717 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2721 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2722 args_space_used = align_up (args_space_used, 16);
2724 write_memory (sp + args_space_used,
2725 value_contents_all (args[i]), len);
2726 /* The System V ABI says that:
2728 "An argument's size is increased, if necessary, to make it a
2729 multiple of [32-bit] words. This may require tail padding,
2730 depending on the size of the argument."
2732 This makes sure the stack stays word-aligned. */
2733 args_space_used += align_up (len, 4);
2737 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2738 args_space = align_up (args_space, 16);
2739 args_space += align_up (len, 4);
2747 /* The original System V ABI only requires word alignment,
2748 but modern incarnations need 16-byte alignment in order
2749 to support SSE. Since wasting a few bytes here isn't
2750 harmful we unconditionally enforce 16-byte alignment. */
2755 /* Store return address. */
2757 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2758 write_memory (sp, buf, 4);
2760 /* Finally, update the stack pointer... */
2761 store_unsigned_integer (buf, 4, byte_order, sp);
2762 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2764 /* ...and fake a frame pointer. */
2765 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2767 /* MarkK wrote: This "+ 8" is all over the place:
2768 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2769 i386_dummy_id). It's there, since all frame unwinders for
2770 a given target have to agree (within a certain margin) on the
2771 definition of the stack address of a frame. Otherwise frame id
2772 comparison might not work correctly. Since DWARF2/GCC uses the
2773 stack address *before* the function call as a frame's CFA. On
2774 the i386, when %ebp is used as a frame pointer, the offset
2775 between the contents %ebp and the CFA as defined by GCC. */
2779 /* These registers are used for returning integers (and on some
2780 targets also for returning `struct' and `union' values when their
2781 size and alignment match an integer type). */
2782 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2783 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2785 /* Read, for architecture GDBARCH, a function return value of TYPE
2786 from REGCACHE, and copy that into VALBUF. */
2789 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2790 struct regcache *regcache, gdb_byte *valbuf)
2792 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2793 int len = TYPE_LENGTH (type);
2794 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2796 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2798 if (tdep->st0_regnum < 0)
2800 warning (_("Cannot find floating-point return value."));
2801 memset (valbuf, 0, len);
2805 /* Floating-point return values can be found in %st(0). Convert
2806 its contents to the desired type. This is probably not
2807 exactly how it would happen on the target itself, but it is
2808 the best we can do. */
2809 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2810 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2814 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2815 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2817 if (len <= low_size)
2819 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2820 memcpy (valbuf, buf, len);
2822 else if (len <= (low_size + high_size))
2824 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2825 memcpy (valbuf, buf, low_size);
2826 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2827 memcpy (valbuf + low_size, buf, len - low_size);
2830 internal_error (__FILE__, __LINE__,
2831 _("Cannot extract return value of %d bytes long."),
2836 /* Write, for architecture GDBARCH, a function return value of TYPE
2837 from VALBUF into REGCACHE. */
2840 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2841 struct regcache *regcache, const gdb_byte *valbuf)
2843 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2844 int len = TYPE_LENGTH (type);
2846 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2849 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2851 if (tdep->st0_regnum < 0)
2853 warning (_("Cannot set floating-point return value."));
2857 /* Returning floating-point values is a bit tricky. Apart from
2858 storing the return value in %st(0), we have to simulate the
2859 state of the FPU at function return point. */
2861 /* Convert the value found in VALBUF to the extended
2862 floating-point format used by the FPU. This is probably
2863 not exactly how it would happen on the target itself, but
2864 it is the best we can do. */
2865 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2866 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2868 /* Set the top of the floating-point register stack to 7. The
2869 actual value doesn't really matter, but 7 is what a normal
2870 function return would end up with if the program started out
2871 with a freshly initialized FPU. */
2872 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2874 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2876 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2877 the floating-point register stack to 7, the appropriate value
2878 for the tag word is 0x3fff. */
2879 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2883 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2884 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2886 if (len <= low_size)
2887 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2888 else if (len <= (low_size + high_size))
2890 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2891 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2892 len - low_size, valbuf + low_size);
2895 internal_error (__FILE__, __LINE__,
2896 _("Cannot store return value of %d bytes long."), len);
2901 /* This is the variable that is set with "set struct-convention", and
2902 its legitimate values. */
2903 static const char default_struct_convention[] = "default";
2904 static const char pcc_struct_convention[] = "pcc";
2905 static const char reg_struct_convention[] = "reg";
2906 static const char *const valid_conventions[] =
2908 default_struct_convention,
2909 pcc_struct_convention,
2910 reg_struct_convention,
2913 static const char *struct_convention = default_struct_convention;
2915 /* Return non-zero if TYPE, which is assumed to be a structure,
2916 a union type, or an array type, should be returned in registers
2917 for architecture GDBARCH. */
2920 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2922 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2923 enum type_code code = TYPE_CODE (type);
2924 int len = TYPE_LENGTH (type);
2926 gdb_assert (code == TYPE_CODE_STRUCT
2927 || code == TYPE_CODE_UNION
2928 || code == TYPE_CODE_ARRAY);
2930 if (struct_convention == pcc_struct_convention
2931 || (struct_convention == default_struct_convention
2932 && tdep->struct_return == pcc_struct_return))
2935 /* Structures consisting of a single `float', `double' or 'long
2936 double' member are returned in %st(0). */
2937 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2939 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2940 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2941 return (len == 4 || len == 8 || len == 12);
2944 return (len == 1 || len == 2 || len == 4 || len == 8);
2947 /* Determine, for architecture GDBARCH, how a return value of TYPE
2948 should be returned. If it is supposed to be returned in registers,
2949 and READBUF is non-zero, read the appropriate value from REGCACHE,
2950 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2951 from WRITEBUF into REGCACHE. */
2953 static enum return_value_convention
2954 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2955 struct type *type, struct regcache *regcache,
2956 gdb_byte *readbuf, const gdb_byte *writebuf)
2958 enum type_code code = TYPE_CODE (type);
2960 if (((code == TYPE_CODE_STRUCT
2961 || code == TYPE_CODE_UNION
2962 || code == TYPE_CODE_ARRAY)
2963 && !i386_reg_struct_return_p (gdbarch, type))
2964 /* Complex double and long double uses the struct return covention. */
2965 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2966 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2967 /* 128-bit decimal float uses the struct return convention. */
2968 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2970 /* The System V ABI says that:
2972 "A function that returns a structure or union also sets %eax
2973 to the value of the original address of the caller's area
2974 before it returns. Thus when the caller receives control
2975 again, the address of the returned object resides in register
2976 %eax and can be used to access the object."
2978 So the ABI guarantees that we can always find the return
2979 value just after the function has returned. */
2981 /* Note that the ABI doesn't mention functions returning arrays,
2982 which is something possible in certain languages such as Ada.
2983 In this case, the value is returned as if it was wrapped in
2984 a record, so the convention applied to records also applies
2991 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2992 read_memory (addr, readbuf, TYPE_LENGTH (type));
2995 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2998 /* This special case is for structures consisting of a single
2999 `float', `double' or 'long double' member. These structures are
3000 returned in %st(0). For these structures, we call ourselves
3001 recursively, changing TYPE into the type of the first member of
3002 the structure. Since that should work for all structures that
3003 have only one member, we don't bother to check the member's type
3005 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
3007 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
3008 return i386_return_value (gdbarch, function, type, regcache,
3013 i386_extract_return_value (gdbarch, type, regcache, readbuf);
3015 i386_store_return_value (gdbarch, type, regcache, writebuf);
3017 return RETURN_VALUE_REGISTER_CONVENTION;
3022 i387_ext_type (struct gdbarch *gdbarch)
3024 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3026 if (!tdep->i387_ext_type)
3028 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3029 gdb_assert (tdep->i387_ext_type != NULL);
3032 return tdep->i387_ext_type;
3035 /* Construct type for pseudo BND registers. We can't use
3036 tdesc_find_type since a complement of one value has to be used
3037 to describe the upper bound. */
3039 static struct type *
3040 i386_bnd_type (struct gdbarch *gdbarch)
3042 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3045 if (!tdep->i386_bnd_type)
3048 const struct builtin_type *bt = builtin_type (gdbarch);
3050 /* The type we're building is described bellow: */
3055 void *ubound; /* One complement of raw ubound field. */
3059 t = arch_composite_type (gdbarch,
3060 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3062 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3063 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3065 TYPE_NAME (t) = "builtin_type_bound128";
3066 tdep->i386_bnd_type = t;
3069 return tdep->i386_bnd_type;
3072 /* Construct vector type for pseudo ZMM registers. We can't use
3073 tdesc_find_type since ZMM isn't described in target description. */
3075 static struct type *
3076 i386_zmm_type (struct gdbarch *gdbarch)
3078 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3080 if (!tdep->i386_zmm_type)
3082 const struct builtin_type *bt = builtin_type (gdbarch);
3084 /* The type we're building is this: */
3086 union __gdb_builtin_type_vec512i
3088 int128_t uint128[4];
3089 int64_t v4_int64[8];
3090 int32_t v8_int32[16];
3091 int16_t v16_int16[32];
3092 int8_t v32_int8[64];
3093 double v4_double[8];
3100 t = arch_composite_type (gdbarch,
3101 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3102 append_composite_type_field (t, "v16_float",
3103 init_vector_type (bt->builtin_float, 16));
3104 append_composite_type_field (t, "v8_double",
3105 init_vector_type (bt->builtin_double, 8));
3106 append_composite_type_field (t, "v64_int8",
3107 init_vector_type (bt->builtin_int8, 64));
3108 append_composite_type_field (t, "v32_int16",
3109 init_vector_type (bt->builtin_int16, 32));
3110 append_composite_type_field (t, "v16_int32",
3111 init_vector_type (bt->builtin_int32, 16));
3112 append_composite_type_field (t, "v8_int64",
3113 init_vector_type (bt->builtin_int64, 8));
3114 append_composite_type_field (t, "v4_int128",
3115 init_vector_type (bt->builtin_int128, 4));
3117 TYPE_VECTOR (t) = 1;
3118 TYPE_NAME (t) = "builtin_type_vec512i";
3119 tdep->i386_zmm_type = t;
3122 return tdep->i386_zmm_type;
3125 /* Construct vector type for pseudo YMM registers. We can't use
3126 tdesc_find_type since YMM isn't described in target description. */
3128 static struct type *
3129 i386_ymm_type (struct gdbarch *gdbarch)
3131 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3133 if (!tdep->i386_ymm_type)
3135 const struct builtin_type *bt = builtin_type (gdbarch);
3137 /* The type we're building is this: */
3139 union __gdb_builtin_type_vec256i
3141 int128_t uint128[2];
3142 int64_t v2_int64[4];
3143 int32_t v4_int32[8];
3144 int16_t v8_int16[16];
3145 int8_t v16_int8[32];
3146 double v2_double[4];
3153 t = arch_composite_type (gdbarch,
3154 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3155 append_composite_type_field (t, "v8_float",
3156 init_vector_type (bt->builtin_float, 8));
3157 append_composite_type_field (t, "v4_double",
3158 init_vector_type (bt->builtin_double, 4));
3159 append_composite_type_field (t, "v32_int8",
3160 init_vector_type (bt->builtin_int8, 32));
3161 append_composite_type_field (t, "v16_int16",
3162 init_vector_type (bt->builtin_int16, 16));
3163 append_composite_type_field (t, "v8_int32",
3164 init_vector_type (bt->builtin_int32, 8));
3165 append_composite_type_field (t, "v4_int64",
3166 init_vector_type (bt->builtin_int64, 4));
3167 append_composite_type_field (t, "v2_int128",
3168 init_vector_type (bt->builtin_int128, 2));
3170 TYPE_VECTOR (t) = 1;
3171 TYPE_NAME (t) = "builtin_type_vec256i";
3172 tdep->i386_ymm_type = t;
3175 return tdep->i386_ymm_type;
3178 /* Construct vector type for MMX registers. */
3179 static struct type *
3180 i386_mmx_type (struct gdbarch *gdbarch)
3182 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3184 if (!tdep->i386_mmx_type)
3186 const struct builtin_type *bt = builtin_type (gdbarch);
3188 /* The type we're building is this: */
3190 union __gdb_builtin_type_vec64i
3193 int32_t v2_int32[2];
3194 int16_t v4_int16[4];
3201 t = arch_composite_type (gdbarch,
3202 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3204 append_composite_type_field (t, "uint64", bt->builtin_int64);
3205 append_composite_type_field (t, "v2_int32",
3206 init_vector_type (bt->builtin_int32, 2));
3207 append_composite_type_field (t, "v4_int16",
3208 init_vector_type (bt->builtin_int16, 4));
3209 append_composite_type_field (t, "v8_int8",
3210 init_vector_type (bt->builtin_int8, 8));
3212 TYPE_VECTOR (t) = 1;
3213 TYPE_NAME (t) = "builtin_type_vec64i";
3214 tdep->i386_mmx_type = t;
3217 return tdep->i386_mmx_type;
3220 /* Return the GDB type object for the "standard" data type of data in
3224 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3226 if (i386_bnd_regnum_p (gdbarch, regnum))
3227 return i386_bnd_type (gdbarch);
3228 if (i386_mmx_regnum_p (gdbarch, regnum))
3229 return i386_mmx_type (gdbarch);
3230 else if (i386_ymm_regnum_p (gdbarch, regnum))
3231 return i386_ymm_type (gdbarch);
3232 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3233 return i386_ymm_type (gdbarch);
3234 else if (i386_zmm_regnum_p (gdbarch, regnum))
3235 return i386_zmm_type (gdbarch);
3238 const struct builtin_type *bt = builtin_type (gdbarch);
3239 if (i386_byte_regnum_p (gdbarch, regnum))
3240 return bt->builtin_int8;
3241 else if (i386_word_regnum_p (gdbarch, regnum))
3242 return bt->builtin_int16;
3243 else if (i386_dword_regnum_p (gdbarch, regnum))
3244 return bt->builtin_int32;
3245 else if (i386_k_regnum_p (gdbarch, regnum))
3246 return bt->builtin_int64;
3249 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3252 /* Map a cooked register onto a raw register or memory. For the i386,
3253 the MMX registers need to be mapped onto floating point registers. */
3256 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3258 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3263 mmxreg = regnum - tdep->mm0_regnum;
3264 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3265 tos = (fstat >> 11) & 0x7;
3266 fpreg = (mmxreg + tos) % 8;
3268 return (I387_ST0_REGNUM (tdep) + fpreg);
3271 /* A helper function for us by i386_pseudo_register_read_value and
3272 amd64_pseudo_register_read_value. It does all the work but reads
3273 the data into an already-allocated value. */
3276 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3277 struct regcache *regcache,
3279 struct value *result_value)
3281 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3282 enum register_status status;
3283 gdb_byte *buf = value_contents_raw (result_value);
3285 if (i386_mmx_regnum_p (gdbarch, regnum))
3287 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3289 /* Extract (always little endian). */
3290 status = regcache_raw_read (regcache, fpnum, raw_buf);
3291 if (status != REG_VALID)
3292 mark_value_bytes_unavailable (result_value, 0,
3293 TYPE_LENGTH (value_type (result_value)));
3295 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3299 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3300 if (i386_bnd_regnum_p (gdbarch, regnum))
3302 regnum -= tdep->bnd0_regnum;
3304 /* Extract (always little endian). Read lower 128bits. */
3305 status = regcache_raw_read (regcache,
3306 I387_BND0R_REGNUM (tdep) + regnum,
3308 if (status != REG_VALID)
3309 mark_value_bytes_unavailable (result_value, 0, 16);
3312 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3313 LONGEST upper, lower;
3314 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3316 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3317 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3320 memcpy (buf, &lower, size);
3321 memcpy (buf + size, &upper, size);
3324 else if (i386_k_regnum_p (gdbarch, regnum))
3326 regnum -= tdep->k0_regnum;
3328 /* Extract (always little endian). */
3329 status = regcache_raw_read (regcache,
3330 tdep->k0_regnum + regnum,
3332 if (status != REG_VALID)
3333 mark_value_bytes_unavailable (result_value, 0, 8);
3335 memcpy (buf, raw_buf, 8);
3337 else if (i386_zmm_regnum_p (gdbarch, regnum))
3339 regnum -= tdep->zmm0_regnum;
3341 if (regnum < num_lower_zmm_regs)
3343 /* Extract (always little endian). Read lower 128bits. */
3344 status = regcache_raw_read (regcache,
3345 I387_XMM0_REGNUM (tdep) + regnum,
3347 if (status != REG_VALID)
3348 mark_value_bytes_unavailable (result_value, 0, 16);
3350 memcpy (buf, raw_buf, 16);
3352 /* Extract (always little endian). Read upper 128bits. */
3353 status = regcache_raw_read (regcache,
3354 tdep->ymm0h_regnum + regnum,
3356 if (status != REG_VALID)
3357 mark_value_bytes_unavailable (result_value, 16, 16);
3359 memcpy (buf + 16, raw_buf, 16);
3363 /* Extract (always little endian). Read lower 128bits. */
3364 status = regcache_raw_read (regcache,
3365 I387_XMM16_REGNUM (tdep) + regnum
3366 - num_lower_zmm_regs,
3368 if (status != REG_VALID)
3369 mark_value_bytes_unavailable (result_value, 0, 16);
3371 memcpy (buf, raw_buf, 16);
3373 /* Extract (always little endian). Read upper 128bits. */
3374 status = regcache_raw_read (regcache,
3375 I387_YMM16H_REGNUM (tdep) + regnum
3376 - num_lower_zmm_regs,
3378 if (status != REG_VALID)
3379 mark_value_bytes_unavailable (result_value, 16, 16);
3381 memcpy (buf + 16, raw_buf, 16);
3384 /* Read upper 256bits. */
3385 status = regcache_raw_read (regcache,
3386 tdep->zmm0h_regnum + regnum,
3388 if (status != REG_VALID)
3389 mark_value_bytes_unavailable (result_value, 32, 32);
3391 memcpy (buf + 32, raw_buf, 32);
3393 else if (i386_ymm_regnum_p (gdbarch, regnum))
3395 regnum -= tdep->ymm0_regnum;
3397 /* Extract (always little endian). Read lower 128bits. */
3398 status = regcache_raw_read (regcache,
3399 I387_XMM0_REGNUM (tdep) + regnum,
3401 if (status != REG_VALID)
3402 mark_value_bytes_unavailable (result_value, 0, 16);
3404 memcpy (buf, raw_buf, 16);
3405 /* Read upper 128bits. */
3406 status = regcache_raw_read (regcache,
3407 tdep->ymm0h_regnum + regnum,
3409 if (status != REG_VALID)
3410 mark_value_bytes_unavailable (result_value, 16, 32);
3412 memcpy (buf + 16, raw_buf, 16);
3414 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3416 regnum -= tdep->ymm16_regnum;
3417 /* Extract (always little endian). Read lower 128bits. */
3418 status = regcache_raw_read (regcache,
3419 I387_XMM16_REGNUM (tdep) + regnum,
3421 if (status != REG_VALID)
3422 mark_value_bytes_unavailable (result_value, 0, 16);
3424 memcpy (buf, raw_buf, 16);
3425 /* Read upper 128bits. */
3426 status = regcache_raw_read (regcache,
3427 tdep->ymm16h_regnum + regnum,
3429 if (status != REG_VALID)
3430 mark_value_bytes_unavailable (result_value, 16, 16);
3432 memcpy (buf + 16, raw_buf, 16);
3434 else if (i386_word_regnum_p (gdbarch, regnum))
3436 int gpnum = regnum - tdep->ax_regnum;
3438 /* Extract (always little endian). */
3439 status = regcache_raw_read (regcache, gpnum, raw_buf);
3440 if (status != REG_VALID)
3441 mark_value_bytes_unavailable (result_value, 0,
3442 TYPE_LENGTH (value_type (result_value)));
3444 memcpy (buf, raw_buf, 2);
3446 else if (i386_byte_regnum_p (gdbarch, regnum))
3448 int gpnum = regnum - tdep->al_regnum;
3450 /* Extract (always little endian). We read both lower and
3452 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3453 if (status != REG_VALID)
3454 mark_value_bytes_unavailable (result_value, 0,
3455 TYPE_LENGTH (value_type (result_value)));
3456 else if (gpnum >= 4)
3457 memcpy (buf, raw_buf + 1, 1);
3459 memcpy (buf, raw_buf, 1);
3462 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3466 static struct value *
3467 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3468 struct regcache *regcache,
3471 struct value *result;
3473 result = allocate_value (register_type (gdbarch, regnum));
3474 VALUE_LVAL (result) = lval_register;
3475 VALUE_REGNUM (result) = regnum;
3477 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3483 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3484 int regnum, const gdb_byte *buf)
3486 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3488 if (i386_mmx_regnum_p (gdbarch, regnum))
3490 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3493 regcache_raw_read (regcache, fpnum, raw_buf);
3494 /* ... Modify ... (always little endian). */
3495 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3497 regcache_raw_write (regcache, fpnum, raw_buf);
3501 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3503 if (i386_bnd_regnum_p (gdbarch, regnum))
3505 ULONGEST upper, lower;
3506 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3507 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3509 /* New values from input value. */
3510 regnum -= tdep->bnd0_regnum;
3511 lower = extract_unsigned_integer (buf, size, byte_order);
3512 upper = extract_unsigned_integer (buf + size, size, byte_order);
3514 /* Fetching register buffer. */
3515 regcache_raw_read (regcache,
3516 I387_BND0R_REGNUM (tdep) + regnum,
3521 /* Set register bits. */
3522 memcpy (raw_buf, &lower, 8);
3523 memcpy (raw_buf + 8, &upper, 8);
3526 regcache_raw_write (regcache,
3527 I387_BND0R_REGNUM (tdep) + regnum,
3530 else if (i386_k_regnum_p (gdbarch, regnum))
3532 regnum -= tdep->k0_regnum;
3534 regcache_raw_write (regcache,
3535 tdep->k0_regnum + regnum,
3538 else if (i386_zmm_regnum_p (gdbarch, regnum))
3540 regnum -= tdep->zmm0_regnum;
3542 if (regnum < num_lower_zmm_regs)
3544 /* Write lower 128bits. */
3545 regcache_raw_write (regcache,
3546 I387_XMM0_REGNUM (tdep) + regnum,
3548 /* Write upper 128bits. */
3549 regcache_raw_write (regcache,
3550 I387_YMM0_REGNUM (tdep) + regnum,
3555 /* Write lower 128bits. */
3556 regcache_raw_write (regcache,
3557 I387_XMM16_REGNUM (tdep) + regnum
3558 - num_lower_zmm_regs,
3560 /* Write upper 128bits. */
3561 regcache_raw_write (regcache,
3562 I387_YMM16H_REGNUM (tdep) + regnum
3563 - num_lower_zmm_regs,
3566 /* Write upper 256bits. */
3567 regcache_raw_write (regcache,
3568 tdep->zmm0h_regnum + regnum,
3571 else if (i386_ymm_regnum_p (gdbarch, regnum))
3573 regnum -= tdep->ymm0_regnum;
3575 /* ... Write lower 128bits. */
3576 regcache_raw_write (regcache,
3577 I387_XMM0_REGNUM (tdep) + regnum,
3579 /* ... Write upper 128bits. */
3580 regcache_raw_write (regcache,
3581 tdep->ymm0h_regnum + regnum,
3584 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3586 regnum -= tdep->ymm16_regnum;
3588 /* ... Write lower 128bits. */
3589 regcache_raw_write (regcache,
3590 I387_XMM16_REGNUM (tdep) + regnum,
3592 /* ... Write upper 128bits. */
3593 regcache_raw_write (regcache,
3594 tdep->ymm16h_regnum + regnum,
3597 else if (i386_word_regnum_p (gdbarch, regnum))
3599 int gpnum = regnum - tdep->ax_regnum;
3602 regcache_raw_read (regcache, gpnum, raw_buf);
3603 /* ... Modify ... (always little endian). */
3604 memcpy (raw_buf, buf, 2);
3606 regcache_raw_write (regcache, gpnum, raw_buf);
3608 else if (i386_byte_regnum_p (gdbarch, regnum))
3610 int gpnum = regnum - tdep->al_regnum;
3612 /* Read ... We read both lower and upper registers. */
3613 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3614 /* ... Modify ... (always little endian). */
3616 memcpy (raw_buf + 1, buf, 1);
3618 memcpy (raw_buf, buf, 1);
3620 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3623 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3627 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3630 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
3631 struct agent_expr *ax, int regnum)
3633 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3635 if (i386_mmx_regnum_p (gdbarch, regnum))
3637 /* MMX to FPU register mapping depends on current TOS. Let's just
3638 not care and collect everything... */
3641 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3642 for (i = 0; i < 8; i++)
3643 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3646 else if (i386_bnd_regnum_p (gdbarch, regnum))
3648 regnum -= tdep->bnd0_regnum;
3649 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3652 else if (i386_k_regnum_p (gdbarch, regnum))
3654 regnum -= tdep->k0_regnum;
3655 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3658 else if (i386_zmm_regnum_p (gdbarch, regnum))
3660 regnum -= tdep->zmm0_regnum;
3661 if (regnum < num_lower_zmm_regs)
3663 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3664 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3668 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
3669 - num_lower_zmm_regs);
3670 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
3671 - num_lower_zmm_regs);
3673 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3676 else if (i386_ymm_regnum_p (gdbarch, regnum))
3678 regnum -= tdep->ymm0_regnum;
3679 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3680 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3683 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3685 regnum -= tdep->ymm16_regnum;
3686 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3687 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3690 else if (i386_word_regnum_p (gdbarch, regnum))
3692 int gpnum = regnum - tdep->ax_regnum;
3694 ax_reg_mask (ax, gpnum);
3697 else if (i386_byte_regnum_p (gdbarch, regnum))
3699 int gpnum = regnum - tdep->al_regnum;
3701 ax_reg_mask (ax, gpnum % 4);
3705 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3710 /* Return the register number of the register allocated by GCC after
3711 REGNUM, or -1 if there is no such register. */
3714 i386_next_regnum (int regnum)
3716 /* GCC allocates the registers in the order:
3718 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3720 Since storing a variable in %esp doesn't make any sense we return
3721 -1 for %ebp and for %esp itself. */
3722 static int next_regnum[] =
3724 I386_EDX_REGNUM, /* Slot for %eax. */
3725 I386_EBX_REGNUM, /* Slot for %ecx. */
3726 I386_ECX_REGNUM, /* Slot for %edx. */
3727 I386_ESI_REGNUM, /* Slot for %ebx. */
3728 -1, -1, /* Slots for %esp and %ebp. */
3729 I386_EDI_REGNUM, /* Slot for %esi. */
3730 I386_EBP_REGNUM /* Slot for %edi. */
3733 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3734 return next_regnum[regnum];
3739 /* Return nonzero if a value of type TYPE stored in register REGNUM
3740 needs any special handling. */
3743 i386_convert_register_p (struct gdbarch *gdbarch,
3744 int regnum, struct type *type)
3746 int len = TYPE_LENGTH (type);
3748 /* Values may be spread across multiple registers. Most debugging
3749 formats aren't expressive enough to specify the locations, so
3750 some heuristics is involved. Right now we only handle types that
3751 have a length that is a multiple of the word size, since GCC
3752 doesn't seem to put any other types into registers. */
3753 if (len > 4 && len % 4 == 0)
3755 int last_regnum = regnum;
3759 last_regnum = i386_next_regnum (last_regnum);
3763 if (last_regnum != -1)
3767 return i387_convert_register_p (gdbarch, regnum, type);
3770 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3771 return its contents in TO. */
3774 i386_register_to_value (struct frame_info *frame, int regnum,
3775 struct type *type, gdb_byte *to,
3776 int *optimizedp, int *unavailablep)
3778 struct gdbarch *gdbarch = get_frame_arch (frame);
3779 int len = TYPE_LENGTH (type);
3781 if (i386_fp_regnum_p (gdbarch, regnum))
3782 return i387_register_to_value (frame, regnum, type, to,
3783 optimizedp, unavailablep);
3785 /* Read a value spread across multiple registers. */
3787 gdb_assert (len > 4 && len % 4 == 0);
3791 gdb_assert (regnum != -1);
3792 gdb_assert (register_size (gdbarch, regnum) == 4);
3794 if (!get_frame_register_bytes (frame, regnum, 0,
3795 register_size (gdbarch, regnum),
3796 to, optimizedp, unavailablep))
3799 regnum = i386_next_regnum (regnum);
3804 *optimizedp = *unavailablep = 0;
3808 /* Write the contents FROM of a value of type TYPE into register
3809 REGNUM in frame FRAME. */
3812 i386_value_to_register (struct frame_info *frame, int regnum,
3813 struct type *type, const gdb_byte *from)
3815 int len = TYPE_LENGTH (type);
3817 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3819 i387_value_to_register (frame, regnum, type, from);
3823 /* Write a value spread across multiple registers. */
3825 gdb_assert (len > 4 && len % 4 == 0);
3829 gdb_assert (regnum != -1);
3830 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3832 put_frame_register (frame, regnum, from);
3833 regnum = i386_next_regnum (regnum);
3839 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3840 in the general-purpose register set REGSET to register cache
3841 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3844 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3845 int regnum, const void *gregs, size_t len)
3847 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3848 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3849 const gdb_byte *regs = (const gdb_byte *) gregs;
3852 gdb_assert (len >= tdep->sizeof_gregset);
3854 for (i = 0; i < tdep->gregset_num_regs; i++)
3856 if ((regnum == i || regnum == -1)
3857 && tdep->gregset_reg_offset[i] != -1)
3858 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3862 /* Collect register REGNUM from the register cache REGCACHE and store
3863 it in the buffer specified by GREGS and LEN as described by the
3864 general-purpose register set REGSET. If REGNUM is -1, do this for
3865 all registers in REGSET. */
3868 i386_collect_gregset (const struct regset *regset,
3869 const struct regcache *regcache,
3870 int regnum, void *gregs, size_t len)
3872 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3873 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3874 gdb_byte *regs = (gdb_byte *) gregs;
3877 gdb_assert (len >= tdep->sizeof_gregset);
3879 for (i = 0; i < tdep->gregset_num_regs; i++)
3881 if ((regnum == i || regnum == -1)
3882 && tdep->gregset_reg_offset[i] != -1)
3883 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3887 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3888 in the floating-point register set REGSET to register cache
3889 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3892 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3893 int regnum, const void *fpregs, size_t len)
3895 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3896 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3898 if (len == I387_SIZEOF_FXSAVE)
3900 i387_supply_fxsave (regcache, regnum, fpregs);
3904 gdb_assert (len >= tdep->sizeof_fpregset);
3905 i387_supply_fsave (regcache, regnum, fpregs);
3908 /* Collect register REGNUM from the register cache REGCACHE and store
3909 it in the buffer specified by FPREGS and LEN as described by the
3910 floating-point register set REGSET. If REGNUM is -1, do this for
3911 all registers in REGSET. */
3914 i386_collect_fpregset (const struct regset *regset,
3915 const struct regcache *regcache,
3916 int regnum, void *fpregs, size_t len)
3918 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3919 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3921 if (len == I387_SIZEOF_FXSAVE)
3923 i387_collect_fxsave (regcache, regnum, fpregs);
3927 gdb_assert (len >= tdep->sizeof_fpregset);
3928 i387_collect_fsave (regcache, regnum, fpregs);
3931 /* Register set definitions. */
3933 const struct regset i386_gregset =
3935 NULL, i386_supply_gregset, i386_collect_gregset
3938 const struct regset i386_fpregset =
3940 NULL, i386_supply_fpregset, i386_collect_fpregset
3943 /* Default iterator over core file register note sections. */
3946 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3947 iterate_over_regset_sections_cb *cb,
3949 const struct regcache *regcache)
3951 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3953 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3954 if (tdep->sizeof_fpregset)
3955 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3959 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3962 i386_pe_skip_trampoline_code (struct frame_info *frame,
3963 CORE_ADDR pc, char *name)
3965 struct gdbarch *gdbarch = get_frame_arch (frame);
3966 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3969 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3971 unsigned long indirect =
3972 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3973 struct minimal_symbol *indsym =
3974 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3975 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3979 if (startswith (symname, "__imp_")
3980 || startswith (symname, "_imp_"))
3982 read_memory_unsigned_integer (indirect, 4, byte_order);
3985 return 0; /* Not a trampoline. */
3989 /* Return whether the THIS_FRAME corresponds to a sigtramp
3993 i386_sigtramp_p (struct frame_info *this_frame)
3995 CORE_ADDR pc = get_frame_pc (this_frame);
3998 find_pc_partial_function (pc, &name, NULL, NULL);
3999 return (name && strcmp ("_sigtramp", name) == 0);
4003 /* We have two flavours of disassembly. The machinery on this page
4004 deals with switching between those. */
4007 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
4009 gdb_assert (disassembly_flavor == att_flavor
4010 || disassembly_flavor == intel_flavor);
4012 info->disassembler_options = disassembly_flavor;
4014 return print_insn_i386 (pc, info);
4018 /* There are a few i386 architecture variants that differ only
4019 slightly from the generic i386 target. For now, we don't give them
4020 their own source file, but include them here. As a consequence,
4021 they'll always be included. */
4023 /* System V Release 4 (SVR4). */
4025 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4029 i386_svr4_sigtramp_p (struct frame_info *this_frame)
4031 CORE_ADDR pc = get_frame_pc (this_frame);
4034 /* The origin of these symbols is currently unknown. */
4035 find_pc_partial_function (pc, &name, NULL, NULL);
4036 return (name && (strcmp ("_sigreturn", name) == 0
4037 || strcmp ("sigvechandler", name) == 0));
4040 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4041 address of the associated sigcontext (ucontext) structure. */
4044 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
4046 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4047 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4051 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4052 sp = extract_unsigned_integer (buf, 4, byte_order);
4054 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4059 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4063 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
4065 return (*s == '$' /* Literal number. */
4066 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4067 || (*s == '(' && s[1] == '%') /* Register indirection. */
4068 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4071 /* Helper function for i386_stap_parse_special_token.
4073 This function parses operands of the form `-8+3+1(%rbp)', which
4074 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4076 Return 1 if the operand was parsed successfully, zero
4080 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
4081 struct stap_parse_info *p)
4083 const char *s = p->arg;
4085 if (isdigit (*s) || *s == '-' || *s == '+')
4089 long displacements[3];
4105 if (!isdigit ((unsigned char) *s))
4108 displacements[0] = strtol (s, &endp, 10);
4111 if (*s != '+' && *s != '-')
4113 /* We are not dealing with a triplet. */
4126 if (!isdigit ((unsigned char) *s))
4129 displacements[1] = strtol (s, &endp, 10);
4132 if (*s != '+' && *s != '-')
4134 /* We are not dealing with a triplet. */
4147 if (!isdigit ((unsigned char) *s))
4150 displacements[2] = strtol (s, &endp, 10);
4153 if (*s != '(' || s[1] != '%')
4159 while (isalnum (*s))
4165 len = s - start - 1;
4166 regname = (char *) alloca (len + 1);
4168 strncpy (regname, start, len);
4169 regname[len] = '\0';
4171 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4172 error (_("Invalid register name `%s' on expression `%s'."),
4173 regname, p->saved_arg);
4175 for (i = 0; i < 3; i++)
4177 write_exp_elt_opcode (&p->pstate, OP_LONG);
4179 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4180 write_exp_elt_longcst (&p->pstate, displacements[i]);
4181 write_exp_elt_opcode (&p->pstate, OP_LONG);
4183 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4186 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4189 write_exp_string (&p->pstate, str);
4190 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4192 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4193 write_exp_elt_type (&p->pstate,
4194 builtin_type (gdbarch)->builtin_data_ptr);
4195 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4197 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4198 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4199 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4201 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4202 write_exp_elt_type (&p->pstate,
4203 lookup_pointer_type (p->arg_type));
4204 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4206 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4216 /* Helper function for i386_stap_parse_special_token.
4218 This function parses operands of the form `register base +
4219 (register index * size) + offset', as represented in
4220 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4222 Return 1 if the operand was parsed successfully, zero
4226 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4227 struct stap_parse_info *p)
4229 const char *s = p->arg;
4231 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4233 int offset_minus = 0;
4242 struct stoken base_token, index_token;
4252 if (offset_minus && !isdigit (*s))
4259 offset = strtol (s, &endp, 10);
4263 if (*s != '(' || s[1] != '%')
4269 while (isalnum (*s))
4272 if (*s != ',' || s[1] != '%')
4275 len_base = s - start;
4276 base = (char *) alloca (len_base + 1);
4277 strncpy (base, start, len_base);
4278 base[len_base] = '\0';
4280 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4281 error (_("Invalid register name `%s' on expression `%s'."),
4282 base, p->saved_arg);
4287 while (isalnum (*s))
4290 len_index = s - start;
4291 index = (char *) alloca (len_index + 1);
4292 strncpy (index, start, len_index);
4293 index[len_index] = '\0';
4295 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4296 error (_("Invalid register name `%s' on expression `%s'."),
4297 index, p->saved_arg);
4299 if (*s != ',' && *s != ')')
4315 size = strtol (s, &endp, 10);
4326 write_exp_elt_opcode (&p->pstate, OP_LONG);
4327 write_exp_elt_type (&p->pstate,
4328 builtin_type (gdbarch)->builtin_long);
4329 write_exp_elt_longcst (&p->pstate, offset);
4330 write_exp_elt_opcode (&p->pstate, OP_LONG);
4332 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4335 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4336 base_token.ptr = base;
4337 base_token.length = len_base;
4338 write_exp_string (&p->pstate, base_token);
4339 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4342 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4344 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4345 index_token.ptr = index;
4346 index_token.length = len_index;
4347 write_exp_string (&p->pstate, index_token);
4348 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4352 write_exp_elt_opcode (&p->pstate, OP_LONG);
4353 write_exp_elt_type (&p->pstate,
4354 builtin_type (gdbarch)->builtin_long);
4355 write_exp_elt_longcst (&p->pstate, size);
4356 write_exp_elt_opcode (&p->pstate, OP_LONG);
4358 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4359 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4362 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4364 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4365 write_exp_elt_type (&p->pstate,
4366 lookup_pointer_type (p->arg_type));
4367 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4369 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4379 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4383 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4384 struct stap_parse_info *p)
4386 /* In order to parse special tokens, we use a state-machine that go
4387 through every known token and try to get a match. */
4391 THREE_ARG_DISPLACEMENT,
4396 current_state = TRIPLET;
4398 /* The special tokens to be parsed here are:
4400 - `register base + (register index * size) + offset', as represented
4401 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4403 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4404 `*(-8 + 3 - 1 + (void *) $eax)'. */
4406 while (current_state != DONE)
4408 switch (current_state)
4411 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4415 case THREE_ARG_DISPLACEMENT:
4416 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4421 /* Advancing to the next state. */
4430 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4431 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4434 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4436 return "(x86_64|i.86)";
4444 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4446 static const char *const stap_integer_prefixes[] = { "$", NULL };
4447 static const char *const stap_register_prefixes[] = { "%", NULL };
4448 static const char *const stap_register_indirection_prefixes[] = { "(",
4450 static const char *const stap_register_indirection_suffixes[] = { ")",
4453 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4454 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4456 /* Registering SystemTap handlers. */
4457 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4458 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4459 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4460 stap_register_indirection_prefixes);
4461 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4462 stap_register_indirection_suffixes);
4463 set_gdbarch_stap_is_single_operand (gdbarch,
4464 i386_stap_is_single_operand);
4465 set_gdbarch_stap_parse_special_token (gdbarch,
4466 i386_stap_parse_special_token);
4469 /* System V Release 4 (SVR4). */
4472 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4474 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4476 /* System V Release 4 uses ELF. */
4477 i386_elf_init_abi (info, gdbarch);
4479 /* System V Release 4 has shared libraries. */
4480 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4482 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4483 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4484 tdep->sc_pc_offset = 36 + 14 * 4;
4485 tdep->sc_sp_offset = 36 + 17 * 4;
4487 tdep->jb_pc_offset = 20;
4493 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4495 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4497 /* DJGPP doesn't have any special frames for signal handlers. */
4498 tdep->sigtramp_p = NULL;
4500 tdep->jb_pc_offset = 36;
4502 /* DJGPP does not support the SSE registers. */
4503 if (! tdesc_has_registers (info.target_desc))
4504 tdep->tdesc = tdesc_i386_mmx;
4506 /* Native compiler is GCC, which uses the SVR4 register numbering
4507 even in COFF and STABS. See the comment in i386_gdbarch_init,
4508 before the calls to set_gdbarch_stab_reg_to_regnum and
4509 set_gdbarch_sdb_reg_to_regnum. */
4510 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4511 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4513 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4515 set_gdbarch_wchar_bit (gdbarch, 16);
4516 set_gdbarch_wchar_signed (gdbarch, 0);
4520 /* i386 register groups. In addition to the normal groups, add "mmx"
4523 static struct reggroup *i386_sse_reggroup;
4524 static struct reggroup *i386_mmx_reggroup;
4527 i386_init_reggroups (void)
4529 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4530 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4534 i386_add_reggroups (struct gdbarch *gdbarch)
4536 reggroup_add (gdbarch, i386_sse_reggroup);
4537 reggroup_add (gdbarch, i386_mmx_reggroup);
4538 reggroup_add (gdbarch, general_reggroup);
4539 reggroup_add (gdbarch, float_reggroup);
4540 reggroup_add (gdbarch, all_reggroup);
4541 reggroup_add (gdbarch, save_reggroup);
4542 reggroup_add (gdbarch, restore_reggroup);
4543 reggroup_add (gdbarch, vector_reggroup);
4544 reggroup_add (gdbarch, system_reggroup);
4548 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4549 struct reggroup *group)
4551 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4552 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4553 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4554 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4555 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4556 avx512_p, avx_p, sse_p, pkru_regnum_p;
4558 /* Don't include pseudo registers, except for MMX, in any register
4560 if (i386_byte_regnum_p (gdbarch, regnum))
4563 if (i386_word_regnum_p (gdbarch, regnum))
4566 if (i386_dword_regnum_p (gdbarch, regnum))
4569 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4570 if (group == i386_mmx_reggroup)
4571 return mmx_regnum_p;
4573 pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum);
4574 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4575 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4576 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4577 if (group == i386_sse_reggroup)
4578 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4580 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4581 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4582 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4584 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4585 == X86_XSTATE_AVX_AVX512_MASK);
4586 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4587 == X86_XSTATE_AVX_MASK) && !avx512_p;
4588 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4589 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4591 if (group == vector_reggroup)
4592 return (mmx_regnum_p
4593 || (zmm_regnum_p && avx512_p)
4594 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4595 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4598 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4599 || i386_fpc_regnum_p (gdbarch, regnum));
4600 if (group == float_reggroup)
4603 /* For "info reg all", don't include upper YMM registers nor XMM
4604 registers when AVX is supported. */
4605 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4606 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4607 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4608 if (group == all_reggroup
4609 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4610 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4612 || ymmh_avx512_regnum_p
4616 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4617 if (group == all_reggroup
4618 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4619 return bnd_regnum_p;
4621 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4622 if (group == all_reggroup
4623 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4626 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4627 if (group == all_reggroup
4628 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4629 return mpx_ctrl_regnum_p;
4631 if (group == general_reggroup)
4632 return (!fp_regnum_p
4636 && !xmm_avx512_regnum_p
4639 && !ymm_avx512_regnum_p
4640 && !ymmh_avx512_regnum_p
4643 && !mpx_ctrl_regnum_p
4648 return default_register_reggroup_p (gdbarch, regnum, group);
4652 /* Get the ARGIth function argument for the current function. */
4655 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4658 struct gdbarch *gdbarch = get_frame_arch (frame);
4659 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4660 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4661 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4664 #define PREFIX_REPZ 0x01
4665 #define PREFIX_REPNZ 0x02
4666 #define PREFIX_LOCK 0x04
4667 #define PREFIX_DATA 0x08
4668 #define PREFIX_ADDR 0x10
4680 /* i386 arith/logic operations */
4693 struct i386_record_s
4695 struct gdbarch *gdbarch;
4696 struct regcache *regcache;
4697 CORE_ADDR orig_addr;
4703 uint8_t mod, reg, rm;
4712 /* Parse the "modrm" part of the memory address irp->addr points at.
4713 Returns -1 if something goes wrong, 0 otherwise. */
4716 i386_record_modrm (struct i386_record_s *irp)
4718 struct gdbarch *gdbarch = irp->gdbarch;
4720 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4724 irp->mod = (irp->modrm >> 6) & 3;
4725 irp->reg = (irp->modrm >> 3) & 7;
4726 irp->rm = irp->modrm & 7;
4731 /* Extract the memory address that the current instruction writes to,
4732 and return it in *ADDR. Return -1 if something goes wrong. */
4735 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4737 struct gdbarch *gdbarch = irp->gdbarch;
4738 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4743 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4750 uint8_t base = irp->rm;
4755 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4758 scale = (byte >> 6) & 3;
4759 index = ((byte >> 3) & 7) | irp->rex_x;
4767 if ((base & 7) == 5)
4770 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4773 *addr = extract_signed_integer (buf, 4, byte_order);
4774 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4775 *addr += irp->addr + irp->rip_offset;
4779 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4782 *addr = (int8_t) buf[0];
4785 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4787 *addr = extract_signed_integer (buf, 4, byte_order);
4795 if (base == 4 && irp->popl_esp_hack)
4796 *addr += irp->popl_esp_hack;
4797 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4800 if (irp->aflag == 2)
4805 *addr = (uint32_t) (offset64 + *addr);
4807 if (havesib && (index != 4 || scale != 0))
4809 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4811 if (irp->aflag == 2)
4812 *addr += offset64 << scale;
4814 *addr = (uint32_t) (*addr + (offset64 << scale));
4819 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4820 address from 32-bit to 64-bit. */
4821 *addr = (uint32_t) *addr;
4832 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4835 *addr = extract_signed_integer (buf, 2, byte_order);
4841 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4844 *addr = (int8_t) buf[0];
4847 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4850 *addr = extract_signed_integer (buf, 2, byte_order);
4857 regcache_raw_read_unsigned (irp->regcache,
4858 irp->regmap[X86_RECORD_REBX_REGNUM],
4860 *addr = (uint32_t) (*addr + offset64);
4861 regcache_raw_read_unsigned (irp->regcache,
4862 irp->regmap[X86_RECORD_RESI_REGNUM],
4864 *addr = (uint32_t) (*addr + offset64);
4867 regcache_raw_read_unsigned (irp->regcache,
4868 irp->regmap[X86_RECORD_REBX_REGNUM],
4870 *addr = (uint32_t) (*addr + offset64);
4871 regcache_raw_read_unsigned (irp->regcache,
4872 irp->regmap[X86_RECORD_REDI_REGNUM],
4874 *addr = (uint32_t) (*addr + offset64);
4877 regcache_raw_read_unsigned (irp->regcache,
4878 irp->regmap[X86_RECORD_REBP_REGNUM],
4880 *addr = (uint32_t) (*addr + offset64);
4881 regcache_raw_read_unsigned (irp->regcache,
4882 irp->regmap[X86_RECORD_RESI_REGNUM],
4884 *addr = (uint32_t) (*addr + offset64);
4887 regcache_raw_read_unsigned (irp->regcache,
4888 irp->regmap[X86_RECORD_REBP_REGNUM],
4890 *addr = (uint32_t) (*addr + offset64);
4891 regcache_raw_read_unsigned (irp->regcache,
4892 irp->regmap[X86_RECORD_REDI_REGNUM],
4894 *addr = (uint32_t) (*addr + offset64);
4897 regcache_raw_read_unsigned (irp->regcache,
4898 irp->regmap[X86_RECORD_RESI_REGNUM],
4900 *addr = (uint32_t) (*addr + offset64);
4903 regcache_raw_read_unsigned (irp->regcache,
4904 irp->regmap[X86_RECORD_REDI_REGNUM],
4906 *addr = (uint32_t) (*addr + offset64);
4909 regcache_raw_read_unsigned (irp->regcache,
4910 irp->regmap[X86_RECORD_REBP_REGNUM],
4912 *addr = (uint32_t) (*addr + offset64);
4915 regcache_raw_read_unsigned (irp->regcache,
4916 irp->regmap[X86_RECORD_REBX_REGNUM],
4918 *addr = (uint32_t) (*addr + offset64);
4928 /* Record the address and contents of the memory that will be changed
4929 by the current instruction. Return -1 if something goes wrong, 0
4933 i386_record_lea_modrm (struct i386_record_s *irp)
4935 struct gdbarch *gdbarch = irp->gdbarch;
4938 if (irp->override >= 0)
4940 if (record_full_memory_query)
4943 Process record ignores the memory change of instruction at address %s\n\
4944 because it can't get the value of the segment register.\n\
4945 Do you want to stop the program?"),
4946 paddress (gdbarch, irp->orig_addr)))
4953 if (i386_record_lea_modrm_addr (irp, &addr))
4956 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4962 /* Record the effects of a push operation. Return -1 if something
4963 goes wrong, 0 otherwise. */
4966 i386_record_push (struct i386_record_s *irp, int size)
4970 if (record_full_arch_list_add_reg (irp->regcache,
4971 irp->regmap[X86_RECORD_RESP_REGNUM]))
4973 regcache_raw_read_unsigned (irp->regcache,
4974 irp->regmap[X86_RECORD_RESP_REGNUM],
4976 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4983 /* Defines contents to record. */
4984 #define I386_SAVE_FPU_REGS 0xfffd
4985 #define I386_SAVE_FPU_ENV 0xfffe
4986 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4988 /* Record the values of the floating point registers which will be
4989 changed by the current instruction. Returns -1 if something is
4990 wrong, 0 otherwise. */
4992 static int i386_record_floats (struct gdbarch *gdbarch,
4993 struct i386_record_s *ir,
4996 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4999 /* Oza: Because of floating point insn push/pop of fpu stack is going to
5000 happen. Currently we store st0-st7 registers, but we need not store all
5001 registers all the time, in future we use ftag register and record only
5002 those who are not marked as an empty. */
5004 if (I386_SAVE_FPU_REGS == iregnum)
5006 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
5008 if (record_full_arch_list_add_reg (ir->regcache, i))
5012 else if (I386_SAVE_FPU_ENV == iregnum)
5014 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5016 if (record_full_arch_list_add_reg (ir->regcache, i))
5020 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
5022 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5024 if (record_full_arch_list_add_reg (ir->regcache, i))
5028 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
5029 (iregnum <= I387_FOP_REGNUM (tdep)))
5031 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
5036 /* Parameter error. */
5039 if(I386_SAVE_FPU_ENV != iregnum)
5041 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5043 if (record_full_arch_list_add_reg (ir->regcache, i))
5050 /* Parse the current instruction, and record the values of the
5051 registers and memory that will be changed by the current
5052 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5054 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5055 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5058 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5059 CORE_ADDR input_addr)
5061 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5067 gdb_byte buf[I386_MAX_REGISTER_SIZE];
5068 struct i386_record_s ir;
5069 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5073 memset (&ir, 0, sizeof (struct i386_record_s));
5074 ir.regcache = regcache;
5075 ir.addr = input_addr;
5076 ir.orig_addr = input_addr;
5080 ir.popl_esp_hack = 0;
5081 ir.regmap = tdep->record_regmap;
5082 ir.gdbarch = gdbarch;
5084 if (record_debug > 1)
5085 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5087 paddress (gdbarch, ir.addr));
5092 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5095 switch (opcode8) /* Instruction prefixes */
5097 case REPE_PREFIX_OPCODE:
5098 prefixes |= PREFIX_REPZ;
5100 case REPNE_PREFIX_OPCODE:
5101 prefixes |= PREFIX_REPNZ;
5103 case LOCK_PREFIX_OPCODE:
5104 prefixes |= PREFIX_LOCK;
5106 case CS_PREFIX_OPCODE:
5107 ir.override = X86_RECORD_CS_REGNUM;
5109 case SS_PREFIX_OPCODE:
5110 ir.override = X86_RECORD_SS_REGNUM;
5112 case DS_PREFIX_OPCODE:
5113 ir.override = X86_RECORD_DS_REGNUM;
5115 case ES_PREFIX_OPCODE:
5116 ir.override = X86_RECORD_ES_REGNUM;
5118 case FS_PREFIX_OPCODE:
5119 ir.override = X86_RECORD_FS_REGNUM;
5121 case GS_PREFIX_OPCODE:
5122 ir.override = X86_RECORD_GS_REGNUM;
5124 case DATA_PREFIX_OPCODE:
5125 prefixes |= PREFIX_DATA;
5127 case ADDR_PREFIX_OPCODE:
5128 prefixes |= PREFIX_ADDR;
5130 case 0x40: /* i386 inc %eax */
5131 case 0x41: /* i386 inc %ecx */
5132 case 0x42: /* i386 inc %edx */
5133 case 0x43: /* i386 inc %ebx */
5134 case 0x44: /* i386 inc %esp */
5135 case 0x45: /* i386 inc %ebp */
5136 case 0x46: /* i386 inc %esi */
5137 case 0x47: /* i386 inc %edi */
5138 case 0x48: /* i386 dec %eax */
5139 case 0x49: /* i386 dec %ecx */
5140 case 0x4a: /* i386 dec %edx */
5141 case 0x4b: /* i386 dec %ebx */
5142 case 0x4c: /* i386 dec %esp */
5143 case 0x4d: /* i386 dec %ebp */
5144 case 0x4e: /* i386 dec %esi */
5145 case 0x4f: /* i386 dec %edi */
5146 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5149 rex_w = (opcode8 >> 3) & 1;
5150 rex_r = (opcode8 & 0x4) << 1;
5151 ir.rex_x = (opcode8 & 0x2) << 2;
5152 ir.rex_b = (opcode8 & 0x1) << 3;
5154 else /* 32 bit target */
5163 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5169 if (prefixes & PREFIX_DATA)
5172 if (prefixes & PREFIX_ADDR)
5174 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5177 /* Now check op code. */
5178 opcode = (uint32_t) opcode8;
5183 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5186 opcode = (uint32_t) opcode8 | 0x0f00;
5190 case 0x00: /* arith & logic */
5238 if (((opcode >> 3) & 7) != OP_CMPL)
5240 if ((opcode & 1) == 0)
5243 ir.ot = ir.dflag + OT_WORD;
5245 switch ((opcode >> 1) & 3)
5247 case 0: /* OP Ev, Gv */
5248 if (i386_record_modrm (&ir))
5252 if (i386_record_lea_modrm (&ir))
5258 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5263 case 1: /* OP Gv, Ev */
5264 if (i386_record_modrm (&ir))
5267 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5269 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5271 case 2: /* OP A, Iv */
5272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5276 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5279 case 0x80: /* GRP1 */
5283 if (i386_record_modrm (&ir))
5286 if (ir.reg != OP_CMPL)
5288 if ((opcode & 1) == 0)
5291 ir.ot = ir.dflag + OT_WORD;
5298 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5299 if (i386_record_lea_modrm (&ir))
5303 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5305 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5308 case 0x40: /* inc */
5317 case 0x48: /* dec */
5326 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5327 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5330 case 0xf6: /* GRP3 */
5332 if ((opcode & 1) == 0)
5335 ir.ot = ir.dflag + OT_WORD;
5336 if (i386_record_modrm (&ir))
5339 if (ir.mod != 3 && ir.reg == 0)
5340 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5351 if (i386_record_lea_modrm (&ir))
5357 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5359 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5361 if (ir.reg == 3) /* neg */
5362 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5368 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5369 if (ir.ot != OT_BYTE)
5370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5375 opcode = opcode << 8 | ir.modrm;
5381 case 0xfe: /* GRP4 */
5382 case 0xff: /* GRP5 */
5383 if (i386_record_modrm (&ir))
5385 if (ir.reg >= 2 && opcode == 0xfe)
5388 opcode = opcode << 8 | ir.modrm;
5395 if ((opcode & 1) == 0)
5398 ir.ot = ir.dflag + OT_WORD;
5401 if (i386_record_lea_modrm (&ir))
5407 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5409 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5411 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5414 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5416 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5421 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5422 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5431 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5433 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5438 opcode = opcode << 8 | ir.modrm;
5444 case 0x84: /* test */
5448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5451 case 0x98: /* CWDE/CBW */
5452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5455 case 0x99: /* CDQ/CWD */
5456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5460 case 0x0faf: /* imul */
5463 ir.ot = ir.dflag + OT_WORD;
5464 if (i386_record_modrm (&ir))
5467 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5468 else if (opcode == 0x6b)
5471 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5474 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5477 case 0x0fc0: /* xadd */
5479 if ((opcode & 1) == 0)
5482 ir.ot = ir.dflag + OT_WORD;
5483 if (i386_record_modrm (&ir))
5488 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5490 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5491 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5497 if (i386_record_lea_modrm (&ir))
5499 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5506 case 0x0fb0: /* cmpxchg */
5508 if ((opcode & 1) == 0)
5511 ir.ot = ir.dflag + OT_WORD;
5512 if (i386_record_modrm (&ir))
5517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5518 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5524 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5525 if (i386_record_lea_modrm (&ir))
5528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5531 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5532 if (i386_record_modrm (&ir))
5536 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5537 an extended opcode. rdrand has bits 110 (/6) and rdseed
5538 has bits 111 (/7). */
5539 if (ir.reg == 6 || ir.reg == 7)
5541 /* The storage register is described by the 3 R/M bits, but the
5542 REX.B prefix may be used to give access to registers
5543 R8~R15. In this case ir.rex_b + R/M will give us the register
5544 in the range R8~R15.
5546 REX.W may also be used to access 64-bit registers, but we
5547 already record entire registers and not just partial bits
5549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm);
5550 /* These instructions also set conditional bits. */
5551 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5556 /* We don't handle this particular instruction yet. */
5558 opcode = opcode << 8 | ir.modrm;
5562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5564 if (i386_record_lea_modrm (&ir))
5566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5569 case 0x50: /* push */
5579 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5581 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5585 case 0x06: /* push es */
5586 case 0x0e: /* push cs */
5587 case 0x16: /* push ss */
5588 case 0x1e: /* push ds */
5589 if (ir.regmap[X86_RECORD_R8_REGNUM])
5594 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5598 case 0x0fa0: /* push fs */
5599 case 0x0fa8: /* push gs */
5600 if (ir.regmap[X86_RECORD_R8_REGNUM])
5605 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5609 case 0x60: /* pusha */
5610 if (ir.regmap[X86_RECORD_R8_REGNUM])
5615 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5619 case 0x58: /* pop */
5627 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5628 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5631 case 0x61: /* popa */
5632 if (ir.regmap[X86_RECORD_R8_REGNUM])
5637 for (regnum = X86_RECORD_REAX_REGNUM;
5638 regnum <= X86_RECORD_REDI_REGNUM;
5640 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5643 case 0x8f: /* pop */
5644 if (ir.regmap[X86_RECORD_R8_REGNUM])
5645 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5647 ir.ot = ir.dflag + OT_WORD;
5648 if (i386_record_modrm (&ir))
5651 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5654 ir.popl_esp_hack = 1 << ir.ot;
5655 if (i386_record_lea_modrm (&ir))
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5661 case 0xc8: /* enter */
5662 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5663 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5665 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5669 case 0xc9: /* leave */
5670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5674 case 0x07: /* pop es */
5675 if (ir.regmap[X86_RECORD_R8_REGNUM])
5680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5685 case 0x17: /* pop ss */
5686 if (ir.regmap[X86_RECORD_R8_REGNUM])
5691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5693 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5696 case 0x1f: /* pop ds */
5697 if (ir.regmap[X86_RECORD_R8_REGNUM])
5702 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5703 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5707 case 0x0fa1: /* pop fs */
5708 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5709 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5710 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5713 case 0x0fa9: /* pop gs */
5714 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5715 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5719 case 0x88: /* mov */
5723 if ((opcode & 1) == 0)
5726 ir.ot = ir.dflag + OT_WORD;
5728 if (i386_record_modrm (&ir))
5733 if (opcode == 0xc6 || opcode == 0xc7)
5734 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5735 if (i386_record_lea_modrm (&ir))
5740 if (opcode == 0xc6 || opcode == 0xc7)
5742 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5744 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5748 case 0x8a: /* mov */
5750 if ((opcode & 1) == 0)
5753 ir.ot = ir.dflag + OT_WORD;
5754 if (i386_record_modrm (&ir))
5757 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5759 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5762 case 0x8c: /* mov seg */
5763 if (i386_record_modrm (&ir))
5768 opcode = opcode << 8 | ir.modrm;
5773 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5777 if (i386_record_lea_modrm (&ir))
5782 case 0x8e: /* mov seg */
5783 if (i386_record_modrm (&ir))
5788 regnum = X86_RECORD_ES_REGNUM;
5791 regnum = X86_RECORD_SS_REGNUM;
5794 regnum = X86_RECORD_DS_REGNUM;
5797 regnum = X86_RECORD_FS_REGNUM;
5800 regnum = X86_RECORD_GS_REGNUM;
5804 opcode = opcode << 8 | ir.modrm;
5808 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5812 case 0x0fb6: /* movzbS */
5813 case 0x0fb7: /* movzwS */
5814 case 0x0fbe: /* movsbS */
5815 case 0x0fbf: /* movswS */
5816 if (i386_record_modrm (&ir))
5818 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5821 case 0x8d: /* lea */
5822 if (i386_record_modrm (&ir))
5827 opcode = opcode << 8 | ir.modrm;
5832 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5834 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5837 case 0xa0: /* mov EAX */
5840 case 0xd7: /* xlat */
5841 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5844 case 0xa2: /* mov EAX */
5846 if (ir.override >= 0)
5848 if (record_full_memory_query)
5851 Process record ignores the memory change of instruction at address %s\n\
5852 because it can't get the value of the segment register.\n\
5853 Do you want to stop the program?"),
5854 paddress (gdbarch, ir.orig_addr)))
5860 if ((opcode & 1) == 0)
5863 ir.ot = ir.dflag + OT_WORD;
5866 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5869 addr = extract_unsigned_integer (buf, 8, byte_order);
5873 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5876 addr = extract_unsigned_integer (buf, 4, byte_order);
5880 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5883 addr = extract_unsigned_integer (buf, 2, byte_order);
5885 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5890 case 0xb0: /* mov R, Ib */
5898 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5899 ? ((opcode & 0x7) | ir.rex_b)
5900 : ((opcode & 0x7) & 0x3));
5903 case 0xb8: /* mov R, Iv */
5911 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5914 case 0x91: /* xchg R, EAX */
5921 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5922 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5925 case 0x86: /* xchg Ev, Gv */
5927 if ((opcode & 1) == 0)
5930 ir.ot = ir.dflag + OT_WORD;
5931 if (i386_record_modrm (&ir))
5936 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5938 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5942 if (i386_record_lea_modrm (&ir))
5946 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5948 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5951 case 0xc4: /* les Gv */
5952 case 0xc5: /* lds Gv */
5953 if (ir.regmap[X86_RECORD_R8_REGNUM])
5959 case 0x0fb2: /* lss Gv */
5960 case 0x0fb4: /* lfs Gv */
5961 case 0x0fb5: /* lgs Gv */
5962 if (i386_record_modrm (&ir))
5970 opcode = opcode << 8 | ir.modrm;
5975 case 0xc4: /* les Gv */
5976 regnum = X86_RECORD_ES_REGNUM;
5978 case 0xc5: /* lds Gv */
5979 regnum = X86_RECORD_DS_REGNUM;
5981 case 0x0fb2: /* lss Gv */
5982 regnum = X86_RECORD_SS_REGNUM;
5984 case 0x0fb4: /* lfs Gv */
5985 regnum = X86_RECORD_FS_REGNUM;
5987 case 0x0fb5: /* lgs Gv */
5988 regnum = X86_RECORD_GS_REGNUM;
5991 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5993 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5996 case 0xc0: /* shifts */
6002 if ((opcode & 1) == 0)
6005 ir.ot = ir.dflag + OT_WORD;
6006 if (i386_record_modrm (&ir))
6008 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
6010 if (i386_record_lea_modrm (&ir))
6016 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
6018 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
6020 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6027 if (i386_record_modrm (&ir))
6031 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
6036 if (i386_record_lea_modrm (&ir))
6041 case 0xd8: /* Floats. */
6049 if (i386_record_modrm (&ir))
6051 ir.reg |= ((opcode & 7) << 3);
6057 if (i386_record_lea_modrm_addr (&ir, &addr64))
6065 /* For fcom, ficom nothing to do. */
6071 /* For fcomp, ficomp pop FPU stack, store all. */
6072 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6099 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6100 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6101 of code, always affects st(0) register. */
6102 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6126 /* Handling fld, fild. */
6127 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6131 switch (ir.reg >> 4)
6134 if (record_full_arch_list_add_mem (addr64, 4))
6138 if (record_full_arch_list_add_mem (addr64, 8))
6144 if (record_full_arch_list_add_mem (addr64, 2))
6150 switch (ir.reg >> 4)
6153 if (record_full_arch_list_add_mem (addr64, 4))
6155 if (3 == (ir.reg & 7))
6157 /* For fstp m32fp. */
6158 if (i386_record_floats (gdbarch, &ir,
6159 I386_SAVE_FPU_REGS))
6164 if (record_full_arch_list_add_mem (addr64, 4))
6166 if ((3 == (ir.reg & 7))
6167 || (5 == (ir.reg & 7))
6168 || (7 == (ir.reg & 7)))
6170 /* For fstp insn. */
6171 if (i386_record_floats (gdbarch, &ir,
6172 I386_SAVE_FPU_REGS))
6177 if (record_full_arch_list_add_mem (addr64, 8))
6179 if (3 == (ir.reg & 7))
6181 /* For fstp m64fp. */
6182 if (i386_record_floats (gdbarch, &ir,
6183 I386_SAVE_FPU_REGS))
6188 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6190 /* For fistp, fbld, fild, fbstp. */
6191 if (i386_record_floats (gdbarch, &ir,
6192 I386_SAVE_FPU_REGS))
6197 if (record_full_arch_list_add_mem (addr64, 2))
6206 if (i386_record_floats (gdbarch, &ir,
6207 I386_SAVE_FPU_ENV_REG_STACK))
6212 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6217 if (i386_record_floats (gdbarch, &ir,
6218 I386_SAVE_FPU_ENV_REG_STACK))
6224 if (record_full_arch_list_add_mem (addr64, 28))
6229 if (record_full_arch_list_add_mem (addr64, 14))
6235 if (record_full_arch_list_add_mem (addr64, 2))
6237 /* Insn fstp, fbstp. */
6238 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6243 if (record_full_arch_list_add_mem (addr64, 10))
6249 if (record_full_arch_list_add_mem (addr64, 28))
6255 if (record_full_arch_list_add_mem (addr64, 14))
6259 if (record_full_arch_list_add_mem (addr64, 80))
6262 if (i386_record_floats (gdbarch, &ir,
6263 I386_SAVE_FPU_ENV_REG_STACK))
6267 if (record_full_arch_list_add_mem (addr64, 8))
6270 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6275 opcode = opcode << 8 | ir.modrm;
6280 /* Opcode is an extension of modR/M byte. */
6286 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6290 if (0x0c == (ir.modrm >> 4))
6292 if ((ir.modrm & 0x0f) <= 7)
6294 if (i386_record_floats (gdbarch, &ir,
6295 I386_SAVE_FPU_REGS))
6300 if (i386_record_floats (gdbarch, &ir,
6301 I387_ST0_REGNUM (tdep)))
6303 /* If only st(0) is changing, then we have already
6305 if ((ir.modrm & 0x0f) - 0x08)
6307 if (i386_record_floats (gdbarch, &ir,
6308 I387_ST0_REGNUM (tdep) +
6309 ((ir.modrm & 0x0f) - 0x08)))
6327 if (i386_record_floats (gdbarch, &ir,
6328 I387_ST0_REGNUM (tdep)))
6346 if (i386_record_floats (gdbarch, &ir,
6347 I386_SAVE_FPU_REGS))
6351 if (i386_record_floats (gdbarch, &ir,
6352 I387_ST0_REGNUM (tdep)))
6354 if (i386_record_floats (gdbarch, &ir,
6355 I387_ST0_REGNUM (tdep) + 1))
6362 if (0xe9 == ir.modrm)
6364 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6367 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6369 if (i386_record_floats (gdbarch, &ir,
6370 I387_ST0_REGNUM (tdep)))
6372 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6374 if (i386_record_floats (gdbarch, &ir,
6375 I387_ST0_REGNUM (tdep) +
6379 else if ((ir.modrm & 0x0f) - 0x08)
6381 if (i386_record_floats (gdbarch, &ir,
6382 I387_ST0_REGNUM (tdep) +
6383 ((ir.modrm & 0x0f) - 0x08)))
6389 if (0xe3 == ir.modrm)
6391 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6394 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6396 if (i386_record_floats (gdbarch, &ir,
6397 I387_ST0_REGNUM (tdep)))
6399 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6401 if (i386_record_floats (gdbarch, &ir,
6402 I387_ST0_REGNUM (tdep) +
6406 else if ((ir.modrm & 0x0f) - 0x08)
6408 if (i386_record_floats (gdbarch, &ir,
6409 I387_ST0_REGNUM (tdep) +
6410 ((ir.modrm & 0x0f) - 0x08)))
6416 if ((0x0c == ir.modrm >> 4)
6417 || (0x0d == ir.modrm >> 4)
6418 || (0x0f == ir.modrm >> 4))
6420 if ((ir.modrm & 0x0f) <= 7)
6422 if (i386_record_floats (gdbarch, &ir,
6423 I387_ST0_REGNUM (tdep) +
6429 if (i386_record_floats (gdbarch, &ir,
6430 I387_ST0_REGNUM (tdep) +
6431 ((ir.modrm & 0x0f) - 0x08)))
6437 if (0x0c == ir.modrm >> 4)
6439 if (i386_record_floats (gdbarch, &ir,
6440 I387_FTAG_REGNUM (tdep)))
6443 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6445 if ((ir.modrm & 0x0f) <= 7)
6447 if (i386_record_floats (gdbarch, &ir,
6448 I387_ST0_REGNUM (tdep) +
6454 if (i386_record_floats (gdbarch, &ir,
6455 I386_SAVE_FPU_REGS))
6461 if ((0x0c == ir.modrm >> 4)
6462 || (0x0e == ir.modrm >> 4)
6463 || (0x0f == ir.modrm >> 4)
6464 || (0xd9 == ir.modrm))
6466 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6471 if (0xe0 == ir.modrm)
6473 if (record_full_arch_list_add_reg (ir.regcache,
6477 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6479 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6487 case 0xa4: /* movsS */
6489 case 0xaa: /* stosS */
6491 case 0x6c: /* insS */
6493 regcache_raw_read_unsigned (ir.regcache,
6494 ir.regmap[X86_RECORD_RECX_REGNUM],
6500 if ((opcode & 1) == 0)
6503 ir.ot = ir.dflag + OT_WORD;
6504 regcache_raw_read_unsigned (ir.regcache,
6505 ir.regmap[X86_RECORD_REDI_REGNUM],
6508 regcache_raw_read_unsigned (ir.regcache,
6509 ir.regmap[X86_RECORD_ES_REGNUM],
6511 regcache_raw_read_unsigned (ir.regcache,
6512 ir.regmap[X86_RECORD_DS_REGNUM],
6514 if (ir.aflag && (es != ds))
6516 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6517 if (record_full_memory_query)
6520 Process record ignores the memory change of instruction at address %s\n\
6521 because it can't get the value of the segment register.\n\
6522 Do you want to stop the program?"),
6523 paddress (gdbarch, ir.orig_addr)))
6529 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6533 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6534 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6535 if (opcode == 0xa4 || opcode == 0xa5)
6536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6542 case 0xa6: /* cmpsS */
6544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6545 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6546 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6551 case 0xac: /* lodsS */
6553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6555 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6560 case 0xae: /* scasS */
6562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6563 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6568 case 0x6e: /* outsS */
6570 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6571 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6572 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6576 case 0xe4: /* port I/O */
6580 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6581 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6591 case 0xc2: /* ret im */
6592 case 0xc3: /* ret */
6593 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6594 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6597 case 0xca: /* lret im */
6598 case 0xcb: /* lret */
6599 case 0xcf: /* iret */
6600 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6601 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6602 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6605 case 0xe8: /* call im */
6606 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6608 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6612 case 0x9a: /* lcall im */
6613 if (ir.regmap[X86_RECORD_R8_REGNUM])
6618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6619 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6623 case 0xe9: /* jmp im */
6624 case 0xea: /* ljmp im */
6625 case 0xeb: /* jmp Jb */
6626 case 0x70: /* jcc Jb */
6642 case 0x0f80: /* jcc Jv */
6660 case 0x0f90: /* setcc Gv */
6676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6678 if (i386_record_modrm (&ir))
6681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6685 if (i386_record_lea_modrm (&ir))
6690 case 0x0f40: /* cmov Gv, Ev */
6706 if (i386_record_modrm (&ir))
6709 if (ir.dflag == OT_BYTE)
6711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6715 case 0x9c: /* pushf */
6716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6717 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6719 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6723 case 0x9d: /* popf */
6724 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6725 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6728 case 0x9e: /* sahf */
6729 if (ir.regmap[X86_RECORD_R8_REGNUM])
6735 case 0xf5: /* cmc */
6736 case 0xf8: /* clc */
6737 case 0xf9: /* stc */
6738 case 0xfc: /* cld */
6739 case 0xfd: /* std */
6740 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6743 case 0x9f: /* lahf */
6744 if (ir.regmap[X86_RECORD_R8_REGNUM])
6749 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6750 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6753 /* bit operations */
6754 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6755 ir.ot = ir.dflag + OT_WORD;
6756 if (i386_record_modrm (&ir))
6761 opcode = opcode << 8 | ir.modrm;
6767 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6770 if (i386_record_lea_modrm (&ir))
6774 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6777 case 0x0fa3: /* bt Gv, Ev */
6778 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6781 case 0x0fab: /* bts */
6782 case 0x0fb3: /* btr */
6783 case 0x0fbb: /* btc */
6784 ir.ot = ir.dflag + OT_WORD;
6785 if (i386_record_modrm (&ir))
6788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6792 if (i386_record_lea_modrm_addr (&ir, &addr64))
6794 regcache_raw_read_unsigned (ir.regcache,
6795 ir.regmap[ir.reg | rex_r],
6800 addr64 += ((int16_t) addr >> 4) << 4;
6803 addr64 += ((int32_t) addr >> 5) << 5;
6806 addr64 += ((int64_t) addr >> 6) << 6;
6809 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6811 if (i386_record_lea_modrm (&ir))
6814 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6817 case 0x0fbc: /* bsf */
6818 case 0x0fbd: /* bsr */
6819 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6820 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6824 case 0x27: /* daa */
6825 case 0x2f: /* das */
6826 case 0x37: /* aaa */
6827 case 0x3f: /* aas */
6828 case 0xd4: /* aam */
6829 case 0xd5: /* aad */
6830 if (ir.regmap[X86_RECORD_R8_REGNUM])
6835 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6836 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6840 case 0x90: /* nop */
6841 if (prefixes & PREFIX_LOCK)
6848 case 0x9b: /* fwait */
6849 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6851 opcode = (uint32_t) opcode8;
6857 case 0xcc: /* int3 */
6858 printf_unfiltered (_("Process record does not support instruction "
6865 case 0xcd: /* int */
6869 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6872 if (interrupt != 0x80
6873 || tdep->i386_intx80_record == NULL)
6875 printf_unfiltered (_("Process record does not support "
6876 "instruction int 0x%02x.\n"),
6881 ret = tdep->i386_intx80_record (ir.regcache);
6888 case 0xce: /* into */
6889 printf_unfiltered (_("Process record does not support "
6890 "instruction into.\n"));
6895 case 0xfa: /* cli */
6896 case 0xfb: /* sti */
6899 case 0x62: /* bound */
6900 printf_unfiltered (_("Process record does not support "
6901 "instruction bound.\n"));
6906 case 0x0fc8: /* bswap reg */
6914 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6917 case 0xd6: /* salc */
6918 if (ir.regmap[X86_RECORD_R8_REGNUM])
6923 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6927 case 0xe0: /* loopnz */
6928 case 0xe1: /* loopz */
6929 case 0xe2: /* loop */
6930 case 0xe3: /* jecxz */
6931 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6932 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6935 case 0x0f30: /* wrmsr */
6936 printf_unfiltered (_("Process record does not support "
6937 "instruction wrmsr.\n"));
6942 case 0x0f32: /* rdmsr */
6943 printf_unfiltered (_("Process record does not support "
6944 "instruction rdmsr.\n"));
6949 case 0x0f31: /* rdtsc */
6950 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6951 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6954 case 0x0f34: /* sysenter */
6957 if (ir.regmap[X86_RECORD_R8_REGNUM])
6962 if (tdep->i386_sysenter_record == NULL)
6964 printf_unfiltered (_("Process record does not support "
6965 "instruction sysenter.\n"));
6969 ret = tdep->i386_sysenter_record (ir.regcache);
6975 case 0x0f35: /* sysexit */
6976 printf_unfiltered (_("Process record does not support "
6977 "instruction sysexit.\n"));
6982 case 0x0f05: /* syscall */
6985 if (tdep->i386_syscall_record == NULL)
6987 printf_unfiltered (_("Process record does not support "
6988 "instruction syscall.\n"));
6992 ret = tdep->i386_syscall_record (ir.regcache);
6998 case 0x0f07: /* sysret */
6999 printf_unfiltered (_("Process record does not support "
7000 "instruction sysret.\n"));
7005 case 0x0fa2: /* cpuid */
7006 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7007 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7008 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7009 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7012 case 0xf4: /* hlt */
7013 printf_unfiltered (_("Process record does not support "
7014 "instruction hlt.\n"));
7020 if (i386_record_modrm (&ir))
7027 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7031 if (i386_record_lea_modrm (&ir))
7040 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7044 opcode = opcode << 8 | ir.modrm;
7051 if (i386_record_modrm (&ir))
7062 opcode = opcode << 8 | ir.modrm;
7065 if (ir.override >= 0)
7067 if (record_full_memory_query)
7070 Process record ignores the memory change of instruction at address %s\n\
7071 because it can't get the value of the segment register.\n\
7072 Do you want to stop the program?"),
7073 paddress (gdbarch, ir.orig_addr)))
7079 if (i386_record_lea_modrm_addr (&ir, &addr64))
7081 if (record_full_arch_list_add_mem (addr64, 2))
7084 if (ir.regmap[X86_RECORD_R8_REGNUM])
7086 if (record_full_arch_list_add_mem (addr64, 8))
7091 if (record_full_arch_list_add_mem (addr64, 4))
7102 case 0: /* monitor */
7105 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7109 opcode = opcode << 8 | ir.modrm;
7117 if (ir.override >= 0)
7119 if (record_full_memory_query)
7122 Process record ignores the memory change of instruction at address %s\n\
7123 because it can't get the value of the segment register.\n\
7124 Do you want to stop the program?"),
7125 paddress (gdbarch, ir.orig_addr)))
7133 if (i386_record_lea_modrm_addr (&ir, &addr64))
7135 if (record_full_arch_list_add_mem (addr64, 2))
7138 if (ir.regmap[X86_RECORD_R8_REGNUM])
7140 if (record_full_arch_list_add_mem (addr64, 8))
7145 if (record_full_arch_list_add_mem (addr64, 4))
7157 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7158 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7162 else if (ir.rm == 1)
7169 opcode = opcode << 8 | ir.modrm;
7176 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7182 if (i386_record_lea_modrm (&ir))
7185 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7188 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7190 case 7: /* invlpg */
7193 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7194 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7198 opcode = opcode << 8 | ir.modrm;
7203 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7207 opcode = opcode << 8 | ir.modrm;
7213 case 0x0f08: /* invd */
7214 case 0x0f09: /* wbinvd */
7217 case 0x63: /* arpl */
7218 if (i386_record_modrm (&ir))
7220 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7222 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7223 ? (ir.reg | rex_r) : ir.rm);
7227 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7228 if (i386_record_lea_modrm (&ir))
7231 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7232 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7235 case 0x0f02: /* lar */
7236 case 0x0f03: /* lsl */
7237 if (i386_record_modrm (&ir))
7239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7240 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7244 if (i386_record_modrm (&ir))
7246 if (ir.mod == 3 && ir.reg == 3)
7249 opcode = opcode << 8 | ir.modrm;
7261 /* nop (multi byte) */
7264 case 0x0f20: /* mov reg, crN */
7265 case 0x0f22: /* mov crN, reg */
7266 if (i386_record_modrm (&ir))
7268 if ((ir.modrm & 0xc0) != 0xc0)
7271 opcode = opcode << 8 | ir.modrm;
7282 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7284 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7288 opcode = opcode << 8 | ir.modrm;
7294 case 0x0f21: /* mov reg, drN */
7295 case 0x0f23: /* mov drN, reg */
7296 if (i386_record_modrm (&ir))
7298 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7299 || ir.reg == 5 || ir.reg >= 8)
7302 opcode = opcode << 8 | ir.modrm;
7306 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7308 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7311 case 0x0f06: /* clts */
7312 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7315 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7317 case 0x0f0d: /* 3DNow! prefetch */
7320 case 0x0f0e: /* 3DNow! femms */
7321 case 0x0f77: /* emms */
7322 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7324 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7327 case 0x0f0f: /* 3DNow! data */
7328 if (i386_record_modrm (&ir))
7330 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7335 case 0x0c: /* 3DNow! pi2fw */
7336 case 0x0d: /* 3DNow! pi2fd */
7337 case 0x1c: /* 3DNow! pf2iw */
7338 case 0x1d: /* 3DNow! pf2id */
7339 case 0x8a: /* 3DNow! pfnacc */
7340 case 0x8e: /* 3DNow! pfpnacc */
7341 case 0x90: /* 3DNow! pfcmpge */
7342 case 0x94: /* 3DNow! pfmin */
7343 case 0x96: /* 3DNow! pfrcp */
7344 case 0x97: /* 3DNow! pfrsqrt */
7345 case 0x9a: /* 3DNow! pfsub */
7346 case 0x9e: /* 3DNow! pfadd */
7347 case 0xa0: /* 3DNow! pfcmpgt */
7348 case 0xa4: /* 3DNow! pfmax */
7349 case 0xa6: /* 3DNow! pfrcpit1 */
7350 case 0xa7: /* 3DNow! pfrsqit1 */
7351 case 0xaa: /* 3DNow! pfsubr */
7352 case 0xae: /* 3DNow! pfacc */
7353 case 0xb0: /* 3DNow! pfcmpeq */
7354 case 0xb4: /* 3DNow! pfmul */
7355 case 0xb6: /* 3DNow! pfrcpit2 */
7356 case 0xb7: /* 3DNow! pmulhrw */
7357 case 0xbb: /* 3DNow! pswapd */
7358 case 0xbf: /* 3DNow! pavgusb */
7359 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7360 goto no_support_3dnow_data;
7361 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7365 no_support_3dnow_data:
7366 opcode = (opcode << 8) | opcode8;
7372 case 0x0faa: /* rsm */
7373 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7374 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7375 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7377 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7378 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7379 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7380 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7381 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7385 if (i386_record_modrm (&ir))
7389 case 0: /* fxsave */
7393 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7394 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7396 if (record_full_arch_list_add_mem (tmpu64, 512))
7401 case 1: /* fxrstor */
7405 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7407 for (i = I387_MM0_REGNUM (tdep);
7408 i386_mmx_regnum_p (gdbarch, i); i++)
7409 record_full_arch_list_add_reg (ir.regcache, i);
7411 for (i = I387_XMM0_REGNUM (tdep);
7412 i386_xmm_regnum_p (gdbarch, i); i++)
7413 record_full_arch_list_add_reg (ir.regcache, i);
7415 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7416 record_full_arch_list_add_reg (ir.regcache,
7417 I387_MXCSR_REGNUM(tdep));
7419 for (i = I387_ST0_REGNUM (tdep);
7420 i386_fp_regnum_p (gdbarch, i); i++)
7421 record_full_arch_list_add_reg (ir.regcache, i);
7423 for (i = I387_FCTRL_REGNUM (tdep);
7424 i386_fpc_regnum_p (gdbarch, i); i++)
7425 record_full_arch_list_add_reg (ir.regcache, i);
7429 case 2: /* ldmxcsr */
7430 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7432 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7435 case 3: /* stmxcsr */
7437 if (i386_record_lea_modrm (&ir))
7441 case 5: /* lfence */
7442 case 6: /* mfence */
7443 case 7: /* sfence clflush */
7447 opcode = (opcode << 8) | ir.modrm;
7453 case 0x0fc3: /* movnti */
7454 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7455 if (i386_record_modrm (&ir))
7460 if (i386_record_lea_modrm (&ir))
7464 /* Add prefix to opcode. */
7579 /* Mask out PREFIX_ADDR. */
7580 switch ((prefixes & ~PREFIX_ADDR))
7592 reswitch_prefix_add:
7600 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7603 opcode = (uint32_t) opcode8 | opcode << 8;
7604 goto reswitch_prefix_add;
7607 case 0x0f10: /* movups */
7608 case 0x660f10: /* movupd */
7609 case 0xf30f10: /* movss */
7610 case 0xf20f10: /* movsd */
7611 case 0x0f12: /* movlps */
7612 case 0x660f12: /* movlpd */
7613 case 0xf30f12: /* movsldup */
7614 case 0xf20f12: /* movddup */
7615 case 0x0f14: /* unpcklps */
7616 case 0x660f14: /* unpcklpd */
7617 case 0x0f15: /* unpckhps */
7618 case 0x660f15: /* unpckhpd */
7619 case 0x0f16: /* movhps */
7620 case 0x660f16: /* movhpd */
7621 case 0xf30f16: /* movshdup */
7622 case 0x0f28: /* movaps */
7623 case 0x660f28: /* movapd */
7624 case 0x0f2a: /* cvtpi2ps */
7625 case 0x660f2a: /* cvtpi2pd */
7626 case 0xf30f2a: /* cvtsi2ss */
7627 case 0xf20f2a: /* cvtsi2sd */
7628 case 0x0f2c: /* cvttps2pi */
7629 case 0x660f2c: /* cvttpd2pi */
7630 case 0x0f2d: /* cvtps2pi */
7631 case 0x660f2d: /* cvtpd2pi */
7632 case 0x660f3800: /* pshufb */
7633 case 0x660f3801: /* phaddw */
7634 case 0x660f3802: /* phaddd */
7635 case 0x660f3803: /* phaddsw */
7636 case 0x660f3804: /* pmaddubsw */
7637 case 0x660f3805: /* phsubw */
7638 case 0x660f3806: /* phsubd */
7639 case 0x660f3807: /* phsubsw */
7640 case 0x660f3808: /* psignb */
7641 case 0x660f3809: /* psignw */
7642 case 0x660f380a: /* psignd */
7643 case 0x660f380b: /* pmulhrsw */
7644 case 0x660f3810: /* pblendvb */
7645 case 0x660f3814: /* blendvps */
7646 case 0x660f3815: /* blendvpd */
7647 case 0x660f381c: /* pabsb */
7648 case 0x660f381d: /* pabsw */
7649 case 0x660f381e: /* pabsd */
7650 case 0x660f3820: /* pmovsxbw */
7651 case 0x660f3821: /* pmovsxbd */
7652 case 0x660f3822: /* pmovsxbq */
7653 case 0x660f3823: /* pmovsxwd */
7654 case 0x660f3824: /* pmovsxwq */
7655 case 0x660f3825: /* pmovsxdq */
7656 case 0x660f3828: /* pmuldq */
7657 case 0x660f3829: /* pcmpeqq */
7658 case 0x660f382a: /* movntdqa */
7659 case 0x660f3a08: /* roundps */
7660 case 0x660f3a09: /* roundpd */
7661 case 0x660f3a0a: /* roundss */
7662 case 0x660f3a0b: /* roundsd */
7663 case 0x660f3a0c: /* blendps */
7664 case 0x660f3a0d: /* blendpd */
7665 case 0x660f3a0e: /* pblendw */
7666 case 0x660f3a0f: /* palignr */
7667 case 0x660f3a20: /* pinsrb */
7668 case 0x660f3a21: /* insertps */
7669 case 0x660f3a22: /* pinsrd pinsrq */
7670 case 0x660f3a40: /* dpps */
7671 case 0x660f3a41: /* dppd */
7672 case 0x660f3a42: /* mpsadbw */
7673 case 0x660f3a60: /* pcmpestrm */
7674 case 0x660f3a61: /* pcmpestri */
7675 case 0x660f3a62: /* pcmpistrm */
7676 case 0x660f3a63: /* pcmpistri */
7677 case 0x0f51: /* sqrtps */
7678 case 0x660f51: /* sqrtpd */
7679 case 0xf20f51: /* sqrtsd */
7680 case 0xf30f51: /* sqrtss */
7681 case 0x0f52: /* rsqrtps */
7682 case 0xf30f52: /* rsqrtss */
7683 case 0x0f53: /* rcpps */
7684 case 0xf30f53: /* rcpss */
7685 case 0x0f54: /* andps */
7686 case 0x660f54: /* andpd */
7687 case 0x0f55: /* andnps */
7688 case 0x660f55: /* andnpd */
7689 case 0x0f56: /* orps */
7690 case 0x660f56: /* orpd */
7691 case 0x0f57: /* xorps */
7692 case 0x660f57: /* xorpd */
7693 case 0x0f58: /* addps */
7694 case 0x660f58: /* addpd */
7695 case 0xf20f58: /* addsd */
7696 case 0xf30f58: /* addss */
7697 case 0x0f59: /* mulps */
7698 case 0x660f59: /* mulpd */
7699 case 0xf20f59: /* mulsd */
7700 case 0xf30f59: /* mulss */
7701 case 0x0f5a: /* cvtps2pd */
7702 case 0x660f5a: /* cvtpd2ps */
7703 case 0xf20f5a: /* cvtsd2ss */
7704 case 0xf30f5a: /* cvtss2sd */
7705 case 0x0f5b: /* cvtdq2ps */
7706 case 0x660f5b: /* cvtps2dq */
7707 case 0xf30f5b: /* cvttps2dq */
7708 case 0x0f5c: /* subps */
7709 case 0x660f5c: /* subpd */
7710 case 0xf20f5c: /* subsd */
7711 case 0xf30f5c: /* subss */
7712 case 0x0f5d: /* minps */
7713 case 0x660f5d: /* minpd */
7714 case 0xf20f5d: /* minsd */
7715 case 0xf30f5d: /* minss */
7716 case 0x0f5e: /* divps */
7717 case 0x660f5e: /* divpd */
7718 case 0xf20f5e: /* divsd */
7719 case 0xf30f5e: /* divss */
7720 case 0x0f5f: /* maxps */
7721 case 0x660f5f: /* maxpd */
7722 case 0xf20f5f: /* maxsd */
7723 case 0xf30f5f: /* maxss */
7724 case 0x660f60: /* punpcklbw */
7725 case 0x660f61: /* punpcklwd */
7726 case 0x660f62: /* punpckldq */
7727 case 0x660f63: /* packsswb */
7728 case 0x660f64: /* pcmpgtb */
7729 case 0x660f65: /* pcmpgtw */
7730 case 0x660f66: /* pcmpgtd */
7731 case 0x660f67: /* packuswb */
7732 case 0x660f68: /* punpckhbw */
7733 case 0x660f69: /* punpckhwd */
7734 case 0x660f6a: /* punpckhdq */
7735 case 0x660f6b: /* packssdw */
7736 case 0x660f6c: /* punpcklqdq */
7737 case 0x660f6d: /* punpckhqdq */
7738 case 0x660f6e: /* movd */
7739 case 0x660f6f: /* movdqa */
7740 case 0xf30f6f: /* movdqu */
7741 case 0x660f70: /* pshufd */
7742 case 0xf20f70: /* pshuflw */
7743 case 0xf30f70: /* pshufhw */
7744 case 0x660f74: /* pcmpeqb */
7745 case 0x660f75: /* pcmpeqw */
7746 case 0x660f76: /* pcmpeqd */
7747 case 0x660f7c: /* haddpd */
7748 case 0xf20f7c: /* haddps */
7749 case 0x660f7d: /* hsubpd */
7750 case 0xf20f7d: /* hsubps */
7751 case 0xf30f7e: /* movq */
7752 case 0x0fc2: /* cmpps */
7753 case 0x660fc2: /* cmppd */
7754 case 0xf20fc2: /* cmpsd */
7755 case 0xf30fc2: /* cmpss */
7756 case 0x660fc4: /* pinsrw */
7757 case 0x0fc6: /* shufps */
7758 case 0x660fc6: /* shufpd */
7759 case 0x660fd0: /* addsubpd */
7760 case 0xf20fd0: /* addsubps */
7761 case 0x660fd1: /* psrlw */
7762 case 0x660fd2: /* psrld */
7763 case 0x660fd3: /* psrlq */
7764 case 0x660fd4: /* paddq */
7765 case 0x660fd5: /* pmullw */
7766 case 0xf30fd6: /* movq2dq */
7767 case 0x660fd8: /* psubusb */
7768 case 0x660fd9: /* psubusw */
7769 case 0x660fda: /* pminub */
7770 case 0x660fdb: /* pand */
7771 case 0x660fdc: /* paddusb */
7772 case 0x660fdd: /* paddusw */
7773 case 0x660fde: /* pmaxub */
7774 case 0x660fdf: /* pandn */
7775 case 0x660fe0: /* pavgb */
7776 case 0x660fe1: /* psraw */
7777 case 0x660fe2: /* psrad */
7778 case 0x660fe3: /* pavgw */
7779 case 0x660fe4: /* pmulhuw */
7780 case 0x660fe5: /* pmulhw */
7781 case 0x660fe6: /* cvttpd2dq */
7782 case 0xf20fe6: /* cvtpd2dq */
7783 case 0xf30fe6: /* cvtdq2pd */
7784 case 0x660fe8: /* psubsb */
7785 case 0x660fe9: /* psubsw */
7786 case 0x660fea: /* pminsw */
7787 case 0x660feb: /* por */
7788 case 0x660fec: /* paddsb */
7789 case 0x660fed: /* paddsw */
7790 case 0x660fee: /* pmaxsw */
7791 case 0x660fef: /* pxor */
7792 case 0xf20ff0: /* lddqu */
7793 case 0x660ff1: /* psllw */
7794 case 0x660ff2: /* pslld */
7795 case 0x660ff3: /* psllq */
7796 case 0x660ff4: /* pmuludq */
7797 case 0x660ff5: /* pmaddwd */
7798 case 0x660ff6: /* psadbw */
7799 case 0x660ff8: /* psubb */
7800 case 0x660ff9: /* psubw */
7801 case 0x660ffa: /* psubd */
7802 case 0x660ffb: /* psubq */
7803 case 0x660ffc: /* paddb */
7804 case 0x660ffd: /* paddw */
7805 case 0x660ffe: /* paddd */
7806 if (i386_record_modrm (&ir))
7809 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7811 record_full_arch_list_add_reg (ir.regcache,
7812 I387_XMM0_REGNUM (tdep) + ir.reg);
7813 if ((opcode & 0xfffffffc) == 0x660f3a60)
7814 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7817 case 0x0f11: /* movups */
7818 case 0x660f11: /* movupd */
7819 case 0xf30f11: /* movss */
7820 case 0xf20f11: /* movsd */
7821 case 0x0f13: /* movlps */
7822 case 0x660f13: /* movlpd */
7823 case 0x0f17: /* movhps */
7824 case 0x660f17: /* movhpd */
7825 case 0x0f29: /* movaps */
7826 case 0x660f29: /* movapd */
7827 case 0x660f3a14: /* pextrb */
7828 case 0x660f3a15: /* pextrw */
7829 case 0x660f3a16: /* pextrd pextrq */
7830 case 0x660f3a17: /* extractps */
7831 case 0x660f7f: /* movdqa */
7832 case 0xf30f7f: /* movdqu */
7833 if (i386_record_modrm (&ir))
7837 if (opcode == 0x0f13 || opcode == 0x660f13
7838 || opcode == 0x0f17 || opcode == 0x660f17)
7841 if (!i386_xmm_regnum_p (gdbarch,
7842 I387_XMM0_REGNUM (tdep) + ir.rm))
7844 record_full_arch_list_add_reg (ir.regcache,
7845 I387_XMM0_REGNUM (tdep) + ir.rm);
7867 if (i386_record_lea_modrm (&ir))
7872 case 0x0f2b: /* movntps */
7873 case 0x660f2b: /* movntpd */
7874 case 0x0fe7: /* movntq */
7875 case 0x660fe7: /* movntdq */
7878 if (opcode == 0x0fe7)
7882 if (i386_record_lea_modrm (&ir))
7886 case 0xf30f2c: /* cvttss2si */
7887 case 0xf20f2c: /* cvttsd2si */
7888 case 0xf30f2d: /* cvtss2si */
7889 case 0xf20f2d: /* cvtsd2si */
7890 case 0xf20f38f0: /* crc32 */
7891 case 0xf20f38f1: /* crc32 */
7892 case 0x0f50: /* movmskps */
7893 case 0x660f50: /* movmskpd */
7894 case 0x0fc5: /* pextrw */
7895 case 0x660fc5: /* pextrw */
7896 case 0x0fd7: /* pmovmskb */
7897 case 0x660fd7: /* pmovmskb */
7898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7901 case 0x0f3800: /* pshufb */
7902 case 0x0f3801: /* phaddw */
7903 case 0x0f3802: /* phaddd */
7904 case 0x0f3803: /* phaddsw */
7905 case 0x0f3804: /* pmaddubsw */
7906 case 0x0f3805: /* phsubw */
7907 case 0x0f3806: /* phsubd */
7908 case 0x0f3807: /* phsubsw */
7909 case 0x0f3808: /* psignb */
7910 case 0x0f3809: /* psignw */
7911 case 0x0f380a: /* psignd */
7912 case 0x0f380b: /* pmulhrsw */
7913 case 0x0f381c: /* pabsb */
7914 case 0x0f381d: /* pabsw */
7915 case 0x0f381e: /* pabsd */
7916 case 0x0f382b: /* packusdw */
7917 case 0x0f3830: /* pmovzxbw */
7918 case 0x0f3831: /* pmovzxbd */
7919 case 0x0f3832: /* pmovzxbq */
7920 case 0x0f3833: /* pmovzxwd */
7921 case 0x0f3834: /* pmovzxwq */
7922 case 0x0f3835: /* pmovzxdq */
7923 case 0x0f3837: /* pcmpgtq */
7924 case 0x0f3838: /* pminsb */
7925 case 0x0f3839: /* pminsd */
7926 case 0x0f383a: /* pminuw */
7927 case 0x0f383b: /* pminud */
7928 case 0x0f383c: /* pmaxsb */
7929 case 0x0f383d: /* pmaxsd */
7930 case 0x0f383e: /* pmaxuw */
7931 case 0x0f383f: /* pmaxud */
7932 case 0x0f3840: /* pmulld */
7933 case 0x0f3841: /* phminposuw */
7934 case 0x0f3a0f: /* palignr */
7935 case 0x0f60: /* punpcklbw */
7936 case 0x0f61: /* punpcklwd */
7937 case 0x0f62: /* punpckldq */
7938 case 0x0f63: /* packsswb */
7939 case 0x0f64: /* pcmpgtb */
7940 case 0x0f65: /* pcmpgtw */
7941 case 0x0f66: /* pcmpgtd */
7942 case 0x0f67: /* packuswb */
7943 case 0x0f68: /* punpckhbw */
7944 case 0x0f69: /* punpckhwd */
7945 case 0x0f6a: /* punpckhdq */
7946 case 0x0f6b: /* packssdw */
7947 case 0x0f6e: /* movd */
7948 case 0x0f6f: /* movq */
7949 case 0x0f70: /* pshufw */
7950 case 0x0f74: /* pcmpeqb */
7951 case 0x0f75: /* pcmpeqw */
7952 case 0x0f76: /* pcmpeqd */
7953 case 0x0fc4: /* pinsrw */
7954 case 0x0fd1: /* psrlw */
7955 case 0x0fd2: /* psrld */
7956 case 0x0fd3: /* psrlq */
7957 case 0x0fd4: /* paddq */
7958 case 0x0fd5: /* pmullw */
7959 case 0xf20fd6: /* movdq2q */
7960 case 0x0fd8: /* psubusb */
7961 case 0x0fd9: /* psubusw */
7962 case 0x0fda: /* pminub */
7963 case 0x0fdb: /* pand */
7964 case 0x0fdc: /* paddusb */
7965 case 0x0fdd: /* paddusw */
7966 case 0x0fde: /* pmaxub */
7967 case 0x0fdf: /* pandn */
7968 case 0x0fe0: /* pavgb */
7969 case 0x0fe1: /* psraw */
7970 case 0x0fe2: /* psrad */
7971 case 0x0fe3: /* pavgw */
7972 case 0x0fe4: /* pmulhuw */
7973 case 0x0fe5: /* pmulhw */
7974 case 0x0fe8: /* psubsb */
7975 case 0x0fe9: /* psubsw */
7976 case 0x0fea: /* pminsw */
7977 case 0x0feb: /* por */
7978 case 0x0fec: /* paddsb */
7979 case 0x0fed: /* paddsw */
7980 case 0x0fee: /* pmaxsw */
7981 case 0x0fef: /* pxor */
7982 case 0x0ff1: /* psllw */
7983 case 0x0ff2: /* pslld */
7984 case 0x0ff3: /* psllq */
7985 case 0x0ff4: /* pmuludq */
7986 case 0x0ff5: /* pmaddwd */
7987 case 0x0ff6: /* psadbw */
7988 case 0x0ff8: /* psubb */
7989 case 0x0ff9: /* psubw */
7990 case 0x0ffa: /* psubd */
7991 case 0x0ffb: /* psubq */
7992 case 0x0ffc: /* paddb */
7993 case 0x0ffd: /* paddw */
7994 case 0x0ffe: /* paddd */
7995 if (i386_record_modrm (&ir))
7997 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7999 record_full_arch_list_add_reg (ir.regcache,
8000 I387_MM0_REGNUM (tdep) + ir.reg);
8003 case 0x0f71: /* psllw */
8004 case 0x0f72: /* pslld */
8005 case 0x0f73: /* psllq */
8006 if (i386_record_modrm (&ir))
8008 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8010 record_full_arch_list_add_reg (ir.regcache,
8011 I387_MM0_REGNUM (tdep) + ir.rm);
8014 case 0x660f71: /* psllw */
8015 case 0x660f72: /* pslld */
8016 case 0x660f73: /* psllq */
8017 if (i386_record_modrm (&ir))
8020 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
8022 record_full_arch_list_add_reg (ir.regcache,
8023 I387_XMM0_REGNUM (tdep) + ir.rm);
8026 case 0x0f7e: /* movd */
8027 case 0x660f7e: /* movd */
8028 if (i386_record_modrm (&ir))
8031 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
8038 if (i386_record_lea_modrm (&ir))
8043 case 0x0f7f: /* movq */
8044 if (i386_record_modrm (&ir))
8048 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8050 record_full_arch_list_add_reg (ir.regcache,
8051 I387_MM0_REGNUM (tdep) + ir.rm);
8056 if (i386_record_lea_modrm (&ir))
8061 case 0xf30fb8: /* popcnt */
8062 if (i386_record_modrm (&ir))
8064 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
8065 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8068 case 0x660fd6: /* movq */
8069 if (i386_record_modrm (&ir))
8074 if (!i386_xmm_regnum_p (gdbarch,
8075 I387_XMM0_REGNUM (tdep) + ir.rm))
8077 record_full_arch_list_add_reg (ir.regcache,
8078 I387_XMM0_REGNUM (tdep) + ir.rm);
8083 if (i386_record_lea_modrm (&ir))
8088 case 0x660f3817: /* ptest */
8089 case 0x0f2e: /* ucomiss */
8090 case 0x660f2e: /* ucomisd */
8091 case 0x0f2f: /* comiss */
8092 case 0x660f2f: /* comisd */
8093 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8096 case 0x0ff7: /* maskmovq */
8097 regcache_raw_read_unsigned (ir.regcache,
8098 ir.regmap[X86_RECORD_REDI_REGNUM],
8100 if (record_full_arch_list_add_mem (addr, 64))
8104 case 0x660ff7: /* maskmovdqu */
8105 regcache_raw_read_unsigned (ir.regcache,
8106 ir.regmap[X86_RECORD_REDI_REGNUM],
8108 if (record_full_arch_list_add_mem (addr, 128))
8123 /* In the future, maybe still need to deal with need_dasm. */
8124 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8125 if (record_full_arch_list_add_end ())
8131 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8132 "at address %s.\n"),
8133 (unsigned int) (opcode),
8134 paddress (gdbarch, ir.orig_addr));
8138 static const int i386_record_regmap[] =
8140 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8141 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8142 0, 0, 0, 0, 0, 0, 0, 0,
8143 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8144 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8147 /* Check that the given address appears suitable for a fast
8148 tracepoint, which on x86-64 means that we need an instruction of at
8149 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8150 jump and not have to worry about program jumps to an address in the
8151 middle of the tracepoint jump. On x86, it may be possible to use
8152 4-byte jumps with a 2-byte offset to a trampoline located in the
8153 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8154 of instruction to replace, and 0 if not, plus an explanatory
8158 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8163 /* Ask the target for the minimum instruction length supported. */
8164 jumplen = target_get_min_fast_tracepoint_insn_len ();
8168 /* If the target does not support the get_min_fast_tracepoint_insn_len
8169 operation, assume that fast tracepoints will always be implemented
8170 using 4-byte relative jumps on both x86 and x86-64. */
8173 else if (jumplen == 0)
8175 /* If the target does support get_min_fast_tracepoint_insn_len but
8176 returns zero, then the IPA has not loaded yet. In this case,
8177 we optimistically assume that truncated 2-byte relative jumps
8178 will be available on x86, and compensate later if this assumption
8179 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8180 jumps will always be used. */
8181 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8184 /* Check for fit. */
8185 len = gdb_insn_length (gdbarch, addr);
8189 /* Return a bit of target-specific detail to add to the caller's
8190 generic failure message. */
8192 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8193 "need at least %d bytes for the jump"),
8205 /* Return a floating-point format for a floating-point variable of
8206 length LEN in bits. If non-NULL, NAME is the name of its type.
8207 If no suitable type is found, return NULL. */
8209 const struct floatformat **
8210 i386_floatformat_for_type (struct gdbarch *gdbarch,
8211 const char *name, int len)
8213 if (len == 128 && name)
8214 if (strcmp (name, "__float128") == 0
8215 || strcmp (name, "_Float128") == 0
8216 || strcmp (name, "complex _Float128") == 0)
8217 return floatformats_ia64_quad;
8219 return default_floatformat_for_type (gdbarch, name, len);
8223 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8224 struct tdesc_arch_data *tdesc_data)
8226 const struct target_desc *tdesc = tdep->tdesc;
8227 const struct tdesc_feature *feature_core;
8229 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8230 *feature_avx512, *feature_pkeys;
8231 int i, num_regs, valid_p;
8233 if (! tdesc_has_registers (tdesc))
8236 /* Get core registers. */
8237 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8238 if (feature_core == NULL)
8241 /* Get SSE registers. */
8242 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8244 /* Try AVX registers. */
8245 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8247 /* Try MPX registers. */
8248 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8250 /* Try AVX512 registers. */
8251 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8254 feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys");
8258 /* The XCR0 bits. */
8261 /* AVX512 register description requires AVX register description. */
8265 tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK;
8267 /* It may have been set by OSABI initialization function. */
8268 if (tdep->k0_regnum < 0)
8270 tdep->k_register_names = i386_k_names;
8271 tdep->k0_regnum = I386_K0_REGNUM;
8274 for (i = 0; i < I387_NUM_K_REGS; i++)
8275 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8276 tdep->k0_regnum + i,
8279 if (tdep->num_zmm_regs == 0)
8281 tdep->zmmh_register_names = i386_zmmh_names;
8282 tdep->num_zmm_regs = 8;
8283 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8286 for (i = 0; i < tdep->num_zmm_regs; i++)
8287 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8288 tdep->zmm0h_regnum + i,
8289 tdep->zmmh_register_names[i]);
8291 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8292 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8293 tdep->xmm16_regnum + i,
8294 tdep->xmm_avx512_register_names[i]);
8296 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8297 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8298 tdep->ymm16h_regnum + i,
8299 tdep->ymm16h_register_names[i]);
8303 /* AVX register description requires SSE register description. */
8307 if (!feature_avx512)
8308 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8310 /* It may have been set by OSABI initialization function. */
8311 if (tdep->num_ymm_regs == 0)
8313 tdep->ymmh_register_names = i386_ymmh_names;
8314 tdep->num_ymm_regs = 8;
8315 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8318 for (i = 0; i < tdep->num_ymm_regs; i++)
8319 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8320 tdep->ymm0h_regnum + i,
8321 tdep->ymmh_register_names[i]);
8323 else if (feature_sse)
8324 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8327 tdep->xcr0 = X86_XSTATE_X87_MASK;
8328 tdep->num_xmm_regs = 0;
8331 num_regs = tdep->num_core_regs;
8332 for (i = 0; i < num_regs; i++)
8333 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8334 tdep->register_names[i]);
8338 /* Need to include %mxcsr, so add one. */
8339 num_regs += tdep->num_xmm_regs + 1;
8340 for (; i < num_regs; i++)
8341 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8342 tdep->register_names[i]);
8347 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8349 if (tdep->bnd0r_regnum < 0)
8351 tdep->mpx_register_names = i386_mpx_names;
8352 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8353 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8356 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8357 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8358 I387_BND0R_REGNUM (tdep) + i,
8359 tdep->mpx_register_names[i]);
8364 tdep->xcr0 |= X86_XSTATE_PKRU;
8365 if (tdep->pkru_regnum < 0)
8367 tdep->pkeys_register_names = i386_pkeys_names;
8368 tdep->pkru_regnum = I386_PKRU_REGNUM;
8369 tdep->num_pkeys_regs = 1;
8372 for (i = 0; i < I387_NUM_PKEYS_REGS; i++)
8373 valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data,
8374 I387_PKRU_REGNUM (tdep) + i,
8375 tdep->pkeys_register_names[i]);
8382 /* Note: This is called for both i386 and amd64. */
8384 static struct gdbarch *
8385 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8387 struct gdbarch_tdep *tdep;
8388 struct gdbarch *gdbarch;
8389 struct tdesc_arch_data *tdesc_data;
8390 const struct target_desc *tdesc;
8396 /* If there is already a candidate, use it. */
8397 arches = gdbarch_list_lookup_by_info (arches, &info);
8399 return arches->gdbarch;
8401 /* Allocate space for the new architecture. Assume i386 for now. */
8402 tdep = XCNEW (struct gdbarch_tdep);
8403 gdbarch = gdbarch_alloc (&info, tdep);
8405 /* General-purpose registers. */
8406 tdep->gregset_reg_offset = NULL;
8407 tdep->gregset_num_regs = I386_NUM_GREGS;
8408 tdep->sizeof_gregset = 0;
8410 /* Floating-point registers. */
8411 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8412 tdep->fpregset = &i386_fpregset;
8414 /* The default settings include the FPU registers, the MMX registers
8415 and the SSE registers. This can be overridden for a specific ABI
8416 by adjusting the members `st0_regnum', `mm0_regnum' and
8417 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8418 will show up in the output of "info all-registers". */
8420 tdep->st0_regnum = I386_ST0_REGNUM;
8422 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8423 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8425 tdep->jb_pc_offset = -1;
8426 tdep->struct_return = pcc_struct_return;
8427 tdep->sigtramp_start = 0;
8428 tdep->sigtramp_end = 0;
8429 tdep->sigtramp_p = i386_sigtramp_p;
8430 tdep->sigcontext_addr = NULL;
8431 tdep->sc_reg_offset = NULL;
8432 tdep->sc_pc_offset = -1;
8433 tdep->sc_sp_offset = -1;
8435 tdep->xsave_xcr0_offset = -1;
8437 tdep->record_regmap = i386_record_regmap;
8439 set_gdbarch_long_long_align_bit (gdbarch, 32);
8441 /* The format used for `long double' on almost all i386 targets is
8442 the i387 extended floating-point format. In fact, of all targets
8443 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8444 on having a `long double' that's not `long' at all. */
8445 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8447 /* Although the i387 extended floating-point has only 80 significant
8448 bits, a `long double' actually takes up 96, probably to enforce
8450 set_gdbarch_long_double_bit (gdbarch, 96);
8452 /* Support for floating-point data type variants. */
8453 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
8455 /* Register numbers of various important registers. */
8456 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8457 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8458 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8459 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8461 /* NOTE: kettenis/20040418: GCC does have two possible register
8462 numbering schemes on the i386: dbx and SVR4. These schemes
8463 differ in how they number %ebp, %esp, %eflags, and the
8464 floating-point registers, and are implemented by the arrays
8465 dbx_register_map[] and svr4_dbx_register_map in
8466 gcc/config/i386.c. GCC also defines a third numbering scheme in
8467 gcc/config/i386.c, which it designates as the "default" register
8468 map used in 64bit mode. This last register numbering scheme is
8469 implemented in dbx64_register_map, and is used for AMD64; see
8472 Currently, each GCC i386 target always uses the same register
8473 numbering scheme across all its supported debugging formats
8474 i.e. SDB (COFF), stabs and DWARF 2. This is because
8475 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8476 DBX_REGISTER_NUMBER macro which is defined by each target's
8477 respective config header in a manner independent of the requested
8478 output debugging format.
8480 This does not match the arrangement below, which presumes that
8481 the SDB and stabs numbering schemes differ from the DWARF and
8482 DWARF 2 ones. The reason for this arrangement is that it is
8483 likely to get the numbering scheme for the target's
8484 default/native debug format right. For targets where GCC is the
8485 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8486 targets where the native toolchain uses a different numbering
8487 scheme for a particular debug format (stabs-in-ELF on Solaris)
8488 the defaults below will have to be overridden, like
8489 i386_elf_init_abi() does. */
8491 /* Use the dbx register numbering scheme for stabs and COFF. */
8492 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8493 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8495 /* Use the SVR4 register numbering scheme for DWARF 2. */
8496 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8498 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8499 be in use on any of the supported i386 targets. */
8501 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8503 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8505 /* Call dummy code. */
8506 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8507 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8508 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8509 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8511 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8512 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8513 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8515 set_gdbarch_return_value (gdbarch, i386_return_value);
8517 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8519 /* Stack grows downward. */
8520 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8522 set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc);
8523 set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind);
8525 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8526 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8528 set_gdbarch_frame_args_skip (gdbarch, 8);
8530 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8532 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8534 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8536 /* Add the i386 register groups. */
8537 i386_add_reggroups (gdbarch);
8538 tdep->register_reggroup_p = i386_register_reggroup_p;
8540 /* Helper for function argument information. */
8541 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8543 /* Hook the function epilogue frame unwinder. This unwinder is
8544 appended to the list first, so that it supercedes the DWARF
8545 unwinder in function epilogues (where the DWARF unwinder
8546 currently fails). */
8547 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8549 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8550 to the list before the prologue-based unwinders, so that DWARF
8551 CFI info will be used if it is available. */
8552 dwarf2_append_unwinders (gdbarch);
8554 frame_base_set_default (gdbarch, &i386_frame_base);
8556 /* Pseudo registers may be changed by amd64_init_abi. */
8557 set_gdbarch_pseudo_register_read_value (gdbarch,
8558 i386_pseudo_register_read_value);
8559 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8560 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8561 i386_ax_pseudo_register_collect);
8563 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8564 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8566 /* Override the normal target description method to make the AVX
8567 upper halves anonymous. */
8568 set_gdbarch_register_name (gdbarch, i386_register_name);
8570 /* Even though the default ABI only includes general-purpose registers,
8571 floating-point registers and the SSE registers, we have to leave a
8572 gap for the upper AVX, MPX and AVX512 registers. */
8573 set_gdbarch_num_regs (gdbarch, I386_PKEYS_NUM_REGS);
8575 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8577 /* Get the x86 target description from INFO. */
8578 tdesc = info.target_desc;
8579 if (! tdesc_has_registers (tdesc))
8581 tdep->tdesc = tdesc;
8583 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8584 tdep->register_names = i386_register_names;
8586 /* No upper YMM registers. */
8587 tdep->ymmh_register_names = NULL;
8588 tdep->ymm0h_regnum = -1;
8590 /* No upper ZMM registers. */
8591 tdep->zmmh_register_names = NULL;
8592 tdep->zmm0h_regnum = -1;
8594 /* No high XMM registers. */
8595 tdep->xmm_avx512_register_names = NULL;
8596 tdep->xmm16_regnum = -1;
8598 /* No upper YMM16-31 registers. */
8599 tdep->ymm16h_register_names = NULL;
8600 tdep->ymm16h_regnum = -1;
8602 tdep->num_byte_regs = 8;
8603 tdep->num_word_regs = 8;
8604 tdep->num_dword_regs = 0;
8605 tdep->num_mmx_regs = 8;
8606 tdep->num_ymm_regs = 0;
8608 /* No MPX registers. */
8609 tdep->bnd0r_regnum = -1;
8610 tdep->bndcfgu_regnum = -1;
8612 /* No AVX512 registers. */
8613 tdep->k0_regnum = -1;
8614 tdep->num_zmm_regs = 0;
8615 tdep->num_ymm_avx512_regs = 0;
8616 tdep->num_xmm_avx512_regs = 0;
8618 /* No PKEYS registers */
8619 tdep->pkru_regnum = -1;
8620 tdep->num_pkeys_regs = 0;
8622 tdesc_data = tdesc_data_alloc ();
8624 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8626 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8628 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8629 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8630 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8632 /* Hook in ABI-specific overrides, if they have been registered.
8633 Note: If INFO specifies a 64 bit arch, this is where we turn
8634 a 32-bit i386 into a 64-bit amd64. */
8635 info.tdep_info = tdesc_data;
8636 gdbarch_init_osabi (info, gdbarch);
8638 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8640 tdesc_data_cleanup (tdesc_data);
8642 gdbarch_free (gdbarch);
8646 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8648 /* Wire in pseudo registers. Number of pseudo registers may be
8650 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8651 + tdep->num_word_regs
8652 + tdep->num_dword_regs
8653 + tdep->num_mmx_regs
8654 + tdep->num_ymm_regs
8656 + tdep->num_ymm_avx512_regs
8657 + tdep->num_zmm_regs));
8659 /* Target description may be changed. */
8660 tdesc = tdep->tdesc;
8662 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8664 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8665 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8667 /* Make %al the first pseudo-register. */
8668 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8669 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8671 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8672 if (tdep->num_dword_regs)
8674 /* Support dword pseudo-register if it hasn't been disabled. */
8675 tdep->eax_regnum = ymm0_regnum;
8676 ymm0_regnum += tdep->num_dword_regs;
8679 tdep->eax_regnum = -1;
8681 mm0_regnum = ymm0_regnum;
8682 if (tdep->num_ymm_regs)
8684 /* Support YMM pseudo-register if it is available. */
8685 tdep->ymm0_regnum = ymm0_regnum;
8686 mm0_regnum += tdep->num_ymm_regs;
8689 tdep->ymm0_regnum = -1;
8691 if (tdep->num_ymm_avx512_regs)
8693 /* Support YMM16-31 pseudo registers if available. */
8694 tdep->ymm16_regnum = mm0_regnum;
8695 mm0_regnum += tdep->num_ymm_avx512_regs;
8698 tdep->ymm16_regnum = -1;
8700 if (tdep->num_zmm_regs)
8702 /* Support ZMM pseudo-register if it is available. */
8703 tdep->zmm0_regnum = mm0_regnum;
8704 mm0_regnum += tdep->num_zmm_regs;
8707 tdep->zmm0_regnum = -1;
8709 bnd0_regnum = mm0_regnum;
8710 if (tdep->num_mmx_regs != 0)
8712 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8713 tdep->mm0_regnum = mm0_regnum;
8714 bnd0_regnum += tdep->num_mmx_regs;
8717 tdep->mm0_regnum = -1;
8719 if (tdep->bnd0r_regnum > 0)
8720 tdep->bnd0_regnum = bnd0_regnum;
8722 tdep-> bnd0_regnum = -1;
8724 /* Hook in the legacy prologue-based unwinders last (fallback). */
8725 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8726 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8727 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8729 /* If we have a register mapping, enable the generic core file
8730 support, unless it has already been enabled. */
8731 if (tdep->gregset_reg_offset
8732 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8733 set_gdbarch_iterate_over_regset_sections
8734 (gdbarch, i386_iterate_over_regset_sections);
8736 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8737 i386_fast_tracepoint_valid_at);
8742 static enum gdb_osabi
8743 i386_coff_osabi_sniffer (bfd *abfd)
8745 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8746 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8747 return GDB_OSABI_GO32;
8749 return GDB_OSABI_UNKNOWN;
8753 /* Return the target description for a specified XSAVE feature mask. */
8755 const struct target_desc *
8756 i386_target_description (uint64_t xcr0)
8758 switch (xcr0 & X86_XSTATE_ALL_MASK)
8760 case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK:
8761 return tdesc_i386_avx_mpx_avx512_pku;
8762 case X86_XSTATE_AVX_AVX512_MASK:
8763 return tdesc_i386_avx_avx512;
8764 case X86_XSTATE_AVX_MPX_MASK:
8765 return tdesc_i386_avx_mpx;
8766 case X86_XSTATE_MPX_MASK:
8767 return tdesc_i386_mpx;
8768 case X86_XSTATE_AVX_MASK:
8769 return tdesc_i386_avx;
8775 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8777 /* Find the bound directory base address. */
8779 static unsigned long
8780 i386_mpx_bd_base (void)
8782 struct regcache *rcache;
8783 struct gdbarch_tdep *tdep;
8785 enum register_status regstatus;
8787 rcache = get_current_regcache ();
8788 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8790 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8792 if (regstatus != REG_VALID)
8793 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8795 return ret & MPX_BASE_MASK;
8799 i386_mpx_enabled (void)
8801 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8802 const struct target_desc *tdesc = tdep->tdesc;
8804 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8807 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8808 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8809 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8810 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8812 /* Find the bound table entry given the pointer location and the base
8813 address of the table. */
8816 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8820 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8821 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8822 CORE_ADDR bd_entry_addr;
8825 struct gdbarch *gdbarch = get_current_arch ();
8826 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8829 if (gdbarch_ptr_bit (gdbarch) == 64)
8831 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8832 bd_ptr_r_shift = 20;
8834 bt_select_r_shift = 3;
8835 bt_select_l_shift = 5;
8836 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8838 if ( sizeof (CORE_ADDR) == 4)
8839 error (_("bound table examination not supported\
8840 for 64-bit process with 32-bit GDB"));
8844 mpx_bd_mask = MPX_BD_MASK_32;
8845 bd_ptr_r_shift = 12;
8847 bt_select_r_shift = 2;
8848 bt_select_l_shift = 4;
8849 bt_mask = MPX_BT_MASK_32;
8852 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8853 bd_entry_addr = bd_base + offset1;
8854 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8856 if ((bd_entry & 0x1) == 0)
8857 error (_("Invalid bounds directory entry at %s."),
8858 paddress (get_current_arch (), bd_entry_addr));
8860 /* Clearing status bit. */
8862 bt_addr = bd_entry & ~bt_select_r_shift;
8863 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8865 return bt_addr + offset2;
8868 /* Print routine for the mpx bounds. */
8871 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8873 struct ui_out *uiout = current_uiout;
8875 struct gdbarch *gdbarch = get_current_arch ();
8876 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8877 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8879 if (bounds_in_map == 1)
8881 uiout->text ("Null bounds on map:");
8882 uiout->text (" pointer value = ");
8883 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8889 uiout->text ("{lbound = ");
8890 uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]);
8891 uiout->text (", ubound = ");
8893 /* The upper bound is stored in 1's complement. */
8894 uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]);
8895 uiout->text ("}: pointer value = ");
8896 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8898 if (gdbarch_ptr_bit (gdbarch) == 64)
8899 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8901 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8903 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8904 -1 represents in this sense full memory access, and there is no need
8907 size = (size > -1 ? size + 1 : size);
8908 uiout->text (", size = ");
8909 uiout->field_fmt ("size", "%s", plongest (size));
8911 uiout->text (", metadata = ");
8912 uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]);
8917 /* Implement the command "show mpx bound". */
8920 i386_mpx_info_bounds (char *args, int from_tty)
8922 CORE_ADDR bd_base = 0;
8924 CORE_ADDR bt_entry_addr = 0;
8925 CORE_ADDR bt_entry[4];
8927 struct gdbarch *gdbarch = get_current_arch ();
8928 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8930 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8931 || !i386_mpx_enabled ())
8933 printf_unfiltered (_("Intel Memory Protection Extensions not "
8934 "supported on this target.\n"));
8940 printf_unfiltered (_("Address of pointer variable expected.\n"));
8944 addr = parse_and_eval_address (args);
8946 bd_base = i386_mpx_bd_base ();
8947 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8949 memset (bt_entry, 0, sizeof (bt_entry));
8951 for (i = 0; i < 4; i++)
8952 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8953 + i * TYPE_LENGTH (data_ptr_type),
8956 i386_mpx_print_bounds (bt_entry);
8959 /* Implement the command "set mpx bound". */
8962 i386_mpx_set_bounds (char *args, int from_tty)
8964 CORE_ADDR bd_base = 0;
8965 CORE_ADDR addr, lower, upper;
8966 CORE_ADDR bt_entry_addr = 0;
8967 CORE_ADDR bt_entry[2];
8968 const char *input = args;
8970 struct gdbarch *gdbarch = get_current_arch ();
8971 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8972 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8974 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8975 || !i386_mpx_enabled ())
8976 error (_("Intel Memory Protection Extensions not supported\
8980 error (_("Pointer value expected."));
8982 addr = value_as_address (parse_to_comma_and_eval (&input));
8984 if (input[0] == ',')
8986 if (input[0] == '\0')
8987 error (_("wrong number of arguments: missing lower and upper bound."));
8988 lower = value_as_address (parse_to_comma_and_eval (&input));
8990 if (input[0] == ',')
8992 if (input[0] == '\0')
8993 error (_("Wrong number of arguments; Missing upper bound."));
8994 upper = value_as_address (parse_to_comma_and_eval (&input));
8996 bd_base = i386_mpx_bd_base ();
8997 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8998 for (i = 0; i < 2; i++)
8999 bt_entry[i] = read_memory_typed_address (bt_entry_addr
9000 + i * TYPE_LENGTH (data_ptr_type),
9002 bt_entry[0] = (uint64_t) lower;
9003 bt_entry[1] = ~(uint64_t) upper;
9005 for (i = 0; i < 2; i++)
9006 write_memory_unsigned_integer (bt_entry_addr
9007 + i * TYPE_LENGTH (data_ptr_type),
9008 TYPE_LENGTH (data_ptr_type), byte_order,
9012 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
9014 /* Helper function for the CLI commands. */
9017 set_mpx_cmd (char *args, int from_tty)
9019 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
9022 /* Helper function for the CLI commands. */
9025 show_mpx_cmd (char *args, int from_tty)
9027 cmd_show_list (mpx_show_cmdlist, from_tty, "");
9030 /* Provide a prototype to silence -Wmissing-prototypes. */
9031 void _initialize_i386_tdep (void);
9034 _initialize_i386_tdep (void)
9036 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
9038 /* Add the variable that controls the disassembly flavor. */
9039 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
9040 &disassembly_flavor, _("\
9041 Set the disassembly flavor."), _("\
9042 Show the disassembly flavor."), _("\
9043 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9045 NULL, /* FIXME: i18n: */
9046 &setlist, &showlist);
9048 /* Add the variable that controls the convention for returning
9050 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
9051 &struct_convention, _("\
9052 Set the convention for returning small structs."), _("\
9053 Show the convention for returning small structs."), _("\
9054 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9057 NULL, /* FIXME: i18n: */
9058 &setlist, &showlist);
9060 /* Add "mpx" prefix for the set commands. */
9062 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
9063 Set Intel Memory Protection Extensions specific variables."),
9064 &mpx_set_cmdlist, "set mpx ",
9065 0 /* allow-unknown */, &setlist);
9067 /* Add "mpx" prefix for the show commands. */
9069 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
9070 Show Intel Memory Protection Extensions specific variables."),
9071 &mpx_show_cmdlist, "show mpx ",
9072 0 /* allow-unknown */, &showlist);
9074 /* Add "bound" command for the show mpx commands list. */
9076 add_cmd ("bound", no_class, i386_mpx_info_bounds,
9077 "Show the memory bounds for a given array/pointer storage\
9078 in the bound table.",
9081 /* Add "bound" command for the set mpx commands list. */
9083 add_cmd ("bound", no_class, i386_mpx_set_bounds,
9084 "Set the memory bounds for a given array/pointer storage\
9085 in the bound table.",
9088 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
9089 i386_coff_osabi_sniffer);
9091 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9092 i386_svr4_init_abi);
9093 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
9094 i386_go32_init_abi);
9096 /* Initialize the i386-specific register groups. */
9097 i386_init_reggroups ();
9099 /* Initialize the standard target descriptions. */
9100 initialize_tdesc_i386 ();
9101 initialize_tdesc_i386_mmx ();
9102 initialize_tdesc_i386_avx ();
9103 initialize_tdesc_i386_mpx ();
9104 initialize_tdesc_i386_avx_mpx ();
9105 initialize_tdesc_i386_avx_avx512 ();
9106 initialize_tdesc_i386_avx_mpx_avx512_pku ();
9108 /* Tell remote stub that we support XML target description. */
9109 register_remote_support_xml ("i386");