1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
56 #include "features/i386/i386-avx512.c"
57 #include "features/i386/i386-mmx.c"
62 #include "stap-probe.h"
63 #include "user-regs.h"
64 #include "cli/cli-utils.h"
65 #include "expression.h"
66 #include "parser-defs.h"
71 static const char *i386_register_names[] =
73 "eax", "ecx", "edx", "ebx",
74 "esp", "ebp", "esi", "edi",
75 "eip", "eflags", "cs", "ss",
76 "ds", "es", "fs", "gs",
77 "st0", "st1", "st2", "st3",
78 "st4", "st5", "st6", "st7",
79 "fctrl", "fstat", "ftag", "fiseg",
80 "fioff", "foseg", "fooff", "fop",
81 "xmm0", "xmm1", "xmm2", "xmm3",
82 "xmm4", "xmm5", "xmm6", "xmm7",
86 static const char *i386_zmm_names[] =
88 "zmm0", "zmm1", "zmm2", "zmm3",
89 "zmm4", "zmm5", "zmm6", "zmm7"
92 static const char *i386_zmmh_names[] =
94 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
95 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
98 static const char *i386_k_names[] =
100 "k0", "k1", "k2", "k3",
101 "k4", "k5", "k6", "k7"
104 static const char *i386_ymm_names[] =
106 "ymm0", "ymm1", "ymm2", "ymm3",
107 "ymm4", "ymm5", "ymm6", "ymm7",
110 static const char *i386_ymmh_names[] =
112 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
113 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
116 static const char *i386_mpx_names[] =
118 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
121 /* Register names for MPX pseudo-registers. */
123 static const char *i386_bnd_names[] =
125 "bnd0", "bnd1", "bnd2", "bnd3"
128 /* Register names for MMX pseudo-registers. */
130 static const char *i386_mmx_names[] =
132 "mm0", "mm1", "mm2", "mm3",
133 "mm4", "mm5", "mm6", "mm7"
136 /* Register names for byte pseudo-registers. */
138 static const char *i386_byte_names[] =
140 "al", "cl", "dl", "bl",
141 "ah", "ch", "dh", "bh"
144 /* Register names for word pseudo-registers. */
146 static const char *i386_word_names[] =
148 "ax", "cx", "dx", "bx",
152 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
153 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
154 we have 16 upper ZMM regs that have to be handled differently. */
156 const int num_lower_zmm_regs = 16;
161 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
163 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
164 int mm0_regnum = tdep->mm0_regnum;
169 regnum -= mm0_regnum;
170 return regnum >= 0 && regnum < tdep->num_mmx_regs;
176 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
178 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
180 regnum -= tdep->al_regnum;
181 return regnum >= 0 && regnum < tdep->num_byte_regs;
187 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
189 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
191 regnum -= tdep->ax_regnum;
192 return regnum >= 0 && regnum < tdep->num_word_regs;
195 /* Dword register? */
198 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
200 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
201 int eax_regnum = tdep->eax_regnum;
206 regnum -= eax_regnum;
207 return regnum >= 0 && regnum < tdep->num_dword_regs;
210 /* AVX512 register? */
213 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
215 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
216 int zmm0h_regnum = tdep->zmm0h_regnum;
218 if (zmm0h_regnum < 0)
221 regnum -= zmm0h_regnum;
222 return regnum >= 0 && regnum < tdep->num_zmm_regs;
226 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
228 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 int zmm0_regnum = tdep->zmm0_regnum;
234 regnum -= zmm0_regnum;
235 return regnum >= 0 && regnum < tdep->num_zmm_regs;
239 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
241 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
242 int k0_regnum = tdep->k0_regnum;
248 return regnum >= 0 && regnum < I387_NUM_K_REGS;
252 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
254 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
255 int ymm0h_regnum = tdep->ymm0h_regnum;
257 if (ymm0h_regnum < 0)
260 regnum -= ymm0h_regnum;
261 return regnum >= 0 && regnum < tdep->num_ymm_regs;
267 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
270 int ymm0_regnum = tdep->ymm0_regnum;
275 regnum -= ymm0_regnum;
276 return regnum >= 0 && regnum < tdep->num_ymm_regs;
280 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
282 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
283 int ymm16h_regnum = tdep->ymm16h_regnum;
285 if (ymm16h_regnum < 0)
288 regnum -= ymm16h_regnum;
289 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
293 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
295 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
296 int ymm16_regnum = tdep->ymm16_regnum;
298 if (ymm16_regnum < 0)
301 regnum -= ymm16_regnum;
302 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
308 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
310 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
311 int bnd0_regnum = tdep->bnd0_regnum;
316 regnum -= bnd0_regnum;
317 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
323 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
325 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
326 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
328 if (num_xmm_regs == 0)
331 regnum -= I387_XMM0_REGNUM (tdep);
332 return regnum >= 0 && regnum < num_xmm_regs;
335 /* XMM_512 register? */
338 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
340 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
341 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
343 if (num_xmm_avx512_regs == 0)
346 regnum -= I387_XMM16_REGNUM (tdep);
347 return regnum >= 0 && regnum < num_xmm_avx512_regs;
351 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
353 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
355 if (I387_NUM_XMM_REGS (tdep) == 0)
358 return (regnum == I387_MXCSR_REGNUM (tdep));
364 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
366 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
368 if (I387_ST0_REGNUM (tdep) < 0)
371 return (I387_ST0_REGNUM (tdep) <= regnum
372 && regnum < I387_FCTRL_REGNUM (tdep));
376 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
378 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
380 if (I387_ST0_REGNUM (tdep) < 0)
383 return (I387_FCTRL_REGNUM (tdep) <= regnum
384 && regnum < I387_XMM0_REGNUM (tdep));
387 /* BNDr (raw) register? */
390 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
392 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
394 if (I387_BND0R_REGNUM (tdep) < 0)
397 regnum -= tdep->bnd0r_regnum;
398 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
401 /* BND control register? */
404 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
406 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
408 if (I387_BNDCFGU_REGNUM (tdep) < 0)
411 regnum -= I387_BNDCFGU_REGNUM (tdep);
412 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
415 /* Return the name of register REGNUM, or the empty string if it is
416 an anonymous register. */
419 i386_register_name (struct gdbarch *gdbarch, int regnum)
421 /* Hide the upper YMM registers. */
422 if (i386_ymmh_regnum_p (gdbarch, regnum))
425 /* Hide the upper YMM16-31 registers. */
426 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
429 /* Hide the upper ZMM registers. */
430 if (i386_zmmh_regnum_p (gdbarch, regnum))
433 return tdesc_register_name (gdbarch, regnum);
436 /* Return the name of register REGNUM. */
439 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
442 if (i386_bnd_regnum_p (gdbarch, regnum))
443 return i386_bnd_names[regnum - tdep->bnd0_regnum];
444 if (i386_mmx_regnum_p (gdbarch, regnum))
445 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
446 else if (i386_ymm_regnum_p (gdbarch, regnum))
447 return i386_ymm_names[regnum - tdep->ymm0_regnum];
448 else if (i386_zmm_regnum_p (gdbarch, regnum))
449 return i386_zmm_names[regnum - tdep->zmm0_regnum];
450 else if (i386_byte_regnum_p (gdbarch, regnum))
451 return i386_byte_names[regnum - tdep->al_regnum];
452 else if (i386_word_regnum_p (gdbarch, regnum))
453 return i386_word_names[regnum - tdep->ax_regnum];
455 internal_error (__FILE__, __LINE__, _("invalid regnum"));
458 /* Convert a dbx register number REG to the appropriate register
459 number used by GDB. */
462 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
464 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
466 /* This implements what GCC calls the "default" register map
467 (dbx_register_map[]). */
469 if (reg >= 0 && reg <= 7)
471 /* General-purpose registers. The debug info calls %ebp
472 register 4, and %esp register 5. */
479 else if (reg >= 12 && reg <= 19)
481 /* Floating-point registers. */
482 return reg - 12 + I387_ST0_REGNUM (tdep);
484 else if (reg >= 21 && reg <= 28)
487 int ymm0_regnum = tdep->ymm0_regnum;
490 && i386_xmm_regnum_p (gdbarch, reg))
491 return reg - 21 + ymm0_regnum;
493 return reg - 21 + I387_XMM0_REGNUM (tdep);
495 else if (reg >= 29 && reg <= 36)
498 return reg - 29 + I387_MM0_REGNUM (tdep);
501 /* This will hopefully provoke a warning. */
502 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
505 /* Convert SVR4 DWARF register number REG to the appropriate register number
509 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
511 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
513 /* This implements the GCC register map that tries to be compatible
514 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
516 /* The SVR4 register numbering includes %eip and %eflags, and
517 numbers the floating point registers differently. */
518 if (reg >= 0 && reg <= 9)
520 /* General-purpose registers. */
523 else if (reg >= 11 && reg <= 18)
525 /* Floating-point registers. */
526 return reg - 11 + I387_ST0_REGNUM (tdep);
528 else if (reg >= 21 && reg <= 36)
530 /* The SSE and MMX registers have the same numbers as with dbx. */
531 return i386_dbx_reg_to_regnum (gdbarch, reg);
536 case 37: return I387_FCTRL_REGNUM (tdep);
537 case 38: return I387_FSTAT_REGNUM (tdep);
538 case 39: return I387_MXCSR_REGNUM (tdep);
539 case 40: return I386_ES_REGNUM;
540 case 41: return I386_CS_REGNUM;
541 case 42: return I386_SS_REGNUM;
542 case 43: return I386_DS_REGNUM;
543 case 44: return I386_FS_REGNUM;
544 case 45: return I386_GS_REGNUM;
550 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
551 num_regs + num_pseudo_regs for other debug formats. */
554 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
556 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
559 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
565 /* This is the variable that is set with "set disassembly-flavor", and
566 its legitimate values. */
567 static const char att_flavor[] = "att";
568 static const char intel_flavor[] = "intel";
569 static const char *const valid_flavors[] =
575 static const char *disassembly_flavor = att_flavor;
578 /* Use the program counter to determine the contents and size of a
579 breakpoint instruction. Return a pointer to a string of bytes that
580 encode a breakpoint instruction, store the length of the string in
581 *LEN and optionally adjust *PC to point to the correct memory
582 location for inserting the breakpoint.
584 On the i386 we have a single breakpoint that fits in a single byte
585 and can be inserted anywhere.
587 This function is 64-bit safe. */
589 static const gdb_byte *
590 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
592 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
594 *len = sizeof (break_insn);
598 /* Displaced instruction handling. */
600 /* Skip the legacy instruction prefixes in INSN.
601 Not all prefixes are valid for any particular insn
602 but we needn't care, the insn will fault if it's invalid.
603 The result is a pointer to the first opcode byte,
604 or NULL if we run off the end of the buffer. */
607 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
609 gdb_byte *end = insn + max_len;
615 case DATA_PREFIX_OPCODE:
616 case ADDR_PREFIX_OPCODE:
617 case CS_PREFIX_OPCODE:
618 case DS_PREFIX_OPCODE:
619 case ES_PREFIX_OPCODE:
620 case FS_PREFIX_OPCODE:
621 case GS_PREFIX_OPCODE:
622 case SS_PREFIX_OPCODE:
623 case LOCK_PREFIX_OPCODE:
624 case REPE_PREFIX_OPCODE:
625 case REPNE_PREFIX_OPCODE:
637 i386_absolute_jmp_p (const gdb_byte *insn)
639 /* jmp far (absolute address in operand). */
645 /* jump near, absolute indirect (/4). */
646 if ((insn[1] & 0x38) == 0x20)
649 /* jump far, absolute indirect (/5). */
650 if ((insn[1] & 0x38) == 0x28)
657 /* Return non-zero if INSN is a jump, zero otherwise. */
660 i386_jmp_p (const gdb_byte *insn)
662 /* jump short, relative. */
666 /* jump near, relative. */
670 return i386_absolute_jmp_p (insn);
674 i386_absolute_call_p (const gdb_byte *insn)
676 /* call far, absolute. */
682 /* Call near, absolute indirect (/2). */
683 if ((insn[1] & 0x38) == 0x10)
686 /* Call far, absolute indirect (/3). */
687 if ((insn[1] & 0x38) == 0x18)
695 i386_ret_p (const gdb_byte *insn)
699 case 0xc2: /* ret near, pop N bytes. */
700 case 0xc3: /* ret near */
701 case 0xca: /* ret far, pop N bytes. */
702 case 0xcb: /* ret far */
703 case 0xcf: /* iret */
712 i386_call_p (const gdb_byte *insn)
714 if (i386_absolute_call_p (insn))
717 /* call near, relative. */
724 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
725 length in bytes. Otherwise, return zero. */
728 i386_syscall_p (const gdb_byte *insn, int *lengthp)
730 /* Is it 'int $0x80'? */
731 if ((insn[0] == 0xcd && insn[1] == 0x80)
732 /* Or is it 'sysenter'? */
733 || (insn[0] == 0x0f && insn[1] == 0x34)
734 /* Or is it 'syscall'? */
735 || (insn[0] == 0x0f && insn[1] == 0x05))
744 /* The gdbarch insn_is_call method. */
747 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
749 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
751 read_code (addr, buf, I386_MAX_INSN_LEN);
752 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
754 return i386_call_p (insn);
757 /* The gdbarch insn_is_ret method. */
760 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
762 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
764 read_code (addr, buf, I386_MAX_INSN_LEN);
765 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
767 return i386_ret_p (insn);
770 /* The gdbarch insn_is_jump method. */
773 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
775 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
777 read_code (addr, buf, I386_MAX_INSN_LEN);
778 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
780 return i386_jmp_p (insn);
783 /* Some kernels may run one past a syscall insn, so we have to cope.
784 Otherwise this is just simple_displaced_step_copy_insn. */
786 struct displaced_step_closure *
787 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
788 CORE_ADDR from, CORE_ADDR to,
789 struct regcache *regs)
791 size_t len = gdbarch_max_insn_length (gdbarch);
792 gdb_byte *buf = (gdb_byte *) xmalloc (len);
794 read_memory (from, buf, len);
796 /* GDB may get control back after the insn after the syscall.
797 Presumably this is a kernel bug.
798 If this is a syscall, make sure there's a nop afterwards. */
803 insn = i386_skip_prefixes (buf, len);
804 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
805 insn[syscall_length] = NOP_OPCODE;
808 write_memory (to, buf, len);
812 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
813 paddress (gdbarch, from), paddress (gdbarch, to));
814 displaced_step_dump_bytes (gdb_stdlog, buf, len);
817 return (struct displaced_step_closure *) buf;
820 /* Fix up the state of registers and memory after having single-stepped
821 a displaced instruction. */
824 i386_displaced_step_fixup (struct gdbarch *gdbarch,
825 struct displaced_step_closure *closure,
826 CORE_ADDR from, CORE_ADDR to,
827 struct regcache *regs)
829 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
831 /* The offset we applied to the instruction's address.
832 This could well be negative (when viewed as a signed 32-bit
833 value), but ULONGEST won't reflect that, so take care when
835 ULONGEST insn_offset = to - from;
837 /* Since we use simple_displaced_step_copy_insn, our closure is a
838 copy of the instruction. */
839 gdb_byte *insn = (gdb_byte *) closure;
840 /* The start of the insn, needed in case we see some prefixes. */
841 gdb_byte *insn_start = insn;
844 fprintf_unfiltered (gdb_stdlog,
845 "displaced: fixup (%s, %s), "
846 "insn = 0x%02x 0x%02x ...\n",
847 paddress (gdbarch, from), paddress (gdbarch, to),
850 /* The list of issues to contend with here is taken from
851 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
852 Yay for Free Software! */
854 /* Relocate the %eip, if necessary. */
856 /* The instruction recognizers we use assume any leading prefixes
857 have been skipped. */
859 /* This is the size of the buffer in closure. */
860 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
861 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
862 /* If there are too many prefixes, just ignore the insn.
863 It will fault when run. */
868 /* Except in the case of absolute or indirect jump or call
869 instructions, or a return instruction, the new eip is relative to
870 the displaced instruction; make it relative. Well, signal
871 handler returns don't need relocation either, but we use the
872 value of %eip to recognize those; see below. */
873 if (! i386_absolute_jmp_p (insn)
874 && ! i386_absolute_call_p (insn)
875 && ! i386_ret_p (insn))
880 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
882 /* A signal trampoline system call changes the %eip, resuming
883 execution of the main program after the signal handler has
884 returned. That makes them like 'return' instructions; we
885 shouldn't relocate %eip.
887 But most system calls don't, and we do need to relocate %eip.
889 Our heuristic for distinguishing these cases: if stepping
890 over the system call instruction left control directly after
891 the instruction, the we relocate --- control almost certainly
892 doesn't belong in the displaced copy. Otherwise, we assume
893 the instruction has put control where it belongs, and leave
894 it unrelocated. Goodness help us if there are PC-relative
896 if (i386_syscall_p (insn, &insn_len)
897 && orig_eip != to + (insn - insn_start) + insn_len
898 /* GDB can get control back after the insn after the syscall.
899 Presumably this is a kernel bug.
900 i386_displaced_step_copy_insn ensures its a nop,
901 we add one to the length for it. */
902 && orig_eip != to + (insn - insn_start) + insn_len + 1)
905 fprintf_unfiltered (gdb_stdlog,
906 "displaced: syscall changed %%eip; "
911 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
913 /* If we just stepped over a breakpoint insn, we don't backup
914 the pc on purpose; this is to match behaviour without
917 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
920 fprintf_unfiltered (gdb_stdlog,
922 "relocated %%eip from %s to %s\n",
923 paddress (gdbarch, orig_eip),
924 paddress (gdbarch, eip));
928 /* If the instruction was PUSHFL, then the TF bit will be set in the
929 pushed value, and should be cleared. We'll leave this for later,
930 since GDB already messes up the TF flag when stepping over a
933 /* If the instruction was a call, the return address now atop the
934 stack is the address following the copied instruction. We need
935 to make it the address following the original instruction. */
936 if (i386_call_p (insn))
940 const ULONGEST retaddr_len = 4;
942 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
943 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
944 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
945 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
948 fprintf_unfiltered (gdb_stdlog,
949 "displaced: relocated return addr at %s to %s\n",
950 paddress (gdbarch, esp),
951 paddress (gdbarch, retaddr));
956 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
958 target_write_memory (*to, buf, len);
963 i386_relocate_instruction (struct gdbarch *gdbarch,
964 CORE_ADDR *to, CORE_ADDR oldloc)
966 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
967 gdb_byte buf[I386_MAX_INSN_LEN];
968 int offset = 0, rel32, newrel;
970 gdb_byte *insn = buf;
972 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
974 insn_length = gdb_buffered_insn_length (gdbarch, insn,
975 I386_MAX_INSN_LEN, oldloc);
977 /* Get past the prefixes. */
978 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
980 /* Adjust calls with 32-bit relative addresses as push/jump, with
981 the address pushed being the location where the original call in
982 the user program would return to. */
985 gdb_byte push_buf[16];
986 unsigned int ret_addr;
988 /* Where "ret" in the original code will return to. */
989 ret_addr = oldloc + insn_length;
990 push_buf[0] = 0x68; /* pushq $... */
991 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
993 append_insns (to, 5, push_buf);
995 /* Convert the relative call to a relative jump. */
998 /* Adjust the destination offset. */
999 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1000 newrel = (oldloc - *to) + rel32;
1001 store_signed_integer (insn + 1, 4, byte_order, newrel);
1003 if (debug_displaced)
1004 fprintf_unfiltered (gdb_stdlog,
1005 "Adjusted insn rel32=%s at %s to"
1006 " rel32=%s at %s\n",
1007 hex_string (rel32), paddress (gdbarch, oldloc),
1008 hex_string (newrel), paddress (gdbarch, *to));
1010 /* Write the adjusted jump into its displaced location. */
1011 append_insns (to, 5, insn);
1015 /* Adjust jumps with 32-bit relative addresses. Calls are already
1017 if (insn[0] == 0xe9)
1019 /* Adjust conditional jumps. */
1020 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1025 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1026 newrel = (oldloc - *to) + rel32;
1027 store_signed_integer (insn + offset, 4, byte_order, newrel);
1028 if (debug_displaced)
1029 fprintf_unfiltered (gdb_stdlog,
1030 "Adjusted insn rel32=%s at %s to"
1031 " rel32=%s at %s\n",
1032 hex_string (rel32), paddress (gdbarch, oldloc),
1033 hex_string (newrel), paddress (gdbarch, *to));
1036 /* Write the adjusted instructions into their displaced
1038 append_insns (to, insn_length, buf);
1042 #ifdef I386_REGNO_TO_SYMMETRY
1043 #error "The Sequent Symmetry is no longer supported."
1046 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1047 and %esp "belong" to the calling function. Therefore these
1048 registers should be saved if they're going to be modified. */
1050 /* The maximum number of saved registers. This should include all
1051 registers mentioned above, and %eip. */
1052 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1054 struct i386_frame_cache
1062 /* Saved registers. */
1063 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1068 /* Stack space reserved for local variables. */
1072 /* Allocate and initialize a frame cache. */
1074 static struct i386_frame_cache *
1075 i386_alloc_frame_cache (void)
1077 struct i386_frame_cache *cache;
1080 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1085 cache->sp_offset = -4;
1088 /* Saved registers. We initialize these to -1 since zero is a valid
1089 offset (that's where %ebp is supposed to be stored). */
1090 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1091 cache->saved_regs[i] = -1;
1092 cache->saved_sp = 0;
1093 cache->saved_sp_reg = -1;
1094 cache->pc_in_eax = 0;
1096 /* Frameless until proven otherwise. */
1102 /* If the instruction at PC is a jump, return the address of its
1103 target. Otherwise, return PC. */
1106 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1108 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1113 if (target_read_code (pc, &op, 1))
1120 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1126 /* Relative jump: if data16 == 0, disp32, else disp16. */
1129 delta = read_memory_integer (pc + 2, 2, byte_order);
1131 /* Include the size of the jmp instruction (including the
1137 delta = read_memory_integer (pc + 1, 4, byte_order);
1139 /* Include the size of the jmp instruction. */
1144 /* Relative jump, disp8 (ignore data16). */
1145 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1147 delta += data16 + 2;
1154 /* Check whether PC points at a prologue for a function returning a
1155 structure or union. If so, it updates CACHE and returns the
1156 address of the first instruction after the code sequence that
1157 removes the "hidden" argument from the stack or CURRENT_PC,
1158 whichever is smaller. Otherwise, return PC. */
1161 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1162 struct i386_frame_cache *cache)
1164 /* Functions that return a structure or union start with:
1167 xchgl %eax, (%esp) 0x87 0x04 0x24
1168 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1170 (the System V compiler puts out the second `xchg' instruction,
1171 and the assembler doesn't try to optimize it, so the 'sib' form
1172 gets generated). This sequence is used to get the address of the
1173 return buffer for a function that returns a structure. */
1174 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1175 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1179 if (current_pc <= pc)
1182 if (target_read_code (pc, &op, 1))
1185 if (op != 0x58) /* popl %eax */
1188 if (target_read_code (pc + 1, buf, 4))
1191 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1194 if (current_pc == pc)
1196 cache->sp_offset += 4;
1200 if (current_pc == pc + 1)
1202 cache->pc_in_eax = 1;
1206 if (buf[1] == proto1[1])
1213 i386_skip_probe (CORE_ADDR pc)
1215 /* A function may start with
1229 if (target_read_code (pc, &op, 1))
1232 if (op == 0x68 || op == 0x6a)
1236 /* Skip past the `pushl' instruction; it has either a one-byte or a
1237 four-byte operand, depending on the opcode. */
1243 /* Read the following 8 bytes, which should be `call _probe' (6
1244 bytes) followed by `addl $4,%esp' (2 bytes). */
1245 read_memory (pc + delta, buf, sizeof (buf));
1246 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1247 pc += delta + sizeof (buf);
1253 /* GCC 4.1 and later, can put code in the prologue to realign the
1254 stack pointer. Check whether PC points to such code, and update
1255 CACHE accordingly. Return the first instruction after the code
1256 sequence or CURRENT_PC, whichever is smaller. If we don't
1257 recognize the code, return PC. */
1260 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1261 struct i386_frame_cache *cache)
1263 /* There are 2 code sequences to re-align stack before the frame
1266 1. Use a caller-saved saved register:
1272 2. Use a callee-saved saved register:
1279 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1281 0x83 0xe4 0xf0 andl $-16, %esp
1282 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1287 int offset, offset_and;
1288 static int regnums[8] = {
1289 I386_EAX_REGNUM, /* %eax */
1290 I386_ECX_REGNUM, /* %ecx */
1291 I386_EDX_REGNUM, /* %edx */
1292 I386_EBX_REGNUM, /* %ebx */
1293 I386_ESP_REGNUM, /* %esp */
1294 I386_EBP_REGNUM, /* %ebp */
1295 I386_ESI_REGNUM, /* %esi */
1296 I386_EDI_REGNUM /* %edi */
1299 if (target_read_code (pc, buf, sizeof buf))
1302 /* Check caller-saved saved register. The first instruction has
1303 to be "leal 4(%esp), %reg". */
1304 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1306 /* MOD must be binary 10 and R/M must be binary 100. */
1307 if ((buf[1] & 0xc7) != 0x44)
1310 /* REG has register number. */
1311 reg = (buf[1] >> 3) & 7;
1316 /* Check callee-saved saved register. The first instruction
1317 has to be "pushl %reg". */
1318 if ((buf[0] & 0xf8) != 0x50)
1324 /* The next instruction has to be "leal 8(%esp), %reg". */
1325 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1328 /* MOD must be binary 10 and R/M must be binary 100. */
1329 if ((buf[2] & 0xc7) != 0x44)
1332 /* REG has register number. Registers in pushl and leal have to
1334 if (reg != ((buf[2] >> 3) & 7))
1340 /* Rigister can't be %esp nor %ebp. */
1341 if (reg == 4 || reg == 5)
1344 /* The next instruction has to be "andl $-XXX, %esp". */
1345 if (buf[offset + 1] != 0xe4
1346 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1349 offset_and = offset;
1350 offset += buf[offset] == 0x81 ? 6 : 3;
1352 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1353 0xfc. REG must be binary 110 and MOD must be binary 01. */
1354 if (buf[offset] != 0xff
1355 || buf[offset + 2] != 0xfc
1356 || (buf[offset + 1] & 0xf8) != 0x70)
1359 /* R/M has register. Registers in leal and pushl have to be the
1361 if (reg != (buf[offset + 1] & 7))
1364 if (current_pc > pc + offset_and)
1365 cache->saved_sp_reg = regnums[reg];
1367 return min (pc + offset + 3, current_pc);
1370 /* Maximum instruction length we need to handle. */
1371 #define I386_MAX_MATCHED_INSN_LEN 6
1373 /* Instruction description. */
1377 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1378 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1381 /* Return whether instruction at PC matches PATTERN. */
1384 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1388 if (target_read_code (pc, &op, 1))
1391 if ((op & pattern.mask[0]) == pattern.insn[0])
1393 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1394 int insn_matched = 1;
1397 gdb_assert (pattern.len > 1);
1398 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1400 if (target_read_code (pc + 1, buf, pattern.len - 1))
1403 for (i = 1; i < pattern.len; i++)
1405 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1408 return insn_matched;
1413 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1414 the first instruction description that matches. Otherwise, return
1417 static struct i386_insn *
1418 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1420 struct i386_insn *pattern;
1422 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1424 if (i386_match_pattern (pc, *pattern))
1431 /* Return whether PC points inside a sequence of instructions that
1432 matches INSN_PATTERNS. */
1435 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1437 CORE_ADDR current_pc;
1439 struct i386_insn *insn;
1441 insn = i386_match_insn (pc, insn_patterns);
1446 ix = insn - insn_patterns;
1447 for (i = ix - 1; i >= 0; i--)
1449 current_pc -= insn_patterns[i].len;
1451 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1455 current_pc = pc + insn->len;
1456 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1458 if (!i386_match_pattern (current_pc, *insn))
1461 current_pc += insn->len;
1467 /* Some special instructions that might be migrated by GCC into the
1468 part of the prologue that sets up the new stack frame. Because the
1469 stack frame hasn't been setup yet, no registers have been saved
1470 yet, and only the scratch registers %eax, %ecx and %edx can be
1473 struct i386_insn i386_frame_setup_skip_insns[] =
1475 /* Check for `movb imm8, r' and `movl imm32, r'.
1477 ??? Should we handle 16-bit operand-sizes here? */
1479 /* `movb imm8, %al' and `movb imm8, %ah' */
1480 /* `movb imm8, %cl' and `movb imm8, %ch' */
1481 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1482 /* `movb imm8, %dl' and `movb imm8, %dh' */
1483 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1484 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1485 { 5, { 0xb8 }, { 0xfe } },
1486 /* `movl imm32, %edx' */
1487 { 5, { 0xba }, { 0xff } },
1489 /* Check for `mov imm32, r32'. Note that there is an alternative
1490 encoding for `mov m32, %eax'.
1492 ??? Should we handle SIB adressing here?
1493 ??? Should we handle 16-bit operand-sizes here? */
1495 /* `movl m32, %eax' */
1496 { 5, { 0xa1 }, { 0xff } },
1497 /* `movl m32, %eax' and `mov; m32, %ecx' */
1498 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1499 /* `movl m32, %edx' */
1500 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1502 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1503 Because of the symmetry, there are actually two ways to encode
1504 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1505 opcode bytes 0x31 and 0x33 for `xorl'. */
1507 /* `subl %eax, %eax' */
1508 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1509 /* `subl %ecx, %ecx' */
1510 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1511 /* `subl %edx, %edx' */
1512 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1513 /* `xorl %eax, %eax' */
1514 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1515 /* `xorl %ecx, %ecx' */
1516 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1517 /* `xorl %edx, %edx' */
1518 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1523 /* Check whether PC points to a no-op instruction. */
1525 i386_skip_noop (CORE_ADDR pc)
1530 if (target_read_code (pc, &op, 1))
1536 /* Ignore `nop' instruction. */
1540 if (target_read_code (pc, &op, 1))
1544 /* Ignore no-op instruction `mov %edi, %edi'.
1545 Microsoft system dlls often start with
1546 a `mov %edi,%edi' instruction.
1547 The 5 bytes before the function start are
1548 filled with `nop' instructions.
1549 This pattern can be used for hot-patching:
1550 The `mov %edi, %edi' instruction can be replaced by a
1551 near jump to the location of the 5 `nop' instructions
1552 which can be replaced by a 32-bit jump to anywhere
1553 in the 32-bit address space. */
1555 else if (op == 0x8b)
1557 if (target_read_code (pc + 1, &op, 1))
1563 if (target_read_code (pc, &op, 1))
1573 /* Check whether PC points at a code that sets up a new stack frame.
1574 If so, it updates CACHE and returns the address of the first
1575 instruction after the sequence that sets up the frame or LIMIT,
1576 whichever is smaller. If we don't recognize the code, return PC. */
1579 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1580 CORE_ADDR pc, CORE_ADDR limit,
1581 struct i386_frame_cache *cache)
1583 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1584 struct i386_insn *insn;
1591 if (target_read_code (pc, &op, 1))
1594 if (op == 0x55) /* pushl %ebp */
1596 /* Take into account that we've executed the `pushl %ebp' that
1597 starts this instruction sequence. */
1598 cache->saved_regs[I386_EBP_REGNUM] = 0;
1599 cache->sp_offset += 4;
1602 /* If that's all, return now. */
1606 /* Check for some special instructions that might be migrated by
1607 GCC into the prologue and skip them. At this point in the
1608 prologue, code should only touch the scratch registers %eax,
1609 %ecx and %edx, so while the number of posibilities is sheer,
1612 Make sure we only skip these instructions if we later see the
1613 `movl %esp, %ebp' that actually sets up the frame. */
1614 while (pc + skip < limit)
1616 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1623 /* If that's all, return now. */
1624 if (limit <= pc + skip)
1627 if (target_read_code (pc + skip, &op, 1))
1630 /* The i386 prologue looks like
1636 and a different prologue can be generated for atom.
1640 lea -0x10(%esp),%esp
1642 We handle both of them here. */
1646 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1648 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1654 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1659 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1660 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1669 /* OK, we actually have a frame. We just don't know how large
1670 it is yet. Set its size to zero. We'll adjust it if
1671 necessary. We also now commit to skipping the special
1672 instructions mentioned before. */
1675 /* If that's all, return now. */
1679 /* Check for stack adjustment
1685 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1686 reg, so we don't have to worry about a data16 prefix. */
1687 if (target_read_code (pc, &op, 1))
1691 /* `subl' with 8-bit immediate. */
1692 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1693 /* Some instruction starting with 0x83 other than `subl'. */
1696 /* `subl' with signed 8-bit immediate (though it wouldn't
1697 make sense to be negative). */
1698 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1701 else if (op == 0x81)
1703 /* Maybe it is `subl' with a 32-bit immediate. */
1704 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1705 /* Some instruction starting with 0x81 other than `subl'. */
1708 /* It is `subl' with a 32-bit immediate. */
1709 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1712 else if (op == 0x8d)
1714 /* The ModR/M byte is 0x64. */
1715 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1717 /* 'lea' with 8-bit displacement. */
1718 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1723 /* Some instruction other than `subl' nor 'lea'. */
1727 else if (op == 0xc8) /* enter */
1729 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1736 /* Check whether PC points at code that saves registers on the stack.
1737 If so, it updates CACHE and returns the address of the first
1738 instruction after the register saves or CURRENT_PC, whichever is
1739 smaller. Otherwise, return PC. */
1742 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1743 struct i386_frame_cache *cache)
1745 CORE_ADDR offset = 0;
1749 if (cache->locals > 0)
1750 offset -= cache->locals;
1751 for (i = 0; i < 8 && pc < current_pc; i++)
1753 if (target_read_code (pc, &op, 1))
1755 if (op < 0x50 || op > 0x57)
1759 cache->saved_regs[op - 0x50] = offset;
1760 cache->sp_offset += 4;
1767 /* Do a full analysis of the prologue at PC and update CACHE
1768 accordingly. Bail out early if CURRENT_PC is reached. Return the
1769 address where the analysis stopped.
1771 We handle these cases:
1773 The startup sequence can be at the start of the function, or the
1774 function can start with a branch to startup code at the end.
1776 %ebp can be set up with either the 'enter' instruction, or "pushl
1777 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1778 once used in the System V compiler).
1780 Local space is allocated just below the saved %ebp by either the
1781 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1782 16-bit unsigned argument for space to allocate, and the 'addl'
1783 instruction could have either a signed byte, or 32-bit immediate.
1785 Next, the registers used by this function are pushed. With the
1786 System V compiler they will always be in the order: %edi, %esi,
1787 %ebx (and sometimes a harmless bug causes it to also save but not
1788 restore %eax); however, the code below is willing to see the pushes
1789 in any order, and will handle up to 8 of them.
1791 If the setup sequence is at the end of the function, then the next
1792 instruction will be a branch back to the start. */
1795 i386_analyze_prologue (struct gdbarch *gdbarch,
1796 CORE_ADDR pc, CORE_ADDR current_pc,
1797 struct i386_frame_cache *cache)
1799 pc = i386_skip_noop (pc);
1800 pc = i386_follow_jump (gdbarch, pc);
1801 pc = i386_analyze_struct_return (pc, current_pc, cache);
1802 pc = i386_skip_probe (pc);
1803 pc = i386_analyze_stack_align (pc, current_pc, cache);
1804 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1805 return i386_analyze_register_saves (pc, current_pc, cache);
1808 /* Return PC of first real instruction. */
1811 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1813 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1815 static gdb_byte pic_pat[6] =
1817 0xe8, 0, 0, 0, 0, /* call 0x0 */
1818 0x5b, /* popl %ebx */
1820 struct i386_frame_cache cache;
1824 CORE_ADDR func_addr;
1826 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1828 CORE_ADDR post_prologue_pc
1829 = skip_prologue_using_sal (gdbarch, func_addr);
1830 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1832 /* Clang always emits a line note before the prologue and another
1833 one after. We trust clang to emit usable line notes. */
1834 if (post_prologue_pc
1836 && COMPUNIT_PRODUCER (cust) != NULL
1837 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1838 return max (start_pc, post_prologue_pc);
1842 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1843 if (cache.locals < 0)
1846 /* Found valid frame setup. */
1848 /* The native cc on SVR4 in -K PIC mode inserts the following code
1849 to get the address of the global offset table (GOT) into register
1854 movl %ebx,x(%ebp) (optional)
1857 This code is with the rest of the prologue (at the end of the
1858 function), so we have to skip it to get to the first real
1859 instruction at the start of the function. */
1861 for (i = 0; i < 6; i++)
1863 if (target_read_code (pc + i, &op, 1))
1866 if (pic_pat[i] != op)
1873 if (target_read_code (pc + delta, &op, 1))
1876 if (op == 0x89) /* movl %ebx, x(%ebp) */
1878 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1880 if (op == 0x5d) /* One byte offset from %ebp. */
1882 else if (op == 0x9d) /* Four byte offset from %ebp. */
1884 else /* Unexpected instruction. */
1887 if (target_read_code (pc + delta, &op, 1))
1892 if (delta > 0 && op == 0x81
1893 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1900 /* If the function starts with a branch (to startup code at the end)
1901 the last instruction should bring us back to the first
1902 instruction of the real code. */
1903 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1904 pc = i386_follow_jump (gdbarch, pc);
1909 /* Check that the code pointed to by PC corresponds to a call to
1910 __main, skip it if so. Return PC otherwise. */
1913 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1915 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1918 if (target_read_code (pc, &op, 1))
1924 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1926 /* Make sure address is computed correctly as a 32bit
1927 integer even if CORE_ADDR is 64 bit wide. */
1928 struct bound_minimal_symbol s;
1929 CORE_ADDR call_dest;
1931 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1932 call_dest = call_dest & 0xffffffffU;
1933 s = lookup_minimal_symbol_by_pc (call_dest);
1934 if (s.minsym != NULL
1935 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1936 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1944 /* This function is 64-bit safe. */
1947 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1951 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1952 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1956 /* Normal frames. */
1959 i386_frame_cache_1 (struct frame_info *this_frame,
1960 struct i386_frame_cache *cache)
1962 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1963 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1967 cache->pc = get_frame_func (this_frame);
1969 /* In principle, for normal frames, %ebp holds the frame pointer,
1970 which holds the base address for the current stack frame.
1971 However, for functions that don't need it, the frame pointer is
1972 optional. For these "frameless" functions the frame pointer is
1973 actually the frame pointer of the calling frame. Signal
1974 trampolines are just a special case of a "frameless" function.
1975 They (usually) share their frame pointer with the frame that was
1976 in progress when the signal occurred. */
1978 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1979 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1980 if (cache->base == 0)
1986 /* For normal frames, %eip is stored at 4(%ebp). */
1987 cache->saved_regs[I386_EIP_REGNUM] = 4;
1990 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1993 if (cache->locals < 0)
1995 /* We didn't find a valid frame, which means that CACHE->base
1996 currently holds the frame pointer for our calling frame. If
1997 we're at the start of a function, or somewhere half-way its
1998 prologue, the function's frame probably hasn't been fully
1999 setup yet. Try to reconstruct the base address for the stack
2000 frame by looking at the stack pointer. For truly "frameless"
2001 functions this might work too. */
2003 if (cache->saved_sp_reg != -1)
2005 /* Saved stack pointer has been saved. */
2006 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2007 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2009 /* We're halfway aligning the stack. */
2010 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2011 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2013 /* This will be added back below. */
2014 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2016 else if (cache->pc != 0
2017 || target_read_code (get_frame_pc (this_frame), buf, 1))
2019 /* We're in a known function, but did not find a frame
2020 setup. Assume that the function does not use %ebp.
2021 Alternatively, we may have jumped to an invalid
2022 address; in that case there is definitely no new
2024 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2025 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2029 /* We're in an unknown function. We could not find the start
2030 of the function to analyze the prologue; our best option is
2031 to assume a typical frame layout with the caller's %ebp
2033 cache->saved_regs[I386_EBP_REGNUM] = 0;
2036 if (cache->saved_sp_reg != -1)
2038 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2039 register may be unavailable). */
2040 if (cache->saved_sp == 0
2041 && deprecated_frame_register_read (this_frame,
2042 cache->saved_sp_reg, buf))
2043 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2045 /* Now that we have the base address for the stack frame we can
2046 calculate the value of %esp in the calling frame. */
2047 else if (cache->saved_sp == 0)
2048 cache->saved_sp = cache->base + 8;
2050 /* Adjust all the saved registers such that they contain addresses
2051 instead of offsets. */
2052 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2053 if (cache->saved_regs[i] != -1)
2054 cache->saved_regs[i] += cache->base;
2059 static struct i386_frame_cache *
2060 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2062 struct i386_frame_cache *cache;
2065 return (struct i386_frame_cache *) *this_cache;
2067 cache = i386_alloc_frame_cache ();
2068 *this_cache = cache;
2072 i386_frame_cache_1 (this_frame, cache);
2074 CATCH (ex, RETURN_MASK_ERROR)
2076 if (ex.error != NOT_AVAILABLE_ERROR)
2077 throw_exception (ex);
2085 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2086 struct frame_id *this_id)
2088 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2091 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2092 else if (cache->base == 0)
2094 /* This marks the outermost frame. */
2098 /* See the end of i386_push_dummy_call. */
2099 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2103 static enum unwind_stop_reason
2104 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2107 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2110 return UNWIND_UNAVAILABLE;
2112 /* This marks the outermost frame. */
2113 if (cache->base == 0)
2114 return UNWIND_OUTERMOST;
2116 return UNWIND_NO_REASON;
2119 static struct value *
2120 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2123 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2125 gdb_assert (regnum >= 0);
2127 /* The System V ABI says that:
2129 "The flags register contains the system flags, such as the
2130 direction flag and the carry flag. The direction flag must be
2131 set to the forward (that is, zero) direction before entry and
2132 upon exit from a function. Other user flags have no specified
2133 role in the standard calling sequence and are not preserved."
2135 To guarantee the "upon exit" part of that statement we fake a
2136 saved flags register that has its direction flag cleared.
2138 Note that GCC doesn't seem to rely on the fact that the direction
2139 flag is cleared after a function return; it always explicitly
2140 clears the flag before operations where it matters.
2142 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2143 right thing to do. The way we fake the flags register here makes
2144 it impossible to change it. */
2146 if (regnum == I386_EFLAGS_REGNUM)
2150 val = get_frame_register_unsigned (this_frame, regnum);
2152 return frame_unwind_got_constant (this_frame, regnum, val);
2155 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2156 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2158 if (regnum == I386_ESP_REGNUM
2159 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2161 /* If the SP has been saved, but we don't know where, then this
2162 means that SAVED_SP_REG register was found unavailable back
2163 when we built the cache. */
2164 if (cache->saved_sp == 0)
2165 return frame_unwind_got_register (this_frame, regnum,
2166 cache->saved_sp_reg);
2168 return frame_unwind_got_constant (this_frame, regnum,
2172 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2173 return frame_unwind_got_memory (this_frame, regnum,
2174 cache->saved_regs[regnum]);
2176 return frame_unwind_got_register (this_frame, regnum, regnum);
2179 static const struct frame_unwind i386_frame_unwind =
2182 i386_frame_unwind_stop_reason,
2184 i386_frame_prev_register,
2186 default_frame_sniffer
2189 /* Normal frames, but in a function epilogue. */
2191 /* Implement the stack_frame_destroyed_p gdbarch method.
2193 The epilogue is defined here as the 'ret' instruction, which will
2194 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2195 the function's stack frame. */
2198 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2201 struct compunit_symtab *cust;
2203 cust = find_pc_compunit_symtab (pc);
2204 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2207 if (target_read_memory (pc, &insn, 1))
2208 return 0; /* Can't read memory at pc. */
2210 if (insn != 0xc3) /* 'ret' instruction. */
2217 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2218 struct frame_info *this_frame,
2219 void **this_prologue_cache)
2221 if (frame_relative_level (this_frame) == 0)
2222 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2223 get_frame_pc (this_frame));
2228 static struct i386_frame_cache *
2229 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2231 struct i386_frame_cache *cache;
2235 return (struct i386_frame_cache *) *this_cache;
2237 cache = i386_alloc_frame_cache ();
2238 *this_cache = cache;
2242 cache->pc = get_frame_func (this_frame);
2244 /* At this point the stack looks as if we just entered the
2245 function, with the return address at the top of the
2247 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2248 cache->base = sp + cache->sp_offset;
2249 cache->saved_sp = cache->base + 8;
2250 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2254 CATCH (ex, RETURN_MASK_ERROR)
2256 if (ex.error != NOT_AVAILABLE_ERROR)
2257 throw_exception (ex);
2264 static enum unwind_stop_reason
2265 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2268 struct i386_frame_cache *cache =
2269 i386_epilogue_frame_cache (this_frame, this_cache);
2272 return UNWIND_UNAVAILABLE;
2274 return UNWIND_NO_REASON;
2278 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2280 struct frame_id *this_id)
2282 struct i386_frame_cache *cache =
2283 i386_epilogue_frame_cache (this_frame, this_cache);
2286 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2288 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2291 static struct value *
2292 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2293 void **this_cache, int regnum)
2295 /* Make sure we've initialized the cache. */
2296 i386_epilogue_frame_cache (this_frame, this_cache);
2298 return i386_frame_prev_register (this_frame, this_cache, regnum);
2301 static const struct frame_unwind i386_epilogue_frame_unwind =
2304 i386_epilogue_frame_unwind_stop_reason,
2305 i386_epilogue_frame_this_id,
2306 i386_epilogue_frame_prev_register,
2308 i386_epilogue_frame_sniffer
2312 /* Stack-based trampolines. */
2314 /* These trampolines are used on cross x86 targets, when taking the
2315 address of a nested function. When executing these trampolines,
2316 no stack frame is set up, so we are in a similar situation as in
2317 epilogues and i386_epilogue_frame_this_id can be re-used. */
2319 /* Static chain passed in register. */
2321 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2323 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2324 { 5, { 0xb8 }, { 0xfe } },
2327 { 5, { 0xe9 }, { 0xff } },
2332 /* Static chain passed on stack (when regparm=3). */
2334 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2337 { 5, { 0x68 }, { 0xff } },
2340 { 5, { 0xe9 }, { 0xff } },
2345 /* Return whether PC points inside a stack trampoline. */
2348 i386_in_stack_tramp_p (CORE_ADDR pc)
2353 /* A stack trampoline is detected if no name is associated
2354 to the current pc and if it points inside a trampoline
2357 find_pc_partial_function (pc, &name, NULL, NULL);
2361 if (target_read_memory (pc, &insn, 1))
2364 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2365 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2372 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2373 struct frame_info *this_frame,
2376 if (frame_relative_level (this_frame) == 0)
2377 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2382 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2385 i386_epilogue_frame_unwind_stop_reason,
2386 i386_epilogue_frame_this_id,
2387 i386_epilogue_frame_prev_register,
2389 i386_stack_tramp_frame_sniffer
2392 /* Generate a bytecode expression to get the value of the saved PC. */
2395 i386_gen_return_address (struct gdbarch *gdbarch,
2396 struct agent_expr *ax, struct axs_value *value,
2399 /* The following sequence assumes the traditional use of the base
2401 ax_reg (ax, I386_EBP_REGNUM);
2403 ax_simple (ax, aop_add);
2404 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2405 value->kind = axs_lvalue_memory;
2409 /* Signal trampolines. */
2411 static struct i386_frame_cache *
2412 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2414 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2416 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2417 struct i386_frame_cache *cache;
2422 return (struct i386_frame_cache *) *this_cache;
2424 cache = i386_alloc_frame_cache ();
2428 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2429 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2431 addr = tdep->sigcontext_addr (this_frame);
2432 if (tdep->sc_reg_offset)
2436 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2438 for (i = 0; i < tdep->sc_num_regs; i++)
2439 if (tdep->sc_reg_offset[i] != -1)
2440 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2444 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2445 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2450 CATCH (ex, RETURN_MASK_ERROR)
2452 if (ex.error != NOT_AVAILABLE_ERROR)
2453 throw_exception (ex);
2457 *this_cache = cache;
2461 static enum unwind_stop_reason
2462 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2465 struct i386_frame_cache *cache =
2466 i386_sigtramp_frame_cache (this_frame, this_cache);
2469 return UNWIND_UNAVAILABLE;
2471 return UNWIND_NO_REASON;
2475 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2476 struct frame_id *this_id)
2478 struct i386_frame_cache *cache =
2479 i386_sigtramp_frame_cache (this_frame, this_cache);
2482 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2485 /* See the end of i386_push_dummy_call. */
2486 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2490 static struct value *
2491 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2492 void **this_cache, int regnum)
2494 /* Make sure we've initialized the cache. */
2495 i386_sigtramp_frame_cache (this_frame, this_cache);
2497 return i386_frame_prev_register (this_frame, this_cache, regnum);
2501 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2502 struct frame_info *this_frame,
2503 void **this_prologue_cache)
2505 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2507 /* We shouldn't even bother if we don't have a sigcontext_addr
2509 if (tdep->sigcontext_addr == NULL)
2512 if (tdep->sigtramp_p != NULL)
2514 if (tdep->sigtramp_p (this_frame))
2518 if (tdep->sigtramp_start != 0)
2520 CORE_ADDR pc = get_frame_pc (this_frame);
2522 gdb_assert (tdep->sigtramp_end != 0);
2523 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2530 static const struct frame_unwind i386_sigtramp_frame_unwind =
2533 i386_sigtramp_frame_unwind_stop_reason,
2534 i386_sigtramp_frame_this_id,
2535 i386_sigtramp_frame_prev_register,
2537 i386_sigtramp_frame_sniffer
2542 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2544 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2549 static const struct frame_base i386_frame_base =
2552 i386_frame_base_address,
2553 i386_frame_base_address,
2554 i386_frame_base_address
2557 static struct frame_id
2558 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2562 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2564 /* See the end of i386_push_dummy_call. */
2565 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2568 /* _Decimal128 function return values need 16-byte alignment on the
2572 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2574 return sp & -(CORE_ADDR)16;
2578 /* Figure out where the longjmp will land. Slurp the args out of the
2579 stack. We expect the first arg to be a pointer to the jmp_buf
2580 structure from which we extract the address that we will land at.
2581 This address is copied into PC. This routine returns non-zero on
2585 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2588 CORE_ADDR sp, jb_addr;
2589 struct gdbarch *gdbarch = get_frame_arch (frame);
2590 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2591 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2593 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2594 longjmp will land. */
2595 if (jb_pc_offset == -1)
2598 get_frame_register (frame, I386_ESP_REGNUM, buf);
2599 sp = extract_unsigned_integer (buf, 4, byte_order);
2600 if (target_read_memory (sp + 4, buf, 4))
2603 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2604 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2607 *pc = extract_unsigned_integer (buf, 4, byte_order);
2612 /* Check whether TYPE must be 16-byte-aligned when passed as a
2613 function argument. 16-byte vectors, _Decimal128 and structures or
2614 unions containing such types must be 16-byte-aligned; other
2615 arguments are 4-byte-aligned. */
2618 i386_16_byte_align_p (struct type *type)
2620 type = check_typedef (type);
2621 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2622 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2623 && TYPE_LENGTH (type) == 16)
2625 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2626 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2627 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2628 || TYPE_CODE (type) == TYPE_CODE_UNION)
2631 for (i = 0; i < TYPE_NFIELDS (type); i++)
2633 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2640 /* Implementation for set_gdbarch_push_dummy_code. */
2643 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2644 struct value **args, int nargs, struct type *value_type,
2645 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2646 struct regcache *regcache)
2648 /* Use 0xcc breakpoint - 1 byte. */
2652 /* Keep the stack aligned. */
2657 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2658 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2659 struct value **args, CORE_ADDR sp, int struct_return,
2660 CORE_ADDR struct_addr)
2662 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2668 /* Determine the total space required for arguments and struct
2669 return address in a first pass (allowing for 16-byte-aligned
2670 arguments), then push arguments in a second pass. */
2672 for (write_pass = 0; write_pass < 2; write_pass++)
2674 int args_space_used = 0;
2680 /* Push value address. */
2681 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2682 write_memory (sp, buf, 4);
2683 args_space_used += 4;
2689 for (i = 0; i < nargs; i++)
2691 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2695 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2696 args_space_used = align_up (args_space_used, 16);
2698 write_memory (sp + args_space_used,
2699 value_contents_all (args[i]), len);
2700 /* The System V ABI says that:
2702 "An argument's size is increased, if necessary, to make it a
2703 multiple of [32-bit] words. This may require tail padding,
2704 depending on the size of the argument."
2706 This makes sure the stack stays word-aligned. */
2707 args_space_used += align_up (len, 4);
2711 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2712 args_space = align_up (args_space, 16);
2713 args_space += align_up (len, 4);
2721 /* The original System V ABI only requires word alignment,
2722 but modern incarnations need 16-byte alignment in order
2723 to support SSE. Since wasting a few bytes here isn't
2724 harmful we unconditionally enforce 16-byte alignment. */
2729 /* Store return address. */
2731 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2732 write_memory (sp, buf, 4);
2734 /* Finally, update the stack pointer... */
2735 store_unsigned_integer (buf, 4, byte_order, sp);
2736 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2738 /* ...and fake a frame pointer. */
2739 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2741 /* MarkK wrote: This "+ 8" is all over the place:
2742 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2743 i386_dummy_id). It's there, since all frame unwinders for
2744 a given target have to agree (within a certain margin) on the
2745 definition of the stack address of a frame. Otherwise frame id
2746 comparison might not work correctly. Since DWARF2/GCC uses the
2747 stack address *before* the function call as a frame's CFA. On
2748 the i386, when %ebp is used as a frame pointer, the offset
2749 between the contents %ebp and the CFA as defined by GCC. */
2753 /* These registers are used for returning integers (and on some
2754 targets also for returning `struct' and `union' values when their
2755 size and alignment match an integer type). */
2756 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2757 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2759 /* Read, for architecture GDBARCH, a function return value of TYPE
2760 from REGCACHE, and copy that into VALBUF. */
2763 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2764 struct regcache *regcache, gdb_byte *valbuf)
2766 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2767 int len = TYPE_LENGTH (type);
2768 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2770 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2772 if (tdep->st0_regnum < 0)
2774 warning (_("Cannot find floating-point return value."));
2775 memset (valbuf, 0, len);
2779 /* Floating-point return values can be found in %st(0). Convert
2780 its contents to the desired type. This is probably not
2781 exactly how it would happen on the target itself, but it is
2782 the best we can do. */
2783 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2784 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2788 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2789 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2791 if (len <= low_size)
2793 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2794 memcpy (valbuf, buf, len);
2796 else if (len <= (low_size + high_size))
2798 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2799 memcpy (valbuf, buf, low_size);
2800 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2801 memcpy (valbuf + low_size, buf, len - low_size);
2804 internal_error (__FILE__, __LINE__,
2805 _("Cannot extract return value of %d bytes long."),
2810 /* Write, for architecture GDBARCH, a function return value of TYPE
2811 from VALBUF into REGCACHE. */
2814 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2815 struct regcache *regcache, const gdb_byte *valbuf)
2817 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2818 int len = TYPE_LENGTH (type);
2820 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2823 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2825 if (tdep->st0_regnum < 0)
2827 warning (_("Cannot set floating-point return value."));
2831 /* Returning floating-point values is a bit tricky. Apart from
2832 storing the return value in %st(0), we have to simulate the
2833 state of the FPU at function return point. */
2835 /* Convert the value found in VALBUF to the extended
2836 floating-point format used by the FPU. This is probably
2837 not exactly how it would happen on the target itself, but
2838 it is the best we can do. */
2839 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2840 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2842 /* Set the top of the floating-point register stack to 7. The
2843 actual value doesn't really matter, but 7 is what a normal
2844 function return would end up with if the program started out
2845 with a freshly initialized FPU. */
2846 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2848 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2850 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2851 the floating-point register stack to 7, the appropriate value
2852 for the tag word is 0x3fff. */
2853 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2857 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2858 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2860 if (len <= low_size)
2861 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2862 else if (len <= (low_size + high_size))
2864 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2865 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2866 len - low_size, valbuf + low_size);
2869 internal_error (__FILE__, __LINE__,
2870 _("Cannot store return value of %d bytes long."), len);
2875 /* This is the variable that is set with "set struct-convention", and
2876 its legitimate values. */
2877 static const char default_struct_convention[] = "default";
2878 static const char pcc_struct_convention[] = "pcc";
2879 static const char reg_struct_convention[] = "reg";
2880 static const char *const valid_conventions[] =
2882 default_struct_convention,
2883 pcc_struct_convention,
2884 reg_struct_convention,
2887 static const char *struct_convention = default_struct_convention;
2889 /* Return non-zero if TYPE, which is assumed to be a structure,
2890 a union type, or an array type, should be returned in registers
2891 for architecture GDBARCH. */
2894 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2896 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2897 enum type_code code = TYPE_CODE (type);
2898 int len = TYPE_LENGTH (type);
2900 gdb_assert (code == TYPE_CODE_STRUCT
2901 || code == TYPE_CODE_UNION
2902 || code == TYPE_CODE_ARRAY);
2904 if (struct_convention == pcc_struct_convention
2905 || (struct_convention == default_struct_convention
2906 && tdep->struct_return == pcc_struct_return))
2909 /* Structures consisting of a single `float', `double' or 'long
2910 double' member are returned in %st(0). */
2911 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2913 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2914 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2915 return (len == 4 || len == 8 || len == 12);
2918 return (len == 1 || len == 2 || len == 4 || len == 8);
2921 /* Determine, for architecture GDBARCH, how a return value of TYPE
2922 should be returned. If it is supposed to be returned in registers,
2923 and READBUF is non-zero, read the appropriate value from REGCACHE,
2924 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2925 from WRITEBUF into REGCACHE. */
2927 static enum return_value_convention
2928 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2929 struct type *type, struct regcache *regcache,
2930 gdb_byte *readbuf, const gdb_byte *writebuf)
2932 enum type_code code = TYPE_CODE (type);
2934 if (((code == TYPE_CODE_STRUCT
2935 || code == TYPE_CODE_UNION
2936 || code == TYPE_CODE_ARRAY)
2937 && !i386_reg_struct_return_p (gdbarch, type))
2938 /* Complex double and long double uses the struct return covention. */
2939 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2940 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2941 /* 128-bit decimal float uses the struct return convention. */
2942 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2944 /* The System V ABI says that:
2946 "A function that returns a structure or union also sets %eax
2947 to the value of the original address of the caller's area
2948 before it returns. Thus when the caller receives control
2949 again, the address of the returned object resides in register
2950 %eax and can be used to access the object."
2952 So the ABI guarantees that we can always find the return
2953 value just after the function has returned. */
2955 /* Note that the ABI doesn't mention functions returning arrays,
2956 which is something possible in certain languages such as Ada.
2957 In this case, the value is returned as if it was wrapped in
2958 a record, so the convention applied to records also applies
2965 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2966 read_memory (addr, readbuf, TYPE_LENGTH (type));
2969 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2972 /* This special case is for structures consisting of a single
2973 `float', `double' or 'long double' member. These structures are
2974 returned in %st(0). For these structures, we call ourselves
2975 recursively, changing TYPE into the type of the first member of
2976 the structure. Since that should work for all structures that
2977 have only one member, we don't bother to check the member's type
2979 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2981 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2982 return i386_return_value (gdbarch, function, type, regcache,
2987 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2989 i386_store_return_value (gdbarch, type, regcache, writebuf);
2991 return RETURN_VALUE_REGISTER_CONVENTION;
2996 i387_ext_type (struct gdbarch *gdbarch)
2998 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3000 if (!tdep->i387_ext_type)
3002 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3003 gdb_assert (tdep->i387_ext_type != NULL);
3006 return tdep->i387_ext_type;
3009 /* Construct type for pseudo BND registers. We can't use
3010 tdesc_find_type since a complement of one value has to be used
3011 to describe the upper bound. */
3013 static struct type *
3014 i386_bnd_type (struct gdbarch *gdbarch)
3016 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3019 if (!tdep->i386_bnd_type)
3021 struct type *t, *bound_t;
3022 const struct builtin_type *bt = builtin_type (gdbarch);
3024 /* The type we're building is described bellow: */
3029 void *ubound; /* One complement of raw ubound field. */
3033 t = arch_composite_type (gdbarch,
3034 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3036 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3037 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3039 TYPE_NAME (t) = "builtin_type_bound128";
3040 tdep->i386_bnd_type = t;
3043 return tdep->i386_bnd_type;
3046 /* Construct vector type for pseudo ZMM registers. We can't use
3047 tdesc_find_type since ZMM isn't described in target description. */
3049 static struct type *
3050 i386_zmm_type (struct gdbarch *gdbarch)
3052 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3054 if (!tdep->i386_zmm_type)
3056 const struct builtin_type *bt = builtin_type (gdbarch);
3058 /* The type we're building is this: */
3060 union __gdb_builtin_type_vec512i
3062 int128_t uint128[4];
3063 int64_t v4_int64[8];
3064 int32_t v8_int32[16];
3065 int16_t v16_int16[32];
3066 int8_t v32_int8[64];
3067 double v4_double[8];
3074 t = arch_composite_type (gdbarch,
3075 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3076 append_composite_type_field (t, "v16_float",
3077 init_vector_type (bt->builtin_float, 16));
3078 append_composite_type_field (t, "v8_double",
3079 init_vector_type (bt->builtin_double, 8));
3080 append_composite_type_field (t, "v64_int8",
3081 init_vector_type (bt->builtin_int8, 64));
3082 append_composite_type_field (t, "v32_int16",
3083 init_vector_type (bt->builtin_int16, 32));
3084 append_composite_type_field (t, "v16_int32",
3085 init_vector_type (bt->builtin_int32, 16));
3086 append_composite_type_field (t, "v8_int64",
3087 init_vector_type (bt->builtin_int64, 8));
3088 append_composite_type_field (t, "v4_int128",
3089 init_vector_type (bt->builtin_int128, 4));
3091 TYPE_VECTOR (t) = 1;
3092 TYPE_NAME (t) = "builtin_type_vec512i";
3093 tdep->i386_zmm_type = t;
3096 return tdep->i386_zmm_type;
3099 /* Construct vector type for pseudo YMM registers. We can't use
3100 tdesc_find_type since YMM isn't described in target description. */
3102 static struct type *
3103 i386_ymm_type (struct gdbarch *gdbarch)
3105 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3107 if (!tdep->i386_ymm_type)
3109 const struct builtin_type *bt = builtin_type (gdbarch);
3111 /* The type we're building is this: */
3113 union __gdb_builtin_type_vec256i
3115 int128_t uint128[2];
3116 int64_t v2_int64[4];
3117 int32_t v4_int32[8];
3118 int16_t v8_int16[16];
3119 int8_t v16_int8[32];
3120 double v2_double[4];
3127 t = arch_composite_type (gdbarch,
3128 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3129 append_composite_type_field (t, "v8_float",
3130 init_vector_type (bt->builtin_float, 8));
3131 append_composite_type_field (t, "v4_double",
3132 init_vector_type (bt->builtin_double, 4));
3133 append_composite_type_field (t, "v32_int8",
3134 init_vector_type (bt->builtin_int8, 32));
3135 append_composite_type_field (t, "v16_int16",
3136 init_vector_type (bt->builtin_int16, 16));
3137 append_composite_type_field (t, "v8_int32",
3138 init_vector_type (bt->builtin_int32, 8));
3139 append_composite_type_field (t, "v4_int64",
3140 init_vector_type (bt->builtin_int64, 4));
3141 append_composite_type_field (t, "v2_int128",
3142 init_vector_type (bt->builtin_int128, 2));
3144 TYPE_VECTOR (t) = 1;
3145 TYPE_NAME (t) = "builtin_type_vec256i";
3146 tdep->i386_ymm_type = t;
3149 return tdep->i386_ymm_type;
3152 /* Construct vector type for MMX registers. */
3153 static struct type *
3154 i386_mmx_type (struct gdbarch *gdbarch)
3156 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3158 if (!tdep->i386_mmx_type)
3160 const struct builtin_type *bt = builtin_type (gdbarch);
3162 /* The type we're building is this: */
3164 union __gdb_builtin_type_vec64i
3167 int32_t v2_int32[2];
3168 int16_t v4_int16[4];
3175 t = arch_composite_type (gdbarch,
3176 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3178 append_composite_type_field (t, "uint64", bt->builtin_int64);
3179 append_composite_type_field (t, "v2_int32",
3180 init_vector_type (bt->builtin_int32, 2));
3181 append_composite_type_field (t, "v4_int16",
3182 init_vector_type (bt->builtin_int16, 4));
3183 append_composite_type_field (t, "v8_int8",
3184 init_vector_type (bt->builtin_int8, 8));
3186 TYPE_VECTOR (t) = 1;
3187 TYPE_NAME (t) = "builtin_type_vec64i";
3188 tdep->i386_mmx_type = t;
3191 return tdep->i386_mmx_type;
3194 /* Return the GDB type object for the "standard" data type of data in
3198 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3200 if (i386_bnd_regnum_p (gdbarch, regnum))
3201 return i386_bnd_type (gdbarch);
3202 if (i386_mmx_regnum_p (gdbarch, regnum))
3203 return i386_mmx_type (gdbarch);
3204 else if (i386_ymm_regnum_p (gdbarch, regnum))
3205 return i386_ymm_type (gdbarch);
3206 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3207 return i386_ymm_type (gdbarch);
3208 else if (i386_zmm_regnum_p (gdbarch, regnum))
3209 return i386_zmm_type (gdbarch);
3212 const struct builtin_type *bt = builtin_type (gdbarch);
3213 if (i386_byte_regnum_p (gdbarch, regnum))
3214 return bt->builtin_int8;
3215 else if (i386_word_regnum_p (gdbarch, regnum))
3216 return bt->builtin_int16;
3217 else if (i386_dword_regnum_p (gdbarch, regnum))
3218 return bt->builtin_int32;
3219 else if (i386_k_regnum_p (gdbarch, regnum))
3220 return bt->builtin_int64;
3223 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3226 /* Map a cooked register onto a raw register or memory. For the i386,
3227 the MMX registers need to be mapped onto floating point registers. */
3230 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3232 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3237 mmxreg = regnum - tdep->mm0_regnum;
3238 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3239 tos = (fstat >> 11) & 0x7;
3240 fpreg = (mmxreg + tos) % 8;
3242 return (I387_ST0_REGNUM (tdep) + fpreg);
3245 /* A helper function for us by i386_pseudo_register_read_value and
3246 amd64_pseudo_register_read_value. It does all the work but reads
3247 the data into an already-allocated value. */
3250 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3251 struct regcache *regcache,
3253 struct value *result_value)
3255 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3256 enum register_status status;
3257 gdb_byte *buf = value_contents_raw (result_value);
3259 if (i386_mmx_regnum_p (gdbarch, regnum))
3261 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3263 /* Extract (always little endian). */
3264 status = regcache_raw_read (regcache, fpnum, raw_buf);
3265 if (status != REG_VALID)
3266 mark_value_bytes_unavailable (result_value, 0,
3267 TYPE_LENGTH (value_type (result_value)));
3269 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3274 if (i386_bnd_regnum_p (gdbarch, regnum))
3276 regnum -= tdep->bnd0_regnum;
3278 /* Extract (always little endian). Read lower 128bits. */
3279 status = regcache_raw_read (regcache,
3280 I387_BND0R_REGNUM (tdep) + regnum,
3282 if (status != REG_VALID)
3283 mark_value_bytes_unavailable (result_value, 0, 16);
3286 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3287 LONGEST upper, lower;
3288 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3290 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3291 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3294 memcpy (buf, &lower, size);
3295 memcpy (buf + size, &upper, size);
3298 else if (i386_k_regnum_p (gdbarch, regnum))
3300 regnum -= tdep->k0_regnum;
3302 /* Extract (always little endian). */
3303 status = regcache_raw_read (regcache,
3304 tdep->k0_regnum + regnum,
3306 if (status != REG_VALID)
3307 mark_value_bytes_unavailable (result_value, 0, 8);
3309 memcpy (buf, raw_buf, 8);
3311 else if (i386_zmm_regnum_p (gdbarch, regnum))
3313 regnum -= tdep->zmm0_regnum;
3315 if (regnum < num_lower_zmm_regs)
3317 /* Extract (always little endian). Read lower 128bits. */
3318 status = regcache_raw_read (regcache,
3319 I387_XMM0_REGNUM (tdep) + regnum,
3321 if (status != REG_VALID)
3322 mark_value_bytes_unavailable (result_value, 0, 16);
3324 memcpy (buf, raw_buf, 16);
3326 /* Extract (always little endian). Read upper 128bits. */
3327 status = regcache_raw_read (regcache,
3328 tdep->ymm0h_regnum + regnum,
3330 if (status != REG_VALID)
3331 mark_value_bytes_unavailable (result_value, 16, 16);
3333 memcpy (buf + 16, raw_buf, 16);
3337 /* Extract (always little endian). Read lower 128bits. */
3338 status = regcache_raw_read (regcache,
3339 I387_XMM16_REGNUM (tdep) + regnum
3340 - num_lower_zmm_regs,
3342 if (status != REG_VALID)
3343 mark_value_bytes_unavailable (result_value, 0, 16);
3345 memcpy (buf, raw_buf, 16);
3347 /* Extract (always little endian). Read upper 128bits. */
3348 status = regcache_raw_read (regcache,
3349 I387_YMM16H_REGNUM (tdep) + regnum
3350 - num_lower_zmm_regs,
3352 if (status != REG_VALID)
3353 mark_value_bytes_unavailable (result_value, 16, 16);
3355 memcpy (buf + 16, raw_buf, 16);
3358 /* Read upper 256bits. */
3359 status = regcache_raw_read (regcache,
3360 tdep->zmm0h_regnum + regnum,
3362 if (status != REG_VALID)
3363 mark_value_bytes_unavailable (result_value, 32, 32);
3365 memcpy (buf + 32, raw_buf, 32);
3367 else if (i386_ymm_regnum_p (gdbarch, regnum))
3369 regnum -= tdep->ymm0_regnum;
3371 /* Extract (always little endian). Read lower 128bits. */
3372 status = regcache_raw_read (regcache,
3373 I387_XMM0_REGNUM (tdep) + regnum,
3375 if (status != REG_VALID)
3376 mark_value_bytes_unavailable (result_value, 0, 16);
3378 memcpy (buf, raw_buf, 16);
3379 /* Read upper 128bits. */
3380 status = regcache_raw_read (regcache,
3381 tdep->ymm0h_regnum + regnum,
3383 if (status != REG_VALID)
3384 mark_value_bytes_unavailable (result_value, 16, 32);
3386 memcpy (buf + 16, raw_buf, 16);
3388 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3390 regnum -= tdep->ymm16_regnum;
3391 /* Extract (always little endian). Read lower 128bits. */
3392 status = regcache_raw_read (regcache,
3393 I387_XMM16_REGNUM (tdep) + regnum,
3395 if (status != REG_VALID)
3396 mark_value_bytes_unavailable (result_value, 0, 16);
3398 memcpy (buf, raw_buf, 16);
3399 /* Read upper 128bits. */
3400 status = regcache_raw_read (regcache,
3401 tdep->ymm16h_regnum + regnum,
3403 if (status != REG_VALID)
3404 mark_value_bytes_unavailable (result_value, 16, 16);
3406 memcpy (buf + 16, raw_buf, 16);
3408 else if (i386_word_regnum_p (gdbarch, regnum))
3410 int gpnum = regnum - tdep->ax_regnum;
3412 /* Extract (always little endian). */
3413 status = regcache_raw_read (regcache, gpnum, raw_buf);
3414 if (status != REG_VALID)
3415 mark_value_bytes_unavailable (result_value, 0,
3416 TYPE_LENGTH (value_type (result_value)));
3418 memcpy (buf, raw_buf, 2);
3420 else if (i386_byte_regnum_p (gdbarch, regnum))
3422 /* Check byte pseudo registers last since this function will
3423 be called from amd64_pseudo_register_read, which handles
3424 byte pseudo registers differently. */
3425 int gpnum = regnum - tdep->al_regnum;
3427 /* Extract (always little endian). We read both lower and
3429 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3430 if (status != REG_VALID)
3431 mark_value_bytes_unavailable (result_value, 0,
3432 TYPE_LENGTH (value_type (result_value)));
3433 else if (gpnum >= 4)
3434 memcpy (buf, raw_buf + 1, 1);
3436 memcpy (buf, raw_buf, 1);
3439 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3443 static struct value *
3444 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3445 struct regcache *regcache,
3448 struct value *result;
3450 result = allocate_value (register_type (gdbarch, regnum));
3451 VALUE_LVAL (result) = lval_register;
3452 VALUE_REGNUM (result) = regnum;
3454 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3460 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3461 int regnum, const gdb_byte *buf)
3463 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3465 if (i386_mmx_regnum_p (gdbarch, regnum))
3467 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3470 regcache_raw_read (regcache, fpnum, raw_buf);
3471 /* ... Modify ... (always little endian). */
3472 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3474 regcache_raw_write (regcache, fpnum, raw_buf);
3478 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3480 if (i386_bnd_regnum_p (gdbarch, regnum))
3482 ULONGEST upper, lower;
3483 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3484 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3486 /* New values from input value. */
3487 regnum -= tdep->bnd0_regnum;
3488 lower = extract_unsigned_integer (buf, size, byte_order);
3489 upper = extract_unsigned_integer (buf + size, size, byte_order);
3491 /* Fetching register buffer. */
3492 regcache_raw_read (regcache,
3493 I387_BND0R_REGNUM (tdep) + regnum,
3498 /* Set register bits. */
3499 memcpy (raw_buf, &lower, 8);
3500 memcpy (raw_buf + 8, &upper, 8);
3503 regcache_raw_write (regcache,
3504 I387_BND0R_REGNUM (tdep) + regnum,
3507 else if (i386_k_regnum_p (gdbarch, regnum))
3509 regnum -= tdep->k0_regnum;
3511 regcache_raw_write (regcache,
3512 tdep->k0_regnum + regnum,
3515 else if (i386_zmm_regnum_p (gdbarch, regnum))
3517 regnum -= tdep->zmm0_regnum;
3519 if (regnum < num_lower_zmm_regs)
3521 /* Write lower 128bits. */
3522 regcache_raw_write (regcache,
3523 I387_XMM0_REGNUM (tdep) + regnum,
3525 /* Write upper 128bits. */
3526 regcache_raw_write (regcache,
3527 I387_YMM0_REGNUM (tdep) + regnum,
3532 /* Write lower 128bits. */
3533 regcache_raw_write (regcache,
3534 I387_XMM16_REGNUM (tdep) + regnum
3535 - num_lower_zmm_regs,
3537 /* Write upper 128bits. */
3538 regcache_raw_write (regcache,
3539 I387_YMM16H_REGNUM (tdep) + regnum
3540 - num_lower_zmm_regs,
3543 /* Write upper 256bits. */
3544 regcache_raw_write (regcache,
3545 tdep->zmm0h_regnum + regnum,
3548 else if (i386_ymm_regnum_p (gdbarch, regnum))
3550 regnum -= tdep->ymm0_regnum;
3552 /* ... Write lower 128bits. */
3553 regcache_raw_write (regcache,
3554 I387_XMM0_REGNUM (tdep) + regnum,
3556 /* ... Write upper 128bits. */
3557 regcache_raw_write (regcache,
3558 tdep->ymm0h_regnum + regnum,
3561 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3563 regnum -= tdep->ymm16_regnum;
3565 /* ... Write lower 128bits. */
3566 regcache_raw_write (regcache,
3567 I387_XMM16_REGNUM (tdep) + regnum,
3569 /* ... Write upper 128bits. */
3570 regcache_raw_write (regcache,
3571 tdep->ymm16h_regnum + regnum,
3574 else if (i386_word_regnum_p (gdbarch, regnum))
3576 int gpnum = regnum - tdep->ax_regnum;
3579 regcache_raw_read (regcache, gpnum, raw_buf);
3580 /* ... Modify ... (always little endian). */
3581 memcpy (raw_buf, buf, 2);
3583 regcache_raw_write (regcache, gpnum, raw_buf);
3585 else if (i386_byte_regnum_p (gdbarch, regnum))
3587 /* Check byte pseudo registers last since this function will
3588 be called from amd64_pseudo_register_read, which handles
3589 byte pseudo registers differently. */
3590 int gpnum = regnum - tdep->al_regnum;
3592 /* Read ... We read both lower and upper registers. */
3593 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3594 /* ... Modify ... (always little endian). */
3596 memcpy (raw_buf + 1, buf, 1);
3598 memcpy (raw_buf, buf, 1);
3600 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3603 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3608 /* Return the register number of the register allocated by GCC after
3609 REGNUM, or -1 if there is no such register. */
3612 i386_next_regnum (int regnum)
3614 /* GCC allocates the registers in the order:
3616 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3618 Since storing a variable in %esp doesn't make any sense we return
3619 -1 for %ebp and for %esp itself. */
3620 static int next_regnum[] =
3622 I386_EDX_REGNUM, /* Slot for %eax. */
3623 I386_EBX_REGNUM, /* Slot for %ecx. */
3624 I386_ECX_REGNUM, /* Slot for %edx. */
3625 I386_ESI_REGNUM, /* Slot for %ebx. */
3626 -1, -1, /* Slots for %esp and %ebp. */
3627 I386_EDI_REGNUM, /* Slot for %esi. */
3628 I386_EBP_REGNUM /* Slot for %edi. */
3631 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3632 return next_regnum[regnum];
3637 /* Return nonzero if a value of type TYPE stored in register REGNUM
3638 needs any special handling. */
3641 i386_convert_register_p (struct gdbarch *gdbarch,
3642 int regnum, struct type *type)
3644 int len = TYPE_LENGTH (type);
3646 /* Values may be spread across multiple registers. Most debugging
3647 formats aren't expressive enough to specify the locations, so
3648 some heuristics is involved. Right now we only handle types that
3649 have a length that is a multiple of the word size, since GCC
3650 doesn't seem to put any other types into registers. */
3651 if (len > 4 && len % 4 == 0)
3653 int last_regnum = regnum;
3657 last_regnum = i386_next_regnum (last_regnum);
3661 if (last_regnum != -1)
3665 return i387_convert_register_p (gdbarch, regnum, type);
3668 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3669 return its contents in TO. */
3672 i386_register_to_value (struct frame_info *frame, int regnum,
3673 struct type *type, gdb_byte *to,
3674 int *optimizedp, int *unavailablep)
3676 struct gdbarch *gdbarch = get_frame_arch (frame);
3677 int len = TYPE_LENGTH (type);
3679 if (i386_fp_regnum_p (gdbarch, regnum))
3680 return i387_register_to_value (frame, regnum, type, to,
3681 optimizedp, unavailablep);
3683 /* Read a value spread across multiple registers. */
3685 gdb_assert (len > 4 && len % 4 == 0);
3689 gdb_assert (regnum != -1);
3690 gdb_assert (register_size (gdbarch, regnum) == 4);
3692 if (!get_frame_register_bytes (frame, regnum, 0,
3693 register_size (gdbarch, regnum),
3694 to, optimizedp, unavailablep))
3697 regnum = i386_next_regnum (regnum);
3702 *optimizedp = *unavailablep = 0;
3706 /* Write the contents FROM of a value of type TYPE into register
3707 REGNUM in frame FRAME. */
3710 i386_value_to_register (struct frame_info *frame, int regnum,
3711 struct type *type, const gdb_byte *from)
3713 int len = TYPE_LENGTH (type);
3715 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3717 i387_value_to_register (frame, regnum, type, from);
3721 /* Write a value spread across multiple registers. */
3723 gdb_assert (len > 4 && len % 4 == 0);
3727 gdb_assert (regnum != -1);
3728 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3730 put_frame_register (frame, regnum, from);
3731 regnum = i386_next_regnum (regnum);
3737 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3738 in the general-purpose register set REGSET to register cache
3739 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3742 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3743 int regnum, const void *gregs, size_t len)
3745 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3746 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3747 const gdb_byte *regs = (const gdb_byte *) gregs;
3750 gdb_assert (len >= tdep->sizeof_gregset);
3752 for (i = 0; i < tdep->gregset_num_regs; i++)
3754 if ((regnum == i || regnum == -1)
3755 && tdep->gregset_reg_offset[i] != -1)
3756 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3760 /* Collect register REGNUM from the register cache REGCACHE and store
3761 it in the buffer specified by GREGS and LEN as described by the
3762 general-purpose register set REGSET. If REGNUM is -1, do this for
3763 all registers in REGSET. */
3766 i386_collect_gregset (const struct regset *regset,
3767 const struct regcache *regcache,
3768 int regnum, void *gregs, size_t len)
3770 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3771 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3772 gdb_byte *regs = (gdb_byte *) gregs;
3775 gdb_assert (len >= tdep->sizeof_gregset);
3777 for (i = 0; i < tdep->gregset_num_regs; i++)
3779 if ((regnum == i || regnum == -1)
3780 && tdep->gregset_reg_offset[i] != -1)
3781 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3785 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3786 in the floating-point register set REGSET to register cache
3787 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3790 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3791 int regnum, const void *fpregs, size_t len)
3793 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3794 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3796 if (len == I387_SIZEOF_FXSAVE)
3798 i387_supply_fxsave (regcache, regnum, fpregs);
3802 gdb_assert (len >= tdep->sizeof_fpregset);
3803 i387_supply_fsave (regcache, regnum, fpregs);
3806 /* Collect register REGNUM from the register cache REGCACHE and store
3807 it in the buffer specified by FPREGS and LEN as described by the
3808 floating-point register set REGSET. If REGNUM is -1, do this for
3809 all registers in REGSET. */
3812 i386_collect_fpregset (const struct regset *regset,
3813 const struct regcache *regcache,
3814 int regnum, void *fpregs, size_t len)
3816 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3817 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3819 if (len == I387_SIZEOF_FXSAVE)
3821 i387_collect_fxsave (regcache, regnum, fpregs);
3825 gdb_assert (len >= tdep->sizeof_fpregset);
3826 i387_collect_fsave (regcache, regnum, fpregs);
3829 /* Register set definitions. */
3831 const struct regset i386_gregset =
3833 NULL, i386_supply_gregset, i386_collect_gregset
3836 const struct regset i386_fpregset =
3838 NULL, i386_supply_fpregset, i386_collect_fpregset
3841 /* Default iterator over core file register note sections. */
3844 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3845 iterate_over_regset_sections_cb *cb,
3847 const struct regcache *regcache)
3849 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3851 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3852 if (tdep->sizeof_fpregset)
3853 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3857 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3860 i386_pe_skip_trampoline_code (struct frame_info *frame,
3861 CORE_ADDR pc, char *name)
3863 struct gdbarch *gdbarch = get_frame_arch (frame);
3864 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3867 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3869 unsigned long indirect =
3870 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3871 struct minimal_symbol *indsym =
3872 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3873 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3877 if (startswith (symname, "__imp_")
3878 || startswith (symname, "_imp_"))
3880 read_memory_unsigned_integer (indirect, 4, byte_order);
3883 return 0; /* Not a trampoline. */
3887 /* Return whether the THIS_FRAME corresponds to a sigtramp
3891 i386_sigtramp_p (struct frame_info *this_frame)
3893 CORE_ADDR pc = get_frame_pc (this_frame);
3896 find_pc_partial_function (pc, &name, NULL, NULL);
3897 return (name && strcmp ("_sigtramp", name) == 0);
3901 /* We have two flavours of disassembly. The machinery on this page
3902 deals with switching between those. */
3905 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3907 gdb_assert (disassembly_flavor == att_flavor
3908 || disassembly_flavor == intel_flavor);
3910 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3911 constified, cast to prevent a compiler warning. */
3912 info->disassembler_options = (char *) disassembly_flavor;
3914 return print_insn_i386 (pc, info);
3918 /* There are a few i386 architecture variants that differ only
3919 slightly from the generic i386 target. For now, we don't give them
3920 their own source file, but include them here. As a consequence,
3921 they'll always be included. */
3923 /* System V Release 4 (SVR4). */
3925 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3929 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3931 CORE_ADDR pc = get_frame_pc (this_frame);
3934 /* The origin of these symbols is currently unknown. */
3935 find_pc_partial_function (pc, &name, NULL, NULL);
3936 return (name && (strcmp ("_sigreturn", name) == 0
3937 || strcmp ("sigvechandler", name) == 0));
3940 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3941 address of the associated sigcontext (ucontext) structure. */
3944 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3946 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3947 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3951 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3952 sp = extract_unsigned_integer (buf, 4, byte_order);
3954 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3959 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3963 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3965 return (*s == '$' /* Literal number. */
3966 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3967 || (*s == '(' && s[1] == '%') /* Register indirection. */
3968 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3971 /* Helper function for i386_stap_parse_special_token.
3973 This function parses operands of the form `-8+3+1(%rbp)', which
3974 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3976 Return 1 if the operand was parsed successfully, zero
3980 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
3981 struct stap_parse_info *p)
3983 const char *s = p->arg;
3985 if (isdigit (*s) || *s == '-' || *s == '+')
3989 long displacements[3];
4005 if (!isdigit ((unsigned char) *s))
4008 displacements[0] = strtol (s, &endp, 10);
4011 if (*s != '+' && *s != '-')
4013 /* We are not dealing with a triplet. */
4026 if (!isdigit ((unsigned char) *s))
4029 displacements[1] = strtol (s, &endp, 10);
4032 if (*s != '+' && *s != '-')
4034 /* We are not dealing with a triplet. */
4047 if (!isdigit ((unsigned char) *s))
4050 displacements[2] = strtol (s, &endp, 10);
4053 if (*s != '(' || s[1] != '%')
4059 while (isalnum (*s))
4065 len = s - start - 1;
4066 regname = (char *) alloca (len + 1);
4068 strncpy (regname, start, len);
4069 regname[len] = '\0';
4071 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4072 error (_("Invalid register name `%s' on expression `%s'."),
4073 regname, p->saved_arg);
4075 for (i = 0; i < 3; i++)
4077 write_exp_elt_opcode (&p->pstate, OP_LONG);
4079 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4080 write_exp_elt_longcst (&p->pstate, displacements[i]);
4081 write_exp_elt_opcode (&p->pstate, OP_LONG);
4083 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4086 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4089 write_exp_string (&p->pstate, str);
4090 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4092 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4093 write_exp_elt_type (&p->pstate,
4094 builtin_type (gdbarch)->builtin_data_ptr);
4095 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4097 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4098 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4099 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4101 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4102 write_exp_elt_type (&p->pstate,
4103 lookup_pointer_type (p->arg_type));
4104 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4106 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4116 /* Helper function for i386_stap_parse_special_token.
4118 This function parses operands of the form `register base +
4119 (register index * size) + offset', as represented in
4120 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4122 Return 1 if the operand was parsed successfully, zero
4126 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4127 struct stap_parse_info *p)
4129 const char *s = p->arg;
4131 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4133 int offset_minus = 0;
4142 struct stoken base_token, index_token;
4152 if (offset_minus && !isdigit (*s))
4159 offset = strtol (s, &endp, 10);
4163 if (*s != '(' || s[1] != '%')
4169 while (isalnum (*s))
4172 if (*s != ',' || s[1] != '%')
4175 len_base = s - start;
4176 base = (char *) alloca (len_base + 1);
4177 strncpy (base, start, len_base);
4178 base[len_base] = '\0';
4180 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4181 error (_("Invalid register name `%s' on expression `%s'."),
4182 base, p->saved_arg);
4187 while (isalnum (*s))
4190 len_index = s - start;
4191 index = (char *) alloca (len_index + 1);
4192 strncpy (index, start, len_index);
4193 index[len_index] = '\0';
4195 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4196 error (_("Invalid register name `%s' on expression `%s'."),
4197 index, p->saved_arg);
4199 if (*s != ',' && *s != ')')
4215 size = strtol (s, &endp, 10);
4226 write_exp_elt_opcode (&p->pstate, OP_LONG);
4227 write_exp_elt_type (&p->pstate,
4228 builtin_type (gdbarch)->builtin_long);
4229 write_exp_elt_longcst (&p->pstate, offset);
4230 write_exp_elt_opcode (&p->pstate, OP_LONG);
4232 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4235 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4236 base_token.ptr = base;
4237 base_token.length = len_base;
4238 write_exp_string (&p->pstate, base_token);
4239 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4242 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4244 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4245 index_token.ptr = index;
4246 index_token.length = len_index;
4247 write_exp_string (&p->pstate, index_token);
4248 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4252 write_exp_elt_opcode (&p->pstate, OP_LONG);
4253 write_exp_elt_type (&p->pstate,
4254 builtin_type (gdbarch)->builtin_long);
4255 write_exp_elt_longcst (&p->pstate, size);
4256 write_exp_elt_opcode (&p->pstate, OP_LONG);
4258 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4259 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4262 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4264 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4265 write_exp_elt_type (&p->pstate,
4266 lookup_pointer_type (p->arg_type));
4267 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4269 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4279 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4283 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4284 struct stap_parse_info *p)
4286 /* In order to parse special tokens, we use a state-machine that go
4287 through every known token and try to get a match. */
4291 THREE_ARG_DISPLACEMENT,
4296 current_state = TRIPLET;
4298 /* The special tokens to be parsed here are:
4300 - `register base + (register index * size) + offset', as represented
4301 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4303 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4304 `*(-8 + 3 - 1 + (void *) $eax)'. */
4306 while (current_state != DONE)
4308 switch (current_state)
4311 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4315 case THREE_ARG_DISPLACEMENT:
4316 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4321 /* Advancing to the next state. */
4330 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4331 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4334 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4336 return "(x86_64|i.86)";
4344 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4346 static const char *const stap_integer_prefixes[] = { "$", NULL };
4347 static const char *const stap_register_prefixes[] = { "%", NULL };
4348 static const char *const stap_register_indirection_prefixes[] = { "(",
4350 static const char *const stap_register_indirection_suffixes[] = { ")",
4353 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4354 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4356 /* Registering SystemTap handlers. */
4357 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4358 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4359 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4360 stap_register_indirection_prefixes);
4361 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4362 stap_register_indirection_suffixes);
4363 set_gdbarch_stap_is_single_operand (gdbarch,
4364 i386_stap_is_single_operand);
4365 set_gdbarch_stap_parse_special_token (gdbarch,
4366 i386_stap_parse_special_token);
4368 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4371 /* System V Release 4 (SVR4). */
4374 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4376 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4378 /* System V Release 4 uses ELF. */
4379 i386_elf_init_abi (info, gdbarch);
4381 /* System V Release 4 has shared libraries. */
4382 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4384 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4385 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4386 tdep->sc_pc_offset = 36 + 14 * 4;
4387 tdep->sc_sp_offset = 36 + 17 * 4;
4389 tdep->jb_pc_offset = 20;
4395 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4397 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4399 /* DJGPP doesn't have any special frames for signal handlers. */
4400 tdep->sigtramp_p = NULL;
4402 tdep->jb_pc_offset = 36;
4404 /* DJGPP does not support the SSE registers. */
4405 if (! tdesc_has_registers (info.target_desc))
4406 tdep->tdesc = tdesc_i386_mmx;
4408 /* Native compiler is GCC, which uses the SVR4 register numbering
4409 even in COFF and STABS. See the comment in i386_gdbarch_init,
4410 before the calls to set_gdbarch_stab_reg_to_regnum and
4411 set_gdbarch_sdb_reg_to_regnum. */
4412 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4413 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4415 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4417 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4421 /* i386 register groups. In addition to the normal groups, add "mmx"
4424 static struct reggroup *i386_sse_reggroup;
4425 static struct reggroup *i386_mmx_reggroup;
4428 i386_init_reggroups (void)
4430 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4431 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4435 i386_add_reggroups (struct gdbarch *gdbarch)
4437 reggroup_add (gdbarch, i386_sse_reggroup);
4438 reggroup_add (gdbarch, i386_mmx_reggroup);
4439 reggroup_add (gdbarch, general_reggroup);
4440 reggroup_add (gdbarch, float_reggroup);
4441 reggroup_add (gdbarch, all_reggroup);
4442 reggroup_add (gdbarch, save_reggroup);
4443 reggroup_add (gdbarch, restore_reggroup);
4444 reggroup_add (gdbarch, vector_reggroup);
4445 reggroup_add (gdbarch, system_reggroup);
4449 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4450 struct reggroup *group)
4452 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4453 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4454 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4455 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4456 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4457 avx512_p, avx_p, sse_p;
4459 /* Don't include pseudo registers, except for MMX, in any register
4461 if (i386_byte_regnum_p (gdbarch, regnum))
4464 if (i386_word_regnum_p (gdbarch, regnum))
4467 if (i386_dword_regnum_p (gdbarch, regnum))
4470 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4471 if (group == i386_mmx_reggroup)
4472 return mmx_regnum_p;
4474 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4475 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4476 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4477 if (group == i386_sse_reggroup)
4478 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4480 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4481 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4482 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4484 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4485 == X86_XSTATE_AVX512_MASK);
4486 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4487 == X86_XSTATE_AVX_MASK) && !avx512_p;
4488 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4489 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4491 if (group == vector_reggroup)
4492 return (mmx_regnum_p
4493 || (zmm_regnum_p && avx512_p)
4494 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4495 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4498 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4499 || i386_fpc_regnum_p (gdbarch, regnum));
4500 if (group == float_reggroup)
4503 /* For "info reg all", don't include upper YMM registers nor XMM
4504 registers when AVX is supported. */
4505 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4506 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4507 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4508 if (group == all_reggroup
4509 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4510 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4512 || ymmh_avx512_regnum_p
4516 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4517 if (group == all_reggroup
4518 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4519 return bnd_regnum_p;
4521 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4522 if (group == all_reggroup
4523 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4526 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4527 if (group == all_reggroup
4528 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4529 return mpx_ctrl_regnum_p;
4531 if (group == general_reggroup)
4532 return (!fp_regnum_p
4536 && !xmm_avx512_regnum_p
4539 && !ymm_avx512_regnum_p
4540 && !ymmh_avx512_regnum_p
4543 && !mpx_ctrl_regnum_p
4547 return default_register_reggroup_p (gdbarch, regnum, group);
4551 /* Get the ARGIth function argument for the current function. */
4554 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4557 struct gdbarch *gdbarch = get_frame_arch (frame);
4558 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4559 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4560 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4563 #define PREFIX_REPZ 0x01
4564 #define PREFIX_REPNZ 0x02
4565 #define PREFIX_LOCK 0x04
4566 #define PREFIX_DATA 0x08
4567 #define PREFIX_ADDR 0x10
4579 /* i386 arith/logic operations */
4592 struct i386_record_s
4594 struct gdbarch *gdbarch;
4595 struct regcache *regcache;
4596 CORE_ADDR orig_addr;
4602 uint8_t mod, reg, rm;
4611 /* Parse the "modrm" part of the memory address irp->addr points at.
4612 Returns -1 if something goes wrong, 0 otherwise. */
4615 i386_record_modrm (struct i386_record_s *irp)
4617 struct gdbarch *gdbarch = irp->gdbarch;
4619 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4623 irp->mod = (irp->modrm >> 6) & 3;
4624 irp->reg = (irp->modrm >> 3) & 7;
4625 irp->rm = irp->modrm & 7;
4630 /* Extract the memory address that the current instruction writes to,
4631 and return it in *ADDR. Return -1 if something goes wrong. */
4634 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4636 struct gdbarch *gdbarch = irp->gdbarch;
4637 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4642 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4649 uint8_t base = irp->rm;
4654 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4657 scale = (byte >> 6) & 3;
4658 index = ((byte >> 3) & 7) | irp->rex_x;
4666 if ((base & 7) == 5)
4669 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4672 *addr = extract_signed_integer (buf, 4, byte_order);
4673 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4674 *addr += irp->addr + irp->rip_offset;
4678 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4681 *addr = (int8_t) buf[0];
4684 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4686 *addr = extract_signed_integer (buf, 4, byte_order);
4694 if (base == 4 && irp->popl_esp_hack)
4695 *addr += irp->popl_esp_hack;
4696 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4699 if (irp->aflag == 2)
4704 *addr = (uint32_t) (offset64 + *addr);
4706 if (havesib && (index != 4 || scale != 0))
4708 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4710 if (irp->aflag == 2)
4711 *addr += offset64 << scale;
4713 *addr = (uint32_t) (*addr + (offset64 << scale));
4718 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4719 address from 32-bit to 64-bit. */
4720 *addr = (uint32_t) *addr;
4731 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4734 *addr = extract_signed_integer (buf, 2, byte_order);
4740 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4743 *addr = (int8_t) buf[0];
4746 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4749 *addr = extract_signed_integer (buf, 2, byte_order);
4756 regcache_raw_read_unsigned (irp->regcache,
4757 irp->regmap[X86_RECORD_REBX_REGNUM],
4759 *addr = (uint32_t) (*addr + offset64);
4760 regcache_raw_read_unsigned (irp->regcache,
4761 irp->regmap[X86_RECORD_RESI_REGNUM],
4763 *addr = (uint32_t) (*addr + offset64);
4766 regcache_raw_read_unsigned (irp->regcache,
4767 irp->regmap[X86_RECORD_REBX_REGNUM],
4769 *addr = (uint32_t) (*addr + offset64);
4770 regcache_raw_read_unsigned (irp->regcache,
4771 irp->regmap[X86_RECORD_REDI_REGNUM],
4773 *addr = (uint32_t) (*addr + offset64);
4776 regcache_raw_read_unsigned (irp->regcache,
4777 irp->regmap[X86_RECORD_REBP_REGNUM],
4779 *addr = (uint32_t) (*addr + offset64);
4780 regcache_raw_read_unsigned (irp->regcache,
4781 irp->regmap[X86_RECORD_RESI_REGNUM],
4783 *addr = (uint32_t) (*addr + offset64);
4786 regcache_raw_read_unsigned (irp->regcache,
4787 irp->regmap[X86_RECORD_REBP_REGNUM],
4789 *addr = (uint32_t) (*addr + offset64);
4790 regcache_raw_read_unsigned (irp->regcache,
4791 irp->regmap[X86_RECORD_REDI_REGNUM],
4793 *addr = (uint32_t) (*addr + offset64);
4796 regcache_raw_read_unsigned (irp->regcache,
4797 irp->regmap[X86_RECORD_RESI_REGNUM],
4799 *addr = (uint32_t) (*addr + offset64);
4802 regcache_raw_read_unsigned (irp->regcache,
4803 irp->regmap[X86_RECORD_REDI_REGNUM],
4805 *addr = (uint32_t) (*addr + offset64);
4808 regcache_raw_read_unsigned (irp->regcache,
4809 irp->regmap[X86_RECORD_REBP_REGNUM],
4811 *addr = (uint32_t) (*addr + offset64);
4814 regcache_raw_read_unsigned (irp->regcache,
4815 irp->regmap[X86_RECORD_REBX_REGNUM],
4817 *addr = (uint32_t) (*addr + offset64);
4827 /* Record the address and contents of the memory that will be changed
4828 by the current instruction. Return -1 if something goes wrong, 0
4832 i386_record_lea_modrm (struct i386_record_s *irp)
4834 struct gdbarch *gdbarch = irp->gdbarch;
4837 if (irp->override >= 0)
4839 if (record_full_memory_query)
4843 target_terminal_ours ();
4845 Process record ignores the memory change of instruction at address %s\n\
4846 because it can't get the value of the segment register.\n\
4847 Do you want to stop the program?"),
4848 paddress (gdbarch, irp->orig_addr));
4849 target_terminal_inferior ();
4857 if (i386_record_lea_modrm_addr (irp, &addr))
4860 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4866 /* Record the effects of a push operation. Return -1 if something
4867 goes wrong, 0 otherwise. */
4870 i386_record_push (struct i386_record_s *irp, int size)
4874 if (record_full_arch_list_add_reg (irp->regcache,
4875 irp->regmap[X86_RECORD_RESP_REGNUM]))
4877 regcache_raw_read_unsigned (irp->regcache,
4878 irp->regmap[X86_RECORD_RESP_REGNUM],
4880 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4887 /* Defines contents to record. */
4888 #define I386_SAVE_FPU_REGS 0xfffd
4889 #define I386_SAVE_FPU_ENV 0xfffe
4890 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4892 /* Record the values of the floating point registers which will be
4893 changed by the current instruction. Returns -1 if something is
4894 wrong, 0 otherwise. */
4896 static int i386_record_floats (struct gdbarch *gdbarch,
4897 struct i386_record_s *ir,
4900 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4903 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4904 happen. Currently we store st0-st7 registers, but we need not store all
4905 registers all the time, in future we use ftag register and record only
4906 those who are not marked as an empty. */
4908 if (I386_SAVE_FPU_REGS == iregnum)
4910 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4912 if (record_full_arch_list_add_reg (ir->regcache, i))
4916 else if (I386_SAVE_FPU_ENV == iregnum)
4918 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4920 if (record_full_arch_list_add_reg (ir->regcache, i))
4924 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4926 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4928 if (record_full_arch_list_add_reg (ir->regcache, i))
4932 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4933 (iregnum <= I387_FOP_REGNUM (tdep)))
4935 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4940 /* Parameter error. */
4943 if(I386_SAVE_FPU_ENV != iregnum)
4945 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4947 if (record_full_arch_list_add_reg (ir->regcache, i))
4954 /* Parse the current instruction, and record the values of the
4955 registers and memory that will be changed by the current
4956 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4958 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4959 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4962 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4963 CORE_ADDR input_addr)
4965 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4971 gdb_byte buf[MAX_REGISTER_SIZE];
4972 struct i386_record_s ir;
4973 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4977 memset (&ir, 0, sizeof (struct i386_record_s));
4978 ir.regcache = regcache;
4979 ir.addr = input_addr;
4980 ir.orig_addr = input_addr;
4984 ir.popl_esp_hack = 0;
4985 ir.regmap = tdep->record_regmap;
4986 ir.gdbarch = gdbarch;
4988 if (record_debug > 1)
4989 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4991 paddress (gdbarch, ir.addr));
4996 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4999 switch (opcode8) /* Instruction prefixes */
5001 case REPE_PREFIX_OPCODE:
5002 prefixes |= PREFIX_REPZ;
5004 case REPNE_PREFIX_OPCODE:
5005 prefixes |= PREFIX_REPNZ;
5007 case LOCK_PREFIX_OPCODE:
5008 prefixes |= PREFIX_LOCK;
5010 case CS_PREFIX_OPCODE:
5011 ir.override = X86_RECORD_CS_REGNUM;
5013 case SS_PREFIX_OPCODE:
5014 ir.override = X86_RECORD_SS_REGNUM;
5016 case DS_PREFIX_OPCODE:
5017 ir.override = X86_RECORD_DS_REGNUM;
5019 case ES_PREFIX_OPCODE:
5020 ir.override = X86_RECORD_ES_REGNUM;
5022 case FS_PREFIX_OPCODE:
5023 ir.override = X86_RECORD_FS_REGNUM;
5025 case GS_PREFIX_OPCODE:
5026 ir.override = X86_RECORD_GS_REGNUM;
5028 case DATA_PREFIX_OPCODE:
5029 prefixes |= PREFIX_DATA;
5031 case ADDR_PREFIX_OPCODE:
5032 prefixes |= PREFIX_ADDR;
5034 case 0x40: /* i386 inc %eax */
5035 case 0x41: /* i386 inc %ecx */
5036 case 0x42: /* i386 inc %edx */
5037 case 0x43: /* i386 inc %ebx */
5038 case 0x44: /* i386 inc %esp */
5039 case 0x45: /* i386 inc %ebp */
5040 case 0x46: /* i386 inc %esi */
5041 case 0x47: /* i386 inc %edi */
5042 case 0x48: /* i386 dec %eax */
5043 case 0x49: /* i386 dec %ecx */
5044 case 0x4a: /* i386 dec %edx */
5045 case 0x4b: /* i386 dec %ebx */
5046 case 0x4c: /* i386 dec %esp */
5047 case 0x4d: /* i386 dec %ebp */
5048 case 0x4e: /* i386 dec %esi */
5049 case 0x4f: /* i386 dec %edi */
5050 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5053 rex_w = (opcode8 >> 3) & 1;
5054 rex_r = (opcode8 & 0x4) << 1;
5055 ir.rex_x = (opcode8 & 0x2) << 2;
5056 ir.rex_b = (opcode8 & 0x1) << 3;
5058 else /* 32 bit target */
5067 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5073 if (prefixes & PREFIX_DATA)
5076 if (prefixes & PREFIX_ADDR)
5078 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5081 /* Now check op code. */
5082 opcode = (uint32_t) opcode8;
5087 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5090 opcode = (uint32_t) opcode8 | 0x0f00;
5094 case 0x00: /* arith & logic */
5142 if (((opcode >> 3) & 7) != OP_CMPL)
5144 if ((opcode & 1) == 0)
5147 ir.ot = ir.dflag + OT_WORD;
5149 switch ((opcode >> 1) & 3)
5151 case 0: /* OP Ev, Gv */
5152 if (i386_record_modrm (&ir))
5156 if (i386_record_lea_modrm (&ir))
5162 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5164 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5167 case 1: /* OP Gv, Ev */
5168 if (i386_record_modrm (&ir))
5171 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5173 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5175 case 2: /* OP A, Iv */
5176 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5180 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5183 case 0x80: /* GRP1 */
5187 if (i386_record_modrm (&ir))
5190 if (ir.reg != OP_CMPL)
5192 if ((opcode & 1) == 0)
5195 ir.ot = ir.dflag + OT_WORD;
5202 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5203 if (i386_record_lea_modrm (&ir))
5207 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5209 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5212 case 0x40: /* inc */
5221 case 0x48: /* dec */
5230 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5231 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5234 case 0xf6: /* GRP3 */
5236 if ((opcode & 1) == 0)
5239 ir.ot = ir.dflag + OT_WORD;
5240 if (i386_record_modrm (&ir))
5243 if (ir.mod != 3 && ir.reg == 0)
5244 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5255 if (i386_record_lea_modrm (&ir))
5261 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5263 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5265 if (ir.reg == 3) /* neg */
5266 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5273 if (ir.ot != OT_BYTE)
5274 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5275 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5279 opcode = opcode << 8 | ir.modrm;
5285 case 0xfe: /* GRP4 */
5286 case 0xff: /* GRP5 */
5287 if (i386_record_modrm (&ir))
5289 if (ir.reg >= 2 && opcode == 0xfe)
5292 opcode = opcode << 8 | ir.modrm;
5299 if ((opcode & 1) == 0)
5302 ir.ot = ir.dflag + OT_WORD;
5305 if (i386_record_lea_modrm (&ir))
5311 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5313 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5315 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5318 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5320 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5322 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5325 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5326 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5332 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5335 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5337 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5342 opcode = opcode << 8 | ir.modrm;
5348 case 0x84: /* test */
5352 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5355 case 0x98: /* CWDE/CBW */
5356 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5359 case 0x99: /* CDQ/CWD */
5360 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5361 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5364 case 0x0faf: /* imul */
5367 ir.ot = ir.dflag + OT_WORD;
5368 if (i386_record_modrm (&ir))
5371 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5372 else if (opcode == 0x6b)
5375 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5377 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5378 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5381 case 0x0fc0: /* xadd */
5383 if ((opcode & 1) == 0)
5386 ir.ot = ir.dflag + OT_WORD;
5387 if (i386_record_modrm (&ir))
5392 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5395 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5397 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5401 if (i386_record_lea_modrm (&ir))
5403 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5405 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5407 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5410 case 0x0fb0: /* cmpxchg */
5412 if ((opcode & 1) == 0)
5415 ir.ot = ir.dflag + OT_WORD;
5416 if (i386_record_modrm (&ir))
5421 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5422 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5429 if (i386_record_lea_modrm (&ir))
5432 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5435 case 0x0fc7: /* cmpxchg8b */
5436 if (i386_record_modrm (&ir))
5441 opcode = opcode << 8 | ir.modrm;
5444 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5445 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5446 if (i386_record_lea_modrm (&ir))
5448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5451 case 0x50: /* push */
5461 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5463 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5467 case 0x06: /* push es */
5468 case 0x0e: /* push cs */
5469 case 0x16: /* push ss */
5470 case 0x1e: /* push ds */
5471 if (ir.regmap[X86_RECORD_R8_REGNUM])
5476 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5480 case 0x0fa0: /* push fs */
5481 case 0x0fa8: /* push gs */
5482 if (ir.regmap[X86_RECORD_R8_REGNUM])
5487 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5491 case 0x60: /* pusha */
5492 if (ir.regmap[X86_RECORD_R8_REGNUM])
5497 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5501 case 0x58: /* pop */
5509 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5510 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5513 case 0x61: /* popa */
5514 if (ir.regmap[X86_RECORD_R8_REGNUM])
5519 for (regnum = X86_RECORD_REAX_REGNUM;
5520 regnum <= X86_RECORD_REDI_REGNUM;
5522 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5525 case 0x8f: /* pop */
5526 if (ir.regmap[X86_RECORD_R8_REGNUM])
5527 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5529 ir.ot = ir.dflag + OT_WORD;
5530 if (i386_record_modrm (&ir))
5533 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5536 ir.popl_esp_hack = 1 << ir.ot;
5537 if (i386_record_lea_modrm (&ir))
5540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5543 case 0xc8: /* enter */
5544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5545 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5547 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5551 case 0xc9: /* leave */
5552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5556 case 0x07: /* pop es */
5557 if (ir.regmap[X86_RECORD_R8_REGNUM])
5562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5567 case 0x17: /* pop ss */
5568 if (ir.regmap[X86_RECORD_R8_REGNUM])
5573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5575 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5578 case 0x1f: /* pop ds */
5579 if (ir.regmap[X86_RECORD_R8_REGNUM])
5584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5585 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5586 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5589 case 0x0fa1: /* pop fs */
5590 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5591 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5592 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5595 case 0x0fa9: /* pop gs */
5596 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5597 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5598 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5601 case 0x88: /* mov */
5605 if ((opcode & 1) == 0)
5608 ir.ot = ir.dflag + OT_WORD;
5610 if (i386_record_modrm (&ir))
5615 if (opcode == 0xc6 || opcode == 0xc7)
5616 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5617 if (i386_record_lea_modrm (&ir))
5622 if (opcode == 0xc6 || opcode == 0xc7)
5624 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5626 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5630 case 0x8a: /* mov */
5632 if ((opcode & 1) == 0)
5635 ir.ot = ir.dflag + OT_WORD;
5636 if (i386_record_modrm (&ir))
5639 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5641 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5644 case 0x8c: /* mov seg */
5645 if (i386_record_modrm (&ir))
5650 opcode = opcode << 8 | ir.modrm;
5655 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5659 if (i386_record_lea_modrm (&ir))
5664 case 0x8e: /* mov seg */
5665 if (i386_record_modrm (&ir))
5670 regnum = X86_RECORD_ES_REGNUM;
5673 regnum = X86_RECORD_SS_REGNUM;
5676 regnum = X86_RECORD_DS_REGNUM;
5679 regnum = X86_RECORD_FS_REGNUM;
5682 regnum = X86_RECORD_GS_REGNUM;
5686 opcode = opcode << 8 | ir.modrm;
5690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5694 case 0x0fb6: /* movzbS */
5695 case 0x0fb7: /* movzwS */
5696 case 0x0fbe: /* movsbS */
5697 case 0x0fbf: /* movswS */
5698 if (i386_record_modrm (&ir))
5700 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5703 case 0x8d: /* lea */
5704 if (i386_record_modrm (&ir))
5709 opcode = opcode << 8 | ir.modrm;
5714 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5719 case 0xa0: /* mov EAX */
5722 case 0xd7: /* xlat */
5723 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5726 case 0xa2: /* mov EAX */
5728 if (ir.override >= 0)
5730 if (record_full_memory_query)
5734 target_terminal_ours ();
5736 Process record ignores the memory change of instruction at address %s\n\
5737 because it can't get the value of the segment register.\n\
5738 Do you want to stop the program?"),
5739 paddress (gdbarch, ir.orig_addr));
5740 target_terminal_inferior ();
5747 if ((opcode & 1) == 0)
5750 ir.ot = ir.dflag + OT_WORD;
5753 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5756 addr = extract_unsigned_integer (buf, 8, byte_order);
5760 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5763 addr = extract_unsigned_integer (buf, 4, byte_order);
5767 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5770 addr = extract_unsigned_integer (buf, 2, byte_order);
5772 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5777 case 0xb0: /* mov R, Ib */
5785 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5786 ? ((opcode & 0x7) | ir.rex_b)
5787 : ((opcode & 0x7) & 0x3));
5790 case 0xb8: /* mov R, Iv */
5798 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5801 case 0x91: /* xchg R, EAX */
5808 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5812 case 0x86: /* xchg Ev, Gv */
5814 if ((opcode & 1) == 0)
5817 ir.ot = ir.dflag + OT_WORD;
5818 if (i386_record_modrm (&ir))
5823 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5825 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5829 if (i386_record_lea_modrm (&ir))
5833 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5835 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5838 case 0xc4: /* les Gv */
5839 case 0xc5: /* lds Gv */
5840 if (ir.regmap[X86_RECORD_R8_REGNUM])
5846 case 0x0fb2: /* lss Gv */
5847 case 0x0fb4: /* lfs Gv */
5848 case 0x0fb5: /* lgs Gv */
5849 if (i386_record_modrm (&ir))
5857 opcode = opcode << 8 | ir.modrm;
5862 case 0xc4: /* les Gv */
5863 regnum = X86_RECORD_ES_REGNUM;
5865 case 0xc5: /* lds Gv */
5866 regnum = X86_RECORD_DS_REGNUM;
5868 case 0x0fb2: /* lss Gv */
5869 regnum = X86_RECORD_SS_REGNUM;
5871 case 0x0fb4: /* lfs Gv */
5872 regnum = X86_RECORD_FS_REGNUM;
5874 case 0x0fb5: /* lgs Gv */
5875 regnum = X86_RECORD_GS_REGNUM;
5878 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5879 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5880 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5883 case 0xc0: /* shifts */
5889 if ((opcode & 1) == 0)
5892 ir.ot = ir.dflag + OT_WORD;
5893 if (i386_record_modrm (&ir))
5895 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5897 if (i386_record_lea_modrm (&ir))
5903 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5905 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5907 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5914 if (i386_record_modrm (&ir))
5918 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5923 if (i386_record_lea_modrm (&ir))
5928 case 0xd8: /* Floats. */
5936 if (i386_record_modrm (&ir))
5938 ir.reg |= ((opcode & 7) << 3);
5944 if (i386_record_lea_modrm_addr (&ir, &addr64))
5952 /* For fcom, ficom nothing to do. */
5958 /* For fcomp, ficomp pop FPU stack, store all. */
5959 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5986 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5987 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5988 of code, always affects st(0) register. */
5989 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6013 /* Handling fld, fild. */
6014 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6018 switch (ir.reg >> 4)
6021 if (record_full_arch_list_add_mem (addr64, 4))
6025 if (record_full_arch_list_add_mem (addr64, 8))
6031 if (record_full_arch_list_add_mem (addr64, 2))
6037 switch (ir.reg >> 4)
6040 if (record_full_arch_list_add_mem (addr64, 4))
6042 if (3 == (ir.reg & 7))
6044 /* For fstp m32fp. */
6045 if (i386_record_floats (gdbarch, &ir,
6046 I386_SAVE_FPU_REGS))
6051 if (record_full_arch_list_add_mem (addr64, 4))
6053 if ((3 == (ir.reg & 7))
6054 || (5 == (ir.reg & 7))
6055 || (7 == (ir.reg & 7)))
6057 /* For fstp insn. */
6058 if (i386_record_floats (gdbarch, &ir,
6059 I386_SAVE_FPU_REGS))
6064 if (record_full_arch_list_add_mem (addr64, 8))
6066 if (3 == (ir.reg & 7))
6068 /* For fstp m64fp. */
6069 if (i386_record_floats (gdbarch, &ir,
6070 I386_SAVE_FPU_REGS))
6075 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6077 /* For fistp, fbld, fild, fbstp. */
6078 if (i386_record_floats (gdbarch, &ir,
6079 I386_SAVE_FPU_REGS))
6084 if (record_full_arch_list_add_mem (addr64, 2))
6093 if (i386_record_floats (gdbarch, &ir,
6094 I386_SAVE_FPU_ENV_REG_STACK))
6099 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6104 if (i386_record_floats (gdbarch, &ir,
6105 I386_SAVE_FPU_ENV_REG_STACK))
6111 if (record_full_arch_list_add_mem (addr64, 28))
6116 if (record_full_arch_list_add_mem (addr64, 14))
6122 if (record_full_arch_list_add_mem (addr64, 2))
6124 /* Insn fstp, fbstp. */
6125 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6130 if (record_full_arch_list_add_mem (addr64, 10))
6136 if (record_full_arch_list_add_mem (addr64, 28))
6142 if (record_full_arch_list_add_mem (addr64, 14))
6146 if (record_full_arch_list_add_mem (addr64, 80))
6149 if (i386_record_floats (gdbarch, &ir,
6150 I386_SAVE_FPU_ENV_REG_STACK))
6154 if (record_full_arch_list_add_mem (addr64, 8))
6157 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6162 opcode = opcode << 8 | ir.modrm;
6167 /* Opcode is an extension of modR/M byte. */
6173 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6177 if (0x0c == (ir.modrm >> 4))
6179 if ((ir.modrm & 0x0f) <= 7)
6181 if (i386_record_floats (gdbarch, &ir,
6182 I386_SAVE_FPU_REGS))
6187 if (i386_record_floats (gdbarch, &ir,
6188 I387_ST0_REGNUM (tdep)))
6190 /* If only st(0) is changing, then we have already
6192 if ((ir.modrm & 0x0f) - 0x08)
6194 if (i386_record_floats (gdbarch, &ir,
6195 I387_ST0_REGNUM (tdep) +
6196 ((ir.modrm & 0x0f) - 0x08)))
6214 if (i386_record_floats (gdbarch, &ir,
6215 I387_ST0_REGNUM (tdep)))
6233 if (i386_record_floats (gdbarch, &ir,
6234 I386_SAVE_FPU_REGS))
6238 if (i386_record_floats (gdbarch, &ir,
6239 I387_ST0_REGNUM (tdep)))
6241 if (i386_record_floats (gdbarch, &ir,
6242 I387_ST0_REGNUM (tdep) + 1))
6249 if (0xe9 == ir.modrm)
6251 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6254 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6256 if (i386_record_floats (gdbarch, &ir,
6257 I387_ST0_REGNUM (tdep)))
6259 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6261 if (i386_record_floats (gdbarch, &ir,
6262 I387_ST0_REGNUM (tdep) +
6266 else if ((ir.modrm & 0x0f) - 0x08)
6268 if (i386_record_floats (gdbarch, &ir,
6269 I387_ST0_REGNUM (tdep) +
6270 ((ir.modrm & 0x0f) - 0x08)))
6276 if (0xe3 == ir.modrm)
6278 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6281 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6283 if (i386_record_floats (gdbarch, &ir,
6284 I387_ST0_REGNUM (tdep)))
6286 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6288 if (i386_record_floats (gdbarch, &ir,
6289 I387_ST0_REGNUM (tdep) +
6293 else if ((ir.modrm & 0x0f) - 0x08)
6295 if (i386_record_floats (gdbarch, &ir,
6296 I387_ST0_REGNUM (tdep) +
6297 ((ir.modrm & 0x0f) - 0x08)))
6303 if ((0x0c == ir.modrm >> 4)
6304 || (0x0d == ir.modrm >> 4)
6305 || (0x0f == ir.modrm >> 4))
6307 if ((ir.modrm & 0x0f) <= 7)
6309 if (i386_record_floats (gdbarch, &ir,
6310 I387_ST0_REGNUM (tdep) +
6316 if (i386_record_floats (gdbarch, &ir,
6317 I387_ST0_REGNUM (tdep) +
6318 ((ir.modrm & 0x0f) - 0x08)))
6324 if (0x0c == ir.modrm >> 4)
6326 if (i386_record_floats (gdbarch, &ir,
6327 I387_FTAG_REGNUM (tdep)))
6330 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6332 if ((ir.modrm & 0x0f) <= 7)
6334 if (i386_record_floats (gdbarch, &ir,
6335 I387_ST0_REGNUM (tdep) +
6341 if (i386_record_floats (gdbarch, &ir,
6342 I386_SAVE_FPU_REGS))
6348 if ((0x0c == ir.modrm >> 4)
6349 || (0x0e == ir.modrm >> 4)
6350 || (0x0f == ir.modrm >> 4)
6351 || (0xd9 == ir.modrm))
6353 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6358 if (0xe0 == ir.modrm)
6360 if (record_full_arch_list_add_reg (ir.regcache,
6364 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6366 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6374 case 0xa4: /* movsS */
6376 case 0xaa: /* stosS */
6378 case 0x6c: /* insS */
6380 regcache_raw_read_unsigned (ir.regcache,
6381 ir.regmap[X86_RECORD_RECX_REGNUM],
6387 if ((opcode & 1) == 0)
6390 ir.ot = ir.dflag + OT_WORD;
6391 regcache_raw_read_unsigned (ir.regcache,
6392 ir.regmap[X86_RECORD_REDI_REGNUM],
6395 regcache_raw_read_unsigned (ir.regcache,
6396 ir.regmap[X86_RECORD_ES_REGNUM],
6398 regcache_raw_read_unsigned (ir.regcache,
6399 ir.regmap[X86_RECORD_DS_REGNUM],
6401 if (ir.aflag && (es != ds))
6403 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6404 if (record_full_memory_query)
6408 target_terminal_ours ();
6410 Process record ignores the memory change of instruction at address %s\n\
6411 because it can't get the value of the segment register.\n\
6412 Do you want to stop the program?"),
6413 paddress (gdbarch, ir.orig_addr));
6414 target_terminal_inferior ();
6421 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6425 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6426 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6427 if (opcode == 0xa4 || opcode == 0xa5)
6428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6429 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6430 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6434 case 0xa6: /* cmpsS */
6436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6437 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6438 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6439 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6440 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6443 case 0xac: /* lodsS */
6445 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6446 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6447 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6452 case 0xae: /* scasS */
6454 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6455 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6460 case 0x6e: /* outsS */
6462 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6463 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6464 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6465 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6468 case 0xe4: /* port I/O */
6472 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6483 case 0xc2: /* ret im */
6484 case 0xc3: /* ret */
6485 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6489 case 0xca: /* lret im */
6490 case 0xcb: /* lret */
6491 case 0xcf: /* iret */
6492 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6497 case 0xe8: /* call im */
6498 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6500 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6504 case 0x9a: /* lcall im */
6505 if (ir.regmap[X86_RECORD_R8_REGNUM])
6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6511 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6515 case 0xe9: /* jmp im */
6516 case 0xea: /* ljmp im */
6517 case 0xeb: /* jmp Jb */
6518 case 0x70: /* jcc Jb */
6534 case 0x0f80: /* jcc Jv */
6552 case 0x0f90: /* setcc Gv */
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6570 if (i386_record_modrm (&ir))
6573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6577 if (i386_record_lea_modrm (&ir))
6582 case 0x0f40: /* cmov Gv, Ev */
6598 if (i386_record_modrm (&ir))
6601 if (ir.dflag == OT_BYTE)
6603 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6607 case 0x9c: /* pushf */
6608 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6609 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6611 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6615 case 0x9d: /* popf */
6616 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6617 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6620 case 0x9e: /* sahf */
6621 if (ir.regmap[X86_RECORD_R8_REGNUM])
6627 case 0xf5: /* cmc */
6628 case 0xf8: /* clc */
6629 case 0xf9: /* stc */
6630 case 0xfc: /* cld */
6631 case 0xfd: /* std */
6632 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6635 case 0x9f: /* lahf */
6636 if (ir.regmap[X86_RECORD_R8_REGNUM])
6641 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6642 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6645 /* bit operations */
6646 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6647 ir.ot = ir.dflag + OT_WORD;
6648 if (i386_record_modrm (&ir))
6653 opcode = opcode << 8 | ir.modrm;
6659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6662 if (i386_record_lea_modrm (&ir))
6666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6669 case 0x0fa3: /* bt Gv, Ev */
6670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6673 case 0x0fab: /* bts */
6674 case 0x0fb3: /* btr */
6675 case 0x0fbb: /* btc */
6676 ir.ot = ir.dflag + OT_WORD;
6677 if (i386_record_modrm (&ir))
6680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6684 if (i386_record_lea_modrm_addr (&ir, &addr64))
6686 regcache_raw_read_unsigned (ir.regcache,
6687 ir.regmap[ir.reg | rex_r],
6692 addr64 += ((int16_t) addr >> 4) << 4;
6695 addr64 += ((int32_t) addr >> 5) << 5;
6698 addr64 += ((int64_t) addr >> 6) << 6;
6701 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6703 if (i386_record_lea_modrm (&ir))
6706 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6709 case 0x0fbc: /* bsf */
6710 case 0x0fbd: /* bsr */
6711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6712 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6716 case 0x27: /* daa */
6717 case 0x2f: /* das */
6718 case 0x37: /* aaa */
6719 case 0x3f: /* aas */
6720 case 0xd4: /* aam */
6721 case 0xd5: /* aad */
6722 if (ir.regmap[X86_RECORD_R8_REGNUM])
6727 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6728 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6732 case 0x90: /* nop */
6733 if (prefixes & PREFIX_LOCK)
6740 case 0x9b: /* fwait */
6741 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6743 opcode = (uint32_t) opcode8;
6749 case 0xcc: /* int3 */
6750 printf_unfiltered (_("Process record does not support instruction "
6757 case 0xcd: /* int */
6761 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6764 if (interrupt != 0x80
6765 || tdep->i386_intx80_record == NULL)
6767 printf_unfiltered (_("Process record does not support "
6768 "instruction int 0x%02x.\n"),
6773 ret = tdep->i386_intx80_record (ir.regcache);
6780 case 0xce: /* into */
6781 printf_unfiltered (_("Process record does not support "
6782 "instruction into.\n"));
6787 case 0xfa: /* cli */
6788 case 0xfb: /* sti */
6791 case 0x62: /* bound */
6792 printf_unfiltered (_("Process record does not support "
6793 "instruction bound.\n"));
6798 case 0x0fc8: /* bswap reg */
6806 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6809 case 0xd6: /* salc */
6810 if (ir.regmap[X86_RECORD_R8_REGNUM])
6815 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6816 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6819 case 0xe0: /* loopnz */
6820 case 0xe1: /* loopz */
6821 case 0xe2: /* loop */
6822 case 0xe3: /* jecxz */
6823 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6824 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6827 case 0x0f30: /* wrmsr */
6828 printf_unfiltered (_("Process record does not support "
6829 "instruction wrmsr.\n"));
6834 case 0x0f32: /* rdmsr */
6835 printf_unfiltered (_("Process record does not support "
6836 "instruction rdmsr.\n"));
6841 case 0x0f31: /* rdtsc */
6842 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6843 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6846 case 0x0f34: /* sysenter */
6849 if (ir.regmap[X86_RECORD_R8_REGNUM])
6854 if (tdep->i386_sysenter_record == NULL)
6856 printf_unfiltered (_("Process record does not support "
6857 "instruction sysenter.\n"));
6861 ret = tdep->i386_sysenter_record (ir.regcache);
6867 case 0x0f35: /* sysexit */
6868 printf_unfiltered (_("Process record does not support "
6869 "instruction sysexit.\n"));
6874 case 0x0f05: /* syscall */
6877 if (tdep->i386_syscall_record == NULL)
6879 printf_unfiltered (_("Process record does not support "
6880 "instruction syscall.\n"));
6884 ret = tdep->i386_syscall_record (ir.regcache);
6890 case 0x0f07: /* sysret */
6891 printf_unfiltered (_("Process record does not support "
6892 "instruction sysret.\n"));
6897 case 0x0fa2: /* cpuid */
6898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6899 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6900 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6901 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6904 case 0xf4: /* hlt */
6905 printf_unfiltered (_("Process record does not support "
6906 "instruction hlt.\n"));
6912 if (i386_record_modrm (&ir))
6919 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6923 if (i386_record_lea_modrm (&ir))
6932 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6936 opcode = opcode << 8 | ir.modrm;
6943 if (i386_record_modrm (&ir))
6954 opcode = opcode << 8 | ir.modrm;
6957 if (ir.override >= 0)
6959 if (record_full_memory_query)
6963 target_terminal_ours ();
6965 Process record ignores the memory change of instruction at address %s\n\
6966 because it can't get the value of the segment register.\n\
6967 Do you want to stop the program?"),
6968 paddress (gdbarch, ir.orig_addr));
6969 target_terminal_inferior ();
6976 if (i386_record_lea_modrm_addr (&ir, &addr64))
6978 if (record_full_arch_list_add_mem (addr64, 2))
6981 if (ir.regmap[X86_RECORD_R8_REGNUM])
6983 if (record_full_arch_list_add_mem (addr64, 8))
6988 if (record_full_arch_list_add_mem (addr64, 4))
6999 case 0: /* monitor */
7002 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7006 opcode = opcode << 8 | ir.modrm;
7014 if (ir.override >= 0)
7016 if (record_full_memory_query)
7020 target_terminal_ours ();
7022 Process record ignores the memory change of instruction at address %s\n\
7023 because it can't get the value of the segment register.\n\
7024 Do you want to stop the program?"),
7025 paddress (gdbarch, ir.orig_addr));
7026 target_terminal_inferior ();
7035 if (i386_record_lea_modrm_addr (&ir, &addr64))
7037 if (record_full_arch_list_add_mem (addr64, 2))
7040 if (ir.regmap[X86_RECORD_R8_REGNUM])
7042 if (record_full_arch_list_add_mem (addr64, 8))
7047 if (record_full_arch_list_add_mem (addr64, 4))
7059 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7064 else if (ir.rm == 1)
7071 opcode = opcode << 8 | ir.modrm;
7078 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7084 if (i386_record_lea_modrm (&ir))
7087 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7090 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7092 case 7: /* invlpg */
7095 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7096 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7100 opcode = opcode << 8 | ir.modrm;
7105 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7109 opcode = opcode << 8 | ir.modrm;
7115 case 0x0f08: /* invd */
7116 case 0x0f09: /* wbinvd */
7119 case 0x63: /* arpl */
7120 if (i386_record_modrm (&ir))
7122 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7124 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7125 ? (ir.reg | rex_r) : ir.rm);
7129 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7130 if (i386_record_lea_modrm (&ir))
7133 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7134 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7137 case 0x0f02: /* lar */
7138 case 0x0f03: /* lsl */
7139 if (i386_record_modrm (&ir))
7141 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7142 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7146 if (i386_record_modrm (&ir))
7148 if (ir.mod == 3 && ir.reg == 3)
7151 opcode = opcode << 8 | ir.modrm;
7163 /* nop (multi byte) */
7166 case 0x0f20: /* mov reg, crN */
7167 case 0x0f22: /* mov crN, reg */
7168 if (i386_record_modrm (&ir))
7170 if ((ir.modrm & 0xc0) != 0xc0)
7173 opcode = opcode << 8 | ir.modrm;
7184 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7186 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7190 opcode = opcode << 8 | ir.modrm;
7196 case 0x0f21: /* mov reg, drN */
7197 case 0x0f23: /* mov drN, reg */
7198 if (i386_record_modrm (&ir))
7200 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7201 || ir.reg == 5 || ir.reg >= 8)
7204 opcode = opcode << 8 | ir.modrm;
7208 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7210 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7213 case 0x0f06: /* clts */
7214 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7217 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7219 case 0x0f0d: /* 3DNow! prefetch */
7222 case 0x0f0e: /* 3DNow! femms */
7223 case 0x0f77: /* emms */
7224 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7226 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7229 case 0x0f0f: /* 3DNow! data */
7230 if (i386_record_modrm (&ir))
7232 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7237 case 0x0c: /* 3DNow! pi2fw */
7238 case 0x0d: /* 3DNow! pi2fd */
7239 case 0x1c: /* 3DNow! pf2iw */
7240 case 0x1d: /* 3DNow! pf2id */
7241 case 0x8a: /* 3DNow! pfnacc */
7242 case 0x8e: /* 3DNow! pfpnacc */
7243 case 0x90: /* 3DNow! pfcmpge */
7244 case 0x94: /* 3DNow! pfmin */
7245 case 0x96: /* 3DNow! pfrcp */
7246 case 0x97: /* 3DNow! pfrsqrt */
7247 case 0x9a: /* 3DNow! pfsub */
7248 case 0x9e: /* 3DNow! pfadd */
7249 case 0xa0: /* 3DNow! pfcmpgt */
7250 case 0xa4: /* 3DNow! pfmax */
7251 case 0xa6: /* 3DNow! pfrcpit1 */
7252 case 0xa7: /* 3DNow! pfrsqit1 */
7253 case 0xaa: /* 3DNow! pfsubr */
7254 case 0xae: /* 3DNow! pfacc */
7255 case 0xb0: /* 3DNow! pfcmpeq */
7256 case 0xb4: /* 3DNow! pfmul */
7257 case 0xb6: /* 3DNow! pfrcpit2 */
7258 case 0xb7: /* 3DNow! pmulhrw */
7259 case 0xbb: /* 3DNow! pswapd */
7260 case 0xbf: /* 3DNow! pavgusb */
7261 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7262 goto no_support_3dnow_data;
7263 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7267 no_support_3dnow_data:
7268 opcode = (opcode << 8) | opcode8;
7274 case 0x0faa: /* rsm */
7275 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7276 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7277 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7278 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7280 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7281 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7282 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7283 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7287 if (i386_record_modrm (&ir))
7291 case 0: /* fxsave */
7295 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7296 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7298 if (record_full_arch_list_add_mem (tmpu64, 512))
7303 case 1: /* fxrstor */
7307 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7309 for (i = I387_MM0_REGNUM (tdep);
7310 i386_mmx_regnum_p (gdbarch, i); i++)
7311 record_full_arch_list_add_reg (ir.regcache, i);
7313 for (i = I387_XMM0_REGNUM (tdep);
7314 i386_xmm_regnum_p (gdbarch, i); i++)
7315 record_full_arch_list_add_reg (ir.regcache, i);
7317 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7318 record_full_arch_list_add_reg (ir.regcache,
7319 I387_MXCSR_REGNUM(tdep));
7321 for (i = I387_ST0_REGNUM (tdep);
7322 i386_fp_regnum_p (gdbarch, i); i++)
7323 record_full_arch_list_add_reg (ir.regcache, i);
7325 for (i = I387_FCTRL_REGNUM (tdep);
7326 i386_fpc_regnum_p (gdbarch, i); i++)
7327 record_full_arch_list_add_reg (ir.regcache, i);
7331 case 2: /* ldmxcsr */
7332 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7334 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7337 case 3: /* stmxcsr */
7339 if (i386_record_lea_modrm (&ir))
7343 case 5: /* lfence */
7344 case 6: /* mfence */
7345 case 7: /* sfence clflush */
7349 opcode = (opcode << 8) | ir.modrm;
7355 case 0x0fc3: /* movnti */
7356 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7357 if (i386_record_modrm (&ir))
7362 if (i386_record_lea_modrm (&ir))
7366 /* Add prefix to opcode. */
7481 /* Mask out PREFIX_ADDR. */
7482 switch ((prefixes & ~PREFIX_ADDR))
7494 reswitch_prefix_add:
7502 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7505 opcode = (uint32_t) opcode8 | opcode << 8;
7506 goto reswitch_prefix_add;
7509 case 0x0f10: /* movups */
7510 case 0x660f10: /* movupd */
7511 case 0xf30f10: /* movss */
7512 case 0xf20f10: /* movsd */
7513 case 0x0f12: /* movlps */
7514 case 0x660f12: /* movlpd */
7515 case 0xf30f12: /* movsldup */
7516 case 0xf20f12: /* movddup */
7517 case 0x0f14: /* unpcklps */
7518 case 0x660f14: /* unpcklpd */
7519 case 0x0f15: /* unpckhps */
7520 case 0x660f15: /* unpckhpd */
7521 case 0x0f16: /* movhps */
7522 case 0x660f16: /* movhpd */
7523 case 0xf30f16: /* movshdup */
7524 case 0x0f28: /* movaps */
7525 case 0x660f28: /* movapd */
7526 case 0x0f2a: /* cvtpi2ps */
7527 case 0x660f2a: /* cvtpi2pd */
7528 case 0xf30f2a: /* cvtsi2ss */
7529 case 0xf20f2a: /* cvtsi2sd */
7530 case 0x0f2c: /* cvttps2pi */
7531 case 0x660f2c: /* cvttpd2pi */
7532 case 0x0f2d: /* cvtps2pi */
7533 case 0x660f2d: /* cvtpd2pi */
7534 case 0x660f3800: /* pshufb */
7535 case 0x660f3801: /* phaddw */
7536 case 0x660f3802: /* phaddd */
7537 case 0x660f3803: /* phaddsw */
7538 case 0x660f3804: /* pmaddubsw */
7539 case 0x660f3805: /* phsubw */
7540 case 0x660f3806: /* phsubd */
7541 case 0x660f3807: /* phsubsw */
7542 case 0x660f3808: /* psignb */
7543 case 0x660f3809: /* psignw */
7544 case 0x660f380a: /* psignd */
7545 case 0x660f380b: /* pmulhrsw */
7546 case 0x660f3810: /* pblendvb */
7547 case 0x660f3814: /* blendvps */
7548 case 0x660f3815: /* blendvpd */
7549 case 0x660f381c: /* pabsb */
7550 case 0x660f381d: /* pabsw */
7551 case 0x660f381e: /* pabsd */
7552 case 0x660f3820: /* pmovsxbw */
7553 case 0x660f3821: /* pmovsxbd */
7554 case 0x660f3822: /* pmovsxbq */
7555 case 0x660f3823: /* pmovsxwd */
7556 case 0x660f3824: /* pmovsxwq */
7557 case 0x660f3825: /* pmovsxdq */
7558 case 0x660f3828: /* pmuldq */
7559 case 0x660f3829: /* pcmpeqq */
7560 case 0x660f382a: /* movntdqa */
7561 case 0x660f3a08: /* roundps */
7562 case 0x660f3a09: /* roundpd */
7563 case 0x660f3a0a: /* roundss */
7564 case 0x660f3a0b: /* roundsd */
7565 case 0x660f3a0c: /* blendps */
7566 case 0x660f3a0d: /* blendpd */
7567 case 0x660f3a0e: /* pblendw */
7568 case 0x660f3a0f: /* palignr */
7569 case 0x660f3a20: /* pinsrb */
7570 case 0x660f3a21: /* insertps */
7571 case 0x660f3a22: /* pinsrd pinsrq */
7572 case 0x660f3a40: /* dpps */
7573 case 0x660f3a41: /* dppd */
7574 case 0x660f3a42: /* mpsadbw */
7575 case 0x660f3a60: /* pcmpestrm */
7576 case 0x660f3a61: /* pcmpestri */
7577 case 0x660f3a62: /* pcmpistrm */
7578 case 0x660f3a63: /* pcmpistri */
7579 case 0x0f51: /* sqrtps */
7580 case 0x660f51: /* sqrtpd */
7581 case 0xf20f51: /* sqrtsd */
7582 case 0xf30f51: /* sqrtss */
7583 case 0x0f52: /* rsqrtps */
7584 case 0xf30f52: /* rsqrtss */
7585 case 0x0f53: /* rcpps */
7586 case 0xf30f53: /* rcpss */
7587 case 0x0f54: /* andps */
7588 case 0x660f54: /* andpd */
7589 case 0x0f55: /* andnps */
7590 case 0x660f55: /* andnpd */
7591 case 0x0f56: /* orps */
7592 case 0x660f56: /* orpd */
7593 case 0x0f57: /* xorps */
7594 case 0x660f57: /* xorpd */
7595 case 0x0f58: /* addps */
7596 case 0x660f58: /* addpd */
7597 case 0xf20f58: /* addsd */
7598 case 0xf30f58: /* addss */
7599 case 0x0f59: /* mulps */
7600 case 0x660f59: /* mulpd */
7601 case 0xf20f59: /* mulsd */
7602 case 0xf30f59: /* mulss */
7603 case 0x0f5a: /* cvtps2pd */
7604 case 0x660f5a: /* cvtpd2ps */
7605 case 0xf20f5a: /* cvtsd2ss */
7606 case 0xf30f5a: /* cvtss2sd */
7607 case 0x0f5b: /* cvtdq2ps */
7608 case 0x660f5b: /* cvtps2dq */
7609 case 0xf30f5b: /* cvttps2dq */
7610 case 0x0f5c: /* subps */
7611 case 0x660f5c: /* subpd */
7612 case 0xf20f5c: /* subsd */
7613 case 0xf30f5c: /* subss */
7614 case 0x0f5d: /* minps */
7615 case 0x660f5d: /* minpd */
7616 case 0xf20f5d: /* minsd */
7617 case 0xf30f5d: /* minss */
7618 case 0x0f5e: /* divps */
7619 case 0x660f5e: /* divpd */
7620 case 0xf20f5e: /* divsd */
7621 case 0xf30f5e: /* divss */
7622 case 0x0f5f: /* maxps */
7623 case 0x660f5f: /* maxpd */
7624 case 0xf20f5f: /* maxsd */
7625 case 0xf30f5f: /* maxss */
7626 case 0x660f60: /* punpcklbw */
7627 case 0x660f61: /* punpcklwd */
7628 case 0x660f62: /* punpckldq */
7629 case 0x660f63: /* packsswb */
7630 case 0x660f64: /* pcmpgtb */
7631 case 0x660f65: /* pcmpgtw */
7632 case 0x660f66: /* pcmpgtd */
7633 case 0x660f67: /* packuswb */
7634 case 0x660f68: /* punpckhbw */
7635 case 0x660f69: /* punpckhwd */
7636 case 0x660f6a: /* punpckhdq */
7637 case 0x660f6b: /* packssdw */
7638 case 0x660f6c: /* punpcklqdq */
7639 case 0x660f6d: /* punpckhqdq */
7640 case 0x660f6e: /* movd */
7641 case 0x660f6f: /* movdqa */
7642 case 0xf30f6f: /* movdqu */
7643 case 0x660f70: /* pshufd */
7644 case 0xf20f70: /* pshuflw */
7645 case 0xf30f70: /* pshufhw */
7646 case 0x660f74: /* pcmpeqb */
7647 case 0x660f75: /* pcmpeqw */
7648 case 0x660f76: /* pcmpeqd */
7649 case 0x660f7c: /* haddpd */
7650 case 0xf20f7c: /* haddps */
7651 case 0x660f7d: /* hsubpd */
7652 case 0xf20f7d: /* hsubps */
7653 case 0xf30f7e: /* movq */
7654 case 0x0fc2: /* cmpps */
7655 case 0x660fc2: /* cmppd */
7656 case 0xf20fc2: /* cmpsd */
7657 case 0xf30fc2: /* cmpss */
7658 case 0x660fc4: /* pinsrw */
7659 case 0x0fc6: /* shufps */
7660 case 0x660fc6: /* shufpd */
7661 case 0x660fd0: /* addsubpd */
7662 case 0xf20fd0: /* addsubps */
7663 case 0x660fd1: /* psrlw */
7664 case 0x660fd2: /* psrld */
7665 case 0x660fd3: /* psrlq */
7666 case 0x660fd4: /* paddq */
7667 case 0x660fd5: /* pmullw */
7668 case 0xf30fd6: /* movq2dq */
7669 case 0x660fd8: /* psubusb */
7670 case 0x660fd9: /* psubusw */
7671 case 0x660fda: /* pminub */
7672 case 0x660fdb: /* pand */
7673 case 0x660fdc: /* paddusb */
7674 case 0x660fdd: /* paddusw */
7675 case 0x660fde: /* pmaxub */
7676 case 0x660fdf: /* pandn */
7677 case 0x660fe0: /* pavgb */
7678 case 0x660fe1: /* psraw */
7679 case 0x660fe2: /* psrad */
7680 case 0x660fe3: /* pavgw */
7681 case 0x660fe4: /* pmulhuw */
7682 case 0x660fe5: /* pmulhw */
7683 case 0x660fe6: /* cvttpd2dq */
7684 case 0xf20fe6: /* cvtpd2dq */
7685 case 0xf30fe6: /* cvtdq2pd */
7686 case 0x660fe8: /* psubsb */
7687 case 0x660fe9: /* psubsw */
7688 case 0x660fea: /* pminsw */
7689 case 0x660feb: /* por */
7690 case 0x660fec: /* paddsb */
7691 case 0x660fed: /* paddsw */
7692 case 0x660fee: /* pmaxsw */
7693 case 0x660fef: /* pxor */
7694 case 0xf20ff0: /* lddqu */
7695 case 0x660ff1: /* psllw */
7696 case 0x660ff2: /* pslld */
7697 case 0x660ff3: /* psllq */
7698 case 0x660ff4: /* pmuludq */
7699 case 0x660ff5: /* pmaddwd */
7700 case 0x660ff6: /* psadbw */
7701 case 0x660ff8: /* psubb */
7702 case 0x660ff9: /* psubw */
7703 case 0x660ffa: /* psubd */
7704 case 0x660ffb: /* psubq */
7705 case 0x660ffc: /* paddb */
7706 case 0x660ffd: /* paddw */
7707 case 0x660ffe: /* paddd */
7708 if (i386_record_modrm (&ir))
7711 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7713 record_full_arch_list_add_reg (ir.regcache,
7714 I387_XMM0_REGNUM (tdep) + ir.reg);
7715 if ((opcode & 0xfffffffc) == 0x660f3a60)
7716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7719 case 0x0f11: /* movups */
7720 case 0x660f11: /* movupd */
7721 case 0xf30f11: /* movss */
7722 case 0xf20f11: /* movsd */
7723 case 0x0f13: /* movlps */
7724 case 0x660f13: /* movlpd */
7725 case 0x0f17: /* movhps */
7726 case 0x660f17: /* movhpd */
7727 case 0x0f29: /* movaps */
7728 case 0x660f29: /* movapd */
7729 case 0x660f3a14: /* pextrb */
7730 case 0x660f3a15: /* pextrw */
7731 case 0x660f3a16: /* pextrd pextrq */
7732 case 0x660f3a17: /* extractps */
7733 case 0x660f7f: /* movdqa */
7734 case 0xf30f7f: /* movdqu */
7735 if (i386_record_modrm (&ir))
7739 if (opcode == 0x0f13 || opcode == 0x660f13
7740 || opcode == 0x0f17 || opcode == 0x660f17)
7743 if (!i386_xmm_regnum_p (gdbarch,
7744 I387_XMM0_REGNUM (tdep) + ir.rm))
7746 record_full_arch_list_add_reg (ir.regcache,
7747 I387_XMM0_REGNUM (tdep) + ir.rm);
7769 if (i386_record_lea_modrm (&ir))
7774 case 0x0f2b: /* movntps */
7775 case 0x660f2b: /* movntpd */
7776 case 0x0fe7: /* movntq */
7777 case 0x660fe7: /* movntdq */
7780 if (opcode == 0x0fe7)
7784 if (i386_record_lea_modrm (&ir))
7788 case 0xf30f2c: /* cvttss2si */
7789 case 0xf20f2c: /* cvttsd2si */
7790 case 0xf30f2d: /* cvtss2si */
7791 case 0xf20f2d: /* cvtsd2si */
7792 case 0xf20f38f0: /* crc32 */
7793 case 0xf20f38f1: /* crc32 */
7794 case 0x0f50: /* movmskps */
7795 case 0x660f50: /* movmskpd */
7796 case 0x0fc5: /* pextrw */
7797 case 0x660fc5: /* pextrw */
7798 case 0x0fd7: /* pmovmskb */
7799 case 0x660fd7: /* pmovmskb */
7800 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7803 case 0x0f3800: /* pshufb */
7804 case 0x0f3801: /* phaddw */
7805 case 0x0f3802: /* phaddd */
7806 case 0x0f3803: /* phaddsw */
7807 case 0x0f3804: /* pmaddubsw */
7808 case 0x0f3805: /* phsubw */
7809 case 0x0f3806: /* phsubd */
7810 case 0x0f3807: /* phsubsw */
7811 case 0x0f3808: /* psignb */
7812 case 0x0f3809: /* psignw */
7813 case 0x0f380a: /* psignd */
7814 case 0x0f380b: /* pmulhrsw */
7815 case 0x0f381c: /* pabsb */
7816 case 0x0f381d: /* pabsw */
7817 case 0x0f381e: /* pabsd */
7818 case 0x0f382b: /* packusdw */
7819 case 0x0f3830: /* pmovzxbw */
7820 case 0x0f3831: /* pmovzxbd */
7821 case 0x0f3832: /* pmovzxbq */
7822 case 0x0f3833: /* pmovzxwd */
7823 case 0x0f3834: /* pmovzxwq */
7824 case 0x0f3835: /* pmovzxdq */
7825 case 0x0f3837: /* pcmpgtq */
7826 case 0x0f3838: /* pminsb */
7827 case 0x0f3839: /* pminsd */
7828 case 0x0f383a: /* pminuw */
7829 case 0x0f383b: /* pminud */
7830 case 0x0f383c: /* pmaxsb */
7831 case 0x0f383d: /* pmaxsd */
7832 case 0x0f383e: /* pmaxuw */
7833 case 0x0f383f: /* pmaxud */
7834 case 0x0f3840: /* pmulld */
7835 case 0x0f3841: /* phminposuw */
7836 case 0x0f3a0f: /* palignr */
7837 case 0x0f60: /* punpcklbw */
7838 case 0x0f61: /* punpcklwd */
7839 case 0x0f62: /* punpckldq */
7840 case 0x0f63: /* packsswb */
7841 case 0x0f64: /* pcmpgtb */
7842 case 0x0f65: /* pcmpgtw */
7843 case 0x0f66: /* pcmpgtd */
7844 case 0x0f67: /* packuswb */
7845 case 0x0f68: /* punpckhbw */
7846 case 0x0f69: /* punpckhwd */
7847 case 0x0f6a: /* punpckhdq */
7848 case 0x0f6b: /* packssdw */
7849 case 0x0f6e: /* movd */
7850 case 0x0f6f: /* movq */
7851 case 0x0f70: /* pshufw */
7852 case 0x0f74: /* pcmpeqb */
7853 case 0x0f75: /* pcmpeqw */
7854 case 0x0f76: /* pcmpeqd */
7855 case 0x0fc4: /* pinsrw */
7856 case 0x0fd1: /* psrlw */
7857 case 0x0fd2: /* psrld */
7858 case 0x0fd3: /* psrlq */
7859 case 0x0fd4: /* paddq */
7860 case 0x0fd5: /* pmullw */
7861 case 0xf20fd6: /* movdq2q */
7862 case 0x0fd8: /* psubusb */
7863 case 0x0fd9: /* psubusw */
7864 case 0x0fda: /* pminub */
7865 case 0x0fdb: /* pand */
7866 case 0x0fdc: /* paddusb */
7867 case 0x0fdd: /* paddusw */
7868 case 0x0fde: /* pmaxub */
7869 case 0x0fdf: /* pandn */
7870 case 0x0fe0: /* pavgb */
7871 case 0x0fe1: /* psraw */
7872 case 0x0fe2: /* psrad */
7873 case 0x0fe3: /* pavgw */
7874 case 0x0fe4: /* pmulhuw */
7875 case 0x0fe5: /* pmulhw */
7876 case 0x0fe8: /* psubsb */
7877 case 0x0fe9: /* psubsw */
7878 case 0x0fea: /* pminsw */
7879 case 0x0feb: /* por */
7880 case 0x0fec: /* paddsb */
7881 case 0x0fed: /* paddsw */
7882 case 0x0fee: /* pmaxsw */
7883 case 0x0fef: /* pxor */
7884 case 0x0ff1: /* psllw */
7885 case 0x0ff2: /* pslld */
7886 case 0x0ff3: /* psllq */
7887 case 0x0ff4: /* pmuludq */
7888 case 0x0ff5: /* pmaddwd */
7889 case 0x0ff6: /* psadbw */
7890 case 0x0ff8: /* psubb */
7891 case 0x0ff9: /* psubw */
7892 case 0x0ffa: /* psubd */
7893 case 0x0ffb: /* psubq */
7894 case 0x0ffc: /* paddb */
7895 case 0x0ffd: /* paddw */
7896 case 0x0ffe: /* paddd */
7897 if (i386_record_modrm (&ir))
7899 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7901 record_full_arch_list_add_reg (ir.regcache,
7902 I387_MM0_REGNUM (tdep) + ir.reg);
7905 case 0x0f71: /* psllw */
7906 case 0x0f72: /* pslld */
7907 case 0x0f73: /* psllq */
7908 if (i386_record_modrm (&ir))
7910 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7912 record_full_arch_list_add_reg (ir.regcache,
7913 I387_MM0_REGNUM (tdep) + ir.rm);
7916 case 0x660f71: /* psllw */
7917 case 0x660f72: /* pslld */
7918 case 0x660f73: /* psllq */
7919 if (i386_record_modrm (&ir))
7922 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7924 record_full_arch_list_add_reg (ir.regcache,
7925 I387_XMM0_REGNUM (tdep) + ir.rm);
7928 case 0x0f7e: /* movd */
7929 case 0x660f7e: /* movd */
7930 if (i386_record_modrm (&ir))
7933 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7940 if (i386_record_lea_modrm (&ir))
7945 case 0x0f7f: /* movq */
7946 if (i386_record_modrm (&ir))
7950 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7952 record_full_arch_list_add_reg (ir.regcache,
7953 I387_MM0_REGNUM (tdep) + ir.rm);
7958 if (i386_record_lea_modrm (&ir))
7963 case 0xf30fb8: /* popcnt */
7964 if (i386_record_modrm (&ir))
7966 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
7967 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7970 case 0x660fd6: /* movq */
7971 if (i386_record_modrm (&ir))
7976 if (!i386_xmm_regnum_p (gdbarch,
7977 I387_XMM0_REGNUM (tdep) + ir.rm))
7979 record_full_arch_list_add_reg (ir.regcache,
7980 I387_XMM0_REGNUM (tdep) + ir.rm);
7985 if (i386_record_lea_modrm (&ir))
7990 case 0x660f3817: /* ptest */
7991 case 0x0f2e: /* ucomiss */
7992 case 0x660f2e: /* ucomisd */
7993 case 0x0f2f: /* comiss */
7994 case 0x660f2f: /* comisd */
7995 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7998 case 0x0ff7: /* maskmovq */
7999 regcache_raw_read_unsigned (ir.regcache,
8000 ir.regmap[X86_RECORD_REDI_REGNUM],
8002 if (record_full_arch_list_add_mem (addr, 64))
8006 case 0x660ff7: /* maskmovdqu */
8007 regcache_raw_read_unsigned (ir.regcache,
8008 ir.regmap[X86_RECORD_REDI_REGNUM],
8010 if (record_full_arch_list_add_mem (addr, 128))
8025 /* In the future, maybe still need to deal with need_dasm. */
8026 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8027 if (record_full_arch_list_add_end ())
8033 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8034 "at address %s.\n"),
8035 (unsigned int) (opcode),
8036 paddress (gdbarch, ir.orig_addr));
8040 static const int i386_record_regmap[] =
8042 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8043 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8044 0, 0, 0, 0, 0, 0, 0, 0,
8045 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8046 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8049 /* Check that the given address appears suitable for a fast
8050 tracepoint, which on x86-64 means that we need an instruction of at
8051 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8052 jump and not have to worry about program jumps to an address in the
8053 middle of the tracepoint jump. On x86, it may be possible to use
8054 4-byte jumps with a 2-byte offset to a trampoline located in the
8055 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8056 of instruction to replace, and 0 if not, plus an explanatory
8060 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8064 static struct ui_file *gdb_null = NULL;
8066 /* Ask the target for the minimum instruction length supported. */
8067 jumplen = target_get_min_fast_tracepoint_insn_len ();
8071 /* If the target does not support the get_min_fast_tracepoint_insn_len
8072 operation, assume that fast tracepoints will always be implemented
8073 using 4-byte relative jumps on both x86 and x86-64. */
8076 else if (jumplen == 0)
8078 /* If the target does support get_min_fast_tracepoint_insn_len but
8079 returns zero, then the IPA has not loaded yet. In this case,
8080 we optimistically assume that truncated 2-byte relative jumps
8081 will be available on x86, and compensate later if this assumption
8082 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8083 jumps will always be used. */
8084 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8087 /* Dummy file descriptor for the disassembler. */
8089 gdb_null = ui_file_new ();
8091 /* Check for fit. */
8092 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8096 /* Return a bit of target-specific detail to add to the caller's
8097 generic failure message. */
8099 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8100 "need at least %d bytes for the jump"),
8113 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8114 struct tdesc_arch_data *tdesc_data)
8116 const struct target_desc *tdesc = tdep->tdesc;
8117 const struct tdesc_feature *feature_core;
8119 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8121 int i, num_regs, valid_p;
8123 if (! tdesc_has_registers (tdesc))
8126 /* Get core registers. */
8127 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8128 if (feature_core == NULL)
8131 /* Get SSE registers. */
8132 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8134 /* Try AVX registers. */
8135 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8137 /* Try MPX registers. */
8138 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8140 /* Try AVX512 registers. */
8141 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8145 /* The XCR0 bits. */
8148 /* AVX512 register description requires AVX register description. */
8152 tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK;
8154 /* It may have been set by OSABI initialization function. */
8155 if (tdep->k0_regnum < 0)
8157 tdep->k_register_names = i386_k_names;
8158 tdep->k0_regnum = I386_K0_REGNUM;
8161 for (i = 0; i < I387_NUM_K_REGS; i++)
8162 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8163 tdep->k0_regnum + i,
8166 if (tdep->num_zmm_regs == 0)
8168 tdep->zmmh_register_names = i386_zmmh_names;
8169 tdep->num_zmm_regs = 8;
8170 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8173 for (i = 0; i < tdep->num_zmm_regs; i++)
8174 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8175 tdep->zmm0h_regnum + i,
8176 tdep->zmmh_register_names[i]);
8178 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8179 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8180 tdep->xmm16_regnum + i,
8181 tdep->xmm_avx512_register_names[i]);
8183 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8184 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8185 tdep->ymm16h_regnum + i,
8186 tdep->ymm16h_register_names[i]);
8190 /* AVX register description requires SSE register description. */
8194 if (!feature_avx512)
8195 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8197 /* It may have been set by OSABI initialization function. */
8198 if (tdep->num_ymm_regs == 0)
8200 tdep->ymmh_register_names = i386_ymmh_names;
8201 tdep->num_ymm_regs = 8;
8202 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8205 for (i = 0; i < tdep->num_ymm_regs; i++)
8206 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8207 tdep->ymm0h_regnum + i,
8208 tdep->ymmh_register_names[i]);
8210 else if (feature_sse)
8211 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8214 tdep->xcr0 = X86_XSTATE_X87_MASK;
8215 tdep->num_xmm_regs = 0;
8218 num_regs = tdep->num_core_regs;
8219 for (i = 0; i < num_regs; i++)
8220 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8221 tdep->register_names[i]);
8225 /* Need to include %mxcsr, so add one. */
8226 num_regs += tdep->num_xmm_regs + 1;
8227 for (; i < num_regs; i++)
8228 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8229 tdep->register_names[i]);
8234 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8236 if (tdep->bnd0r_regnum < 0)
8238 tdep->mpx_register_names = i386_mpx_names;
8239 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8240 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8243 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8244 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8245 I387_BND0R_REGNUM (tdep) + i,
8246 tdep->mpx_register_names[i]);
8253 static struct gdbarch *
8254 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8256 struct gdbarch_tdep *tdep;
8257 struct gdbarch *gdbarch;
8258 struct tdesc_arch_data *tdesc_data;
8259 const struct target_desc *tdesc;
8267 /* If there is already a candidate, use it. */
8268 arches = gdbarch_list_lookup_by_info (arches, &info);
8270 return arches->gdbarch;
8272 /* Allocate space for the new architecture. */
8273 tdep = XCNEW (struct gdbarch_tdep);
8274 gdbarch = gdbarch_alloc (&info, tdep);
8276 /* General-purpose registers. */
8277 tdep->gregset_reg_offset = NULL;
8278 tdep->gregset_num_regs = I386_NUM_GREGS;
8279 tdep->sizeof_gregset = 0;
8281 /* Floating-point registers. */
8282 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8283 tdep->fpregset = &i386_fpregset;
8285 /* The default settings include the FPU registers, the MMX registers
8286 and the SSE registers. This can be overridden for a specific ABI
8287 by adjusting the members `st0_regnum', `mm0_regnum' and
8288 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8289 will show up in the output of "info all-registers". */
8291 tdep->st0_regnum = I386_ST0_REGNUM;
8293 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8294 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8296 tdep->jb_pc_offset = -1;
8297 tdep->struct_return = pcc_struct_return;
8298 tdep->sigtramp_start = 0;
8299 tdep->sigtramp_end = 0;
8300 tdep->sigtramp_p = i386_sigtramp_p;
8301 tdep->sigcontext_addr = NULL;
8302 tdep->sc_reg_offset = NULL;
8303 tdep->sc_pc_offset = -1;
8304 tdep->sc_sp_offset = -1;
8306 tdep->xsave_xcr0_offset = -1;
8308 tdep->record_regmap = i386_record_regmap;
8310 set_gdbarch_long_long_align_bit (gdbarch, 32);
8312 /* The format used for `long double' on almost all i386 targets is
8313 the i387 extended floating-point format. In fact, of all targets
8314 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8315 on having a `long double' that's not `long' at all. */
8316 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8318 /* Although the i387 extended floating-point has only 80 significant
8319 bits, a `long double' actually takes up 96, probably to enforce
8321 set_gdbarch_long_double_bit (gdbarch, 96);
8323 /* Register numbers of various important registers. */
8324 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8325 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8326 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8327 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8329 /* NOTE: kettenis/20040418: GCC does have two possible register
8330 numbering schemes on the i386: dbx and SVR4. These schemes
8331 differ in how they number %ebp, %esp, %eflags, and the
8332 floating-point registers, and are implemented by the arrays
8333 dbx_register_map[] and svr4_dbx_register_map in
8334 gcc/config/i386.c. GCC also defines a third numbering scheme in
8335 gcc/config/i386.c, which it designates as the "default" register
8336 map used in 64bit mode. This last register numbering scheme is
8337 implemented in dbx64_register_map, and is used for AMD64; see
8340 Currently, each GCC i386 target always uses the same register
8341 numbering scheme across all its supported debugging formats
8342 i.e. SDB (COFF), stabs and DWARF 2. This is because
8343 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8344 DBX_REGISTER_NUMBER macro which is defined by each target's
8345 respective config header in a manner independent of the requested
8346 output debugging format.
8348 This does not match the arrangement below, which presumes that
8349 the SDB and stabs numbering schemes differ from the DWARF and
8350 DWARF 2 ones. The reason for this arrangement is that it is
8351 likely to get the numbering scheme for the target's
8352 default/native debug format right. For targets where GCC is the
8353 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8354 targets where the native toolchain uses a different numbering
8355 scheme for a particular debug format (stabs-in-ELF on Solaris)
8356 the defaults below will have to be overridden, like
8357 i386_elf_init_abi() does. */
8359 /* Use the dbx register numbering scheme for stabs and COFF. */
8360 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8361 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8363 /* Use the SVR4 register numbering scheme for DWARF 2. */
8364 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8366 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8367 be in use on any of the supported i386 targets. */
8369 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8371 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8373 /* Call dummy code. */
8374 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8375 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8376 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8377 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8379 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8380 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8381 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8383 set_gdbarch_return_value (gdbarch, i386_return_value);
8385 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8387 /* Stack grows downward. */
8388 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8390 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
8391 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8392 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8394 set_gdbarch_frame_args_skip (gdbarch, 8);
8396 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8398 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8400 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8402 /* Add the i386 register groups. */
8403 i386_add_reggroups (gdbarch);
8404 tdep->register_reggroup_p = i386_register_reggroup_p;
8406 /* Helper for function argument information. */
8407 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8409 /* Hook the function epilogue frame unwinder. This unwinder is
8410 appended to the list first, so that it supercedes the DWARF
8411 unwinder in function epilogues (where the DWARF unwinder
8412 currently fails). */
8413 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8415 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8416 to the list before the prologue-based unwinders, so that DWARF
8417 CFI info will be used if it is available. */
8418 dwarf2_append_unwinders (gdbarch);
8420 frame_base_set_default (gdbarch, &i386_frame_base);
8422 /* Pseudo registers may be changed by amd64_init_abi. */
8423 set_gdbarch_pseudo_register_read_value (gdbarch,
8424 i386_pseudo_register_read_value);
8425 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8427 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8428 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8430 /* Override the normal target description method to make the AVX
8431 upper halves anonymous. */
8432 set_gdbarch_register_name (gdbarch, i386_register_name);
8434 /* Even though the default ABI only includes general-purpose registers,
8435 floating-point registers and the SSE registers, we have to leave a
8436 gap for the upper AVX, MPX and AVX512 registers. */
8437 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8439 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8441 /* Get the x86 target description from INFO. */
8442 tdesc = info.target_desc;
8443 if (! tdesc_has_registers (tdesc))
8445 tdep->tdesc = tdesc;
8447 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8448 tdep->register_names = i386_register_names;
8450 /* No upper YMM registers. */
8451 tdep->ymmh_register_names = NULL;
8452 tdep->ymm0h_regnum = -1;
8454 /* No upper ZMM registers. */
8455 tdep->zmmh_register_names = NULL;
8456 tdep->zmm0h_regnum = -1;
8458 /* No high XMM registers. */
8459 tdep->xmm_avx512_register_names = NULL;
8460 tdep->xmm16_regnum = -1;
8462 /* No upper YMM16-31 registers. */
8463 tdep->ymm16h_register_names = NULL;
8464 tdep->ymm16h_regnum = -1;
8466 tdep->num_byte_regs = 8;
8467 tdep->num_word_regs = 8;
8468 tdep->num_dword_regs = 0;
8469 tdep->num_mmx_regs = 8;
8470 tdep->num_ymm_regs = 0;
8472 /* No MPX registers. */
8473 tdep->bnd0r_regnum = -1;
8474 tdep->bndcfgu_regnum = -1;
8476 /* No AVX512 registers. */
8477 tdep->k0_regnum = -1;
8478 tdep->num_zmm_regs = 0;
8479 tdep->num_ymm_avx512_regs = 0;
8480 tdep->num_xmm_avx512_regs = 0;
8482 tdesc_data = tdesc_data_alloc ();
8484 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8486 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8488 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8489 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8490 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8492 /* Hook in ABI-specific overrides, if they have been registered. */
8493 info.tdep_info = tdesc_data;
8494 gdbarch_init_osabi (info, gdbarch);
8496 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8498 tdesc_data_cleanup (tdesc_data);
8500 gdbarch_free (gdbarch);
8504 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8506 /* Wire in pseudo registers. Number of pseudo registers may be
8508 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8509 + tdep->num_word_regs
8510 + tdep->num_dword_regs
8511 + tdep->num_mmx_regs
8512 + tdep->num_ymm_regs
8514 + tdep->num_ymm_avx512_regs
8515 + tdep->num_zmm_regs));
8517 /* Target description may be changed. */
8518 tdesc = tdep->tdesc;
8520 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8522 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8523 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8525 /* Make %al the first pseudo-register. */
8526 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8527 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8529 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8530 if (tdep->num_dword_regs)
8532 /* Support dword pseudo-register if it hasn't been disabled. */
8533 tdep->eax_regnum = ymm0_regnum;
8534 ymm0_regnum += tdep->num_dword_regs;
8537 tdep->eax_regnum = -1;
8539 mm0_regnum = ymm0_regnum;
8540 if (tdep->num_ymm_regs)
8542 /* Support YMM pseudo-register if it is available. */
8543 tdep->ymm0_regnum = ymm0_regnum;
8544 mm0_regnum += tdep->num_ymm_regs;
8547 tdep->ymm0_regnum = -1;
8549 if (tdep->num_ymm_avx512_regs)
8551 /* Support YMM16-31 pseudo registers if available. */
8552 tdep->ymm16_regnum = mm0_regnum;
8553 mm0_regnum += tdep->num_ymm_avx512_regs;
8556 tdep->ymm16_regnum = -1;
8558 if (tdep->num_zmm_regs)
8560 /* Support ZMM pseudo-register if it is available. */
8561 tdep->zmm0_regnum = mm0_regnum;
8562 mm0_regnum += tdep->num_zmm_regs;
8565 tdep->zmm0_regnum = -1;
8567 bnd0_regnum = mm0_regnum;
8568 if (tdep->num_mmx_regs != 0)
8570 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8571 tdep->mm0_regnum = mm0_regnum;
8572 bnd0_regnum += tdep->num_mmx_regs;
8575 tdep->mm0_regnum = -1;
8577 if (tdep->bnd0r_regnum > 0)
8578 tdep->bnd0_regnum = bnd0_regnum;
8580 tdep-> bnd0_regnum = -1;
8582 /* Hook in the legacy prologue-based unwinders last (fallback). */
8583 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8584 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8585 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8587 /* If we have a register mapping, enable the generic core file
8588 support, unless it has already been enabled. */
8589 if (tdep->gregset_reg_offset
8590 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8591 set_gdbarch_iterate_over_regset_sections
8592 (gdbarch, i386_iterate_over_regset_sections);
8594 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8595 i386_fast_tracepoint_valid_at);
8600 static enum gdb_osabi
8601 i386_coff_osabi_sniffer (bfd *abfd)
8603 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8604 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8605 return GDB_OSABI_GO32;
8607 return GDB_OSABI_UNKNOWN;
8611 /* Return the target description for a specified XSAVE feature mask. */
8613 const struct target_desc *
8614 i386_target_description (uint64_t xcr0)
8616 switch (xcr0 & X86_XSTATE_ALL_MASK)
8618 case X86_XSTATE_MPX_AVX512_MASK:
8619 case X86_XSTATE_AVX512_MASK:
8620 return tdesc_i386_avx512;
8621 case X86_XSTATE_MPX_MASK:
8622 return tdesc_i386_mpx;
8623 case X86_XSTATE_AVX_MASK:
8624 return tdesc_i386_avx;
8630 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8632 /* Find the bound directory base address. */
8634 static unsigned long
8635 i386_mpx_bd_base (void)
8637 struct regcache *rcache;
8638 struct gdbarch_tdep *tdep;
8640 enum register_status regstatus;
8641 struct gdb_exception except;
8643 rcache = get_current_regcache ();
8644 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8646 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8648 if (regstatus != REG_VALID)
8649 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8651 return ret & MPX_BASE_MASK;
8654 /* Check if the current target is MPX enabled. */
8657 i386_mpx_enabled (void)
8659 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8660 const struct target_desc *tdesc = tdep->tdesc;
8662 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8665 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8666 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8667 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8668 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8670 /* Find the bound table entry given the pointer location and the base
8671 address of the table. */
8674 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8678 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8679 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8680 CORE_ADDR bd_entry_addr;
8683 struct gdbarch *gdbarch = get_current_arch ();
8684 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8687 if (gdbarch_ptr_bit (gdbarch) == 64)
8689 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8690 bd_ptr_r_shift = 20;
8692 bt_select_r_shift = 3;
8693 bt_select_l_shift = 5;
8694 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8696 if ( sizeof (CORE_ADDR) == 4)
8697 error (_("bound table examination not supported\
8698 for 64-bit process with 32-bit GDB"));
8702 mpx_bd_mask = MPX_BD_MASK_32;
8703 bd_ptr_r_shift = 12;
8705 bt_select_r_shift = 2;
8706 bt_select_l_shift = 4;
8707 bt_mask = MPX_BT_MASK_32;
8710 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8711 bd_entry_addr = bd_base + offset1;
8712 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8714 if ((bd_entry & 0x1) == 0)
8715 error (_("Invalid bounds directory entry at %s."),
8716 paddress (get_current_arch (), bd_entry_addr));
8718 /* Clearing status bit. */
8720 bt_addr = bd_entry & ~bt_select_r_shift;
8721 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8723 return bt_addr + offset2;
8726 /* Print routine for the mpx bounds. */
8729 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8731 struct ui_out *uiout = current_uiout;
8733 struct gdbarch *gdbarch = get_current_arch ();
8734 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8735 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8737 if (bounds_in_map == 1)
8739 ui_out_text (uiout, "Null bounds on map:");
8740 ui_out_text (uiout, " pointer value = ");
8741 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8742 ui_out_text (uiout, ".");
8743 ui_out_text (uiout, "\n");
8747 ui_out_text (uiout, "{lbound = ");
8748 ui_out_field_core_addr (uiout, "lower-bound", gdbarch, bt_entry[0]);
8749 ui_out_text (uiout, ", ubound = ");
8751 /* The upper bound is stored in 1's complement. */
8752 ui_out_field_core_addr (uiout, "upper-bound", gdbarch, ~bt_entry[1]);
8753 ui_out_text (uiout, "}: pointer value = ");
8754 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8756 if (gdbarch_ptr_bit (gdbarch) == 64)
8757 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8759 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8761 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8762 -1 represents in this sense full memory access, and there is no need
8765 size = (size > -1 ? size + 1 : size);
8766 ui_out_text (uiout, ", size = ");
8767 ui_out_field_fmt (uiout, "size", "%s", plongest (size));
8769 ui_out_text (uiout, ", metadata = ");
8770 ui_out_field_core_addr (uiout, "metadata", gdbarch, bt_entry[3]);
8771 ui_out_text (uiout, "\n");
8775 /* Implement the command "show mpx bound". */
8778 i386_mpx_info_bounds (char *args, int from_tty)
8780 CORE_ADDR bd_base = 0;
8782 CORE_ADDR bt_entry_addr = 0;
8783 CORE_ADDR bt_entry[4];
8785 struct gdbarch *gdbarch = get_current_arch ();
8786 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8788 if (!i386_mpx_enabled ())
8790 printf_unfiltered (_("Intel(R) Memory Protection Extensions not "
8791 "supported on this target.\n"));
8797 printf_unfiltered (_("Address of pointer variable expected.\n"));
8801 addr = parse_and_eval_address (args);
8803 bd_base = i386_mpx_bd_base ();
8804 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8806 memset (bt_entry, 0, sizeof (bt_entry));
8808 for (i = 0; i < 4; i++)
8809 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8810 + i * data_ptr_type->length,
8813 i386_mpx_print_bounds (bt_entry);
8816 /* Implement the command "set mpx bound". */
8819 i386_mpx_set_bounds (char *args, int from_tty)
8821 CORE_ADDR bd_base = 0;
8822 CORE_ADDR addr, lower, upper;
8823 CORE_ADDR bt_entry_addr = 0;
8824 CORE_ADDR bt_entry[2];
8825 const char *input = args;
8827 struct gdbarch *gdbarch = get_current_arch ();
8828 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8829 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8831 if (!i386_mpx_enabled ())
8832 error (_("Intel(R) Memory Protection Extensions not supported\
8836 error (_("Pointer value expected."));
8838 addr = value_as_address (parse_to_comma_and_eval (&input));
8840 if (input[0] == ',')
8842 if (input[0] == '\0')
8843 error (_("wrong number of arguments: missing lower and upper bound."));
8844 lower = value_as_address (parse_to_comma_and_eval (&input));
8846 if (input[0] == ',')
8848 if (input[0] == '\0')
8849 error (_("Wrong number of arguments; Missing upper bound."));
8850 upper = value_as_address (parse_to_comma_and_eval (&input));
8852 bd_base = i386_mpx_bd_base ();
8853 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8854 for (i = 0; i < 2; i++)
8855 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8856 + i * data_ptr_type->length,
8858 bt_entry[0] = (uint64_t) lower;
8859 bt_entry[1] = ~(uint64_t) upper;
8861 for (i = 0; i < 2; i++)
8862 write_memory_unsigned_integer (bt_entry_addr + i * data_ptr_type->length,
8863 data_ptr_type->length, byte_order,
8867 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
8869 /* Helper function for the CLI commands. */
8872 set_mpx_cmd (char *args, int from_tty)
8874 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
8877 /* Helper function for the CLI commands. */
8880 show_mpx_cmd (char *args, int from_tty)
8882 cmd_show_list (mpx_show_cmdlist, from_tty, "");
8885 /* Provide a prototype to silence -Wmissing-prototypes. */
8886 void _initialize_i386_tdep (void);
8889 _initialize_i386_tdep (void)
8891 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8893 /* Add the variable that controls the disassembly flavor. */
8894 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8895 &disassembly_flavor, _("\
8896 Set the disassembly flavor."), _("\
8897 Show the disassembly flavor."), _("\
8898 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8900 NULL, /* FIXME: i18n: */
8901 &setlist, &showlist);
8903 /* Add the variable that controls the convention for returning
8905 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8906 &struct_convention, _("\
8907 Set the convention for returning small structs."), _("\
8908 Show the convention for returning small structs."), _("\
8909 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8912 NULL, /* FIXME: i18n: */
8913 &setlist, &showlist);
8915 /* Add "mpx" prefix for the set commands. */
8917 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
8918 Set Intel(R) Memory Protection Extensions specific variables."),
8919 &mpx_set_cmdlist, "set mpx ",
8920 0 /* allow-unknown */, &setlist);
8922 /* Add "mpx" prefix for the show commands. */
8924 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
8925 Show Intel(R) Memory Protection Extensions specific variables."),
8926 &mpx_show_cmdlist, "show mpx ",
8927 0 /* allow-unknown */, &showlist);
8929 /* Add "bound" command for the show mpx commands list. */
8931 add_cmd ("bound", no_class, i386_mpx_info_bounds,
8932 "Show the memory bounds for a given array/pointer storage\
8933 in the bound table.",
8936 /* Add "bound" command for the set mpx commands list. */
8938 add_cmd ("bound", no_class, i386_mpx_set_bounds,
8939 "Set the memory bounds for a given array/pointer storage\
8940 in the bound table.",
8943 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
8944 i386_coff_osabi_sniffer);
8946 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8947 i386_svr4_init_abi);
8948 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8949 i386_go32_init_abi);
8951 /* Initialize the i386-specific register groups. */
8952 i386_init_reggroups ();
8954 /* Initialize the standard target descriptions. */
8955 initialize_tdesc_i386 ();
8956 initialize_tdesc_i386_mmx ();
8957 initialize_tdesc_i386_avx ();
8958 initialize_tdesc_i386_mpx ();
8959 initialize_tdesc_i386_avx512 ();
8961 /* Tell remote stub that we support XML target description. */
8962 register_remote_support_xml ("i386");