1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "target-descriptions.h"
54 #include "arch/i386.h"
59 #include "stap-probe.h"
60 #include "user-regs.h"
61 #include "cli/cli-utils.h"
62 #include "expression.h"
63 #include "parser-defs.h"
69 static const char *i386_register_names[] =
71 "eax", "ecx", "edx", "ebx",
72 "esp", "ebp", "esi", "edi",
73 "eip", "eflags", "cs", "ss",
74 "ds", "es", "fs", "gs",
75 "st0", "st1", "st2", "st3",
76 "st4", "st5", "st6", "st7",
77 "fctrl", "fstat", "ftag", "fiseg",
78 "fioff", "foseg", "fooff", "fop",
79 "xmm0", "xmm1", "xmm2", "xmm3",
80 "xmm4", "xmm5", "xmm6", "xmm7",
84 static const char *i386_zmm_names[] =
86 "zmm0", "zmm1", "zmm2", "zmm3",
87 "zmm4", "zmm5", "zmm6", "zmm7"
90 static const char *i386_zmmh_names[] =
92 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
93 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
96 static const char *i386_k_names[] =
98 "k0", "k1", "k2", "k3",
99 "k4", "k5", "k6", "k7"
102 static const char *i386_ymm_names[] =
104 "ymm0", "ymm1", "ymm2", "ymm3",
105 "ymm4", "ymm5", "ymm6", "ymm7",
108 static const char *i386_ymmh_names[] =
110 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
111 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
114 static const char *i386_mpx_names[] =
116 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
119 static const char* i386_pkeys_names[] =
124 /* Register names for MPX pseudo-registers. */
126 static const char *i386_bnd_names[] =
128 "bnd0", "bnd1", "bnd2", "bnd3"
131 /* Register names for MMX pseudo-registers. */
133 static const char *i386_mmx_names[] =
135 "mm0", "mm1", "mm2", "mm3",
136 "mm4", "mm5", "mm6", "mm7"
139 /* Register names for byte pseudo-registers. */
141 static const char *i386_byte_names[] =
143 "al", "cl", "dl", "bl",
144 "ah", "ch", "dh", "bh"
147 /* Register names for word pseudo-registers. */
149 static const char *i386_word_names[] =
151 "ax", "cx", "dx", "bx",
155 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
156 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
157 we have 16 upper ZMM regs that have to be handled differently. */
159 const int num_lower_zmm_regs = 16;
164 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
167 int mm0_regnum = tdep->mm0_regnum;
172 regnum -= mm0_regnum;
173 return regnum >= 0 && regnum < tdep->num_mmx_regs;
179 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
181 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
183 regnum -= tdep->al_regnum;
184 return regnum >= 0 && regnum < tdep->num_byte_regs;
190 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
192 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
194 regnum -= tdep->ax_regnum;
195 return regnum >= 0 && regnum < tdep->num_word_regs;
198 /* Dword register? */
201 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
203 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
204 int eax_regnum = tdep->eax_regnum;
209 regnum -= eax_regnum;
210 return regnum >= 0 && regnum < tdep->num_dword_regs;
213 /* AVX512 register? */
216 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
218 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
219 int zmm0h_regnum = tdep->zmm0h_regnum;
221 if (zmm0h_regnum < 0)
224 regnum -= zmm0h_regnum;
225 return regnum >= 0 && regnum < tdep->num_zmm_regs;
229 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
231 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
232 int zmm0_regnum = tdep->zmm0_regnum;
237 regnum -= zmm0_regnum;
238 return regnum >= 0 && regnum < tdep->num_zmm_regs;
242 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
245 int k0_regnum = tdep->k0_regnum;
251 return regnum >= 0 && regnum < I387_NUM_K_REGS;
255 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
257 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
258 int ymm0h_regnum = tdep->ymm0h_regnum;
260 if (ymm0h_regnum < 0)
263 regnum -= ymm0h_regnum;
264 return regnum >= 0 && regnum < tdep->num_ymm_regs;
270 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
272 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
273 int ymm0_regnum = tdep->ymm0_regnum;
278 regnum -= ymm0_regnum;
279 return regnum >= 0 && regnum < tdep->num_ymm_regs;
283 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
286 int ymm16h_regnum = tdep->ymm16h_regnum;
288 if (ymm16h_regnum < 0)
291 regnum -= ymm16h_regnum;
292 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
296 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
298 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
299 int ymm16_regnum = tdep->ymm16_regnum;
301 if (ymm16_regnum < 0)
304 regnum -= ymm16_regnum;
305 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
311 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
313 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
314 int bnd0_regnum = tdep->bnd0_regnum;
319 regnum -= bnd0_regnum;
320 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
326 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
328 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
329 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
331 if (num_xmm_regs == 0)
334 regnum -= I387_XMM0_REGNUM (tdep);
335 return regnum >= 0 && regnum < num_xmm_regs;
338 /* XMM_512 register? */
341 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
343 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
344 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
346 if (num_xmm_avx512_regs == 0)
349 regnum -= I387_XMM16_REGNUM (tdep);
350 return regnum >= 0 && regnum < num_xmm_avx512_regs;
354 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
358 if (I387_NUM_XMM_REGS (tdep) == 0)
361 return (regnum == I387_MXCSR_REGNUM (tdep));
367 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
369 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
371 if (I387_ST0_REGNUM (tdep) < 0)
374 return (I387_ST0_REGNUM (tdep) <= regnum
375 && regnum < I387_FCTRL_REGNUM (tdep));
379 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
381 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
383 if (I387_ST0_REGNUM (tdep) < 0)
386 return (I387_FCTRL_REGNUM (tdep) <= regnum
387 && regnum < I387_XMM0_REGNUM (tdep));
390 /* BNDr (raw) register? */
393 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
395 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
397 if (I387_BND0R_REGNUM (tdep) < 0)
400 regnum -= tdep->bnd0r_regnum;
401 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
404 /* BND control register? */
407 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
409 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
411 if (I387_BNDCFGU_REGNUM (tdep) < 0)
414 regnum -= I387_BNDCFGU_REGNUM (tdep);
415 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
421 i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum)
423 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
424 int pkru_regnum = tdep->pkru_regnum;
429 regnum -= pkru_regnum;
430 return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS;
433 /* Return the name of register REGNUM, or the empty string if it is
434 an anonymous register. */
437 i386_register_name (struct gdbarch *gdbarch, int regnum)
439 /* Hide the upper YMM registers. */
440 if (i386_ymmh_regnum_p (gdbarch, regnum))
443 /* Hide the upper YMM16-31 registers. */
444 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
447 /* Hide the upper ZMM registers. */
448 if (i386_zmmh_regnum_p (gdbarch, regnum))
451 return tdesc_register_name (gdbarch, regnum);
454 /* Return the name of register REGNUM. */
457 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
459 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
460 if (i386_bnd_regnum_p (gdbarch, regnum))
461 return i386_bnd_names[regnum - tdep->bnd0_regnum];
462 if (i386_mmx_regnum_p (gdbarch, regnum))
463 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
464 else if (i386_ymm_regnum_p (gdbarch, regnum))
465 return i386_ymm_names[regnum - tdep->ymm0_regnum];
466 else if (i386_zmm_regnum_p (gdbarch, regnum))
467 return i386_zmm_names[regnum - tdep->zmm0_regnum];
468 else if (i386_byte_regnum_p (gdbarch, regnum))
469 return i386_byte_names[regnum - tdep->al_regnum];
470 else if (i386_word_regnum_p (gdbarch, regnum))
471 return i386_word_names[regnum - tdep->ax_regnum];
473 internal_error (__FILE__, __LINE__, _("invalid regnum"));
476 /* Convert a dbx register number REG to the appropriate register
477 number used by GDB. */
480 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
482 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
484 /* This implements what GCC calls the "default" register map
485 (dbx_register_map[]). */
487 if (reg >= 0 && reg <= 7)
489 /* General-purpose registers. The debug info calls %ebp
490 register 4, and %esp register 5. */
497 else if (reg >= 12 && reg <= 19)
499 /* Floating-point registers. */
500 return reg - 12 + I387_ST0_REGNUM (tdep);
502 else if (reg >= 21 && reg <= 28)
505 int ymm0_regnum = tdep->ymm0_regnum;
508 && i386_xmm_regnum_p (gdbarch, reg))
509 return reg - 21 + ymm0_regnum;
511 return reg - 21 + I387_XMM0_REGNUM (tdep);
513 else if (reg >= 29 && reg <= 36)
516 return reg - 29 + I387_MM0_REGNUM (tdep);
519 /* This will hopefully provoke a warning. */
520 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
523 /* Convert SVR4 DWARF register number REG to the appropriate register number
527 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
529 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
531 /* This implements the GCC register map that tries to be compatible
532 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
534 /* The SVR4 register numbering includes %eip and %eflags, and
535 numbers the floating point registers differently. */
536 if (reg >= 0 && reg <= 9)
538 /* General-purpose registers. */
541 else if (reg >= 11 && reg <= 18)
543 /* Floating-point registers. */
544 return reg - 11 + I387_ST0_REGNUM (tdep);
546 else if (reg >= 21 && reg <= 36)
548 /* The SSE and MMX registers have the same numbers as with dbx. */
549 return i386_dbx_reg_to_regnum (gdbarch, reg);
554 case 37: return I387_FCTRL_REGNUM (tdep);
555 case 38: return I387_FSTAT_REGNUM (tdep);
556 case 39: return I387_MXCSR_REGNUM (tdep);
557 case 40: return I386_ES_REGNUM;
558 case 41: return I386_CS_REGNUM;
559 case 42: return I386_SS_REGNUM;
560 case 43: return I386_DS_REGNUM;
561 case 44: return I386_FS_REGNUM;
562 case 45: return I386_GS_REGNUM;
568 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
569 num_regs + num_pseudo_regs for other debug formats. */
572 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
574 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
577 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
583 /* This is the variable that is set with "set disassembly-flavor", and
584 its legitimate values. */
585 static const char att_flavor[] = "att";
586 static const char intel_flavor[] = "intel";
587 static const char *const valid_flavors[] =
593 static const char *disassembly_flavor = att_flavor;
596 /* Use the program counter to determine the contents and size of a
597 breakpoint instruction. Return a pointer to a string of bytes that
598 encode a breakpoint instruction, store the length of the string in
599 *LEN and optionally adjust *PC to point to the correct memory
600 location for inserting the breakpoint.
602 On the i386 we have a single breakpoint that fits in a single byte
603 and can be inserted anywhere.
605 This function is 64-bit safe. */
607 constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */
609 typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint;
612 /* Displaced instruction handling. */
614 /* Skip the legacy instruction prefixes in INSN.
615 Not all prefixes are valid for any particular insn
616 but we needn't care, the insn will fault if it's invalid.
617 The result is a pointer to the first opcode byte,
618 or NULL if we run off the end of the buffer. */
621 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
623 gdb_byte *end = insn + max_len;
629 case DATA_PREFIX_OPCODE:
630 case ADDR_PREFIX_OPCODE:
631 case CS_PREFIX_OPCODE:
632 case DS_PREFIX_OPCODE:
633 case ES_PREFIX_OPCODE:
634 case FS_PREFIX_OPCODE:
635 case GS_PREFIX_OPCODE:
636 case SS_PREFIX_OPCODE:
637 case LOCK_PREFIX_OPCODE:
638 case REPE_PREFIX_OPCODE:
639 case REPNE_PREFIX_OPCODE:
651 i386_absolute_jmp_p (const gdb_byte *insn)
653 /* jmp far (absolute address in operand). */
659 /* jump near, absolute indirect (/4). */
660 if ((insn[1] & 0x38) == 0x20)
663 /* jump far, absolute indirect (/5). */
664 if ((insn[1] & 0x38) == 0x28)
671 /* Return non-zero if INSN is a jump, zero otherwise. */
674 i386_jmp_p (const gdb_byte *insn)
676 /* jump short, relative. */
680 /* jump near, relative. */
684 return i386_absolute_jmp_p (insn);
688 i386_absolute_call_p (const gdb_byte *insn)
690 /* call far, absolute. */
696 /* Call near, absolute indirect (/2). */
697 if ((insn[1] & 0x38) == 0x10)
700 /* Call far, absolute indirect (/3). */
701 if ((insn[1] & 0x38) == 0x18)
709 i386_ret_p (const gdb_byte *insn)
713 case 0xc2: /* ret near, pop N bytes. */
714 case 0xc3: /* ret near */
715 case 0xca: /* ret far, pop N bytes. */
716 case 0xcb: /* ret far */
717 case 0xcf: /* iret */
726 i386_call_p (const gdb_byte *insn)
728 if (i386_absolute_call_p (insn))
731 /* call near, relative. */
738 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
739 length in bytes. Otherwise, return zero. */
742 i386_syscall_p (const gdb_byte *insn, int *lengthp)
744 /* Is it 'int $0x80'? */
745 if ((insn[0] == 0xcd && insn[1] == 0x80)
746 /* Or is it 'sysenter'? */
747 || (insn[0] == 0x0f && insn[1] == 0x34)
748 /* Or is it 'syscall'? */
749 || (insn[0] == 0x0f && insn[1] == 0x05))
758 /* The gdbarch insn_is_call method. */
761 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
763 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
765 read_code (addr, buf, I386_MAX_INSN_LEN);
766 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
768 return i386_call_p (insn);
771 /* The gdbarch insn_is_ret method. */
774 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
776 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
778 read_code (addr, buf, I386_MAX_INSN_LEN);
779 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
781 return i386_ret_p (insn);
784 /* The gdbarch insn_is_jump method. */
787 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
789 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
791 read_code (addr, buf, I386_MAX_INSN_LEN);
792 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
794 return i386_jmp_p (insn);
797 /* Some kernels may run one past a syscall insn, so we have to cope.
798 Otherwise this is just simple_displaced_step_copy_insn. */
800 struct displaced_step_closure *
801 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
802 CORE_ADDR from, CORE_ADDR to,
803 struct regcache *regs)
805 size_t len = gdbarch_max_insn_length (gdbarch);
806 gdb_byte *buf = (gdb_byte *) xmalloc (len);
808 read_memory (from, buf, len);
810 /* GDB may get control back after the insn after the syscall.
811 Presumably this is a kernel bug.
812 If this is a syscall, make sure there's a nop afterwards. */
817 insn = i386_skip_prefixes (buf, len);
818 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
819 insn[syscall_length] = NOP_OPCODE;
822 write_memory (to, buf, len);
826 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
827 paddress (gdbarch, from), paddress (gdbarch, to));
828 displaced_step_dump_bytes (gdb_stdlog, buf, len);
831 return (struct displaced_step_closure *) buf;
834 /* Fix up the state of registers and memory after having single-stepped
835 a displaced instruction. */
838 i386_displaced_step_fixup (struct gdbarch *gdbarch,
839 struct displaced_step_closure *closure,
840 CORE_ADDR from, CORE_ADDR to,
841 struct regcache *regs)
843 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
845 /* The offset we applied to the instruction's address.
846 This could well be negative (when viewed as a signed 32-bit
847 value), but ULONGEST won't reflect that, so take care when
849 ULONGEST insn_offset = to - from;
851 /* Since we use simple_displaced_step_copy_insn, our closure is a
852 copy of the instruction. */
853 gdb_byte *insn = (gdb_byte *) closure;
854 /* The start of the insn, needed in case we see some prefixes. */
855 gdb_byte *insn_start = insn;
858 fprintf_unfiltered (gdb_stdlog,
859 "displaced: fixup (%s, %s), "
860 "insn = 0x%02x 0x%02x ...\n",
861 paddress (gdbarch, from), paddress (gdbarch, to),
864 /* The list of issues to contend with here is taken from
865 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
866 Yay for Free Software! */
868 /* Relocate the %eip, if necessary. */
870 /* The instruction recognizers we use assume any leading prefixes
871 have been skipped. */
873 /* This is the size of the buffer in closure. */
874 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
875 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
876 /* If there are too many prefixes, just ignore the insn.
877 It will fault when run. */
882 /* Except in the case of absolute or indirect jump or call
883 instructions, or a return instruction, the new eip is relative to
884 the displaced instruction; make it relative. Well, signal
885 handler returns don't need relocation either, but we use the
886 value of %eip to recognize those; see below. */
887 if (! i386_absolute_jmp_p (insn)
888 && ! i386_absolute_call_p (insn)
889 && ! i386_ret_p (insn))
894 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
896 /* A signal trampoline system call changes the %eip, resuming
897 execution of the main program after the signal handler has
898 returned. That makes them like 'return' instructions; we
899 shouldn't relocate %eip.
901 But most system calls don't, and we do need to relocate %eip.
903 Our heuristic for distinguishing these cases: if stepping
904 over the system call instruction left control directly after
905 the instruction, the we relocate --- control almost certainly
906 doesn't belong in the displaced copy. Otherwise, we assume
907 the instruction has put control where it belongs, and leave
908 it unrelocated. Goodness help us if there are PC-relative
910 if (i386_syscall_p (insn, &insn_len)
911 && orig_eip != to + (insn - insn_start) + insn_len
912 /* GDB can get control back after the insn after the syscall.
913 Presumably this is a kernel bug.
914 i386_displaced_step_copy_insn ensures its a nop,
915 we add one to the length for it. */
916 && orig_eip != to + (insn - insn_start) + insn_len + 1)
919 fprintf_unfiltered (gdb_stdlog,
920 "displaced: syscall changed %%eip; "
925 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
927 /* If we just stepped over a breakpoint insn, we don't backup
928 the pc on purpose; this is to match behaviour without
931 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
934 fprintf_unfiltered (gdb_stdlog,
936 "relocated %%eip from %s to %s\n",
937 paddress (gdbarch, orig_eip),
938 paddress (gdbarch, eip));
942 /* If the instruction was PUSHFL, then the TF bit will be set in the
943 pushed value, and should be cleared. We'll leave this for later,
944 since GDB already messes up the TF flag when stepping over a
947 /* If the instruction was a call, the return address now atop the
948 stack is the address following the copied instruction. We need
949 to make it the address following the original instruction. */
950 if (i386_call_p (insn))
954 const ULONGEST retaddr_len = 4;
956 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
957 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
958 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
959 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
962 fprintf_unfiltered (gdb_stdlog,
963 "displaced: relocated return addr at %s to %s\n",
964 paddress (gdbarch, esp),
965 paddress (gdbarch, retaddr));
970 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
972 target_write_memory (*to, buf, len);
977 i386_relocate_instruction (struct gdbarch *gdbarch,
978 CORE_ADDR *to, CORE_ADDR oldloc)
980 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
981 gdb_byte buf[I386_MAX_INSN_LEN];
982 int offset = 0, rel32, newrel;
984 gdb_byte *insn = buf;
986 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
988 insn_length = gdb_buffered_insn_length (gdbarch, insn,
989 I386_MAX_INSN_LEN, oldloc);
991 /* Get past the prefixes. */
992 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
994 /* Adjust calls with 32-bit relative addresses as push/jump, with
995 the address pushed being the location where the original call in
996 the user program would return to. */
999 gdb_byte push_buf[16];
1000 unsigned int ret_addr;
1002 /* Where "ret" in the original code will return to. */
1003 ret_addr = oldloc + insn_length;
1004 push_buf[0] = 0x68; /* pushq $... */
1005 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1006 /* Push the push. */
1007 append_insns (to, 5, push_buf);
1009 /* Convert the relative call to a relative jump. */
1012 /* Adjust the destination offset. */
1013 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1014 newrel = (oldloc - *to) + rel32;
1015 store_signed_integer (insn + 1, 4, byte_order, newrel);
1017 if (debug_displaced)
1018 fprintf_unfiltered (gdb_stdlog,
1019 "Adjusted insn rel32=%s at %s to"
1020 " rel32=%s at %s\n",
1021 hex_string (rel32), paddress (gdbarch, oldloc),
1022 hex_string (newrel), paddress (gdbarch, *to));
1024 /* Write the adjusted jump into its displaced location. */
1025 append_insns (to, 5, insn);
1029 /* Adjust jumps with 32-bit relative addresses. Calls are already
1031 if (insn[0] == 0xe9)
1033 /* Adjust conditional jumps. */
1034 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1039 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1040 newrel = (oldloc - *to) + rel32;
1041 store_signed_integer (insn + offset, 4, byte_order, newrel);
1042 if (debug_displaced)
1043 fprintf_unfiltered (gdb_stdlog,
1044 "Adjusted insn rel32=%s at %s to"
1045 " rel32=%s at %s\n",
1046 hex_string (rel32), paddress (gdbarch, oldloc),
1047 hex_string (newrel), paddress (gdbarch, *to));
1050 /* Write the adjusted instructions into their displaced
1052 append_insns (to, insn_length, buf);
1056 #ifdef I386_REGNO_TO_SYMMETRY
1057 #error "The Sequent Symmetry is no longer supported."
1060 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1061 and %esp "belong" to the calling function. Therefore these
1062 registers should be saved if they're going to be modified. */
1064 /* The maximum number of saved registers. This should include all
1065 registers mentioned above, and %eip. */
1066 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1068 struct i386_frame_cache
1076 /* Saved registers. */
1077 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1082 /* Stack space reserved for local variables. */
1086 /* Allocate and initialize a frame cache. */
1088 static struct i386_frame_cache *
1089 i386_alloc_frame_cache (void)
1091 struct i386_frame_cache *cache;
1094 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1099 cache->sp_offset = -4;
1102 /* Saved registers. We initialize these to -1 since zero is a valid
1103 offset (that's where %ebp is supposed to be stored). */
1104 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1105 cache->saved_regs[i] = -1;
1106 cache->saved_sp = 0;
1107 cache->saved_sp_reg = -1;
1108 cache->pc_in_eax = 0;
1110 /* Frameless until proven otherwise. */
1116 /* If the instruction at PC is a jump, return the address of its
1117 target. Otherwise, return PC. */
1120 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1122 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1127 if (target_read_code (pc, &op, 1))
1134 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1140 /* Relative jump: if data16 == 0, disp32, else disp16. */
1143 delta = read_memory_integer (pc + 2, 2, byte_order);
1145 /* Include the size of the jmp instruction (including the
1151 delta = read_memory_integer (pc + 1, 4, byte_order);
1153 /* Include the size of the jmp instruction. */
1158 /* Relative jump, disp8 (ignore data16). */
1159 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1161 delta += data16 + 2;
1168 /* Check whether PC points at a prologue for a function returning a
1169 structure or union. If so, it updates CACHE and returns the
1170 address of the first instruction after the code sequence that
1171 removes the "hidden" argument from the stack or CURRENT_PC,
1172 whichever is smaller. Otherwise, return PC. */
1175 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1176 struct i386_frame_cache *cache)
1178 /* Functions that return a structure or union start with:
1181 xchgl %eax, (%esp) 0x87 0x04 0x24
1182 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1184 (the System V compiler puts out the second `xchg' instruction,
1185 and the assembler doesn't try to optimize it, so the 'sib' form
1186 gets generated). This sequence is used to get the address of the
1187 return buffer for a function that returns a structure. */
1188 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1189 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1193 if (current_pc <= pc)
1196 if (target_read_code (pc, &op, 1))
1199 if (op != 0x58) /* popl %eax */
1202 if (target_read_code (pc + 1, buf, 4))
1205 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1208 if (current_pc == pc)
1210 cache->sp_offset += 4;
1214 if (current_pc == pc + 1)
1216 cache->pc_in_eax = 1;
1220 if (buf[1] == proto1[1])
1227 i386_skip_probe (CORE_ADDR pc)
1229 /* A function may start with
1243 if (target_read_code (pc, &op, 1))
1246 if (op == 0x68 || op == 0x6a)
1250 /* Skip past the `pushl' instruction; it has either a one-byte or a
1251 four-byte operand, depending on the opcode. */
1257 /* Read the following 8 bytes, which should be `call _probe' (6
1258 bytes) followed by `addl $4,%esp' (2 bytes). */
1259 read_memory (pc + delta, buf, sizeof (buf));
1260 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1261 pc += delta + sizeof (buf);
1267 /* GCC 4.1 and later, can put code in the prologue to realign the
1268 stack pointer. Check whether PC points to such code, and update
1269 CACHE accordingly. Return the first instruction after the code
1270 sequence or CURRENT_PC, whichever is smaller. If we don't
1271 recognize the code, return PC. */
1274 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1275 struct i386_frame_cache *cache)
1277 /* There are 2 code sequences to re-align stack before the frame
1280 1. Use a caller-saved saved register:
1286 2. Use a callee-saved saved register:
1293 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1295 0x83 0xe4 0xf0 andl $-16, %esp
1296 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1301 int offset, offset_and;
1302 static int regnums[8] = {
1303 I386_EAX_REGNUM, /* %eax */
1304 I386_ECX_REGNUM, /* %ecx */
1305 I386_EDX_REGNUM, /* %edx */
1306 I386_EBX_REGNUM, /* %ebx */
1307 I386_ESP_REGNUM, /* %esp */
1308 I386_EBP_REGNUM, /* %ebp */
1309 I386_ESI_REGNUM, /* %esi */
1310 I386_EDI_REGNUM /* %edi */
1313 if (target_read_code (pc, buf, sizeof buf))
1316 /* Check caller-saved saved register. The first instruction has
1317 to be "leal 4(%esp), %reg". */
1318 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1320 /* MOD must be binary 10 and R/M must be binary 100. */
1321 if ((buf[1] & 0xc7) != 0x44)
1324 /* REG has register number. */
1325 reg = (buf[1] >> 3) & 7;
1330 /* Check callee-saved saved register. The first instruction
1331 has to be "pushl %reg". */
1332 if ((buf[0] & 0xf8) != 0x50)
1338 /* The next instruction has to be "leal 8(%esp), %reg". */
1339 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1342 /* MOD must be binary 10 and R/M must be binary 100. */
1343 if ((buf[2] & 0xc7) != 0x44)
1346 /* REG has register number. Registers in pushl and leal have to
1348 if (reg != ((buf[2] >> 3) & 7))
1354 /* Rigister can't be %esp nor %ebp. */
1355 if (reg == 4 || reg == 5)
1358 /* The next instruction has to be "andl $-XXX, %esp". */
1359 if (buf[offset + 1] != 0xe4
1360 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1363 offset_and = offset;
1364 offset += buf[offset] == 0x81 ? 6 : 3;
1366 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1367 0xfc. REG must be binary 110 and MOD must be binary 01. */
1368 if (buf[offset] != 0xff
1369 || buf[offset + 2] != 0xfc
1370 || (buf[offset + 1] & 0xf8) != 0x70)
1373 /* R/M has register. Registers in leal and pushl have to be the
1375 if (reg != (buf[offset + 1] & 7))
1378 if (current_pc > pc + offset_and)
1379 cache->saved_sp_reg = regnums[reg];
1381 return std::min (pc + offset + 3, current_pc);
1384 /* Maximum instruction length we need to handle. */
1385 #define I386_MAX_MATCHED_INSN_LEN 6
1387 /* Instruction description. */
1391 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1392 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1395 /* Return whether instruction at PC matches PATTERN. */
1398 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1402 if (target_read_code (pc, &op, 1))
1405 if ((op & pattern.mask[0]) == pattern.insn[0])
1407 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1408 int insn_matched = 1;
1411 gdb_assert (pattern.len > 1);
1412 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1414 if (target_read_code (pc + 1, buf, pattern.len - 1))
1417 for (i = 1; i < pattern.len; i++)
1419 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1422 return insn_matched;
1427 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1428 the first instruction description that matches. Otherwise, return
1431 static struct i386_insn *
1432 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1434 struct i386_insn *pattern;
1436 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1438 if (i386_match_pattern (pc, *pattern))
1445 /* Return whether PC points inside a sequence of instructions that
1446 matches INSN_PATTERNS. */
1449 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1451 CORE_ADDR current_pc;
1453 struct i386_insn *insn;
1455 insn = i386_match_insn (pc, insn_patterns);
1460 ix = insn - insn_patterns;
1461 for (i = ix - 1; i >= 0; i--)
1463 current_pc -= insn_patterns[i].len;
1465 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1469 current_pc = pc + insn->len;
1470 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1472 if (!i386_match_pattern (current_pc, *insn))
1475 current_pc += insn->len;
1481 /* Some special instructions that might be migrated by GCC into the
1482 part of the prologue that sets up the new stack frame. Because the
1483 stack frame hasn't been setup yet, no registers have been saved
1484 yet, and only the scratch registers %eax, %ecx and %edx can be
1487 struct i386_insn i386_frame_setup_skip_insns[] =
1489 /* Check for `movb imm8, r' and `movl imm32, r'.
1491 ??? Should we handle 16-bit operand-sizes here? */
1493 /* `movb imm8, %al' and `movb imm8, %ah' */
1494 /* `movb imm8, %cl' and `movb imm8, %ch' */
1495 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1496 /* `movb imm8, %dl' and `movb imm8, %dh' */
1497 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1498 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1499 { 5, { 0xb8 }, { 0xfe } },
1500 /* `movl imm32, %edx' */
1501 { 5, { 0xba }, { 0xff } },
1503 /* Check for `mov imm32, r32'. Note that there is an alternative
1504 encoding for `mov m32, %eax'.
1506 ??? Should we handle SIB adressing here?
1507 ??? Should we handle 16-bit operand-sizes here? */
1509 /* `movl m32, %eax' */
1510 { 5, { 0xa1 }, { 0xff } },
1511 /* `movl m32, %eax' and `mov; m32, %ecx' */
1512 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1513 /* `movl m32, %edx' */
1514 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1516 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1517 Because of the symmetry, there are actually two ways to encode
1518 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1519 opcode bytes 0x31 and 0x33 for `xorl'. */
1521 /* `subl %eax, %eax' */
1522 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1523 /* `subl %ecx, %ecx' */
1524 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1525 /* `subl %edx, %edx' */
1526 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1527 /* `xorl %eax, %eax' */
1528 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1529 /* `xorl %ecx, %ecx' */
1530 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1531 /* `xorl %edx, %edx' */
1532 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1537 /* Check whether PC points to a no-op instruction. */
1539 i386_skip_noop (CORE_ADDR pc)
1544 if (target_read_code (pc, &op, 1))
1550 /* Ignore `nop' instruction. */
1554 if (target_read_code (pc, &op, 1))
1558 /* Ignore no-op instruction `mov %edi, %edi'.
1559 Microsoft system dlls often start with
1560 a `mov %edi,%edi' instruction.
1561 The 5 bytes before the function start are
1562 filled with `nop' instructions.
1563 This pattern can be used for hot-patching:
1564 The `mov %edi, %edi' instruction can be replaced by a
1565 near jump to the location of the 5 `nop' instructions
1566 which can be replaced by a 32-bit jump to anywhere
1567 in the 32-bit address space. */
1569 else if (op == 0x8b)
1571 if (target_read_code (pc + 1, &op, 1))
1577 if (target_read_code (pc, &op, 1))
1587 /* Check whether PC points at a code that sets up a new stack frame.
1588 If so, it updates CACHE and returns the address of the first
1589 instruction after the sequence that sets up the frame or LIMIT,
1590 whichever is smaller. If we don't recognize the code, return PC. */
1593 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1594 CORE_ADDR pc, CORE_ADDR limit,
1595 struct i386_frame_cache *cache)
1597 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1598 struct i386_insn *insn;
1605 if (target_read_code (pc, &op, 1))
1608 if (op == 0x55) /* pushl %ebp */
1610 /* Take into account that we've executed the `pushl %ebp' that
1611 starts this instruction sequence. */
1612 cache->saved_regs[I386_EBP_REGNUM] = 0;
1613 cache->sp_offset += 4;
1616 /* If that's all, return now. */
1620 /* Check for some special instructions that might be migrated by
1621 GCC into the prologue and skip them. At this point in the
1622 prologue, code should only touch the scratch registers %eax,
1623 %ecx and %edx, so while the number of posibilities is sheer,
1626 Make sure we only skip these instructions if we later see the
1627 `movl %esp, %ebp' that actually sets up the frame. */
1628 while (pc + skip < limit)
1630 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1637 /* If that's all, return now. */
1638 if (limit <= pc + skip)
1641 if (target_read_code (pc + skip, &op, 1))
1644 /* The i386 prologue looks like
1650 and a different prologue can be generated for atom.
1654 lea -0x10(%esp),%esp
1656 We handle both of them here. */
1660 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1662 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1668 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1673 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1674 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1683 /* OK, we actually have a frame. We just don't know how large
1684 it is yet. Set its size to zero. We'll adjust it if
1685 necessary. We also now commit to skipping the special
1686 instructions mentioned before. */
1689 /* If that's all, return now. */
1693 /* Check for stack adjustment
1699 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1700 reg, so we don't have to worry about a data16 prefix. */
1701 if (target_read_code (pc, &op, 1))
1705 /* `subl' with 8-bit immediate. */
1706 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1707 /* Some instruction starting with 0x83 other than `subl'. */
1710 /* `subl' with signed 8-bit immediate (though it wouldn't
1711 make sense to be negative). */
1712 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1715 else if (op == 0x81)
1717 /* Maybe it is `subl' with a 32-bit immediate. */
1718 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1719 /* Some instruction starting with 0x81 other than `subl'. */
1722 /* It is `subl' with a 32-bit immediate. */
1723 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1726 else if (op == 0x8d)
1728 /* The ModR/M byte is 0x64. */
1729 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1731 /* 'lea' with 8-bit displacement. */
1732 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1737 /* Some instruction other than `subl' nor 'lea'. */
1741 else if (op == 0xc8) /* enter */
1743 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1750 /* Check whether PC points at code that saves registers on the stack.
1751 If so, it updates CACHE and returns the address of the first
1752 instruction after the register saves or CURRENT_PC, whichever is
1753 smaller. Otherwise, return PC. */
1756 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1757 struct i386_frame_cache *cache)
1759 CORE_ADDR offset = 0;
1763 if (cache->locals > 0)
1764 offset -= cache->locals;
1765 for (i = 0; i < 8 && pc < current_pc; i++)
1767 if (target_read_code (pc, &op, 1))
1769 if (op < 0x50 || op > 0x57)
1773 cache->saved_regs[op - 0x50] = offset;
1774 cache->sp_offset += 4;
1781 /* Do a full analysis of the prologue at PC and update CACHE
1782 accordingly. Bail out early if CURRENT_PC is reached. Return the
1783 address where the analysis stopped.
1785 We handle these cases:
1787 The startup sequence can be at the start of the function, or the
1788 function can start with a branch to startup code at the end.
1790 %ebp can be set up with either the 'enter' instruction, or "pushl
1791 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1792 once used in the System V compiler).
1794 Local space is allocated just below the saved %ebp by either the
1795 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1796 16-bit unsigned argument for space to allocate, and the 'addl'
1797 instruction could have either a signed byte, or 32-bit immediate.
1799 Next, the registers used by this function are pushed. With the
1800 System V compiler they will always be in the order: %edi, %esi,
1801 %ebx (and sometimes a harmless bug causes it to also save but not
1802 restore %eax); however, the code below is willing to see the pushes
1803 in any order, and will handle up to 8 of them.
1805 If the setup sequence is at the end of the function, then the next
1806 instruction will be a branch back to the start. */
1809 i386_analyze_prologue (struct gdbarch *gdbarch,
1810 CORE_ADDR pc, CORE_ADDR current_pc,
1811 struct i386_frame_cache *cache)
1813 pc = i386_skip_noop (pc);
1814 pc = i386_follow_jump (gdbarch, pc);
1815 pc = i386_analyze_struct_return (pc, current_pc, cache);
1816 pc = i386_skip_probe (pc);
1817 pc = i386_analyze_stack_align (pc, current_pc, cache);
1818 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1819 return i386_analyze_register_saves (pc, current_pc, cache);
1822 /* Return PC of first real instruction. */
1825 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1827 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1829 static gdb_byte pic_pat[6] =
1831 0xe8, 0, 0, 0, 0, /* call 0x0 */
1832 0x5b, /* popl %ebx */
1834 struct i386_frame_cache cache;
1838 CORE_ADDR func_addr;
1840 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1842 CORE_ADDR post_prologue_pc
1843 = skip_prologue_using_sal (gdbarch, func_addr);
1844 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1846 /* Clang always emits a line note before the prologue and another
1847 one after. We trust clang to emit usable line notes. */
1848 if (post_prologue_pc
1850 && COMPUNIT_PRODUCER (cust) != NULL
1851 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1852 return std::max (start_pc, post_prologue_pc);
1856 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1857 if (cache.locals < 0)
1860 /* Found valid frame setup. */
1862 /* The native cc on SVR4 in -K PIC mode inserts the following code
1863 to get the address of the global offset table (GOT) into register
1868 movl %ebx,x(%ebp) (optional)
1871 This code is with the rest of the prologue (at the end of the
1872 function), so we have to skip it to get to the first real
1873 instruction at the start of the function. */
1875 for (i = 0; i < 6; i++)
1877 if (target_read_code (pc + i, &op, 1))
1880 if (pic_pat[i] != op)
1887 if (target_read_code (pc + delta, &op, 1))
1890 if (op == 0x89) /* movl %ebx, x(%ebp) */
1892 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1894 if (op == 0x5d) /* One byte offset from %ebp. */
1896 else if (op == 0x9d) /* Four byte offset from %ebp. */
1898 else /* Unexpected instruction. */
1901 if (target_read_code (pc + delta, &op, 1))
1906 if (delta > 0 && op == 0x81
1907 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1914 /* If the function starts with a branch (to startup code at the end)
1915 the last instruction should bring us back to the first
1916 instruction of the real code. */
1917 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1918 pc = i386_follow_jump (gdbarch, pc);
1923 /* Check that the code pointed to by PC corresponds to a call to
1924 __main, skip it if so. Return PC otherwise. */
1927 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1929 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1932 if (target_read_code (pc, &op, 1))
1938 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1940 /* Make sure address is computed correctly as a 32bit
1941 integer even if CORE_ADDR is 64 bit wide. */
1942 struct bound_minimal_symbol s;
1943 CORE_ADDR call_dest;
1945 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1946 call_dest = call_dest & 0xffffffffU;
1947 s = lookup_minimal_symbol_by_pc (call_dest);
1948 if (s.minsym != NULL
1949 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1950 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1958 /* This function is 64-bit safe. */
1961 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1965 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1966 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1970 /* Normal frames. */
1973 i386_frame_cache_1 (struct frame_info *this_frame,
1974 struct i386_frame_cache *cache)
1976 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1977 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1981 cache->pc = get_frame_func (this_frame);
1983 /* In principle, for normal frames, %ebp holds the frame pointer,
1984 which holds the base address for the current stack frame.
1985 However, for functions that don't need it, the frame pointer is
1986 optional. For these "frameless" functions the frame pointer is
1987 actually the frame pointer of the calling frame. Signal
1988 trampolines are just a special case of a "frameless" function.
1989 They (usually) share their frame pointer with the frame that was
1990 in progress when the signal occurred. */
1992 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1993 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1994 if (cache->base == 0)
2000 /* For normal frames, %eip is stored at 4(%ebp). */
2001 cache->saved_regs[I386_EIP_REGNUM] = 4;
2004 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2007 if (cache->locals < 0)
2009 /* We didn't find a valid frame, which means that CACHE->base
2010 currently holds the frame pointer for our calling frame. If
2011 we're at the start of a function, or somewhere half-way its
2012 prologue, the function's frame probably hasn't been fully
2013 setup yet. Try to reconstruct the base address for the stack
2014 frame by looking at the stack pointer. For truly "frameless"
2015 functions this might work too. */
2017 if (cache->saved_sp_reg != -1)
2019 /* Saved stack pointer has been saved. */
2020 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2021 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2023 /* We're halfway aligning the stack. */
2024 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2025 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2027 /* This will be added back below. */
2028 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2030 else if (cache->pc != 0
2031 || target_read_code (get_frame_pc (this_frame), buf, 1))
2033 /* We're in a known function, but did not find a frame
2034 setup. Assume that the function does not use %ebp.
2035 Alternatively, we may have jumped to an invalid
2036 address; in that case there is definitely no new
2038 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2039 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2043 /* We're in an unknown function. We could not find the start
2044 of the function to analyze the prologue; our best option is
2045 to assume a typical frame layout with the caller's %ebp
2047 cache->saved_regs[I386_EBP_REGNUM] = 0;
2050 if (cache->saved_sp_reg != -1)
2052 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2053 register may be unavailable). */
2054 if (cache->saved_sp == 0
2055 && deprecated_frame_register_read (this_frame,
2056 cache->saved_sp_reg, buf))
2057 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2059 /* Now that we have the base address for the stack frame we can
2060 calculate the value of %esp in the calling frame. */
2061 else if (cache->saved_sp == 0)
2062 cache->saved_sp = cache->base + 8;
2064 /* Adjust all the saved registers such that they contain addresses
2065 instead of offsets. */
2066 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2067 if (cache->saved_regs[i] != -1)
2068 cache->saved_regs[i] += cache->base;
2073 static struct i386_frame_cache *
2074 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2076 struct i386_frame_cache *cache;
2079 return (struct i386_frame_cache *) *this_cache;
2081 cache = i386_alloc_frame_cache ();
2082 *this_cache = cache;
2086 i386_frame_cache_1 (this_frame, cache);
2088 CATCH (ex, RETURN_MASK_ERROR)
2090 if (ex.error != NOT_AVAILABLE_ERROR)
2091 throw_exception (ex);
2099 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2100 struct frame_id *this_id)
2102 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2105 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2106 else if (cache->base == 0)
2108 /* This marks the outermost frame. */
2112 /* See the end of i386_push_dummy_call. */
2113 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2117 static enum unwind_stop_reason
2118 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2121 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2124 return UNWIND_UNAVAILABLE;
2126 /* This marks the outermost frame. */
2127 if (cache->base == 0)
2128 return UNWIND_OUTERMOST;
2130 return UNWIND_NO_REASON;
2133 static struct value *
2134 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2137 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2139 gdb_assert (regnum >= 0);
2141 /* The System V ABI says that:
2143 "The flags register contains the system flags, such as the
2144 direction flag and the carry flag. The direction flag must be
2145 set to the forward (that is, zero) direction before entry and
2146 upon exit from a function. Other user flags have no specified
2147 role in the standard calling sequence and are not preserved."
2149 To guarantee the "upon exit" part of that statement we fake a
2150 saved flags register that has its direction flag cleared.
2152 Note that GCC doesn't seem to rely on the fact that the direction
2153 flag is cleared after a function return; it always explicitly
2154 clears the flag before operations where it matters.
2156 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2157 right thing to do. The way we fake the flags register here makes
2158 it impossible to change it. */
2160 if (regnum == I386_EFLAGS_REGNUM)
2164 val = get_frame_register_unsigned (this_frame, regnum);
2166 return frame_unwind_got_constant (this_frame, regnum, val);
2169 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2170 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2172 if (regnum == I386_ESP_REGNUM
2173 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2175 /* If the SP has been saved, but we don't know where, then this
2176 means that SAVED_SP_REG register was found unavailable back
2177 when we built the cache. */
2178 if (cache->saved_sp == 0)
2179 return frame_unwind_got_register (this_frame, regnum,
2180 cache->saved_sp_reg);
2182 return frame_unwind_got_constant (this_frame, regnum,
2186 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2187 return frame_unwind_got_memory (this_frame, regnum,
2188 cache->saved_regs[regnum]);
2190 return frame_unwind_got_register (this_frame, regnum, regnum);
2193 static const struct frame_unwind i386_frame_unwind =
2196 i386_frame_unwind_stop_reason,
2198 i386_frame_prev_register,
2200 default_frame_sniffer
2203 /* Normal frames, but in a function epilogue. */
2205 /* Implement the stack_frame_destroyed_p gdbarch method.
2207 The epilogue is defined here as the 'ret' instruction, which will
2208 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2209 the function's stack frame. */
2212 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2215 struct compunit_symtab *cust;
2217 cust = find_pc_compunit_symtab (pc);
2218 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2221 if (target_read_memory (pc, &insn, 1))
2222 return 0; /* Can't read memory at pc. */
2224 if (insn != 0xc3) /* 'ret' instruction. */
2231 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2232 struct frame_info *this_frame,
2233 void **this_prologue_cache)
2235 if (frame_relative_level (this_frame) == 0)
2236 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2237 get_frame_pc (this_frame));
2242 static struct i386_frame_cache *
2243 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2245 struct i386_frame_cache *cache;
2249 return (struct i386_frame_cache *) *this_cache;
2251 cache = i386_alloc_frame_cache ();
2252 *this_cache = cache;
2256 cache->pc = get_frame_func (this_frame);
2258 /* At this point the stack looks as if we just entered the
2259 function, with the return address at the top of the
2261 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2262 cache->base = sp + cache->sp_offset;
2263 cache->saved_sp = cache->base + 8;
2264 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2268 CATCH (ex, RETURN_MASK_ERROR)
2270 if (ex.error != NOT_AVAILABLE_ERROR)
2271 throw_exception (ex);
2278 static enum unwind_stop_reason
2279 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2282 struct i386_frame_cache *cache =
2283 i386_epilogue_frame_cache (this_frame, this_cache);
2286 return UNWIND_UNAVAILABLE;
2288 return UNWIND_NO_REASON;
2292 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2294 struct frame_id *this_id)
2296 struct i386_frame_cache *cache =
2297 i386_epilogue_frame_cache (this_frame, this_cache);
2300 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2302 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2305 static struct value *
2306 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2307 void **this_cache, int regnum)
2309 /* Make sure we've initialized the cache. */
2310 i386_epilogue_frame_cache (this_frame, this_cache);
2312 return i386_frame_prev_register (this_frame, this_cache, regnum);
2315 static const struct frame_unwind i386_epilogue_frame_unwind =
2318 i386_epilogue_frame_unwind_stop_reason,
2319 i386_epilogue_frame_this_id,
2320 i386_epilogue_frame_prev_register,
2322 i386_epilogue_frame_sniffer
2326 /* Stack-based trampolines. */
2328 /* These trampolines are used on cross x86 targets, when taking the
2329 address of a nested function. When executing these trampolines,
2330 no stack frame is set up, so we are in a similar situation as in
2331 epilogues and i386_epilogue_frame_this_id can be re-used. */
2333 /* Static chain passed in register. */
2335 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2337 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2338 { 5, { 0xb8 }, { 0xfe } },
2341 { 5, { 0xe9 }, { 0xff } },
2346 /* Static chain passed on stack (when regparm=3). */
2348 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2351 { 5, { 0x68 }, { 0xff } },
2354 { 5, { 0xe9 }, { 0xff } },
2359 /* Return whether PC points inside a stack trampoline. */
2362 i386_in_stack_tramp_p (CORE_ADDR pc)
2367 /* A stack trampoline is detected if no name is associated
2368 to the current pc and if it points inside a trampoline
2371 find_pc_partial_function (pc, &name, NULL, NULL);
2375 if (target_read_memory (pc, &insn, 1))
2378 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2379 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2386 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2387 struct frame_info *this_frame,
2390 if (frame_relative_level (this_frame) == 0)
2391 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2396 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2399 i386_epilogue_frame_unwind_stop_reason,
2400 i386_epilogue_frame_this_id,
2401 i386_epilogue_frame_prev_register,
2403 i386_stack_tramp_frame_sniffer
2406 /* Generate a bytecode expression to get the value of the saved PC. */
2409 i386_gen_return_address (struct gdbarch *gdbarch,
2410 struct agent_expr *ax, struct axs_value *value,
2413 /* The following sequence assumes the traditional use of the base
2415 ax_reg (ax, I386_EBP_REGNUM);
2417 ax_simple (ax, aop_add);
2418 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2419 value->kind = axs_lvalue_memory;
2423 /* Signal trampolines. */
2425 static struct i386_frame_cache *
2426 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2428 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2429 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2430 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2431 struct i386_frame_cache *cache;
2436 return (struct i386_frame_cache *) *this_cache;
2438 cache = i386_alloc_frame_cache ();
2442 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2443 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2445 addr = tdep->sigcontext_addr (this_frame);
2446 if (tdep->sc_reg_offset)
2450 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2452 for (i = 0; i < tdep->sc_num_regs; i++)
2453 if (tdep->sc_reg_offset[i] != -1)
2454 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2458 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2459 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2464 CATCH (ex, RETURN_MASK_ERROR)
2466 if (ex.error != NOT_AVAILABLE_ERROR)
2467 throw_exception (ex);
2471 *this_cache = cache;
2475 static enum unwind_stop_reason
2476 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2479 struct i386_frame_cache *cache =
2480 i386_sigtramp_frame_cache (this_frame, this_cache);
2483 return UNWIND_UNAVAILABLE;
2485 return UNWIND_NO_REASON;
2489 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2490 struct frame_id *this_id)
2492 struct i386_frame_cache *cache =
2493 i386_sigtramp_frame_cache (this_frame, this_cache);
2496 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2499 /* See the end of i386_push_dummy_call. */
2500 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2504 static struct value *
2505 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2506 void **this_cache, int regnum)
2508 /* Make sure we've initialized the cache. */
2509 i386_sigtramp_frame_cache (this_frame, this_cache);
2511 return i386_frame_prev_register (this_frame, this_cache, regnum);
2515 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2516 struct frame_info *this_frame,
2517 void **this_prologue_cache)
2519 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2521 /* We shouldn't even bother if we don't have a sigcontext_addr
2523 if (tdep->sigcontext_addr == NULL)
2526 if (tdep->sigtramp_p != NULL)
2528 if (tdep->sigtramp_p (this_frame))
2532 if (tdep->sigtramp_start != 0)
2534 CORE_ADDR pc = get_frame_pc (this_frame);
2536 gdb_assert (tdep->sigtramp_end != 0);
2537 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2544 static const struct frame_unwind i386_sigtramp_frame_unwind =
2547 i386_sigtramp_frame_unwind_stop_reason,
2548 i386_sigtramp_frame_this_id,
2549 i386_sigtramp_frame_prev_register,
2551 i386_sigtramp_frame_sniffer
2556 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2558 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2563 static const struct frame_base i386_frame_base =
2566 i386_frame_base_address,
2567 i386_frame_base_address,
2568 i386_frame_base_address
2571 static struct frame_id
2572 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2576 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2578 /* See the end of i386_push_dummy_call. */
2579 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2582 /* _Decimal128 function return values need 16-byte alignment on the
2586 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2588 return sp & -(CORE_ADDR)16;
2592 /* Figure out where the longjmp will land. Slurp the args out of the
2593 stack. We expect the first arg to be a pointer to the jmp_buf
2594 structure from which we extract the address that we will land at.
2595 This address is copied into PC. This routine returns non-zero on
2599 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2602 CORE_ADDR sp, jb_addr;
2603 struct gdbarch *gdbarch = get_frame_arch (frame);
2604 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2605 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2607 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2608 longjmp will land. */
2609 if (jb_pc_offset == -1)
2612 get_frame_register (frame, I386_ESP_REGNUM, buf);
2613 sp = extract_unsigned_integer (buf, 4, byte_order);
2614 if (target_read_memory (sp + 4, buf, 4))
2617 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2618 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2621 *pc = extract_unsigned_integer (buf, 4, byte_order);
2626 /* Check whether TYPE must be 16-byte-aligned when passed as a
2627 function argument. 16-byte vectors, _Decimal128 and structures or
2628 unions containing such types must be 16-byte-aligned; other
2629 arguments are 4-byte-aligned. */
2632 i386_16_byte_align_p (struct type *type)
2634 type = check_typedef (type);
2635 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2636 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2637 && TYPE_LENGTH (type) == 16)
2639 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2640 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2641 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2642 || TYPE_CODE (type) == TYPE_CODE_UNION)
2645 for (i = 0; i < TYPE_NFIELDS (type); i++)
2647 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2654 /* Implementation for set_gdbarch_push_dummy_code. */
2657 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2658 struct value **args, int nargs, struct type *value_type,
2659 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2660 struct regcache *regcache)
2662 /* Use 0xcc breakpoint - 1 byte. */
2666 /* Keep the stack aligned. */
2671 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2672 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2673 struct value **args, CORE_ADDR sp, int struct_return,
2674 CORE_ADDR struct_addr)
2676 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2682 /* BND registers can be in arbitrary values at the moment of the
2683 inferior call. This can cause boundary violations that are not
2684 due to a real bug or even desired by the user. The best to be done
2685 is set the BND registers to allow access to the whole memory, INIT
2686 state, before pushing the inferior call. */
2687 i387_reset_bnd_regs (gdbarch, regcache);
2689 /* Determine the total space required for arguments and struct
2690 return address in a first pass (allowing for 16-byte-aligned
2691 arguments), then push arguments in a second pass. */
2693 for (write_pass = 0; write_pass < 2; write_pass++)
2695 int args_space_used = 0;
2701 /* Push value address. */
2702 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2703 write_memory (sp, buf, 4);
2704 args_space_used += 4;
2710 for (i = 0; i < nargs; i++)
2712 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2716 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2717 args_space_used = align_up (args_space_used, 16);
2719 write_memory (sp + args_space_used,
2720 value_contents_all (args[i]), len);
2721 /* The System V ABI says that:
2723 "An argument's size is increased, if necessary, to make it a
2724 multiple of [32-bit] words. This may require tail padding,
2725 depending on the size of the argument."
2727 This makes sure the stack stays word-aligned. */
2728 args_space_used += align_up (len, 4);
2732 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2733 args_space = align_up (args_space, 16);
2734 args_space += align_up (len, 4);
2742 /* The original System V ABI only requires word alignment,
2743 but modern incarnations need 16-byte alignment in order
2744 to support SSE. Since wasting a few bytes here isn't
2745 harmful we unconditionally enforce 16-byte alignment. */
2750 /* Store return address. */
2752 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2753 write_memory (sp, buf, 4);
2755 /* Finally, update the stack pointer... */
2756 store_unsigned_integer (buf, 4, byte_order, sp);
2757 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2759 /* ...and fake a frame pointer. */
2760 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2762 /* MarkK wrote: This "+ 8" is all over the place:
2763 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2764 i386_dummy_id). It's there, since all frame unwinders for
2765 a given target have to agree (within a certain margin) on the
2766 definition of the stack address of a frame. Otherwise frame id
2767 comparison might not work correctly. Since DWARF2/GCC uses the
2768 stack address *before* the function call as a frame's CFA. On
2769 the i386, when %ebp is used as a frame pointer, the offset
2770 between the contents %ebp and the CFA as defined by GCC. */
2774 /* These registers are used for returning integers (and on some
2775 targets also for returning `struct' and `union' values when their
2776 size and alignment match an integer type). */
2777 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2778 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2780 /* Read, for architecture GDBARCH, a function return value of TYPE
2781 from REGCACHE, and copy that into VALBUF. */
2784 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2785 struct regcache *regcache, gdb_byte *valbuf)
2787 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2788 int len = TYPE_LENGTH (type);
2789 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2791 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2793 if (tdep->st0_regnum < 0)
2795 warning (_("Cannot find floating-point return value."));
2796 memset (valbuf, 0, len);
2800 /* Floating-point return values can be found in %st(0). Convert
2801 its contents to the desired type. This is probably not
2802 exactly how it would happen on the target itself, but it is
2803 the best we can do. */
2804 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2805 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2809 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2810 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2812 if (len <= low_size)
2814 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2815 memcpy (valbuf, buf, len);
2817 else if (len <= (low_size + high_size))
2819 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2820 memcpy (valbuf, buf, low_size);
2821 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2822 memcpy (valbuf + low_size, buf, len - low_size);
2825 internal_error (__FILE__, __LINE__,
2826 _("Cannot extract return value of %d bytes long."),
2831 /* Write, for architecture GDBARCH, a function return value of TYPE
2832 from VALBUF into REGCACHE. */
2835 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2836 struct regcache *regcache, const gdb_byte *valbuf)
2838 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2839 int len = TYPE_LENGTH (type);
2841 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2844 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2846 if (tdep->st0_regnum < 0)
2848 warning (_("Cannot set floating-point return value."));
2852 /* Returning floating-point values is a bit tricky. Apart from
2853 storing the return value in %st(0), we have to simulate the
2854 state of the FPU at function return point. */
2856 /* Convert the value found in VALBUF to the extended
2857 floating-point format used by the FPU. This is probably
2858 not exactly how it would happen on the target itself, but
2859 it is the best we can do. */
2860 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2861 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2863 /* Set the top of the floating-point register stack to 7. The
2864 actual value doesn't really matter, but 7 is what a normal
2865 function return would end up with if the program started out
2866 with a freshly initialized FPU. */
2867 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2869 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2871 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2872 the floating-point register stack to 7, the appropriate value
2873 for the tag word is 0x3fff. */
2874 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2878 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2879 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2881 if (len <= low_size)
2882 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2883 else if (len <= (low_size + high_size))
2885 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2886 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2887 len - low_size, valbuf + low_size);
2890 internal_error (__FILE__, __LINE__,
2891 _("Cannot store return value of %d bytes long."), len);
2896 /* This is the variable that is set with "set struct-convention", and
2897 its legitimate values. */
2898 static const char default_struct_convention[] = "default";
2899 static const char pcc_struct_convention[] = "pcc";
2900 static const char reg_struct_convention[] = "reg";
2901 static const char *const valid_conventions[] =
2903 default_struct_convention,
2904 pcc_struct_convention,
2905 reg_struct_convention,
2908 static const char *struct_convention = default_struct_convention;
2910 /* Return non-zero if TYPE, which is assumed to be a structure,
2911 a union type, or an array type, should be returned in registers
2912 for architecture GDBARCH. */
2915 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2917 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2918 enum type_code code = TYPE_CODE (type);
2919 int len = TYPE_LENGTH (type);
2921 gdb_assert (code == TYPE_CODE_STRUCT
2922 || code == TYPE_CODE_UNION
2923 || code == TYPE_CODE_ARRAY);
2925 if (struct_convention == pcc_struct_convention
2926 || (struct_convention == default_struct_convention
2927 && tdep->struct_return == pcc_struct_return))
2930 /* Structures consisting of a single `float', `double' or 'long
2931 double' member are returned in %st(0). */
2932 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2934 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2935 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2936 return (len == 4 || len == 8 || len == 12);
2939 return (len == 1 || len == 2 || len == 4 || len == 8);
2942 /* Determine, for architecture GDBARCH, how a return value of TYPE
2943 should be returned. If it is supposed to be returned in registers,
2944 and READBUF is non-zero, read the appropriate value from REGCACHE,
2945 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2946 from WRITEBUF into REGCACHE. */
2948 static enum return_value_convention
2949 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2950 struct type *type, struct regcache *regcache,
2951 gdb_byte *readbuf, const gdb_byte *writebuf)
2953 enum type_code code = TYPE_CODE (type);
2955 if (((code == TYPE_CODE_STRUCT
2956 || code == TYPE_CODE_UNION
2957 || code == TYPE_CODE_ARRAY)
2958 && !i386_reg_struct_return_p (gdbarch, type))
2959 /* Complex double and long double uses the struct return covention. */
2960 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2961 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2962 /* 128-bit decimal float uses the struct return convention. */
2963 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2965 /* The System V ABI says that:
2967 "A function that returns a structure or union also sets %eax
2968 to the value of the original address of the caller's area
2969 before it returns. Thus when the caller receives control
2970 again, the address of the returned object resides in register
2971 %eax and can be used to access the object."
2973 So the ABI guarantees that we can always find the return
2974 value just after the function has returned. */
2976 /* Note that the ABI doesn't mention functions returning arrays,
2977 which is something possible in certain languages such as Ada.
2978 In this case, the value is returned as if it was wrapped in
2979 a record, so the convention applied to records also applies
2986 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2987 read_memory (addr, readbuf, TYPE_LENGTH (type));
2990 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2993 /* This special case is for structures consisting of a single
2994 `float', `double' or 'long double' member. These structures are
2995 returned in %st(0). For these structures, we call ourselves
2996 recursively, changing TYPE into the type of the first member of
2997 the structure. Since that should work for all structures that
2998 have only one member, we don't bother to check the member's type
3000 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
3002 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
3003 return i386_return_value (gdbarch, function, type, regcache,
3008 i386_extract_return_value (gdbarch, type, regcache, readbuf);
3010 i386_store_return_value (gdbarch, type, regcache, writebuf);
3012 return RETURN_VALUE_REGISTER_CONVENTION;
3017 i387_ext_type (struct gdbarch *gdbarch)
3019 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3021 if (!tdep->i387_ext_type)
3023 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3024 gdb_assert (tdep->i387_ext_type != NULL);
3027 return tdep->i387_ext_type;
3030 /* Construct type for pseudo BND registers. We can't use
3031 tdesc_find_type since a complement of one value has to be used
3032 to describe the upper bound. */
3034 static struct type *
3035 i386_bnd_type (struct gdbarch *gdbarch)
3037 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3040 if (!tdep->i386_bnd_type)
3043 const struct builtin_type *bt = builtin_type (gdbarch);
3045 /* The type we're building is described bellow: */
3050 void *ubound; /* One complement of raw ubound field. */
3054 t = arch_composite_type (gdbarch,
3055 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3057 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3058 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3060 TYPE_NAME (t) = "builtin_type_bound128";
3061 tdep->i386_bnd_type = t;
3064 return tdep->i386_bnd_type;
3067 /* Construct vector type for pseudo ZMM registers. We can't use
3068 tdesc_find_type since ZMM isn't described in target description. */
3070 static struct type *
3071 i386_zmm_type (struct gdbarch *gdbarch)
3073 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3075 if (!tdep->i386_zmm_type)
3077 const struct builtin_type *bt = builtin_type (gdbarch);
3079 /* The type we're building is this: */
3081 union __gdb_builtin_type_vec512i
3083 int128_t uint128[4];
3084 int64_t v4_int64[8];
3085 int32_t v8_int32[16];
3086 int16_t v16_int16[32];
3087 int8_t v32_int8[64];
3088 double v4_double[8];
3095 t = arch_composite_type (gdbarch,
3096 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3097 append_composite_type_field (t, "v16_float",
3098 init_vector_type (bt->builtin_float, 16));
3099 append_composite_type_field (t, "v8_double",
3100 init_vector_type (bt->builtin_double, 8));
3101 append_composite_type_field (t, "v64_int8",
3102 init_vector_type (bt->builtin_int8, 64));
3103 append_composite_type_field (t, "v32_int16",
3104 init_vector_type (bt->builtin_int16, 32));
3105 append_composite_type_field (t, "v16_int32",
3106 init_vector_type (bt->builtin_int32, 16));
3107 append_composite_type_field (t, "v8_int64",
3108 init_vector_type (bt->builtin_int64, 8));
3109 append_composite_type_field (t, "v4_int128",
3110 init_vector_type (bt->builtin_int128, 4));
3112 TYPE_VECTOR (t) = 1;
3113 TYPE_NAME (t) = "builtin_type_vec512i";
3114 tdep->i386_zmm_type = t;
3117 return tdep->i386_zmm_type;
3120 /* Construct vector type for pseudo YMM registers. We can't use
3121 tdesc_find_type since YMM isn't described in target description. */
3123 static struct type *
3124 i386_ymm_type (struct gdbarch *gdbarch)
3126 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3128 if (!tdep->i386_ymm_type)
3130 const struct builtin_type *bt = builtin_type (gdbarch);
3132 /* The type we're building is this: */
3134 union __gdb_builtin_type_vec256i
3136 int128_t uint128[2];
3137 int64_t v2_int64[4];
3138 int32_t v4_int32[8];
3139 int16_t v8_int16[16];
3140 int8_t v16_int8[32];
3141 double v2_double[4];
3148 t = arch_composite_type (gdbarch,
3149 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3150 append_composite_type_field (t, "v8_float",
3151 init_vector_type (bt->builtin_float, 8));
3152 append_composite_type_field (t, "v4_double",
3153 init_vector_type (bt->builtin_double, 4));
3154 append_composite_type_field (t, "v32_int8",
3155 init_vector_type (bt->builtin_int8, 32));
3156 append_composite_type_field (t, "v16_int16",
3157 init_vector_type (bt->builtin_int16, 16));
3158 append_composite_type_field (t, "v8_int32",
3159 init_vector_type (bt->builtin_int32, 8));
3160 append_composite_type_field (t, "v4_int64",
3161 init_vector_type (bt->builtin_int64, 4));
3162 append_composite_type_field (t, "v2_int128",
3163 init_vector_type (bt->builtin_int128, 2));
3165 TYPE_VECTOR (t) = 1;
3166 TYPE_NAME (t) = "builtin_type_vec256i";
3167 tdep->i386_ymm_type = t;
3170 return tdep->i386_ymm_type;
3173 /* Construct vector type for MMX registers. */
3174 static struct type *
3175 i386_mmx_type (struct gdbarch *gdbarch)
3177 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3179 if (!tdep->i386_mmx_type)
3181 const struct builtin_type *bt = builtin_type (gdbarch);
3183 /* The type we're building is this: */
3185 union __gdb_builtin_type_vec64i
3188 int32_t v2_int32[2];
3189 int16_t v4_int16[4];
3196 t = arch_composite_type (gdbarch,
3197 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3199 append_composite_type_field (t, "uint64", bt->builtin_int64);
3200 append_composite_type_field (t, "v2_int32",
3201 init_vector_type (bt->builtin_int32, 2));
3202 append_composite_type_field (t, "v4_int16",
3203 init_vector_type (bt->builtin_int16, 4));
3204 append_composite_type_field (t, "v8_int8",
3205 init_vector_type (bt->builtin_int8, 8));
3207 TYPE_VECTOR (t) = 1;
3208 TYPE_NAME (t) = "builtin_type_vec64i";
3209 tdep->i386_mmx_type = t;
3212 return tdep->i386_mmx_type;
3215 /* Return the GDB type object for the "standard" data type of data in
3219 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3221 if (i386_bnd_regnum_p (gdbarch, regnum))
3222 return i386_bnd_type (gdbarch);
3223 if (i386_mmx_regnum_p (gdbarch, regnum))
3224 return i386_mmx_type (gdbarch);
3225 else if (i386_ymm_regnum_p (gdbarch, regnum))
3226 return i386_ymm_type (gdbarch);
3227 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3228 return i386_ymm_type (gdbarch);
3229 else if (i386_zmm_regnum_p (gdbarch, regnum))
3230 return i386_zmm_type (gdbarch);
3233 const struct builtin_type *bt = builtin_type (gdbarch);
3234 if (i386_byte_regnum_p (gdbarch, regnum))
3235 return bt->builtin_int8;
3236 else if (i386_word_regnum_p (gdbarch, regnum))
3237 return bt->builtin_int16;
3238 else if (i386_dword_regnum_p (gdbarch, regnum))
3239 return bt->builtin_int32;
3240 else if (i386_k_regnum_p (gdbarch, regnum))
3241 return bt->builtin_int64;
3244 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3247 /* Map a cooked register onto a raw register or memory. For the i386,
3248 the MMX registers need to be mapped onto floating point registers. */
3251 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3253 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3258 mmxreg = regnum - tdep->mm0_regnum;
3259 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3260 tos = (fstat >> 11) & 0x7;
3261 fpreg = (mmxreg + tos) % 8;
3263 return (I387_ST0_REGNUM (tdep) + fpreg);
3266 /* A helper function for us by i386_pseudo_register_read_value and
3267 amd64_pseudo_register_read_value. It does all the work but reads
3268 the data into an already-allocated value. */
3271 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3272 struct regcache *regcache,
3274 struct value *result_value)
3276 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3277 enum register_status status;
3278 gdb_byte *buf = value_contents_raw (result_value);
3280 if (i386_mmx_regnum_p (gdbarch, regnum))
3282 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3284 /* Extract (always little endian). */
3285 status = regcache_raw_read (regcache, fpnum, raw_buf);
3286 if (status != REG_VALID)
3287 mark_value_bytes_unavailable (result_value, 0,
3288 TYPE_LENGTH (value_type (result_value)));
3290 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3294 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3295 if (i386_bnd_regnum_p (gdbarch, regnum))
3297 regnum -= tdep->bnd0_regnum;
3299 /* Extract (always little endian). Read lower 128bits. */
3300 status = regcache_raw_read (regcache,
3301 I387_BND0R_REGNUM (tdep) + regnum,
3303 if (status != REG_VALID)
3304 mark_value_bytes_unavailable (result_value, 0, 16);
3307 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3308 LONGEST upper, lower;
3309 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3311 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3312 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3315 memcpy (buf, &lower, size);
3316 memcpy (buf + size, &upper, size);
3319 else if (i386_k_regnum_p (gdbarch, regnum))
3321 regnum -= tdep->k0_regnum;
3323 /* Extract (always little endian). */
3324 status = regcache_raw_read (regcache,
3325 tdep->k0_regnum + regnum,
3327 if (status != REG_VALID)
3328 mark_value_bytes_unavailable (result_value, 0, 8);
3330 memcpy (buf, raw_buf, 8);
3332 else if (i386_zmm_regnum_p (gdbarch, regnum))
3334 regnum -= tdep->zmm0_regnum;
3336 if (regnum < num_lower_zmm_regs)
3338 /* Extract (always little endian). Read lower 128bits. */
3339 status = regcache_raw_read (regcache,
3340 I387_XMM0_REGNUM (tdep) + regnum,
3342 if (status != REG_VALID)
3343 mark_value_bytes_unavailable (result_value, 0, 16);
3345 memcpy (buf, raw_buf, 16);
3347 /* Extract (always little endian). Read upper 128bits. */
3348 status = regcache_raw_read (regcache,
3349 tdep->ymm0h_regnum + regnum,
3351 if (status != REG_VALID)
3352 mark_value_bytes_unavailable (result_value, 16, 16);
3354 memcpy (buf + 16, raw_buf, 16);
3358 /* Extract (always little endian). Read lower 128bits. */
3359 status = regcache_raw_read (regcache,
3360 I387_XMM16_REGNUM (tdep) + regnum
3361 - num_lower_zmm_regs,
3363 if (status != REG_VALID)
3364 mark_value_bytes_unavailable (result_value, 0, 16);
3366 memcpy (buf, raw_buf, 16);
3368 /* Extract (always little endian). Read upper 128bits. */
3369 status = regcache_raw_read (regcache,
3370 I387_YMM16H_REGNUM (tdep) + regnum
3371 - num_lower_zmm_regs,
3373 if (status != REG_VALID)
3374 mark_value_bytes_unavailable (result_value, 16, 16);
3376 memcpy (buf + 16, raw_buf, 16);
3379 /* Read upper 256bits. */
3380 status = regcache_raw_read (regcache,
3381 tdep->zmm0h_regnum + regnum,
3383 if (status != REG_VALID)
3384 mark_value_bytes_unavailable (result_value, 32, 32);
3386 memcpy (buf + 32, raw_buf, 32);
3388 else if (i386_ymm_regnum_p (gdbarch, regnum))
3390 regnum -= tdep->ymm0_regnum;
3392 /* Extract (always little endian). Read lower 128bits. */
3393 status = regcache_raw_read (regcache,
3394 I387_XMM0_REGNUM (tdep) + regnum,
3396 if (status != REG_VALID)
3397 mark_value_bytes_unavailable (result_value, 0, 16);
3399 memcpy (buf, raw_buf, 16);
3400 /* Read upper 128bits. */
3401 status = regcache_raw_read (regcache,
3402 tdep->ymm0h_regnum + regnum,
3404 if (status != REG_VALID)
3405 mark_value_bytes_unavailable (result_value, 16, 32);
3407 memcpy (buf + 16, raw_buf, 16);
3409 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3411 regnum -= tdep->ymm16_regnum;
3412 /* Extract (always little endian). Read lower 128bits. */
3413 status = regcache_raw_read (regcache,
3414 I387_XMM16_REGNUM (tdep) + regnum,
3416 if (status != REG_VALID)
3417 mark_value_bytes_unavailable (result_value, 0, 16);
3419 memcpy (buf, raw_buf, 16);
3420 /* Read upper 128bits. */
3421 status = regcache_raw_read (regcache,
3422 tdep->ymm16h_regnum + regnum,
3424 if (status != REG_VALID)
3425 mark_value_bytes_unavailable (result_value, 16, 16);
3427 memcpy (buf + 16, raw_buf, 16);
3429 else if (i386_word_regnum_p (gdbarch, regnum))
3431 int gpnum = regnum - tdep->ax_regnum;
3433 /* Extract (always little endian). */
3434 status = regcache_raw_read (regcache, gpnum, raw_buf);
3435 if (status != REG_VALID)
3436 mark_value_bytes_unavailable (result_value, 0,
3437 TYPE_LENGTH (value_type (result_value)));
3439 memcpy (buf, raw_buf, 2);
3441 else if (i386_byte_regnum_p (gdbarch, regnum))
3443 int gpnum = regnum - tdep->al_regnum;
3445 /* Extract (always little endian). We read both lower and
3447 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3448 if (status != REG_VALID)
3449 mark_value_bytes_unavailable (result_value, 0,
3450 TYPE_LENGTH (value_type (result_value)));
3451 else if (gpnum >= 4)
3452 memcpy (buf, raw_buf + 1, 1);
3454 memcpy (buf, raw_buf, 1);
3457 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3461 static struct value *
3462 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3463 struct regcache *regcache,
3466 struct value *result;
3468 result = allocate_value (register_type (gdbarch, regnum));
3469 VALUE_LVAL (result) = lval_register;
3470 VALUE_REGNUM (result) = regnum;
3472 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3478 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3479 int regnum, const gdb_byte *buf)
3481 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3483 if (i386_mmx_regnum_p (gdbarch, regnum))
3485 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3488 regcache_raw_read (regcache, fpnum, raw_buf);
3489 /* ... Modify ... (always little endian). */
3490 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3492 regcache_raw_write (regcache, fpnum, raw_buf);
3496 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3498 if (i386_bnd_regnum_p (gdbarch, regnum))
3500 ULONGEST upper, lower;
3501 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3502 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3504 /* New values from input value. */
3505 regnum -= tdep->bnd0_regnum;
3506 lower = extract_unsigned_integer (buf, size, byte_order);
3507 upper = extract_unsigned_integer (buf + size, size, byte_order);
3509 /* Fetching register buffer. */
3510 regcache_raw_read (regcache,
3511 I387_BND0R_REGNUM (tdep) + regnum,
3516 /* Set register bits. */
3517 memcpy (raw_buf, &lower, 8);
3518 memcpy (raw_buf + 8, &upper, 8);
3521 regcache_raw_write (regcache,
3522 I387_BND0R_REGNUM (tdep) + regnum,
3525 else if (i386_k_regnum_p (gdbarch, regnum))
3527 regnum -= tdep->k0_regnum;
3529 regcache_raw_write (regcache,
3530 tdep->k0_regnum + regnum,
3533 else if (i386_zmm_regnum_p (gdbarch, regnum))
3535 regnum -= tdep->zmm0_regnum;
3537 if (regnum < num_lower_zmm_regs)
3539 /* Write lower 128bits. */
3540 regcache_raw_write (regcache,
3541 I387_XMM0_REGNUM (tdep) + regnum,
3543 /* Write upper 128bits. */
3544 regcache_raw_write (regcache,
3545 I387_YMM0_REGNUM (tdep) + regnum,
3550 /* Write lower 128bits. */
3551 regcache_raw_write (regcache,
3552 I387_XMM16_REGNUM (tdep) + regnum
3553 - num_lower_zmm_regs,
3555 /* Write upper 128bits. */
3556 regcache_raw_write (regcache,
3557 I387_YMM16H_REGNUM (tdep) + regnum
3558 - num_lower_zmm_regs,
3561 /* Write upper 256bits. */
3562 regcache_raw_write (regcache,
3563 tdep->zmm0h_regnum + regnum,
3566 else if (i386_ymm_regnum_p (gdbarch, regnum))
3568 regnum -= tdep->ymm0_regnum;
3570 /* ... Write lower 128bits. */
3571 regcache_raw_write (regcache,
3572 I387_XMM0_REGNUM (tdep) + regnum,
3574 /* ... Write upper 128bits. */
3575 regcache_raw_write (regcache,
3576 tdep->ymm0h_regnum + regnum,
3579 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3581 regnum -= tdep->ymm16_regnum;
3583 /* ... Write lower 128bits. */
3584 regcache_raw_write (regcache,
3585 I387_XMM16_REGNUM (tdep) + regnum,
3587 /* ... Write upper 128bits. */
3588 regcache_raw_write (regcache,
3589 tdep->ymm16h_regnum + regnum,
3592 else if (i386_word_regnum_p (gdbarch, regnum))
3594 int gpnum = regnum - tdep->ax_regnum;
3597 regcache_raw_read (regcache, gpnum, raw_buf);
3598 /* ... Modify ... (always little endian). */
3599 memcpy (raw_buf, buf, 2);
3601 regcache_raw_write (regcache, gpnum, raw_buf);
3603 else if (i386_byte_regnum_p (gdbarch, regnum))
3605 int gpnum = regnum - tdep->al_regnum;
3607 /* Read ... We read both lower and upper registers. */
3608 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3609 /* ... Modify ... (always little endian). */
3611 memcpy (raw_buf + 1, buf, 1);
3613 memcpy (raw_buf, buf, 1);
3615 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3618 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3622 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3625 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
3626 struct agent_expr *ax, int regnum)
3628 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3630 if (i386_mmx_regnum_p (gdbarch, regnum))
3632 /* MMX to FPU register mapping depends on current TOS. Let's just
3633 not care and collect everything... */
3636 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3637 for (i = 0; i < 8; i++)
3638 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3641 else if (i386_bnd_regnum_p (gdbarch, regnum))
3643 regnum -= tdep->bnd0_regnum;
3644 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3647 else if (i386_k_regnum_p (gdbarch, regnum))
3649 regnum -= tdep->k0_regnum;
3650 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3653 else if (i386_zmm_regnum_p (gdbarch, regnum))
3655 regnum -= tdep->zmm0_regnum;
3656 if (regnum < num_lower_zmm_regs)
3658 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3659 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3663 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
3664 - num_lower_zmm_regs);
3665 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
3666 - num_lower_zmm_regs);
3668 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3671 else if (i386_ymm_regnum_p (gdbarch, regnum))
3673 regnum -= tdep->ymm0_regnum;
3674 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3675 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3678 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3680 regnum -= tdep->ymm16_regnum;
3681 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3682 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3685 else if (i386_word_regnum_p (gdbarch, regnum))
3687 int gpnum = regnum - tdep->ax_regnum;
3689 ax_reg_mask (ax, gpnum);
3692 else if (i386_byte_regnum_p (gdbarch, regnum))
3694 int gpnum = regnum - tdep->al_regnum;
3696 ax_reg_mask (ax, gpnum % 4);
3700 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3705 /* Return the register number of the register allocated by GCC after
3706 REGNUM, or -1 if there is no such register. */
3709 i386_next_regnum (int regnum)
3711 /* GCC allocates the registers in the order:
3713 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3715 Since storing a variable in %esp doesn't make any sense we return
3716 -1 for %ebp and for %esp itself. */
3717 static int next_regnum[] =
3719 I386_EDX_REGNUM, /* Slot for %eax. */
3720 I386_EBX_REGNUM, /* Slot for %ecx. */
3721 I386_ECX_REGNUM, /* Slot for %edx. */
3722 I386_ESI_REGNUM, /* Slot for %ebx. */
3723 -1, -1, /* Slots for %esp and %ebp. */
3724 I386_EDI_REGNUM, /* Slot for %esi. */
3725 I386_EBP_REGNUM /* Slot for %edi. */
3728 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3729 return next_regnum[regnum];
3734 /* Return nonzero if a value of type TYPE stored in register REGNUM
3735 needs any special handling. */
3738 i386_convert_register_p (struct gdbarch *gdbarch,
3739 int regnum, struct type *type)
3741 int len = TYPE_LENGTH (type);
3743 /* Values may be spread across multiple registers. Most debugging
3744 formats aren't expressive enough to specify the locations, so
3745 some heuristics is involved. Right now we only handle types that
3746 have a length that is a multiple of the word size, since GCC
3747 doesn't seem to put any other types into registers. */
3748 if (len > 4 && len % 4 == 0)
3750 int last_regnum = regnum;
3754 last_regnum = i386_next_regnum (last_regnum);
3758 if (last_regnum != -1)
3762 return i387_convert_register_p (gdbarch, regnum, type);
3765 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3766 return its contents in TO. */
3769 i386_register_to_value (struct frame_info *frame, int regnum,
3770 struct type *type, gdb_byte *to,
3771 int *optimizedp, int *unavailablep)
3773 struct gdbarch *gdbarch = get_frame_arch (frame);
3774 int len = TYPE_LENGTH (type);
3776 if (i386_fp_regnum_p (gdbarch, regnum))
3777 return i387_register_to_value (frame, regnum, type, to,
3778 optimizedp, unavailablep);
3780 /* Read a value spread across multiple registers. */
3782 gdb_assert (len > 4 && len % 4 == 0);
3786 gdb_assert (regnum != -1);
3787 gdb_assert (register_size (gdbarch, regnum) == 4);
3789 if (!get_frame_register_bytes (frame, regnum, 0,
3790 register_size (gdbarch, regnum),
3791 to, optimizedp, unavailablep))
3794 regnum = i386_next_regnum (regnum);
3799 *optimizedp = *unavailablep = 0;
3803 /* Write the contents FROM of a value of type TYPE into register
3804 REGNUM in frame FRAME. */
3807 i386_value_to_register (struct frame_info *frame, int regnum,
3808 struct type *type, const gdb_byte *from)
3810 int len = TYPE_LENGTH (type);
3812 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3814 i387_value_to_register (frame, regnum, type, from);
3818 /* Write a value spread across multiple registers. */
3820 gdb_assert (len > 4 && len % 4 == 0);
3824 gdb_assert (regnum != -1);
3825 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3827 put_frame_register (frame, regnum, from);
3828 regnum = i386_next_regnum (regnum);
3834 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3835 in the general-purpose register set REGSET to register cache
3836 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3839 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3840 int regnum, const void *gregs, size_t len)
3842 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3843 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3844 const gdb_byte *regs = (const gdb_byte *) gregs;
3847 gdb_assert (len >= tdep->sizeof_gregset);
3849 for (i = 0; i < tdep->gregset_num_regs; i++)
3851 if ((regnum == i || regnum == -1)
3852 && tdep->gregset_reg_offset[i] != -1)
3853 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3857 /* Collect register REGNUM from the register cache REGCACHE and store
3858 it in the buffer specified by GREGS and LEN as described by the
3859 general-purpose register set REGSET. If REGNUM is -1, do this for
3860 all registers in REGSET. */
3863 i386_collect_gregset (const struct regset *regset,
3864 const struct regcache *regcache,
3865 int regnum, void *gregs, size_t len)
3867 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3868 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3869 gdb_byte *regs = (gdb_byte *) gregs;
3872 gdb_assert (len >= tdep->sizeof_gregset);
3874 for (i = 0; i < tdep->gregset_num_regs; i++)
3876 if ((regnum == i || regnum == -1)
3877 && tdep->gregset_reg_offset[i] != -1)
3878 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3882 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3883 in the floating-point register set REGSET to register cache
3884 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3887 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3888 int regnum, const void *fpregs, size_t len)
3890 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3891 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3893 if (len == I387_SIZEOF_FXSAVE)
3895 i387_supply_fxsave (regcache, regnum, fpregs);
3899 gdb_assert (len >= tdep->sizeof_fpregset);
3900 i387_supply_fsave (regcache, regnum, fpregs);
3903 /* Collect register REGNUM from the register cache REGCACHE and store
3904 it in the buffer specified by FPREGS and LEN as described by the
3905 floating-point register set REGSET. If REGNUM is -1, do this for
3906 all registers in REGSET. */
3909 i386_collect_fpregset (const struct regset *regset,
3910 const struct regcache *regcache,
3911 int regnum, void *fpregs, size_t len)
3913 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3914 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3916 if (len == I387_SIZEOF_FXSAVE)
3918 i387_collect_fxsave (regcache, regnum, fpregs);
3922 gdb_assert (len >= tdep->sizeof_fpregset);
3923 i387_collect_fsave (regcache, regnum, fpregs);
3926 /* Register set definitions. */
3928 const struct regset i386_gregset =
3930 NULL, i386_supply_gregset, i386_collect_gregset
3933 const struct regset i386_fpregset =
3935 NULL, i386_supply_fpregset, i386_collect_fpregset
3938 /* Default iterator over core file register note sections. */
3941 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3942 iterate_over_regset_sections_cb *cb,
3944 const struct regcache *regcache)
3946 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3948 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3949 if (tdep->sizeof_fpregset)
3950 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3954 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3957 i386_pe_skip_trampoline_code (struct frame_info *frame,
3958 CORE_ADDR pc, char *name)
3960 struct gdbarch *gdbarch = get_frame_arch (frame);
3961 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3964 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3966 unsigned long indirect =
3967 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3968 struct minimal_symbol *indsym =
3969 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3970 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3974 if (startswith (symname, "__imp_")
3975 || startswith (symname, "_imp_"))
3977 read_memory_unsigned_integer (indirect, 4, byte_order);
3980 return 0; /* Not a trampoline. */
3984 /* Return whether the THIS_FRAME corresponds to a sigtramp
3988 i386_sigtramp_p (struct frame_info *this_frame)
3990 CORE_ADDR pc = get_frame_pc (this_frame);
3993 find_pc_partial_function (pc, &name, NULL, NULL);
3994 return (name && strcmp ("_sigtramp", name) == 0);
3998 /* We have two flavours of disassembly. The machinery on this page
3999 deals with switching between those. */
4002 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
4004 gdb_assert (disassembly_flavor == att_flavor
4005 || disassembly_flavor == intel_flavor);
4007 info->disassembler_options = disassembly_flavor;
4009 return default_print_insn (pc, info);
4013 /* There are a few i386 architecture variants that differ only
4014 slightly from the generic i386 target. For now, we don't give them
4015 their own source file, but include them here. As a consequence,
4016 they'll always be included. */
4018 /* System V Release 4 (SVR4). */
4020 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4024 i386_svr4_sigtramp_p (struct frame_info *this_frame)
4026 CORE_ADDR pc = get_frame_pc (this_frame);
4029 /* The origin of these symbols is currently unknown. */
4030 find_pc_partial_function (pc, &name, NULL, NULL);
4031 return (name && (strcmp ("_sigreturn", name) == 0
4032 || strcmp ("sigvechandler", name) == 0));
4035 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4036 address of the associated sigcontext (ucontext) structure. */
4039 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
4041 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4042 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4046 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4047 sp = extract_unsigned_integer (buf, 4, byte_order);
4049 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4054 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4058 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
4060 return (*s == '$' /* Literal number. */
4061 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4062 || (*s == '(' && s[1] == '%') /* Register indirection. */
4063 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4066 /* Helper function for i386_stap_parse_special_token.
4068 This function parses operands of the form `-8+3+1(%rbp)', which
4069 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4071 Return 1 if the operand was parsed successfully, zero
4075 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
4076 struct stap_parse_info *p)
4078 const char *s = p->arg;
4080 if (isdigit (*s) || *s == '-' || *s == '+')
4084 long displacements[3];
4100 if (!isdigit ((unsigned char) *s))
4103 displacements[0] = strtol (s, &endp, 10);
4106 if (*s != '+' && *s != '-')
4108 /* We are not dealing with a triplet. */
4121 if (!isdigit ((unsigned char) *s))
4124 displacements[1] = strtol (s, &endp, 10);
4127 if (*s != '+' && *s != '-')
4129 /* We are not dealing with a triplet. */
4142 if (!isdigit ((unsigned char) *s))
4145 displacements[2] = strtol (s, &endp, 10);
4148 if (*s != '(' || s[1] != '%')
4154 while (isalnum (*s))
4160 len = s - start - 1;
4161 regname = (char *) alloca (len + 1);
4163 strncpy (regname, start, len);
4164 regname[len] = '\0';
4166 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4167 error (_("Invalid register name `%s' on expression `%s'."),
4168 regname, p->saved_arg);
4170 for (i = 0; i < 3; i++)
4172 write_exp_elt_opcode (&p->pstate, OP_LONG);
4174 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4175 write_exp_elt_longcst (&p->pstate, displacements[i]);
4176 write_exp_elt_opcode (&p->pstate, OP_LONG);
4178 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4181 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4184 write_exp_string (&p->pstate, str);
4185 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4187 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4188 write_exp_elt_type (&p->pstate,
4189 builtin_type (gdbarch)->builtin_data_ptr);
4190 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4192 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4193 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4194 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4196 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4197 write_exp_elt_type (&p->pstate,
4198 lookup_pointer_type (p->arg_type));
4199 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4201 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4211 /* Helper function for i386_stap_parse_special_token.
4213 This function parses operands of the form `register base +
4214 (register index * size) + offset', as represented in
4215 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4217 Return 1 if the operand was parsed successfully, zero
4221 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4222 struct stap_parse_info *p)
4224 const char *s = p->arg;
4226 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4228 int offset_minus = 0;
4237 struct stoken base_token, index_token;
4247 if (offset_minus && !isdigit (*s))
4254 offset = strtol (s, &endp, 10);
4258 if (*s != '(' || s[1] != '%')
4264 while (isalnum (*s))
4267 if (*s != ',' || s[1] != '%')
4270 len_base = s - start;
4271 base = (char *) alloca (len_base + 1);
4272 strncpy (base, start, len_base);
4273 base[len_base] = '\0';
4275 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4276 error (_("Invalid register name `%s' on expression `%s'."),
4277 base, p->saved_arg);
4282 while (isalnum (*s))
4285 len_index = s - start;
4286 index = (char *) alloca (len_index + 1);
4287 strncpy (index, start, len_index);
4288 index[len_index] = '\0';
4290 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4291 error (_("Invalid register name `%s' on expression `%s'."),
4292 index, p->saved_arg);
4294 if (*s != ',' && *s != ')')
4310 size = strtol (s, &endp, 10);
4321 write_exp_elt_opcode (&p->pstate, OP_LONG);
4322 write_exp_elt_type (&p->pstate,
4323 builtin_type (gdbarch)->builtin_long);
4324 write_exp_elt_longcst (&p->pstate, offset);
4325 write_exp_elt_opcode (&p->pstate, OP_LONG);
4327 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4330 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4331 base_token.ptr = base;
4332 base_token.length = len_base;
4333 write_exp_string (&p->pstate, base_token);
4334 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4337 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4339 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4340 index_token.ptr = index;
4341 index_token.length = len_index;
4342 write_exp_string (&p->pstate, index_token);
4343 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4347 write_exp_elt_opcode (&p->pstate, OP_LONG);
4348 write_exp_elt_type (&p->pstate,
4349 builtin_type (gdbarch)->builtin_long);
4350 write_exp_elt_longcst (&p->pstate, size);
4351 write_exp_elt_opcode (&p->pstate, OP_LONG);
4353 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4354 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4357 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4359 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4360 write_exp_elt_type (&p->pstate,
4361 lookup_pointer_type (p->arg_type));
4362 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4364 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4374 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4378 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4379 struct stap_parse_info *p)
4381 /* In order to parse special tokens, we use a state-machine that go
4382 through every known token and try to get a match. */
4386 THREE_ARG_DISPLACEMENT,
4391 current_state = TRIPLET;
4393 /* The special tokens to be parsed here are:
4395 - `register base + (register index * size) + offset', as represented
4396 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4398 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4399 `*(-8 + 3 - 1 + (void *) $eax)'. */
4401 while (current_state != DONE)
4403 switch (current_state)
4406 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4410 case THREE_ARG_DISPLACEMENT:
4411 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4416 /* Advancing to the next state. */
4425 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4426 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4429 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4431 return "(x86_64|i.86)";
4439 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4441 static const char *const stap_integer_prefixes[] = { "$", NULL };
4442 static const char *const stap_register_prefixes[] = { "%", NULL };
4443 static const char *const stap_register_indirection_prefixes[] = { "(",
4445 static const char *const stap_register_indirection_suffixes[] = { ")",
4448 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4449 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4451 /* Registering SystemTap handlers. */
4452 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4453 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4454 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4455 stap_register_indirection_prefixes);
4456 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4457 stap_register_indirection_suffixes);
4458 set_gdbarch_stap_is_single_operand (gdbarch,
4459 i386_stap_is_single_operand);
4460 set_gdbarch_stap_parse_special_token (gdbarch,
4461 i386_stap_parse_special_token);
4464 /* System V Release 4 (SVR4). */
4467 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4469 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4471 /* System V Release 4 uses ELF. */
4472 i386_elf_init_abi (info, gdbarch);
4474 /* System V Release 4 has shared libraries. */
4475 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4477 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4478 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4479 tdep->sc_pc_offset = 36 + 14 * 4;
4480 tdep->sc_sp_offset = 36 + 17 * 4;
4482 tdep->jb_pc_offset = 20;
4487 /* i386 register groups. In addition to the normal groups, add "mmx"
4490 static struct reggroup *i386_sse_reggroup;
4491 static struct reggroup *i386_mmx_reggroup;
4494 i386_init_reggroups (void)
4496 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4497 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4501 i386_add_reggroups (struct gdbarch *gdbarch)
4503 reggroup_add (gdbarch, i386_sse_reggroup);
4504 reggroup_add (gdbarch, i386_mmx_reggroup);
4505 reggroup_add (gdbarch, general_reggroup);
4506 reggroup_add (gdbarch, float_reggroup);
4507 reggroup_add (gdbarch, all_reggroup);
4508 reggroup_add (gdbarch, save_reggroup);
4509 reggroup_add (gdbarch, restore_reggroup);
4510 reggroup_add (gdbarch, vector_reggroup);
4511 reggroup_add (gdbarch, system_reggroup);
4515 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4516 struct reggroup *group)
4518 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4519 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4520 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4521 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4522 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4523 avx512_p, avx_p, sse_p, pkru_regnum_p;
4525 /* Don't include pseudo registers, except for MMX, in any register
4527 if (i386_byte_regnum_p (gdbarch, regnum))
4530 if (i386_word_regnum_p (gdbarch, regnum))
4533 if (i386_dword_regnum_p (gdbarch, regnum))
4536 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4537 if (group == i386_mmx_reggroup)
4538 return mmx_regnum_p;
4540 pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum);
4541 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4542 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4543 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4544 if (group == i386_sse_reggroup)
4545 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4547 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4548 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4549 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4551 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4552 == X86_XSTATE_AVX_AVX512_MASK);
4553 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4554 == X86_XSTATE_AVX_MASK) && !avx512_p;
4555 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4556 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4558 if (group == vector_reggroup)
4559 return (mmx_regnum_p
4560 || (zmm_regnum_p && avx512_p)
4561 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4562 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4565 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4566 || i386_fpc_regnum_p (gdbarch, regnum));
4567 if (group == float_reggroup)
4570 /* For "info reg all", don't include upper YMM registers nor XMM
4571 registers when AVX is supported. */
4572 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4573 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4574 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4575 if (group == all_reggroup
4576 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4577 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4579 || ymmh_avx512_regnum_p
4583 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4584 if (group == all_reggroup
4585 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4586 return bnd_regnum_p;
4588 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4589 if (group == all_reggroup
4590 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4593 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4594 if (group == all_reggroup
4595 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4596 return mpx_ctrl_regnum_p;
4598 if (group == general_reggroup)
4599 return (!fp_regnum_p
4603 && !xmm_avx512_regnum_p
4606 && !ymm_avx512_regnum_p
4607 && !ymmh_avx512_regnum_p
4610 && !mpx_ctrl_regnum_p
4615 return default_register_reggroup_p (gdbarch, regnum, group);
4619 /* Get the ARGIth function argument for the current function. */
4622 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4625 struct gdbarch *gdbarch = get_frame_arch (frame);
4626 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4627 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4628 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4631 #define PREFIX_REPZ 0x01
4632 #define PREFIX_REPNZ 0x02
4633 #define PREFIX_LOCK 0x04
4634 #define PREFIX_DATA 0x08
4635 #define PREFIX_ADDR 0x10
4647 /* i386 arith/logic operations */
4660 struct i386_record_s
4662 struct gdbarch *gdbarch;
4663 struct regcache *regcache;
4664 CORE_ADDR orig_addr;
4670 uint8_t mod, reg, rm;
4679 /* Parse the "modrm" part of the memory address irp->addr points at.
4680 Returns -1 if something goes wrong, 0 otherwise. */
4683 i386_record_modrm (struct i386_record_s *irp)
4685 struct gdbarch *gdbarch = irp->gdbarch;
4687 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4691 irp->mod = (irp->modrm >> 6) & 3;
4692 irp->reg = (irp->modrm >> 3) & 7;
4693 irp->rm = irp->modrm & 7;
4698 /* Extract the memory address that the current instruction writes to,
4699 and return it in *ADDR. Return -1 if something goes wrong. */
4702 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4704 struct gdbarch *gdbarch = irp->gdbarch;
4705 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4710 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4717 uint8_t base = irp->rm;
4722 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4725 scale = (byte >> 6) & 3;
4726 index = ((byte >> 3) & 7) | irp->rex_x;
4734 if ((base & 7) == 5)
4737 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4740 *addr = extract_signed_integer (buf, 4, byte_order);
4741 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4742 *addr += irp->addr + irp->rip_offset;
4746 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4749 *addr = (int8_t) buf[0];
4752 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4754 *addr = extract_signed_integer (buf, 4, byte_order);
4762 if (base == 4 && irp->popl_esp_hack)
4763 *addr += irp->popl_esp_hack;
4764 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4767 if (irp->aflag == 2)
4772 *addr = (uint32_t) (offset64 + *addr);
4774 if (havesib && (index != 4 || scale != 0))
4776 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4778 if (irp->aflag == 2)
4779 *addr += offset64 << scale;
4781 *addr = (uint32_t) (*addr + (offset64 << scale));
4786 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4787 address from 32-bit to 64-bit. */
4788 *addr = (uint32_t) *addr;
4799 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4802 *addr = extract_signed_integer (buf, 2, byte_order);
4808 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4811 *addr = (int8_t) buf[0];
4814 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4817 *addr = extract_signed_integer (buf, 2, byte_order);
4824 regcache_raw_read_unsigned (irp->regcache,
4825 irp->regmap[X86_RECORD_REBX_REGNUM],
4827 *addr = (uint32_t) (*addr + offset64);
4828 regcache_raw_read_unsigned (irp->regcache,
4829 irp->regmap[X86_RECORD_RESI_REGNUM],
4831 *addr = (uint32_t) (*addr + offset64);
4834 regcache_raw_read_unsigned (irp->regcache,
4835 irp->regmap[X86_RECORD_REBX_REGNUM],
4837 *addr = (uint32_t) (*addr + offset64);
4838 regcache_raw_read_unsigned (irp->regcache,
4839 irp->regmap[X86_RECORD_REDI_REGNUM],
4841 *addr = (uint32_t) (*addr + offset64);
4844 regcache_raw_read_unsigned (irp->regcache,
4845 irp->regmap[X86_RECORD_REBP_REGNUM],
4847 *addr = (uint32_t) (*addr + offset64);
4848 regcache_raw_read_unsigned (irp->regcache,
4849 irp->regmap[X86_RECORD_RESI_REGNUM],
4851 *addr = (uint32_t) (*addr + offset64);
4854 regcache_raw_read_unsigned (irp->regcache,
4855 irp->regmap[X86_RECORD_REBP_REGNUM],
4857 *addr = (uint32_t) (*addr + offset64);
4858 regcache_raw_read_unsigned (irp->regcache,
4859 irp->regmap[X86_RECORD_REDI_REGNUM],
4861 *addr = (uint32_t) (*addr + offset64);
4864 regcache_raw_read_unsigned (irp->regcache,
4865 irp->regmap[X86_RECORD_RESI_REGNUM],
4867 *addr = (uint32_t) (*addr + offset64);
4870 regcache_raw_read_unsigned (irp->regcache,
4871 irp->regmap[X86_RECORD_REDI_REGNUM],
4873 *addr = (uint32_t) (*addr + offset64);
4876 regcache_raw_read_unsigned (irp->regcache,
4877 irp->regmap[X86_RECORD_REBP_REGNUM],
4879 *addr = (uint32_t) (*addr + offset64);
4882 regcache_raw_read_unsigned (irp->regcache,
4883 irp->regmap[X86_RECORD_REBX_REGNUM],
4885 *addr = (uint32_t) (*addr + offset64);
4895 /* Record the address and contents of the memory that will be changed
4896 by the current instruction. Return -1 if something goes wrong, 0
4900 i386_record_lea_modrm (struct i386_record_s *irp)
4902 struct gdbarch *gdbarch = irp->gdbarch;
4905 if (irp->override >= 0)
4907 if (record_full_memory_query)
4910 Process record ignores the memory change of instruction at address %s\n\
4911 because it can't get the value of the segment register.\n\
4912 Do you want to stop the program?"),
4913 paddress (gdbarch, irp->orig_addr)))
4920 if (i386_record_lea_modrm_addr (irp, &addr))
4923 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4929 /* Record the effects of a push operation. Return -1 if something
4930 goes wrong, 0 otherwise. */
4933 i386_record_push (struct i386_record_s *irp, int size)
4937 if (record_full_arch_list_add_reg (irp->regcache,
4938 irp->regmap[X86_RECORD_RESP_REGNUM]))
4940 regcache_raw_read_unsigned (irp->regcache,
4941 irp->regmap[X86_RECORD_RESP_REGNUM],
4943 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4950 /* Defines contents to record. */
4951 #define I386_SAVE_FPU_REGS 0xfffd
4952 #define I386_SAVE_FPU_ENV 0xfffe
4953 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4955 /* Record the values of the floating point registers which will be
4956 changed by the current instruction. Returns -1 if something is
4957 wrong, 0 otherwise. */
4959 static int i386_record_floats (struct gdbarch *gdbarch,
4960 struct i386_record_s *ir,
4963 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4966 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4967 happen. Currently we store st0-st7 registers, but we need not store all
4968 registers all the time, in future we use ftag register and record only
4969 those who are not marked as an empty. */
4971 if (I386_SAVE_FPU_REGS == iregnum)
4973 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4975 if (record_full_arch_list_add_reg (ir->regcache, i))
4979 else if (I386_SAVE_FPU_ENV == iregnum)
4981 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4983 if (record_full_arch_list_add_reg (ir->regcache, i))
4987 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4989 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4991 if (record_full_arch_list_add_reg (ir->regcache, i))
4995 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4996 (iregnum <= I387_FOP_REGNUM (tdep)))
4998 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
5003 /* Parameter error. */
5006 if(I386_SAVE_FPU_ENV != iregnum)
5008 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5010 if (record_full_arch_list_add_reg (ir->regcache, i))
5017 /* Parse the current instruction, and record the values of the
5018 registers and memory that will be changed by the current
5019 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5021 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5022 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5025 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5026 CORE_ADDR input_addr)
5028 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5034 gdb_byte buf[I386_MAX_REGISTER_SIZE];
5035 struct i386_record_s ir;
5036 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5040 memset (&ir, 0, sizeof (struct i386_record_s));
5041 ir.regcache = regcache;
5042 ir.addr = input_addr;
5043 ir.orig_addr = input_addr;
5047 ir.popl_esp_hack = 0;
5048 ir.regmap = tdep->record_regmap;
5049 ir.gdbarch = gdbarch;
5051 if (record_debug > 1)
5052 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5054 paddress (gdbarch, ir.addr));
5059 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5062 switch (opcode8) /* Instruction prefixes */
5064 case REPE_PREFIX_OPCODE:
5065 prefixes |= PREFIX_REPZ;
5067 case REPNE_PREFIX_OPCODE:
5068 prefixes |= PREFIX_REPNZ;
5070 case LOCK_PREFIX_OPCODE:
5071 prefixes |= PREFIX_LOCK;
5073 case CS_PREFIX_OPCODE:
5074 ir.override = X86_RECORD_CS_REGNUM;
5076 case SS_PREFIX_OPCODE:
5077 ir.override = X86_RECORD_SS_REGNUM;
5079 case DS_PREFIX_OPCODE:
5080 ir.override = X86_RECORD_DS_REGNUM;
5082 case ES_PREFIX_OPCODE:
5083 ir.override = X86_RECORD_ES_REGNUM;
5085 case FS_PREFIX_OPCODE:
5086 ir.override = X86_RECORD_FS_REGNUM;
5088 case GS_PREFIX_OPCODE:
5089 ir.override = X86_RECORD_GS_REGNUM;
5091 case DATA_PREFIX_OPCODE:
5092 prefixes |= PREFIX_DATA;
5094 case ADDR_PREFIX_OPCODE:
5095 prefixes |= PREFIX_ADDR;
5097 case 0x40: /* i386 inc %eax */
5098 case 0x41: /* i386 inc %ecx */
5099 case 0x42: /* i386 inc %edx */
5100 case 0x43: /* i386 inc %ebx */
5101 case 0x44: /* i386 inc %esp */
5102 case 0x45: /* i386 inc %ebp */
5103 case 0x46: /* i386 inc %esi */
5104 case 0x47: /* i386 inc %edi */
5105 case 0x48: /* i386 dec %eax */
5106 case 0x49: /* i386 dec %ecx */
5107 case 0x4a: /* i386 dec %edx */
5108 case 0x4b: /* i386 dec %ebx */
5109 case 0x4c: /* i386 dec %esp */
5110 case 0x4d: /* i386 dec %ebp */
5111 case 0x4e: /* i386 dec %esi */
5112 case 0x4f: /* i386 dec %edi */
5113 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5116 rex_w = (opcode8 >> 3) & 1;
5117 rex_r = (opcode8 & 0x4) << 1;
5118 ir.rex_x = (opcode8 & 0x2) << 2;
5119 ir.rex_b = (opcode8 & 0x1) << 3;
5121 else /* 32 bit target */
5130 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5136 if (prefixes & PREFIX_DATA)
5139 if (prefixes & PREFIX_ADDR)
5141 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5144 /* Now check op code. */
5145 opcode = (uint32_t) opcode8;
5150 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5153 opcode = (uint32_t) opcode8 | 0x0f00;
5157 case 0x00: /* arith & logic */
5205 if (((opcode >> 3) & 7) != OP_CMPL)
5207 if ((opcode & 1) == 0)
5210 ir.ot = ir.dflag + OT_WORD;
5212 switch ((opcode >> 1) & 3)
5214 case 0: /* OP Ev, Gv */
5215 if (i386_record_modrm (&ir))
5219 if (i386_record_lea_modrm (&ir))
5225 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5227 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5230 case 1: /* OP Gv, Ev */
5231 if (i386_record_modrm (&ir))
5234 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5238 case 2: /* OP A, Iv */
5239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5243 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5246 case 0x80: /* GRP1 */
5250 if (i386_record_modrm (&ir))
5253 if (ir.reg != OP_CMPL)
5255 if ((opcode & 1) == 0)
5258 ir.ot = ir.dflag + OT_WORD;
5265 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5266 if (i386_record_lea_modrm (&ir))
5270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5275 case 0x40: /* inc */
5284 case 0x48: /* dec */
5293 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5294 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5297 case 0xf6: /* GRP3 */
5299 if ((opcode & 1) == 0)
5302 ir.ot = ir.dflag + OT_WORD;
5303 if (i386_record_modrm (&ir))
5306 if (ir.mod != 3 && ir.reg == 0)
5307 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5312 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5318 if (i386_record_lea_modrm (&ir))
5324 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5326 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5328 if (ir.reg == 3) /* neg */
5329 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5336 if (ir.ot != OT_BYTE)
5337 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5338 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5342 opcode = opcode << 8 | ir.modrm;
5348 case 0xfe: /* GRP4 */
5349 case 0xff: /* GRP5 */
5350 if (i386_record_modrm (&ir))
5352 if (ir.reg >= 2 && opcode == 0xfe)
5355 opcode = opcode << 8 | ir.modrm;
5362 if ((opcode & 1) == 0)
5365 ir.ot = ir.dflag + OT_WORD;
5368 if (i386_record_lea_modrm (&ir))
5374 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5378 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5381 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5383 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5385 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5388 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5389 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5391 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5398 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5400 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5405 opcode = opcode << 8 | ir.modrm;
5411 case 0x84: /* test */
5415 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5418 case 0x98: /* CWDE/CBW */
5419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5422 case 0x99: /* CDQ/CWD */
5423 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5427 case 0x0faf: /* imul */
5430 ir.ot = ir.dflag + OT_WORD;
5431 if (i386_record_modrm (&ir))
5434 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5435 else if (opcode == 0x6b)
5438 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5440 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5441 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5444 case 0x0fc0: /* xadd */
5446 if ((opcode & 1) == 0)
5449 ir.ot = ir.dflag + OT_WORD;
5450 if (i386_record_modrm (&ir))
5455 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5458 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5460 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5464 if (i386_record_lea_modrm (&ir))
5466 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5470 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5473 case 0x0fb0: /* cmpxchg */
5475 if ((opcode & 1) == 0)
5478 ir.ot = ir.dflag + OT_WORD;
5479 if (i386_record_modrm (&ir))
5484 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5485 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5487 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5491 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5492 if (i386_record_lea_modrm (&ir))
5495 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5498 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5499 if (i386_record_modrm (&ir))
5503 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5504 an extended opcode. rdrand has bits 110 (/6) and rdseed
5505 has bits 111 (/7). */
5506 if (ir.reg == 6 || ir.reg == 7)
5508 /* The storage register is described by the 3 R/M bits, but the
5509 REX.B prefix may be used to give access to registers
5510 R8~R15. In this case ir.rex_b + R/M will give us the register
5511 in the range R8~R15.
5513 REX.W may also be used to access 64-bit registers, but we
5514 already record entire registers and not just partial bits
5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm);
5517 /* These instructions also set conditional bits. */
5518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5523 /* We don't handle this particular instruction yet. */
5525 opcode = opcode << 8 | ir.modrm;
5529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5531 if (i386_record_lea_modrm (&ir))
5533 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5536 case 0x50: /* push */
5546 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5548 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5552 case 0x06: /* push es */
5553 case 0x0e: /* push cs */
5554 case 0x16: /* push ss */
5555 case 0x1e: /* push ds */
5556 if (ir.regmap[X86_RECORD_R8_REGNUM])
5561 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5565 case 0x0fa0: /* push fs */
5566 case 0x0fa8: /* push gs */
5567 if (ir.regmap[X86_RECORD_R8_REGNUM])
5572 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5576 case 0x60: /* pusha */
5577 if (ir.regmap[X86_RECORD_R8_REGNUM])
5582 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5586 case 0x58: /* pop */
5594 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5595 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5598 case 0x61: /* popa */
5599 if (ir.regmap[X86_RECORD_R8_REGNUM])
5604 for (regnum = X86_RECORD_REAX_REGNUM;
5605 regnum <= X86_RECORD_REDI_REGNUM;
5607 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5610 case 0x8f: /* pop */
5611 if (ir.regmap[X86_RECORD_R8_REGNUM])
5612 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5614 ir.ot = ir.dflag + OT_WORD;
5615 if (i386_record_modrm (&ir))
5618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5621 ir.popl_esp_hack = 1 << ir.ot;
5622 if (i386_record_lea_modrm (&ir))
5625 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5628 case 0xc8: /* enter */
5629 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5630 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5632 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5636 case 0xc9: /* leave */
5637 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5638 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5641 case 0x07: /* pop es */
5642 if (ir.regmap[X86_RECORD_R8_REGNUM])
5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5648 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5649 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5652 case 0x17: /* pop ss */
5653 if (ir.regmap[X86_RECORD_R8_REGNUM])
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5660 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5663 case 0x1f: /* pop ds */
5664 if (ir.regmap[X86_RECORD_R8_REGNUM])
5669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5674 case 0x0fa1: /* pop fs */
5675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5680 case 0x0fa9: /* pop gs */
5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5683 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5686 case 0x88: /* mov */
5690 if ((opcode & 1) == 0)
5693 ir.ot = ir.dflag + OT_WORD;
5695 if (i386_record_modrm (&ir))
5700 if (opcode == 0xc6 || opcode == 0xc7)
5701 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5702 if (i386_record_lea_modrm (&ir))
5707 if (opcode == 0xc6 || opcode == 0xc7)
5709 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5715 case 0x8a: /* mov */
5717 if ((opcode & 1) == 0)
5720 ir.ot = ir.dflag + OT_WORD;
5721 if (i386_record_modrm (&ir))
5724 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5726 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5729 case 0x8c: /* mov seg */
5730 if (i386_record_modrm (&ir))
5735 opcode = opcode << 8 | ir.modrm;
5740 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5744 if (i386_record_lea_modrm (&ir))
5749 case 0x8e: /* mov seg */
5750 if (i386_record_modrm (&ir))
5755 regnum = X86_RECORD_ES_REGNUM;
5758 regnum = X86_RECORD_SS_REGNUM;
5761 regnum = X86_RECORD_DS_REGNUM;
5764 regnum = X86_RECORD_FS_REGNUM;
5767 regnum = X86_RECORD_GS_REGNUM;
5771 opcode = opcode << 8 | ir.modrm;
5775 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5776 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5779 case 0x0fb6: /* movzbS */
5780 case 0x0fb7: /* movzwS */
5781 case 0x0fbe: /* movsbS */
5782 case 0x0fbf: /* movswS */
5783 if (i386_record_modrm (&ir))
5785 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5788 case 0x8d: /* lea */
5789 if (i386_record_modrm (&ir))
5794 opcode = opcode << 8 | ir.modrm;
5799 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5801 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5804 case 0xa0: /* mov EAX */
5807 case 0xd7: /* xlat */
5808 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5811 case 0xa2: /* mov EAX */
5813 if (ir.override >= 0)
5815 if (record_full_memory_query)
5818 Process record ignores the memory change of instruction at address %s\n\
5819 because it can't get the value of the segment register.\n\
5820 Do you want to stop the program?"),
5821 paddress (gdbarch, ir.orig_addr)))
5827 if ((opcode & 1) == 0)
5830 ir.ot = ir.dflag + OT_WORD;
5833 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5836 addr = extract_unsigned_integer (buf, 8, byte_order);
5840 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5843 addr = extract_unsigned_integer (buf, 4, byte_order);
5847 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5850 addr = extract_unsigned_integer (buf, 2, byte_order);
5852 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5857 case 0xb0: /* mov R, Ib */
5865 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5866 ? ((opcode & 0x7) | ir.rex_b)
5867 : ((opcode & 0x7) & 0x3));
5870 case 0xb8: /* mov R, Iv */
5878 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5881 case 0x91: /* xchg R, EAX */
5888 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5889 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5892 case 0x86: /* xchg Ev, Gv */
5894 if ((opcode & 1) == 0)
5897 ir.ot = ir.dflag + OT_WORD;
5898 if (i386_record_modrm (&ir))
5903 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5905 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5909 if (i386_record_lea_modrm (&ir))
5913 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5915 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5918 case 0xc4: /* les Gv */
5919 case 0xc5: /* lds Gv */
5920 if (ir.regmap[X86_RECORD_R8_REGNUM])
5926 case 0x0fb2: /* lss Gv */
5927 case 0x0fb4: /* lfs Gv */
5928 case 0x0fb5: /* lgs Gv */
5929 if (i386_record_modrm (&ir))
5937 opcode = opcode << 8 | ir.modrm;
5942 case 0xc4: /* les Gv */
5943 regnum = X86_RECORD_ES_REGNUM;
5945 case 0xc5: /* lds Gv */
5946 regnum = X86_RECORD_DS_REGNUM;
5948 case 0x0fb2: /* lss Gv */
5949 regnum = X86_RECORD_SS_REGNUM;
5951 case 0x0fb4: /* lfs Gv */
5952 regnum = X86_RECORD_FS_REGNUM;
5954 case 0x0fb5: /* lgs Gv */
5955 regnum = X86_RECORD_GS_REGNUM;
5958 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5959 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5960 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5963 case 0xc0: /* shifts */
5969 if ((opcode & 1) == 0)
5972 ir.ot = ir.dflag + OT_WORD;
5973 if (i386_record_modrm (&ir))
5975 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5977 if (i386_record_lea_modrm (&ir))
5983 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5985 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5987 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5994 if (i386_record_modrm (&ir))
5998 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
6003 if (i386_record_lea_modrm (&ir))
6008 case 0xd8: /* Floats. */
6016 if (i386_record_modrm (&ir))
6018 ir.reg |= ((opcode & 7) << 3);
6024 if (i386_record_lea_modrm_addr (&ir, &addr64))
6032 /* For fcom, ficom nothing to do. */
6038 /* For fcomp, ficomp pop FPU stack, store all. */
6039 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6066 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6067 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6068 of code, always affects st(0) register. */
6069 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6093 /* Handling fld, fild. */
6094 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6098 switch (ir.reg >> 4)
6101 if (record_full_arch_list_add_mem (addr64, 4))
6105 if (record_full_arch_list_add_mem (addr64, 8))
6111 if (record_full_arch_list_add_mem (addr64, 2))
6117 switch (ir.reg >> 4)
6120 if (record_full_arch_list_add_mem (addr64, 4))
6122 if (3 == (ir.reg & 7))
6124 /* For fstp m32fp. */
6125 if (i386_record_floats (gdbarch, &ir,
6126 I386_SAVE_FPU_REGS))
6131 if (record_full_arch_list_add_mem (addr64, 4))
6133 if ((3 == (ir.reg & 7))
6134 || (5 == (ir.reg & 7))
6135 || (7 == (ir.reg & 7)))
6137 /* For fstp insn. */
6138 if (i386_record_floats (gdbarch, &ir,
6139 I386_SAVE_FPU_REGS))
6144 if (record_full_arch_list_add_mem (addr64, 8))
6146 if (3 == (ir.reg & 7))
6148 /* For fstp m64fp. */
6149 if (i386_record_floats (gdbarch, &ir,
6150 I386_SAVE_FPU_REGS))
6155 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6157 /* For fistp, fbld, fild, fbstp. */
6158 if (i386_record_floats (gdbarch, &ir,
6159 I386_SAVE_FPU_REGS))
6164 if (record_full_arch_list_add_mem (addr64, 2))
6173 if (i386_record_floats (gdbarch, &ir,
6174 I386_SAVE_FPU_ENV_REG_STACK))
6179 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6184 if (i386_record_floats (gdbarch, &ir,
6185 I386_SAVE_FPU_ENV_REG_STACK))
6191 if (record_full_arch_list_add_mem (addr64, 28))
6196 if (record_full_arch_list_add_mem (addr64, 14))
6202 if (record_full_arch_list_add_mem (addr64, 2))
6204 /* Insn fstp, fbstp. */
6205 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6210 if (record_full_arch_list_add_mem (addr64, 10))
6216 if (record_full_arch_list_add_mem (addr64, 28))
6222 if (record_full_arch_list_add_mem (addr64, 14))
6226 if (record_full_arch_list_add_mem (addr64, 80))
6229 if (i386_record_floats (gdbarch, &ir,
6230 I386_SAVE_FPU_ENV_REG_STACK))
6234 if (record_full_arch_list_add_mem (addr64, 8))
6237 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6242 opcode = opcode << 8 | ir.modrm;
6247 /* Opcode is an extension of modR/M byte. */
6253 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6257 if (0x0c == (ir.modrm >> 4))
6259 if ((ir.modrm & 0x0f) <= 7)
6261 if (i386_record_floats (gdbarch, &ir,
6262 I386_SAVE_FPU_REGS))
6267 if (i386_record_floats (gdbarch, &ir,
6268 I387_ST0_REGNUM (tdep)))
6270 /* If only st(0) is changing, then we have already
6272 if ((ir.modrm & 0x0f) - 0x08)
6274 if (i386_record_floats (gdbarch, &ir,
6275 I387_ST0_REGNUM (tdep) +
6276 ((ir.modrm & 0x0f) - 0x08)))
6294 if (i386_record_floats (gdbarch, &ir,
6295 I387_ST0_REGNUM (tdep)))
6313 if (i386_record_floats (gdbarch, &ir,
6314 I386_SAVE_FPU_REGS))
6318 if (i386_record_floats (gdbarch, &ir,
6319 I387_ST0_REGNUM (tdep)))
6321 if (i386_record_floats (gdbarch, &ir,
6322 I387_ST0_REGNUM (tdep) + 1))
6329 if (0xe9 == ir.modrm)
6331 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6334 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6336 if (i386_record_floats (gdbarch, &ir,
6337 I387_ST0_REGNUM (tdep)))
6339 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6341 if (i386_record_floats (gdbarch, &ir,
6342 I387_ST0_REGNUM (tdep) +
6346 else if ((ir.modrm & 0x0f) - 0x08)
6348 if (i386_record_floats (gdbarch, &ir,
6349 I387_ST0_REGNUM (tdep) +
6350 ((ir.modrm & 0x0f) - 0x08)))
6356 if (0xe3 == ir.modrm)
6358 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6361 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6363 if (i386_record_floats (gdbarch, &ir,
6364 I387_ST0_REGNUM (tdep)))
6366 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6368 if (i386_record_floats (gdbarch, &ir,
6369 I387_ST0_REGNUM (tdep) +
6373 else if ((ir.modrm & 0x0f) - 0x08)
6375 if (i386_record_floats (gdbarch, &ir,
6376 I387_ST0_REGNUM (tdep) +
6377 ((ir.modrm & 0x0f) - 0x08)))
6383 if ((0x0c == ir.modrm >> 4)
6384 || (0x0d == ir.modrm >> 4)
6385 || (0x0f == ir.modrm >> 4))
6387 if ((ir.modrm & 0x0f) <= 7)
6389 if (i386_record_floats (gdbarch, &ir,
6390 I387_ST0_REGNUM (tdep) +
6396 if (i386_record_floats (gdbarch, &ir,
6397 I387_ST0_REGNUM (tdep) +
6398 ((ir.modrm & 0x0f) - 0x08)))
6404 if (0x0c == ir.modrm >> 4)
6406 if (i386_record_floats (gdbarch, &ir,
6407 I387_FTAG_REGNUM (tdep)))
6410 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6412 if ((ir.modrm & 0x0f) <= 7)
6414 if (i386_record_floats (gdbarch, &ir,
6415 I387_ST0_REGNUM (tdep) +
6421 if (i386_record_floats (gdbarch, &ir,
6422 I386_SAVE_FPU_REGS))
6428 if ((0x0c == ir.modrm >> 4)
6429 || (0x0e == ir.modrm >> 4)
6430 || (0x0f == ir.modrm >> 4)
6431 || (0xd9 == ir.modrm))
6433 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6438 if (0xe0 == ir.modrm)
6440 if (record_full_arch_list_add_reg (ir.regcache,
6444 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6446 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6454 case 0xa4: /* movsS */
6456 case 0xaa: /* stosS */
6458 case 0x6c: /* insS */
6460 regcache_raw_read_unsigned (ir.regcache,
6461 ir.regmap[X86_RECORD_RECX_REGNUM],
6467 if ((opcode & 1) == 0)
6470 ir.ot = ir.dflag + OT_WORD;
6471 regcache_raw_read_unsigned (ir.regcache,
6472 ir.regmap[X86_RECORD_REDI_REGNUM],
6475 regcache_raw_read_unsigned (ir.regcache,
6476 ir.regmap[X86_RECORD_ES_REGNUM],
6478 regcache_raw_read_unsigned (ir.regcache,
6479 ir.regmap[X86_RECORD_DS_REGNUM],
6481 if (ir.aflag && (es != ds))
6483 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6484 if (record_full_memory_query)
6487 Process record ignores the memory change of instruction at address %s\n\
6488 because it can't get the value of the segment register.\n\
6489 Do you want to stop the program?"),
6490 paddress (gdbarch, ir.orig_addr)))
6496 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6500 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6502 if (opcode == 0xa4 || opcode == 0xa5)
6503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6505 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6509 case 0xa6: /* cmpsS */
6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6513 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6514 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6515 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6518 case 0xac: /* lodsS */
6520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6522 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6524 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6527 case 0xae: /* scasS */
6529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6530 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6535 case 0x6e: /* outsS */
6537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6538 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6543 case 0xe4: /* port I/O */
6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6558 case 0xc2: /* ret im */
6559 case 0xc3: /* ret */
6560 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6564 case 0xca: /* lret im */
6565 case 0xcb: /* lret */
6566 case 0xcf: /* iret */
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6569 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6572 case 0xe8: /* call im */
6573 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6575 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6579 case 0x9a: /* lcall im */
6580 if (ir.regmap[X86_RECORD_R8_REGNUM])
6585 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6586 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6590 case 0xe9: /* jmp im */
6591 case 0xea: /* ljmp im */
6592 case 0xeb: /* jmp Jb */
6593 case 0x70: /* jcc Jb */
6609 case 0x0f80: /* jcc Jv */
6627 case 0x0f90: /* setcc Gv */
6643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6645 if (i386_record_modrm (&ir))
6648 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6652 if (i386_record_lea_modrm (&ir))
6657 case 0x0f40: /* cmov Gv, Ev */
6673 if (i386_record_modrm (&ir))
6676 if (ir.dflag == OT_BYTE)
6678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6682 case 0x9c: /* pushf */
6683 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6684 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6686 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6690 case 0x9d: /* popf */
6691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6695 case 0x9e: /* sahf */
6696 if (ir.regmap[X86_RECORD_R8_REGNUM])
6702 case 0xf5: /* cmc */
6703 case 0xf8: /* clc */
6704 case 0xf9: /* stc */
6705 case 0xfc: /* cld */
6706 case 0xfd: /* std */
6707 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6710 case 0x9f: /* lahf */
6711 if (ir.regmap[X86_RECORD_R8_REGNUM])
6716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6717 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6720 /* bit operations */
6721 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6722 ir.ot = ir.dflag + OT_WORD;
6723 if (i386_record_modrm (&ir))
6728 opcode = opcode << 8 | ir.modrm;
6734 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6737 if (i386_record_lea_modrm (&ir))
6741 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6744 case 0x0fa3: /* bt Gv, Ev */
6745 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6748 case 0x0fab: /* bts */
6749 case 0x0fb3: /* btr */
6750 case 0x0fbb: /* btc */
6751 ir.ot = ir.dflag + OT_WORD;
6752 if (i386_record_modrm (&ir))
6755 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6759 if (i386_record_lea_modrm_addr (&ir, &addr64))
6761 regcache_raw_read_unsigned (ir.regcache,
6762 ir.regmap[ir.reg | rex_r],
6767 addr64 += ((int16_t) addr >> 4) << 4;
6770 addr64 += ((int32_t) addr >> 5) << 5;
6773 addr64 += ((int64_t) addr >> 6) << 6;
6776 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6778 if (i386_record_lea_modrm (&ir))
6781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6784 case 0x0fbc: /* bsf */
6785 case 0x0fbd: /* bsr */
6786 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6791 case 0x27: /* daa */
6792 case 0x2f: /* das */
6793 case 0x37: /* aaa */
6794 case 0x3f: /* aas */
6795 case 0xd4: /* aam */
6796 case 0xd5: /* aad */
6797 if (ir.regmap[X86_RECORD_R8_REGNUM])
6802 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6803 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6807 case 0x90: /* nop */
6808 if (prefixes & PREFIX_LOCK)
6815 case 0x9b: /* fwait */
6816 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6818 opcode = (uint32_t) opcode8;
6824 case 0xcc: /* int3 */
6825 printf_unfiltered (_("Process record does not support instruction "
6832 case 0xcd: /* int */
6836 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6839 if (interrupt != 0x80
6840 || tdep->i386_intx80_record == NULL)
6842 printf_unfiltered (_("Process record does not support "
6843 "instruction int 0x%02x.\n"),
6848 ret = tdep->i386_intx80_record (ir.regcache);
6855 case 0xce: /* into */
6856 printf_unfiltered (_("Process record does not support "
6857 "instruction into.\n"));
6862 case 0xfa: /* cli */
6863 case 0xfb: /* sti */
6866 case 0x62: /* bound */
6867 printf_unfiltered (_("Process record does not support "
6868 "instruction bound.\n"));
6873 case 0x0fc8: /* bswap reg */
6881 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6884 case 0xd6: /* salc */
6885 if (ir.regmap[X86_RECORD_R8_REGNUM])
6890 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6891 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6894 case 0xe0: /* loopnz */
6895 case 0xe1: /* loopz */
6896 case 0xe2: /* loop */
6897 case 0xe3: /* jecxz */
6898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6899 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6902 case 0x0f30: /* wrmsr */
6903 printf_unfiltered (_("Process record does not support "
6904 "instruction wrmsr.\n"));
6909 case 0x0f32: /* rdmsr */
6910 printf_unfiltered (_("Process record does not support "
6911 "instruction rdmsr.\n"));
6916 case 0x0f31: /* rdtsc */
6917 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6918 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6921 case 0x0f34: /* sysenter */
6924 if (ir.regmap[X86_RECORD_R8_REGNUM])
6929 if (tdep->i386_sysenter_record == NULL)
6931 printf_unfiltered (_("Process record does not support "
6932 "instruction sysenter.\n"));
6936 ret = tdep->i386_sysenter_record (ir.regcache);
6942 case 0x0f35: /* sysexit */
6943 printf_unfiltered (_("Process record does not support "
6944 "instruction sysexit.\n"));
6949 case 0x0f05: /* syscall */
6952 if (tdep->i386_syscall_record == NULL)
6954 printf_unfiltered (_("Process record does not support "
6955 "instruction syscall.\n"));
6959 ret = tdep->i386_syscall_record (ir.regcache);
6965 case 0x0f07: /* sysret */
6966 printf_unfiltered (_("Process record does not support "
6967 "instruction sysret.\n"));
6972 case 0x0fa2: /* cpuid */
6973 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6975 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6976 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6979 case 0xf4: /* hlt */
6980 printf_unfiltered (_("Process record does not support "
6981 "instruction hlt.\n"));
6987 if (i386_record_modrm (&ir))
6994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6998 if (i386_record_lea_modrm (&ir))
7007 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7011 opcode = opcode << 8 | ir.modrm;
7018 if (i386_record_modrm (&ir))
7029 opcode = opcode << 8 | ir.modrm;
7032 if (ir.override >= 0)
7034 if (record_full_memory_query)
7037 Process record ignores the memory change of instruction at address %s\n\
7038 because it can't get the value of the segment register.\n\
7039 Do you want to stop the program?"),
7040 paddress (gdbarch, ir.orig_addr)))
7046 if (i386_record_lea_modrm_addr (&ir, &addr64))
7048 if (record_full_arch_list_add_mem (addr64, 2))
7051 if (ir.regmap[X86_RECORD_R8_REGNUM])
7053 if (record_full_arch_list_add_mem (addr64, 8))
7058 if (record_full_arch_list_add_mem (addr64, 4))
7069 case 0: /* monitor */
7072 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7076 opcode = opcode << 8 | ir.modrm;
7084 if (ir.override >= 0)
7086 if (record_full_memory_query)
7089 Process record ignores the memory change of instruction at address %s\n\
7090 because it can't get the value of the segment register.\n\
7091 Do you want to stop the program?"),
7092 paddress (gdbarch, ir.orig_addr)))
7100 if (i386_record_lea_modrm_addr (&ir, &addr64))
7102 if (record_full_arch_list_add_mem (addr64, 2))
7105 if (ir.regmap[X86_RECORD_R8_REGNUM])
7107 if (record_full_arch_list_add_mem (addr64, 8))
7112 if (record_full_arch_list_add_mem (addr64, 4))
7124 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7125 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7129 else if (ir.rm == 1)
7136 opcode = opcode << 8 | ir.modrm;
7143 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7149 if (i386_record_lea_modrm (&ir))
7152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7155 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7157 case 7: /* invlpg */
7160 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7161 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7165 opcode = opcode << 8 | ir.modrm;
7170 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7174 opcode = opcode << 8 | ir.modrm;
7180 case 0x0f08: /* invd */
7181 case 0x0f09: /* wbinvd */
7184 case 0x63: /* arpl */
7185 if (i386_record_modrm (&ir))
7187 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7189 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7190 ? (ir.reg | rex_r) : ir.rm);
7194 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7195 if (i386_record_lea_modrm (&ir))
7198 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7199 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7202 case 0x0f02: /* lar */
7203 case 0x0f03: /* lsl */
7204 if (i386_record_modrm (&ir))
7206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7207 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7211 if (i386_record_modrm (&ir))
7213 if (ir.mod == 3 && ir.reg == 3)
7216 opcode = opcode << 8 | ir.modrm;
7228 /* nop (multi byte) */
7231 case 0x0f20: /* mov reg, crN */
7232 case 0x0f22: /* mov crN, reg */
7233 if (i386_record_modrm (&ir))
7235 if ((ir.modrm & 0xc0) != 0xc0)
7238 opcode = opcode << 8 | ir.modrm;
7249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7251 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7255 opcode = opcode << 8 | ir.modrm;
7261 case 0x0f21: /* mov reg, drN */
7262 case 0x0f23: /* mov drN, reg */
7263 if (i386_record_modrm (&ir))
7265 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7266 || ir.reg == 5 || ir.reg >= 8)
7269 opcode = opcode << 8 | ir.modrm;
7273 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7275 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7278 case 0x0f06: /* clts */
7279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7282 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7284 case 0x0f0d: /* 3DNow! prefetch */
7287 case 0x0f0e: /* 3DNow! femms */
7288 case 0x0f77: /* emms */
7289 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7291 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7294 case 0x0f0f: /* 3DNow! data */
7295 if (i386_record_modrm (&ir))
7297 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7302 case 0x0c: /* 3DNow! pi2fw */
7303 case 0x0d: /* 3DNow! pi2fd */
7304 case 0x1c: /* 3DNow! pf2iw */
7305 case 0x1d: /* 3DNow! pf2id */
7306 case 0x8a: /* 3DNow! pfnacc */
7307 case 0x8e: /* 3DNow! pfpnacc */
7308 case 0x90: /* 3DNow! pfcmpge */
7309 case 0x94: /* 3DNow! pfmin */
7310 case 0x96: /* 3DNow! pfrcp */
7311 case 0x97: /* 3DNow! pfrsqrt */
7312 case 0x9a: /* 3DNow! pfsub */
7313 case 0x9e: /* 3DNow! pfadd */
7314 case 0xa0: /* 3DNow! pfcmpgt */
7315 case 0xa4: /* 3DNow! pfmax */
7316 case 0xa6: /* 3DNow! pfrcpit1 */
7317 case 0xa7: /* 3DNow! pfrsqit1 */
7318 case 0xaa: /* 3DNow! pfsubr */
7319 case 0xae: /* 3DNow! pfacc */
7320 case 0xb0: /* 3DNow! pfcmpeq */
7321 case 0xb4: /* 3DNow! pfmul */
7322 case 0xb6: /* 3DNow! pfrcpit2 */
7323 case 0xb7: /* 3DNow! pmulhrw */
7324 case 0xbb: /* 3DNow! pswapd */
7325 case 0xbf: /* 3DNow! pavgusb */
7326 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7327 goto no_support_3dnow_data;
7328 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7332 no_support_3dnow_data:
7333 opcode = (opcode << 8) | opcode8;
7339 case 0x0faa: /* rsm */
7340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7348 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7352 if (i386_record_modrm (&ir))
7356 case 0: /* fxsave */
7360 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7361 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7363 if (record_full_arch_list_add_mem (tmpu64, 512))
7368 case 1: /* fxrstor */
7372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7374 for (i = I387_MM0_REGNUM (tdep);
7375 i386_mmx_regnum_p (gdbarch, i); i++)
7376 record_full_arch_list_add_reg (ir.regcache, i);
7378 for (i = I387_XMM0_REGNUM (tdep);
7379 i386_xmm_regnum_p (gdbarch, i); i++)
7380 record_full_arch_list_add_reg (ir.regcache, i);
7382 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7383 record_full_arch_list_add_reg (ir.regcache,
7384 I387_MXCSR_REGNUM(tdep));
7386 for (i = I387_ST0_REGNUM (tdep);
7387 i386_fp_regnum_p (gdbarch, i); i++)
7388 record_full_arch_list_add_reg (ir.regcache, i);
7390 for (i = I387_FCTRL_REGNUM (tdep);
7391 i386_fpc_regnum_p (gdbarch, i); i++)
7392 record_full_arch_list_add_reg (ir.regcache, i);
7396 case 2: /* ldmxcsr */
7397 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7399 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7402 case 3: /* stmxcsr */
7404 if (i386_record_lea_modrm (&ir))
7408 case 5: /* lfence */
7409 case 6: /* mfence */
7410 case 7: /* sfence clflush */
7414 opcode = (opcode << 8) | ir.modrm;
7420 case 0x0fc3: /* movnti */
7421 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7422 if (i386_record_modrm (&ir))
7427 if (i386_record_lea_modrm (&ir))
7431 /* Add prefix to opcode. */
7546 /* Mask out PREFIX_ADDR. */
7547 switch ((prefixes & ~PREFIX_ADDR))
7559 reswitch_prefix_add:
7567 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7570 opcode = (uint32_t) opcode8 | opcode << 8;
7571 goto reswitch_prefix_add;
7574 case 0x0f10: /* movups */
7575 case 0x660f10: /* movupd */
7576 case 0xf30f10: /* movss */
7577 case 0xf20f10: /* movsd */
7578 case 0x0f12: /* movlps */
7579 case 0x660f12: /* movlpd */
7580 case 0xf30f12: /* movsldup */
7581 case 0xf20f12: /* movddup */
7582 case 0x0f14: /* unpcklps */
7583 case 0x660f14: /* unpcklpd */
7584 case 0x0f15: /* unpckhps */
7585 case 0x660f15: /* unpckhpd */
7586 case 0x0f16: /* movhps */
7587 case 0x660f16: /* movhpd */
7588 case 0xf30f16: /* movshdup */
7589 case 0x0f28: /* movaps */
7590 case 0x660f28: /* movapd */
7591 case 0x0f2a: /* cvtpi2ps */
7592 case 0x660f2a: /* cvtpi2pd */
7593 case 0xf30f2a: /* cvtsi2ss */
7594 case 0xf20f2a: /* cvtsi2sd */
7595 case 0x0f2c: /* cvttps2pi */
7596 case 0x660f2c: /* cvttpd2pi */
7597 case 0x0f2d: /* cvtps2pi */
7598 case 0x660f2d: /* cvtpd2pi */
7599 case 0x660f3800: /* pshufb */
7600 case 0x660f3801: /* phaddw */
7601 case 0x660f3802: /* phaddd */
7602 case 0x660f3803: /* phaddsw */
7603 case 0x660f3804: /* pmaddubsw */
7604 case 0x660f3805: /* phsubw */
7605 case 0x660f3806: /* phsubd */
7606 case 0x660f3807: /* phsubsw */
7607 case 0x660f3808: /* psignb */
7608 case 0x660f3809: /* psignw */
7609 case 0x660f380a: /* psignd */
7610 case 0x660f380b: /* pmulhrsw */
7611 case 0x660f3810: /* pblendvb */
7612 case 0x660f3814: /* blendvps */
7613 case 0x660f3815: /* blendvpd */
7614 case 0x660f381c: /* pabsb */
7615 case 0x660f381d: /* pabsw */
7616 case 0x660f381e: /* pabsd */
7617 case 0x660f3820: /* pmovsxbw */
7618 case 0x660f3821: /* pmovsxbd */
7619 case 0x660f3822: /* pmovsxbq */
7620 case 0x660f3823: /* pmovsxwd */
7621 case 0x660f3824: /* pmovsxwq */
7622 case 0x660f3825: /* pmovsxdq */
7623 case 0x660f3828: /* pmuldq */
7624 case 0x660f3829: /* pcmpeqq */
7625 case 0x660f382a: /* movntdqa */
7626 case 0x660f3a08: /* roundps */
7627 case 0x660f3a09: /* roundpd */
7628 case 0x660f3a0a: /* roundss */
7629 case 0x660f3a0b: /* roundsd */
7630 case 0x660f3a0c: /* blendps */
7631 case 0x660f3a0d: /* blendpd */
7632 case 0x660f3a0e: /* pblendw */
7633 case 0x660f3a0f: /* palignr */
7634 case 0x660f3a20: /* pinsrb */
7635 case 0x660f3a21: /* insertps */
7636 case 0x660f3a22: /* pinsrd pinsrq */
7637 case 0x660f3a40: /* dpps */
7638 case 0x660f3a41: /* dppd */
7639 case 0x660f3a42: /* mpsadbw */
7640 case 0x660f3a60: /* pcmpestrm */
7641 case 0x660f3a61: /* pcmpestri */
7642 case 0x660f3a62: /* pcmpistrm */
7643 case 0x660f3a63: /* pcmpistri */
7644 case 0x0f51: /* sqrtps */
7645 case 0x660f51: /* sqrtpd */
7646 case 0xf20f51: /* sqrtsd */
7647 case 0xf30f51: /* sqrtss */
7648 case 0x0f52: /* rsqrtps */
7649 case 0xf30f52: /* rsqrtss */
7650 case 0x0f53: /* rcpps */
7651 case 0xf30f53: /* rcpss */
7652 case 0x0f54: /* andps */
7653 case 0x660f54: /* andpd */
7654 case 0x0f55: /* andnps */
7655 case 0x660f55: /* andnpd */
7656 case 0x0f56: /* orps */
7657 case 0x660f56: /* orpd */
7658 case 0x0f57: /* xorps */
7659 case 0x660f57: /* xorpd */
7660 case 0x0f58: /* addps */
7661 case 0x660f58: /* addpd */
7662 case 0xf20f58: /* addsd */
7663 case 0xf30f58: /* addss */
7664 case 0x0f59: /* mulps */
7665 case 0x660f59: /* mulpd */
7666 case 0xf20f59: /* mulsd */
7667 case 0xf30f59: /* mulss */
7668 case 0x0f5a: /* cvtps2pd */
7669 case 0x660f5a: /* cvtpd2ps */
7670 case 0xf20f5a: /* cvtsd2ss */
7671 case 0xf30f5a: /* cvtss2sd */
7672 case 0x0f5b: /* cvtdq2ps */
7673 case 0x660f5b: /* cvtps2dq */
7674 case 0xf30f5b: /* cvttps2dq */
7675 case 0x0f5c: /* subps */
7676 case 0x660f5c: /* subpd */
7677 case 0xf20f5c: /* subsd */
7678 case 0xf30f5c: /* subss */
7679 case 0x0f5d: /* minps */
7680 case 0x660f5d: /* minpd */
7681 case 0xf20f5d: /* minsd */
7682 case 0xf30f5d: /* minss */
7683 case 0x0f5e: /* divps */
7684 case 0x660f5e: /* divpd */
7685 case 0xf20f5e: /* divsd */
7686 case 0xf30f5e: /* divss */
7687 case 0x0f5f: /* maxps */
7688 case 0x660f5f: /* maxpd */
7689 case 0xf20f5f: /* maxsd */
7690 case 0xf30f5f: /* maxss */
7691 case 0x660f60: /* punpcklbw */
7692 case 0x660f61: /* punpcklwd */
7693 case 0x660f62: /* punpckldq */
7694 case 0x660f63: /* packsswb */
7695 case 0x660f64: /* pcmpgtb */
7696 case 0x660f65: /* pcmpgtw */
7697 case 0x660f66: /* pcmpgtd */
7698 case 0x660f67: /* packuswb */
7699 case 0x660f68: /* punpckhbw */
7700 case 0x660f69: /* punpckhwd */
7701 case 0x660f6a: /* punpckhdq */
7702 case 0x660f6b: /* packssdw */
7703 case 0x660f6c: /* punpcklqdq */
7704 case 0x660f6d: /* punpckhqdq */
7705 case 0x660f6e: /* movd */
7706 case 0x660f6f: /* movdqa */
7707 case 0xf30f6f: /* movdqu */
7708 case 0x660f70: /* pshufd */
7709 case 0xf20f70: /* pshuflw */
7710 case 0xf30f70: /* pshufhw */
7711 case 0x660f74: /* pcmpeqb */
7712 case 0x660f75: /* pcmpeqw */
7713 case 0x660f76: /* pcmpeqd */
7714 case 0x660f7c: /* haddpd */
7715 case 0xf20f7c: /* haddps */
7716 case 0x660f7d: /* hsubpd */
7717 case 0xf20f7d: /* hsubps */
7718 case 0xf30f7e: /* movq */
7719 case 0x0fc2: /* cmpps */
7720 case 0x660fc2: /* cmppd */
7721 case 0xf20fc2: /* cmpsd */
7722 case 0xf30fc2: /* cmpss */
7723 case 0x660fc4: /* pinsrw */
7724 case 0x0fc6: /* shufps */
7725 case 0x660fc6: /* shufpd */
7726 case 0x660fd0: /* addsubpd */
7727 case 0xf20fd0: /* addsubps */
7728 case 0x660fd1: /* psrlw */
7729 case 0x660fd2: /* psrld */
7730 case 0x660fd3: /* psrlq */
7731 case 0x660fd4: /* paddq */
7732 case 0x660fd5: /* pmullw */
7733 case 0xf30fd6: /* movq2dq */
7734 case 0x660fd8: /* psubusb */
7735 case 0x660fd9: /* psubusw */
7736 case 0x660fda: /* pminub */
7737 case 0x660fdb: /* pand */
7738 case 0x660fdc: /* paddusb */
7739 case 0x660fdd: /* paddusw */
7740 case 0x660fde: /* pmaxub */
7741 case 0x660fdf: /* pandn */
7742 case 0x660fe0: /* pavgb */
7743 case 0x660fe1: /* psraw */
7744 case 0x660fe2: /* psrad */
7745 case 0x660fe3: /* pavgw */
7746 case 0x660fe4: /* pmulhuw */
7747 case 0x660fe5: /* pmulhw */
7748 case 0x660fe6: /* cvttpd2dq */
7749 case 0xf20fe6: /* cvtpd2dq */
7750 case 0xf30fe6: /* cvtdq2pd */
7751 case 0x660fe8: /* psubsb */
7752 case 0x660fe9: /* psubsw */
7753 case 0x660fea: /* pminsw */
7754 case 0x660feb: /* por */
7755 case 0x660fec: /* paddsb */
7756 case 0x660fed: /* paddsw */
7757 case 0x660fee: /* pmaxsw */
7758 case 0x660fef: /* pxor */
7759 case 0xf20ff0: /* lddqu */
7760 case 0x660ff1: /* psllw */
7761 case 0x660ff2: /* pslld */
7762 case 0x660ff3: /* psllq */
7763 case 0x660ff4: /* pmuludq */
7764 case 0x660ff5: /* pmaddwd */
7765 case 0x660ff6: /* psadbw */
7766 case 0x660ff8: /* psubb */
7767 case 0x660ff9: /* psubw */
7768 case 0x660ffa: /* psubd */
7769 case 0x660ffb: /* psubq */
7770 case 0x660ffc: /* paddb */
7771 case 0x660ffd: /* paddw */
7772 case 0x660ffe: /* paddd */
7773 if (i386_record_modrm (&ir))
7776 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7778 record_full_arch_list_add_reg (ir.regcache,
7779 I387_XMM0_REGNUM (tdep) + ir.reg);
7780 if ((opcode & 0xfffffffc) == 0x660f3a60)
7781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7784 case 0x0f11: /* movups */
7785 case 0x660f11: /* movupd */
7786 case 0xf30f11: /* movss */
7787 case 0xf20f11: /* movsd */
7788 case 0x0f13: /* movlps */
7789 case 0x660f13: /* movlpd */
7790 case 0x0f17: /* movhps */
7791 case 0x660f17: /* movhpd */
7792 case 0x0f29: /* movaps */
7793 case 0x660f29: /* movapd */
7794 case 0x660f3a14: /* pextrb */
7795 case 0x660f3a15: /* pextrw */
7796 case 0x660f3a16: /* pextrd pextrq */
7797 case 0x660f3a17: /* extractps */
7798 case 0x660f7f: /* movdqa */
7799 case 0xf30f7f: /* movdqu */
7800 if (i386_record_modrm (&ir))
7804 if (opcode == 0x0f13 || opcode == 0x660f13
7805 || opcode == 0x0f17 || opcode == 0x660f17)
7808 if (!i386_xmm_regnum_p (gdbarch,
7809 I387_XMM0_REGNUM (tdep) + ir.rm))
7811 record_full_arch_list_add_reg (ir.regcache,
7812 I387_XMM0_REGNUM (tdep) + ir.rm);
7834 if (i386_record_lea_modrm (&ir))
7839 case 0x0f2b: /* movntps */
7840 case 0x660f2b: /* movntpd */
7841 case 0x0fe7: /* movntq */
7842 case 0x660fe7: /* movntdq */
7845 if (opcode == 0x0fe7)
7849 if (i386_record_lea_modrm (&ir))
7853 case 0xf30f2c: /* cvttss2si */
7854 case 0xf20f2c: /* cvttsd2si */
7855 case 0xf30f2d: /* cvtss2si */
7856 case 0xf20f2d: /* cvtsd2si */
7857 case 0xf20f38f0: /* crc32 */
7858 case 0xf20f38f1: /* crc32 */
7859 case 0x0f50: /* movmskps */
7860 case 0x660f50: /* movmskpd */
7861 case 0x0fc5: /* pextrw */
7862 case 0x660fc5: /* pextrw */
7863 case 0x0fd7: /* pmovmskb */
7864 case 0x660fd7: /* pmovmskb */
7865 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7868 case 0x0f3800: /* pshufb */
7869 case 0x0f3801: /* phaddw */
7870 case 0x0f3802: /* phaddd */
7871 case 0x0f3803: /* phaddsw */
7872 case 0x0f3804: /* pmaddubsw */
7873 case 0x0f3805: /* phsubw */
7874 case 0x0f3806: /* phsubd */
7875 case 0x0f3807: /* phsubsw */
7876 case 0x0f3808: /* psignb */
7877 case 0x0f3809: /* psignw */
7878 case 0x0f380a: /* psignd */
7879 case 0x0f380b: /* pmulhrsw */
7880 case 0x0f381c: /* pabsb */
7881 case 0x0f381d: /* pabsw */
7882 case 0x0f381e: /* pabsd */
7883 case 0x0f382b: /* packusdw */
7884 case 0x0f3830: /* pmovzxbw */
7885 case 0x0f3831: /* pmovzxbd */
7886 case 0x0f3832: /* pmovzxbq */
7887 case 0x0f3833: /* pmovzxwd */
7888 case 0x0f3834: /* pmovzxwq */
7889 case 0x0f3835: /* pmovzxdq */
7890 case 0x0f3837: /* pcmpgtq */
7891 case 0x0f3838: /* pminsb */
7892 case 0x0f3839: /* pminsd */
7893 case 0x0f383a: /* pminuw */
7894 case 0x0f383b: /* pminud */
7895 case 0x0f383c: /* pmaxsb */
7896 case 0x0f383d: /* pmaxsd */
7897 case 0x0f383e: /* pmaxuw */
7898 case 0x0f383f: /* pmaxud */
7899 case 0x0f3840: /* pmulld */
7900 case 0x0f3841: /* phminposuw */
7901 case 0x0f3a0f: /* palignr */
7902 case 0x0f60: /* punpcklbw */
7903 case 0x0f61: /* punpcklwd */
7904 case 0x0f62: /* punpckldq */
7905 case 0x0f63: /* packsswb */
7906 case 0x0f64: /* pcmpgtb */
7907 case 0x0f65: /* pcmpgtw */
7908 case 0x0f66: /* pcmpgtd */
7909 case 0x0f67: /* packuswb */
7910 case 0x0f68: /* punpckhbw */
7911 case 0x0f69: /* punpckhwd */
7912 case 0x0f6a: /* punpckhdq */
7913 case 0x0f6b: /* packssdw */
7914 case 0x0f6e: /* movd */
7915 case 0x0f6f: /* movq */
7916 case 0x0f70: /* pshufw */
7917 case 0x0f74: /* pcmpeqb */
7918 case 0x0f75: /* pcmpeqw */
7919 case 0x0f76: /* pcmpeqd */
7920 case 0x0fc4: /* pinsrw */
7921 case 0x0fd1: /* psrlw */
7922 case 0x0fd2: /* psrld */
7923 case 0x0fd3: /* psrlq */
7924 case 0x0fd4: /* paddq */
7925 case 0x0fd5: /* pmullw */
7926 case 0xf20fd6: /* movdq2q */
7927 case 0x0fd8: /* psubusb */
7928 case 0x0fd9: /* psubusw */
7929 case 0x0fda: /* pminub */
7930 case 0x0fdb: /* pand */
7931 case 0x0fdc: /* paddusb */
7932 case 0x0fdd: /* paddusw */
7933 case 0x0fde: /* pmaxub */
7934 case 0x0fdf: /* pandn */
7935 case 0x0fe0: /* pavgb */
7936 case 0x0fe1: /* psraw */
7937 case 0x0fe2: /* psrad */
7938 case 0x0fe3: /* pavgw */
7939 case 0x0fe4: /* pmulhuw */
7940 case 0x0fe5: /* pmulhw */
7941 case 0x0fe8: /* psubsb */
7942 case 0x0fe9: /* psubsw */
7943 case 0x0fea: /* pminsw */
7944 case 0x0feb: /* por */
7945 case 0x0fec: /* paddsb */
7946 case 0x0fed: /* paddsw */
7947 case 0x0fee: /* pmaxsw */
7948 case 0x0fef: /* pxor */
7949 case 0x0ff1: /* psllw */
7950 case 0x0ff2: /* pslld */
7951 case 0x0ff3: /* psllq */
7952 case 0x0ff4: /* pmuludq */
7953 case 0x0ff5: /* pmaddwd */
7954 case 0x0ff6: /* psadbw */
7955 case 0x0ff8: /* psubb */
7956 case 0x0ff9: /* psubw */
7957 case 0x0ffa: /* psubd */
7958 case 0x0ffb: /* psubq */
7959 case 0x0ffc: /* paddb */
7960 case 0x0ffd: /* paddw */
7961 case 0x0ffe: /* paddd */
7962 if (i386_record_modrm (&ir))
7964 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7966 record_full_arch_list_add_reg (ir.regcache,
7967 I387_MM0_REGNUM (tdep) + ir.reg);
7970 case 0x0f71: /* psllw */
7971 case 0x0f72: /* pslld */
7972 case 0x0f73: /* psllq */
7973 if (i386_record_modrm (&ir))
7975 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7977 record_full_arch_list_add_reg (ir.regcache,
7978 I387_MM0_REGNUM (tdep) + ir.rm);
7981 case 0x660f71: /* psllw */
7982 case 0x660f72: /* pslld */
7983 case 0x660f73: /* psllq */
7984 if (i386_record_modrm (&ir))
7987 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7989 record_full_arch_list_add_reg (ir.regcache,
7990 I387_XMM0_REGNUM (tdep) + ir.rm);
7993 case 0x0f7e: /* movd */
7994 case 0x660f7e: /* movd */
7995 if (i386_record_modrm (&ir))
7998 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
8005 if (i386_record_lea_modrm (&ir))
8010 case 0x0f7f: /* movq */
8011 if (i386_record_modrm (&ir))
8015 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8017 record_full_arch_list_add_reg (ir.regcache,
8018 I387_MM0_REGNUM (tdep) + ir.rm);
8023 if (i386_record_lea_modrm (&ir))
8028 case 0xf30fb8: /* popcnt */
8029 if (i386_record_modrm (&ir))
8031 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
8032 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8035 case 0x660fd6: /* movq */
8036 if (i386_record_modrm (&ir))
8041 if (!i386_xmm_regnum_p (gdbarch,
8042 I387_XMM0_REGNUM (tdep) + ir.rm))
8044 record_full_arch_list_add_reg (ir.regcache,
8045 I387_XMM0_REGNUM (tdep) + ir.rm);
8050 if (i386_record_lea_modrm (&ir))
8055 case 0x660f3817: /* ptest */
8056 case 0x0f2e: /* ucomiss */
8057 case 0x660f2e: /* ucomisd */
8058 case 0x0f2f: /* comiss */
8059 case 0x660f2f: /* comisd */
8060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8063 case 0x0ff7: /* maskmovq */
8064 regcache_raw_read_unsigned (ir.regcache,
8065 ir.regmap[X86_RECORD_REDI_REGNUM],
8067 if (record_full_arch_list_add_mem (addr, 64))
8071 case 0x660ff7: /* maskmovdqu */
8072 regcache_raw_read_unsigned (ir.regcache,
8073 ir.regmap[X86_RECORD_REDI_REGNUM],
8075 if (record_full_arch_list_add_mem (addr, 128))
8090 /* In the future, maybe still need to deal with need_dasm. */
8091 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8092 if (record_full_arch_list_add_end ())
8098 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8099 "at address %s.\n"),
8100 (unsigned int) (opcode),
8101 paddress (gdbarch, ir.orig_addr));
8105 static const int i386_record_regmap[] =
8107 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8108 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8109 0, 0, 0, 0, 0, 0, 0, 0,
8110 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8111 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8114 /* Check that the given address appears suitable for a fast
8115 tracepoint, which on x86-64 means that we need an instruction of at
8116 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8117 jump and not have to worry about program jumps to an address in the
8118 middle of the tracepoint jump. On x86, it may be possible to use
8119 4-byte jumps with a 2-byte offset to a trampoline located in the
8120 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8121 of instruction to replace, and 0 if not, plus an explanatory
8125 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8130 /* Ask the target for the minimum instruction length supported. */
8131 jumplen = target_get_min_fast_tracepoint_insn_len ();
8135 /* If the target does not support the get_min_fast_tracepoint_insn_len
8136 operation, assume that fast tracepoints will always be implemented
8137 using 4-byte relative jumps on both x86 and x86-64. */
8140 else if (jumplen == 0)
8142 /* If the target does support get_min_fast_tracepoint_insn_len but
8143 returns zero, then the IPA has not loaded yet. In this case,
8144 we optimistically assume that truncated 2-byte relative jumps
8145 will be available on x86, and compensate later if this assumption
8146 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8147 jumps will always be used. */
8148 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8151 /* Check for fit. */
8152 len = gdb_insn_length (gdbarch, addr);
8156 /* Return a bit of target-specific detail to add to the caller's
8157 generic failure message. */
8159 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8160 "need at least %d bytes for the jump"),
8172 /* Return a floating-point format for a floating-point variable of
8173 length LEN in bits. If non-NULL, NAME is the name of its type.
8174 If no suitable type is found, return NULL. */
8176 const struct floatformat **
8177 i386_floatformat_for_type (struct gdbarch *gdbarch,
8178 const char *name, int len)
8180 if (len == 128 && name)
8181 if (strcmp (name, "__float128") == 0
8182 || strcmp (name, "_Float128") == 0
8183 || strcmp (name, "complex _Float128") == 0)
8184 return floatformats_ia64_quad;
8186 return default_floatformat_for_type (gdbarch, name, len);
8190 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8191 struct tdesc_arch_data *tdesc_data)
8193 const struct target_desc *tdesc = tdep->tdesc;
8194 const struct tdesc_feature *feature_core;
8196 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8197 *feature_avx512, *feature_pkeys;
8198 int i, num_regs, valid_p;
8200 if (! tdesc_has_registers (tdesc))
8203 /* Get core registers. */
8204 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8205 if (feature_core == NULL)
8208 /* Get SSE registers. */
8209 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8211 /* Try AVX registers. */
8212 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8214 /* Try MPX registers. */
8215 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8217 /* Try AVX512 registers. */
8218 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8221 feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys");
8225 /* The XCR0 bits. */
8228 /* AVX512 register description requires AVX register description. */
8232 tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK;
8234 /* It may have been set by OSABI initialization function. */
8235 if (tdep->k0_regnum < 0)
8237 tdep->k_register_names = i386_k_names;
8238 tdep->k0_regnum = I386_K0_REGNUM;
8241 for (i = 0; i < I387_NUM_K_REGS; i++)
8242 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8243 tdep->k0_regnum + i,
8246 if (tdep->num_zmm_regs == 0)
8248 tdep->zmmh_register_names = i386_zmmh_names;
8249 tdep->num_zmm_regs = 8;
8250 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8253 for (i = 0; i < tdep->num_zmm_regs; i++)
8254 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8255 tdep->zmm0h_regnum + i,
8256 tdep->zmmh_register_names[i]);
8258 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8259 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8260 tdep->xmm16_regnum + i,
8261 tdep->xmm_avx512_register_names[i]);
8263 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8264 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8265 tdep->ymm16h_regnum + i,
8266 tdep->ymm16h_register_names[i]);
8270 /* AVX register description requires SSE register description. */
8274 if (!feature_avx512)
8275 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8277 /* It may have been set by OSABI initialization function. */
8278 if (tdep->num_ymm_regs == 0)
8280 tdep->ymmh_register_names = i386_ymmh_names;
8281 tdep->num_ymm_regs = 8;
8282 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8285 for (i = 0; i < tdep->num_ymm_regs; i++)
8286 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8287 tdep->ymm0h_regnum + i,
8288 tdep->ymmh_register_names[i]);
8290 else if (feature_sse)
8291 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8294 tdep->xcr0 = X86_XSTATE_X87_MASK;
8295 tdep->num_xmm_regs = 0;
8298 num_regs = tdep->num_core_regs;
8299 for (i = 0; i < num_regs; i++)
8300 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8301 tdep->register_names[i]);
8305 /* Need to include %mxcsr, so add one. */
8306 num_regs += tdep->num_xmm_regs + 1;
8307 for (; i < num_regs; i++)
8308 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8309 tdep->register_names[i]);
8314 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8316 if (tdep->bnd0r_regnum < 0)
8318 tdep->mpx_register_names = i386_mpx_names;
8319 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8320 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8323 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8324 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8325 I387_BND0R_REGNUM (tdep) + i,
8326 tdep->mpx_register_names[i]);
8331 tdep->xcr0 |= X86_XSTATE_PKRU;
8332 if (tdep->pkru_regnum < 0)
8334 tdep->pkeys_register_names = i386_pkeys_names;
8335 tdep->pkru_regnum = I386_PKRU_REGNUM;
8336 tdep->num_pkeys_regs = 1;
8339 for (i = 0; i < I387_NUM_PKEYS_REGS; i++)
8340 valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data,
8341 I387_PKRU_REGNUM (tdep) + i,
8342 tdep->pkeys_register_names[i]);
8349 /* Note: This is called for both i386 and amd64. */
8351 static struct gdbarch *
8352 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8354 struct gdbarch_tdep *tdep;
8355 struct gdbarch *gdbarch;
8356 struct tdesc_arch_data *tdesc_data;
8357 const struct target_desc *tdesc;
8363 /* If there is already a candidate, use it. */
8364 arches = gdbarch_list_lookup_by_info (arches, &info);
8366 return arches->gdbarch;
8368 /* Allocate space for the new architecture. Assume i386 for now. */
8369 tdep = XCNEW (struct gdbarch_tdep);
8370 gdbarch = gdbarch_alloc (&info, tdep);
8372 /* General-purpose registers. */
8373 tdep->gregset_reg_offset = NULL;
8374 tdep->gregset_num_regs = I386_NUM_GREGS;
8375 tdep->sizeof_gregset = 0;
8377 /* Floating-point registers. */
8378 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8379 tdep->fpregset = &i386_fpregset;
8381 /* The default settings include the FPU registers, the MMX registers
8382 and the SSE registers. This can be overridden for a specific ABI
8383 by adjusting the members `st0_regnum', `mm0_regnum' and
8384 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8385 will show up in the output of "info all-registers". */
8387 tdep->st0_regnum = I386_ST0_REGNUM;
8389 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8390 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8392 tdep->jb_pc_offset = -1;
8393 tdep->struct_return = pcc_struct_return;
8394 tdep->sigtramp_start = 0;
8395 tdep->sigtramp_end = 0;
8396 tdep->sigtramp_p = i386_sigtramp_p;
8397 tdep->sigcontext_addr = NULL;
8398 tdep->sc_reg_offset = NULL;
8399 tdep->sc_pc_offset = -1;
8400 tdep->sc_sp_offset = -1;
8402 tdep->xsave_xcr0_offset = -1;
8404 tdep->record_regmap = i386_record_regmap;
8406 set_gdbarch_long_long_align_bit (gdbarch, 32);
8408 /* The format used for `long double' on almost all i386 targets is
8409 the i387 extended floating-point format. In fact, of all targets
8410 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8411 on having a `long double' that's not `long' at all. */
8412 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8414 /* Although the i387 extended floating-point has only 80 significant
8415 bits, a `long double' actually takes up 96, probably to enforce
8417 set_gdbarch_long_double_bit (gdbarch, 96);
8419 /* Support for floating-point data type variants. */
8420 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
8422 /* Register numbers of various important registers. */
8423 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8424 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8425 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8426 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8428 /* NOTE: kettenis/20040418: GCC does have two possible register
8429 numbering schemes on the i386: dbx and SVR4. These schemes
8430 differ in how they number %ebp, %esp, %eflags, and the
8431 floating-point registers, and are implemented by the arrays
8432 dbx_register_map[] and svr4_dbx_register_map in
8433 gcc/config/i386.c. GCC also defines a third numbering scheme in
8434 gcc/config/i386.c, which it designates as the "default" register
8435 map used in 64bit mode. This last register numbering scheme is
8436 implemented in dbx64_register_map, and is used for AMD64; see
8439 Currently, each GCC i386 target always uses the same register
8440 numbering scheme across all its supported debugging formats
8441 i.e. SDB (COFF), stabs and DWARF 2. This is because
8442 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8443 DBX_REGISTER_NUMBER macro which is defined by each target's
8444 respective config header in a manner independent of the requested
8445 output debugging format.
8447 This does not match the arrangement below, which presumes that
8448 the SDB and stabs numbering schemes differ from the DWARF and
8449 DWARF 2 ones. The reason for this arrangement is that it is
8450 likely to get the numbering scheme for the target's
8451 default/native debug format right. For targets where GCC is the
8452 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8453 targets where the native toolchain uses a different numbering
8454 scheme for a particular debug format (stabs-in-ELF on Solaris)
8455 the defaults below will have to be overridden, like
8456 i386_elf_init_abi() does. */
8458 /* Use the dbx register numbering scheme for stabs and COFF. */
8459 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8460 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8462 /* Use the SVR4 register numbering scheme for DWARF 2. */
8463 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8465 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8466 be in use on any of the supported i386 targets. */
8468 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8470 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8472 /* Call dummy code. */
8473 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8474 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8475 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8476 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8478 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8479 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8480 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8482 set_gdbarch_return_value (gdbarch, i386_return_value);
8484 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8486 /* Stack grows downward. */
8487 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8489 set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc);
8490 set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind);
8492 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8493 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8495 set_gdbarch_frame_args_skip (gdbarch, 8);
8497 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8499 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8501 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8503 /* Add the i386 register groups. */
8504 i386_add_reggroups (gdbarch);
8505 tdep->register_reggroup_p = i386_register_reggroup_p;
8507 /* Helper for function argument information. */
8508 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8510 /* Hook the function epilogue frame unwinder. This unwinder is
8511 appended to the list first, so that it supercedes the DWARF
8512 unwinder in function epilogues (where the DWARF unwinder
8513 currently fails). */
8514 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8516 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8517 to the list before the prologue-based unwinders, so that DWARF
8518 CFI info will be used if it is available. */
8519 dwarf2_append_unwinders (gdbarch);
8521 frame_base_set_default (gdbarch, &i386_frame_base);
8523 /* Pseudo registers may be changed by amd64_init_abi. */
8524 set_gdbarch_pseudo_register_read_value (gdbarch,
8525 i386_pseudo_register_read_value);
8526 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8527 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8528 i386_ax_pseudo_register_collect);
8530 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8531 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8533 /* Override the normal target description method to make the AVX
8534 upper halves anonymous. */
8535 set_gdbarch_register_name (gdbarch, i386_register_name);
8537 /* Even though the default ABI only includes general-purpose registers,
8538 floating-point registers and the SSE registers, we have to leave a
8539 gap for the upper AVX, MPX and AVX512 registers. */
8540 set_gdbarch_num_regs (gdbarch, I386_PKEYS_NUM_REGS);
8542 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8544 /* Get the x86 target description from INFO. */
8545 tdesc = info.target_desc;
8546 if (! tdesc_has_registers (tdesc))
8547 tdesc = i386_target_description (X86_XSTATE_SSE_MASK);
8548 tdep->tdesc = tdesc;
8550 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8551 tdep->register_names = i386_register_names;
8553 /* No upper YMM registers. */
8554 tdep->ymmh_register_names = NULL;
8555 tdep->ymm0h_regnum = -1;
8557 /* No upper ZMM registers. */
8558 tdep->zmmh_register_names = NULL;
8559 tdep->zmm0h_regnum = -1;
8561 /* No high XMM registers. */
8562 tdep->xmm_avx512_register_names = NULL;
8563 tdep->xmm16_regnum = -1;
8565 /* No upper YMM16-31 registers. */
8566 tdep->ymm16h_register_names = NULL;
8567 tdep->ymm16h_regnum = -1;
8569 tdep->num_byte_regs = 8;
8570 tdep->num_word_regs = 8;
8571 tdep->num_dword_regs = 0;
8572 tdep->num_mmx_regs = 8;
8573 tdep->num_ymm_regs = 0;
8575 /* No MPX registers. */
8576 tdep->bnd0r_regnum = -1;
8577 tdep->bndcfgu_regnum = -1;
8579 /* No AVX512 registers. */
8580 tdep->k0_regnum = -1;
8581 tdep->num_zmm_regs = 0;
8582 tdep->num_ymm_avx512_regs = 0;
8583 tdep->num_xmm_avx512_regs = 0;
8585 /* No PKEYS registers */
8586 tdep->pkru_regnum = -1;
8587 tdep->num_pkeys_regs = 0;
8589 tdesc_data = tdesc_data_alloc ();
8591 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8593 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8595 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8596 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8597 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8599 /* Hook in ABI-specific overrides, if they have been registered.
8600 Note: If INFO specifies a 64 bit arch, this is where we turn
8601 a 32-bit i386 into a 64-bit amd64. */
8602 info.tdesc_data = tdesc_data;
8603 gdbarch_init_osabi (info, gdbarch);
8605 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8607 tdesc_data_cleanup (tdesc_data);
8609 gdbarch_free (gdbarch);
8613 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8615 /* Wire in pseudo registers. Number of pseudo registers may be
8617 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8618 + tdep->num_word_regs
8619 + tdep->num_dword_regs
8620 + tdep->num_mmx_regs
8621 + tdep->num_ymm_regs
8623 + tdep->num_ymm_avx512_regs
8624 + tdep->num_zmm_regs));
8626 /* Target description may be changed. */
8627 tdesc = tdep->tdesc;
8629 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8631 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8632 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8634 /* Make %al the first pseudo-register. */
8635 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8636 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8638 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8639 if (tdep->num_dword_regs)
8641 /* Support dword pseudo-register if it hasn't been disabled. */
8642 tdep->eax_regnum = ymm0_regnum;
8643 ymm0_regnum += tdep->num_dword_regs;
8646 tdep->eax_regnum = -1;
8648 mm0_regnum = ymm0_regnum;
8649 if (tdep->num_ymm_regs)
8651 /* Support YMM pseudo-register if it is available. */
8652 tdep->ymm0_regnum = ymm0_regnum;
8653 mm0_regnum += tdep->num_ymm_regs;
8656 tdep->ymm0_regnum = -1;
8658 if (tdep->num_ymm_avx512_regs)
8660 /* Support YMM16-31 pseudo registers if available. */
8661 tdep->ymm16_regnum = mm0_regnum;
8662 mm0_regnum += tdep->num_ymm_avx512_regs;
8665 tdep->ymm16_regnum = -1;
8667 if (tdep->num_zmm_regs)
8669 /* Support ZMM pseudo-register if it is available. */
8670 tdep->zmm0_regnum = mm0_regnum;
8671 mm0_regnum += tdep->num_zmm_regs;
8674 tdep->zmm0_regnum = -1;
8676 bnd0_regnum = mm0_regnum;
8677 if (tdep->num_mmx_regs != 0)
8679 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8680 tdep->mm0_regnum = mm0_regnum;
8681 bnd0_regnum += tdep->num_mmx_regs;
8684 tdep->mm0_regnum = -1;
8686 if (tdep->bnd0r_regnum > 0)
8687 tdep->bnd0_regnum = bnd0_regnum;
8689 tdep-> bnd0_regnum = -1;
8691 /* Hook in the legacy prologue-based unwinders last (fallback). */
8692 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8693 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8694 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8696 /* If we have a register mapping, enable the generic core file
8697 support, unless it has already been enabled. */
8698 if (tdep->gregset_reg_offset
8699 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8700 set_gdbarch_iterate_over_regset_sections
8701 (gdbarch, i386_iterate_over_regset_sections);
8703 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8704 i386_fast_tracepoint_valid_at);
8711 /* Return the target description for a specified XSAVE feature mask. */
8713 const struct target_desc *
8714 i386_target_description (uint64_t xcr0)
8716 static target_desc *i386_tdescs \
8717 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
8718 target_desc **tdesc;
8720 tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0]
8721 [(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
8722 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
8723 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
8724 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0];
8727 *tdesc = i386_create_target_description (xcr0, false);
8732 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8734 /* Find the bound directory base address. */
8736 static unsigned long
8737 i386_mpx_bd_base (void)
8739 struct regcache *rcache;
8740 struct gdbarch_tdep *tdep;
8742 enum register_status regstatus;
8744 rcache = get_current_regcache ();
8745 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8747 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8749 if (regstatus != REG_VALID)
8750 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8752 return ret & MPX_BASE_MASK;
8756 i386_mpx_enabled (void)
8758 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8759 const struct target_desc *tdesc = tdep->tdesc;
8761 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8764 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8765 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8766 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8767 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8769 /* Find the bound table entry given the pointer location and the base
8770 address of the table. */
8773 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8777 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8778 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8779 CORE_ADDR bd_entry_addr;
8782 struct gdbarch *gdbarch = get_current_arch ();
8783 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8786 if (gdbarch_ptr_bit (gdbarch) == 64)
8788 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8789 bd_ptr_r_shift = 20;
8791 bt_select_r_shift = 3;
8792 bt_select_l_shift = 5;
8793 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8795 if ( sizeof (CORE_ADDR) == 4)
8796 error (_("bound table examination not supported\
8797 for 64-bit process with 32-bit GDB"));
8801 mpx_bd_mask = MPX_BD_MASK_32;
8802 bd_ptr_r_shift = 12;
8804 bt_select_r_shift = 2;
8805 bt_select_l_shift = 4;
8806 bt_mask = MPX_BT_MASK_32;
8809 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8810 bd_entry_addr = bd_base + offset1;
8811 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8813 if ((bd_entry & 0x1) == 0)
8814 error (_("Invalid bounds directory entry at %s."),
8815 paddress (get_current_arch (), bd_entry_addr));
8817 /* Clearing status bit. */
8819 bt_addr = bd_entry & ~bt_select_r_shift;
8820 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8822 return bt_addr + offset2;
8825 /* Print routine for the mpx bounds. */
8828 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8830 struct ui_out *uiout = current_uiout;
8832 struct gdbarch *gdbarch = get_current_arch ();
8833 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8834 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8836 if (bounds_in_map == 1)
8838 uiout->text ("Null bounds on map:");
8839 uiout->text (" pointer value = ");
8840 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8846 uiout->text ("{lbound = ");
8847 uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]);
8848 uiout->text (", ubound = ");
8850 /* The upper bound is stored in 1's complement. */
8851 uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]);
8852 uiout->text ("}: pointer value = ");
8853 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8855 if (gdbarch_ptr_bit (gdbarch) == 64)
8856 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8858 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8860 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8861 -1 represents in this sense full memory access, and there is no need
8864 size = (size > -1 ? size + 1 : size);
8865 uiout->text (", size = ");
8866 uiout->field_fmt ("size", "%s", plongest (size));
8868 uiout->text (", metadata = ");
8869 uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]);
8874 /* Implement the command "show mpx bound". */
8877 i386_mpx_info_bounds (const char *args, int from_tty)
8879 CORE_ADDR bd_base = 0;
8881 CORE_ADDR bt_entry_addr = 0;
8882 CORE_ADDR bt_entry[4];
8884 struct gdbarch *gdbarch = get_current_arch ();
8885 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8887 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8888 || !i386_mpx_enabled ())
8890 printf_unfiltered (_("Intel Memory Protection Extensions not "
8891 "supported on this target.\n"));
8897 printf_unfiltered (_("Address of pointer variable expected.\n"));
8901 addr = parse_and_eval_address (args);
8903 bd_base = i386_mpx_bd_base ();
8904 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8906 memset (bt_entry, 0, sizeof (bt_entry));
8908 for (i = 0; i < 4; i++)
8909 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8910 + i * TYPE_LENGTH (data_ptr_type),
8913 i386_mpx_print_bounds (bt_entry);
8916 /* Implement the command "set mpx bound". */
8919 i386_mpx_set_bounds (const char *args, int from_tty)
8921 CORE_ADDR bd_base = 0;
8922 CORE_ADDR addr, lower, upper;
8923 CORE_ADDR bt_entry_addr = 0;
8924 CORE_ADDR bt_entry[2];
8925 const char *input = args;
8927 struct gdbarch *gdbarch = get_current_arch ();
8928 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8929 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8931 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8932 || !i386_mpx_enabled ())
8933 error (_("Intel Memory Protection Extensions not supported\
8937 error (_("Pointer value expected."));
8939 addr = value_as_address (parse_to_comma_and_eval (&input));
8941 if (input[0] == ',')
8943 if (input[0] == '\0')
8944 error (_("wrong number of arguments: missing lower and upper bound."));
8945 lower = value_as_address (parse_to_comma_and_eval (&input));
8947 if (input[0] == ',')
8949 if (input[0] == '\0')
8950 error (_("Wrong number of arguments; Missing upper bound."));
8951 upper = value_as_address (parse_to_comma_and_eval (&input));
8953 bd_base = i386_mpx_bd_base ();
8954 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8955 for (i = 0; i < 2; i++)
8956 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8957 + i * TYPE_LENGTH (data_ptr_type),
8959 bt_entry[0] = (uint64_t) lower;
8960 bt_entry[1] = ~(uint64_t) upper;
8962 for (i = 0; i < 2; i++)
8963 write_memory_unsigned_integer (bt_entry_addr
8964 + i * TYPE_LENGTH (data_ptr_type),
8965 TYPE_LENGTH (data_ptr_type), byte_order,
8969 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
8971 /* Helper function for the CLI commands. */
8974 set_mpx_cmd (char *args, int from_tty)
8976 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
8979 /* Helper function for the CLI commands. */
8982 show_mpx_cmd (char *args, int from_tty)
8984 cmd_show_list (mpx_show_cmdlist, from_tty, "");
8988 _initialize_i386_tdep (void)
8990 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8992 /* Add the variable that controls the disassembly flavor. */
8993 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8994 &disassembly_flavor, _("\
8995 Set the disassembly flavor."), _("\
8996 Show the disassembly flavor."), _("\
8997 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8999 NULL, /* FIXME: i18n: */
9000 &setlist, &showlist);
9002 /* Add the variable that controls the convention for returning
9004 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
9005 &struct_convention, _("\
9006 Set the convention for returning small structs."), _("\
9007 Show the convention for returning small structs."), _("\
9008 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9011 NULL, /* FIXME: i18n: */
9012 &setlist, &showlist);
9014 /* Add "mpx" prefix for the set commands. */
9016 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
9017 Set Intel Memory Protection Extensions specific variables."),
9018 &mpx_set_cmdlist, "set mpx ",
9019 0 /* allow-unknown */, &setlist);
9021 /* Add "mpx" prefix for the show commands. */
9023 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
9024 Show Intel Memory Protection Extensions specific variables."),
9025 &mpx_show_cmdlist, "show mpx ",
9026 0 /* allow-unknown */, &showlist);
9028 /* Add "bound" command for the show mpx commands list. */
9030 add_cmd ("bound", no_class, i386_mpx_info_bounds,
9031 "Show the memory bounds for a given array/pointer storage\
9032 in the bound table.",
9035 /* Add "bound" command for the set mpx commands list. */
9037 add_cmd ("bound", no_class, i386_mpx_set_bounds,
9038 "Set the memory bounds for a given array/pointer storage\
9039 in the bound table.",
9042 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9043 i386_svr4_init_abi);
9045 /* Initialize the i386-specific register groups. */
9046 i386_init_reggroups ();
9048 /* Tell remote stub that we support XML target description. */
9049 register_remote_support_xml ("i386");
9057 { "i386/i386.xml", X86_XSTATE_SSE_MASK },
9058 { "i386/i386-mmx.xml", X86_XSTATE_X87_MASK },
9059 { "i386/i386-avx.xml", X86_XSTATE_AVX_MASK },
9060 { "i386/i386-mpx.xml", X86_XSTATE_MPX_MASK },
9061 { "i386/i386-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
9062 { "i386/i386-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
9063 { "i386/i386-avx-mpx-avx512-pku.xml",
9064 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
9067 for (auto &a : xml_masks)
9069 auto tdesc = i386_target_description (a.mask);
9071 selftests::record_xml_tdesc (a.xml, tdesc);
9073 #endif /* GDB_SELF_TEST */